diff --git a/.properties b/.properties index 9659678218..d7e208a462 100644 --- a/.properties +++ b/.properties @@ -1,6 +1,6 @@ id=com.silabs.sdk.stack.super -version=4.4.1 +version=4.4.2 label=Gecko SDK Suite description=Gecko SDK Suite diff --git a/README.md b/README.md index c6d6d79f2f..c84f56f436 100644 --- a/README.md +++ b/README.md @@ -9,10 +9,6 @@ The Gecko SDK (GSDK) combines Silicon Labs wireless software development kits (S Silicon Labs also helps future-proof your devices with over-the-air software and security updates, helping to minimize maintenance cost and improve your end user product experience! -## Announcements - -On December 13th, 2023, the git LFS server changed and enabled a bandwidth quota based on your IP address. Go [here](https://github.com/SiliconLabs/.github) for more information on how to resolve this issue. - ## Licensing Gecko SDK is covered by one of several different licenses. diff --git a/app/bluetooth/bluetooth_experimental_demos.xml b/app/bluetooth/bluetooth_experimental_demos.xml index f8564645fe..00ef9f01c7 100644 --- a/app/bluetooth/bluetooth_experimental_demos.xml +++ b/app/bluetooth/bluetooth_experimental_demos.xml @@ -6,11 +6,11 @@ - + - + ABR Network Co-Processor (NCP) target application. Runs the Bluetooth stack and provides access to it by exposing the Bluetooth API (BGAPI) via UART connection. NCP mode makes it possible to run your application on a host controller or PC. This example does not have a GATT database, but makes it possible to build one from the application using Dynamic GATT API. @@ -18,11 +18,11 @@ - + - + ABR Network Co-Processor (NCP) target application. Runs the Bluetooth stack and provides access to it by exposing the Bluetooth API (BGAPI) via UART connection. NCP mode makes it possible to run your application on a host controller or PC. This example does not have a GATT database, but makes it possible to build one from the application using Dynamic GATT API. @@ -30,11 +30,11 @@ - + - + ABR Network Co-Processor (NCP) target application. Runs the Bluetooth stack and provides access to it by exposing the Bluetooth API (BGAPI) via UART connection. NCP mode makes it possible to run your application on a host controller or PC. This example does not have a GATT database, but makes it possible to build one from the application using Dynamic GATT API. @@ -42,11 +42,11 @@ - + - + ABR initiator for Bluetooth. The example connects to an ABR reflector and starts distance measurement. Results are printed on the display of the WSTK. @@ -54,11 +54,11 @@ - + - + ABR initiator for Bluetooth. The example connects to an ABR reflector and starts distance measurement. Results are printed on the display of the WSTK. @@ -66,11 +66,11 @@ - + - + ABR initiator for Bluetooth. The example connects to an ABR reflector and starts distance measurement. Results are printed on the display of the WSTK. @@ -78,11 +78,11 @@ - + - + ABR reflector for Bluetooth. The example sends measurement results to the initiator via GATT. The application starts advertising after boot and restarts advertising after a connection is closed. It also supports Over-the-Air Device Firmware Upgrade (OTA DFU). @@ -90,11 +90,11 @@ - + - + ABR reflector for Bluetooth. The example sends measurement results to the initiator via GATT. The application starts advertising after boot and restarts advertising after a connection is closed. It also supports Over-the-Air Device Firmware Upgrade (OTA DFU). @@ -102,11 +102,11 @@ - + - + ABR reflector for Bluetooth. The example sends measurement results to the initiator via GATT. The application starts advertising after boot and restarts advertising after a connection is closed. It also supports Over-the-Air Device Firmware Upgrade (OTA DFU). @@ -114,10 +114,10 @@ - + - + diff --git a/app/bluetooth/bluetooth_internal_demos.xml b/app/bluetooth/bluetooth_internal_demos.xml index 7012c49a4f..36a30746d7 100644 --- a/app/bluetooth/bluetooth_internal_demos.xml +++ b/app/bluetooth/bluetooth_internal_demos.xml @@ -6,11 +6,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -18,11 +18,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -30,11 +30,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -42,11 +42,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -54,11 +54,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -66,11 +66,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -78,11 +78,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -90,11 +90,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -102,11 +102,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -114,11 +114,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -126,11 +126,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -138,11 +138,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -150,11 +150,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -162,11 +162,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -174,11 +174,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -186,11 +186,11 @@ - + - + This example is an evaluation showcase for a Bluetooth Electronic Shelf Label (ESL) Tag application with the ESL Tag Demo component. The example includes image and display capabilities of an ESL Tag, utilizing the memory LCD display on the WSTK board while images are stored in RAM, only. Instead of the Silicon Labs logo, the Demo example will ask the user to run the QRCode generator on startup using the WSTK's display. After configuration the display will show ESL related information. @@ -198,10 +198,10 @@ - + - + diff --git a/app/bluetooth/bluetooth_production_demos.xml b/app/bluetooth/bluetooth_production_demos.xml index b8994035c8..2ea95bf6df 100644 --- a/app/bluetooth/bluetooth_production_demos.xml +++ b/app/bluetooth/bluetooth_production_demos.xml @@ -6,11 +6,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -18,11 +18,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -30,11 +30,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -42,11 +42,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -54,11 +54,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -66,11 +66,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -78,11 +78,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -90,11 +90,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -102,11 +102,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -114,11 +114,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -126,11 +126,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -138,11 +138,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -150,11 +150,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -162,11 +162,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -174,11 +174,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -186,11 +186,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -198,11 +198,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -210,11 +210,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -222,11 +222,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -234,11 +234,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -246,11 +246,11 @@ - + - + Network Co-Processor (NCP) target application with additional features to support the Electronic Shelf Label Profile ESL Access Point role. Note: Some BLE features unused by the ESL Access Point are removed compared to the NCP target application. @@ -258,11 +258,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -270,11 +270,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -282,11 +282,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -294,11 +294,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -306,11 +306,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -318,11 +318,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -330,11 +330,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -342,11 +342,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -354,11 +354,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -366,11 +366,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -378,11 +378,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -390,11 +390,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -402,11 +402,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -414,11 +414,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -426,11 +426,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -438,11 +438,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -450,11 +450,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -462,11 +462,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -474,11 +474,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -486,11 +486,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -498,11 +498,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -510,11 +510,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -522,11 +522,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -534,11 +534,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -546,11 +546,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -558,11 +558,11 @@ - + - + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. @@ -570,11 +570,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -582,11 +582,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -594,11 +594,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -606,11 +606,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -618,11 +618,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -630,11 +630,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -642,11 +642,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -654,11 +654,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -666,11 +666,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -678,11 +678,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -690,11 +690,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -702,11 +702,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -714,11 +714,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -726,11 +726,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -738,11 +738,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -750,11 +750,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -762,11 +762,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -774,11 +774,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -786,11 +786,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -798,11 +798,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -810,11 +810,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -822,11 +822,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -834,11 +834,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -846,11 +846,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -858,11 +858,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -870,11 +870,11 @@ - + - + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. @@ -882,11 +882,11 @@ - + - + Demonstrates the features of the EFR32xG24 Dev Kit Board. This can be tested with the EFR Connect mobile app. @@ -894,11 +894,11 @@ - + - + Demonstrates the features of the EFR32xG27 DevKit board. Features can be evaluated with the EFR Connect mobile app. @@ -906,11 +906,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -918,11 +918,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -930,11 +930,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -942,11 +942,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -954,11 +954,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -966,11 +966,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -978,11 +978,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -990,11 +990,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1002,11 +1002,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1014,11 +1014,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1026,11 +1026,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1038,11 +1038,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1050,11 +1050,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. @@ -1062,11 +1062,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1074,11 +1074,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1086,11 +1086,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1098,11 +1098,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1110,11 +1110,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1122,11 +1122,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1134,11 +1134,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1146,11 +1146,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1158,11 +1158,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1170,11 +1170,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1182,11 +1182,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1194,11 +1194,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1206,11 +1206,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1218,11 +1218,11 @@ - + - + Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. @@ -1230,11 +1230,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1242,11 +1242,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1254,11 +1254,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1266,11 +1266,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1278,11 +1278,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1290,11 +1290,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1302,11 +1302,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1314,11 +1314,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1326,11 +1326,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1338,11 +1338,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1350,11 +1350,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1362,11 +1362,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1374,11 +1374,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1386,11 +1386,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1398,11 +1398,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1410,11 +1410,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1422,11 +1422,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1434,11 +1434,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1446,11 +1446,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1458,11 +1458,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1470,11 +1470,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1482,11 +1482,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1494,11 +1494,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1506,11 +1506,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1518,11 +1518,11 @@ - + - + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. @@ -1530,11 +1530,11 @@ - + - + Demonstrates the features of the Thunderboard EFR32BG22 Kit. This can be tested with the EFR Connect mobile app. @@ -1542,11 +1542,11 @@ - + - + Demonstrates the features of the Thunderboard EFR32BG22 Kit. This can be tested with the EFR Connect mobile app. @@ -1554,11 +1554,11 @@ - + - + Demonstrates the features of the Thunderboard Sense 2 Kit. This can be tested with the EFR Connect mobile app. @@ -1566,11 +1566,11 @@ - + - + Voice over Bluetooth Low Energy sample application. It is supported by Thunderboard Sense 2 and Thunderboard EFR32BG22 boards and demonstrates how to send voice data over GATT, which is acquired from the on-board microphones. @@ -1578,11 +1578,11 @@ - + - + Voice over Bluetooth Low Energy sample application. It is supported by Thunderboard Sense 2 and Thunderboard EFR32BG22 boards and demonstrates how to send voice data over GATT, which is acquired from the on-board microphones. @@ -1590,11 +1590,11 @@ - + - + Voice over Bluetooth Low Energy sample application. It is supported by Thunderboard Sense 2 and Thunderboard EFR32BG22 boards and demonstrates how to send voice data over GATT, which is acquired from the on-board microphones. @@ -1602,11 +1602,11 @@ - + - + Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. @@ -1614,7 +1614,7 @@ - + @@ -1625,7 +1625,7 @@ - + @@ -1636,7 +1636,7 @@ - + @@ -1647,7 +1647,7 @@ - + @@ -1658,7 +1658,7 @@ - + @@ -1669,7 +1669,7 @@ - + @@ -1680,7 +1680,7 @@ - + @@ -1691,7 +1691,7 @@ - + @@ -1702,7 +1702,7 @@ - + @@ -1713,7 +1713,7 @@ - + @@ -1724,7 +1724,7 @@ - + @@ -1735,7 +1735,7 @@ - + @@ -1746,7 +1746,7 @@ - + @@ -1757,7 +1757,7 @@ - + @@ -1768,7 +1768,7 @@ - + @@ -1779,7 +1779,7 @@ - + @@ -1790,7 +1790,7 @@ - + @@ -1801,7 +1801,7 @@ - + @@ -1812,7 +1812,7 @@ - + @@ -1823,7 +1823,7 @@ - + @@ -1834,7 +1834,7 @@ - + @@ -1845,7 +1845,7 @@ - + @@ -1856,7 +1856,7 @@ - + @@ -1867,7 +1867,7 @@ - + @@ -1878,7 +1878,7 @@ - + @@ -1889,7 +1889,7 @@ - + @@ -1900,7 +1900,7 @@ - + @@ -1911,7 +1911,7 @@ - + @@ -1922,7 +1922,7 @@ - + @@ -1933,7 +1933,7 @@ - + @@ -1944,7 +1944,7 @@ - + @@ -1955,7 +1955,7 @@ - + @@ -1966,7 +1966,7 @@ - + @@ -1977,11 +1977,11 @@ - + - + Network Co-Processor (NCP) target application extended with CTE Receiver support. It enables Angle of Arrival (AoA) calculation. Use this application with Direction Finding host examples. @@ -1989,11 +1989,11 @@ - + - + This sample app demonstrates a CTE (Constant Tone Extension) transmitter that can be used as an asset tag in a Direction Finding setup estimating Angle of Arrival (AoA). @@ -2001,11 +2001,11 @@ - + - + This sample app demonstrates a CTE (Constant Tone Extension) transmitter that can be used as an asset tag in a Direction Finding setup estimating Angle of Arrival (AoA). @@ -2013,11 +2013,11 @@ - + - + This sample app demonstrates a CTE (Constant Tone Extension) transmitter that can be used as an asset tag in a Direction Finding setup estimating Angle of Arrival (AoA). @@ -2025,11 +2025,11 @@ - + - + Network Co-Processor (NCP) target application extended with CTE Receiver support. It enables Angle of Departure (AoD) calculation. Use this application with Direction Finding Studio tools. @@ -2037,11 +2037,11 @@ - + - + Network Co-Processor (NCP) target application extended with CTE Receiver support. It enables Angle of Departure (AoD) calculation. Use this application with Direction Finding Studio tools. @@ -2049,11 +2049,11 @@ - + - + Network Co-Processor (NCP) target application extended with CTE Receiver support. It enables Angle of Departure (AoD) calculation. Use this application with Direction Finding Studio tools. @@ -2061,11 +2061,11 @@ - + - + This sample app demonstrates a CTE (Constant Tone Extension) transmitter that can be used as a locator beacon in a Direction Finding setup estimating Angle of Departure (AoD). @@ -2073,11 +2073,11 @@ - + - + This sample app demonstrates a CTE (Constant Tone Extension) transmitter that can be used as a locator beacon in a Direction Finding setup estimating Angle of Departure (AoD). @@ -2085,11 +2085,11 @@ - + - + This is a Dynamic Multiprotocol reference application demonstrating a light bulb that can be switched both via Bluetooth and via a Proprietary protocol. Can be tested with the EFR Connect mobile app and Flex (RAIL) Switch sample app. @@ -2097,10 +2097,10 @@ - + - + diff --git a/app/bluetooth/common/abr_cs_parser/abr_file_log.c b/app/bluetooth/common/abr_cs_parser/abr_file_log.c index 33c46a2a0a..385cb27f5a 100644 --- a/app/bluetooth/common/abr_cs_parser/abr_file_log.c +++ b/app/bluetooth/common/abr_cs_parser/abr_file_log.c @@ -954,6 +954,8 @@ sl_status_t abr_file_log_store_step(abr_role_t role, cs_step_t *step_data) return sc; } +// ----------------------------------------------------------------------------- +// Private function definitions static void replace_char(char *str, char target_char, char new_char) { for (int i = 0; str[i] != '\0'; i++) { diff --git a/app/bluetooth/common/abr_initiator/abr_initiator.c b/app/bluetooth/common/abr_initiator/abr_initiator.c index 8f37cb68c2..4b546cdcbe 100644 --- a/app/bluetooth/common/abr_initiator/abr_initiator.c +++ b/app/bluetooth/common/abr_initiator/abr_initiator.c @@ -426,6 +426,9 @@ void abr_initiator_deinit(void) sl_status_t sc; if (connection_handle != SL_BT_INVALID_CONNECTION_HANDLE) { + app_log_info("Shutting down CS parser" APP_LOG_NL); + sc = abr_cs_parser_deinit(); + app_assert_status(sc); app_log_info("Closing connection" APP_LOG_NL); sc = sl_bt_connection_close(connection_handle); app_assert_status(sc); diff --git a/app/bluetooth/common/cbap_lib/lib/cbap_CM33_gcc.a b/app/bluetooth/common/cbap_lib/lib/cbap_CM33_gcc.a index a363a2924b..501810c2fa 100644 --- a/app/bluetooth/common/cbap_lib/lib/cbap_CM33_gcc.a +++ b/app/bluetooth/common/cbap_lib/lib/cbap_CM33_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bdec4fc9fa229b8d3f4d8914b8fe10b44509dda30dfd8269f34c609ddb2dce76 +oid sha256:24315681109032cf71671416cd53eefd73a05b710a567935b703f3b72cac5047 size 5326 diff --git a/app/bluetooth/common/cbap_lib/lib/cbap_CM33_iar.a b/app/bluetooth/common/cbap_lib/lib/cbap_CM33_iar.a index 7a51539a98..a0397d8ba6 100644 --- a/app/bluetooth/common/cbap_lib/lib/cbap_CM33_iar.a +++ b/app/bluetooth/common/cbap_lib/lib/cbap_CM33_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:91007e2571715dc8739d5a3228bada4882be2c7d99d1e534169d4c48049f54f8 +oid sha256:43c12b1b2061cfadb814162b284ce1f01a1e55fa09486a8b9f9a6c5704d89314 size 10582 diff --git a/app/bluetooth/common/esl_tag_core/inc/esl_tag_core.h b/app/bluetooth/common/esl_tag_core/inc/esl_tag_core.h index 494b5e1a4a..b89c5501c7 100644 --- a/app/bluetooth/common/esl_tag_core/inc/esl_tag_core.h +++ b/app/bluetooth/common/esl_tag_core/inc/esl_tag_core.h @@ -179,10 +179,21 @@ uint8_t esl_core_get_basic_state_bit(uint8_t bit); *****************************************************************************/ esl_basic_state_t esl_core_set_basic_state_bit(uint8_t bit, uint8_t value); +/**************************************************************************//** + * Get randomizer value for ESL response packet encryption. + * Returns SL_STATUS_NOT_READY until the randomizer is initialized. + * Returns SL_STATUS_OK on success after which the data will be available in + * the randomizer array passed as input parameter. + * + * @param[out] randomizer sl_bt_ead_randomizer_t array type to the storage + * @return sl_status_t + *****************************************************************************/ +sl_status_t esl_core_get_randomizer(sl_bt_ead_randomizer_t randomizer); + /**************************************************************************//** * Read the value from the AP Key characteristics of ESL service. * Returns SL_STATUS_NOT_READY until AP Key is written by the bonded AP. - * My return other failing status as well, depending on stack response, or + * May return other failing status as well, depending on stack response, or * SL_STATUS_OK on success. In the latter case, the data will be available in * *(uint8_t*)ap_key in a format of little endian (packed) byte stream. Size of * the stream is defined in ESL standard. diff --git a/app/bluetooth/common/esl_tag_core/src/esl_tag_core.c b/app/bluetooth/common/esl_tag_core/src/esl_tag_core.c index 9b68dfcbd5..dce823a0de 100644 --- a/app/bluetooth/common/esl_tag_core/src/esl_tag_core.c +++ b/app/bluetooth/common/esl_tag_core/src/esl_tag_core.c @@ -86,6 +86,7 @@ #define ESL_CONFIG_FLAG_ESL_RESPONSE_KEY (0x04u) #define ESL_CONFIG_FLAG_ESL_ABS_TIME (0x08u) #define ESL_CONFIG_FLAG_UPDATE_COMPLETE (0x10u) +#define ESL_CONFIG_FLAG_RANDOMIZER_READY (0x20u) #define ESL_CONFIG_FLAGS_MANDATORY_MASK (ESL_CONFIG_FLAG_ESL_ADDRESS \ | ESL_CONFIG_FLAG_ESL_AP_KEY \ | ESL_CONFIG_FLAG_ESL_RESPONSE_KEY \ @@ -158,6 +159,16 @@ typedef struct { uint8_t advertising_set_handle; } esl_persistent_struct_t; +typedef union { + // Note: this will only work as expected on little endian machines! + sl_bt_ead_randomizer_t randomizer; + // Use exact naming from Core spec. v5.4, Vol 6, Part E, Section 2 (CCM) + uint64_t packetCounter; +} response_randomizer_t; + +// EAD Randomizer for ESL Responses encryption +static response_randomizer_t esl_core_response_randomizer = { 0 }; + // Custom data for advertising, in accordance with ESLS v1.0r01, section 2.7.3.1 static const uint8_t esl_core_advertising_data[] = { 0x02, 0x01, 0x06, // Flags @@ -200,6 +211,16 @@ static esl_persistent_struct_t esl_tag_persistent = { .advertising_set_handle = SL_BT_INVALID_ADVERTISING_SET_HANDLE }; +// ESL Tag asynchronous randomizer callback +static void esl_core_async_randomizer(void *p_event_data, uint16_t event_size) +{ + (void)event_size; + + // Remove ready flag so a new randomizer value will be generated by CSPRNG + esl_tag.config_status &= (uint8_t) (~ESL_CONFIG_FLAG_RANDOMIZER_READY); + (void)esl_core_get_randomizer(p_event_data); +} + // ESL Tag PAwR sync handle getter uint16_t esl_core_get_sync_handle(void) { @@ -432,6 +453,9 @@ static void esl_state_boot_handler(sl_bt_msg_t *evt) ESL_LOG_LEVEL_DEBUG, "Started with random seed: %lu.", seed); + // set an arbitrary, initial random value for the ESL EAD Randomizer + esl_core_response_randomizer.packetCounter = 0xfa7eful * seed; + esl_tag.config_status |= ESL_CONFIG_FLAG_RANDOMIZER_READY; // init stdlib's rand() generator by our TRNG seed srand(seed); // Set custom data for advertising, according to ESLS v0.9d095r08, section 2.7.3.1 @@ -736,6 +760,9 @@ static void esl_state_configuring_handler(sl_bt_msg_t *evt) ESL_LOG_LEVEL_INFO, "Write AP Response Key Material"); + // get new randomizer value whenever the Response Key Material is written + (void)app_scheduler_add(&esl_core_async_randomizer, 0, 0, NULL); + if (overall_size == SL_BT_EAD_KEY_MATERIAL_SIZE) { esl_tag.config_status |= execute_write_flag; break; @@ -1296,6 +1323,34 @@ esl_basic_state_t esl_core_set_basic_state_bit(uint8_t bit, uint8_t value) return esl_tag.basic_state; } +sl_status_t esl_core_get_randomizer(sl_bt_ead_randomizer_t randomizer) +{ + sl_status_t result = SL_STATUS_NOT_READY; + + if (!!(esl_tag.config_status & ESL_CONFIG_FLAG_RANDOMIZER_READY)) { + // Increase packet counter for every new packet + ++esl_core_response_randomizer.packetCounter; + result = SL_STATUS_OK; + } else { + struct sl_bt_ead_nonce_s nonce; + + result = sl_bt_ead_randomizer_update(&nonce); + + if (result == SL_STATUS_OK) { + memcpy((void *)esl_core_response_randomizer.randomizer, (void *)nonce.randomizer, + SL_BT_EAD_RANDOMIZER_SIZE); + esl_tag.config_status |= ESL_CONFIG_FLAG_RANDOMIZER_READY; + } + } + + if (result == SL_STATUS_OK && randomizer != NULL) { + memcpy((void *)randomizer, (void *)esl_core_response_randomizer.randomizer, + SL_BT_EAD_RANDOMIZER_SIZE); + } + + return result; +} + sl_status_t esl_core_read_ap_key(sl_bt_ead_key_material_p ap_key) { sl_status_t result = SL_STATUS_NOT_READY; diff --git a/app/bluetooth/common/esl_tag_core/src/esl_tag_crypto.c b/app/bluetooth/common/esl_tag_core/src/esl_tag_crypto.c index e201b58946..7de78b44ff 100644 --- a/app/bluetooth/common/esl_tag_core/src/esl_tag_crypto.c +++ b/app/bluetooth/common/esl_tag_core/src/esl_tag_crypto.c @@ -65,7 +65,13 @@ void* esl_core_encrypt_message(void *msg, uint8_t *len) status = esl_core_read_response_key(&key_material); if (status == SL_STATUS_OK) { - status = sl_bt_ead_session_init(&key_material, NULL, &nonce); + status = esl_core_get_randomizer(nonce.randomizer); + } + + if (status == SL_STATUS_OK) { + status = sl_bt_ead_session_init(&key_material, + nonce.randomizer, + &nonce); } if (status == SL_STATUS_OK) { diff --git a/app/bluetooth/common/esl_tag_core/src/esl_tag_opcodes.c b/app/bluetooth/common/esl_tag_core/src/esl_tag_opcodes.c index 141755e1ea..8a6b0a605f 100644 --- a/app/bluetooth/common/esl_tag_core/src/esl_tag_opcodes.c +++ b/app/bluetooth/common/esl_tag_core/src/esl_tag_opcodes.c @@ -3,7 +3,7 @@ * @brief ESL Tag opcode processor implementation ******************************************************************************* * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -29,6 +29,7 @@ ******************************************************************************/ #include #include +#include "sl_common.h" #include "esl_tag_log.h" #include "esl_tag_tlv.h" #include "esl_tag_core.h" diff --git a/app/bluetooth/common/gatt_service_aio/sl_gatt_service_aio.c b/app/bluetooth/common/gatt_service_aio/sl_gatt_service_aio.c index 62ed5f2a2b..77c5f301d3 100644 --- a/app/bluetooth/common/gatt_service_aio/sl_gatt_service_aio.c +++ b/app/bluetooth/common/gatt_service_aio/sl_gatt_service_aio.c @@ -3,7 +3,7 @@ * @brief Automation IO GATT service ******************************************************************************* * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -29,6 +29,7 @@ ******************************************************************************/ #include "stdbool.h" +#include "sl_common.h" #include "sl_status.h" #include "gatt_db.h" #include "app_assert.h" diff --git a/app/bluetooth/common/ots/src/sl_bt_ots_client.c b/app/bluetooth/common/ots/src/sl_bt_ots_client.c index 177e6ab518..b9926949f6 100644 --- a/app/bluetooth/common/ots/src/sl_bt_ots_client.c +++ b/app/bluetooth/common/ots/src/sl_bt_ots_client.c @@ -1187,11 +1187,11 @@ void sli_bt_ots_client_on_bt_event(sl_bt_msg_t *evt) // Set status handle->status = CLIENT_STATUS_DISCONNECTED; - // Do callback - CALL_SAFE(handle, on_disconnect, handle); - // Remove client from the list sl_slist_remove(&client_list, &handle->node); + + // The callback should be invoked last, as this might free up allocated memory behind the handle. + CALL_SAFE(handle, on_disconnect, handle); break; } } diff --git a/app/bluetooth/common/simple_com/sl_simple_com_cpc.c b/app/bluetooth/common/simple_com/sl_simple_com_cpc.c index 8dfd4e3715..e84570f470 100644 --- a/app/bluetooth/common/simple_com/sl_simple_com_cpc.c +++ b/app/bluetooth/common/simple_com/sl_simple_com_cpc.c @@ -3,7 +3,7 @@ * @brief Simple Communication Interface (CPC) ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -28,6 +28,7 @@ * ******************************************************************************/ +#include "sl_common.h" #include #include "sl_simple_com.h" #include "sl_simple_com_config.h" diff --git a/app/bluetooth/common/wake_lock/sl_wake_lock.c b/app/bluetooth/common/wake_lock/sl_wake_lock.c index 448884d5bb..096879d305 100644 --- a/app/bluetooth/common/wake_lock/sl_wake_lock.c +++ b/app/bluetooth/common/wake_lock/sl_wake_lock.c @@ -3,7 +3,7 @@ * @brief Wake and sleep functionality ******************************************************************************* * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -31,6 +31,7 @@ #define CURRENT_MODULE_NAME "APP_BLUETOOTH_EXAMPLE_WAKE_LOCK" #include "em_gpio.h" +#include "sl_common.h" #include "gpiointerrupt.h" #include "sl_wake_lock.h" #include "sl_power_manager.h" diff --git a/app/bluetooth/common_host/app_timer/app_timer_win.c b/app/bluetooth/common_host/app_timer/app_timer_win.c index 66b290f507..2295af1df5 100644 --- a/app/bluetooth/common_host/app_timer/app_timer_win.c +++ b/app/bluetooth/common_host/app_timer/app_timer_win.c @@ -117,7 +117,7 @@ __attribute__((stdcall)) static void app_timer_common_callback(HWND hwnd, tmp_timer_ptr = tmp_timer_ptr->next; } if (NULL == tmp_timer_ptr) { - app_log_error("Timer handle %d not found." APP_LOG_NL, timer_id); + app_log_error("Timer handle %p not found." APP_LOG_NL, (void*)timer_id); (void)KillTimer(NULL, timer_id); (void)GetLastError(); } else { diff --git a/app/bluetooth/common_host/esl_lib/esl_lib.h b/app/bluetooth/common_host/esl_lib/esl_lib.h index 5600f25c4e..94bc9a88e7 100644 --- a/app/bluetooth/common_host/esl_lib/esl_lib.h +++ b/app/bluetooth/common_host/esl_lib/esl_lib.h @@ -62,17 +62,17 @@ extern "C" { // Periodic advertisement interval for PAwR train. // Value in units of 1.25 ms. -#define ESL_LIB_PAWR_MIN_INTERVAL_DEFAULT 1233 +#define ESL_LIB_PAWR_MIN_INTERVAL_DEFAULT 1248 // Number of subevents, practically has to be equal to the supported number // of ESL groups. #define ESL_LIB_PAWR_MAX_INTERVAL_DEFAULT ESL_LIB_PAWR_MIN_INTERVAL_DEFAULT -// Scalable up to 7140 tags in 28 groups -#define ESL_LIB_PAWR_SUBEVENT_COUNT_DEFAULT 28 +// Scalable up to 6630 tags in 26 groups +#define ESL_LIB_PAWR_SUBEVENT_COUNT_DEFAULT 26 // 55 ms -#define ESL_LIB_PAWR_SUBEVENT_INTERVAL_DEFAULT 44 +#define ESL_LIB_PAWR_SUBEVENT_INTERVAL_DEFAULT 48 // Time between the advertising packet in a subevent and the first response // slot. Value in units of 1.25 ms. -#define ESL_LIB_PAWR_RESPONSE_SLOT_DELAY_DEFAULT 30 +#define ESL_LIB_PAWR_RESPONSE_SLOT_DELAY_DEFAULT 34 // Time between response slots. Value in units of 0.125 ms. // 0.75 ms enough for up to 75 bytes on 1M phy // (including LL overhead plus T_IFS) @@ -456,6 +456,7 @@ typedef struct esl_lib_evt_connection_opened_s { esl_lib_connection_handle_t connection_handle; ///< Connection handle esl_lib_address_t address; ///< BLE address esl_lib_gattdb_handles_t gattdb_handles; ///< GATT database handles + sl_status_t status; ///< Status } esl_lib_evt_connection_opened_t; /// Bonding data event diff --git a/app/bluetooth/common_host/esl_lib/esl_lib_ap_control.c b/app/bluetooth/common_host/esl_lib/esl_lib_ap_control.c index ade29d221b..2b17b3db20 100644 --- a/app/bluetooth/common_host/esl_lib/esl_lib_ap_control.c +++ b/app/bluetooth/common_host/esl_lib/esl_lib_ap_control.c @@ -97,15 +97,15 @@ static sl_status_t send_event_from_storage(esl_lib_ap_control_evt_type_t evt_typ // Private variables static ap_control_t ap_control = { - .initialized = false, - .cp_handle = ESL_LIB_INVALID_CHARACTERISTIC_HANDLE, - .it_handle = ESL_LIB_INVALID_CHARACTERISTIC_HANDLE, - .state = ESL_LIB_AP_CONTROL_STATE_DISCONNECTED, - .conn_handle = SL_BT_INVALID_CONNECTION_HANDLE, + .initialized = false, + .cp_handle = ESL_LIB_INVALID_CHARACTERISTIC_HANDLE, + .it_handle = ESL_LIB_INVALID_CHARACTERISTIC_HANDLE, + .state = ESL_LIB_AP_CONTROL_STATE_DISCONNECTED, + .conn_handle = SL_BT_INVALID_CONNECTION_HANDLE, .subscribed_cp = false, .subscribed_it = false, - .adv_handle = SL_BT_INVALID_ADVERTISING_SET_HANDLE, - .cp_storage = ESL_LIB_INVALID_HANDLE + .adv_handle = SL_BT_INVALID_ADVERTISING_SET_HANDLE, + .cp_storage = ESL_LIB_INVALID_HANDLE }; // ----------------------------------------------------------------------------- @@ -113,12 +113,24 @@ static ap_control_t ap_control = { sl_status_t esl_lib_ap_control_cleanup(void) { - if (ap_control.conn_handle != SL_BT_INVALID_CONNECTION_HANDLE) { - (void)sl_bt_connection_close(ap_control.conn_handle); + if (ap_control.initialized) { + if (ap_control.conn_handle != SL_BT_INVALID_CONNECTION_HANDLE) { + (void)sl_bt_connection_close(ap_control.conn_handle); + } + (void)esl_lib_ap_control_adv_enable(false); + (void)esl_lib_storage_delete(&ap_control.cp_storage); + esl_lib_log_ap_control_debug("AP Control cleanup complete" APP_LOG_NL); + // Reset static state storage + ap_control.initialized = false; + ap_control.cp_handle = ESL_LIB_INVALID_CHARACTERISTIC_HANDLE; + ap_control.it_handle = ESL_LIB_INVALID_CHARACTERISTIC_HANDLE; + ap_control.state = ESL_LIB_AP_CONTROL_STATE_DISCONNECTED; + ap_control.conn_handle = SL_BT_INVALID_CONNECTION_HANDLE; + ap_control.subscribed_cp = false; + ap_control.subscribed_it = false; + ap_control.adv_handle = SL_BT_INVALID_ADVERTISING_SET_HANDLE; + ap_control.cp_storage = ESL_LIB_INVALID_HANDLE; } - (void)esl_lib_storage_delete(&ap_control.cp_storage); - (void)esl_lib_ap_control_adv_enable(false); - esl_lib_log_ap_control_debug("AP Control cleanup complete" APP_LOG_NL); return SL_STATUS_OK; } diff --git a/app/bluetooth/common_host/esl_lib/esl_lib_connection.c b/app/bluetooth/common_host/esl_lib/esl_lib_connection.c index 91b135a5e9..d603eb2c78 100644 --- a/app/bluetooth/common_host/esl_lib/esl_lib_connection.c +++ b/app/bluetooth/common_host/esl_lib/esl_lib_connection.c @@ -112,7 +112,7 @@ static void connection_timeout(app_timer_t *timer, static void reconnect_timeout(app_timer_t *timer, void *data); static bool uuid_16_match(uint8_t *uuid_a, uint8_t *uuid_b); -static void connection_complete(esl_lib_connection_t *conn); +static void connection_complete(esl_lib_connection_t *conn, sl_status_t result); static bool check_connected(esl_lib_connection_t *conn); static bool check_image_transfer(esl_lib_connection_t *conn); static void on_image_transfer_type_arrived(esl_lib_image_transfer_handle_t handle, @@ -217,7 +217,7 @@ sl_status_t esl_lib_connection_open(esl_lib_command_list_cmd_t *cmd) sl_status_t sc = SL_STATUS_OK; esl_lib_address_t *identity = NULL; bd_addr *identity_addr = NULL; - esl_lib_connection_t *conn = cmd->data.cmd_connect.conn_hnd; + esl_lib_connection_t *conn = (esl_lib_connection_t *)cmd->data.cmd_connect.conn_hnd; uint8_t connection_handle = SL_BT_INVALID_CONNECTION_HANDLE; bd_addr *addr = NULL; uint8_t address_type = 0; @@ -247,7 +247,6 @@ sl_status_t esl_lib_connection_open(esl_lib_command_list_cmd_t *cmd) } else { esl_lib_log_connection_debug("Initiate new connection" APP_LOG_NL); } - if (cmd->data.cmd_connect.retries_left) { // Set address address = &cmd->data.cmd_connect.address; @@ -318,6 +317,7 @@ sl_status_t esl_lib_connection_open(esl_lib_command_list_cmd_t *cmd) sl_bt_gap_phy_1m, &connection_handle); } + if (sc == SL_STATUS_OK) { // If not retry, add a new connection if (conn == ESL_LIB_INVALID_HANDLE) { @@ -369,7 +369,7 @@ sl_status_t esl_lib_connection_open(esl_lib_command_list_cmd_t *cmd) // Pass the ownership of initial connect command to conn. handle on success - otherwise ap_core will free it conn->command = cmd; - conn->command->data.cmd_connect.conn_hnd = conn; + conn->command->data.cmd_connect.conn_hnd = (esl_lib_connection_handle_t)conn; conn->command_complete = false; esl_lib_log_connection_debug(CONN_FMT "Pending new connection to " ESL_LIB_LOG_ADDR_FORMAT APP_LOG_NL, conn, @@ -400,16 +400,30 @@ sl_status_t esl_lib_connection_open(esl_lib_command_list_cmd_t *cmd) ESL_LIB_LOG_ADDR(*address), sc); if (conn != NULL) { + // Let the caller free the command in case of error + if (conn->command == cmd) { + conn->command = NULL; + } (void)esl_lib_connection_remove_ptr(conn); cmd->data.cmd_connect.conn_hnd = ESL_LIB_INVALID_HANDLE; } } } else { - esl_lib_log_connection_error("Connection failure, no more retry attempts" APP_LOG_NL); - sc = SL_STATUS_BT_CTRL_CONNECTION_FAILED_TO_BE_ESTABLISHED; - // Force removal of connection handle in case of no more retry - (void)esl_lib_connection_remove_ptr(conn); - cmd->data.cmd_connect.conn_hnd = ESL_LIB_INVALID_HANDLE; + if (conn == ESL_LIB_INVALID_HANDLE) { + // Just to avoid any NULL dereferencing below - otherwise this code path is implausible: + // cmd->data.cmd_connect.retries_left shall never be initialized to zero! + sc = SL_STATUS_NOT_READY; + } else { + esl_lib_log_connection_error("Connection failure, no more retry attempts" APP_LOG_NL); + sc = SL_STATUS_BT_CTRL_CONNECTION_FAILED_TO_BE_ESTABLISHED; + // Let the caller free the command in case of error + if (conn->command == cmd) { + conn->command = NULL; + } + // Force removal of connection handle in case of no more retry + (void)esl_lib_connection_remove_ptr(conn); + cmd->data.cmd_connect.conn_hnd = ESL_LIB_INVALID_HANDLE; + } } return sc; } @@ -434,10 +448,11 @@ sl_status_t esl_lib_connection_add(uint8_t conn, } else { ptr = (esl_lib_connection_t *)esl_lib_memory_allocate(sizeof(esl_lib_connection_t)); if (ptr != NULL) { - *ptr_out = ptr; memset(ptr, 0, sizeof(*ptr)); ptr->connection_handle = conn; ptr->command_complete = true; + ptr->last_error = SL_STATUS_IN_PROGRESS; // Operation is in progress and not yet complete (pass or fail) + *ptr_out = ptr; sl_slist_push_back(&connection_list, &ptr->node); sc = app_timer_start(&ptr->timer, @@ -665,6 +680,7 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) (void)esl_lib_connection_remove_ptr(conn); conn = NULL; } else if (conn->command != NULL) { + const bool pending_connect = (conn->state == ESL_LIB_CONNECTION_STATE_CONNECTING || conn->state == ESL_LIB_CONNECTION_STATE_RECONNECTING); // Not connected, check if a retry is required (link issue or bonding issue) if ((conn->command->cmd_code == ESL_LIB_CMD_CONNECT) && (conn->command->data.cmd_connect.retries_left) @@ -681,9 +697,7 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) timeout = (pawr->config.adv_interval.max << 1) - (pawr->config.adv_interval.max >> 3); // = 1.5f * (pawr->config.adv_interval.max * 1.25f) [ms] } - if (reason == SL_STATUS_BT_CTRL_CONNECTION_FAILED_TO_BE_ESTABLISHED - && (conn->state == ESL_LIB_CONNECTION_STATE_CONNECTING - || conn->state == ESL_LIB_CONNECTION_STATE_RECONNECTING)) { + if (pending_connect) { // If a connection request via PAwR times out, the sl_bt_evt_connection_closed_id // event occurs without the preceding sl_bt_evt_connection_opened_id event! conn->command_complete = true; @@ -710,7 +724,7 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) break; } } else { - // check again for the out-of-retries reason - set SL_STATUS_ABORT in case + // Check again for the out-of-retries reason - set SL_STATUS_ABORT in case if (conn->command->cmd_code == ESL_LIB_CMD_CONNECT && conn->command->data.cmd_connect.retries_left == 0) { reason = SL_STATUS_ABORT; esl_lib_log_connection_debug(CONN_FMT "No more connect retry for " ESL_LIB_LOG_ADDR_FORMAT ", last handle = %u" APP_LOG_NL, @@ -719,14 +733,14 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) (conn->address_type ? "random" : "public"), ESL_LIB_LOG_BD_ADDR(conn->address), conn->connection_handle); + // Decouple the handle mapping to the ESL_LIB_CMD_CONNECT command as the connection handle will be freed, soon + conn->command->data.cmd_connect.conn_hnd = ESL_LIB_INVALID_HANDLE; } (void)send_connection_error(conn, ESL_LIB_STATUS_CONN_FAILED, reason, conn->state); - if ((conn->state == ESL_LIB_CONNECTION_STATE_CONNECTING - || conn->state == ESL_LIB_CONNECTION_STATE_RECONNECTING) - && find_tlv(conn->command, ESL_LIB_CONNECT_DATA_TYPE_PAWR, &tlv)) { + if (pending_connect) { // If a connection request via PAwR times out, the sl_bt_evt_connection_closed_id // event occurs without the preceding sl_bt_evt_connection_opened_id event! conn->command_complete = true; @@ -789,7 +803,7 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) conn->connection_handle, sc); // Close connection - (void)sl_bt_connection_close(conn->connection_handle); + (void)(void)close_connection(conn); lib_status = ESL_LIB_STATUS_CONN_SUBSCRIBE_FAILED; } } else { @@ -813,7 +827,7 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) conn->connection_handle, sc); // Close connection - (void)sl_bt_connection_close(conn->connection_handle); + (void)close_connection(conn); lib_status = ESL_LIB_STATUS_CONN_DISCOVERY_FAILED; } } @@ -936,7 +950,7 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) conn, conn->connection_handle); // Close the connection in case of error. - (void)sl_bt_connection_close(conn->connection_handle); + (void)close_connection(conn); } } else { esl_lib_log_connection_error(CONN_FMT "No passkey available but requested, connection handle = %u" APP_LOG_NL, @@ -960,7 +974,7 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) conn->state = ESL_LIB_CONNECTION_STATE_BONDING; } else { // Close the connection in case of error. - (void)sl_bt_connection_close(conn->connection_handle); + (void)close_connection(conn); lib_status = ESL_LIB_STATUS_BONDING_FAILED; esl_lib_log_connection_error(CONN_FMT "Increase security failed, connection handle = %u, sc = 0x%04x" APP_LOG_NL, conn, @@ -1028,7 +1042,7 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) // Save reason to the status variable. sc = evt->data.evt_sm_bonding_failed.reason; } - // Try to close connection + // Try to close connection gently - it should be closing already (void)close_connection(conn); } else { // Suppress error event for unknown connections @@ -1048,7 +1062,7 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) conn, conn->connection_handle, sc); - (void)sl_bt_connection_close(conn->connection_handle); + (void)close_connection(conn); } else if (evt->data.evt_gatt_service.uuid.len == sizeof(sl_bt_uuid_16_t)) { // Check for service UUIDs if (uuid_16_match(evt->data.evt_gatt_service.uuid.data, (uint8_t *)uuid_map.services.dis.data)) { @@ -1220,7 +1234,7 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) } if (sc != SL_STATUS_OK) { // Close connection - (void)sl_bt_connection_close(conn->connection_handle); + (void)close_connection(conn); lib_status = ESL_LIB_STATUS_CONN_DISCOVERY_FAILED; esl_lib_log_connection_error(CONN_FMT "DIS discovery failed, connection handle = %u, sc = 0x%04x" APP_LOG_NL, conn, @@ -1243,11 +1257,11 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) false); } } else { - sc = SL_STATUS_BT_ATT_INVALID_HANDLE; + sc = SL_STATUS_BT_ATT_REQUEST_NOT_SUPPORTED; } if (sc != SL_STATUS_OK) { // Close connection - (void)sl_bt_connection_close(conn->connection_handle); + (void)close_connection(conn); lib_status = ESL_LIB_STATUS_CONN_DISCOVERY_FAILED; esl_lib_log_connection_error(CONN_FMT "Discovery failed, connection handle = %u, sc = 0x%04x" APP_LOG_NL, conn, @@ -1275,7 +1289,7 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) } if (sc != SL_STATUS_OK) { // Close connection - (void)sl_bt_connection_close(conn->connection_handle); + (void)close_connection(conn); lib_status = ESL_LIB_STATUS_CONN_DISCOVERY_FAILED; esl_lib_log_connection_error(CONN_FMT "DIS discovery failed, connection handle = %u, sc = 0x%04x" APP_LOG_NL, conn, @@ -1286,7 +1300,7 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) // Set the cause of the error sc = SL_STATUS_INVALID_HANDLE; // Close connection - (void)sl_bt_connection_close(conn->connection_handle); + (void)close_connection(conn); lib_status = ESL_LIB_STATUS_CONN_DISCOVERY_FAILED; esl_lib_log_connection_error(CONN_FMT "ESL Service not found, connection handle = %u, sc = 0x%04x" APP_LOG_NL, conn, @@ -1322,7 +1336,7 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) } if (sc != SL_STATUS_OK) { // Close connection - (void)sl_bt_connection_close(conn->connection_handle); + (void)close_connection(conn); lib_status = ESL_LIB_STATUS_CONN_SUBSCRIBE_FAILED; esl_lib_log_connection_error(CONN_FMT "Subscribe failed, connection handle = %u, sc = 0x%04x" APP_LOG_NL, conn, @@ -1333,7 +1347,7 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) // Set the cause of the error sc = SL_STATUS_INVALID_HANDLE; // Close connection - (void)sl_bt_connection_close(conn->connection_handle); + (void)close_connection(conn); lib_status = ESL_LIB_STATUS_CONN_SUBSCRIBE_FAILED; esl_lib_log_connection_error(CONN_FMT "ESL CP not found, connection handle = %u, sc = 0x%04x" APP_LOG_NL, conn, @@ -1360,7 +1374,7 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) conn->state = ESL_LIB_CONNECTION_STATE_OTS_INIT; } else { // Close connection - (void)sl_bt_connection_close(conn->connection_handle); + (void)close_connection(conn); lib_status = ESL_LIB_STATUS_OTS_INIT_FAILED; esl_lib_log_connection_error(CONN_FMT "Image Transfer - OTS init failed, connection handle = %u, sc = 0x%04x" APP_LOG_NL, conn, @@ -1369,7 +1383,7 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) } } else { // If no OTS present, consider complete - connection_complete(conn); + connection_complete(conn, SL_STATUS_OK); } break; default: @@ -1379,7 +1393,7 @@ void esl_lib_connection_on_bt_event(sl_bt_msg_t *evt) // If not in image transfer, procedures handled by this module if (!check_image_transfer(conn)) { // Close connection on procedure failure - (void)sl_bt_connection_close(conn->connection_handle); + (void)close_connection(conn); lib_status = ESL_LIB_STATUS_CONN_LOST; sc = evt->data.evt_gatt_procedure_completed.result; esl_lib_log_connection_error(CONN_FMT "Procedure failure, connection handle = %u, result = 0x%04x" APP_LOG_NL, @@ -1446,46 +1460,45 @@ static void esl_lib_connection_safe_remove_ptr(esl_lib_connection_t *ptr) esl_lib_memory_free(ptr->command); } clean_tag_info(ptr); - esl_lib_log_connection_debug(CONN_FMT "Removed connection handle = %u" APP_LOG_NL, + esl_lib_log_connection_debug(CONN_FMT "Removed connection handle = %u, last error: 0x%04x" APP_LOG_NL, ptr, - ptr->connection_handle); + ptr->connection_handle, + ptr->last_error); // Sanitize handles in memory area to avoid possible corruption later due to garbage ptr->connection_handle = SL_BT_INVALID_CONNECTION_HANDLE; - ptr->ots_handle = ESL_LIB_INVALID_HANDLE; + esl_lib_image_dump_transfer_by_handle(&ptr->ots_handle); esl_lib_memory_free(ptr); } static void run_command(esl_lib_command_list_cmd_t *cmd) { - sl_status_t sc = SL_STATUS_OK; + sl_status_t sc = SL_STATUS_DELETED; esl_lib_connection_t *conn = NULL; esl_lib_status_t lib_status = ESL_LIB_STATUS_NO_ERROR; switch (cmd->cmd_code) { case ESL_LIB_CMD_CLOSE_CONNECTION: conn = (esl_lib_connection_t *)cmd->data.cmd_close_connection; - esl_lib_log_connection_debug(CONN_FMT "Close connection command, connection handle = %u" APP_LOG_NL, - conn, - conn->connection_handle); if (esl_lib_connection_contains(conn)) { + esl_lib_log_connection_debug(CONN_FMT "Close connection command, connection handle = %u" APP_LOG_NL, + conn, + conn->connection_handle); sc = close_connection(conn); + esl_lib_log_connection_debug(CONN_FMT "After Close connection command, connection handle = %u , sc = 0x%04x" APP_LOG_NL, + conn, + conn->connection_handle, + sc); } else { - sc = SL_STATUS_DELETED; - lib_status = ESL_LIB_STATUS_CONN_FAILED; - conn->command_complete = true; + lib_status = ESL_LIB_STATUS_CONN_CLOSE_FAILED; } - esl_lib_log_connection_debug(CONN_FMT "After Close connection command, connection handle = %u , sc = 0x%04x" APP_LOG_NL, - conn, - conn->connection_handle, - sc); break; case ESL_LIB_CMD_GET_TAG_INFO: conn = (esl_lib_connection_t *)cmd->data.cmd_write_image.connection_handle; - esl_lib_log_connection_debug(CONN_FMT "Get tag info command, connection handle = %u" APP_LOG_NL, - conn, - conn->connection_handle); lib_status = ESL_LIB_STATUS_CONN_READ_FAILED; if (esl_lib_connection_contains(conn)) { + esl_lib_log_connection_debug(CONN_FMT "Get tag info command, connection handle = %u" APP_LOG_NL, + conn, + conn->connection_handle); // Check OTS features if (conn->ots_handle != ESL_LIB_INVALID_HANDLE) { conn->tag_info_type = ESL_LIB_DATA_TYPE_GATT_OTS_FEATURE; @@ -1516,7 +1529,7 @@ static void run_command(esl_lib_command_list_cmd_t *cmd) conn, conn->tag_info_type, conn->connection_handle); - sc = get_tag_info_finish(conn, sc); + (void)get_tag_info_finish(conn, sc); } } if (sc == SL_STATUS_OK) { @@ -1526,35 +1539,30 @@ static void run_command(esl_lib_command_list_cmd_t *cmd) lib_status = ESL_LIB_STATUS_NO_ERROR; } } - } else { - sc = SL_STATUS_DELETED; - conn->command_complete = true; } break; case ESL_LIB_CMD_CONFIGURE_TAG: conn = (esl_lib_connection_t *)cmd->data.cmd_configure_tag.connection_handle; - esl_lib_log_connection_debug(CONN_FMT "Configure tag command, connection handle = %u" APP_LOG_NL, - conn, - conn->connection_handle); - lib_status = ESL_LIB_STATUS_CONN_CONFIG_FAILED; if (esl_lib_connection_contains(conn)) { + esl_lib_log_connection_debug(CONN_FMT "Configure tag command, connection handle = %u" APP_LOG_NL, + conn, + conn->connection_handle); // Clear index and type conn->config_index = 0; conn->config_type = ESL_LIB_DATA_TYPE_UNINITIALIZED; // Start write process using TLV(s) - (void)write_next_config_value(conn); + sc = write_next_config_value(conn); } else { - sc = SL_STATUS_DELETED; - conn->command_complete = true; + lib_status = ESL_LIB_STATUS_CONN_CONFIG_FAILED; } break; case ESL_LIB_CMD_WRITE_CONTROL_POINT: conn = (esl_lib_connection_t *)cmd->data.cmd_write_control_point.connection_handle; - esl_lib_log_connection_debug(CONN_FMT "Write control point command, connection handle = %u" APP_LOG_NL, - conn, - conn->connection_handle); lib_status = ESL_LIB_STATUS_CONN_WRITE_CP_FAILED; if (esl_lib_connection_contains(conn) && conn->command != NULL) { + esl_lib_log_connection_debug(CONN_FMT "Write control point command, connection handle = %u" APP_LOG_NL, + conn, + conn->connection_handle); // Write characteristic value (with or without response) sc = write_value(conn, conn->command->data.cmd_write_control_point.att_response, @@ -1580,18 +1588,16 @@ static void run_command(esl_lib_command_list_cmd_t *cmd) // Do not generate error event sc = SL_STATUS_OK; } - } else { - sc = SL_STATUS_DELETED; - conn->command_complete = true; } break; case ESL_LIB_CMD_WRITE_IMAGE: conn = (esl_lib_connection_t *)cmd->data.cmd_write_image.connection_handle; - esl_lib_log_connection_debug(CONN_FMT "Write image command, connection handle = %u" APP_LOG_NL, - conn, - conn->connection_handle); + lib_status = ESL_LIB_STATUS_OTS_ERROR; if (esl_lib_connection_contains(conn)) { esl_lib_image_transfer_handle_t it_handle = conn->ots_handle; + esl_lib_log_connection_debug(CONN_FMT "Write image command, connection handle = %u" APP_LOG_NL, + conn, + conn->connection_handle); if (it_handle != ESL_LIB_INVALID_HANDLE) { sc = esl_lib_image_transfer_start(it_handle, cmd->data.cmd_write_image.img_index, @@ -1600,129 +1606,125 @@ static void run_command(esl_lib_command_list_cmd_t *cmd) cmd->data.cmd_write_image.img_data_copied); if (sc == SL_STATUS_OK) { conn->state = ESL_LIB_CONNECTION_STATE_OTS_IMAGE_TRANSFER; + lib_status = ESL_LIB_STATUS_NO_ERROR; } else { - lib_status = ESL_LIB_STATUS_OTS_ERROR; conn->command_complete = true; } } else { - sc = SL_STATUS_NOT_INITIALIZED; - lib_status = ESL_LIB_STATUS_OTS_ERROR; + sc = SL_STATUS_NOT_INITIALIZED; conn->command_complete = true; } - } else { - sc = SL_STATUS_DELETED; - lib_status = ESL_LIB_STATUS_OTS_ERROR; - conn->command_complete = true; } break; case ESL_LIB_CMD_GET_IMAGE_TYPE: conn = (esl_lib_connection_t *)cmd->data.cmd_get_image_type.connection_handle; - esl_lib_log_connection_debug(CONN_FMT "Get image type command, connection handle = %u" APP_LOG_NL, - conn, - conn->connection_handle); + lib_status = ESL_LIB_STATUS_OTS_ERROR; if (esl_lib_connection_contains(conn)) { + esl_lib_log_connection_debug(CONN_FMT "Get image type command, connection handle = %u" APP_LOG_NL, + conn, + conn->connection_handle); esl_lib_image_transfer_handle_t it_handle = conn->ots_handle; if (it_handle != ESL_LIB_INVALID_HANDLE) { sc = esl_lib_image_transfer_get_type(it_handle, cmd->data.cmd_get_image_type.img_index); if (sc == SL_STATUS_OK) { conn->state = ESL_LIB_CONNECTION_STATE_OTS_GET_TYPE; + lib_status = ESL_LIB_STATUS_NO_ERROR; } else { - lib_status = ESL_LIB_STATUS_OTS_ERROR; conn->command_complete = true; } } else { - sc = SL_STATUS_NOT_INITIALIZED; - lib_status = ESL_LIB_STATUS_OTS_ERROR; + sc = SL_STATUS_NOT_INITIALIZED; conn->command_complete = true; } - } else { - sc = SL_STATUS_DELETED; - lib_status = ESL_LIB_STATUS_OTS_ERROR; - conn->command_complete = true; } break; - case ESL_LIB_CMD_INITIATE_PAST: { - uint32_t supervison_timeout = PAST_CONN_DEFAULT_TIMEOUT; - uint16_t min_interval = 2 * PAST_CONN_INTERVAL_MIN; - uint16_t max_interval = PAST_CONN_INTERVAL_MAX; - + case ESL_LIB_CMD_INITIATE_PAST: conn = (esl_lib_connection_t *)cmd->data.cmd_init_past.connection_handle; - esl_lib_pawr_t *pawr = NULL; - esl_lib_log_connection_debug(CONN_FMT "Initiate PAST command, connection handle = %u" APP_LOG_NL, - conn, - conn->connection_handle); - if (conn->command != NULL) { - pawr = (esl_lib_pawr_t *)conn->command->data.cmd_init_past.pawr_handle; - } + if (esl_lib_connection_contains(conn)) { + uint32_t supervison_timeout = PAST_CONN_DEFAULT_TIMEOUT; + uint16_t min_interval = 2 * PAST_CONN_INTERVAL_MIN; + uint16_t max_interval = PAST_CONN_INTERVAL_MAX; + esl_lib_pawr_t *pawr = NULL; + esl_lib_log_connection_debug(CONN_FMT "Initiate PAST command, connection handle = %u" APP_LOG_NL, + conn, + conn->connection_handle); + if (conn->command != NULL) { + pawr = (esl_lib_pawr_t *)conn->command->data.cmd_init_past.pawr_handle; + } - if (esl_lib_connection_contains(conn) && esl_lib_pawr_contains(pawr)) { - supervison_timeout = pawr->config.adv_interval.max + pawr->config.adv_interval.max / 4; // * 1.25ms - min_interval = pawr->config.adv_interval.min / 8; - max_interval = pawr->config.adv_interval.max / 4; + if (esl_lib_pawr_contains(pawr)) { + supervison_timeout = pawr->config.adv_interval.max + pawr->config.adv_interval.max / 4; // * 1.25ms + min_interval = pawr->config.adv_interval.min / 8; + max_interval = pawr->config.adv_interval.max / 4; - if (max_interval > PAST_CONN_INTERVAL_MAX) { - max_interval = PAST_CONN_INTERVAL_MAX; - } + if (max_interval > PAST_CONN_INTERVAL_MAX) { + max_interval = PAST_CONN_INTERVAL_MAX; + } - supervison_timeout *= (PAST_CONN_PERIPHERAL_LATENCY + 1); // Core spec. 5.4 Vol 4, Part E, 7.8.31. - supervison_timeout = (supervison_timeout / 10) + 1; + supervison_timeout *= (PAST_CONN_PERIPHERAL_LATENCY + 1); // Core spec. 5.4 Vol 4, Part E, 7.8.31. + supervison_timeout = (supervison_timeout / 10) + 1; - if (supervison_timeout > PAST_CONN_MAX_TIMEOUT) { - supervison_timeout = PAST_CONN_MAX_TIMEOUT; - } else if (supervison_timeout < PAST_CONN_MIN_TIMEOUT) { - supervison_timeout = PAST_CONN_MIN_TIMEOUT; - } + if (supervison_timeout > PAST_CONN_MAX_TIMEOUT) { + supervison_timeout = PAST_CONN_MAX_TIMEOUT; + } else if (supervison_timeout < PAST_CONN_MIN_TIMEOUT) { + supervison_timeout = PAST_CONN_MIN_TIMEOUT; + } - if (min_interval < PAST_CONN_INTERVAL_MIN) { - min_interval = PAST_CONN_INTERVAL_MIN; - } else if (min_interval > max_interval / 2) { - min_interval = max_interval / 2; - } + if (min_interval < PAST_CONN_INTERVAL_MIN) { + min_interval = PAST_CONN_INTERVAL_MIN; + } else if (min_interval > max_interval / 2) { + min_interval = max_interval / 2; + } - sc = sl_bt_connection_set_parameters(conn->connection_handle, + sc = sl_bt_connection_set_parameters(conn->connection_handle, + min_interval, + max_interval, + PAST_CONN_PERIPHERAL_LATENCY, + (uint16_t)supervison_timeout, + PAST_CONN_MIN_CE_LENGTH, + PAST_CONN_MAX_CE_LENGTH); + if (sc == SL_STATUS_OK) { + conn->state = ESL_LIB_CONNECTION_STATE_PAST_INIT; + } else { + lib_status = ESL_LIB_STATUS_PAST_INIT_FAILED; + conn->command_complete = true; + // Ignore the warning if the connection is already closed by a remote node still in sync + if (sc != SL_STATUS_BT_CTRL_COMMAND_DISALLOWED) { + esl_lib_log_connection_warning(CONN_FMT "PAST init fail with connection interval[%u - %u] and timeout: %u, connection handle = %u, sc = 0x%04x" APP_LOG_NL, + conn, min_interval, max_interval, - PAST_CONN_PERIPHERAL_LATENCY, - (uint16_t)supervison_timeout, - PAST_CONN_MIN_CE_LENGTH, - PAST_CONN_MAX_CE_LENGTH); - if (sc == SL_STATUS_OK) { - conn->state = ESL_LIB_CONNECTION_STATE_PAST_INIT; - } else { - lib_status = ESL_LIB_STATUS_PAST_INIT_FAILED; - conn->command_complete = true; - // Ignore the warning if the connection is already closed by a remote node still in sync - if (sc != SL_STATUS_BT_CTRL_COMMAND_DISALLOWED) { - esl_lib_log_connection_warning(CONN_FMT "PAST init fail with connection interval[%u - %u] and timeout: %u, connection handle = %u, sc = 0x%04x" APP_LOG_NL, - conn, - min_interval, - max_interval, - supervison_timeout, - conn->connection_handle, - sc); + supervison_timeout, + conn->connection_handle, + sc); + } } + // Start timeout anyway: the ESL may close/closing/closed the connection because it can be already in sync + sc = app_timer_start(&conn->timer, + 10 * supervison_timeout, + connection_timeout, + conn, + false); } - // Start timeout anyway: the ESL may close/closing/closed the connection because it can be already in sync - sc = app_timer_start(&conn->timer, - 10 * supervison_timeout, - connection_timeout, - conn, - false); } else { - sc = SL_STATUS_DELETED; lib_status = ESL_LIB_STATUS_PAST_INIT_FAILED; - conn->command_complete = true; } - } break; + break; default: break; } - if (sc != SL_STATUS_OK && conn != NULL) { - esl_lib_log_connection_warning(CONN_FMT "Command failure, connection handle = %u, sc = 0x%04x" APP_LOG_NL, + + if (sc == SL_STATUS_DELETED) { + esl_lib_log_connection_warning(CONN_FMT "Command failure on command %d, sc = 0x%04x" APP_LOG_NL, conn, - conn->connection_handle, + cmd->cmd_code, sc); + } else if (sc != SL_STATUS_OK && conn != NULL) { + esl_lib_log_connection_error(CONN_FMT "Command failure, connection handle = %u, sc = 0x%04x" APP_LOG_NL, + conn, + conn->connection_handle, + sc); // Send connection error if connection is present. (void)send_connection_error(conn, lib_status, @@ -1870,6 +1872,8 @@ static sl_status_t send_connection_status(esl_lib_connection_t *conn, // Set handle lib_evt->data.evt_connection_opened.connection_handle = (esl_lib_connection_handle_t)conn; + // Set sl_status + lib_evt->data.evt_connection_opened.status = reason; // Copy address lib_evt->data.evt_connection_opened.address.address_type = conn->address_type; memcpy(lib_evt->data.evt_connection_opened.address.addr, @@ -1994,8 +1998,13 @@ static sl_status_t send_connection_error(esl_lib_connection_t *conn, static sl_status_t close_connection(esl_lib_connection_t *conn) { - sl_status_t sc; - sc = sl_bt_connection_close(conn->connection_handle); + sl_status_t sc = SL_STATUS_OK; + + if (conn->last_error != SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_BY_LOCAL_HOST) { + sc = sl_bt_connection_close(conn->connection_handle); + // Invalidate to avoid later possible redundant close calls that would fail + conn->last_error = SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_BY_LOCAL_HOST; + } return sc; } @@ -2004,9 +2013,9 @@ static bool uuid_16_match(uint8_t *uuid_a, uint8_t *uuid_b) return (memcmp(uuid_a, uuid_b, sizeof(sl_bt_uuid_16_t)) == 0); } -static void connection_complete(esl_lib_connection_t *conn) +static void connection_complete(esl_lib_connection_t *conn, sl_status_t result) { - (void)send_connection_status(conn, ESL_LIB_TRUE, SL_STATUS_OK); + (void)send_connection_status(conn, ESL_LIB_TRUE, result); conn->state = ESL_LIB_CONNECTION_STATE_CONNECTED; // Open command has been completed. if (conn->command->cmd_code == ESL_LIB_CMD_CONNECT) { @@ -2071,31 +2080,42 @@ static void on_image_transfer_status(esl_lib_image_transfer_handle_t handle, if (state == ESL_LIB_IMAGE_TRANSFER_STATE_IDLE) { // init succeeded - connection_complete(conn); + connection_complete(conn, result); + conn->command_complete = true; } } - if (state == ESL_LIB_IMAGE_TRANSFER_REMOVED && check_image_transfer(conn)) { - // Removed since there were an error during init or transfer - (void)send_connection_error(conn, - ESL_LIB_STATUS_OTS_INIT_FAILED, - result, - conn->state); - // Close connection as OTS errors are mostly unrecoverable - esl_lib_log_connection_debug(CONN_FMT "Close connection due image transfer status 0x%04x, connection handle = %u, sc = 0x%04x" APP_LOG_NL, - conn, - result, - sc, - conn->connection_handle); - close_broken_connection(&conn); + if (state == ESL_LIB_IMAGE_TRANSFER_REMOVED) { + // Clear local handle reference in case of it's been already deleted by an error + conn->ots_handle = ESL_LIB_INVALID_HANDLE; + } - if (conn != NULL) { - // Note that conn might have been deleted already due an error case! + if (check_image_transfer(conn)) { + if (state == ESL_LIB_IMAGE_TRANSFER_STATE_NOT_INITIALIZED) { + // Removed since there were an error during init or transfer + (void)send_connection_error(conn, + ESL_LIB_STATUS_OTS_INIT_FAILED, + result, + conn->state); + // Close connection as OTS errors are mostly unrecoverable + esl_lib_log_connection_debug(CONN_FMT "Close connection due image transfer status 0x%04x, connection handle = %u, state = %d" APP_LOG_NL, + conn, + result, + conn->connection_handle, + state); + close_broken_connection(&conn); + } else if (state == ESL_LIB_IMAGE_TRANSFER_STATE_ERROR) { + (void)send_connection_error(conn, + ESL_LIB_STATUS_OTS_ERROR, + result, + conn->state); + // Let the AP try to continue in this case conn->command_complete = true; + conn->state = ESL_LIB_CONNECTION_STATE_CONNECTED; } } } else { - esl_lib_log_connection_debug("[Unknown] Image transfer status changed for a forcibly closed connection, no handle available anymore." APP_LOG_NL); + esl_lib_log_connection_warning("[Unknown] Image transfer status changed for a deceised connection, no handle available anymore" APP_LOG_NL); } } @@ -2116,6 +2136,13 @@ static void on_image_transfer_finished(esl_lib_image_transfer_handle_t handle, result, conn->connection_handle); + // Free up image data if still there after ESL_LIB_CMD_WRITE_IMAGE request + if (conn->command != NULL && conn->command->cmd_code == ESL_LIB_CMD_WRITE_IMAGE && conn->command->data.cmd_write_image.img_data_copied != NULL) { + esl_lib_memory_free(conn->command->data.cmd_write_image.img_data_copied); + conn->command_complete = true; // Also report command complete + conn->state = ESL_LIB_CONNECTION_STATE_CONNECTED; // And return to connected, idle. + } + if (result == SL_STATUS_OK) { sc = esl_lib_event_list_allocate(ESL_LIB_EVT_IMAGE_TRANSFER_FINISHED, 0, &lib_evt); if (sc == SL_STATUS_OK) { @@ -2129,29 +2156,20 @@ static void on_image_transfer_finished(esl_lib_image_transfer_handle_t handle, ESL_LIB_STATUS_OTS_TRANSFER_FAILED, result, conn->state); - esl_lib_log_connection_debug(CONN_FMT "Close connection due image transfer finished result: 0x%04x, connection handle = %u, sc = 0x%04x" APP_LOG_NL, - conn, - result, - conn->connection_handle, - sc); if (result == SL_STATUS_TIMEOUT - || result == SL_STATUS_NO_MORE_RESOURCE || result == SL_STATUS_FAIL + || result == SL_STATUS_INITIALIZATION + || result == SL_STATUS_TRANSMIT_INCOMPLETE + || result == SL_STATUS_NO_MORE_RESOURCE || result == SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_NO_SUITABLE_CHANNEL_FOUND) { + esl_lib_log_connection_debug(CONN_FMT "Close connection due image transfer finished result: 0x%04x, connection handle = %u" APP_LOG_NL, + conn, + result, + conn->connection_handle); // Close connection as some OTS errors are unrecoverable close_broken_connection(&conn); } } - - if (conn != NULL && conn->command != NULL) { - // Note that conn might have been deleted already due an error case! - // Free up image data if still there - if (conn->command->data.cmd_write_image.img_data_copied != NULL) { - esl_lib_memory_free(conn->command->data.cmd_write_image.img_data_copied); - } - conn->command_complete = true; - conn->state = ESL_LIB_CONNECTION_STATE_CONNECTED; - } } } @@ -2173,6 +2191,8 @@ static void on_image_transfer_type_arrived(esl_lib_image_transfer_handle_t handl result, conn->connection_handle); if (result == SL_STATUS_OK) { + conn->command_complete = true; + conn->state = ESL_LIB_CONNECTION_STATE_CONNECTED; sc = esl_lib_event_list_allocate(ESL_LIB_EVT_IMAGE_TYPE, len, &lib_evt); if (sc == SL_STATUS_OK) { lib_evt->data.evt_image_type.connection_handle = conn; @@ -2190,18 +2210,11 @@ static void on_image_transfer_type_arrived(esl_lib_image_transfer_handle_t handl ESL_LIB_STATUS_OTS_META_READ_FAILED, result, conn->state); - esl_lib_log_connection_debug(CONN_FMT "Close connection due image get type fail 0x%04x, connection handle = %u, sc = 0x%04x" APP_LOG_NL, + esl_lib_log_connection_debug(CONN_FMT "OTS Image get type fail (0x%04x), image index: %u, connection handle = %u" APP_LOG_NL, conn, result, - sc, + image_index, conn->connection_handle); - // Close connection as OTS errors are mostly unrecoverable - close_broken_connection(&conn); - } - if (conn != NULL) { - // Note that conn might have been deleted already due an error case! - conn->command_complete = true; - conn->state = ESL_LIB_CONNECTION_STATE_CONNECTED; } } } @@ -2254,21 +2267,27 @@ static void reconnect_timeout(app_timer_t *timer, conn, ESL_LIB_LOG_ADDR(conn->command->data.cmd_connect.address), conn->connection_handle); - // Resend command to core queue - sc = esl_lib_core_add_command(conn->command); + if (conn->command && conn->command->cmd_code == ESL_LIB_CMD_CONNECT) { + // Resend connect command to core queue + sc = esl_lib_core_add_command(conn->command); + } else { + // It's an error condition if there's no active command for the connection or it's not an ESL_LIB_CMD_CONNECT request! + sc = SL_STATUS_DELETED; + } if (sc != SL_STATUS_OK) { (void)send_connection_error(conn, ESL_LIB_STATUS_CONN_FAILED, sc, conn->state); - esl_lib_log_connection_error(CONN_FMT "Failed to reopen connection, connection handle = %u" APP_LOG_NL, + esl_lib_log_connection_error(CONN_FMT "Failed to reopen connection, connection handle = %u, sc = 0x%04x" APP_LOG_NL, conn, - conn->connection_handle); + conn->connection_handle, + sc); // And also remove connection from the list. (void)esl_lib_connection_remove_ptr(conn); - conn = NULL; } else { + // Decouple the connect command as it's been successfully queued again - we'll take ownership again, later. conn->command = NULL; conn->command_complete = true; } @@ -2283,21 +2302,29 @@ static void connection_timeout(app_timer_t *timer, { (void)timer; sl_status_t sc; - esl_lib_status_t status; + esl_lib_status_t status = ESL_LIB_STATUS_CONN_TIMEOUT; esl_lib_connection_t *conn = (esl_lib_connection_t *)data; // Check if it exists if (esl_lib_connection_contains(conn)) { esl_lib_log_connection_warning(CONN_FMT "Connection timeout, connection handle = %u" APP_LOG_NL, conn, conn->connection_handle); - // Try to close the connection - sc = close_connection(conn); - if (sc == SL_STATUS_OK) { - // Send timeout - status = ESL_LIB_STATUS_CONN_TIMEOUT; - } else { - // Send error for closing + if (conn->last_error == SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_BY_LOCAL_HOST) { + // This is the timeout for earlier local close request! Send error for closing because close event didn't arrive. status = ESL_LIB_STATUS_CONN_CLOSE_FAILED; + } else { + // Try to gentle close the connection in the first place + sc = close_connection(conn); + if (sc != SL_STATUS_OK) { + status = ESL_LIB_STATUS_CONN_CLOSE_FAILED; + } else { + // Restart timer one last time as final watchdog + (void)app_timer_start(&conn->timer, + CLOSE_TIMEOUT_MS, + connection_timeout, + conn, + false); + } } (void)send_connection_error(conn, @@ -2305,12 +2332,12 @@ static void connection_timeout(app_timer_t *timer, SL_STATUS_TIMEOUT, conn->state); - if (conn->state == ESL_LIB_CONNECTION_STATE_CONNECTING - || conn->state == ESL_LIB_CONNECTION_STATE_RECONNECTING) { - esl_lib_core_connection_complete(); - } - if (status == ESL_LIB_STATUS_CONN_CLOSE_FAILED) { + if (conn->state == ESL_LIB_CONNECTION_STATE_CONNECTING + || conn->state == ESL_LIB_CONNECTION_STATE_RECONNECTING) { + // Report connection complete only if the connection opened event didn't arrive before the timeout + esl_lib_core_connection_complete(); + } // Remove connection (void)esl_lib_connection_remove_ptr(conn); } @@ -2477,7 +2504,7 @@ static sl_status_t get_tag_info_finish(esl_lib_connection_t *conn, sl_status_t s // Set command complete conn->command_complete = true; } else { - esl_lib_log_connection_debug("[Unknown] Get tag info finished for a forcibly closed broken connection, no handle available anymore." APP_LOG_NL); + esl_lib_log_connection_warning("[Unknown] Get tag info finished for a deceised connection, no handle available anymore" APP_LOG_NL); } return sc; @@ -2723,12 +2750,21 @@ static sl_status_t write_value(esl_lib_connection_t *conn, len, data, &sent_len); - if (sc == SL_STATUS_OK) { + if (sc == SL_STATUS_OK && sent_len == len) { esl_lib_log_connection_debug(CONN_FMT "Writing value type %u (0x%02x) succeeded, connection handle = %u" APP_LOG_NL, conn, type, characteristic, conn->connection_handle); + } else { + esl_lib_log_connection_warning(CONN_FMT "Writing value type %u (0x%02x) unsuccesful, connection handle = %u, length/sent: %u/%u, sc = 0x%04x" APP_LOG_NL, + conn, + type, + characteristic, + conn->connection_handle, + len, + sent_len, + sc); } } } else { @@ -2770,12 +2806,20 @@ static bool find_tlv(esl_lib_command_list_cmd_t *cmd, static void close_broken_connection(esl_lib_connection_t **conn) { - if (conn == NULL || *conn == NULL || (*conn)->connection_handle == SL_BT_INVALID_CONNECTION_HANDLE) { + if (conn == NULL || *conn == NULL + || (*conn)->connection_handle == SL_BT_INVALID_CONNECTION_HANDLE + || (*conn)->last_error == SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_BY_LOCAL_HOST) { // Nothing left to close (second invocation can happen on the same connection in edge cases, especially in case of various OTS errors) return; + } else { + (void)app_timer_stop(&(*conn)->timer); + esl_lib_log_connection_debug(CONN_FMT "Cleanup command list for connection handle = %u during close on error" APP_LOG_NL, + *conn, + (*conn)->connection_handle); + esl_lib_command_list_cleanup(&(*conn)->command_list); } - sl_status_t sc = sl_bt_connection_close((*conn)->connection_handle); + sl_status_t sc = close_connection(*conn); if (sc != SL_STATUS_OK) { esl_lib_log_connection_error(CONN_FMT "Closing request failed with status: 0x%04x on connection handle = %u during close on error" APP_LOG_NL, *conn, @@ -2790,11 +2834,12 @@ static void close_broken_connection(esl_lib_connection_t **conn) esl_lib_log_connection_debug(CONN_FMT "Requested closing connection with handle = %u on error" APP_LOG_NL, *conn, (*conn)->connection_handle); - (void)app_timer_stop(&(*conn)->timer); (void)app_timer_start(&(*conn)->timer, CLOSE_TIMEOUT_MS, connection_timeout, *conn, false); + // Prevent executing any future commands until the connection is closed + (*conn)->command_complete = false; } } diff --git a/app/bluetooth/common_host/esl_lib/esl_lib_core.c b/app/bluetooth/common_host/esl_lib/esl_lib_core.c index 8abc116596..fd97e6d229 100644 --- a/app/bluetooth/common_host/esl_lib/esl_lib_core.c +++ b/app/bluetooth/common_host/esl_lib/esl_lib_core.c @@ -146,8 +146,8 @@ void esl_lib_init(char *config) void esl_lib_process_action(void) { esl_lib_core_step(); - esl_lib_connection_step(); esl_lib_pawr_step(); + esl_lib_connection_step(); esl_lib_image_transfer_step(); } @@ -173,16 +173,20 @@ sl_status_t esl_lib_core_add_command(esl_lib_command_list_cmd_t *cmd) void sl_bt_on_event(sl_bt_msg_t *evt) { + esl_lib_pawr_on_bt_event(evt); esl_lib_image_transfer_on_bt_event(evt); esl_lib_connection_on_bt_event(evt); - esl_lib_pawr_on_bt_event(evt); esl_lib_core_on_bt_event(evt); esl_lib_ap_control_on_bt_event(evt); } void esl_lib_core_connection_complete() { - ap_state->command_complete = true; + // This function should only be called after the ESL_LIB_CMD_CONNECT request is processed (with or without error) + if (ap_state->command == NULL) { + // Since the ESL_LIB_CMD_CONNECT request is the owner of the command, the ap_state->command should be NULL + ap_state->command_complete = true; + } } // ----------------------------------------------------------------------------- @@ -562,7 +566,6 @@ static void run_command(esl_lib_command_list_cmd_t *cmd) } else { sc = SL_STATUS_INVALID_STATE; } - ap_state->command_complete = true; } else { lib_status = ESL_LIB_STATUS_SCAN_STOP_FAILED; sc = sl_bt_scanner_stop(); diff --git a/app/bluetooth/common_host/esl_lib/esl_lib_image_transfer.c b/app/bluetooth/common_host/esl_lib/esl_lib_image_transfer.c index 11c9fd75a9..f7a186c170 100644 --- a/app/bluetooth/common_host/esl_lib/esl_lib_image_transfer.c +++ b/app/bluetooth/common_host/esl_lib/esl_lib_image_transfer.c @@ -73,7 +73,6 @@ typedef enum { // Structure type holding a client typedef struct { sl_slist_node_t node; - esl_lib_image_transfer_handle_t image_transfer_handle; uint8_t connection_handle; sl_bt_ots_client_t ots_client; sl_bt_ots_features_t ots_server_features; @@ -218,7 +217,6 @@ sl_status_t esl_lib_image_transfer_init(uint8_t return SL_STATUS_ALLOCATION_FAILED; } else { memset(transfer, 0, sizeof(*transfer)); - transfer->image_transfer_handle = (esl_lib_image_transfer_handle_t)transfer; transfer->connection_handle = connection; if (gattdb_handles != NULL) { @@ -246,10 +244,10 @@ sl_status_t esl_lib_image_transfer_init(uint8_t // Add to the transfer list sl_slist_push(&image_transfer_list, &transfer->node); - *handle_out = transfer->image_transfer_handle; + *handle_out = (esl_lib_image_transfer_handle_t)transfer; esl_lib_log_it_debug(IT_FMT "Image transfer init started, connection handle = %u" APP_LOG_NL, - transfer->image_transfer_handle, + transfer, connection); // Start timer app_timer_start(&transfer->timer, @@ -259,7 +257,7 @@ sl_status_t esl_lib_image_transfer_init(uint8_t false); } else { esl_lib_log_it_error(IT_FMT "Image transfer init failed, sc = 0x%04x, connection handle = %u" APP_LOG_NL, - transfer->image_transfer_handle, + transfer, sc, connection); // Free up memory on error @@ -269,6 +267,30 @@ sl_status_t esl_lib_image_transfer_init(uint8_t return sc; } +sl_status_t esl_lib_image_dump_transfer_by_handle(esl_lib_image_transfer_handle_t *handle) +{ + sl_status_t sc = SL_STATUS_NULL_POINTER; + image_transfer_t *image_transfer; + + if (handle == NULL || *handle == ESL_LIB_INVALID_HANDLE) { + return sc; + } + + image_transfer = find_image_transfer_by_handle(*handle); + + if (image_transfer != ESL_LIB_IMAGE_TRANSFER_INVALID_HANDLE) { + // Dump transfer shall only ever call on deceased connections (if sl_bt_connection_close() fails)! + remove_transfer(&image_transfer, + SL_STATUS_NONE_WAITING, // Signal expected absence of sl_bt_evt_connection_closed_id event + false); + } else { + sc = SL_STATUS_INVALID_HANDLE; + } + + *handle = ESL_LIB_INVALID_HANDLE; + return sc; +} + sl_status_t esl_lib_image_transfer_get_type(esl_lib_image_transfer_handle_t handle, uint8_t image_index) { @@ -561,7 +583,7 @@ static sl_status_t search_image(image_transfer_t *image_transfer, // Set requested object ID image_index_to_object_id(image_index, &image_transfer->ots_requested_object_id); esl_lib_log_it_debug(IT_FMT "Searching index %u = %02X %02X ..." APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, image_index, image_transfer->ots_requested_object_id.data[0], image_transfer->ots_requested_object_id.data[1]); @@ -578,7 +600,7 @@ static sl_status_t search_image(image_transfer_t *image_transfer, if (goto_supported) { esl_lib_log_it_debug(IT_FMT "Moving with GOTO to image, index %u" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, image_index); sc = sl_bt_ots_client_olcp_go_to(&image_transfer->ots_client, &image_transfer->ots_requested_object_id); @@ -597,7 +619,7 @@ static sl_status_t search_image(image_transfer_t *image_transfer, } } else { esl_lib_log_it_debug(IT_FMT "Moving with FIRST+NEXT to image, index %u" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, image_index); sc = sl_bt_ots_client_olcp_first(&image_transfer->ots_client); if (sc == SL_STATUS_OK) { @@ -614,14 +636,14 @@ static sl_status_t search_image(image_transfer_t *image_transfer, NULL); } else { esl_lib_log_it_debug(IT_FMT "Write to the currently selected image, index %u" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, image_index); } } } if (sc != SL_STATUS_OK) { esl_lib_log_it_error(IT_FMT "Search image index %u failed, sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, image_index, sc); } @@ -755,7 +777,7 @@ static void start_requested_operation(image_transfer_t *image_transfer) (void)app_timer_stop(&image_transfer->timer); if (image_transfer->ots_ongoing_command == OTS_COMMAND_OBJECT_TYPE) { esl_lib_log_it_debug(IT_FMT "Reading object type of current object" APP_LOG_NL, - image_transfer->image_transfer_handle); + image_transfer); sc = sl_bt_ots_client_read_object_type(&image_transfer->ots_client); if (sc == SL_STATUS_OK) { @@ -768,14 +790,14 @@ static void start_requested_operation(image_transfer_t *image_transfer) image_transfer->ots_state = OTS_STATE_OBJECT_TYPE; } else { esl_lib_log_it_error(IT_FMT "Read object type failed, sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, sc); // Could not read type, finish the operation operation_finished(image_transfer, sc, false); } } else if (image_transfer->ots_ongoing_command == OTS_COMMAND_WRITE) { esl_lib_log_it_debug(IT_FMT "Write current object of size %u bytes." APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, image_transfer->ots_write_size); // Current object is selected, move on with writing the object. @@ -795,7 +817,7 @@ static void start_requested_operation(image_transfer_t *image_transfer) image_transfer->ots_state = OTS_STATE_WRITE; } else { esl_lib_log_it_error(IT_FMT "Write failed, sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, sc); // Could not start write, finish the operation operation_finished(image_transfer, sc, true); @@ -807,20 +829,27 @@ static void remove_transfer(image_transfer_t **image_transfer, sl_status_t sc, bool finish_transfer) { + if (sc != SL_STATUS_DELETED && find_image_transfer_by_handle(*image_transfer) == ESL_LIB_IMAGE_TRANSFER_INVALID_HANDLE) { + esl_lib_log_it_warning(IT_FMT "Remove attempt on already removed handle, sc = 0x%04x" APP_LOG_NL, + *image_transfer, + sc); + return; + } + (void)app_timer_stop(&(*image_transfer)->timer); esl_lib_log_it_debug(IT_FMT "Removing transfer" APP_LOG_NL, - (*image_transfer)->image_transfer_handle); + *image_transfer); sl_slist_remove(&image_transfer_list, &(*image_transfer)->node); + set_state(*image_transfer, ESL_LIB_IMAGE_TRANSFER_REMOVED, sc, NULL); if (finish_transfer) { esl_lib_log_it_debug(IT_FMT "Finishing transfer" APP_LOG_NL, - (*image_transfer)->image_transfer_handle); - (*image_transfer)->cb_finish((esl_lib_image_transfer_handle_t)image_transfer, + *image_transfer); + (*image_transfer)->cb_finish((esl_lib_image_transfer_handle_t)(*image_transfer), (*image_transfer)->connection_handle, sc, (*image_transfer)->requested_image_index); } - set_state(*image_transfer, ESL_LIB_IMAGE_TRANSFER_REMOVED, sc, NULL); // Remove transfer esl_lib_memory_free(*image_transfer); } @@ -829,34 +858,39 @@ static void operation_finished(image_transfer_t *image_transfer, sl_status_t sc, bool finish_transfer) { + if (find_image_transfer_by_handle(image_transfer) == ESL_LIB_IMAGE_TRANSFER_INVALID_HANDLE) { + esl_lib_log_it_warning(IT_FMT "OTS operation finished on removed handle, sc = 0x%04x" APP_LOG_NL, + image_transfer, + sc); + return; + } + if (sc == SL_STATUS_OK) { esl_lib_log_it_debug(IT_FMT "OTS operation succeeded, sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, sc); } else { esl_lib_log_it_error(IT_FMT "OTS operation failed, sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, sc); } - if (sc != SL_STATUS_OK && image_transfer->ots_ongoing_command == OTS_COMMAND_OBJECT_TYPE) { - // Send type back - image_transfer->cb_type((esl_lib_image_transfer_handle_t)image_transfer, - image_transfer->connection_handle, - sc, - image_transfer->requested_image_index, - NULL, - 0); - } - image_transfer->ots_state = OTS_STATE_IDLE; image_transfer->ots_ongoing_command = OTS_COMMAND_NONE; - set_state(image_transfer, ESL_LIB_IMAGE_TRANSFER_STATE_IDLE, sc, NULL); - // Send error in case of object type requested + if (sc == SL_STATUS_OK) { + set_state(image_transfer, ESL_LIB_IMAGE_TRANSFER_STATE_IDLE, sc, NULL); + } else { + if (image_transfer->ots_state == OTS_STATE_NOT_INITIALIZED || image_transfer->ots_state == OTS_STATE_INITIALIZED) { + set_state(image_transfer, ESL_LIB_IMAGE_TRANSFER_STATE_NOT_INITIALIZED, sc, NULL); + } else { + set_state(image_transfer, ESL_LIB_IMAGE_TRANSFER_STATE_ERROR, sc, NULL); + } + } + image_transfer->ots_state = OTS_STATE_IDLE; if (finish_transfer) { esl_lib_log_it_debug(IT_FMT "Finishing transfer" APP_LOG_NL, - image_transfer->image_transfer_handle); + image_transfer); image_transfer->cb_finish((esl_lib_image_transfer_handle_t)image_transfer, image_transfer->connection_handle, sc, @@ -880,7 +914,7 @@ static void ots_init(sl_bt_ots_client_handle_t client, if (image_transfer->ots_state == OTS_STATE_NOT_INITIALIZED && result == SL_STATUS_OK) { esl_lib_log_it_debug(IT_FMT "OTS init finished, Reading features" APP_LOG_NL, - image_transfer->image_transfer_handle); + image_transfer); sc = sl_bt_ots_client_read_ots_features(&image_transfer->ots_client); if (sc == SL_STATUS_OK) { // Start timer (with init callback) @@ -896,15 +930,17 @@ static void ots_init(sl_bt_ots_client_handle_t client, gattdb_handles); } else { esl_lib_log_it_error(IT_FMT "Failed to read features, sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, sc); - remove_transfer(&image_transfer, sc, false); + // Send operation finished with error event + operation_finished(image_transfer, SL_STATUS_FAIL, true); } } else { esl_lib_log_it_error(IT_FMT "OTS not initialized, sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, result); - remove_transfer(&image_transfer, result, false); + // Send operation finished with error event + operation_finished(image_transfer, SL_STATUS_INITIALIZATION, true); } } } @@ -923,7 +959,7 @@ static void ots_features(sl_bt_ots_client_handle_t client, &features, sizeof(sl_bt_ots_features_t)); esl_lib_log_it_debug(IT_FMT "OTS features arrived, OACP = 0x%04x , OLCP = 0x%04x , OTS init done" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, image_transfer->ots_server_features.oacp_features, image_transfer->ots_server_features.olcp_features); // Set state to idle. @@ -934,10 +970,10 @@ static void ots_features(sl_bt_ots_client_handle_t client, NULL); } else { esl_lib_log_it_error(IT_FMT "Failed to get OTS features, sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, status); // Error during feature read - remove_transfer(&image_transfer, status, false); + operation_finished(image_transfer, SL_STATUS_FAIL, true); } } } @@ -964,7 +1000,7 @@ static void ots_meta_read(sl_bt_ots_client_handle_t client, && image_transfer->ots_ongoing_command == OTS_COMMAND_OBJECT_TYPE) { if (sc == SL_STATUS_OK) { esl_lib_log_it_debug(IT_FMT "OTS object type arrived, sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, sc); type = parameters->object_type.uuid_data; len = SL_BT_OTS_UUID_SIZE_128; @@ -973,26 +1009,24 @@ static void ots_meta_read(sl_bt_ots_client_handle_t client, } } else { esl_lib_log_it_error(IT_FMT "OTS object type read error, sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, sc); } - // Type read operation finished, also sends the error if present + // Send the type report + image_transfer->cb_type((esl_lib_image_transfer_handle_t)image_transfer, + image_transfer->connection_handle, + sc, + image_transfer->requested_image_index, + type, + len); + // Type read operation finished operation_finished(image_transfer, sc, false); - // Send the type in case of success, - if (sc == SL_STATUS_OK) { - image_transfer->cb_type((esl_lib_image_transfer_handle_t)image_transfer, - image_transfer->connection_handle, - sc, - image_transfer->requested_image_index, - type, - len); - } } else if (event == SL_BT_OTS_OBJECT_METADATA_READ_OBJECT_ID) { if (sc == SL_STATUS_OK) { esl_lib_log_it_debug(IT_FMT "OTS object ID arrived, sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, sc); memcpy(image_transfer->ots_current_object_id.data, parameters->object_id.data, @@ -1002,13 +1036,13 @@ static void ots_meta_read(sl_bt_ots_client_handle_t client, image_transfer->ots_requested_object_id.data, sizeof(image_transfer->ots_requested_object_id.data)) == 0) { esl_lib_log_it_debug(IT_FMT "OTS object ID found, starting operation" APP_LOG_NL, - image_transfer->image_transfer_handle); + image_transfer); // Found the requested object, start the operation. start_requested_operation(image_transfer); } else { esl_lib_log_it_debug(IT_FMT "Object ID does not match, move to next" APP_LOG_NL, - image_transfer->image_transfer_handle); + image_transfer); // Not found the requested object, move to the next object sc = sl_bt_ots_client_olcp_next(&image_transfer->ots_client); if (sc == SL_STATUS_OK) { @@ -1021,7 +1055,7 @@ static void ots_meta_read(sl_bt_ots_client_handle_t client, image_transfer->ots_state = OTS_STATE_NEXT; } else { esl_lib_log_it_error(IT_FMT "Failed to move to next object, sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, sc); // Could not get next, finish transfer if in progress operation_finished(image_transfer, @@ -1031,7 +1065,7 @@ static void ots_meta_read(sl_bt_ots_client_handle_t client, } } else { esl_lib_log_it_error(IT_FMT "OTS Object ID read error, sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, sc); // Read Object ID failed - operation finished operation_finished(image_transfer, @@ -1060,12 +1094,12 @@ static void ots_olcp(sl_bt_ots_client_handle_t client, if ((opcode == SL_BT_OTS_OLCP_OPCODE_FIRST && image_transfer->ots_state == OTS_STATE_FIRST) || (opcode == SL_BT_OTS_OLCP_OPCODE_NEXT && image_transfer->ots_state == OTS_STATE_NEXT)) { esl_lib_log_it_debug(IT_FMT "OTS OLCP FIRST/NEXT operation succeeded" APP_LOG_NL, - image_transfer->image_transfer_handle); + image_transfer); sc = sl_bt_ots_client_read_object_id(&image_transfer->ots_client); if (sc != SL_STATUS_OK) { esl_lib_log_it_error(IT_FMT "OTS Reading object ID failed, sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, sc); // Read ID failed operation_finished(image_transfer, @@ -1073,7 +1107,7 @@ static void ots_olcp(sl_bt_ots_client_handle_t client, image_transfer->ots_ongoing_command == OTS_COMMAND_WRITE); } else { esl_lib_log_it_debug(IT_FMT "OTS Reading object ID started" APP_LOG_NL, - image_transfer->image_transfer_handle); + image_transfer); // Start timer app_timer_start(&image_transfer->timer, TIMEOUT_GATT_MS, @@ -1083,7 +1117,7 @@ static void ots_olcp(sl_bt_ots_client_handle_t client, } } else if (opcode == SL_BT_OTS_OLCP_OPCODE_GO_TO && image_transfer->ots_state == OTS_STATE_GO_TO) { esl_lib_log_it_debug(IT_FMT "OTS OLCP GOTO operation succeeded. Starting requested operation" APP_LOG_NL, - image_transfer->image_transfer_handle); + image_transfer); // Object selected memcpy(&image_transfer->ots_current_object_id, @@ -1098,25 +1132,25 @@ static void ots_olcp(sl_bt_ots_client_handle_t client, if (gatt_status != SL_STATUS_OK) { sc = gatt_status; esl_lib_log_it_error(IT_FMT "OTS OLCP operation failed due to ATT error 0x%04x, sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, response, sc); } else { // Check if no more items in the list if (response == SL_BT_OTS_OLCP_RESPONSE_CODE_SUCCESS) { esl_lib_log_it_debug(IT_FMT "OTS OLCP operation succeeded" APP_LOG_NL, - image_transfer->image_transfer_handle); + image_transfer); sc = SL_STATUS_OK; } else if (response == SL_BT_OTS_OLCP_RESPONSE_CODE_OUT_OF_BOUNDS || response == SL_BT_OTS_OLCP_RESPONSE_CODE_OBJECT_ID_NOT_FOUND) { sc = SL_STATUS_NOT_FOUND; esl_lib_log_it_error(IT_FMT "OTS OLCP operation failed: object not found, sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, sc); } else { sc = SL_STATUS_FAIL; esl_lib_log_it_error(IT_FMT "OTS OLCP operation failed due unknown error, sc = 0x%04x, response = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, sc, response); } @@ -1145,7 +1179,7 @@ static void ots_oacp(sl_bt_ots_client_handle_t client, // Stop timer app_timer_stop(&image_transfer->timer); esl_lib_log_it_error(IT_FMT "OTS OACP Write operation failed, status = 0x%04x, response = 0x%04x, sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, status, response, sc); @@ -1201,12 +1235,12 @@ static void ots_finished(sl_bt_ots_client_handle_t client, break; } esl_lib_log_it_error(IT_FMT "OTS transfer failed, result = 0x%04x , sc = 0x%04x" APP_LOG_NL, - image_transfer->image_transfer_handle, + image_transfer, result, sc); } else { esl_lib_log_it_debug(IT_FMT "OTS transfer succeeded" APP_LOG_NL, - image_transfer->image_transfer_handle); + image_transfer); } // OACP operation completed @@ -1224,7 +1258,7 @@ static void ots_disconnect(sl_bt_ots_client_handle_t client) // Stop timer on disconnect app_timer_stop(&image_transfer->timer); esl_lib_log_it_debug(IT_FMT "OTS disconnected" APP_LOG_NL, - image_transfer->image_transfer_handle); + image_transfer); sc = SL_STATUS_BT_CTRL_REMOTE_USER_TERMINATED; remove_transfer(&image_transfer, sc, @@ -1237,9 +1271,9 @@ static void init_timeout(app_timer_t *timer, { image_transfer_t *image_transfer = (image_transfer_t *)data; esl_lib_log_it_error(IT_FMT "OTS init timeout" APP_LOG_NL, - image_transfer->image_transfer_handle); - // Remove transfer that could not be initialized - remove_transfer(&image_transfer, SL_STATUS_TIMEOUT, false); + image_transfer); + // Send operation finished with error event + operation_finished(image_transfer, SL_STATUS_INITIALIZATION, false); } static void gatt_timeout(app_timer_t *timer, @@ -1247,11 +1281,9 @@ static void gatt_timeout(app_timer_t *timer, { image_transfer_t *image_transfer = (image_transfer_t *)data; esl_lib_log_it_error(IT_FMT "OTS GATT timeout" APP_LOG_NL, - image_transfer->image_transfer_handle); + image_transfer); // Send operation finished with error event - operation_finished(image_transfer, - SL_STATUS_TIMEOUT, - image_transfer->ots_ongoing_command == OTS_COMMAND_WRITE); + operation_finished(image_transfer, SL_STATUS_TIMEOUT, true); } static void transfer_timeout(app_timer_t *timer, @@ -1259,6 +1291,6 @@ static void transfer_timeout(app_timer_t *timer, { image_transfer_t *image_transfer = (image_transfer_t *)data; esl_lib_log_it_error(IT_FMT "OTS transfer timeout" APP_LOG_NL, - image_transfer->image_transfer_handle); - operation_finished(image_transfer, SL_STATUS_TIMEOUT, true); + image_transfer); + operation_finished(image_transfer, SL_STATUS_TRANSMIT_INCOMPLETE, true); } diff --git a/app/bluetooth/common_host/esl_lib/esl_lib_image_transfer.h b/app/bluetooth/common_host/esl_lib/esl_lib_image_transfer.h index 1fac377cd5..e507bbdaaf 100644 --- a/app/bluetooth/common_host/esl_lib/esl_lib_image_transfer.h +++ b/app/bluetooth/common_host/esl_lib/esl_lib_image_transfer.h @@ -54,6 +54,7 @@ typedef enum { ESL_LIB_IMAGE_TRANSFER_STATE_INIT_IN_PROGRESS, ESL_LIB_IMAGE_TRANSFER_STATE_IDLE, ESL_LIB_IMAGE_TRANSFER_STATE_BUSY, + ESL_LIB_IMAGE_TRANSFER_STATE_ERROR, ESL_LIB_IMAGE_TRANSFER_REMOVED } esl_image_transfer_state_t; @@ -129,6 +130,14 @@ sl_status_t esl_lib_image_transfer_init(uint8_t esl_lib_ots_gattdb_handles_t *gattdb_handles, esl_lib_image_transfer_handle_t *handle_out); +/***************************************************************************//** + * Discard and clanup transfer by handle + * @note Call only if `sl_bt_evt_connection_closed_id` event can't be expected! + * @param[in] handle Pointer to an ESL Image Transfer handle. + * @return Status of the operation + ******************************************************************************/ +sl_status_t esl_lib_image_dump_transfer_by_handle(esl_lib_image_transfer_handle_t *handle); + /***************************************************************************//** * Read object type * @param[in] handle ESL Image Transfer handle. diff --git a/app/bluetooth/common_host/esl_lib/esl_lib_memory.c b/app/bluetooth/common_host/esl_lib/esl_lib_memory.c index d86805169d..bfbb8c6486 100644 --- a/app/bluetooth/common_host/esl_lib/esl_lib_memory.c +++ b/app/bluetooth/common_host/esl_lib/esl_lib_memory.c @@ -78,7 +78,7 @@ void *_esl_lib_malloc(size_t size, const char *file, uint32_t line) // Push it to the list sl_slist_push(&list, &item->node); if (item->file[8] != 'e') { // event list allocations excluded - esl_lib_log_debug(LOG_MODULE, "%8p Size = %zu allocated in %s:%u" APP_LOG_NL, + esl_lib_log_debug(LOG_MODULE, ESL_LIB_LOG_HANDLE_FORMAT " Size = %zu allocated in %s:%u" APP_LOG_NL, item->ptr, item->size, item->file, @@ -99,7 +99,7 @@ void _esl_lib_free(void *ptr, const char *file, uint32_t line) // Remove from the list sl_slist_remove(&list, &item->node); if (item->file[8] != 'e') { // events excluded - esl_lib_log_debug(LOG_MODULE, "%8p Size = %zu freed in %s:%u" APP_LOG_NL, + esl_lib_log_debug(LOG_MODULE, ESL_LIB_LOG_HANDLE_FORMAT " Size = %zu freed in %s:%u" APP_LOG_NL, item->ptr, item->size, item->file, @@ -109,6 +109,11 @@ void _esl_lib_free(void *ptr, const char *file, uint32_t line) free(ptr); // Free list item free(item); + } else { + esl_lib_log_critical(LOG_MODULE, "Unknown free request for " ESL_LIB_LOG_HANDLE_FORMAT " in %s:%u" APP_LOG_NL, + ptr, + file, + line); } } diff --git a/app/bluetooth/common_host/ncp_host/ncp_host.c b/app/bluetooth/common_host/ncp_host/ncp_host.c index 6d9e013288..b53b5b0b6a 100644 --- a/app/bluetooth/common_host/ncp_host/ncp_host.c +++ b/app/bluetooth/common_host/ncp_host/ncp_host.c @@ -83,7 +83,9 @@ static bool enable_security = false; #endif // defined(SECURITY) && SECURITY == 1 static int32_t ncp_host_peek_timeout(uint32_t len, uint32_t timeout); -void ncp_sec_host_command_handler(buf_ncp_host_t *buf); +static void ncp_sec_host_command_handler(buf_ncp_host_t *buf); +static int32_t ncp_host_lazy_peek(void); +static int32_t ncp_host_get_msg(void); /**************************************************************************//** * Initialize NCP connection. @@ -92,7 +94,7 @@ sl_status_t ncp_host_init(void) { sl_status_t sc; - sc = sl_bt_api_initialize_nonblock(ncp_host_tx, ncp_host_rx, ncp_host_peek); + sc = sl_bt_api_initialize_nonblock(ncp_host_tx, ncp_host_rx, ncp_host_lazy_peek); if (sc == SL_STATUS_OK) { sc = host_comm_init(); @@ -163,30 +165,50 @@ void ncp_host_tx(uint32_t len, uint8_t* data) int32_t ncp_host_rx(uint32_t len, uint8_t* data) { int32_t ret; + static uint16_t read_offset = 0; if (buf_ncp_in.len == 0) { - ret = ncp_host_peek(); + ret = ncp_host_get_msg(); + // Finished receiving a brand new, complete NCP message + read_offset = 0; } else { - ret = buf_ncp_in.len; + // NCP host code is still processing the previosuly received message + ret = buf_ncp_in.len - read_offset; } if (ret > 0) { - if (len <= buf_ncp_in.len) { - memcpy(data, buf_ncp_in.buf, len); - buf_ncp_in.len -= len; - memmove(buf_ncp_in.buf, &buf_ncp_in.buf[len], buf_ncp_in.len); + if (len <= ret) { + memcpy(data, &buf_ncp_in.buf[read_offset], len); + read_offset += len; } else { ret = -1; + // Drop seemingly partial messages + buf_ncp_in.len = 0; } } else { + // Reset the length counter until a full message arrives + buf_ncp_in.len = 0; ret = -1; } return ret; } -/**************************************************************************//** - * Peek if readable data exists with timeout option. +/****************************************************************************** + * Check if any data is available in receive buffer, sleep if empty + *****************************************************************************/ +static int32_t ncp_host_lazy_peek(void) +{ + int32_t ret = HOST_COMM_PEEK(); + + if (ret < 1) { + app_sleep_us(PEEK_US_SLEEP); + } + return ret; +} + +/****************************************************************************** + * Check if given amount of data is available in receive buffer within timeout *****************************************************************************/ -int32_t ncp_host_peek_timeout(uint32_t len, uint32_t timeout) +static int32_t ncp_host_peek_timeout(uint32_t len, uint32_t timeout) { int32_t ret; uint32_t timeout_counter = 0; @@ -203,23 +225,20 @@ int32_t ncp_host_peek_timeout(uint32_t len, uint32_t timeout) return ret; } -/**************************************************************************//** - * Peek if readable data exists. +/****************************************************************************** + * Assemble complete BGAPI message from the receive buffer *****************************************************************************/ -int32_t ncp_host_peek(void) +static int32_t ncp_host_get_msg(void) { int32_t msg_len; - msg_len = HOST_COMM_PEEK(); - if (msg_len) { + msg_len = ncp_host_lazy_peek(); + if (msg_len > 0) { int32_t ret; uint8_t msg_header = 0; // Read first byte ret = HOST_COMM_RX(1, &buf_ncp_raw.buf[0]); - if (ret < 0) { - return -1; - } msg_header = (uint8_t)(buf_ncp_raw.buf[0] & 0xf8); msg_len = 256 * (buf_ncp_raw.buf[0] & 0x07); // Get the high bits of the message length // Check if proper ncp header arrived @@ -230,9 +249,6 @@ int32_t ncp_host_peek(void) return -1; } ret = HOST_COMM_RX(1, (void *)&buf_ncp_raw.buf[1]); - if (ret < 0) { - return -1; - } msg_len |= buf_ncp_raw.buf[1]; msg_len += 2; // Check if length will fit to buffer @@ -264,15 +280,15 @@ int32_t ncp_host_peek(void) ncp_sec_host_command_handler(&buf_ncp_in); } #endif // defined(SECURITY) && SECURITY == 1 + } else { + return -1; } - } else { - app_sleep_us(PEEK_US_SLEEP); } return msg_len; } #if defined(SECURITY) && SECURITY == 1 -void ncp_sec_host_command_handler(buf_ncp_host_t *buf) +static void ncp_sec_host_command_handler(buf_ncp_host_t *buf) { uint8_t response[DEFAULT_HOST_BUFLEN]; sl_bt_msg_t *command = NULL; diff --git a/app/bluetooth/common_host/ncp_host/ncp_host.h b/app/bluetooth/common_host/ncp_host/ncp_host.h index 372eaa7b4b..1dc407add5 100644 --- a/app/bluetooth/common_host/ncp_host/ncp_host.h +++ b/app/bluetooth/common_host/ncp_host/ncp_host.h @@ -94,12 +94,4 @@ void ncp_host_tx(uint32_t len, uint8_t *data); * @return Number of bytes read, -1 on error. *****************************************************************************/ int32_t ncp_host_rx(uint32_t len, uint8_t *data); - -/**************************************************************************//** - * Peek if readable data exists. - * - * @return Number of bytes on the buffer, -1 on error. - *****************************************************************************/ -int32_t ncp_host_peek(void); - #endif // NCP_HOST_H diff --git a/app/bluetooth/common_host/ncp_sec/ncp_sec_host.c b/app/bluetooth/common_host/ncp_sec/ncp_sec_host.c index c94e40ff88..c645a1cb51 100644 --- a/app/bluetooth/common_host/ncp_sec/ncp_sec_host.c +++ b/app/bluetooth/common_host/ncp_sec/ncp_sec_host.c @@ -564,6 +564,7 @@ void security_decrypt_packet(char *src, char *dst, unsigned *len) // remove tag and counter value *len = *len - NCP_SEC_PAYLOAD_OVERHEAD; + new_length += 4; //verify counter to prevent replay attacks conn_nonce_t nonce; @@ -591,7 +592,7 @@ void security_decrypt_packet(char *src, char *dst, unsigned *len) auth_data, 7, (uint8_t *)dst, (uint8_t *)src + *len); if (err) { - app_log_warning("Packet decryption failed 0x%x" APP_LOG_NL, err); + app_log_warning("Packet decryption failed 0x%x, len: %u/%u" APP_LOG_NL, err, *len, new_length); *len = 0; return; } diff --git a/app/bluetooth/component_host/ncp_host_bt.mk b/app/bluetooth/component_host/ncp_host_bt.mk index 69aee17ef3..d42e257ded 100644 --- a/app/bluetooth/component_host/ncp_host_bt.mk +++ b/app/bluetooth/component_host/ncp_host_bt.mk @@ -115,5 +115,5 @@ endif ifeq ($(OS), win) # Ws2_32: WinSock library - override LDFLAGS += -lWs2_32 + override LDFLAGS += -lWs2_32 -lcrypt32 endif diff --git a/app/bluetooth/documentation/slBluetooth_docContent.xml b/app/bluetooth/documentation/slBluetooth_docContent.xml index ecbd0c95bd..14249cd402 100644 --- a/app/bluetooth/documentation/slBluetooth_docContent.xml +++ b/app/bluetooth/documentation/slBluetooth_docContent.xml @@ -1,6 +1,6 @@ - + Includes detailed information on using the Gecko Bootloader with Silicon Labs Bluetooth applications. It supplements the general Gecko Bootloader implementation information provided in UG489: Silicon Labs Gecko Bootloader User's Guide. @@ -8,7 +8,7 @@ - + Describes the Wi-Fi impact on Bluetooth and methods to improve Bluetooth coexistence with Wi-Fi. Explains design considerations to improve coexistence without direct interaction between Bluetooth and Wi-Fi radios. These techniques are applicable to the EFR32MGx and EFR32BGx series. Discusses the Silicon Labs Packet Traffic Arbitration (PTA) support to coordinate 2.4GHz RF traffic for co-located Bluetooth and Wi-Fi radios. @@ -16,7 +16,7 @@ - + Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. @@ -24,7 +24,7 @@ - + Describes how to lock and unlock the debug access of EFR32 Gecko Series 2 devices. Many aspects of the debug access, including the secure debug unlock are described. The Debug Challenge Interface (DCI) and Secure Engine (SE) Mailbox Interface for locking and unlocking debug access are also included. @@ -32,7 +32,7 @@ - + Contains detailed information on configuring and using the Secure Boot with hardware Root of Trust and Secure Loader on Series 2 devices, including how to provision the signing key. This is a companion document to UG489: Silicon Labs Gecko Bootloader User's Guide. @@ -40,7 +40,7 @@ - + Details on programming, provisioning, and configuring Series 2 devices in production environments. Covers Secure Engine Subsystem of Series 2 devices, which runs easily upgradeable Secure Engine (SE) or Virtual Secure Engine (VSE) firmware. @@ -48,14 +48,14 @@ - + Describes how to measure the power consumption of EFR32BG devices running the Bluetooth i-Beacon example. For general instructions, see AN969: Measuring Power Consumption in Wireless Gecko Devices, available on silabs.com. - + How to program, provision, and configure the anti-tamper module on EFR32 Series 2 devices with Secure Vault. @@ -63,7 +63,7 @@ - + Describes how to configure the NCP target and how to program the NCP host when using the Bluetooth Stack in Network Co-Processor mode @@ -71,14 +71,14 @@ - + Describes how to integrate a v3.x Silicon Labs Bluetooth application with an RTOS, and demonstrate how a time- and event-driven application can be run in parallel with the Bluetooth stack. - + Reviews performing radio frequency physical layer evaluation with EFR32BG SoCs and BGM modules using the Direct Test Mode protocol in Bluetooth SDK v3.x. @@ -86,7 +86,7 @@ - + How to authenticate an EFR32 Series 2 device with Secure Vault, using secure device certificates and signatures. @@ -94,14 +94,14 @@ - + Provides details on how to develop a dynamic multiprotocol application running Bluetooth and a proprietary protocol on RAIL in GSDK v3.x. - + How to securely "wrap" keys in EFR32 Series 2 devices with Secure Vault, so they can be stored in non-volatile storage. @@ -109,28 +109,28 @@ - + Describes the sample applications provided to demonstrate the directing finding capabilities of Bluetooth 5.1. Angle of Arrival (AoA) estimation is demonstrated with the use of Silicon Labs' Real Time Locating (RTL) library. These techniques are applicable to the EFR32MGx and EFR32BGx series. - + Bluetooth 5.1 makes it possible to send Constant Tone Extensions (CTEs) in Bluetooth packets on which phase measurements can be done. This guide is for those implementing custom applications that take advantage of phase measurement and antenna switching capabilites. - + Provides details on designing Bluetooth Low Energy applications with security and privacy in mind. - + Describes how to provision and configure Series 2 devices through the DCI and SWD. @@ -138,14 +138,14 @@ - + Includes the results of the interoperability testing of Silicon Labs' ICs and Bluetooth Low Energy stack with Android and iOS smart phones. - + Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. @@ -153,7 +153,7 @@ - + Describes using Simplicity Studio 5's Network Analyzer to debug Bluetooth Mesh and Low Energy applications. It can be read jointly with AN958: Debugging and Programming Interfaces for Customer Designs for more information on using Packet Trace Interface with custom hardware. @@ -161,7 +161,7 @@ - + Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. @@ -169,14 +169,14 @@ - + Gives a short overview of the standard Host Controller Interface (HCI) and how to use it with a Silicon Labs Bluetooth LE controller. - + Describes how to run any combination of Zigbee EmberZNet, OpenThread, and Bluetooth networking stacks on a Linux host processor, interfacing with a single EFR32 Radio Co-processor (RCP) with multiprotocol and multi-PAN support, as well as how to run the Zigbee stack on the EFR32 as a network co-processor (NCP) alongside the OpenThread RCP. @@ -184,21 +184,21 @@ - + Summarizes Amazon FreeRTOS components and sample applications, and explains how to use the examples to communicate with the Amazon Web Services (AWS) cloud with a smart phone app. - + Describes how to exploit the different features of Bluetooth technology to achieve the minimum possible energy consumption for a given use case. - + Covers the basics of ARMv8-M TrustZone, describes how TrustZone is implemented on Series 2 devices, and provides application examples. @@ -206,14 +206,14 @@ - + Describes the theoretical background of certificate-based authentication and pairing, and demonstrates the usage of the related sample applications that can be found in the Silicon Labs Bluetooth SDK. - + Describes how to run a combination of Zigbee, Bluetooth, and OpenThread networking stacks and the Zigbee application layer on a System-on-Chip (SoC). @@ -221,56 +221,56 @@ - + Provides an overview and hyperlinks to all packaged documentation. - + Describes the differences between using Bluetooth SDK v2.x in Simplicity Studio 4 and using Bluetooth SDK v3.x in Simplicity Studio 5. Outlines the steps needed to migrate a v2.x project to v3.x. - + Describes the software components provided by Silicon Labs to support Direction Finding (DF) and provides instructions on how to start developing your own application. - + Contains a comprehensive list of APIs used to interface to the Silicon Labs Bluetooth Real-Time Locating Library. - + Contains a comprehensive list of APIs used to interface to the Silicon Labs Bluetooth stack. - + Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the Silicon Labs Bluetooth SDK and associated utilities, including added/deleted/deprecated features/API, and lists fixed and known issues. - + Discusses the latest changes to the The Real-Time Locating (RTL) library, including added/deleted/deprecated APIs, and lists fixed and known issues. - + A detailed overview of the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform includes EMLIB, EMDRV, RAIL Library, NVM3, and the component-based infrastructure. @@ -278,7 +278,7 @@ - + Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. @@ -286,7 +286,7 @@ - + Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader as well as legacy Ember and Bluetooth bootloaders, and describes the file formats used by each. @@ -294,7 +294,7 @@ - + Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: Simulated EEPROM, PS Store, and NVM3. @@ -302,14 +302,14 @@ - + Offers an overview for those new to the Bluetooth low energy technology. - + Describes the four multiprotocol modes, discusses considerations when selecting protocols for multiprotocol implementations, and reviews the Radio Scheduler, a required component of a dynamic multiprotocol solution. @@ -317,7 +317,7 @@ - + Describes methods to improve the coexistence of 2.4 GHz IEEE 802.11b/g/n Wi-Fi and other 2.4 GHz radios such as Bluetooth, Bluetooth Mesh, Bluetooth Low Energy, and IEEE 802.15.4-based radios such as Zigbee and OpenThread. @@ -325,14 +325,14 @@ - + Explains the basics of Bluetooth Angle of Arrival (AoA) and Angle of Departure (AoD) direction finding technologies and provides the theory behind estimating angle of arrival. - + Reviews using this XML-based mark-up language to describe the Bluetooth GATT database, configure access and security properties, and include the GATT database as part of the firmware. @@ -340,7 +340,7 @@ - + Describes how and when to use Simplicity Commander's Command-Line Interface. @@ -348,7 +348,7 @@ - + Describes how to implement a dynamic multiprotocol solution. @@ -356,14 +356,14 @@ - + Covers the Bluetooth stack v7.x architecture, application development flow, using the MCU core and peripherals, stack configuration options, and stack resource usage. - + Describes how to use the Simplicity Studio 5 GATT Configurator, an intuitive interface providing access to all the Profiles, Services, Characteristics, and Descriptors as defined in the Bluetooth specification. @@ -371,7 +371,7 @@ - + Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. @@ -379,7 +379,7 @@ - + The Bluetooth Direction Finding Tool Suite is meant to ease development with the Silicon Labs' RTL library. It provides multiple tools to configure the system, and also helps the development with analyzer tools that calculate many output parameters from the observed IQ samples. diff --git a/app/bluetooth/esf.properties b/app/bluetooth/esf.properties index b2e0b77d1e..0b104c14ea 100644 --- a/app/bluetooth/esf.properties +++ b/app/bluetooth/esf.properties @@ -3,8 +3,8 @@ id=com.silabs.stack.ble label=Bluetooth SDK description=Bluetooth Software Development Kit -version=7.0.1.0 -prop.subLabel=Bluetooth\\ 7.0.1 +version=7.1.0.0 +prop.subLabel=Bluetooth\\ 7.1.0 # Default compatibility of the BLE SDK prop.boardCompatibility=.* diff --git a/app/bluetooth/example/bt_abr_ncp_initiator/app.c b/app/bluetooth/example/bt_abr_ncp_initiator/app.c index a817a93b67..eea1b1ec19 100644 --- a/app/bluetooth/example/bt_abr_ncp_initiator/app.c +++ b/app/bluetooth/example/bt_abr_ncp_initiator/app.c @@ -44,6 +44,9 @@ #define ANTENNA_PIN0 0 #define ANTENNA_PIN1 1 #define APPLY_ANTENNA_PIN(pin, value) ((value) ? GPIO_PinOutSet(ANTENNA_PORT, pin) : GPIO_PinOutClear(ANTENNA_PORT, pin)) +#ifndef SL_BOARD_NAME +#define SL_BOARD_NAME "UNKNOWN!" +#endif // SL_BOARD_NAME static void ans_set_GPIOS_for_antenna(uint8_t); diff --git a/app/bluetooth/example/bt_ncp/bt_ncp_esl_ap.slcp b/app/bluetooth/example/bt_ncp/bt_ncp_esl_ap.slcp index 4359745797..d83964f70e 100644 --- a/app/bluetooth/example/bt_ncp/bt_ncp_esl_ap.slcp +++ b/app/bluetooth/example/bt_ncp/bt_ncp_esl_ap.slcp @@ -49,6 +49,7 @@ requires: - name: bluetooth_feature_periodic_advertiser - name: bluetooth_feature_connection_phy_update - name: bluetooth_feature_external_bonding_database + - name: bluetooth_feature_connection_pawr_scheduling - name: bluetooth_feature_use_accurate_api_address_types source: @@ -80,9 +81,9 @@ configuration: - name: SL_NCP_CMD_BUF_SIZE value: "288" - name: SL_NCP_EVT_BUF_SIZE - value: "260" + value: "264" - name: SL_SIMPLE_COM_TX_BUF_SIZE - value: "260" + value: "264" - name: SL_SIMPLE_COM_RX_BUF_SIZE value: "288" - name: SL_NCP_CMD_TIMEOUT_MS @@ -99,6 +100,8 @@ configuration: value: "3" - name: SL_BT_CONFIG_MAX_PERIODIC_ADVERTISERS value: "2" + - name: SL_BT_CONFIG_MAX_ADVERTISED_DATA_LENGTH_HINT + value: "74" - name: SL_BT_CONFIG_MAX_PAWR_ADVERTISERS value: "2" - name: SL_DEVICE_INIT_LFRCO_PRECISION diff --git a/app/bluetooth/example/bt_soc_esl_tag/app.c b/app/bluetooth/example/bt_soc_esl_tag/app.c index 5aef0d8bde..340259cfef 100644 --- a/app/bluetooth/example/bt_soc_esl_tag/app.c +++ b/app/bluetooth/example/bt_soc_esl_tag/app.c @@ -206,14 +206,14 @@ static void sw_pwm_led_off(led_sw_pwm_t *instance) } #endif // gattdb_esl_led_info +#ifdef SL_CATALOG_SIMPLE_LED_LED0_PRESENT // Power manager callback with some LED feedback static void pm_callback(sl_power_manager_em_t from, sl_power_manager_em_t to) { (void)from; - - #ifdef SL_CATALOG_SIMPLE_LED_LED0_PRESENT uint8_t basic_state = esl_core_get_basic_state_bit(ESL_BASIC_STATE_SYNCHRONIZED_BIT); + switch (to) { case SL_POWER_MANAGER_EM0: if (led0_feedback_enabled) { @@ -243,9 +243,6 @@ static void pm_callback(sl_power_manager_em_t from, default: break; } - #else // SL_CATALOG_SIMPLE_LED_LED0_PRESENT - (void)to; - #endif // SL_CATALOG_SIMPLE_LED_LED0_PRESENT } static sl_power_manager_em_transition_event_handle_t event_handle; @@ -254,14 +251,21 @@ static sl_power_manager_em_transition_event_info_t event_info = { | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM0, .on_event = pm_callback, }; +#endif // SL_CATALOG_SIMPLE_LED_LED0_PRESENT /**************************************************************************//** * Application Init. *****************************************************************************/ SL_WEAK void app_init(void) { +#ifdef SL_CATALOG_SIMPLE_LED_LED0_PRESENT + // Provide optical feedback of the ESL internal status through led 0 instance + // Attention! Enable for debugging purposes only, as the vast increase in EM2 + // wake-up time can increase the average power consumption of the synchronized + // ESL by up to 3uAh! sl_power_manager_init(); sl_power_manager_subscribe_em_transition_event(&event_handle, &event_info); +#endif // SL_CATALOG_SIMPLE_LED_LED0_PRESENT ///////////////////////////////////////////////////////////////////////////// // Put your additional application init code here! // @@ -541,14 +545,12 @@ sl_status_t esl_sensor_custom_read(uint8_t index, void esl_core_unassociate_callback(void) { - uint8_t device_index; - sl_bt_esl_log(ESL_LOG_COMPONENT_APP, ESL_LOG_LEVEL_INFO, "Execute unassociate callback"); #ifdef gattdb_esl_led_info - device_index = esl_led_get_count(); + uint8_t device_index = esl_led_get_count(); // disable all available LED on board while (device_index--) { diff --git a/app/bluetooth/example/bt_soc_ibeacon/app.c b/app/bluetooth/example/bt_soc_ibeacon/app.c index c062027e52..6dfa83bd81 100644 --- a/app/bluetooth/example/bt_soc_ibeacon/app.c +++ b/app/bluetooth/example/bt_soc_ibeacon/app.c @@ -3,7 +3,7 @@ * @brief Core application logic. ******************************************************************************* * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -28,6 +28,7 @@ * ******************************************************************************/ +#include "sl_common.h" #include "sl_bluetooth.h" #include "app_assert.h" #include "app.h" diff --git a/app/bluetooth/example/bt_soc_voice/voice.c b/app/bluetooth/example/bt_soc_voice/voice.c index f77f45e884..437d68962d 100644 --- a/app/bluetooth/example/bt_soc_voice/voice.c +++ b/app/bluetooth/example/bt_soc_voice/voice.c @@ -3,7 +3,7 @@ * @brief Voice transmission ******************************************************************************* * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -27,10 +27,11 @@ * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ -// Define module name for Power Manager debuging feature. +// Define module name for Power Manager debugging feature. #define CURRENT_MODULE_NAME "APP_BLUETOOTH_EXAMPLE_SOC_VOICE" #include +#include "sl_common.h" #include "sl_power_manager.h" #include "sl_board_control.h" #include "app_assert.h" diff --git a/app/bluetooth/example_host/bt_host_esl_ap/ap_cli.py b/app/bluetooth/example_host/bt_host_esl_ap/ap_cli.py index 0cc00a3b21..c5e5b861b8 100644 --- a/app/bluetooth/example_host/bt_host_esl_ap/ap_cli.py +++ b/app/bluetooth/example_host/bt_host_esl_ap/ap_cli.py @@ -642,6 +642,9 @@ def arg_image_update(self): image_update 1 "/user/home/path with space/img.jpg" all Use the 'all' keyword as special address to send the same image to slot 1 on all connected ESLs. + + image_update 0 *qrcode all + To send unique QR codes to all connected tags for use with ESL Demo, enter "*qrcode" instead of a valid image file path. ''') parser_image_update.add_argument('image_index', type=int, help="Image storage index of the ESL tag to be updated.") parser_image_update.add_argument('imagefile_path', type=str, help="Relative or full path to the selected image file. Use quotation marks if the path contains spaces.") @@ -666,13 +669,15 @@ def do_image_update(self, arg): label = None rotation = None cropfit = False + filename = None if arg.image_index in range(0,256): image_index = arg.image_index else: self.log.error("Image index must be between 0 and 255") input_error = True - filename = arg.imagefile_path + if arg.imagefile_path != "*qrcode": # Check if this is not the specific use case for the ESL demo + filename = arg.imagefile_path if arg.raw: raw_img = True if arg.display_index is not None: diff --git a/app/bluetooth/example_host/bt_host_esl_ap/ap_config.py b/app/bluetooth/example_host/bt_host_esl_ap/ap_config.py index 22fb1e17de..b083bc46f9 100644 --- a/app/bluetooth/example_host/bt_host_esl_ap/ap_config.py +++ b/app/bluetooth/example_host/bt_host_esl_ap/ap_config.py @@ -45,7 +45,7 @@ ESL_CMD_MAX_PENDING_CONNECTION_REQUEST_COUNT = 2 # Tags in a group in automated mode addressing -ESL_MAX_TAGS_IN_AUTO_GROUP = 16 +ESL_MAX_TAGS_IN_AUTO_GROUP = 32 # Default RSSI threshold in dBm RSSI_THRESHOLD = -60 diff --git a/app/bluetooth/example_host/bt_host_esl_ap/ap_core.py b/app/bluetooth/example_host/bt_host_esl_ap/ap_core.py index b84c8def43..efc58653e1 100644 --- a/app/bluetooth/example_host/bt_host_esl_ap/ap_core.py +++ b/app/bluetooth/example_host/bt_host_esl_ap/ap_core.py @@ -41,6 +41,8 @@ from esl_tag_db import TagDB from ap_ead import KeyMaterial, EAD from esl_command import ESLCommand +from qrcode_generator import generate_qrcode +from io import BytesIO import esl_key_lib import esl_lib import esl_lib_wrapper as elw @@ -377,6 +379,7 @@ def ap_imageupdate(self, image_index, file, raw=False, display_ind=None, label=N - label Label to be printed as an overlay to the image - rotation Clockwise (cw), Counter-clockwise (ccw), flip """ + qr_request = False # If image file is from console, check validity if isinstance(file, str) and not self.controller_command: self.raw_image = b"" @@ -421,8 +424,20 @@ def ap_imageupdate(self, image_index, file, raw=False, display_ind=None, label=N self.notify_controller(CCMD_REQUEST_DATA, CONTROLLER_COMMAND_SUCCESS, REQUEST_IMAGE_DATA_HEADER, self.image_data_offset, REQUEST_IMAGE_DATA_RESERVED) return + if file is None and len(tags_to_update) != 0: + self.log.info("QR code generation requested for %d number of tags to image slot %d", len(tags_to_update), image_index) + qr_request = True + for tag in tags_to_update: try: + if qr_request: + # Create Silabs' ESL Demo specific command encoded into a QR code + _, file = generate_qrcode(f"connect {str(tag.ble_address).partition(',')[0]}", 128, 128) + # Convert to byte stream as if sent from demo controller + img_byte_arr = BytesIO() + file.save(img_byte_arr, format='PNG') + # Each tag will have its own, unique QR now as byte stream input + file = img_byte_arr.getvalue() tag.image_update(image_index, file, raw, display_ind, label, rotation, cropfit) self.log.info("Image update started for tag at %s to image slot %d", tag.ble_address, image_index) except ImageUpdateFailed as ex: @@ -1237,7 +1252,7 @@ def esl_event_error(self, evt: esl_lib.EventError): if not tag.blocked: self.log.warning("ESL at address %s has been blocked due to unsuccessful connection attempt(s).", evt.node_id) tag.block(elw.ESL_LIB_STATUS_BONDING_FAILED) - elif evt.sl_status == elw.SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_BY_LOCAL_HOST and evt.data == elw.ESL_LIB_CONNECTION_STATE_ESL_DISCOVERY: + elif evt.sl_status == elw.SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_BY_LOCAL_HOST and (evt.data == elw.ESL_LIB_CONNECTION_STATE_ESL_DISCOVERY or evt.data == elw.ESL_LIB_CONNECTION_STATE_SERVICE_DISCOVERY): if tag.blocked: self.key_db.delete_ltk(tag.ble_address) # remove key of ESLs which are violating the spec (that is, which are lack of any mandatory GATT entries) self.log.debug("Bonding for ESL at address %s deleted due to ESL Profile/Service violation.", tag.ble_address) @@ -1272,7 +1287,11 @@ def esl_event_error(self, evt: esl_lib.EventError): if tag is not None and tag.provisioned and not tag.advertising: self.log.debug("Check if Tag at address %s got synchronized despite the connection closing timeout.", tag.ble_address) self.ap_ping(tag.esl_id, tag.group_id) # Special edge case in which the synced flag may not be set after disconnection -> check if tag is synced - + elif evt.lib_status == elw.ESL_LIB_STATUS_CONN_DISCOVERY_FAILED and evt.sl_status == elw.SL_STATUS_BT_ATT_REQUEST_NOT_SUPPORTED and evt.data == elw.ESL_LIB_CONNECTION_STATE_SERVICE_DISCOVERY: + tag = self.tag_db.find(evt.node_id) + if tag is not None and not tag.blocked: + self.log.warning("ESL at address %s has been blocked due to missing mandatory service!", evt.node_id) + tag.block(evt.lib_status) def esl_event_image_type(self, evt: esl_lib.EventImageType): """ ESL event handler """ # Cache image type @@ -1333,7 +1352,7 @@ def auto_esl_event_tag_found(self, evt: esl_lib.EventTagFound): if tag is not None and tag.state == TagState.IDLE: if tag.advertising: if self.pawr_active and not tag.blocked: - self.check_address_list() + self.check_address_list(tag) elif not self.pawr_active: self.log.error("ESL tag cannot be synchronized because PAwR is not started!") self.log.info("Please re-start auto mode with command: 'mode auto' to recover.") @@ -1369,11 +1388,14 @@ def auto_esl_event_connection_opened(self, evt: esl_lib.EventConnectionOpened): self.log.warning("AUTO MODE TEMPORARILY CHANGED TO MANUAL!") self.cmd_mode = self.auto_override self.set_mode_handlers() - elif tag is not None and tag.provisioned: # we remain in auto mode, so aviod stuck connected in special case below - if tag.max_image_index is not None and tag.has_image_transfer and IMAGE_MAX_AUTO_UPLOAD_COUNT and tag.auto_image_count < min((tag.max_image_index + 1), IMAGE_MAX_AUTO_UPLOAD_COUNT): - self.upload_auto_image((tag.auto_image_count % len(self.image_files)), tag) - else: - self.ap_update_complete(tag.esl_id, tag.group_id) + elif tag is not None: + if evt.status != elw.SL_STATUS_OK: + self.disconnect(tag) # auto mode can't do anything with a Tag that is connected with failure + elif tag.provisioned: # we remain in auto mode, so aviod stuck connected in special case below + if tag.max_image_index is not None and tag.has_image_transfer and IMAGE_MAX_AUTO_UPLOAD_COUNT and tag.auto_image_count < min((tag.max_image_index + 1), IMAGE_MAX_AUTO_UPLOAD_COUNT): + self.upload_auto_image((tag.auto_image_count % len(self.image_files)), tag) + else: + self.ap_update_complete(tag.esl_id, tag.group_id) def auto_esl_event_tag_info(self, evt: esl_lib.EventTagInfo): """ ESL event handler in auto mode """ @@ -1510,7 +1532,13 @@ def demo_ap_control_status(self, status: int): def demo_esl_event_connection_opened(self, evt: esl_lib.EventConnectionOpened): """ ESL event handler in demo mode """ if self.controller_command != None and not self.demo_auto_reconfigure: - self.notify_controller(self.controller_command,CONTROLLER_COMMAND_SUCCESS) + if (evt.status == elw.SL_STATUS_OK): + self.notify_controller(self.controller_command,CONTROLLER_COMMAND_SUCCESS) + else: + self.notify_controller(self.controller_command,CONTROLLER_COMMAND_FAIL) + tag = self.tag_db.find(evt.address) + if tag is not None: + self.disconnect(tag) def demo_esl_event_tag_found(self, evt: esl_lib.EventTagFound): """ ESL event handler in demo mode """ @@ -1528,7 +1556,8 @@ def demo_esl_event_configure_tag_response(self, evt: esl_lib.EventConfigureTagRe def demo_esl_event_connection_closed(self, evt: esl_lib.EventConnectionClosed): """ ESL event handler in demo mode """ - self.demo_auto_reconfigure = False + if self.demo_auto_reconfigure and len(self.tag_db.list_state((TagState.CONNECTED, TagState.CONNECTING))) == 0: + self.demo_auto_reconfigure = False if self.controller_command == CCMD_DISCONNECT: self.notify_controller(self.controller_command, CONTROLLER_COMMAND_SUCCESS) elif self.controller_command != None: @@ -1557,15 +1586,19 @@ def revert_auto_mode(self): self.log.warning("REVERT TO AUTO MODE!") self.set_mode_handlers() - def check_address_list(self): - """ Check address list """ + def check_address_list(self, target = None): # no specific tag by default + """ Check address list, or try connect to particular tag """ if self.pawr_active and self.bonding_finished and len(self.tag_db.list_state(TagState.CONNECTING)) < ESL_CMD_MAX_PENDING_CONNECTION_REQUEST_COUNT: - self.log.info("Checking for next advertising ESL") - # Advertising IDLE state tags those are not blocked - tag_list = [tag for tag in self.tag_db.list_state(TagState.IDLE) if not tag.blocked and tag.advertising] + if target is None: + self.log.info("Checking for next advertising ESL") + # Advertising IDLE state tags those are not blocked + tag_list = [tag for tag in self.tag_db.list_state(TagState.IDLE) if not tag.blocked and tag.advertising] + else: + self.log.info("Initiate connection to ESL at %s address.", target.ble_address) + tag_list = [target] if len(tag_list) > 0: - tag = tag_list[0] if not self.max_conn_count_reached: + tag = tag_list[random.randint(0, len(tag_list) - 1)] # chosing randomly helps to cope with netwokrs that include erroneous tags self.bonding_finished = False self.connect(tag) if self.auto_config_start_time is None: @@ -2049,6 +2082,10 @@ def route_command(self, esl_id, group_id, data, force_pawr=False): tag = active_tag if tag is None: + # Check if the current PAwR has the proper amount of subevents for the group request + if (group_id >= self.subevent_count): + self.log.error("Sending to group %d is impossible because there are only %d subevents in current PAwR train!", group_id, self.subevent_count) + return self.queue_pawr_command(group_id, data) else: self.send_cp_command(tag, data) diff --git a/app/bluetooth/example_host/bt_host_esl_ap/ap_logger.py b/app/bluetooth/example_host/bt_host_esl_ap/ap_logger.py index 5524e6283a..60e7234bd6 100644 --- a/app/bluetooth/example_host/bt_host_esl_ap/ap_logger.py +++ b/app/bluetooth/example_host/bt_host_esl_ap/ap_logger.py @@ -60,7 +60,7 @@ def log(*args, _half_indent_log :bool=False, **kwargs): ''' Print with 1 tab + 1 whitespace indentation ''' args = [arg.replace('\n', '\n\t ') if isinstance(arg, str) else arg for arg in args] with lock: - print('\t' if not _half_indent_log else 3*' ', *args, file=sys.stdout if stdout else sys.stderr, **kwargs) + print('\t' if not _half_indent_log else 3*' ', *args, file=sys.stdout if stdout else sys.stderr, flush=True, **kwargs) class StreamHandler(logging.StreamHandler): def __init__(self): diff --git a/app/bluetooth/example_host/bt_host_esl_ap/esl_lib.py b/app/bluetooth/example_host/bt_host_esl_ap/esl_lib.py index 2a177640a0..b7357a053d 100644 --- a/app/bluetooth/example_host/bt_host_esl_ap/esl_lib.py +++ b/app/bluetooth/example_host/bt_host_esl_ap/esl_lib.py @@ -84,6 +84,10 @@ def get_enum(prefix, index): except KeyError: return f'Unknown {index} ({hex(index)})' +def get_sl_status_str(index): + '''Return string for an sl_status_t index''' + return get_enum('SL_STATUS_', index) + def event_factory(evt_code: elw.esl_lib_evt_type_t, evt_data: elw.esl_lib_evt_data_t): '''Transform ctype object to specific class instance''' evt_class_list = [ @@ -260,7 +264,7 @@ def __init__(self, evt_data: elw.esl_lib_evt_data_t): def __repr__(self) -> str: type_str = get_enum('ESL_LIB_DATA_TYPE_', self.type) - status_str = get_enum('SL_STATUS_', self.status) + status_str = get_sl_status_str(self.status) return f'{self.evt_code}, {self.connection_handle}, {type_str}, {status_str}' class EventControlPointResponse(): @@ -273,7 +277,7 @@ def __init__(self, evt_data: elw.esl_lib_evt_data_t): self.data_sent = array_to_bytes(evt_data.evt_control_point_response.data_sent) def __repr__(self) -> str: - status_str = get_enum('SL_STATUS_', self.status) + status_str = get_sl_status_str(self.status) return f'{self.evt_code}, {self.connection_handle}, {status_str}, {self.data_sent.hex()}' class EventControlPointNotification(): @@ -295,10 +299,12 @@ def __init__(self, evt_data: elw.esl_lib_evt_data_t): self.connection_handle = ConnectionHandle(evt_data.evt_connection_opened.connection_handle) self.address = Address.from_ctype(evt_data.evt_connection_opened.address) self.gattdb_handles = elw.esl_lib_gattdb_handles_t.from_buffer_copy(evt_data.evt_connection_opened.gattdb_handles) + self.status = evt_data.evt_connection_opened.status def __repr__(self) -> str: - gattdb_str = f'[{self.gattdb_handles.services.esl}, {self.gattdb_handles.services.ots}, {self.gattdb_handles.services.dis}]' - return f'{self.evt_code}, {self.connection_handle}, {self.address}, {gattdb_str}' + gattdb_str = f'[{hex(self.gattdb_handles.services.esl)}, {hex(self.gattdb_handles.services.ots)}, {hex(self.gattdb_handles.services.dis)}]' + status_str = get_sl_status_str(self.status) + return f'{self.evt_code}, {self.connection_handle}, {self.address}, {status_str}, {gattdb_str}' class EventConnectionRetry(): '''Wrapper for esl_lib_evt_connection_retry_t''' @@ -312,7 +318,7 @@ def __init__(self, evt_data: elw.esl_lib_evt_data_t): self.retries_left = evt_data.evt_connection_retry.retries_left def __repr__(self) -> str: - reason_str = get_enum('SL_STATUS_', self.reason) + reason_str = get_sl_status_str(self.reason) state_str = get_enum('ESL_LIB_CONNECTION_STATE_',self.connection_state) return f'{self.evt_code}, {self.connection_handle}, {reason_str}, {state_str}, {self.address}, {self.retries_left}' @@ -326,7 +332,7 @@ def __init__(self, evt_data: elw.esl_lib_evt_data_t): self.reason = evt_data.evt_connection_closed.reason def __repr__(self) -> str: - reason_str = get_enum('SL_STATUS_', self.reason) + reason_str = get_sl_status_str(self.reason) return f'{self.evt_code}, {self.connection_handle}, {self.address}, {reason_str}' class EventBondingData(): @@ -362,7 +368,7 @@ def __init__(self, evt_data: elw.esl_lib_evt_data_t): self.status = evt_data.evt_image_transfer_finished.status def __repr__(self) -> str: - status_str = get_enum('SL_STATUS_', self.status) + status_str = get_sl_status_str(self.status) return f'{self.evt_code}, {self.connection_handle}, {self.img_index}, {status_str}' class EventImageType(): @@ -432,7 +438,7 @@ def __init__(self, evt_data: elw.esl_lib_evt_data_t): def __repr__(self) -> str: lib_status_str = get_enum('ESL_LIB_STATUS_', self.lib_status) - sl_status_str = get_enum('SL_STATUS_', self.sl_status) + sl_status_str = get_sl_status_str(self.sl_status) try: if isinstance(self.node_id, ConnectionHandle) or isinstance(self.node_id, (Address)): # Connection handle node ID type @@ -534,7 +540,7 @@ def _serialize_command(self, command, args=None): except BrokenPipeError as err: raise CommandFailedError('Lib process terminated unexpectedly') from err if result[0]: - raise CommandFailedError(f'{command[1:]} failed with result: {get_enum("SL_STATUS_", result[0])}', result[0]) + raise CommandFailedError(f'{command[1:]} failed with result: {get_sl_status_str(result[0])}', result[0]) return result def stop(self, timeout=3): diff --git a/app/bluetooth/example_host/bt_host_esl_ap/esl_tag.py b/app/bluetooth/example_host/bt_host_esl_ap/esl_tag.py index c2f912af3f..4ddd397804 100644 --- a/app/bluetooth/example_host/bt_host_esl_ap/esl_tag.py +++ b/app/bluetooth/example_host/bt_host_esl_ap/esl_tag.py @@ -545,6 +545,10 @@ def get_info(self): info += f" Product_ID: {self.pnp_product_id:#x} Product_version: {self.pnp_product_version:#x}" else: info += "Not available" + + if self.serial_number is not None: + info += f"\n{'Serial Number:':{justify_column}}" + info += str(self.serial_number) info += f"\n{'Last status:':{justify_column}}" bs_string = ", ".join([value for key, value in BASIC_STATE_STRINGS.items() if self.basic_state_flags & key]) @@ -564,20 +568,23 @@ def handle_event(self, evt): if evt.address == self.ble_address: if self._connection_timer.is_alive(): self._connection_timer.cancel() + if self._advertising_timer.is_alive(): + self._advertising_timer.cancel() + self._advertising = False self._past_timer.cancel() self._past_initiated = False self.connection_handle = evt.connection_handle self.gattdb_handles = evt.gattdb_handles self.pending_unassociate = False + if evt.status != elw.SL_STATUS_OK: + self.log.error("Tag at address %s connected with failure: %s", self.ble_address, esl_lib.get_sl_status_str(evt.status)) + return if not self.provisioned: self.log.info("Reading tag information from address %s", self.ble_address) self.get_tag_info() else: self.log.info("Tag info already available, skipping discovery for %s", self.ble_address) - if self._advertising_timer.is_alive(): - self._advertising_timer.cancel() - self._advertising = False if self.esl_address is None: self.log.info("Registering ESL Tag at BLE address: %s", self.ble_address) if self.provisioned: @@ -595,14 +602,14 @@ def handle_event(self, evt): self._connection_timer.start() self._advertising = True # necessary step for any connect requests to undetected advertisers! self.log.warning( - "Tag at BLE address: %s reconnecting, reason: %s, %s retries left: %d", + "Reconnect to %s addr., reason: %s, %s, %d more left", self.ble_address, esl_lib.get_enum("ESL_LIB_CONNECTION_STATE_", evt.connection_state), - esl_lib.get_enum("SL_STATUS_", evt.reason), + esl_lib.get_sl_status_str(evt.reason), evt.retries_left, ) elif isinstance(evt, esl_lib.EventConnectionClosed): - if evt.connection_handle == self.connection_handle: + if evt.connection_handle == self.connection_handle or evt.address == self.ble_address: self._past_timer.cancel() self.connection_handle = None self._past_initiated = False @@ -615,7 +622,7 @@ def handle_event(self, evt): self.update_timestamps() elif evt.reason == elw.SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_BY_LOCAL_HOST: self.__update_flags(BASIC_STATE_FLAG_SYNCHRONIZED, False) - self.log.info("Connection to %s closed with reason %s",self.ble_address, esl_lib.get_enum("SL_STATUS_",evt.reason)) + self.log.info("Connection to %s closed with reason %s",self.ble_address, esl_lib.get_sl_status_str(evt.reason)) elif isinstance(evt, esl_lib.EventTagInfo): if evt.connection_handle == self.connection_handle: for ix, (tlv, value) in enumerate(evt.tlv_data.items()): diff --git a/app/bluetooth/example_host/bt_host_esl_ap/qrcode_generator.py b/app/bluetooth/example_host/bt_host_esl_ap/qrcode_generator.py index 2d5d7d620e..3521d25513 100755 --- a/app/bluetooth/example_host/bt_host_esl_ap/qrcode_generator.py +++ b/app/bluetooth/example_host/bt_host_esl_ap/qrcode_generator.py @@ -146,7 +146,7 @@ def generate_qrcode(data, height, width): # Create bytes from image img_xbm = XbmConverter(result) xbm = img_xbm.convert() - return xbm + return xbm, result def merge_qr_hex(qrcode, ihex, sa, hex_file_out="merged.hex"): diff --git a/app/bluetooth/example_host/bt_host_esl_ap/readme/readme.md b/app/bluetooth/example_host/bt_host_esl_ap/readme/readme.md index 23db926a5a..9287675c0b 100644 --- a/app/bluetooth/example_host/bt_host_esl_ap/readme/readme.md +++ b/app/bluetooth/example_host/bt_host_esl_ap/readme/readme.md @@ -323,10 +323,14 @@ Examples: - `image_update 0 ./image/banana.png --label="Line 1\nLine 2"` Send an image to index 0 on the single connected ESL with two lines of label. Note that address is a positional argument yet it can be omitted if there's only one connected device present at the moment. -- `image_update 1 "/user/home/path with space/img.jpg"` all +- `image_update 1 "/user/home/path with space/img.jpg" all` Use the 'all' keyword as special address to send the same image to slot 1 on all connected ESLs. +- `image_update 0 *qrcode all` + + To send unique QR codes to all connected tags for use with ESL Demo, enter "*qrcode" instead of a valid image file path. Typically beneficial for ESLs equipped with permanent displays, such as ePaper. + #### led Turn on / off or flash an LED utilizing the LED control command. diff --git a/app/btmesh/btmesh.properties b/app/btmesh/btmesh.properties index 4896576b3e..11c461e26b 100644 --- a/app/btmesh/btmesh.properties +++ b/app/btmesh/btmesh.properties @@ -2,8 +2,8 @@ id=com.silabs.stack.btMesh label=Bluetooth Mesh SDK description=Bluetooth Mesh Software Development Kit -version=6.0.1.0 -prop.subLabel=Bluetooth\\ Mesh\\ 6.0.1 +version=6.1.0.0 +prop.subLabel=Bluetooth\\ Mesh\\ 6.1.0 # Default compatibility of the BT Mesh SDK (This is needed for the documentation only) prop.boardCompatibility=.* diff --git a/app/btmesh/btmesh_internal_demos.xml b/app/btmesh/btmesh_internal_demos.xml index e38e3dd3aa..b13d9fa2ae 100644 --- a/app/btmesh/btmesh_internal_demos.xml +++ b/app/btmesh/btmesh_internal_demos.xml @@ -6,11 +6,11 @@ - + - + Friend example for IOP test. This node acts as a friend for the low power node and caches messages sent to it when the low power node is sleeping. @@ -18,11 +18,11 @@ - + - + Friend example for IOP test. This node acts as a friend for the low power node and caches messages sent to it when the low power node is sleeping. @@ -30,11 +30,23 @@ - + - + + + + Friend example for IOP test. This node acts as a friend for the low power node and caches messages sent to it when the low power node is sleeping. + + + + + + + + + Friend example for IOP test. This node acts as a friend for the low power node and caches messages sent to it when the low power node is sleeping. @@ -42,11 +54,11 @@ - + - + Friend example for IOP test. This node acts as a friend for the low power node and caches messages sent to it when the low power node is sleeping. @@ -54,11 +66,11 @@ - + - + Low power node example for IOP test. This node acts as a typical low power device and sleeps most of the time. It needs a friend node to cache messages and forward them when polled. @@ -66,11 +78,11 @@ - + - + Low power node example for IOP test. This node acts as a typical low power device and sleeps most of the time. It needs a friend node to cache messages and forward them when polled. @@ -78,11 +90,11 @@ - + - + Low power node example for IOP test. This node acts as a typical low power device and sleeps most of the time. It needs a friend node to cache messages and forward them when polled. @@ -90,11 +102,11 @@ - + - + Low power node example for IOP test. This node acts as a typical low power device and sleeps most of the time. It needs a friend node to cache messages and forward them when polled. @@ -102,11 +114,23 @@ - + + + + + + + + Low power node example for IOP test. This node acts as a typical low power device and sleeps most of the time. It needs a friend node to cache messages and forward them when polled. + + + + + - + Low power node example for IOP test. This node acts as a typical low power device and sleeps most of the time. It needs a friend node to cache messages and forward them when polled. @@ -114,11 +138,11 @@ - + - + Low power node example for IOP test. This node acts as a typical low power device and sleeps most of the time. It needs a friend node to cache messages and forward them when polled. @@ -126,11 +150,11 @@ - + - + Proxy example for IOP test. This node forwards/relays messages between GATT and advertising bearers in the network. @@ -138,11 +162,11 @@ - + - + Proxy example for IOP test. This node forwards/relays messages between GATT and advertising bearers in the network. @@ -150,11 +174,11 @@ - + - + Proxy example for IOP test. This node forwards/relays messages between GATT and advertising bearers in the network. @@ -162,11 +186,23 @@ - + - + + + + Proxy example for IOP test. This node forwards/relays messages between GATT and advertising bearers in the network. + + + + + + + + + Proxy example for IOP test. This node forwards/relays messages between GATT and advertising bearers in the network. @@ -174,11 +210,11 @@ - + - + Proxy example for IOP test. This node forwards/relays messages between GATT and advertising bearers in the network. @@ -186,11 +222,11 @@ - + - + Relay example for IOP test. This node acts as a relay, i.e. if a node is out of range for another node, it relays messages between the two, provided the relay node is in range for both. @@ -198,11 +234,11 @@ - + - + Relay example for IOP test. This node acts as a relay, i.e. if a node is out of range for another node, it relays messages between the two, provided the relay node is in range for both. @@ -210,11 +246,11 @@ - + - + Relay example for IOP test. This node acts as a relay, i.e. if a node is out of range for another node, it relays messages between the two, provided the relay node is in range for both. @@ -222,11 +258,23 @@ - + + + + + + + + Relay example for IOP test. This node acts as a relay, i.e. if a node is out of range for another node, it relays messages between the two, provided the relay node is in range for both. + + + + + - + Relay example for IOP test. This node acts as a relay, i.e. if a node is out of range for another node, it relays messages between the two, provided the relay node is in range for both. @@ -234,11 +282,11 @@ - + - + Relay example for IOP test. This node acts as a relay, i.e. if a node is out of range for another node, it relays messages between the two, provided the relay node is in range for both. @@ -246,11 +294,11 @@ - + - + An out-of-the-box software demo which can provision and configure nearby switch devices. @@ -259,7 +307,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -271,7 +319,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -283,7 +331,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -295,7 +343,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -307,7 +355,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -319,7 +367,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -331,7 +379,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -343,7 +391,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -355,7 +403,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -367,7 +415,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -379,7 +427,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -391,7 +439,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -403,7 +451,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -415,7 +463,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -427,7 +475,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -439,7 +487,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -451,7 +499,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -463,7 +511,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -475,7 +523,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -487,7 +535,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -499,7 +547,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -511,7 +559,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -523,7 +571,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -535,7 +583,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -547,7 +595,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -559,7 +607,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -571,7 +619,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -583,7 +631,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -595,7 +643,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -607,7 +655,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -619,7 +667,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -631,7 +679,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -643,7 +691,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -655,7 +703,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -667,7 +715,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -679,7 +727,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -691,7 +739,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -703,7 +751,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -715,7 +763,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -727,7 +775,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -739,7 +787,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -751,7 +799,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -763,7 +811,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -775,7 +823,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -787,7 +835,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -799,7 +847,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -811,7 +859,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -823,7 +871,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -835,7 +883,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -847,7 +895,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -859,7 +907,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -871,7 +919,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -883,7 +931,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -895,7 +943,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -907,7 +955,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -919,7 +967,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -931,7 +979,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -943,7 +991,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -955,7 +1003,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -967,7 +1015,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -979,7 +1027,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + @@ -991,7 +1039,7 @@ The LEDs of the mainboard can be switched on and off and their lighting intensit - + diff --git a/app/btmesh/btmesh_production_demos.xml b/app/btmesh/btmesh_production_demos.xml index 8faeec1dcc..21452c6bd8 100644 --- a/app/btmesh/btmesh_production_demos.xml +++ b/app/btmesh/btmesh_production_demos.xml @@ -6,11 +6,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -18,11 +18,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -30,11 +30,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -42,11 +42,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -54,11 +54,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -66,11 +66,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -78,11 +78,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -90,11 +90,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -102,11 +102,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -114,11 +114,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -126,11 +126,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -138,11 +138,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -150,11 +150,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -162,11 +162,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -174,11 +174,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -186,11 +186,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -198,11 +198,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -210,11 +210,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. Contains models from BT mesh specification 1.1. @@ -222,11 +222,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -234,11 +234,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -246,11 +246,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -258,11 +258,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -270,11 +270,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -282,11 +282,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -294,11 +294,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -306,11 +306,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -318,11 +318,11 @@ - + - + An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. @@ -330,11 +330,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -342,11 +342,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -354,11 +354,11 @@ - + - + Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. @@ -366,11 +366,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -378,11 +378,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -390,11 +390,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -402,11 +402,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -414,11 +414,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -426,11 +426,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -438,11 +438,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -450,11 +450,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -462,11 +462,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -474,11 +474,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -486,11 +486,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -498,11 +498,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -510,11 +510,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -522,11 +522,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -534,11 +534,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -546,11 +546,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -558,11 +558,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -570,11 +570,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -582,11 +582,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -594,11 +594,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -606,11 +606,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -618,11 +618,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -630,11 +630,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an ambient light sensor in a Networked Lighting Control (NLC) system. The device simulates ambient light measurements and sends these to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -642,11 +642,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an Ambient Light Sensor in a Networked Lighting Control (NLC) system. The device measures ambient light and sends these measurements to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -654,11 +654,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an Ambient Light Sensor in a Networked Lighting Control (NLC) system. The device measures ambient light and sends these measurements to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -666,11 +666,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an Ambient Light Sensor in a Networked Lighting Control (NLC) system. The device measures ambient light and sends these measurements to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -678,11 +678,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an Ambient Light Sensor in a Networked Lighting Control (NLC) system. The device measures ambient light and sends these measurements to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -690,11 +690,11 @@ - + - + An out-of-the-box Software Demo where the device acts as an Ambient Light Sensor in a Networked Lighting Control (NLC) system. The device measures ambient light and sends these measurements to the network. Properly configured NLC Basic Lightness Controllers then can act on the received data. @@ -702,11 +702,11 @@ - + - + An out-of-the-box software demo where the device acts as a Basic Lightness Controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -715,11 +715,11 @@ This project uses the RGB LED on the xG24 Dev Kit. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -728,7 +728,7 @@ This project uses the LEDs on the mainboard. - + @@ -740,11 +740,11 @@ This project uses the LEDs on the mainboard. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -753,7 +753,7 @@ This project uses the LEDs on the mainboard. - + @@ -765,7 +765,7 @@ This project uses the LEDs on the mainboard. - + @@ -777,7 +777,7 @@ This project uses the LEDs on the mainboard. - + @@ -789,7 +789,7 @@ This project uses the LEDs on the mainboard. - + @@ -801,11 +801,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -814,11 +814,11 @@ This project uses the LEDs on the mainboard. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness Controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -827,11 +827,11 @@ This project uses the RGB LEDs on the Thunderboard Sense 2 board. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -840,11 +840,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -853,11 +853,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -866,11 +866,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -879,11 +879,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -892,11 +892,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -905,11 +905,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -918,11 +918,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -931,11 +931,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -944,11 +944,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -957,11 +957,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -970,11 +970,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -983,11 +983,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -996,11 +996,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -1009,11 +1009,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -1022,11 +1022,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the device acts as a Basic Lightness controller in a Networked Lighting Control (NLC) system. The device listens to messages from other NLC devices, namely Occupancy Sensor, Ambient Light Sensor, Dimming Control and Basic Scene Selector nodes. @@ -1035,11 +1035,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1047,11 +1047,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1059,11 +1059,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1071,11 +1071,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1083,11 +1083,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1095,11 +1095,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1107,11 +1107,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1119,11 +1119,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1131,11 +1131,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1143,11 +1143,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1155,11 +1155,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1167,11 +1167,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1179,11 +1179,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1191,11 +1191,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1203,11 +1203,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1215,11 +1215,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1227,11 +1227,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1239,11 +1239,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1251,11 +1251,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1263,11 +1263,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1275,11 +1275,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1287,11 +1287,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1299,11 +1299,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1311,11 +1311,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1323,11 +1323,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1335,11 +1335,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1347,11 +1347,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1359,11 +1359,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1371,11 +1371,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1383,11 +1383,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1395,11 +1395,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1407,11 +1407,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1419,11 +1419,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1431,11 +1431,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1443,11 +1443,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1455,11 +1455,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1467,11 +1467,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1479,11 +1479,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1491,11 +1491,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1503,11 +1503,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1515,11 +1515,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1527,11 +1527,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1539,11 +1539,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1551,11 +1551,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1563,11 +1563,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1575,11 +1575,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1587,11 +1587,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1599,11 +1599,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1611,11 +1611,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1623,11 +1623,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1635,11 +1635,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1647,11 +1647,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1659,11 +1659,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1671,11 +1671,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1683,11 +1683,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1695,11 +1695,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1707,11 +1707,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1719,11 +1719,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1731,11 +1731,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1743,11 +1743,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1755,11 +1755,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1767,11 +1767,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Basic Scene Selector in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by scene recall requests. @@ -1779,11 +1779,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1791,11 +1791,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1803,11 +1803,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1815,11 +1815,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1827,11 +1827,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1839,11 +1839,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1851,11 +1851,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1863,11 +1863,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1875,11 +1875,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1887,11 +1887,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1899,11 +1899,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1911,11 +1911,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1923,11 +1923,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1935,11 +1935,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1947,11 +1947,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1959,11 +1959,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1971,11 +1971,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1983,11 +1983,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -1995,11 +1995,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2007,11 +2007,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2019,11 +2019,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2031,11 +2031,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2043,11 +2043,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2055,11 +2055,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2067,11 +2067,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2079,11 +2079,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2091,11 +2091,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2103,11 +2103,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2115,11 +2115,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2127,11 +2127,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2139,11 +2139,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2151,11 +2151,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2163,11 +2163,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2175,11 +2175,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2187,11 +2187,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2199,11 +2199,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2211,11 +2211,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2223,11 +2223,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2235,11 +2235,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2247,11 +2247,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2259,11 +2259,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2271,11 +2271,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2283,11 +2283,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2295,11 +2295,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2307,11 +2307,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2319,11 +2319,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2331,11 +2331,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2343,11 +2343,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2355,11 +2355,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2367,11 +2367,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2379,11 +2379,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2391,11 +2391,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2403,11 +2403,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2415,11 +2415,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2427,11 +2427,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2439,11 +2439,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2451,11 +2451,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2463,11 +2463,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2475,11 +2475,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2487,11 +2487,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2499,11 +2499,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a Dimming Control in a Networked Lighting Control (NLC) system. Push Button presses control Basic Lightness Controllers in the network by Generic Level Delta or Generic On/Off messages. @@ -2511,11 +2511,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2523,11 +2523,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2535,11 +2535,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2547,11 +2547,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2559,11 +2559,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2571,11 +2571,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2583,11 +2583,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2595,11 +2595,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2607,11 +2607,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2619,11 +2619,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2631,11 +2631,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2643,11 +2643,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2655,11 +2655,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2667,11 +2667,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2679,11 +2679,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2691,11 +2691,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2703,11 +2703,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2715,11 +2715,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2727,11 +2727,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2739,11 +2739,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2751,11 +2751,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2763,11 +2763,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2775,11 +2775,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2787,11 +2787,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2799,11 +2799,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2811,11 +2811,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2823,11 +2823,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2835,11 +2835,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2847,11 +2847,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2859,11 +2859,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2871,11 +2871,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as an Occupancy Sensor in a Networked Lighting Control (NLC) system. Push Button presses imitate people count changes which can control a properly configured NLC Basic Lightness Controller. @@ -2883,11 +2883,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2895,11 +2895,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2907,11 +2907,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2919,11 +2919,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2931,11 +2931,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2943,11 +2943,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2955,11 +2955,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2967,11 +2967,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2979,11 +2979,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -2991,11 +2991,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -3003,11 +3003,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -3015,11 +3015,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -3027,11 +3027,11 @@ This project uses the LEDs and display on the WSTK. - + - + Certificate generating firmware example. Software is generating the device EC key pair, the signing request for the device certificate, and other related data. The generated data can be read out by the Central Authority. @@ -3039,11 +3039,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3051,11 +3051,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3063,11 +3063,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3075,11 +3075,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3087,11 +3087,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3099,11 +3099,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3111,11 +3111,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3123,11 +3123,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3135,11 +3135,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3147,11 +3147,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3159,11 +3159,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3171,11 +3171,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3183,11 +3183,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3195,11 +3195,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3207,11 +3207,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3219,11 +3219,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3231,11 +3231,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3243,11 +3243,11 @@ This project uses the LEDs and display on the WSTK. - + - + Demonstrates the Firmware Distributor role based on the BT Mesh Model specification. Distributor is responsible for delivering new firmware images to the Target nodes and monitoring the progress of the firmware update. @@ -3255,11 +3255,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3267,11 +3267,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3279,11 +3279,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3291,11 +3291,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3303,11 +3303,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3315,11 +3315,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the Thunderboard Sense 2 board can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3327,11 +3327,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3339,11 +3339,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3351,11 +3351,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3363,11 +3363,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3375,11 +3375,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3387,11 +3387,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3399,11 +3399,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3411,11 +3411,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3423,11 +3423,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3435,11 +3435,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3447,11 +3447,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3459,11 +3459,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3471,11 +3471,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3483,11 +3483,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3495,11 +3495,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3507,11 +3507,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. @@ -3519,11 +3519,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3531,11 +3531,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3543,11 +3543,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3555,11 +3555,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3567,11 +3567,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3579,11 +3579,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the Thunderboard Sense 2 can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3591,11 +3591,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3603,11 +3603,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3615,11 +3615,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3627,11 +3627,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3639,11 +3639,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3651,11 +3651,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3663,11 +3663,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3675,11 +3675,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3687,11 +3687,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3699,11 +3699,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3711,11 +3711,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3723,11 +3723,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3735,11 +3735,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3747,11 +3747,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3759,11 +3759,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3771,11 +3771,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. @@ -3783,11 +3783,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3795,11 +3795,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3807,11 +3807,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3819,11 +3819,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3831,11 +3831,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3843,11 +3843,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3855,11 +3855,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3867,11 +3867,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3879,11 +3879,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3891,11 +3891,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3903,11 +3903,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3915,11 +3915,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3927,11 +3927,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3939,11 +3939,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3951,11 +3951,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3963,11 +3963,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3975,11 +3975,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3987,11 +3987,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -3999,11 +3999,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -4011,11 +4011,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -4023,11 +4023,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -4035,11 +4035,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -4047,11 +4047,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -4059,11 +4059,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -4071,11 +4071,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -4083,11 +4083,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -4095,11 +4095,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -4107,11 +4107,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -4119,11 +4119,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -4131,11 +4131,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -4143,11 +4143,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). @@ -4155,11 +4155,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4167,11 +4167,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4179,11 +4179,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4191,11 +4191,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4203,11 +4203,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4215,11 +4215,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4227,11 +4227,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4239,11 +4239,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4251,11 +4251,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4263,11 +4263,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4275,11 +4275,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4287,11 +4287,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4299,11 +4299,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4311,11 +4311,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4323,11 +4323,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4335,11 +4335,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4347,11 +4347,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4359,11 +4359,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4371,11 +4371,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4383,11 +4383,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4395,11 +4395,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4407,11 +4407,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4419,11 +4419,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4431,11 +4431,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4443,11 +4443,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4455,11 +4455,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4467,11 +4467,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4479,11 +4479,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4491,11 +4491,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4503,11 +4503,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4515,11 +4515,11 @@ This project uses the LEDs and display on the WSTK. - + - + This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. If available, it measures CPU temperature and uses that data as temperature reading, otherwise it sends mocked temperature data to a remote device (e.g., btmesh_soc_sensor_client). @@ -4527,11 +4527,11 @@ This project uses the LEDs and display on the WSTK. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4540,11 +4540,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4553,11 +4553,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4566,11 +4566,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4579,11 +4579,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4592,11 +4592,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4605,11 +4605,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4618,11 +4618,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4631,11 +4631,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4644,11 +4644,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4657,11 +4657,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4670,11 +4670,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4683,11 +4683,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4696,11 +4696,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4709,11 +4709,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4722,11 +4722,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4735,11 +4735,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4748,11 +4748,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4761,11 +4761,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4774,11 +4774,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4787,11 +4787,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4800,11 +4800,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4813,11 +4813,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4826,11 +4826,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4839,11 +4839,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4852,11 +4852,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4865,11 +4865,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4878,11 +4878,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4891,11 +4891,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4904,11 +4904,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4917,11 +4917,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. It is optimized for low current consumption with disabled CLI, logging, and LCD. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4930,11 +4930,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4943,11 +4943,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4956,11 +4956,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4969,11 +4969,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4982,11 +4982,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -4995,11 +4995,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5008,11 +5008,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5021,11 +5021,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5034,11 +5034,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5047,11 +5047,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5060,11 +5060,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5073,11 +5073,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5086,11 +5086,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5099,11 +5099,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5112,11 +5112,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5125,11 +5125,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5138,11 +5138,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5151,11 +5151,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5164,11 +5164,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5177,11 +5177,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5190,11 +5190,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5203,11 +5203,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5216,11 +5216,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5229,11 +5229,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5242,11 +5242,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5255,11 +5255,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5268,11 +5268,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5281,11 +5281,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5294,11 +5294,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5307,11 +5307,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5320,11 +5320,11 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + An out-of-the-box Software Demo where the device acts as a switch using the Light CTL Client Model. Push Button presses or CLI commands can control the lightness and color temperature of the LEDs on a remote device. @@ -5333,10 +5333,10 @@ Note - this example is not compatible with the Dimming Control NLC Profile. - + - + diff --git a/app/btmesh/common/btmesh_ctl_server/config/sl_btmesh_ctl_server_config.h b/app/btmesh/common/btmesh_ctl_server/config/sl_btmesh_ctl_server_config.h index 6b766004a4..5679c90ddc 100644 --- a/app/btmesh/common/btmesh_ctl_server/config/sl_btmesh_ctl_server_config.h +++ b/app/btmesh/common/btmesh_ctl_server/config/sl_btmesh_ctl_server_config.h @@ -45,9 +45,9 @@ #define SL_BTMESH_CTL_SERVER_PS_KEY_CFG_VAL (0x4005) // Periodicity [ms] for updating the PWM duty cycle during a transition. -// Default: 1 +// Default: 10 // Periodicity [ms] for updating the PWM duty cycle during a transition. -#define SL_BTMESH_CTL_SERVER_PWM_UPDATE_PERIOD_CFG_VAL (1) +#define SL_BTMESH_CTL_SERVER_PWM_UPDATE_PERIOD_CFG_VAL (10) // Periodicity [ms] for updating the UI with temperature & delta UV during a transition. // Default: 100 diff --git a/app/btmesh/common/btmesh_ctl_server/sl_btmesh_ctl_server.c b/app/btmesh/common/btmesh_ctl_server/sl_btmesh_ctl_server.c index adb142a0ad..9d5395fbb2 100644 --- a/app/btmesh/common/btmesh_ctl_server/sl_btmesh_ctl_server.c +++ b/app/btmesh/common/btmesh_ctl_server/sl_btmesh_ctl_server.c @@ -79,6 +79,8 @@ #define HIGH_PRIORITY 0 ///< High Priority /// Values greater than max 37200000 are treated as unknown remaining time #define UNKNOWN_REMAINING_TIME 40000000 +/// Difference between Generic Level and temperature value to convert the ranges +#define GENERIC_TO_TEMP_LEVEL_SHIFT 32768 /// Lightbulb state static PACKSTRUCT(struct lightbulb_state { @@ -1496,6 +1498,9 @@ static void sec_level_move_schedule_next_request(int32_t remaining_delta) ******************************************************************************/ static void sec_level_move_request(void) { + // sync current sec level and actual value + lightbulb_state.sec_level_current = lightbulb_state.temperature_current - GENERIC_TO_TEMP_LEVEL_SHIFT; + log_info("Secondary level move: level %d -> %d, delta %d in %lu ms" NL, lightbulb_state.sec_level_current, lightbulb_state.sec_level_target, @@ -1508,18 +1513,13 @@ static void sec_level_move_request(void) if (abs(remaining_delta) < abs(move_sec_level_delta)) { // end of move level as it reached target state lightbulb_state.sec_level_current = lightbulb_state.sec_level_target; - lightbulb_state.temperature_current = lightbulb_state.temperature_target; } else { lightbulb_state.sec_level_current += move_sec_level_delta; - uint16_t temperature = level_to_temperature(lightbulb_state.sec_level_current); - lightbulb_state.temperature_current = temperature; } lightbulb_state_changed(); sec_level_update_and_publish(BTMESH_CTL_SERVER_TEMPERATURE, UNKNOWN_REMAINING_TIME); - remaining_delta = (int32_t)lightbulb_state.sec_level_target - - lightbulb_state.sec_level_current; if (remaining_delta != 0) { sec_level_move_schedule_next_request(remaining_delta); } diff --git a/app/btmesh/common/btmesh_ctl_server/sl_btmesh_ctl_signal_transition_handler.c b/app/btmesh/common/btmesh_ctl_server/sl_btmesh_ctl_signal_transition_handler.c index 3e9cfe3ff3..9e77588013 100644 --- a/app/btmesh/common/btmesh_ctl_server/sl_btmesh_ctl_signal_transition_handler.c +++ b/app/btmesh/common/btmesh_ctl_server/sl_btmesh_ctl_signal_transition_handler.c @@ -37,6 +37,7 @@ #include "app_assert.h" #include "app_timer.h" +#include "sl_sleeptimer.h" #ifdef SL_COMPONENT_CATALOG_PRESENT #include "sl_component_catalog.h" @@ -74,12 +75,14 @@ static int16_t start_deltauv; /// target level of delta UV transition static int16_t target_deltauv; -/// temperature transition time in timer ticks -static uint32_t temp_transtime_ticks; +/// temperature transition time in ms +static uint32_t temp_transtime_ms; /// time elapsed from temperature transition start static uint32_t temp_transtime_elapsed; /// non-zero if temperature transition is active static uint8_t temp_transitioning; +/// timestamp of the last sleeptimer tick +static uint64_t last_tick; static app_timer_t transition_timer; @@ -109,6 +112,13 @@ static void transition_timer_cb(app_timer_t *timer, void *data) { (void)data; (void)timer; + + // Use sleeptimer to account for scheduling errors + uint64_t current_tick = sl_sleeptimer_get_tick_count64(); + uint64_t period_ms = 0; + sl_sleeptimer_tick64_to_ms(current_tick - last_tick, &period_ms); + last_tick = current_tick; + // Initialize the variable to UI update period in order to trigger a UI update // at the beginning of the transition. static uint16_t time_elapsed_since_ui_update = SL_BTMESH_CTL_SERVER_UI_UPDATE_PERIOD_CFG_VAL; @@ -118,9 +128,9 @@ static void transition_timer_cb(app_timer_t *timer, void *data) app_assert_status_f(sc, "Failed to stop Periodic Level Transition Timer\n"); return; } else { - temp_transtime_elapsed++; + temp_transtime_elapsed += period_ms; - if (temp_transtime_elapsed >= temp_transtime_ticks) { + if (temp_transtime_elapsed >= temp_transtime_ms) { // transition complete temp_transitioning = 0; current_temperature = target_temperature; @@ -139,24 +149,24 @@ static void transition_timer_cb(app_timer_t *timer, void *data) current_temperature = start_temperature + (target_temperature - start_temperature) * (uint64_t)temp_transtime_elapsed - / temp_transtime_ticks; + / temp_transtime_ms; } else { current_temperature = start_temperature - (start_temperature - target_temperature) * (uint64_t)temp_transtime_elapsed - / temp_transtime_ticks; + / temp_transtime_ms; } if (target_deltauv >= start_deltauv) { current_deltauv = start_deltauv + (target_deltauv - start_deltauv) * (uint64_t)temp_transtime_elapsed - / temp_transtime_ticks; + / temp_transtime_ms; } else { current_deltauv = start_deltauv - (start_deltauv - target_deltauv) * (uint64_t)temp_transtime_elapsed - / temp_transtime_ticks; + / temp_transtime_ms; } // When transition is ongoing generate an event to application once every @@ -191,6 +201,9 @@ void sl_btmesh_ctl_set_temperature_deltauv_level(uint16_t temperature, temperature = SL_BTMESH_CTL_SERVER_MAXIMUM_TEMPERATURE_CFG_VAL; } + // get last tick before running the first transition timer + last_tick = sl_sleeptimer_get_tick_count64(); + if (transition_ms == 0) { current_temperature = temperature; current_deltauv = deltauv; @@ -207,7 +220,7 @@ void sl_btmesh_ctl_set_temperature_deltauv_level(uint16_t temperature, return; } - temp_transtime_ticks = transition_ms; + temp_transtime_ms = transition_ms; start_temperature = current_temperature; target_temperature = temperature; @@ -227,6 +240,9 @@ void sl_btmesh_ctl_set_temperature_deltauv_level(uint16_t temperature, true); app_assert_status_f(sc, "Failed to start periodic Transition Timer\n"); + // run first transition since the timer will not trigger now + transition_timer_cb(NULL, NULL); + return; } diff --git a/app/btmesh/common/btmesh_dcd_configuration/dcd_config.btmeshconf b/app/btmesh/common/btmesh_dcd_configuration/dcd_config.btmeshconf index 4753009e99..15e9497cc1 100644 --- a/app/btmesh/common/btmesh_dcd_configuration/dcd_config.btmeshconf +++ b/app/btmesh/common/btmesh_dcd_configuration/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0xffff", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/btmesh/common/btmesh_hsl_server/config/sl_btmesh_hsl_server_config.h b/app/btmesh/common/btmesh_hsl_server/config/sl_btmesh_hsl_server_config.h index 0c48f90979..3872a49a48 100644 --- a/app/btmesh/common/btmesh_hsl_server/config/sl_btmesh_hsl_server_config.h +++ b/app/btmesh/common/btmesh_hsl_server/config/sl_btmesh_hsl_server_config.h @@ -16,14 +16,14 @@ #define SL_BTMESH_HSL_SERVER_PS_KEY_CFG_VAL (0x4008) // Periodicity [ms] for updating the hue during a transition. -// Default: 1 +// Default: 10 // Periodicity [ms] for updating the hue during a transition. -#define SL_BTMESH_HSL_SERVER_HUE_UPDATE_PERIOD_CFG_VAL (1) +#define SL_BTMESH_HSL_SERVER_HUE_UPDATE_PERIOD_CFG_VAL (10) // Periodicity [ms] for updating the saturation during a transition. -// Default: 1 +// Default: 10 // Periodicity [ms] for updating the saturation during a transition. -#define SL_BTMESH_HSL_SERVER_SATURATION_UPDATE_PERIOD_CFG_VAL (1) +#define SL_BTMESH_HSL_SERVER_SATURATION_UPDATE_PERIOD_CFG_VAL (10) // Periodicity [ms] for updating the UI with hue during a transition. // Default: 100 diff --git a/app/btmesh/common/btmesh_hsl_server/sl_btmesh_hsl_server.c b/app/btmesh/common/btmesh_hsl_server/sl_btmesh_hsl_server.c index b6560c1987..b059c23655 100644 --- a/app/btmesh/common/btmesh_hsl_server/sl_btmesh_hsl_server.c +++ b/app/btmesh/common/btmesh_hsl_server/sl_btmesh_hsl_server.c @@ -80,6 +80,8 @@ #define HIGH_PRIORITY 0 ///< High Priority /// Values greater than max 37200000 are treated as unknown remaining time #define UNKNOWN_REMAINING_TIME 40000000 +/// Difference between Generic Level and Hue/Saturation Level to convert the ranges +#define GENERIC_TO_HSL_LEVEL_SHIFT 32768 /// Lightbulb state static PACKSTRUCT(struct lightbulb_state { @@ -1486,6 +1488,9 @@ static void hue_level_move_schedule_next_request(int32_t remaining_delta) ******************************************************************************/ static void hue_level_move_request(void) { + // sync current hue level with actual value + lightbulb_state.hue_level_current = lightbulb_state.hue_current - GENERIC_TO_HSL_LEVEL_SHIFT; + log_info("Hue generic level move: level %d -> %d, delta %d in %lu ms" NL, lightbulb_state.hue_level_current, lightbulb_state.hue_level_target, @@ -1498,17 +1503,12 @@ static void hue_level_move_request(void) if (abs(remaining_delta) < abs(move_hue_level_delta)) { // end of move level as it reached target state lightbulb_state.hue_level_current = lightbulb_state.hue_level_target; - lightbulb_state.hue_current = lightbulb_state.hue_target; } else { lightbulb_state.hue_level_current += move_hue_level_delta; - lightbulb_state.hue_current += move_hue_level_delta; } lightbulb_state_changed(); hue_level_update_and_publish(BTMESH_HSL_SERVER_HUE, UNKNOWN_REMAINING_TIME); - remaining_delta = (int32_t)lightbulb_state.hue_level_target - - lightbulb_state.hue_level_current; - hue_level_move_schedule_next_request(remaining_delta); } @@ -2340,6 +2340,9 @@ static void saturation_level_move_schedule_next_request(int32_t remaining_delta) ******************************************************************************/ static void saturation_level_move_request(void) { + // sync current saturation level with actual value + lightbulb_state.saturation_level_current = lightbulb_state.saturation_current - GENERIC_TO_HSL_LEVEL_SHIFT; + log_info("Saturation generic level move: level %d -> %d, delta %d in %lu ms" NL, lightbulb_state.saturation_level_current, lightbulb_state.saturation_level_target, @@ -2352,18 +2355,13 @@ static void saturation_level_move_request(void) if (abs(remaining_delta) < abs(move_saturation_level_delta)) { // end of move level as it reached target state lightbulb_state.saturation_level_current = lightbulb_state.saturation_level_target; - lightbulb_state.saturation_current = lightbulb_state.saturation_target; } else { lightbulb_state.saturation_level_current += move_saturation_level_delta; - lightbulb_state.saturation_current += move_saturation_level_delta; } lightbulb_state_changed(); saturation_level_update_and_publish(BTMESH_HSL_SERVER_SATURATION, UNKNOWN_REMAINING_TIME); - remaining_delta = (int32_t)lightbulb_state.saturation_level_target - - lightbulb_state.saturation_level_current; - saturation_level_move_schedule_next_request(remaining_delta); } diff --git a/app/btmesh/common/btmesh_hsl_server/sl_btmesh_hsl_signal_transition_handler.c b/app/btmesh/common/btmesh_hsl_server/sl_btmesh_hsl_signal_transition_handler.c index 67d4f948e2..31fbf0ef2e 100644 --- a/app/btmesh/common/btmesh_hsl_server/sl_btmesh_hsl_signal_transition_handler.c +++ b/app/btmesh/common/btmesh_hsl_server/sl_btmesh_hsl_signal_transition_handler.c @@ -37,6 +37,7 @@ #include "sl_status.h" #include "app_timer.h" +#include "sl_sleeptimer.h" #ifdef SL_COMPONENT_CATALOG_PRESENT #include "sl_component_catalog.h" @@ -70,19 +71,23 @@ static uint16_t start_saturation; /// target level of saturation transition static uint16_t target_saturation; -/// hue transition time in timer ticks -static uint32_t hue_transtime_ticks; +/// hue transition time in ms +static uint32_t hue_transtime_ms; /// time elapsed from hue transition start static uint32_t hue_transtime_elapsed; /// non-zero if hue transition is active static uint8_t hue_transitioning; +/// timestamp of the last sleeptimer tick +static uint64_t hue_last_tick; -/// saturation transition time in timer ticks -static uint32_t saturation_transtime_ticks; +/// saturation transition time in ms +static uint32_t saturation_transtime_ms; /// time elapsed from saturation transition start static uint32_t saturation_transtime_elapsed; /// non-zero if saturation transition is active static uint8_t saturation_transitioning; +/// timestamp of the last sleeptimer tick +static uint64_t saturation_last_tick; static app_timer_t hue_transition_timer; static app_timer_t saturation_transition_timer; @@ -122,6 +127,13 @@ static void hue_transition_timer_cb(app_timer_t *timer, void *data) { (void)data; (void)timer; + + // Use sleeptimer to account for scheduling errors + uint64_t current_tick = sl_sleeptimer_get_tick_count64(); + uint64_t period_ms = 0; + sl_sleeptimer_tick64_to_ms(current_tick - hue_last_tick, &period_ms); + hue_last_tick = current_tick; + // Initialize the variable to UI update period in order to trigger a UI update // at the beginning of the transition. static uint16_t time_elapsed_since_ui_update = SL_BTMESH_HSL_SERVER_HUE_UI_UPDATE_PERIOD_CFG_VAL; @@ -131,9 +143,9 @@ static void hue_transition_timer_cb(app_timer_t *timer, void *data) app_assert_status_f(sc, "Failed to stop Periodic Hue Transition Timer"); return; } else { - hue_transtime_elapsed++; + hue_transtime_elapsed += period_ms; - if (hue_transtime_elapsed >= hue_transtime_ticks) { + if (hue_transtime_elapsed >= hue_transtime_ms) { // transition complete hue_transitioning = 0; current_hue = target_hue; @@ -151,12 +163,12 @@ static void hue_transition_timer_cb(app_timer_t *timer, void *data) current_hue = start_hue + (target_hue - start_hue) * (uint64_t)hue_transtime_elapsed - / hue_transtime_ticks; + / hue_transtime_ms; } else { current_hue = start_hue - (start_hue - target_hue) * (uint64_t)hue_transtime_elapsed - / hue_transtime_ticks; + / hue_transtime_ms; } // When transition is ongoing generate an event to application once every @@ -181,6 +193,13 @@ static void saturation_transition_timer_cb(app_timer_t *timer, void *data) { (void)data; (void)timer; + + // Use sleeptimer to account for scheduling errors + uint64_t current_tick = sl_sleeptimer_get_tick_count64(); + uint64_t period_ms = 0; + sl_sleeptimer_tick64_to_ms(current_tick - saturation_last_tick, &period_ms); + saturation_last_tick = current_tick; + // Initialize the variable to UI update period in order to trigger a UI update // at the beginning of the transition. static uint16_t time_elapsed_since_ui_update = SL_BTMESH_HSL_SERVER_SATURATION_UI_UPDATE_PERIOD_CFG_VAL; @@ -190,9 +209,9 @@ static void saturation_transition_timer_cb(app_timer_t *timer, void *data) app_assert_status_f(sc, "Failed to stop Periodic Saturation Transition Timer"); return; } else { - saturation_transtime_elapsed++; + saturation_transtime_elapsed += period_ms; - if (saturation_transtime_elapsed >= saturation_transtime_ticks) { + if (saturation_transtime_elapsed >= saturation_transtime_ms) { // transition complete saturation_transitioning = 0; current_saturation = target_saturation; @@ -210,12 +229,12 @@ static void saturation_transition_timer_cb(app_timer_t *timer, void *data) current_saturation = start_saturation + (target_saturation - start_saturation) * (uint64_t)saturation_transtime_elapsed - / saturation_transtime_ticks; + / saturation_transtime_ms; } else { current_saturation = start_saturation - (target_saturation - start_saturation) * (uint64_t)saturation_transtime_elapsed - / saturation_transtime_ticks; + / saturation_transtime_ms; } // When transition is ongoing generate an event to application once every @@ -253,6 +272,9 @@ void sl_btmesh_hsl_set_hue_level(uint16_t hue, uint32_t transition_ms) } #endif + // get last tick before running the first transition timer + hue_last_tick = sl_sleeptimer_get_tick_count64(); + if (transition_ms == 0) { current_hue = hue; @@ -268,7 +290,7 @@ void sl_btmesh_hsl_set_hue_level(uint16_t hue, uint32_t transition_ms) return; } - hue_transtime_ticks = transition_ms; + hue_transtime_ms = transition_ms; start_hue = current_hue; target_hue = hue; @@ -285,6 +307,9 @@ void sl_btmesh_hsl_set_hue_level(uint16_t hue, uint32_t transition_ms) true); app_assert_status_f(sc, "Failed to start periodic Hue Transition Timer"); + // run first transition since the timer will not trigger now + hue_transition_timer_cb(NULL, NULL); + return; } @@ -308,6 +333,9 @@ void sl_btmesh_hsl_set_saturation_level(uint16_t saturation, uint32_t transition } #endif + // get last tick before running the first transition timer + saturation_last_tick = sl_sleeptimer_get_tick_count64(); + if (transition_ms == 0) { current_saturation = saturation; @@ -323,7 +351,7 @@ void sl_btmesh_hsl_set_saturation_level(uint16_t saturation, uint32_t transition return; } - saturation_transtime_ticks = transition_ms; + saturation_transtime_ms = transition_ms; start_saturation = current_saturation; target_saturation = saturation; @@ -340,6 +368,9 @@ void sl_btmesh_hsl_set_saturation_level(uint16_t saturation, uint32_t transition true); app_assert_status_f(sc, "Failed to start periodic Saturation Transition Timer"); + // run first transition since the timer will not trigger now + saturation_transition_timer_cb(NULL, NULL); + return; } diff --git a/app/btmesh/common/btmesh_lighting_server/config/sl_btmesh_lighting_server_config.h b/app/btmesh/common/btmesh_lighting_server/config/sl_btmesh_lighting_server_config.h index 4b99db69ce..6b3197fef5 100644 --- a/app/btmesh/common/btmesh_lighting_server/config/sl_btmesh_lighting_server_config.h +++ b/app/btmesh/common/btmesh_lighting_server/config/sl_btmesh_lighting_server_config.h @@ -45,9 +45,9 @@ #define SL_BTMESH_LIGHTING_SERVER_PS_KEY_CFG_VAL (0x4004) // Periodicity [ms] for updating the PWM duty cycle during a transition. -// Default: 1 +// Default: 10 // Periodicity [ms] for updating the PWM duty cycle during a transition. -#define SL_BTMESH_LIGHTING_SERVER_PWM_UPDATE_PERIOD_CFG_VAL (1) +#define SL_BTMESH_LIGHTING_SERVER_PWM_UPDATE_PERIOD_CFG_VAL (10) // for updating the UI with lightness level during a transition. // Default: 100 diff --git a/app/btmesh/common/btmesh_lighting_server/sl_btmesh_lighting_level_transition_handler.c b/app/btmesh/common/btmesh_lighting_server/sl_btmesh_lighting_level_transition_handler.c index d2dddbd2ab..7335e0b574 100644 --- a/app/btmesh/common/btmesh_lighting_server/sl_btmesh_lighting_level_transition_handler.c +++ b/app/btmesh/common/btmesh_lighting_server/sl_btmesh_lighting_level_transition_handler.c @@ -33,6 +33,7 @@ #include "app_assert.h" #include "app_timer.h" +#include "sl_sleeptimer.h" #ifdef SL_COMPONENT_CATALOG_PRESENT #include "sl_component_catalog.h" @@ -63,12 +64,14 @@ static uint16_t start_level; /// target level of lightness transition static uint16_t target_level; -/// lightness transition time in timer ticks -static uint32_t level_transtime_ticks; +/// lightness transition time in ms +static uint32_t level_transtime_ms; /// time elapsed from lightness transition start static uint32_t level_transtime_elapsed; /// non-zero if lightness transition is active static uint8_t level_transitioning; +/// timestamp of the last sleeptimer tick +static uint64_t last_tick; static app_timer_t transition_timer; @@ -99,6 +102,12 @@ static void transition_timer_cb(app_timer_t *handle, (void)data; (void)handle; + // Use sleeptimer to account for scheduling errors + uint64_t current_tick = sl_sleeptimer_get_tick_count64(); + uint64_t period_ms = 0; + sl_sleeptimer_tick64_to_ms(current_tick - last_tick, &period_ms); + last_tick = current_tick; + // Initialize the variable to UI update period in order to trigger a UI update // at the beginning of the transition. static uint16_t time_elapsed_since_ui_update = @@ -109,9 +118,9 @@ static void transition_timer_cb(app_timer_t *handle, app_assert_status_f(sc, "Failed to stop Periodic Level Transition Timer"); return; } else { - level_transtime_elapsed++; + level_transtime_elapsed += period_ms; - if (level_transtime_elapsed >= level_transtime_ticks) { + if (level_transtime_elapsed >= level_transtime_ms) { // transition complete level_transitioning = 0; current_level = target_level; @@ -123,19 +132,19 @@ static void transition_timer_cb(app_timer_t *handle, // Trigger a UI update in order to provide the target values at the end // of the current transition sl_btmesh_lighting_server_on_ui_update(current_level); - sl_btmesh_update_lightness(current_level, level_transtime_ticks - level_transtime_elapsed); + sl_btmesh_update_lightness(current_level, level_transtime_ms - level_transtime_elapsed); } else { // calculate current PWM duty cycle based on elapsed transition time if (target_level >= start_level) { current_level = start_level + (target_level - start_level) * (uint64_t)level_transtime_elapsed - / level_transtime_ticks; + / level_transtime_ms; } else { current_level = start_level - (start_level - target_level) * (uint64_t)level_transtime_elapsed - / level_transtime_ticks; + / level_transtime_ms; } // When transition is ongoing generate an event to application once every @@ -146,7 +155,7 @@ static void transition_timer_cb(app_timer_t *handle, if (SL_BTMESH_LIGHTING_SERVER_UI_UPDATE_PERIOD_CFG_VAL <= time_elapsed_since_ui_update) { time_elapsed_since_ui_update -= SL_BTMESH_LIGHTING_SERVER_UI_UPDATE_PERIOD_CFG_VAL; sl_btmesh_lighting_server_on_ui_update(current_level); - sl_btmesh_update_lightness(current_level, level_transtime_ticks - level_transtime_elapsed); + sl_btmesh_update_lightness(current_level, level_transtime_ms - level_transtime_elapsed); } } } @@ -162,6 +171,8 @@ static void transition_timer_cb(app_timer_t *handle, ******************************************************************************/ void sl_btmesh_lighting_set_level(uint16_t level, uint32_t transition_ms) { + // get last tick before running the first transition timer + last_tick = sl_sleeptimer_get_tick_count64(); if (transition_ms == 0) { current_level = level; @@ -177,7 +188,7 @@ void sl_btmesh_lighting_set_level(uint16_t level, uint32_t transition_ms) return; } - level_transtime_ticks = transition_ms; + level_transtime_ms = transition_ms; start_level = current_level; target_level = level; @@ -194,6 +205,9 @@ void sl_btmesh_lighting_set_level(uint16_t level, uint32_t transition_ms) true); app_assert_status_f(sc, "Failed to start periodic Transition Timer"); + // run first transition since the timer will not trigger now + transition_timer_cb(NULL, NULL); + return; } diff --git a/app/btmesh/common/btmesh_lighting_server/sl_btmesh_lighting_server.c b/app/btmesh/common/btmesh_lighting_server/sl_btmesh_lighting_server.c index cf47691d5a..5eb3c68353 100644 --- a/app/btmesh/common/btmesh_lighting_server/sl_btmesh_lighting_server.c +++ b/app/btmesh/common/btmesh_lighting_server/sl_btmesh_lighting_server.c @@ -1862,6 +1862,9 @@ static void pri_level_move_schedule_next_request(int32_t remaining_delta) ******************************************************************************/ static void pri_level_move_request(void) { + // sync current pri level and actual lightness + lightbulb_state.pri_level_current = lightbulb_state.lightness_current - GENERIC_TO_LIGHTNESS_LEVEL_SHIFT; + log_info("Primary level move: level %d -> %d, delta %d in %lu ms" NL, lightbulb_state.pri_level_current, lightbulb_state.pri_level_target, @@ -1874,17 +1877,13 @@ static void pri_level_move_request(void) if (abs(remaining_delta) < abs(move_pri_level_delta)) { // end of move level as it reached target state lightbulb_state.pri_level_current = lightbulb_state.pri_level_target; - lightbulb_state.lightness_current = lightbulb_state.lightness_target; } else { lightbulb_state.pri_level_current += move_pri_level_delta; - lightbulb_state.lightness_current += move_pri_level_delta; } lightbulb_state_changed(); pri_level_update_and_publish(BTMESH_LIGHTING_SERVER_MAIN, UNKNOWN_REMAINING_TIME); - remaining_delta = (int32_t)lightbulb_state.pri_level_target - - lightbulb_state.pri_level_current; if (remaining_delta != 0) { pri_level_move_schedule_next_request(remaining_delta); } @@ -1946,6 +1945,8 @@ static void pri_level_request(uint16_t model_id, pri_level_move_stop(); + lightness_kind = mesh_generic_state_level; + if (lightbulb_state.pri_level_current == request->level) { log_info("Request for current state received; no op" NL); lightbulb_state.pri_level_target = request->level; diff --git a/app/btmesh/component/btmesh_lighting_server.slcc b/app/btmesh/component/btmesh_lighting_server.slcc index 1a386fce06..036f7a28f9 100644 --- a/app/btmesh/component/btmesh_lighting_server.slcc +++ b/app/btmesh/component/btmesh_lighting_server.slcc @@ -42,6 +42,8 @@ requires: - name: "btmesh_stack_generic_server" - name: "btmesh_stack_node" - name: "btmesh_generic_server" + - name: "component_catalog" + - name: "sleeptimer" - name: "btmesh_stack" - name: "app_timer" recommends: diff --git a/app/btmesh/documentation/btmesh-release-highlights.txt b/app/btmesh/documentation/btmesh-release-highlights.txt index 0fa8929cef..9443ce291d 100644 --- a/app/btmesh/documentation/btmesh-release-highlights.txt +++ b/app/btmesh/documentation/btmesh-release-highlights.txt @@ -1,2 +1,2 @@ -Bluetooth Mesh SDK 6.0.1 -- Targeted quality improvements and bugfixes +Bluetooth Mesh SDK 6.1.0 +- Targeted quality improvements and bugfixes. diff --git a/app/btmesh/documentation/slBtMesh_docContent.xml b/app/btmesh/documentation/slBtMesh_docContent.xml index 7a435b2fc5..8ce4ac4f1e 100644 --- a/app/btmesh/documentation/slBtMesh_docContent.xml +++ b/app/btmesh/documentation/slBtMesh_docContent.xml @@ -1,6 +1,6 @@ - + Includes detailed information on using the Gecko Bootloader with Silicon Labs Bluetooth applications. It supplements the general Gecko Bootloader implementation information provided in UG489: Silicon Labs Gecko Bootloader User's Guide. @@ -8,7 +8,7 @@ - + Describes the Wi-Fi impact on Bluetooth and methods to improve Bluetooth coexistence with Wi-Fi. Explains design considerations to improve coexistence without direct interaction between Bluetooth and Wi-Fi radios. These techniques are applicable to the EFR32MGx and EFR32BGx series. Discusses the Silicon Labs Packet Traffic Arbitration (PTA) support to coordinate 2.4GHz RF traffic for co-located Bluetooth and Wi-Fi radios. @@ -16,7 +16,7 @@ - + Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. @@ -24,14 +24,14 @@ - + Details methods for testing Bluetooth mesh network performance; results are intended to provide guidance on design practices and principles as well as expected field performance results. - + Reviews the Zigbee, Thread, and Bluetooth mesh networks to evaluate their differences in performance and behavior. @@ -39,7 +39,7 @@ - + Describes how to lock and unlock the debug access of EFR32 Gecko Series 2 devices. Many aspects of the debug access, including the secure debug unlock are described. The Debug Challenge Interface (DCI) and Secure Engine (SE) Mailbox Interface for locking and unlocking debug access are also included. @@ -47,7 +47,7 @@ - + Contains detailed information on configuring and using the Secure Boot with hardware Root of Trust and Secure Loader on Series 2 devices, including how to provision the signing key. This is a companion document to UG489: Silicon Labs Gecko Bootloader User's Guide. @@ -55,7 +55,7 @@ - + Details on programming, provisioning, and configuring Series 2 devices in production environments. Covers Secure Engine Subsystem of Series 2 devices, which runs easily upgradeable Secure Engine (SE) or Virtual Secure Engine (VSE) firmware. @@ -63,7 +63,7 @@ - + How to program, provision, and configure the anti-tamper module on EFR32 Series 2 devices with Secure Vault. @@ -71,7 +71,7 @@ - + Describes how to configure the NCP target and how to program the NCP host when using the Bluetooth Stack in Network Co-Processor mode @@ -79,7 +79,7 @@ - + Reviews performing radio frequency physical layer evaluation with EFR32BG SoCs and BGM modules using the Direct Test Mode protocol in Bluetooth SDK v3.x. @@ -87,7 +87,7 @@ - + How to authenticate an EFR32 Series 2 device with Secure Vault, using secure device certificates and signatures. @@ -95,7 +95,7 @@ - + How to securely "wrap" keys in EFR32 Series 2 devices with Secure Vault, so they can be stored in non-volatile storage. @@ -103,28 +103,28 @@ - + Describes the differences between using Bluetooth mesh SDK v1.x in Simplicity Studio 4 and using Bluetooth mesh SDK v2.x in Simplicity Studio 5. Outlines the steps needed to migrate a v1.x project to v2.x. - + Discusses the basics of Bluetooth mesh required to understand the Bluetooth mesh lighting example, and walks through key aspects of the application source code. - + Discusses the basics of sensor models and describe the related sample applications in the SDK that create a wireless network of sensors and sensor clients using Bluetooth mesh technology. - + Describes how to provision and configure Series 2 devices through the DCI and SWD. @@ -132,14 +132,14 @@ - + Includes the results of the interoperability testing of Silicon Labs' ICs and Bluetooth Mesh stack with Android and iOS smart phones. - + Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. @@ -147,21 +147,21 @@ - + Describes Low Power Node (LPN) and Friend operation and the parameters related to power consumption. It also describes how to measure the power consumption of EFR32BG devices acting as Bluetooth mesh LPNs using the setup and procedures recommended in AN969: Measuring Power Consumption in Wireless Gecko Devices. - + Describes in detail how the Bluetooth mesh toplogy can influence network operation. Provides tips on how to tune your network and its nodes to achieve best performance. - + Describes using Simplicity Studio 5's Network Analyzer to debug Bluetooth Mesh and Low Energy applications. It can be read jointly with AN958: Debugging and Programming Interfaces for Customer Designs for more information on using Packet Trace Interface with custom hardware. @@ -169,21 +169,21 @@ - + Provides background information on the sequence number and IV index in a Bluetooth mesh network and the IV Update and IV Index Recovery procedures. It also discusses how to implement IV Update functionality in a Bluetooth mesh application. - + Provides background information on the Bluetooth Mesh Device Firmware Update (DFU) feature, including the BLOB transfer, the DFU roles in a Bluetooth mesh network, the models required for these roles, and the firmware update process. - + Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. @@ -191,91 +191,91 @@ - + Describes the Bluetooth Mesh Remote Provisioning feature and provides an example walkthrough. With the feature, a device can be provisioned without a direct radio connection between the provisioner and the unprovisioned node. - + Describes the bootloader configurations and the device firmware update (DFU) models in the SDK's example projects, and walks through a firmware update demonstration. - + The NCP Host Provisioner example demonstrates how to run a provisioner on a computer with a NCP node connected. The user can provision, configure, and reset other nodes through the NCP node. - + Describes how certificates are used to establish the authenticity of devices wishing to join a mesh network. - + Describes the Bluetooth Mesh Advertising Extensions feature. The non-standard Bluetooth Mesh modification achieves better performance through utilizing the Bluetooth 5 Advertising Extensions feature, which allows sending much larger advertisement packets. - + Walks through a device firmware update demonstration using the DFU Python script. The script is an NCP host application that requires an NCP node connected. - + Describes the following Networked Lighting Control (NLC) profiles: ambient light sensor, basic scene selector, dimming control, basic lightness controller, and occupancy sensor. - + Provides an overview and hyperlinks to all packaged documentation. - + Describes how to get started with Bluetooth mesh development using the Bluetooth Mesh Software Development Kit (SDK) version 4.x and higher, and Simplicity Studio 5 with a compatible wireless starter kit. Contains information about features specific to Bluetooth mesh specification version 1.1. - + Contains a comprehensive list of APIs used to interface to the Silicon Labs Bluetooth Mesh stack. - + A reference for those developing C-based applications for the Silicon Labs EFR32 products using the Silicon Labs Bluetooth mesh stack. A companion to UG434: Silicon Labs Bluetooth C Application Developers Guide for SDK v3.x containing content specific to Bluetooth mesh application development. Covers Bluetooth mesh stack architecture, application development flow, use and limitations of the MCU core and peripherals, stack configuration options, and stack resource usage. - + Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the Silicon Labs Bluetooth mesh SDK and associated utilities, including added/deleted/deprecated features/API, and lists fixed and known issues. - + A detailed overview of the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform includes EMLIB, EMDRV, RAIL Library, NVM3, and the component-based infrastructure. @@ -283,7 +283,7 @@ - + Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. @@ -291,7 +291,7 @@ - + Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader as well as legacy Ember and Bluetooth bootloaders, and describes the file formats used by each. @@ -299,7 +299,7 @@ - + Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: Simulated EEPROM, PS Store, and NVM3. @@ -307,7 +307,7 @@ - + Describes methods to improve the coexistence of 2.4 GHz IEEE 802.11b/g/n Wi-Fi and other 2.4 GHz radios such as Bluetooth, Bluetooth Mesh, Bluetooth Low Energy, and IEEE 802.15.4-based radios such as Zigbee and OpenThread. @@ -315,7 +315,7 @@ - + Reviews using this XML-based mark-up language to describe the Bluetooth GATT database, configure access and security properties, and include the GATT database as part of the firmware. @@ -323,7 +323,7 @@ - + Describes how and when to use Simplicity Commander's Command-Line Interface. @@ -331,7 +331,7 @@ - + Provides the information needed to effectively use the Bluetooth GATT Configurator provided as a part of Simplicity Studio 5 with Bluetooth SDK 3.x and higher and Bluetooth Mesh SDK 2.x and higher. @@ -339,14 +339,14 @@ - + Describes the components, stack, and DCD (Device Composition Data) configuration options for the Bluetooth Mesh v2.x SDK. - + Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. @@ -354,7 +354,7 @@ - + Introduces Simplicity Studio 5 Bluetooth Mesh SDK components. Describes how to modify the Device Composition Data (DCD), including device information, elements, and models. Describes the stack configuration options to optimize RAM and persistent storage usage. diff --git a/app/btmesh/example/btmesh_ncp_empty/dcd_config.btmeshconf b/app/btmesh/example/btmesh_ncp_empty/dcd_config.btmeshconf index 18d9de7b05..99d83bae74 100644 --- a/app/btmesh/example/btmesh_ncp_empty/dcd_config.btmeshconf +++ b/app/btmesh/example/btmesh_ncp_empty/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0000", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Primary Element", diff --git a/app/btmesh/example/btmesh_ncp_empty/dcd_config_v1_1.btmeshconf b/app/btmesh/example/btmesh_ncp_empty/dcd_config_v1_1.btmeshconf index 451e2b19eb..a65d097c3b 100644 --- a/app/btmesh/example/btmesh_ncp_empty/dcd_config_v1_1.btmeshconf +++ b/app/btmesh/example/btmesh_ncp_empty/dcd_config_v1_1.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0000", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Primary Element", diff --git a/app/btmesh/example/btmesh_ncp_empty/dcd_config_xg22.btmeshconf b/app/btmesh/example/btmesh_ncp_empty/dcd_config_xg22.btmeshconf index 649714ab70..7407313ca6 100644 --- a/app/btmesh/example/btmesh_ncp_empty/dcd_config_xg22.btmeshconf +++ b/app/btmesh/example/btmesh_ncp_empty/dcd_config_xg22.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0000", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/btmesh/example/btmesh_soc_dfu_distributor/dcd_config.btmeshconf b/app/btmesh/example/btmesh_soc_dfu_distributor/dcd_config.btmeshconf index d873fa225e..40dac8abca 100644 --- a/app/btmesh/example/btmesh_soc_dfu_distributor/dcd_config.btmeshconf +++ b/app/btmesh/example/btmesh_soc_dfu_distributor/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x000c", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/btmesh/example/btmesh_soc_empty/dcd_config.btmeshconf b/app/btmesh/example/btmesh_soc_empty/dcd_config.btmeshconf index e424ef941a..cd8c710f08 100644 --- a/app/btmesh/example/btmesh_soc_empty/dcd_config.btmeshconf +++ b/app/btmesh/example/btmesh_soc_empty/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0001", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/btmesh/example/btmesh_soc_empty_cbp/dcd_config.btmeshconf b/app/btmesh/example/btmesh_soc_empty_cbp/dcd_config.btmeshconf index c4be5f169a..facb681aa4 100644 --- a/app/btmesh/example/btmesh_soc_empty_cbp/dcd_config.btmeshconf +++ b/app/btmesh/example/btmesh_soc_empty_cbp/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x000d", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/btmesh/example/btmesh_soc_light_ctl/dcd_config.btmeshconf b/app/btmesh/example/btmesh_soc_light_ctl/dcd_config.btmeshconf index bc2ef74f9c..fcee98064e 100644 --- a/app/btmesh/example/btmesh_soc_light_ctl/dcd_config.btmeshconf +++ b/app/btmesh/example/btmesh_soc_light_ctl/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0017", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/btmesh/example/btmesh_soc_light_hsl/dcd_config.btmeshconf b/app/btmesh/example/btmesh_soc_light_hsl/dcd_config.btmeshconf index 58a4a7f22e..b1bf83549a 100644 --- a/app/btmesh/example/btmesh_soc_light_hsl/dcd_config.btmeshconf +++ b/app/btmesh/example/btmesh_soc_light_hsl/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0018", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/btmesh/example/btmesh_soc_nlc_basic_lightness_controller/dcd_config.btmeshconf b/app/btmesh/example/btmesh_soc_nlc_basic_lightness_controller/dcd_config.btmeshconf index 277c06fecb..7fed56a78b 100644 --- a/app/btmesh/example/btmesh_soc_nlc_basic_lightness_controller/dcd_config.btmeshconf +++ b/app/btmesh/example/btmesh_soc_nlc_basic_lightness_controller/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x000e", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/btmesh/example/btmesh_soc_nlc_basic_scene_selector/dcd_config.btmeshconf b/app/btmesh/example/btmesh_soc_nlc_basic_scene_selector/dcd_config.btmeshconf index 884a3997bd..c14f4bb517 100644 --- a/app/btmesh/example/btmesh_soc_nlc_basic_scene_selector/dcd_config.btmeshconf +++ b/app/btmesh/example/btmesh_soc_nlc_basic_scene_selector/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0013", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/btmesh/example/btmesh_soc_nlc_basic_scene_selector/dcd_config_low_power.btmeshconf b/app/btmesh/example/btmesh_soc_nlc_basic_scene_selector/dcd_config_low_power.btmeshconf index 55654a9ff4..9c34aa8146 100644 --- a/app/btmesh/example/btmesh_soc_nlc_basic_scene_selector/dcd_config_low_power.btmeshconf +++ b/app/btmesh/example/btmesh_soc_nlc_basic_scene_selector/dcd_config_low_power.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0014", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/btmesh/example/btmesh_soc_nlc_dimming_control/dcd_config.btmeshconf b/app/btmesh/example/btmesh_soc_nlc_dimming_control/dcd_config.btmeshconf index 9305e10f8e..d765473930 100644 --- a/app/btmesh/example/btmesh_soc_nlc_dimming_control/dcd_config.btmeshconf +++ b/app/btmesh/example/btmesh_soc_nlc_dimming_control/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x000f", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/btmesh/example/btmesh_soc_nlc_dimming_control/dcd_config_low_power.btmeshconf b/app/btmesh/example/btmesh_soc_nlc_dimming_control/dcd_config_low_power.btmeshconf index 0c60b54eab..71da2565cb 100644 --- a/app/btmesh/example/btmesh_soc_nlc_dimming_control/dcd_config_low_power.btmeshconf +++ b/app/btmesh/example/btmesh_soc_nlc_dimming_control/dcd_config_low_power.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0010", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/btmesh/example/btmesh_soc_nlc_sensor_ambient_light/dcd_config.btmeshconf b/app/btmesh/example/btmesh_soc_nlc_sensor_ambient_light/dcd_config.btmeshconf index 346d9faa78..fcf4aad014 100644 --- a/app/btmesh/example/btmesh_soc_nlc_sensor_ambient_light/dcd_config.btmeshconf +++ b/app/btmesh/example/btmesh_soc_nlc_sensor_ambient_light/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0011", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/btmesh/example/btmesh_soc_nlc_sensor_occupancy/dcd_config.btmeshconf b/app/btmesh/example/btmesh_soc_nlc_sensor_occupancy/dcd_config.btmeshconf index 6711a19959..61e0eefeeb 100644 --- a/app/btmesh/example/btmesh_soc_nlc_sensor_occupancy/dcd_config.btmeshconf +++ b/app/btmesh/example/btmesh_soc_nlc_sensor_occupancy/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0012", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/btmesh/example/btmesh_soc_sensor_client/dcd_config.btmeshconf b/app/btmesh/example/btmesh_soc_sensor_client/dcd_config.btmeshconf index 048b1f9853..9a6661c7ae 100644 --- a/app/btmesh/example/btmesh_soc_sensor_client/dcd_config.btmeshconf +++ b/app/btmesh/example/btmesh_soc_sensor_client/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0004", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/btmesh/example/btmesh_soc_sensor_thermometer/dcd_config.btmeshconf b/app/btmesh/example/btmesh_soc_sensor_thermometer/dcd_config.btmeshconf index cff712b600..591bcf9478 100644 --- a/app/btmesh/example/btmesh_soc_sensor_thermometer/dcd_config.btmeshconf +++ b/app/btmesh/example/btmesh_soc_sensor_thermometer/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0019", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/btmesh/example/btmesh_soc_switch_ctl/dcd_config.btmeshconf b/app/btmesh/example/btmesh_soc_switch_ctl/dcd_config.btmeshconf index 0870c88c05..3e990d69a8 100644 --- a/app/btmesh/example/btmesh_soc_switch_ctl/dcd_config.btmeshconf +++ b/app/btmesh/example/btmesh_soc_switch_ctl/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0015", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/btmesh/example/btmesh_soc_switch_ctl/dcd_config_low_power.btmeshconf b/app/btmesh/example/btmesh_soc_switch_ctl/dcd_config_low_power.btmeshconf index 894c8a2685..b9e3b0851e 100644 --- a/app/btmesh/example/btmesh_soc_switch_ctl/dcd_config_low_power.btmeshconf +++ b/app/btmesh/example/btmesh_soc_switch_ctl/dcd_config_low_power.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0016", - "vid": "0x0601", + "vid": "0x0610", "elements": [ { "name": "Main", diff --git a/app/common/app_common.properties b/app/common/app_common.properties index 416a5bebe8..47c6969565 100644 --- a/app/common/app_common.properties +++ b/app/common/app_common.properties @@ -2,9 +2,9 @@ id=com.silabs.sdk.platform label=Platform description=Platform -version=4.4.1.0 -dependantSdkVersion=4.4.1 -prop.subLabel=Platform\\ 4.4.1.0 +version=4.4.2.0 +dependantSdkVersion=4.4.2 +prop.subLabel=Platform\\ 4.4.2.0 # General properties are prepended with "prop." prop.file.templatesFile=platform_evaluation_templates.xml platform_experimental_templates.xml builtin_templates.xml platform_production_templates.xml platform_internal_templates.xml diff --git a/app/common/platform_production_demos.xml b/app/common/platform_production_demos.xml index fd363e4d21..b41e9c49f2 100644 --- a/app/common/platform_production_demos.xml +++ b/app/common/platform_production_demos.xml @@ -6,7 +6,7 @@ - + @@ -17,7 +17,7 @@ - + @@ -28,7 +28,7 @@ - + @@ -39,7 +39,7 @@ - + @@ -50,7 +50,7 @@ - + @@ -61,7 +61,7 @@ - + @@ -72,7 +72,7 @@ - + @@ -83,7 +83,7 @@ - + @@ -94,7 +94,7 @@ - + @@ -105,7 +105,7 @@ - + @@ -116,7 +116,7 @@ - + @@ -127,7 +127,7 @@ - + @@ -138,7 +138,7 @@ - + @@ -149,7 +149,7 @@ - + @@ -160,7 +160,7 @@ - + @@ -171,7 +171,7 @@ - + @@ -182,7 +182,7 @@ - + @@ -193,7 +193,7 @@ - + @@ -204,7 +204,7 @@ - + @@ -215,7 +215,7 @@ - + @@ -226,7 +226,7 @@ - + @@ -237,7 +237,7 @@ - + @@ -248,7 +248,7 @@ - + @@ -259,7 +259,7 @@ - + @@ -270,7 +270,7 @@ - + @@ -281,7 +281,7 @@ - + @@ -292,7 +292,7 @@ - + @@ -303,7 +303,7 @@ - + @@ -314,7 +314,7 @@ - + @@ -325,7 +325,7 @@ - + @@ -336,7 +336,7 @@ - + @@ -347,7 +347,7 @@ - + @@ -358,7 +358,7 @@ - + @@ -369,7 +369,7 @@ - + @@ -380,7 +380,7 @@ - + @@ -391,7 +391,7 @@ - + @@ -402,7 +402,7 @@ - + @@ -413,7 +413,7 @@ - + @@ -424,7 +424,7 @@ - + @@ -435,7 +435,7 @@ - + @@ -446,7 +446,7 @@ - + @@ -457,7 +457,7 @@ - + @@ -468,7 +468,7 @@ - + @@ -479,7 +479,7 @@ - + @@ -490,7 +490,7 @@ - + @@ -501,7 +501,7 @@ - + @@ -512,7 +512,7 @@ - + @@ -523,7 +523,7 @@ - + @@ -534,7 +534,7 @@ - + @@ -545,7 +545,7 @@ - + @@ -556,7 +556,7 @@ - + @@ -567,7 +567,7 @@ - + @@ -578,7 +578,7 @@ - + @@ -589,7 +589,7 @@ - + @@ -600,7 +600,7 @@ - + @@ -611,7 +611,7 @@ - + @@ -622,7 +622,7 @@ - + @@ -633,7 +633,7 @@ - + @@ -644,7 +644,7 @@ - + @@ -655,7 +655,7 @@ - + @@ -666,7 +666,7 @@ - + @@ -677,7 +677,7 @@ - + @@ -688,7 +688,7 @@ - + @@ -699,7 +699,7 @@ - + @@ -710,7 +710,7 @@ - + @@ -721,7 +721,7 @@ - + @@ -732,7 +732,7 @@ - + @@ -743,7 +743,7 @@ - + @@ -754,7 +754,7 @@ - + @@ -765,7 +765,7 @@ - + @@ -776,7 +776,7 @@ - + @@ -787,7 +787,7 @@ - + @@ -798,7 +798,7 @@ - + @@ -809,7 +809,7 @@ - + @@ -820,7 +820,7 @@ - + @@ -831,7 +831,7 @@ - + @@ -842,7 +842,7 @@ - + @@ -853,7 +853,7 @@ - + @@ -864,7 +864,7 @@ - + @@ -875,7 +875,7 @@ - + @@ -886,7 +886,7 @@ - + @@ -897,7 +897,7 @@ - + @@ -908,7 +908,7 @@ - + @@ -919,7 +919,7 @@ - + @@ -930,7 +930,7 @@ - + @@ -941,7 +941,7 @@ - + @@ -952,7 +952,7 @@ - + @@ -963,7 +963,7 @@ - + @@ -974,7 +974,7 @@ - + @@ -985,7 +985,7 @@ - + @@ -996,7 +996,7 @@ - + @@ -1007,7 +1007,7 @@ - + @@ -1018,7 +1018,7 @@ - + @@ -1029,7 +1029,7 @@ - + @@ -1040,7 +1040,7 @@ - + @@ -1051,7 +1051,7 @@ - + @@ -1062,7 +1062,7 @@ - + @@ -1073,7 +1073,7 @@ - + @@ -1084,7 +1084,7 @@ - + @@ -1095,7 +1095,7 @@ - + @@ -1106,7 +1106,7 @@ - + @@ -1117,7 +1117,7 @@ - + @@ -1128,7 +1128,7 @@ - + @@ -1139,7 +1139,7 @@ - + @@ -1150,7 +1150,7 @@ - + @@ -1161,7 +1161,7 @@ - + @@ -1172,7 +1172,7 @@ - + @@ -1183,7 +1183,7 @@ - + @@ -1194,7 +1194,7 @@ - + @@ -1205,7 +1205,7 @@ - + @@ -1216,7 +1216,7 @@ - + @@ -1227,7 +1227,7 @@ - + @@ -1238,7 +1238,7 @@ - + @@ -1249,7 +1249,7 @@ - + @@ -1260,7 +1260,7 @@ - + @@ -1271,7 +1271,7 @@ - + @@ -1282,7 +1282,7 @@ - + @@ -1293,7 +1293,7 @@ - + @@ -1304,7 +1304,7 @@ - + @@ -1315,7 +1315,7 @@ - + @@ -1326,7 +1326,7 @@ - + @@ -1337,7 +1337,7 @@ - + @@ -1348,7 +1348,7 @@ - + @@ -1359,7 +1359,7 @@ - + @@ -1370,7 +1370,7 @@ - + @@ -1381,7 +1381,7 @@ - + @@ -1392,7 +1392,7 @@ - + @@ -1403,7 +1403,7 @@ - + @@ -1414,7 +1414,7 @@ - + @@ -1425,7 +1425,7 @@ - + @@ -1436,7 +1436,7 @@ - + @@ -1447,7 +1447,7 @@ - + @@ -1458,7 +1458,7 @@ - + @@ -1469,7 +1469,7 @@ - + @@ -1480,7 +1480,7 @@ - + @@ -1491,7 +1491,7 @@ - + @@ -1502,7 +1502,18 @@ - + + + + + + + This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + @@ -1513,7 +1524,7 @@ - + @@ -1524,7 +1535,7 @@ - + @@ -1535,7 +1546,7 @@ - + @@ -1546,7 +1557,7 @@ - + @@ -1557,7 +1568,7 @@ - + @@ -1568,7 +1579,7 @@ - + @@ -1579,7 +1590,7 @@ - + @@ -1590,7 +1601,7 @@ - + @@ -1601,7 +1612,7 @@ - + @@ -1612,7 +1623,7 @@ - + diff --git a/app/common/platform_production_templates.xml b/app/common/platform_production_templates.xml index 8933e16a11..00d1f5a640 100644 --- a/app/common/platform_production_templates.xml +++ b/app/common/platform_production_templates.xml @@ -6,7 +6,7 @@ - + @@ -22,7 +22,7 @@ - + @@ -38,7 +38,7 @@ - + @@ -53,7 +53,7 @@ - + @@ -68,7 +68,7 @@ - + @@ -83,7 +83,7 @@ - + @@ -98,7 +98,7 @@ - + @@ -113,7 +113,7 @@ - + @@ -128,7 +128,7 @@ - + @@ -173,7 +173,7 @@ - + @@ -188,7 +188,7 @@ - + @@ -203,7 +203,7 @@ - + @@ -218,7 +218,7 @@ - + @@ -248,7 +248,7 @@ - + @@ -263,7 +263,7 @@ - + @@ -278,7 +278,7 @@ - + @@ -293,7 +293,7 @@ - + @@ -308,7 +308,7 @@ - + @@ -323,7 +323,7 @@ - + @@ -338,7 +338,7 @@ - + @@ -353,7 +353,7 @@ - + @@ -368,7 +368,7 @@ - + @@ -443,7 +443,7 @@ - + @@ -458,7 +458,7 @@ - + @@ -473,7 +473,7 @@ - + @@ -488,7 +488,7 @@ - + @@ -503,7 +503,7 @@ - + @@ -533,7 +533,7 @@ - + @@ -563,7 +563,7 @@ - + @@ -593,7 +593,7 @@ - + @@ -608,7 +608,7 @@ - + @@ -623,7 +623,7 @@ - + @@ -638,7 +638,7 @@ - + @@ -653,7 +653,7 @@ - + @@ -668,7 +668,7 @@ - + @@ -683,7 +683,7 @@ - + @@ -698,7 +698,7 @@ - + @@ -713,7 +713,7 @@ - + @@ -728,7 +728,7 @@ - + @@ -743,7 +743,7 @@ - + @@ -758,7 +758,7 @@ - + @@ -773,7 +773,7 @@ - + @@ -788,7 +788,7 @@ - + @@ -803,7 +803,7 @@ - + @@ -833,7 +833,7 @@ - + @@ -848,7 +848,7 @@ - + @@ -863,7 +863,7 @@ - + @@ -878,7 +878,7 @@ - + @@ -923,7 +923,7 @@ - + @@ -938,7 +938,7 @@ - + @@ -953,7 +953,7 @@ - + @@ -983,7 +983,7 @@ - + @@ -998,7 +998,7 @@ - + @@ -1013,7 +1013,7 @@ - + @@ -1058,7 +1058,7 @@ - + @@ -1073,7 +1073,7 @@ - + @@ -1088,7 +1088,7 @@ - + @@ -1103,7 +1103,7 @@ - + @@ -1118,7 +1118,7 @@ - + @@ -1133,7 +1133,7 @@ - + @@ -1148,7 +1148,7 @@ - + @@ -1163,7 +1163,7 @@ - + @@ -1178,7 +1178,7 @@ - + @@ -1193,7 +1193,7 @@ - + @@ -1208,7 +1208,7 @@ - + @@ -1223,7 +1223,7 @@ - + @@ -1238,7 +1238,7 @@ - + diff --git a/app/common/util/app_button_press/app_button_press.c b/app/common/util/app_button_press/app_button_press.c index d73292904d..3bb3f23562 100644 --- a/app/common/util/app_button_press/app_button_press.c +++ b/app/common/util/app_button_press/app_button_press.c @@ -3,7 +3,7 @@ * @brief Button Press source code ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -28,6 +28,7 @@ * ******************************************************************************/ +#include "sl_common.h" #include "sl_sleeptimer.h" #include "app_button_press.h" #include "app_button_press_config.h" diff --git a/app/flex/documentation/release-highlights.txt b/app/flex/documentation/release-highlights.txt old mode 100644 new mode 100755 index 1bb8383a46..c6f286973b --- a/app/flex/documentation/release-highlights.txt +++ b/app/flex/documentation/release-highlights.txt @@ -1,2 +1,2 @@ -Flex SDK 3.7.1.0 -- Targeted quality improvements and bug fixes \ No newline at end of file +Flex SDK 3.7.2.0 +- Targeted quality improvements and bug fixes. \ No newline at end of file diff --git a/app/flex/documentation/slFlex_docContent.xml b/app/flex/documentation/slFlex_docContent.xml index f0c2dbb5a3..13317efa67 100644 --- a/app/flex/documentation/slFlex_docContent.xml +++ b/app/flex/documentation/slFlex_docContent.xml @@ -1,20 +1,20 @@ - + Includes detailed information on using the Silicon Labs Gecko Bootloader with Connect. It supplements the general Gecko Bootloader implementation information provided in UG489: Silicon Labs Gecko Bootloader User's Guide. - + Describes using the Flex SDK for Wireless M-Bus development on EFR32 Wireless Geckos. Includes features and limitations as well as examples. - + Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. @@ -22,7 +22,7 @@ - + Describes tokens and shows how to use them for non-volatile data storage in EmberZNet PRO and Silicon Labs Flex applications. @@ -30,7 +30,7 @@ - + Describes how to lock and unlock the debug access of EFR32 Gecko Series 2 devices. Many aspects of the debug access, including the secure debug unlock are described. The Debug Challenge Interface (DCI) and Secure Engine (SE) Mailbox Interface for locking and unlocking debug access are also included. @@ -38,7 +38,7 @@ - + Contains detailed information on configuring and using the Secure Boot with hardware Root of Trust and Secure Loader on Series 2 devices, including how to provision the signing key. This is a companion document to UG489: Silicon Labs Gecko Bootloader User's Guide. @@ -46,7 +46,7 @@ - + Details on programming, provisioning, and configuring Series 2 devices in production environments. Covers Secure Engine Subsystem of Series 2 devices, which runs easily upgradeable Secure Engine (SE) or Virtual Secure Engine (VSE) firmware. @@ -54,14 +54,14 @@ - + Describes the distinguishing features of different EFR32 families that are most relevant to porting proprietary wireless applications between them. Provides insight that is also helpful when selecting an initial target platform for proprietary wireless solutions. - + How to program, provision, and configure the anti-tamper module on EFR32 Series 2 devices with Secure Vault. @@ -69,21 +69,21 @@ - + Illustrates reducing power consumption in a Connect v3.x application using the sensor example. - + Describes the radio configurator GUI for RAIL framework applications in Simplicity Studio 5. With it, you can create standard or custom radio configurations on which to run your RAIL-based applications. The role of each GUI item is explained. - + How to authenticate an EFR32 Series 2 device with Secure Vault, using secure device certificates and signatures. @@ -91,7 +91,7 @@ - + How to securely "wrap" keys in EFR32 Series 2 devices with Secure Vault, so they can be stored in non-volatile storage. @@ -99,7 +99,7 @@ - + Describes how to provision and configure Series 2 devices through the DCI and SWD. @@ -107,7 +107,7 @@ - + Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. @@ -115,7 +115,7 @@ - + Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. @@ -123,14 +123,14 @@ - + Describes using the Flex SDK for 802.15.4 development on EFR32 wireless parts. - + Describes how to initialize a piece of custom hardware (a 'device') based on the EFR32MG and EFR32FG families so that it interfaces correctly with a network stack. The same procedures can be used to restore devices whose settings have been corrupted or erased. @@ -138,49 +138,49 @@ - + Describes using RAILTest to evaluate radio functionality, as well as peripherals, deep sleep states, etc. With it you can fully evaluate the receiving and transmitting performance and test RF functionality of development kit hardware or custom hardware. - + Provides an overview and hyperlinks to all packaged documentation. - + Provides basic information on configuring, building, and installing applications using Silicon Labs Connect and RAIL, the two development paths in the Silicon Labs Proprietary Flex SDK v3.x. - + Contains a comprehensive list of APIs used to interface to the Silicon Labs Connect stack. - + Contains a comprehensive list of APIs used to interface to the Silicon Labs RAIL library. - + Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the SiliconLabs Flex SDK, including added/deleted/deprecated features/API. Reviews fixed and known issues. - + A detailed overview of the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform includes EMLIB, EMDRV, RAIL Library, NVM3, and the component-based infrastructure. @@ -188,7 +188,7 @@ - + Introduces some fundamental concepts of wireless networking. These concepts are referred to in other Fundamentals documents. If you are new to wireless networking, you should read this document first. @@ -196,7 +196,7 @@ - + Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. @@ -204,7 +204,7 @@ - + Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader as well as legacy Ember and Bluetooth bootloaders, and describes the file formats used by each. @@ -212,7 +212,7 @@ - + Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: Simulated EEPROM, PS Store, and NVM3. @@ -220,21 +220,21 @@ - + Describes the features and functions of the Silicon Labs Connect stack, including its device types, network topologies, and its 'building block' development methodology using plugins. - + Describes the features and functions of Silicon Labs RAIL (Radio Abstraction Interface Layer). RAIL provides an intuitive, easily-customizable radio interface layer that is designed to support proprietary or standards-based wireless protocols. - + Describes the four multiprotocol modes, discusses considerations when selecting protocols for multiprotocol implementations, and reviews the Radio Scheduler, a required component of a dynamic multiprotocol solution. @@ -242,7 +242,7 @@ - + Describes how and when to use Simplicity Commander's Command-Line Interface. @@ -250,7 +250,7 @@ - + Describes how to implement a dynamic multiprotocol solution. @@ -258,91 +258,91 @@ - + Describes the functionality available in the RAILtest application. - + Introduces the Connect User's Guide for the Flex SDK v3.x. - + Introduces the IEEE 802.15.4 standard on which Connect v3.x is based. - + Describes the architecture of the Silicon Labs Connect stack v3.x an how it implements IEEE 802.15.4. - + Describes how to use components, callbacks, and events on top of the Gecko Platform application framework to configure features and application behavior. - + Describes the process to implement a Connect-based application on top of one of the supported Real Time Operating Systems (RTOS). - + Explains standalone (serial) and application (OTA) bootloader options available for use within Connect v3.x -based applications - + Describes the features available in Connect v3.x to reduce power consumption. Using those features is described in AN1252: Building Low Power Networks with the Silicon Labs Connect Stack v3.x. - + Describes how to run the Silicon Labs Connect stack in Network Co-Processor (NCP) mode, where the NCP runs on the EFR32 while the Host application and the Co-processor Communication daemon (CPCd) run on the Host device. - + Introduces the long-range radio profile, describes its development, and examines underlying details that enable it to realize extended range. Instructions for using example applications are included. - + Describes how to test long range performance on EFR32 Series 2 devices using Simplicity Studio 5 and Silicon Labs development hardware. Instructions for using example applications are included. - + Provides an easy way to evaluate the link budget of the Wireless Gecko EFR32 devices using Silicon Labs RAIL (RAIL) by performing a range test between two nodes using Range Test, a standalone test application. The range test demo implements Packet Error Rate (PER) measurement. - + Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. diff --git a/app/flex/esf.properties b/app/flex/esf.properties index e8741efd01..20fc97b856 100644 --- a/app/flex/esf.properties +++ b/app/flex/esf.properties @@ -3,8 +3,8 @@ id=com.silabs.stack.flex label=Flex SDK description=Flex Software Development Kit -version=3.7.1.0 -prop.subLabel=Flex\\ 3.7.1.0 +version=3.7.2.0 +prop.subLabel=Flex\\ 3.7.2.0 # General properties are prepended with "prop." prop.file.templatesFile=flex_production_templates.xml flex_demos_only_templates.xml flex_internal_templates.xml diff --git a/app/flex/flex_demos_only_demos.xml b/app/flex/flex_demos_only_demos.xml index 76c1e261be..db84284be5 100644 --- a/app/flex/flex_demos_only_demos.xml +++ b/app/flex/flex_demos_only_demos.xml @@ -5,7 +5,7 @@ - + @@ -15,7 +15,7 @@ - + diff --git a/app/flex/flex_production_demos.xml b/app/flex/flex_production_demos.xml index 30bbd7eadd..d3b1dd99c4 100644 --- a/app/flex/flex_production_demos.xml +++ b/app/flex/flex_production_demos.xml @@ -5,7 +5,7 @@ - + @@ -15,7 +15,7 @@ - + @@ -25,7 +25,7 @@ - + @@ -35,7 +35,7 @@ - + @@ -45,7 +45,7 @@ - + @@ -55,7 +55,7 @@ - + @@ -65,7 +65,7 @@ - + @@ -75,7 +75,7 @@ - + @@ -85,7 +85,7 @@ - + @@ -95,7 +95,7 @@ - + @@ -105,7 +105,7 @@ - + @@ -115,7 +115,7 @@ - + @@ -125,7 +125,7 @@ - + @@ -135,7 +135,7 @@ - + @@ -145,7 +145,7 @@ - + @@ -155,7 +155,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -185,7 +185,7 @@ - + @@ -195,7 +195,7 @@ - + @@ -205,7 +205,7 @@ - + @@ -215,7 +215,7 @@ - + @@ -225,7 +225,7 @@ - + @@ -235,7 +235,7 @@ - + @@ -245,7 +245,7 @@ - + @@ -255,7 +255,7 @@ - + @@ -265,7 +265,7 @@ - + @@ -275,7 +275,7 @@ - + @@ -285,7 +285,7 @@ - + @@ -295,7 +295,7 @@ - + @@ -305,7 +305,7 @@ - + @@ -315,7 +315,7 @@ - + @@ -325,7 +325,7 @@ - + @@ -335,7 +335,7 @@ - + @@ -345,7 +345,7 @@ - + @@ -355,7 +355,7 @@ - + @@ -365,18 +365,18 @@ - + - + Range Test BLE and IEEE802.15.4 with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This application demonstrates over the air range of the Silicon Labs boards. 5 predefined PHYs can be used for this: BLE: 125kbps, BLE: 500kbps, BLE: 1Mbps, BLE: 2Mbps, IEEE80215.4: 250kbps. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length defined by the PHY and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given predefined PHY and inspects the packets received. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. Radio related events can be logged on UART on demand. CLI can be used to set and get configuration of the app, and to start and stop it. To get started with CLI send 'help' with a terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, a USB power bank can be used if portability is needed. - + @@ -386,7 +386,7 @@ - + @@ -396,7 +396,7 @@ - + @@ -406,7 +406,7 @@ - + @@ -416,7 +416,7 @@ - + @@ -426,7 +426,7 @@ - + @@ -436,7 +436,7 @@ - + @@ -446,7 +446,7 @@ - + @@ -456,7 +456,7 @@ - + @@ -466,7 +466,7 @@ - + @@ -476,7 +476,7 @@ - + @@ -486,7 +486,7 @@ - + @@ -496,7 +496,7 @@ - + @@ -506,7 +506,7 @@ - + @@ -516,7 +516,7 @@ - + @@ -526,7 +526,7 @@ - + @@ -536,7 +536,7 @@ - + @@ -546,7 +546,7 @@ - + @@ -556,7 +556,7 @@ - + @@ -566,7 +566,7 @@ - + @@ -576,7 +576,7 @@ - + @@ -586,7 +586,7 @@ - + @@ -596,7 +596,7 @@ - + @@ -606,7 +606,7 @@ - + @@ -616,7 +616,7 @@ - + @@ -626,7 +626,7 @@ - + @@ -636,7 +636,7 @@ - + @@ -646,7 +646,7 @@ - + @@ -656,7 +656,7 @@ - + @@ -666,7 +666,7 @@ - + @@ -676,7 +676,7 @@ - + @@ -686,7 +686,7 @@ - + @@ -696,7 +696,7 @@ - + @@ -706,7 +706,7 @@ - + @@ -716,7 +716,7 @@ - + @@ -726,7 +726,7 @@ - + @@ -736,7 +736,7 @@ - + @@ -746,7 +746,7 @@ - + @@ -756,7 +756,7 @@ - + @@ -766,7 +766,7 @@ - + @@ -776,7 +776,7 @@ - + @@ -786,7 +786,7 @@ - + @@ -796,7 +796,7 @@ - + @@ -806,7 +806,7 @@ - + @@ -816,7 +816,7 @@ - + @@ -826,7 +826,7 @@ - + @@ -836,7 +836,7 @@ - + @@ -846,7 +846,7 @@ - + @@ -856,7 +856,7 @@ - + @@ -866,7 +866,7 @@ - + @@ -876,7 +876,7 @@ - + @@ -886,7 +886,7 @@ - + @@ -896,7 +896,7 @@ - + @@ -906,7 +906,7 @@ - + @@ -916,7 +916,7 @@ - + @@ -926,7 +926,7 @@ - + @@ -936,7 +936,7 @@ - + @@ -946,7 +946,7 @@ - + @@ -956,7 +956,7 @@ - + @@ -966,7 +966,7 @@ - + @@ -976,7 +976,7 @@ - + @@ -986,7 +986,7 @@ - + @@ -996,7 +996,7 @@ - + @@ -1006,7 +1006,7 @@ - + @@ -1016,7 +1016,7 @@ - + @@ -1026,7 +1026,7 @@ - + @@ -1036,7 +1036,7 @@ - + @@ -1046,7 +1046,7 @@ - + @@ -1056,7 +1056,7 @@ - + @@ -1066,7 +1066,7 @@ - + @@ -1076,7 +1076,7 @@ - + @@ -1086,7 +1086,7 @@ - + @@ -1096,7 +1096,7 @@ - + @@ -1106,7 +1106,7 @@ - + @@ -1116,7 +1116,7 @@ - + @@ -1126,7 +1126,7 @@ - + @@ -1136,7 +1136,7 @@ - + @@ -1146,7 +1146,7 @@ - + @@ -1156,7 +1156,7 @@ - + @@ -1166,7 +1166,7 @@ - + @@ -1176,7 +1176,7 @@ - + @@ -1186,7 +1186,7 @@ - + diff --git a/app/mcu_example/app_mcu.properties b/app/mcu_example/app_mcu.properties index 6baee33efc..e9cc250282 100644 --- a/app/mcu_example/app_mcu.properties +++ b/app/mcu_example/app_mcu.properties @@ -3,9 +3,9 @@ id=com.silabs.sdk.mcu label=32-bit MCU SDK description=Silicon Labs 32-bit MCU SDK for EFM32 and EZR32 -version=6.6.1.0 +version=6.6.2.0 supportedParts=mcu.arm.efm32.* mcu.arm.ezr32.* .*wgm16.* -prop.subLabel=MCU\\ 6.6.1.0 +prop.subLabel=MCU\\ 6.6.2.0 # General properties are prepended with "prop." prop.file.templatesFile=mcu_production_templates.xml diff --git a/app/mcu_example/documentation/release-highlights.txt b/app/mcu_example/documentation/release-highlights.txt index 129f49e9b5..534de654d0 100644 --- a/app/mcu_example/documentation/release-highlights.txt +++ b/app/mcu_example/documentation/release-highlights.txt @@ -1,2 +1,2 @@ -32-Bit MCU SDK 6.6.1.0 +32-Bit MCU SDK 6.6.2.0 - Underlying platform changes only. \ No newline at end of file diff --git a/app/mcu_example/mcu_production_demos.xml b/app/mcu_example/mcu_production_demos.xml index c9aba28acc..5d0dcfb378 100644 --- a/app/mcu_example/mcu_production_demos.xml +++ b/app/mcu_example/mcu_production_demos.xml @@ -5,7 +5,7 @@ - + @@ -16,7 +16,7 @@ - + @@ -27,7 +27,7 @@ - + @@ -38,7 +38,7 @@ - + @@ -49,7 +49,7 @@ - + @@ -61,7 +61,7 @@ This example shows how to use the Micrium OS network stack with the ETH periphe - + @@ -73,7 +73,7 @@ This example shows how to use the Micrium OS network stack with the ETH periphe - + @@ -84,7 +84,7 @@ You must have the Hall Effect Evaluation kit, Si72xx-WD-Kit, to make use of this - + diff --git a/app/wisun/component/app_core/sl_wisun_app_core.c b/app/wisun/component/app_core/sl_wisun_app_core.c index 3184bdc3e9..edd585128d 100644 --- a/app/wisun/component/app_core/sl_wisun_app_core.c +++ b/app/wisun/component/app_core/sl_wisun_app_core.c @@ -353,6 +353,7 @@ void sl_wisun_disconnected_event_hnd(sl_wisun_evt_t *evt) __CHECK_FOR_STATUS(evt->evt.error.status); _app_wisun_core_set_state(SL_WISUN_APP_CORE_STATE_NETWORK_DISCONNECTED); + _join_state = SL_WISUN_JOIN_STATE_DISCONNECTED; } /* Socket connection lost event handler*/ diff --git a/app/wisun/component/cli_util/sl_wisun_cli_settings.c b/app/wisun/component/cli_util/sl_wisun_cli_settings.c index 0acded20da..0045391423 100644 --- a/app/wisun/component/cli_util/sl_wisun_cli_settings.c +++ b/app/wisun/component/cli_util/sl_wisun_cli_settings.c @@ -323,6 +323,12 @@ sl_status_t app_settings_set_string(const char *value_str, entry_value_str = entry->value; strncpy(entry_value_str, value_str, entry->value_size - 1); entry_value_str[entry->value_size - 1] = '\0'; + if (strlen(value_str) >= entry->value_size) { + printf("Warning: string is too long for %s.%s, truncated to \"%s\"\r\n", + app_settings_domain_str[entry->domain], + entry->key, + entry_value_str); + } return SL_STATUS_OK; } diff --git a/app/wisun/component/ftp/config/sl_ftp_config.h b/app/wisun/component/ftp/config/sl_ftp_config.h index 39189f8400..2caa23d835 100644 --- a/app/wisun/component/ftp/config/sl_ftp_config.h +++ b/app/wisun/component/ftp/config/sl_ftp_config.h @@ -91,10 +91,6 @@ // Default value 256 bytes #define SL_TFTP_CLNT_STACK_SIZE_WORD 256UL -// TFTP address storage size in bytes -// Default value 20 bytes -#define SL_TFTP_ADDR_SIZE 28UL - // TFTP Default remote host address string // Default: "aabb:ccdd::eeff:0011:2233:4455" (dummy) #define SL_TFTP_CLNT_DEFAULT_HOST "aabb:ccdd::eeff:0011:2233:4455" diff --git a/app/wisun/component/ftp/sl_ftp.h b/app/wisun/component/ftp/sl_ftp.h index 1ae652ab9f..9e408834da 100644 --- a/app/wisun/component/ftp/sl_ftp.h +++ b/app/wisun/component/ftp/sl_ftp.h @@ -271,17 +271,22 @@ int32_t sl_tftp_udp_sendto(int32_t sockid, const void *buff, uint32_t len, const int32_t sl_tftp_udp_recvfrom(int32_t sockid, void *buff, uint32_t len, void *src_addr); /**************************************************************************//** - * @brief Get UDP address bytes - * @details Create address bytes from host string and port + * @brief Get UDP address structure + * @details Allocate address structue and set host address and port * @param[in] host Host string * @param[in] port Port - * @param[in,out] dst Destiantion ptr - * @param[in] dst_size Destination size + * @return void * Address structure *****************************************************************************/ -void sl_tftp_udp_get_addr_bytes(const char *host, - uint16_t port, - void * const dst, - size_t dst_size); +void * sl_tftp_udp_get_addr(const char *host, + uint16_t port); + +/**************************************************************************//** + * @brief Free address + * @details Release the allocated address strcutre + * @param[in] addr Address structure + *****************************************************************************/ +void sl_tftp_udp_free_addr(void *addr); + #endif #ifdef __cplusplus diff --git a/app/wisun/component/ftp/sl_tftp_clnt.c b/app/wisun/component/ftp/sl_tftp_clnt.c index 2e0297e493..be19340a56 100644 --- a/app/wisun/component/ftp/sl_tftp_clnt.c +++ b/app/wisun/component/ftp/sl_tftp_clnt.c @@ -623,7 +623,7 @@ static void _rrq_hnd(sl_tftp_clnt_t * const clnt, uint32_t timeout = 0UL; uint16_t pkt_payload_size = 0U; uint16_t block_num = 1U; - static uint8_t host_addr[SL_TFTP_ADDR_SIZE] = { 0U }; + void * host_addr = NULL; int32_t res = SL_FTP_ERROR; sock_id = sl_tftp_udp_socket_create(); @@ -632,7 +632,12 @@ static void _rrq_hnd(sl_tftp_clnt_t * const clnt, return; } - sl_tftp_udp_get_addr_bytes(clnt->host, clnt->port, host_addr, SL_TFTP_ADDR_SIZE); + host_addr = sl_tftp_udp_get_addr(clnt->host, clnt->port); + if (host_addr == NULL) { + sl_tftp_socket_close(sock_id); + printf("[TFTP Address error]\n"); + return; + } pkt_payload_size = _build_packet(&clnt->packet, buff, buff_size); (void) sl_tftp_udp_sendto(sock_id, buff, pkt_payload_size, host_addr); @@ -685,7 +690,7 @@ static void _rrq_hnd(sl_tftp_clnt_t * const clnt, timeout = 0UL; } - + sl_tftp_udp_free_addr(host_addr); sl_tftp_socket_close(sock_id); } @@ -698,7 +703,7 @@ static void _wrq_hnd(sl_tftp_clnt_t * const clnt, uint16_t pkt_payload_size = 0U; uint16_t block_num = 0U; uint16_t required_block_num = 0U; - static uint8_t host_addr[SL_TFTP_ADDR_SIZE] = { 0U }; + void * host_addr = NULL; int32_t res = SL_FTP_ERROR; uint8_t *ptr = NULL; uint32_t remained_size = 0UL; @@ -710,7 +715,12 @@ static void _wrq_hnd(sl_tftp_clnt_t * const clnt, return; } - sl_tftp_udp_get_addr_bytes(clnt->host, clnt->port, host_addr, SL_TFTP_ADDR_SIZE); + host_addr = sl_tftp_udp_get_addr(clnt->host, clnt->port); + if (host_addr == NULL) { + sl_tftp_socket_close(sock_id); + printf("[TFTP Address error]\n"); + return; + } pkt_payload_size = _build_packet(&clnt->packet, buff, buff_size); (void) sl_tftp_udp_sendto(sock_id, buff, pkt_payload_size, host_addr); @@ -718,7 +728,6 @@ static void _wrq_hnd(sl_tftp_clnt_t * const clnt, ptr = (uint8_t *) clnt->ext_data; remained_size = clnt->ext_data_size; required_block_num = remained_size / SL_TFTP_DATA_BLOCK_SIZE + 1U; - sl_tftp_debug("Prepare transfer: 0x%p address, %lu bytes\n", ptr, remained_size); while (timeout < SL_TFTP_CLNT_RECV_TIMEOUT_MS) { sl_tftp_delay_ms(100UL); @@ -740,7 +749,6 @@ static void _wrq_hnd(sl_tftp_clnt_t * const clnt, if (clnt->packet.opcode == SL_TFTP_OPCODE_ACK) { if (!remained_size && block_num == required_block_num) { - sl_tftp_debug("Received last ack\n"); break; } // reset timeout counter @@ -774,7 +782,7 @@ static void _wrq_hnd(sl_tftp_clnt_t * const clnt, sl_tftp_dump_buff(ptr, data_size); #endif } - sl_tftp_debug("Closing WRQ socket\n"); + sl_tftp_udp_free_addr(host_addr); sl_tftp_socket_close(sock_id); } @@ -801,9 +809,8 @@ static void _clnt_thr_fnc(void * args) sl_tftp_delay_ms(100UL); continue; } - sl_tftp_debug("TFTP Client started\n"); - #if defined(SL_TFTP_DEBUG) + sl_tftp_debug("TFTP Client started\n"); sl_tftp_clnt_print_pkt(&clnt.packet); #endif @@ -818,8 +825,10 @@ static void _clnt_thr_fnc(void * args) (void) osEventFlagsClear(clnt.evt_flags, SL_TFTP_EVT_ALL_MSK); (void) osEventFlagsSet(clnt.evt_flags, SL_TFTP_EVT_OP_FINISHED_MSK); - // sl_tftp_socket_close(sock_id); +#if defined(SL_TFTP_DEBUG) sl_tftp_debug("TFTP Client socket closed\n"); +#endif + sl_tftp_delay_ms(100UL); } } diff --git a/app/wisun/component/ftp_posix_port/sl_wisun_ftp_posix_port.c b/app/wisun/component/ftp_posix_port/sl_wisun_ftp_posix_port.c index 30bc10e7c4..63bb805f2f 100644 --- a/app/wisun/component/ftp_posix_port/sl_wisun_ftp_posix_port.c +++ b/app/wisun/component/ftp_posix_port/sl_wisun_ftp_posix_port.c @@ -39,6 +39,8 @@ #include "sl_wisun_app_core_util.h" #include "sl_wisun_types.h" #include "sl_wisun_api.h" +#include "sl_wisun_trace_util.h" + #if SL_FTP_ENABLE_TFTP_PROTOCOL #include "sl_tftp_clnt.h" #endif @@ -224,30 +226,31 @@ int32_t sl_tftp_udp_recvfrom(int32_t sockid, void *buff, uint32_t len, void *src return recvfrom(sockid, buff, len, 0L, (struct sockaddr *)src_addr, &addr_len); } -void sl_tftp_udp_get_addr_bytes(const char *host, - uint16_t port, - void * const dst, - size_t dst_size) + +void * sl_tftp_udp_get_addr(const char *host, + uint16_t port) { - sockaddr_in6_t waddr = { 0U }; + sockaddr_in6_t *waddr = NULL; - if (dst == NULL || !dst_size) { - return; + waddr = (sockaddr_in6_t *)app_wisun_malloc(sizeof(sockaddr_in6_t)); + if (waddr == NULL) { + return NULL; } - if (inet_pton(AF_INET6, host, - &waddr.sin6_addr) == SOCKET_RETVAL_ERROR) { - memset(dst, 0U, dst_size); + if (inet_pton(AF_INET6, host, &waddr->sin6_addr) == SOCKET_RETVAL_ERROR) { + app_wisun_free(waddr); + return NULL; } - waddr.sin6_family = AF_INET6; - waddr.sin6_port = port; + waddr->sin6_family = AF_INET6; + waddr->sin6_port = port; - if (dst_size < sizeof(sockaddr_in6_t)) { - memset(dst, 0U, dst_size); - } else { - memcpy(dst, &waddr, sizeof(sockaddr_in6_t)); - } + return (void *)waddr; } +void sl_tftp_udp_free_addr(void *addr) +{ + app_wisun_free(addr); +} + #endif diff --git a/app/wisun/component/ping/sl_wisun_ping.c b/app/wisun/component/ping/sl_wisun_ping.c index 2e3bb46de3..7cd6de1cd3 100644 --- a/app/wisun/component/ping/sl_wisun_ping.c +++ b/app/wisun/component/ping/sl_wisun_ping.c @@ -443,7 +443,7 @@ static void _ping_task_fnc(void *args) req.remote_addr.sin6_family = AF_INET6; req.remote_addr.sin6_port = htons(SL_WISUN_PING_ICMP_PORT); - sockid = socket(AF_INET6, SOCK_RAW, IPPROTO_ICMP); + sockid = socket(AF_INET6, SOCK_RAW | SOCK_NONBLOCK, IPPROTO_ICMP); if (sockid == SOCKET_INVALID_ID) { _prepare_and_push_failed_response(&resp, SL_WISUN_PING_STATUS_SOCKET_ERROR); diff --git a/app/wisun/documentation/release-highlights.txt b/app/wisun/documentation/release-highlights.txt old mode 100644 new mode 100755 index d82e99e924..67bb5ceb02 --- a/app/wisun/documentation/release-highlights.txt +++ b/app/wisun/documentation/release-highlights.txt @@ -1,2 +1,2 @@ -Wi-SUN SDK 1.9.0 -- Targeted quality improvements and bug fixes \ No newline at end of file +Wi-SUN SDK 1.10.0 +- Targeted quality improvements and bug fixes. \ No newline at end of file diff --git a/app/wisun/documentation/slWi-SUN_docContent.xml b/app/wisun/documentation/slWi-SUN_docContent.xml index 5ccf800175..6903b427e0 100644 --- a/app/wisun/documentation/slWi-SUN_docContent.xml +++ b/app/wisun/documentation/slWi-SUN_docContent.xml @@ -1,6 +1,6 @@ - + Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. @@ -8,7 +8,7 @@ - + Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. @@ -16,7 +16,7 @@ - + Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. @@ -24,63 +24,63 @@ - + Describes the test environment and methods for testing Wi-SUN network performance. The results are intended to provide guidance on design practices and principles as well as expected field performance results. - + Describes how to use the Wi-SUN Network Performance Measurement Application from either the LCD output or the CLI, and includes suggestions for improving ping latency in a Wi-SUN network. - + Provides an introduction to the Wi-SUN PHY Mode Switch feature using the RAILtest example application. - + Explains how to program EFR32FG25 devices to enable the Wi-SUN concurrent detection feature. - + Provides an overview and hyperlinks to all packaged documentation. - + Contains a comprehensive list of APIs used to interface to the Silicon Labs Wi-SUN stack. - + Reference for those developing applications using the Silicon Labs Wi-SUN SDK. The guide covers guidelines to develop an application on top of Silicon Labs Wi-SUN stack . The purpose of this document is to fill in the gaps between the Silicon Labs Wi-SUN Field Area Network (FAN) API reference, Gecko Platform references, and documentation for the target EFR32xG part. - + Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the SiliconLabs Wi-SUN SDK, including added/deleted/deprecated features/API. Reviews fixed and known issues. - + A detailed overview of the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform includes EMLIB, EMDRV, RAIL Library, NVM3, and the component-based infrastructure. @@ -88,7 +88,7 @@ - + Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. @@ -96,7 +96,7 @@ - + Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader as well as legacy Ember and Bluetooth bootloaders, and describes the file formats used by each. @@ -104,7 +104,7 @@ - + Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: Simulated EEPROM, PS Store, and NVM3. @@ -112,7 +112,7 @@ - + Describes how and when to use Simplicity Commander's Command-Line Interface. @@ -120,7 +120,7 @@ - + Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. diff --git a/app/wisun/esf.properties b/app/wisun/esf.properties index 460fccc426..7f8ebdafae 100644 --- a/app/wisun/esf.properties +++ b/app/wisun/esf.properties @@ -3,8 +3,8 @@ id=com.silabs.stack.wisun label=Wi-SUN description=Silicon Labs Wi-SUN SDK -version=1.9.0.0 -prop.subLabel=Wi-SUN\\ 1.9.0.0 +version=1.10.0.0 +prop.subLabel=Wi-SUN\\ 1.10.0.0 # General properties are prepended with "prop." prop.file.templatesFile=wisun_production_templates.xml wisun_br_demos_templates.xml diff --git a/app/wisun/wisun_br_demos_demos.xml b/app/wisun/wisun_br_demos_demos.xml index 8963cf9644..9bc73943df 100644 --- a/app/wisun/wisun_br_demos_demos.xml +++ b/app/wisun/wisun_br_demos_demos.xml @@ -5,7 +5,7 @@ - + @@ -15,7 +15,7 @@ - + @@ -25,7 +25,7 @@ - + @@ -35,7 +35,7 @@ - + @@ -45,7 +45,7 @@ - + @@ -55,7 +55,7 @@ - + @@ -65,7 +65,7 @@ - + @@ -75,7 +75,7 @@ - + @@ -85,7 +85,7 @@ - + @@ -95,7 +95,7 @@ - + @@ -105,7 +105,7 @@ - + @@ -115,7 +115,7 @@ - + @@ -125,7 +125,7 @@ - + @@ -135,7 +135,7 @@ - + @@ -145,7 +145,7 @@ - + @@ -155,7 +155,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -185,7 +185,7 @@ - + @@ -195,7 +195,7 @@ - + @@ -205,7 +205,7 @@ - + @@ -215,7 +215,7 @@ - + @@ -225,7 +225,7 @@ - + @@ -235,7 +235,7 @@ - + @@ -245,7 +245,7 @@ - + @@ -255,7 +255,7 @@ - + @@ -265,7 +265,7 @@ - + @@ -275,7 +275,7 @@ - + @@ -285,7 +285,7 @@ - + @@ -295,7 +295,7 @@ - + @@ -305,7 +305,7 @@ - + @@ -315,7 +315,7 @@ - + @@ -325,7 +325,7 @@ - + @@ -335,7 +335,7 @@ - + @@ -345,7 +345,7 @@ - + @@ -355,7 +355,7 @@ - + @@ -365,7 +365,7 @@ - + @@ -375,7 +375,7 @@ - + diff --git a/app/wisun/wisun_production_demos.xml b/app/wisun/wisun_production_demos.xml index c88cff34ea..89e99abcb4 100644 --- a/app/wisun/wisun_production_demos.xml +++ b/app/wisun/wisun_production_demos.xml @@ -5,7 +5,7 @@ - + @@ -15,7 +15,7 @@ - + @@ -25,7 +25,7 @@ - + @@ -35,7 +35,7 @@ - + @@ -45,7 +45,7 @@ - + @@ -55,7 +55,7 @@ - + @@ -65,7 +65,7 @@ - + @@ -75,7 +75,7 @@ - + @@ -85,7 +85,7 @@ - + @@ -95,7 +95,7 @@ - + @@ -105,7 +105,7 @@ - + @@ -115,7 +115,7 @@ - + @@ -125,7 +125,7 @@ - + @@ -135,7 +135,7 @@ - + @@ -145,7 +145,7 @@ - + @@ -155,7 +155,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -185,137 +185,137 @@ - + - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN LFN device. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. - + - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN LFN device. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. - + - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN LFN device. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. - + - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN LFN device. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. - + - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN LFN device. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. - + - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN LFN device. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. - + - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN LFN device. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. - + - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN LFN device. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. - + - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN LFN device. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. - + - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN LFN device. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. - + - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN LFN device. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. - + - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN LFN device. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. - + - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN LFN device. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. - + @@ -325,7 +325,7 @@ - + @@ -335,7 +335,7 @@ - + @@ -345,7 +345,7 @@ - + @@ -355,7 +355,7 @@ - + @@ -365,7 +365,7 @@ - + @@ -375,7 +375,7 @@ - + @@ -385,7 +385,7 @@ - + @@ -395,7 +395,7 @@ - + @@ -405,7 +405,7 @@ - + @@ -415,7 +415,7 @@ - + @@ -425,7 +425,7 @@ - + @@ -435,7 +435,7 @@ - + @@ -445,7 +445,7 @@ - + @@ -455,7 +455,7 @@ - + @@ -465,7 +465,7 @@ - + @@ -475,7 +475,7 @@ - + @@ -485,7 +485,7 @@ - + @@ -495,7 +495,7 @@ - + @@ -505,7 +505,7 @@ - + diff --git a/app/wisun/wisun_production_templates.xml b/app/wisun/wisun_production_templates.xml index 180c7d1c12..544238a5c0 100644 --- a/app/wisun/wisun_production_templates.xml +++ b/app/wisun/wisun_production_templates.xml @@ -8,14 +8,14 @@ - + - + @@ -23,7 +23,7 @@ - + @@ -38,7 +38,7 @@ - + @@ -53,7 +53,7 @@ - + @@ -68,7 +68,7 @@ - + @@ -83,7 +83,7 @@ - + @@ -98,7 +98,7 @@ - + @@ -113,7 +113,7 @@ - + @@ -128,7 +128,7 @@ - + @@ -143,7 +143,7 @@ - + @@ -158,7 +158,7 @@ - + @@ -173,7 +173,7 @@ - + @@ -188,7 +188,7 @@ - + @@ -203,7 +203,7 @@ - + diff --git a/gecko_sdk.slcs b/gecko_sdk.slcs index f067959bdd..9c19baba12 100644 --- a/gecko_sdk.slcs +++ b/gecko_sdk.slcs @@ -2,7 +2,7 @@ id: "gecko_sdk" label: "Gecko SDK Suite" description: |- Gecko SDK Suite for EM3xx, EFM32, EZR32 and EFR32 microcontrollers and radios. -sdk_version: "4.4.1" +sdk_version: "4.4.2" specification_version: 10 component_path: - path: "app/amazon/component" @@ -93,29 +93,31 @@ component_path: toolchain_mapping: "platform/common/toolchain/toolchains.slct" documentation: - docset: gecko-platform - version: "4.4.1" + version: "4.4.2" - docset: mbed-tls version: "3.5.0" - docset: connect-stack - version: "3.7.1" + version: "3.7.2" - docset: mcu-bootloader - version: "2.4.1" + version: "2.4.2" - docset: openthread - version: "2.4.1" + version: "2.4.2" - docset: rail - version: "2.16.1" + version: "2.16.2" - docset: wifi/wf200/rtos - version: "3.0.1" + version: "3.0.2" - docset: wisun - version: "1.9.0" + version: "1.10.0" - docset: zigbee - version: "7.4.1" + version: "7.4.2" - docset: rtl-lib - version: "7.0.1" + version: "7.1.0" - docset: bluetooth - version: "7.0.1" + version: "7.1.0" - docset: protocol-usb - version: "1.2.0" + version: "1.2.1" + - docset: machine-learning + version: "1.3.0" upgrade_manifest: - path: "app/common/upgrade.slcu" - path: "hardware/upgrade.slcu" diff --git a/hardware/board/component/bg22-pk6022a.slcc b/hardware/board/component/bg22-pk6022a.slcc new file mode 100644 index 0000000000..f0ae8a7ec2 --- /dev/null +++ b/hardware/board/component/bg22-pk6022a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: bg22_pk6022a +- label: BG22-PK6022A +- package: platform +- description: Kit BSP support for the BG22 Direction Finding Pro Kit. +- category: Platform|Board|Kit|Pro Kit +- quality: production +- requires: + - name: hardware_board_from_bg22-pk6022a +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"BG22-PK6022A"' + - name: SL_KIT_REV + value: '"A00"' +- tag: + - kit:opn:BG22-PK6022A + - kit:pn:PK6022 + - kit:variant:A + - kit:revision:A00 diff --git a/hardware/board/component/brd2204a.slcc b/hardware/board/component/brd2204a.slcc index dba76a54e0..205a60981a 100644 --- a/hardware/board/component/brd2204a.slcc +++ b/hardware/board/component/brd2204a.slcc @@ -16,6 +16,7 @@ - name: hardware_board_from_slstk3701a - name: hardware_board_has_si70xx - name: hardware_board_has_tempsensor + - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_hfxo_freq_50mhz - name: hardware_board_has_hfxo diff --git a/hardware/board/component/brd2204c.slcc b/hardware/board/component/brd2204c.slcc index 41f2654806..7232903980 100644 --- a/hardware/board/component/brd2204c.slcc +++ b/hardware/board/component/brd2204c.slcc @@ -16,6 +16,7 @@ - name: hardware_board_from_slstk3701a - name: hardware_board_has_si70xx - name: hardware_board_has_tempsensor + - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_hfxo_freq_50mhz - name: hardware_board_has_hfxo diff --git a/hardware/board/component/brd2207a.slcc b/hardware/board/component/brd2207a.slcc index d5d614b2a4..7f31f3ada8 100644 --- a/hardware/board/component/brd2207a.slcc +++ b/hardware/board/component/brd2207a.slcc @@ -14,6 +14,7 @@ - name: hardware_board_tb - name: hardware_board_from_tb - name: hardware_board_from_sltb009a + - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_hfxo_freq_50mhz - name: hardware_board_has_hfxo diff --git a/hardware/board/component/brd2601a.slcc b/hardware/board/component/brd2601a.slcc index ab41c976b3..b9ec9f4611 100644 --- a/hardware/board/component/brd2601a.slcc +++ b/hardware/board/component/brd2601a.slcc @@ -16,6 +16,7 @@ - name: hardware_board_from_xg24-dk2601a - name: hardware_board_has_si70xx - name: hardware_board_has_tempsensor + - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_hfxo_freq_39mhz diff --git a/hardware/board/component/brd2601b.slcc b/hardware/board/component/brd2601b.slcc index ba5fe8243c..267951d13c 100644 --- a/hardware/board/component/brd2601b.slcc +++ b/hardware/board/component/brd2601b.slcc @@ -16,6 +16,7 @@ - name: hardware_board_from_xg24-dk2601b - name: hardware_board_has_si70xx - name: hardware_board_has_tempsensor + - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_hfxo_freq_39mhz diff --git a/hardware/board/component/brd2603a.slcc b/hardware/board/component/brd2603a.slcc index babd9dd641..8f1f7f59d5 100644 --- a/hardware/board/component/brd2603a.slcc +++ b/hardware/board/component/brd2603a.slcc @@ -18,6 +18,7 @@ - name: hardware_board_from_zwave-pk800b - name: hardware_board_has_si70xx - name: hardware_board_has_tempsensor + - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_lfxo diff --git a/hardware/board/component/brd4001a.slcc b/hardware/board/component/brd4001a.slcc index d4bcaa4bb1..cb80210b16 100644 --- a/hardware/board/component/brd4001a.slcc +++ b/hardware/board/component/brd4001a.slcc @@ -18,8 +18,8 @@ - name: SL_BOARD_NAME value: '"BRD4001A"' - name: SL_BOARD_REV - value: '"A03"' + value: '"A02"' - tag: - board:pn:BRD4001 - board:variant:A - - board:revision:A03 + - board:revision:A02 diff --git a/hardware/board/component/brd4002a.slcc b/hardware/board/component/brd4002a.slcc index 86c2fb401e..83de8b2ddd 100644 --- a/hardware/board/component/brd4002a.slcc +++ b/hardware/board/component/brd4002a.slcc @@ -11,10 +11,14 @@ - name: hardware_board_mainboard_wstk - name: hardware_board_mainboard - name: hardware_board_from_wmb - - name: hardware_board_from_slwmb4002a - recommends: [] - template_contribution: [] +- define: + - name: SL_BOARD_NAME + value: '"BRD4002A"' + - name: SL_BOARD_REV + value: '"A06"' - tag: - board:pn:BRD4002 - board:variant:A - - board:revision:A02 + - board:revision:A06 diff --git a/hardware/board/component/brd4200a.slcc b/hardware/board/component/brd4200a.slcc index 31e6d1f1e0..e2eb2e3933 100644 --- a/hardware/board/component/brd4200a.slcc +++ b/hardware/board/component/brd4200a.slcc @@ -17,6 +17,7 @@ - name: hardware_board_from_slwrb4200a - name: hardware_board_has_si70xx - name: hardware_board_has_tempsensor + - name: hardware_board_has_rgb - name: hardware_board_has_rfswitch_zwave - name: hardware_board_has_vcom - name: hardware_board_has_rfswitch diff --git a/hardware/board/component/brd4202a.slcc b/hardware/board/component/brd4202a.slcc index 3df6aa9c07..e85684afb4 100644 --- a/hardware/board/component/brd4202a.slcc +++ b/hardware/board/component/brd4202a.slcc @@ -18,6 +18,7 @@ - name: hardware_board_from_slwstk6050a - name: hardware_board_has_si70xx - name: hardware_board_has_tempsensor + - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_supports_rf_band_868 - name: hardware_board_supports_rf_band_914 diff --git a/hardware/board/component/brd4203a.slcc b/hardware/board/component/brd4203a.slcc index 94a37fd1ee..d5d12f4670 100644 --- a/hardware/board/component/brd4203a.slcc +++ b/hardware/board/component/brd4203a.slcc @@ -16,6 +16,7 @@ - name: hardware_board_from_stk - name: hardware_board_has_si70xx - name: hardware_board_has_tempsensor + - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_hfxo_freq_39mhz diff --git a/hardware/board/component/brd4205a.slcc b/hardware/board/component/brd4205a.slcc index 9f69b80bde..cb3d6e4d33 100644 --- a/hardware/board/component/brd4205a.slcc +++ b/hardware/board/component/brd4205a.slcc @@ -16,6 +16,7 @@ - name: hardware_board_from_stk - name: hardware_board_has_si70xx - name: hardware_board_has_tempsensor + - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_supports_rf_band_868 diff --git a/hardware/board/component/brd4205b.slcc b/hardware/board/component/brd4205b.slcc index 3c9e1d8fc2..9a4aaeecf9 100644 --- a/hardware/board/component/brd4205b.slcc +++ b/hardware/board/component/brd4205b.slcc @@ -19,6 +19,7 @@ - name: hardware_board_from_zwave-pk800b - name: hardware_board_has_si70xx - name: hardware_board_has_tempsensor + - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_supports_rf_band_868 diff --git a/hardware/board/component/brd4207a.slcc b/hardware/board/component/brd4207a.slcc index 0a4aaf68c1..1c7cb000a0 100644 --- a/hardware/board/component/brd4207a.slcc +++ b/hardware/board/component/brd4207a.slcc @@ -19,6 +19,7 @@ - name: hardware_board_from_slwstk6050c - name: hardware_board_has_si70xx - name: hardware_board_has_tempsensor + - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_supports_rf_band_868 - name: hardware_board_supports_rf_band_914 diff --git a/hardware/board/component/brd4209a.slcc b/hardware/board/component/brd4209a.slcc index 784ebc4475..ab23f4ea2d 100644 --- a/hardware/board/component/brd4209a.slcc +++ b/hardware/board/component/brd4209a.slcc @@ -16,6 +16,7 @@ - name: hardware_board_from_stk - name: hardware_board_has_si70xx - name: hardware_board_has_tempsensor + - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_hfxo_freq_39mhz diff --git a/hardware/board/component/brd4328a.slcc b/hardware/board/component/brd4328a.slcc index 36e0fc1d4e..f15ca6c8fe 100644 --- a/hardware/board/component/brd4328a.slcc +++ b/hardware/board/component/brd4328a.slcc @@ -17,6 +17,7 @@ - name: hardware_board_from_fgm230-rb4328a - name: hardware_board_has_si70xx - name: hardware_board_has_tempsensor + - name: hardware_board_has_rgb - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_supports_rf_band_868 diff --git a/hardware/board/component/brd4328b.slcc b/hardware/board/component/brd4328b.slcc new file mode 100644 index 0000000000..0bc82b3cbd --- /dev/null +++ b/hardware/board/component/brd4328b.slcc @@ -0,0 +1,81 @@ +!!omap +- id: brd4328b +- label: BRD4328B +- package: platform +- description: Board support for BRD4328B. +- category: Platform|Board|Radio Board +- quality: production +- requires: + - name: fgm230sa27hgn + - name: brd4328b_config + - name: hardware_board_mainboard +- provides: + - name: brd4328b + - name: hardware_board + - name: hardware_board_rb + - name: hardware_board_from_stk + - name: hardware_board_from_fgm230-rb4328b + - name: hardware_board_has_si70xx + - name: hardware_board_has_tempsensor + - name: hardware_board_has_rgb + - name: hardware_board_has_vcom + - name: hardware_board_has_spiflash + - name: hardware_board_supports_rf_band_868 + - name: hardware_board_supports_rf_band_914 + - name: hardware_board_supports_rf_band_924 + - name: hardware_board_supports_3_rf_bands + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_868 +- recommends: + - id: brd4002a + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver + - id: i2cspm + instance: + - sensor + - id: ls013b7dh03 + - id: memlcd_usart + - id: simple_led + instance: + - led0 + - led1 + - led2 + - led3 + - led4 + - id: simple_button + instance: + - btn0 + - btn1 + - id: mx25_flash_shutdown_usart + - id: bootloader_spi_controller_usart_driver + - id: bootloader_spi_peripheral_usart_driver +- template_contribution: + - name: board_default_init + value: sl_board_disable_vcom() +- define: + - name: SL_BOARD_NAME + value: '"BRD4328B"' + - name: SL_BOARD_REV + value: '"A00"' + - name: HARDWARE_BOARD_SUPPORTS_RF_BAND_868 + - name: HARDWARE_BOARD_SUPPORTS_RF_BAND_914 + - name: HARDWARE_BOARD_SUPPORTS_RF_BAND_924 + - name: HARDWARE_BOARD_SUPPORTS_3_RF_BANDS + - name: HARDWARE_BOARD_DEFAULT_RF_BAND_868 +- tag: + - board:pn:BRD4328 + - board:variant:B + - board:revision:A00 + - board:device:fgm230sa27hgn + - hardware:has:vcom + - hardware:has:pti + - hardware:has:sensor:si7021 + - hardware:has:display:ls013b7dh03 + - hardware:has:led:5 + - hardware:has:button:2 + - hardware:has:memory:spi:mx25r8035f + - hardware:has:exp_header:spi + - hardware:has:exp_header:uart + - hardware:has:exp_header:i2c diff --git a/hardware/board/component/fg25-pk6011a.slcc b/hardware/board/component/fg25-pk6011a.slcc new file mode 100644 index 0000000000..fdebcbf2e9 --- /dev/null +++ b/hardware/board/component/fg25-pk6011a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: fg25_pk6011a +- label: FG25-PK6011A +- package: platform +- description: Kit BSP support for the FG25 US/Japan Pro Kit. +- category: Platform|Board|Kit|Pro Kit +- quality: production +- requires: + - name: hardware_board_from_fg25-pk6011a +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"FG25-PK6011A"' + - name: SL_KIT_REV + value: '"A02"' +- tag: + - kit:opn:FG25-PK6011A + - kit:pn:PK6011 + - kit:variant:A + - kit:revision:A02 diff --git a/hardware/board/component/fg25-pk6012a.slcc b/hardware/board/component/fg25-pk6012a.slcc new file mode 100644 index 0000000000..3aeb6643f8 --- /dev/null +++ b/hardware/board/component/fg25-pk6012a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: fg25_pk6012a +- label: FG25-PK6012A +- package: platform +- description: Kit BSP support for the FG25 RoW Pro Kit. +- category: Platform|Board|Kit|Pro Kit +- quality: production +- requires: + - name: hardware_board_from_fg25-pk6012a +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"FG25-PK6012A"' + - name: SL_KIT_REV + value: '"A02"' +- tag: + - kit:opn:FG25-PK6012A + - kit:pn:PK6012 + - kit:variant:A + - kit:revision:A02 diff --git a/hardware/board/component/fg25-pk6013a.slcc b/hardware/board/component/fg25-pk6013a.slcc new file mode 100644 index 0000000000..970fa9ca84 --- /dev/null +++ b/hardware/board/component/fg25-pk6013a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: fg25_pk6013a +- label: FG25-PK6013A +- package: platform +- description: Kit BSP support for the FG25-EFF01 US/Japan Pro Kit. +- category: Platform|Board|Kit|Pro Kit +- quality: production +- requires: + - name: hardware_board_from_fg25-pk6013a +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"FG25-PK6013A"' + - name: SL_KIT_REV + value: '"A00"' +- tag: + - kit:opn:FG25-PK6013A + - kit:pn:PK6013 + - kit:variant:A + - kit:revision:A00 diff --git a/hardware/board/component/fg25-pk6014a.slcc b/hardware/board/component/fg25-pk6014a.slcc new file mode 100644 index 0000000000..08737e37c4 --- /dev/null +++ b/hardware/board/component/fg25-pk6014a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: fg25_pk6014a +- label: FG25-PK6014A +- package: platform +- description: Kit BSP support for the FG25-EFF01 RoW Pro Kit. +- category: Platform|Board|Kit|Pro Kit +- quality: production +- requires: + - name: hardware_board_from_fg25-pk6014a +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"FG25-PK6014A"' + - name: SL_KIT_REV + value: '"A00"' +- tag: + - kit:opn:FG25-PK6014A + - kit:pn:PK6014 + - kit:variant:A + - kit:revision:A00 diff --git a/hardware/board/component/fgm230-rb4328b.slcc b/hardware/board/component/fgm230-rb4328b.slcc new file mode 100644 index 0000000000..01843ebe41 --- /dev/null +++ b/hardware/board/component/fgm230-rb4328b.slcc @@ -0,0 +1,22 @@ +!!omap +- id: fgm230_rb4328b +- label: FGM230-RB4328B +- package: platform +- description: Kit BSP support for the FGM230SA Module Radio Board. +- category: Platform|Board|Kit|Radio Board +- quality: production +- requires: + - name: hardware_board_from_fgm230-rb4328b +- provides: + - name: hardware_kit + - name: hardware_kit_rb +- define: + - name: SL_KIT_NAME + value: '"FGM230-RB4328B"' + - name: SL_KIT_REV + value: '"A00"' +- tag: + - kit:opn:FGM230-RB4328B + - kit:pn:RB4328 + - kit:variant:B + - kit:revision:A00 diff --git a/hardware/board/component/slwstk6000b.slcc b/hardware/board/component/slwstk6000b.slcc index 6a3c641b1e..e4ce62a6cf 100644 --- a/hardware/board/component/slwstk6000b.slcc +++ b/hardware/board/component/slwstk6000b.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6000b - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6000B"' - name: SL_KIT_REV - value: '"B05"' + value: '"C00"' - tag: - kit:opn:SLWSTK6000B - kit:pn:WSTK6000 - kit:variant:B - - kit:revision:B05 + - kit:revision:C00 diff --git a/hardware/board/component/slwstk6005a.slcc b/hardware/board/component/slwstk6005a.slcc index 69d6145769..c438e42259 100644 --- a/hardware/board/component/slwstk6005a.slcc +++ b/hardware/board/component/slwstk6005a.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6005a - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6005A"' - name: SL_KIT_REV - value: '"A04"' + value: '"B00"' - tag: - kit:opn:SLWSTK6005A - kit:pn:WSTK6005 - kit:variant:A - - kit:revision:A04 + - kit:revision:B00 diff --git a/hardware/board/component/slwstk6006a.slcc b/hardware/board/component/slwstk6006a.slcc index 07093436de..26d92739a3 100644 --- a/hardware/board/component/slwstk6006a.slcc +++ b/hardware/board/component/slwstk6006a.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6006a - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6006A"' - name: SL_KIT_REV - value: '"B06"' + value: '"C01"' - tag: - kit:opn:SLWSTK6006A - kit:pn:WSTK6006 - kit:variant:A - - kit:revision:B06 + - kit:revision:C01 diff --git a/hardware/board/component/slwstk6007a.slcc b/hardware/board/component/slwstk6007a.slcc index b3cbdd2cdc..f82a5258d0 100644 --- a/hardware/board/component/slwstk6007a.slcc +++ b/hardware/board/component/slwstk6007a.slcc @@ -7,7 +7,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6007a - provides: - name: hardware_kit @@ -16,9 +16,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6007A"' - name: SL_KIT_REV - value: '"A00"' + value: '"A01"' - tag: - kit:opn:SLWSTK6007A - kit:pn:WSTK6007 - kit:variant:A - - kit:revision:A00 + - kit:revision:A01 diff --git a/hardware/board/component/slwstk6020b.slcc b/hardware/board/component/slwstk6020b.slcc index 08eed96c8a..774aa9a09c 100644 --- a/hardware/board/component/slwstk6020b.slcc +++ b/hardware/board/component/slwstk6020b.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6020b - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6020B"' - name: SL_KIT_REV - value: '"A05"' + value: '"B00"' - tag: - kit:opn:SLWSTK6020B - kit:pn:WSTK6020 - kit:variant:B - - kit:revision:A05 + - kit:revision:B00 diff --git a/hardware/board/component/slwstk6021a.slcc b/hardware/board/component/slwstk6021a.slcc index fee145f113..a4f9cd1fb2 100644 --- a/hardware/board/component/slwstk6021a.slcc +++ b/hardware/board/component/slwstk6021a.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6021a - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6021A"' - name: SL_KIT_REV - value: '"A04"' + value: '"B00"' - tag: - kit:opn:SLWSTK6021A - kit:pn:WSTK6021 - kit:variant:A - - kit:revision:A04 + - kit:revision:B00 diff --git a/hardware/board/component/slwstk6023a.slcc b/hardware/board/component/slwstk6023a.slcc index b9dbe55f5e..80b22868dc 100644 --- a/hardware/board/component/slwstk6023a.slcc +++ b/hardware/board/component/slwstk6023a.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6023a - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6023A"' - name: SL_KIT_REV - value: '"A03"' + value: '"B00"' - tag: - kit:opn:SLWSTK6023A - kit:pn:WSTK6023 - kit:variant:A - - kit:revision:A03 + - kit:revision:B00 diff --git a/hardware/board/component/slwstk6050b.slcc b/hardware/board/component/slwstk6050b.slcc index 1c0f28b5fe..b6d39282b1 100644 --- a/hardware/board/component/slwstk6050b.slcc +++ b/hardware/board/component/slwstk6050b.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6050b - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6050B"' - name: SL_KIT_REV - value: '"A01"' + value: '"B00"' - tag: - kit:opn:SLWSTK6050B - kit:pn:WSTK6050 - kit:variant:B - - kit:revision:A01 + - kit:revision:B00 diff --git a/hardware/board/component/slwstk6050c.slcc b/hardware/board/component/slwstk6050c.slcc new file mode 100644 index 0000000000..e1fc437f65 --- /dev/null +++ b/hardware/board/component/slwstk6050c.slcc @@ -0,0 +1,23 @@ +!!omap +- id: slwstk6050c +- label: SLWSTK6050C +- package: platform +- description: Kit BSP support for the Z-Wave 700 Starter Kit. +- category: Platform|Board|Kit|Wireless Starter Kit +- quality: production +- requires: + - name: brd4002a + - name: hardware_board_from_slwstk6050c +- provides: + - name: hardware_kit + - name: hardware_kit_stk +- define: + - name: SL_KIT_NAME + value: '"SLWSTK6050C"' + - name: SL_KIT_REV + value: '"A00"' +- tag: + - kit:opn:SLWSTK6050C + - kit:pn:WSTK6050 + - kit:variant:C + - kit:revision:A00 diff --git a/hardware/board/component/slwstk6061b.slcc b/hardware/board/component/slwstk6061b.slcc index ec3a2d5352..d7406a760d 100644 --- a/hardware/board/component/slwstk6061b.slcc +++ b/hardware/board/component/slwstk6061b.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6061b - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6061B"' - name: SL_KIT_REV - value: '"A04"' + value: '"B00"' - tag: - kit:opn:SLWSTK6061B - kit:pn:WSTK6061 - kit:variant:B - - kit:revision:A04 + - kit:revision:B00 diff --git a/hardware/board/component/slwstk6063b.slcc b/hardware/board/component/slwstk6063b.slcc index 4b31deebdd..a9461ebb4b 100644 --- a/hardware/board/component/slwstk6063b.slcc +++ b/hardware/board/component/slwstk6063b.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6063b - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6063B"' - name: SL_KIT_REV - value: '"A03"' + value: '"B00"' - tag: - kit:opn:SLWSTK6063B - kit:pn:WSTK6063 - kit:variant:B - - kit:revision:A03 + - kit:revision:B00 diff --git a/hardware/board/component/slwstk6065b.slcc b/hardware/board/component/slwstk6065b.slcc index 287af1a036..fe9c2ff364 100644 --- a/hardware/board/component/slwstk6065b.slcc +++ b/hardware/board/component/slwstk6065b.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6065b - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6065B"' - name: SL_KIT_REV - value: '"A03"' + value: '"B01"' - tag: - kit:opn:SLWSTK6065B - kit:pn:WSTK6065 - kit:variant:B - - kit:revision:A03 + - kit:revision:B01 diff --git a/hardware/board/component/slwstk6101d.slcc b/hardware/board/component/slwstk6101d.slcc index 4e146c5175..899bb96612 100644 --- a/hardware/board/component/slwstk6101d.slcc +++ b/hardware/board/component/slwstk6101d.slcc @@ -7,7 +7,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6101d - provides: - name: hardware_kit @@ -16,9 +16,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6101D"' - name: SL_KIT_REV - value: '"A04"' + value: '"B00"' - tag: - kit:opn:SLWSTK6101D - kit:pn:WSTK6101 - kit:variant:D - - kit:revision:A04 + - kit:revision:B00 diff --git a/hardware/board/component/slwstk6102a.slcc b/hardware/board/component/slwstk6102a.slcc index 035066b4f1..4bb2a3327b 100644 --- a/hardware/board/component/slwstk6102a.slcc +++ b/hardware/board/component/slwstk6102a.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6102a - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6102A"' - name: SL_KIT_REV - value: '"B00"' + value: '"C00"' - tag: - kit:opn:SLWSTK6102A - kit:pn:WSTK6102 - kit:variant:A - - kit:revision:B00 + - kit:revision:C00 diff --git a/hardware/board/component/slwstk6103a.slcc b/hardware/board/component/slwstk6103a.slcc index 052d6ac36a..71cfa32614 100644 --- a/hardware/board/component/slwstk6103a.slcc +++ b/hardware/board/component/slwstk6103a.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6103a - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6103A"' - name: SL_KIT_REV - value: '"A07"' + value: '"B01"' - tag: - kit:opn:SLWSTK6103A - kit:pn:WSTK6103 - kit:variant:A - - kit:revision:A07 + - kit:revision:B01 diff --git a/hardware/board/component/slwstk6104a.slcc b/hardware/board/component/slwstk6104a.slcc index a721175499..6564fda4d2 100644 --- a/hardware/board/component/slwstk6104a.slcc +++ b/hardware/board/component/slwstk6104a.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6104a - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6104A"' - name: SL_KIT_REV - value: '"A02"' + value: '"B00"' - tag: - kit:opn:SLWSTK6104A - kit:pn:WSTK6104 - kit:variant:A - - kit:revision:A02 + - kit:revision:B00 diff --git a/hardware/board/component/slwstk6220a.slcc b/hardware/board/component/slwstk6220a.slcc index a7ae455970..6d1891d28c 100644 --- a/hardware/board/component/slwstk6220a.slcc +++ b/hardware/board/component/slwstk6220a.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6220a - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6220A"' - name: SL_KIT_REV - value: '"D01"' + value: '"E00"' - tag: - kit:opn:SLWSTK6220A - kit:pn:WSTK6220 - kit:variant:A - - kit:revision:D01 + - kit:revision:E00 diff --git a/hardware/board/component/slwstk6222a.slcc b/hardware/board/component/slwstk6222a.slcc index fe70b9d677..974f6ade88 100644 --- a/hardware/board/component/slwstk6222a.slcc +++ b/hardware/board/component/slwstk6222a.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6222a - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6222A"' - name: SL_KIT_REV - value: '"D02"' + value: '"E01"' - tag: - kit:opn:SLWSTK6222A - kit:pn:WSTK6222 - kit:variant:A - - kit:revision:D02 + - kit:revision:E01 diff --git a/hardware/board/component/slwstk6224a.slcc b/hardware/board/component/slwstk6224a.slcc index d990301de3..aa3ce54e62 100644 --- a/hardware/board/component/slwstk6224a.slcc +++ b/hardware/board/component/slwstk6224a.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6224a - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6224A"' - name: SL_KIT_REV - value: '"D01"' + value: '"E00"' - tag: - kit:opn:SLWSTK6224A - kit:pn:WSTK6224 - kit:variant:A - - kit:revision:D01 + - kit:revision:E00 diff --git a/hardware/board/component/slwstk6240a.slcc b/hardware/board/component/slwstk6240a.slcc index abc2bd0a8d..11bdd76b72 100644 --- a/hardware/board/component/slwstk6240a.slcc +++ b/hardware/board/component/slwstk6240a.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6240a - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6240A"' - name: SL_KIT_REV - value: '"D01"' + value: '"E00"' - tag: - kit:opn:SLWSTK6240A - kit:pn:WSTK6240 - kit:variant:A - - kit:revision:D01 + - kit:revision:E00 diff --git a/hardware/board/component/slwstk6242a.slcc b/hardware/board/component/slwstk6242a.slcc index ded1864b81..9d335cfd86 100644 --- a/hardware/board/component/slwstk6242a.slcc +++ b/hardware/board/component/slwstk6242a.slcc @@ -6,7 +6,7 @@ - category: Platform|Board|Kit|Wireless Starter Kit - quality: production - requires: - - name: brd4001a + - name: brd4002a - name: hardware_board_from_slwstk6242a - provides: - name: hardware_kit @@ -15,9 +15,9 @@ - name: SL_KIT_NAME value: '"SLWSTK6242A"' - name: SL_KIT_REV - value: '"D01"' + value: '"E00"' - tag: - kit:opn:SLWSTK6242A - kit:pn:WSTK6242 - kit:variant:A - - kit:revision:D01 + - kit:revision:E00 diff --git a/hardware/board/component/wi-sun-pk6015a.slcc b/hardware/board/component/wi-sun-pk6015a.slcc new file mode 100644 index 0000000000..7d7d361abe --- /dev/null +++ b/hardware/board/component/wi-sun-pk6015a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: wi_sun_pk6015a +- label: WI-SUN-PK6015A +- package: platform +- description: Kit BSP support for the Wi-SUN FAN RoW Pro Kit. +- category: Platform|Board|Kit|Pro Kit +- quality: production +- requires: + - name: hardware_board_from_wi-sun-pk6015a +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"WI-SUN-PK6015A"' + - name: SL_KIT_REV + value: '"A01"' +- tag: + - kit:opn:Wi-SUN-PK6015A + - kit:pn:PK6015 + - kit:variant:A + - kit:revision:A01 diff --git a/hardware/board/component/wi-sun-pk6016a.slcc b/hardware/board/component/wi-sun-pk6016a.slcc new file mode 100644 index 0000000000..1e5449b864 --- /dev/null +++ b/hardware/board/component/wi-sun-pk6016a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: wi_sun_pk6016a +- label: WI-SUN-PK6016A +- package: platform +- description: Kit BSP support for the Wi-SUN FAN US/Japan Pro Kit. +- category: Platform|Board|Kit|Pro Kit +- quality: production +- requires: + - name: hardware_board_from_wi-sun-pk6016a +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"WI-SUN-PK6016A"' + - name: SL_KIT_REV + value: '"A01"' +- tag: + - kit:opn:Wi-SUN-PK6016A + - kit:pn:PK6016 + - kit:variant:A + - kit:revision:A01 diff --git a/hardware/board/component/xg21-pk6026a.slcc b/hardware/board/component/xg21-pk6026a.slcc new file mode 100644 index 0000000000..4d2cbfa672 --- /dev/null +++ b/hardware/board/component/xg21-pk6026a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: xg21_pk6026a +- label: XG21-PK6026A +- package: platform +- description: Kit BSP support for the xG21 2.4 GHz 10 dBm Pro Kit. +- category: Platform|Board|Kit|Pro Kit +- quality: production +- requires: + - name: hardware_board_from_xg21-pk6026a +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"XG21-PK6026A"' + - name: SL_KIT_REV + value: '"A00"' +- tag: + - kit:opn:xG21-PK6026A + - kit:pn:PK6026 + - kit:variant:A + - kit:revision:A00 diff --git a/hardware/board/component/xg21-pk6027a.slcc b/hardware/board/component/xg21-pk6027a.slcc new file mode 100644 index 0000000000..dcd60ea5fb --- /dev/null +++ b/hardware/board/component/xg21-pk6027a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: xg21_pk6027a +- label: XG21-PK6027A +- package: platform +- description: Kit BSP support for the xG21 2.4 GHz 20 dBm Pro Kit. +- category: Platform|Board|Kit|Pro Kit +- quality: production +- requires: + - name: hardware_board_from_xg21-pk6027a +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"XG21-PK6027A"' + - name: SL_KIT_REV + value: '"A00"' +- tag: + - kit:opn:xG21-PK6027A + - kit:pn:PK6027 + - kit:variant:A + - kit:revision:A00 diff --git a/hardware/board/component/xg23-pk6067a.slcc b/hardware/board/component/xg23-pk6067a.slcc index bb1fc74be2..0efb94139f 100644 --- a/hardware/board/component/xg23-pk6067a.slcc +++ b/hardware/board/component/xg23-pk6067a.slcc @@ -14,9 +14,9 @@ - name: SL_KIT_NAME value: '"XG23-PK6067A"' - name: SL_KIT_REV - value: '"A00"' + value: '"B01"' - tag: - kit:opn:xG23-PK6067A - kit:pn:PK6067 - kit:variant:A - - kit:revision:A00 + - kit:revision:B01 diff --git a/hardware/board/component/xg23-pk6068a.slcc b/hardware/board/component/xg23-pk6068a.slcc index bc0c8d51b6..73b5d670fe 100644 --- a/hardware/board/component/xg23-pk6068a.slcc +++ b/hardware/board/component/xg23-pk6068a.slcc @@ -14,9 +14,9 @@ - name: SL_KIT_NAME value: '"XG23-PK6068A"' - name: SL_KIT_REV - value: '"A00"' + value: '"B01"' - tag: - kit:opn:xG23-PK6068A - kit:pn:PK6068 - kit:variant:A - - kit:revision:A00 + - kit:revision:B01 diff --git a/hardware/board/component/xg24-pk6009a.slcc b/hardware/board/component/xg24-pk6009a.slcc new file mode 100644 index 0000000000..2244047984 --- /dev/null +++ b/hardware/board/component/xg24-pk6009a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: xg24_pk6009a +- label: XG24-PK6009A +- package: platform +- description: Kit BSP support for the xG24 10 dBm Pro Kit. +- category: Platform|Board|Kit|Pro Kit +- quality: production +- requires: + - name: hardware_board_from_xg24-pk6009a +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"XG24-PK6009A"' + - name: SL_KIT_REV + value: '"A01"' +- tag: + - kit:opn:xG24-PK6009A + - kit:pn:PK6009 + - kit:variant:A + - kit:revision:A01 diff --git a/hardware/board/component/xg24-pk6010a.slcc b/hardware/board/component/xg24-pk6010a.slcc new file mode 100644 index 0000000000..ce89151398 --- /dev/null +++ b/hardware/board/component/xg24-pk6010a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: xg24_pk6010a +- label: XG24-PK6010A +- package: platform +- description: Kit BSP support for the xG24 20 dBm Pro Kit. +- category: Platform|Board|Kit|Pro Kit +- quality: production +- requires: + - name: hardware_board_from_xg24-pk6010a +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"XG24-PK6010A"' + - name: SL_KIT_REV + value: '"A01"' +- tag: + - kit:opn:xG24-PK6010A + - kit:pn:PK6010 + - kit:variant:A + - kit:revision:A01 diff --git a/hardware/board/component/xg27-pk6017a.slcc b/hardware/board/component/xg27-pk6017a.slcc new file mode 100644 index 0000000000..645e37c29b --- /dev/null +++ b/hardware/board/component/xg27-pk6017a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: xg27_pk6017a +- label: XG27-PK6017A +- package: platform +- description: Kit BSP support for the xG27 2.4 GHz +8 dBm Pro Kit. +- category: Platform|Board|Kit|Pro Kit +- quality: production +- requires: + - name: hardware_board_from_xg27-pk6017a +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"XG27-PK6017A"' + - name: SL_KIT_REV + value: '"A00"' +- tag: + - kit:opn:xG27-PK6017A + - kit:pn:PK6017 + - kit:variant:A + - kit:revision:A00 diff --git a/hardware/board/component/xg27-pk6018a.slcc b/hardware/board/component/xg27-pk6018a.slcc new file mode 100644 index 0000000000..656ee9c636 --- /dev/null +++ b/hardware/board/component/xg27-pk6018a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: xg27_pk6018a +- label: XG27-PK6018A +- package: platform +- description: Kit BSP support for the xG27 2.4 GHz +4 dBm Pro Kit (Buck). +- category: Platform|Board|Kit|Pro Kit +- quality: production +- requires: + - name: hardware_board_from_xg27-pk6018a +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"XG27-PK6018A"' + - name: SL_KIT_REV + value: '"A01"' +- tag: + - kit:opn:xG27-PK6018A + - kit:pn:PK6018 + - kit:variant:A + - kit:revision:A01 diff --git a/hardware/board/component/xg27-pk6019a.slcc b/hardware/board/component/xg27-pk6019a.slcc new file mode 100644 index 0000000000..386ed22ee9 --- /dev/null +++ b/hardware/board/component/xg27-pk6019a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: xg27_pk6019a +- label: XG27-PK6019A +- package: platform +- description: Kit BSP support for the xG27 2.4 GHz +4 dBm Pro Kit (Boost). +- category: Platform|Board|Kit|Pro Kit +- quality: production +- requires: + - name: hardware_board_from_xg27-pk6019a +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"XG27-PK6019A"' + - name: SL_KIT_REV + value: '"A01"' +- tag: + - kit:opn:xG27-PK6019A + - kit:pn:PK6019 + - kit:variant:A + - kit:revision:A01 diff --git a/hardware/board/component/xg28-pk6024a.slcc b/hardware/board/component/xg28-pk6024a.slcc new file mode 100644 index 0000000000..9aa1f71084 --- /dev/null +++ b/hardware/board/component/xg28-pk6024a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: xg28_pk6024a +- label: XG28-PK6024A +- package: platform +- description: Kit BSP support for the EFR32xG28 14 dBm Pro Kit. +- category: Platform|Board|Kit|Pro Kit +- quality: production +- requires: + - name: hardware_board_from_xg28-pk6024a +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"XG28-PK6024A"' + - name: SL_KIT_REV + value: '"A02"' +- tag: + - kit:opn:xG28-PK6024A + - kit:pn:PK6024 + - kit:variant:A + - kit:revision:A02 diff --git a/hardware/board/component/xg28-pk6025a.slcc b/hardware/board/component/xg28-pk6025a.slcc new file mode 100644 index 0000000000..9594896e3d --- /dev/null +++ b/hardware/board/component/xg28-pk6025a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: xg28_pk6025a +- label: XG28-PK6025A +- package: platform +- description: Kit BSP support for the EFR32xG28 20 dBm Pro Kit. +- category: Platform|Board|Kit|Pro Kit +- quality: production +- requires: + - name: hardware_board_from_xg28-pk6025a +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"XG28-PK6025A"' + - name: SL_KIT_REV + value: '"A02"' +- tag: + - kit:opn:xG28-PK6025A + - kit:pn:PK6025 + - kit:variant:A + - kit:revision:A02 diff --git a/hardware/board/component/zwave-pk800a.slcc b/hardware/board/component/zwave-pk800a.slcc index b5c49d7826..3c9401e4d4 100644 --- a/hardware/board/component/zwave-pk800a.slcc +++ b/hardware/board/component/zwave-pk800a.slcc @@ -14,9 +14,9 @@ - name: SL_KIT_NAME value: '"ZWAVE-PK800A"' - name: SL_KIT_REV - value: '"A00"' + value: '"B01"' - tag: - kit:opn:ZWAVE-PK800A - kit:pn:PK800 - kit:variant:A - - kit:revision:A00 + - kit:revision:B01 diff --git a/hardware/board/component/zwave-pk800b.slcc b/hardware/board/component/zwave-pk800b.slcc new file mode 100644 index 0000000000..546fb61fff --- /dev/null +++ b/hardware/board/component/zwave-pk800b.slcc @@ -0,0 +1,22 @@ +!!omap +- id: zwave_pk800b +- label: ZWAVE-PK800B +- package: platform +- description: Kit BSP support for the ZWAVE-PK800B. +- category: Platform|Board|Kit|Pro Kit +- quality: production +- requires: + - name: hardware_board_from_zwave-pk800b +- provides: + - name: hardware_kit + - name: hardware_kit_pk +- define: + - name: SL_KIT_NAME + value: '"ZWAVE-PK800B"' + - name: SL_KIT_REV + value: '"A00"' +- tag: + - kit:opn:ZWAVE-PK800B + - kit:pn:PK800 + - kit:variant:B + - kit:revision:A00 diff --git a/hardware/board/config/brd2010a/btl_uart_driver_cfg.h b/hardware/board/config/brd2010a/btl_uart_driver_cfg.h index 177265ba1f..5be766f055 100644 --- a/hardware/board/config/brd2010a/btl_uart_driver_cfg.h +++ b/hardware/board/config/brd2010a/btl_uart_driver_cfg.h @@ -72,7 +72,7 @@ // $[GPIO_SL_VCOM_ENABLE] #define SL_VCOM_ENABLE_PORT gpioPortA -#define SL_VCOM_ENABLE_PIN 8 +#define SL_VCOM_ENABLE_PIN 9 // [GPIO_SL_VCOM_ENABLE]$ diff --git a/hardware/board/config/brd2010a/sl_board_control_config.h b/hardware/board/config/brd2010a/sl_board_control_config.h index b664c5506f..ef558e2ac7 100644 --- a/hardware/board/config/brd2010a/sl_board_control_config.h +++ b/hardware/board/config/brd2010a/sl_board_control_config.h @@ -48,7 +48,7 @@ // SL_BOARD_ENABLE_VCOM // $[GPIO_SL_BOARD_ENABLE_VCOM] #define SL_BOARD_ENABLE_VCOM_PORT gpioPortA -#define SL_BOARD_ENABLE_VCOM_PIN 8 +#define SL_BOARD_ENABLE_VCOM_PIN 9 // [GPIO_SL_BOARD_ENABLE_VCOM]$ // SL_BOARD_ENABLE_DISPLAY diff --git a/hardware/board/config/brd4328b_brd4001a/btl_euart_driver_cfg.h b/hardware/board/config/brd4328b_brd4001a/btl_euart_driver_cfg.h new file mode 100644 index 0000000000..9f7c84438c --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/btl_euart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader euart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EUART_DRIVER_CONFIG_H +#define BTL_EUART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_EUART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_EUART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_EUART +// $[EUSART_SL_SERIAL_EUART] +#define SL_SERIAL_EUART_PERIPHERAL EUSART0 +#define SL_SERIAL_EUART_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_SERIAL_EUART_TX_PORT gpioPortA +#define SL_SERIAL_EUART_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_SERIAL_EUART_RX_PORT gpioPortA +#define SL_SERIAL_EUART_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_SERIAL_EUART_CTS_PORT gpioPortA +#define SL_SERIAL_EUART_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_SERIAL_EUART_RTS_PORT gpioPortA +#define SL_SERIAL_EUART_RTS_PIN 0 + +// [EUSART_SL_SERIAL_EUART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT gpioPortB +#define SL_VCOM_ENABLE_PIN 0 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EUART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/btl_ezsp_gpio_activation_cfg.h b/hardware/board/config/brd4328b_brd4001a/btl_ezsp_gpio_activation_cfg.h new file mode 100644 index 0000000000..c8016ffd03 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/btl_ezsp_gpio_activation_cfg.h @@ -0,0 +1,52 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader EZSP GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EZSP_GPIO_ACTIVATION_CONFIG_H +#define BTL_EZSP_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of SPI NCP + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_EZSP_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EZSPSPI_HOST_INT +// $[GPIO_SL_EZSPSPI_HOST_INT] +#define SL_EZSPSPI_HOST_INT_PORT gpioPortA +#define SL_EZSPSPI_HOST_INT_PIN 5 + +// [GPIO_SL_EZSPSPI_HOST_INT]$ + +// SL_EZSPSPI_WAKE_INT +// $[GPIO_SL_EZSPSPI_WAKE_INT] +#define SL_EZSPSPI_WAKE_INT_PORT gpioPortD +#define SL_EZSPSPI_WAKE_INT_PIN 2 + +// [GPIO_SL_EZSPSPI_WAKE_INT]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EZSP_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/btl_gpio_activation_cfg.h b/hardware/board/config/brd4328b_brd4001a/btl_gpio_activation_cfg.h new file mode 100644 index 0000000000..f73756e2d5 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/btl_gpio_activation_cfg.h @@ -0,0 +1,47 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_GPIO_ACTIVATION_CONFIG_H +#define BTL_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of Bootloader Entry + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BTL_BUTTON + +// $[GPIO_SL_BTL_BUTTON] +#define SL_BTL_BUTTON_PORT gpioPortB +#define SL_BTL_BUTTON_PIN 1 + +// [GPIO_SL_BTL_BUTTON]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/btl_spi_controller_eusart_driver_cfg.h b/hardware/board/config/brd4328b_brd4001a/btl_spi_controller_eusart_driver_cfg.h new file mode 100644 index 0000000000..dfa2459451 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/btl_spi_controller_eusart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Eusart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller EUSART Driver + +// Frequency +// Default: 6400000 +#define SL_EUSART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EUSART_EXTFLASH +// $[EUSART_SL_EUSART_EXTFLASH] +#define SL_EUSART_EXTFLASH_PERIPHERAL EUSART1 +#define SL_EUSART_EXTFLASH_PERIPHERAL_NO 1 + +// EUSART1 TX on PC01 +#define SL_EUSART_EXTFLASH_TX_PORT gpioPortC +#define SL_EUSART_EXTFLASH_TX_PIN 1 + +// EUSART1 RX on PC02 +#define SL_EUSART_EXTFLASH_RX_PORT gpioPortC +#define SL_EUSART_EXTFLASH_RX_PIN 2 + +// EUSART1 SCLK on PC03 +#define SL_EUSART_EXTFLASH_SCLK_PORT gpioPortC +#define SL_EUSART_EXTFLASH_SCLK_PIN 3 + +// EUSART1 CS on PC04 +#define SL_EUSART_EXTFLASH_CS_PORT gpioPortC +#define SL_EUSART_EXTFLASH_CS_PIN 4 + +// [EUSART_SL_EUSART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/btl_spi_controller_usart_driver_cfg.h b/hardware/board/config/brd4328b_brd4001a/btl_spi_controller_usart_driver_cfg.h new file mode 100644 index 0000000000..a666144221 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/btl_spi_controller_usart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller USART Driver + +// Frequency +// Default: 6400000 +#define SL_USART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_EXTFLASH +// $[USART_SL_USART_EXTFLASH] +#define SL_USART_EXTFLASH_PERIPHERAL USART0 +#define SL_USART_EXTFLASH_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_USART_EXTFLASH_TX_PORT gpioPortC +#define SL_USART_EXTFLASH_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_USART_EXTFLASH_RX_PORT gpioPortC +#define SL_USART_EXTFLASH_RX_PIN 2 + +// USART0 CLK on PC03 +#define SL_USART_EXTFLASH_CLK_PORT gpioPortC +#define SL_USART_EXTFLASH_CLK_PIN 3 + +// USART0 CS on PC04 +#define SL_USART_EXTFLASH_CS_PORT gpioPortC +#define SL_USART_EXTFLASH_CS_PIN 4 + +// [USART_SL_USART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h b/hardware/board/config/brd4328b_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h new file mode 100644 index 0000000000..8bdc092f79 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Eusart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Eusart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_EUSART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_EUSART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EUSART_SPINCP + +// $[EUSART_SL_EUSART_SPINCP] +#define SL_EUSART_SPINCP_PERIPHERAL EUSART1 +#define SL_EUSART_SPINCP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC01 +#define SL_EUSART_SPINCP_TX_PORT gpioPortC +#define SL_EUSART_SPINCP_TX_PIN 1 + +// EUSART1 RX on PC02 +#define SL_EUSART_SPINCP_RX_PORT gpioPortC +#define SL_EUSART_SPINCP_RX_PIN 2 + +// EUSART1 CS on PC00 +#define SL_EUSART_SPINCP_CS_PORT gpioPortC +#define SL_EUSART_SPINCP_CS_PIN 0 + +// EUSART1 SCLK on PC03 +#define SL_EUSART_SPINCP_SCLK_PORT gpioPortC +#define SL_EUSART_SPINCP_SCLK_PIN 3 + +// [EUSART_SL_EUSART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/btl_spi_peripheral_usart_driver_cfg.h b/hardware/board/config/brd4328b_brd4001a/btl_spi_peripheral_usart_driver_cfg.h new file mode 100644 index 0000000000..4310485bc4 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/btl_spi_peripheral_usart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Usart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_USART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_USART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_USART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_USART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_SPINCP + +// $[USART_SL_USART_SPINCP] +#define SL_USART_SPINCP_PERIPHERAL USART0 +#define SL_USART_SPINCP_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_USART_SPINCP_TX_PORT gpioPortC +#define SL_USART_SPINCP_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_USART_SPINCP_RX_PORT gpioPortC +#define SL_USART_SPINCP_RX_PIN 2 + +// USART0 CS on PC00 +#define SL_USART_SPINCP_CS_PORT gpioPortC +#define SL_USART_SPINCP_CS_PIN 0 + +// USART0 CLK on PC03 +#define SL_USART_SPINCP_CLK_PORT gpioPortC +#define SL_USART_SPINCP_CLK_PIN 3 + +// [USART_SL_USART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/btl_uart_driver_cfg.h b/hardware/board/config/brd4328b_brd4001a/btl_uart_driver_cfg.h new file mode 100644 index 0000000000..42676179a9 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/btl_uart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Uart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_UART_DRIVER_CONFIG_H +#define BTL_UART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_UART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_UART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_UART +// $[USART_SL_SERIAL_UART] +#define SL_SERIAL_UART_PERIPHERAL USART0 +#define SL_SERIAL_UART_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_SERIAL_UART_TX_PORT gpioPortA +#define SL_SERIAL_UART_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_SERIAL_UART_RX_PORT gpioPortA +#define SL_SERIAL_UART_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_SERIAL_UART_CTS_PORT gpioPortA +#define SL_SERIAL_UART_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_SERIAL_UART_RTS_PORT gpioPortA +#define SL_SERIAL_UART_RTS_PIN 0 + +// [USART_SL_SERIAL_UART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT gpioPortB +#define SL_VCOM_ENABLE_PIN 0 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_UART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/iot_flash_cfg_exp.h b/hardware/board/config/brd4328b_brd4001a/iot_flash_cfg_exp.h new file mode 100644 index 0000000000..e54999dcf3 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/iot_flash_cfg_exp.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_EXP_H_ +#define _IOT_FLASH_CFG_EXP_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_EXP_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_EXP_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_EXP_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_EXP_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_EXP_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_EXP_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_EXP_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_EXP_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_EXP_SPI +// $[USART_IOT_FLASH_CFG_EXP_SPI] +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define IOT_FLASH_CFG_EXP_SPI_TX_PORT gpioPortC +#define IOT_FLASH_CFG_EXP_SPI_TX_PIN 1 + +// USART0 RX on PC02 +#define IOT_FLASH_CFG_EXP_SPI_RX_PORT gpioPortC +#define IOT_FLASH_CFG_EXP_SPI_RX_PIN 2 + +// USART0 CLK on PC03 +#define IOT_FLASH_CFG_EXP_SPI_CLK_PORT gpioPortC +#define IOT_FLASH_CFG_EXP_SPI_CLK_PIN 3 + +// USART0 CS on PC00 +#define IOT_FLASH_CFG_EXP_SPI_CS_PORT gpioPortC +#define IOT_FLASH_CFG_EXP_SPI_CS_PIN 0 + +// [USART_IOT_FLASH_CFG_EXP_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4328b_brd4001a/iot_flash_cfg_msc.h b/hardware/board/config/brd4328b_brd4001a/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..c2af14bc7d --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/iot_flash_cfg_msc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MSC_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/board/config/brd4328b_brd4001a/iot_flash_cfg_spiflash.h b/hardware/board/config/brd4328b_brd4001a/iot_flash_cfg_spiflash.h new file mode 100644 index 0000000000..0dd0bb9f60 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/iot_flash_cfg_spiflash.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_SPIFLASH_H_ +#define _IOT_FLASH_CFG_SPIFLASH_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_SPIFLASH_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_SPIFLASH_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_SPIFLASH_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_SPIFLASH_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_SPIFLASH_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_SPIFLASH_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_SPIFLASH_SPI +// $[USART_IOT_FLASH_CFG_SPIFLASH_SPI] +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PORT gpioPortC +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PIN 1 + +// USART0 RX on PC02 +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PORT gpioPortC +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PIN 2 + +// USART0 CLK on PC03 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PORT gpioPortC +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PIN 3 + +// USART0 CS on PC04 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PORT gpioPortC +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PIN 4 + +// [USART_IOT_FLASH_CFG_SPIFLASH_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_SPIFLASH_H_ */ diff --git a/hardware/board/config/brd4328b_brd4001a/iot_i2c_cfg_exp.h b/hardware/board/config/brd4328b_brd4001a/iot_i2c_cfg_exp.h new file mode 100644 index 0000000000..b538ec590e --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/iot_i2c_cfg_exp.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_EXP_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_EXP_H_ +#define _IOT_I2C_CFG_EXP_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_EXP_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_EXP_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_EXP_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_EXP_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_EXP_ENABLE +// $[GPIO_IOT_I2C_CFG_EXP_ENABLE] +#define IOT_I2C_CFG_EXP_ENABLE_PORT gpioPortA +#define IOT_I2C_CFG_EXP_ENABLE_PIN 5 + +// [GPIO_IOT_I2C_CFG_EXP_ENABLE]$ + +// IOT_I2C_CFG_EXP +// $[I2C_IOT_I2C_CFG_EXP] +#define IOT_I2C_CFG_EXP_PERIPHERAL I2C1 +#define IOT_I2C_CFG_EXP_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_EXP_SCL_PORT gpioPortC +#define IOT_I2C_CFG_EXP_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_EXP_SDA_PORT gpioPortC +#define IOT_I2C_CFG_EXP_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_EXP]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4328b_brd4001a/iot_i2c_cfg_sensor.h b/hardware/board/config/brd4328b_brd4001a/iot_i2c_cfg_sensor.h new file mode 100644 index 0000000000..0692295a6d --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/iot_i2c_cfg_sensor.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_SENSOR_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_SENSOR_H_ +#define _IOT_I2C_CFG_SENSOR_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_SENSOR_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_SENSOR_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_SENSOR_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_SENSOR_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_SENSOR_ENABLE +// $[GPIO_IOT_I2C_CFG_SENSOR_ENABLE] + +// [GPIO_IOT_I2C_CFG_SENSOR_ENABLE]$ + +// IOT_I2C_CFG_SENSOR +// $[I2C_IOT_I2C_CFG_SENSOR] +#define IOT_I2C_CFG_SENSOR_PERIPHERAL I2C1 +#define IOT_I2C_CFG_SENSOR_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_SENSOR_SCL_PORT gpioPortC +#define IOT_I2C_CFG_SENSOR_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_SENSOR_SDA_PORT gpioPortC +#define IOT_I2C_CFG_SENSOR_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_SENSOR]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_SENSOR_H_ */ diff --git a/hardware/board/config/brd4328b_brd4001a/iot_i2c_cfg_test.h b/hardware/board/config/brd4328b_brd4001a/iot_i2c_cfg_test.h new file mode 100644 index 0000000000..8fc615bc1e --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/iot_i2c_cfg_test.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_TEST_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_TEST_H_ +#define _IOT_I2C_CFG_TEST_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_TEST_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_TEST_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_TEST_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_TEST_ACCEPT_NACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_TEST_ENABLE +// $[GPIO_IOT_I2C_CFG_TEST_ENABLE] +#define IOT_I2C_CFG_TEST_ENABLE_PORT gpioPortA +#define IOT_I2C_CFG_TEST_ENABLE_PIN 5 + +// [GPIO_IOT_I2C_CFG_TEST_ENABLE]$ + +// IOT_I2C_CFG_TEST +// $[I2C_IOT_I2C_CFG_TEST] +#define IOT_I2C_CFG_TEST_PERIPHERAL I2C1 +#define IOT_I2C_CFG_TEST_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_TEST_SCL_PORT gpioPortC +#define IOT_I2C_CFG_TEST_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_TEST_SDA_PORT gpioPortC +#define IOT_I2C_CFG_TEST_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_TEST]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_TEST_H_ */ diff --git a/hardware/board/config/brd4328b_brd4001a/iot_pwm_cfg_exp.h b/hardware/board/config/brd4328b_brd4001a/iot_pwm_cfg_exp.h new file mode 100644 index 0000000000..07189e64c2 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/iot_pwm_cfg_exp.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_EXP_H_ +#define _IOT_PWM_CFG_EXP_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_EXP_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_EXP +// $[TIMER_IOT_PWM_CFG_EXP] +#define IOT_PWM_CFG_EXP_PERIPHERAL TIMER4 +#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 4 + +// TIMER4 CC0 on PA05 +#define IOT_PWM_CFG_EXP_CC0_PORT gpioPortA +#define IOT_PWM_CFG_EXP_CC0_PIN 5 + + + +// [TIMER_IOT_PWM_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4328b_brd4001a/iot_pwm_cfg_led0.h b/hardware/board/config/brd4328b_brd4001a/iot_pwm_cfg_led0.h new file mode 100644 index 0000000000..037f953d0f --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/iot_pwm_cfg_led0.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED0_H_ +#define _IOT_PWM_CFG_LED0_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED0_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED0 +// $[TIMER_IOT_PWM_CFG_LED0] +#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 +#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 + +// TIMER0 CC0 on PB02 +#define IOT_PWM_CFG_LED0_CC0_PORT gpioPortB +#define IOT_PWM_CFG_LED0_CC0_PIN 2 + + + +// [TIMER_IOT_PWM_CFG_LED0]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd4328b_brd4001a/iot_pwm_cfg_led1.h b/hardware/board/config/brd4328b_brd4001a/iot_pwm_cfg_led1.h new file mode 100644 index 0000000000..f290b8319e --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/iot_pwm_cfg_led1.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED1_H_ +#define _IOT_PWM_CFG_LED1_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED1_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED1 +// $[TIMER_IOT_PWM_CFG_LED1] +#define IOT_PWM_CFG_LED1_PERIPHERAL TIMER1 +#define IOT_PWM_CFG_LED1_PERIPHERAL_NO 1 + +// TIMER1 CC0 on PD03 +#define IOT_PWM_CFG_LED1_CC0_PORT gpioPortD +#define IOT_PWM_CFG_LED1_CC0_PIN 3 + + + +// [TIMER_IOT_PWM_CFG_LED1]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED1_H_ */ diff --git a/hardware/board/config/brd4328b_brd4001a/iot_spi_cfg_exp.h b/hardware/board/config/brd4328b_brd4001a/iot_spi_cfg_exp.h new file mode 100644 index 0000000000..d0dcc63132 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/iot_spi_cfg_exp.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_EXP_H_ +#define _IOT_SPI_CFG_EXP_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_EXP_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_EXP_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_EXP_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_EXP_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_EXP_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_EXP_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_EXP_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_EXP_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_EXP +// $[USART_IOT_SPI_CFG_EXP] +#define IOT_SPI_CFG_EXP_PERIPHERAL USART0 +#define IOT_SPI_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define IOT_SPI_CFG_EXP_TX_PORT gpioPortC +#define IOT_SPI_CFG_EXP_TX_PIN 1 + +// USART0 RX on PC02 +#define IOT_SPI_CFG_EXP_RX_PORT gpioPortC +#define IOT_SPI_CFG_EXP_RX_PIN 2 + +// USART0 CLK on PC03 +#define IOT_SPI_CFG_EXP_CLK_PORT gpioPortC +#define IOT_SPI_CFG_EXP_CLK_PIN 3 + +// USART0 CS on PC00 +#define IOT_SPI_CFG_EXP_CS_PORT gpioPortC +#define IOT_SPI_CFG_EXP_CS_PIN 0 + +// [USART_IOT_SPI_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4328b_brd4001a/iot_spi_cfg_loopback.h b/hardware/board/config/brd4328b_brd4001a/iot_spi_cfg_loopback.h new file mode 100644 index 0000000000..c5fe826e25 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/iot_spi_cfg_loopback.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_LOOPBACK_H_ +#define _IOT_SPI_CFG_LOOPBACK_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_LOOPBACK +// $[USART_IOT_SPI_CFG_LOOPBACK] +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define IOT_SPI_CFG_LOOPBACK_TX_PORT gpioPortC +#define IOT_SPI_CFG_LOOPBACK_TX_PIN 1 + +// USART0 RX on PC02 +#define IOT_SPI_CFG_LOOPBACK_RX_PORT gpioPortC +#define IOT_SPI_CFG_LOOPBACK_RX_PIN 2 + +// USART0 CLK on PC03 +#define IOT_SPI_CFG_LOOPBACK_CLK_PORT gpioPortC +#define IOT_SPI_CFG_LOOPBACK_CLK_PIN 3 + +// USART0 CS on PC00 +#define IOT_SPI_CFG_LOOPBACK_CS_PORT gpioPortC +#define IOT_SPI_CFG_LOOPBACK_CS_PIN 0 + +// [USART_IOT_SPI_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4328b_brd4001a/iot_uart_cfg_exp.h b/hardware/board/config/brd4328b_brd4001a/iot_uart_cfg_exp.h new file mode 100644 index 0000000000..b9a823f0fa --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/iot_uart_cfg_exp.h @@ -0,0 +1,126 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_EXP_H_ +#define _IOT_UART_CFG_EXP_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_EXP_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_EXP +// $[USART_IOT_UART_CFG_EXP] +#define IOT_UART_CFG_EXP_PERIPHERAL USART0 +#define IOT_UART_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define IOT_UART_CFG_EXP_TX_PORT gpioPortA +#define IOT_UART_CFG_EXP_TX_PIN 8 + +// USART0 RX on PA09 +#define IOT_UART_CFG_EXP_RX_PORT gpioPortA +#define IOT_UART_CFG_EXP_RX_PIN 9 + + + + + +// [USART_IOT_UART_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4328b_brd4001a/iot_uart_cfg_loopback.h b/hardware/board/config/brd4328b_brd4001a/iot_uart_cfg_loopback.h new file mode 100644 index 0000000000..b9d7759c50 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/iot_uart_cfg_loopback.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_LOOPBACK_H_ +#define _IOT_UART_CFG_LOOPBACK_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_LOOPBACK +// $[USART_IOT_UART_CFG_LOOPBACK] +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define IOT_UART_CFG_LOOPBACK_TX_PORT gpioPortA +#define IOT_UART_CFG_LOOPBACK_TX_PIN 8 + +// USART0 RX on PA09 +#define IOT_UART_CFG_LOOPBACK_RX_PORT gpioPortA +#define IOT_UART_CFG_LOOPBACK_RX_PIN 9 + + + +// USART0 RTS on PA00 +#define IOT_UART_CFG_LOOPBACK_RTS_PORT gpioPortA +#define IOT_UART_CFG_LOOPBACK_RTS_PIN 0 + +// USART0 CTS on PA10 +#define IOT_UART_CFG_LOOPBACK_CTS_PORT gpioPortA +#define IOT_UART_CFG_LOOPBACK_CTS_PIN 10 + +// [USART_IOT_UART_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4328b_brd4001a/iot_uart_cfg_vcom.h b/hardware/board/config/brd4328b_brd4001a/iot_uart_cfg_vcom.h new file mode 100644 index 0000000000..ea72497782 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/iot_uart_cfg_vcom.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_VCOM_H_ +#define _IOT_UART_CFG_VCOM_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_VCOM_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_VCOM_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_VCOM +// $[USART_IOT_UART_CFG_VCOM] +#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 +#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define IOT_UART_CFG_VCOM_TX_PORT gpioPortA +#define IOT_UART_CFG_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define IOT_UART_CFG_VCOM_RX_PORT gpioPortA +#define IOT_UART_CFG_VCOM_RX_PIN 9 + + + +// USART0 RTS on PA00 +#define IOT_UART_CFG_VCOM_RTS_PORT gpioPortA +#define IOT_UART_CFG_VCOM_RTS_PIN 0 + +// USART0 CTS on PA10 +#define IOT_UART_CFG_VCOM_CTS_PORT gpioPortA +#define IOT_UART_CFG_VCOM_CTS_PIN 10 + +// [USART_IOT_UART_CFG_VCOM]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd4328b_brd4001a/legacy_ncp_spi_config.h b/hardware/board/config/brd4328b_brd4001a/legacy_ncp_spi_config.h new file mode 100644 index 0000000000..d11f9eeb32 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/legacy_ncp_spi_config.h @@ -0,0 +1,60 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef LEGACY_NCP_SPI_CONFIG_H +#define LEGACY_NCP_SPI_CONFIG_H + +// <<< sl:start pin_tool >>> +// LEGACY_NCP_SPI +// $[USART_LEGACY_NCP_SPI] +#define LEGACY_NCP_SPI_PERIPHERAL USART0 +#define LEGACY_NCP_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define LEGACY_NCP_SPI_TX_PORT gpioPortC +#define LEGACY_NCP_SPI_TX_PIN 1 + +// USART0 RX on PC02 +#define LEGACY_NCP_SPI_RX_PORT gpioPortC +#define LEGACY_NCP_SPI_RX_PIN 2 + +// USART0 CLK on PC03 +#define LEGACY_NCP_SPI_CLK_PORT gpioPortC +#define LEGACY_NCP_SPI_CLK_PIN 3 + +// USART0 CS on PC00 +#define LEGACY_NCP_SPI_CS_PORT gpioPortC +#define LEGACY_NCP_SPI_CS_PIN 0 + +// [USART_LEGACY_NCP_SPI]$ + +// LEGACY_NCP_SPI_HOST_INT +// $[GPIO_LEGACY_NCP_SPI_HOST_INT] +#define LEGACY_NCP_SPI_HOST_INT_PORT gpioPortA +#define LEGACY_NCP_SPI_HOST_INT_PIN 5 + +// [GPIO_LEGACY_NCP_SPI_HOST_INT]$ + +// LEGACY_NCP_SPI_WAKE_INT +// $[GPIO_LEGACY_NCP_SPI_WAKE_INT] +#define LEGACY_NCP_SPI_WAKE_INT_PORT gpioPortD +#define LEGACY_NCP_SPI_WAKE_INT_PIN 2 + +// [GPIO_LEGACY_NCP_SPI_WAKE_INT]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_board_control_config.h b/hardware/board/config/brd4328b_brd4001a/sl_board_control_config.h new file mode 100644 index 0000000000..049d22e03a --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortB +#define SL_BOARD_ENABLE_VCOM_PIN 0 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortC +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 0 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_secondary_spi_eusart_exp_config.h b/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_secondary_spi_eusart_exp_config.h new file mode 100644 index 0000000000..e7b20e6571 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_secondary_spi_eusart_exp_config.h @@ -0,0 +1,120 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CPC_DRV_SPI_EUSART_EXP_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_EUSART_EXP_SECONDARY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// CPC-Secondary SPI Driver Configuration + +// Queues size configuration + +// Number of frame that can be queued in the driver receive queue +// A greater number decreases the chances of retransmission due to dropped frames at the cost of memory footprint +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// A greater number increases the transmission responsiveness at the cost of memory footprint +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 +// + +// LDMA SYNCTRIG bit configuration +// The LDMA SYNCTRIG bit number for the TX availability [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// Default : 7 +// 7 +#define SL_CPC_DRV_SPI_EXP_TX_AVAILABILITY_SYNCTRIG_CH 6 + +// The LDMA SYNCTRIG bit number for the CS PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 5 +// 5 +#define SL_CPC_DRV_SPI_EXP_CS_SYNCTRIG_PRS_CH 5 + +// The LDMA SYNCTRIG bit number for the TXC PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 6 +// 6 +#define SL_CPC_DRV_SPI_EXP_TXC_SYNCTRIG_PRS_CH 4 +// + +// Chip Select PRS Routing +// The Chip Select input to EXTernal Interrupt number <0-7> +// The CS input needs to be routed to a PRS channel in order to manipulate its LDMA SYNCTRIG bit. +// Modify this value to avoid collisions if any specific EXTI number needs to be used elsewhere in the project. +// Note that only EXTI0..7 can be used as input for a PRS channel, and only pins Px0..7 can be routed to those. +// Default : 0 (pin0..4 of any port) +// 0 +#define SL_CPC_DRV_SPI_EXP_CS_EXTI_NUMBER 0 +// + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_EXP_RX_IRQ +// $[GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ] +#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PORT gpioPortA +#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PIN 5 + +// [GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ]$ + +// SL_CPC_DRV_SPI_EXP +// $[EUSART_SL_CPC_DRV_SPI_EXP] +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL EUSART1 +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC01 +#define SL_CPC_DRV_SPI_EXP_TX_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_TX_PIN 1 + +// EUSART1 RX on PC02 +#define SL_CPC_DRV_SPI_EXP_RX_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_RX_PIN 2 + +// EUSART1 SCLK on PC03 +#define SL_CPC_DRV_SPI_EXP_SCLK_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_SCLK_PIN 3 + +// EUSART1 CS on PC00 +#define SL_CPC_DRV_SPI_EXP_CS_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_CS_PIN 0 + +// [EUSART_SL_CPC_DRV_SPI_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h b/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h new file mode 100644 index 0000000000..c69f5a5ed0 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h @@ -0,0 +1,110 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// CPC-Secondary SPI Driver Configuration + +// Queues size configuration + +// Number of frame that can be queued in the driver receive queue +// A greater number decreases the chances of retransmission due to dropped frames at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// A greater number increases the transmission responsiveness at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 +// + +// LDMA SYNCTRIG bit configuration +// The LDMA SYNCTRIG bit number for the TX availability [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// Default : 7 +// 7 +#define SL_CPC_DRV_SPI_EXP_TX_AVAILABILITY_SYNCTRIG_CH 6 + +// The LDMA SYNCTRIG bit number for the CS PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 5 +// 5 +#define SL_CPC_DRV_SPI_EXP_CS_SYNCTRIG_PRS_CH 5 + +// The LDMA SYNCTRIG bit number for the TXC PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 6 +// 6 +#define SL_CPC_DRV_SPI_EXP_TXC_SYNCTRIG_PRS_CH 4 + +// +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_EXP_RX_IRQ +// $[GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ] +#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PORT gpioPortA +#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PIN 5 + +// [GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ]$ + +// SL_CPC_DRV_SPI_EXP +// $[USART_SL_CPC_DRV_SPI_EXP] +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_CPC_DRV_SPI_EXP_TX_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_CPC_DRV_SPI_EXP_RX_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_RX_PIN 2 + +// USART0 CLK on PC03 +#define SL_CPC_DRV_SPI_EXP_CLK_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_CLK_PIN 3 + +// USART0 CS on PC00 +#define SL_CPC_DRV_SPI_EXP_CS_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_CS_PIN 0 + +// [USART_SL_CPC_DRV_SPI_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h b/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h new file mode 100644 index 0000000000..d99b864969 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlNone +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[EUSART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUSART1 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC01 +#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_TX_PIN 1 + +// EUSART1 RX on PC02 +#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_RX_PIN 2 + +// EUSART1 CTS on PC03 +#define SL_CPC_DRV_UART_EXP_CTS_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_CTS_PIN 3 + +// EUSART1 RTS on PC00 +#define SL_CPC_DRV_UART_EXP_RTS_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_RTS_PIN 0 + +// [EUSART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h b/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h new file mode 100644 index 0000000000..6901c2ac47 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlNone +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[EUSART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUSART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 + +// [EUSART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_uart_usart_exp_config.h b/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_uart_usart_exp_config.h new file mode 100644 index 0000000000..467312777c --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_uart_usart_exp_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_USART_EXP_CONFIG_H + +// CPC - UART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[USART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_RX_PIN 2 + +// USART0 CTS on PC03 +#define SL_CPC_DRV_UART_EXP_CTS_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_CTS_PIN 3 + +// USART0 RTS on PC00 +#define SL_CPC_DRV_UART_EXP_RTS_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_RTS_PIN 0 + +// [USART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h b/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h new file mode 100644 index 0000000000..5e13497282 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_USART_VCOM_CONFIG_H + +// CPC - UART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[USART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 + +// [USART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/platform/radio/rail_lib/plugin/rail_util_sequencer/config/efr32xg13/seq_1_zwave/sl_rail_util_sequencer_config.h b/hardware/board/config/brd4328b_brd4001a/sl_cpc_gpio_expander_gpio_btn0_config.h similarity index 62% rename from platform/radio/rail_lib/plugin/rail_util_sequencer/config/efr32xg13/seq_1_zwave/sl_rail_util_sequencer_config.h rename to hardware/board/config/brd4328b_brd4001a/sl_cpc_gpio_expander_gpio_btn0_config.h index 3701c8af33..331c3bc888 100644 --- a/platform/radio/rail_lib/plugin/rail_util_sequencer/config/efr32xg13/seq_1_zwave/sl_rail_util_sequencer_config.h +++ b/hardware/board/config/brd4328b_brd4001a/sl_cpc_gpio_expander_gpio_btn0_config.h @@ -1,6 +1,6 @@ /***************************************************************************//** * @file - * @brief + * @brief CPC GPIO Expander instance configuration file. ******************************************************************************* * # License * Copyright 2023 Silicon Laboratories Inc. www.silabs.com @@ -28,21 +28,26 @@ * ******************************************************************************/ -#ifndef SL_RAIL_UTIL_SEQUENCER_H -#define SL_RAIL_UTIL_SEQUENCER_H +// <<< Use Configuration Wizard in Context Menu >>> -#include "rail.h" +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H -#ifdef __cplusplus -extern "C" { -#endif +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_NAME "BTN0" -#define SL_RAIL_UTIL_SEQUENCER_RUNTIME_IMAGE_SELECTION 0 +// <<< end of configuration section >>> -#define SL_RAIL_UTIL_SEQUENCER_IMAGE RAIL_SEQ_IMAGE_ZWAVE +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN0 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PORT gpioPortB +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PIN 1 -#ifdef __cplusplus -} -#endif +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0]$ -#endif // SL_RAIL_UTIL_SEQUENCER_H +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H */ diff --git a/hardware/board/config/brd4328b_brd4001a/sl_cpc_gpio_expander_gpio_btn1_config.h b/hardware/board/config/brd4328b_brd4001a/sl_cpc_gpio_expander_gpio_btn1_config.h new file mode 100644 index 0000000000..74ef962318 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_cpc_gpio_expander_gpio_btn1_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_NAME "BTN1" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN1 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PORT gpioPortB +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PIN 3 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H */ diff --git a/hardware/board/config/brd4328b_brd4001a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4328b_brd4001a/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..78b14ee253 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_device_init_hfxo_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 39000000 +#define SL_DEVICE_INIT_HFXO_FREQ 39000000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 140 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_i2cspm_sensor_config.h b/hardware/board/config/brd4328b_brd4001a/sl_i2cspm_sensor_config.h new file mode 100644 index 0000000000..b5fedf050d --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_i2cspm_sensor_config.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief I2CSPM Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_I2CSPM_SENSOR_CONFIG_H +#define SL_I2CSPM_SENSOR_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu + +// I2CSPM settings + +// Reference clock frequency +// Frequency in Hz of the reference clock. +// Select 0 to use the frequency of the currently selected clock. +// Default: 0 +#define SL_I2CSPM_SENSOR_REFERENCE_CLOCK 0 + +// Speed mode +// <0=> Standard mode (100kbit/s) +// <1=> Fast mode (400kbit/s) +// <2=> Fast mode plus (1Mbit/s) +// Default: 0 +#define SL_I2CSPM_SENSOR_SPEED_MODE 0 +// end I2CSPM config + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_I2CSPM_SENSOR +// $[I2C_SL_I2CSPM_SENSOR] +#define SL_I2CSPM_SENSOR_PERIPHERAL I2C1 +#define SL_I2CSPM_SENSOR_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define SL_I2CSPM_SENSOR_SCL_PORT gpioPortC +#define SL_I2CSPM_SENSOR_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define SL_I2CSPM_SENSOR_SDA_PORT gpioPortC +#define SL_I2CSPM_SENSOR_SDA_PIN 7 + +// [I2C_SL_I2CSPM_SENSOR]$ +// <<< sl:end pin_tool >>> + +#endif // SL_I2CSPM_SENSOR_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4328b_brd4001a/sl_iostream_eusart_exp_config.h new file mode 100644 index 0000000000..cbe96bbdcb --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_iostream_eusart_exp_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_IOSTREAM_EUSART_EXP_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_IOSTREAM_EUSART_EXP_STOP_BITS eusartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: eusartHwFlowControlNone +#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP +// $[EUSART_SL_IOSTREAM_EUSART_EXP] +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUSART0 +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_IOSTREAM_EUSART_EXP_TX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_EXP_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_IOSTREAM_EUSART_EXP_RX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_EXP_RX_PIN 9 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4328b_brd4001a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4328b_brd4001a/sl_iostream_eusart_vcom_config.h new file mode 100644 index 0000000000..db8ecd8a79 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_iostream_eusart_vcom_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H +#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_IOSTREAM_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: eusartHwFlowControlNone +#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_VCOM +// $[EUSART_SL_IOSTREAM_EUSART_VCOM] +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_IOSTREAM_EUSART_VCOM_TX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_IOSTREAM_EUSART_VCOM_RX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4328b_brd4001a/sl_iostream_usart_exp_config.h b/hardware/board/config/brd4328b_brd4001a/sl_iostream_usart_exp_config.h new file mode 100644 index 0000000000..e5f8850848 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_iostream_usart_exp_config.h @@ -0,0 +1,109 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H +#define SL_IOSTREAM_USART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP +// $[USART_SL_IOSTREAM_USART_EXP] +#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_IOSTREAM_USART_EXP_TX_PORT gpioPortA +#define SL_IOSTREAM_USART_EXP_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_IOSTREAM_USART_EXP_RX_PORT gpioPortA +#define SL_IOSTREAM_USART_EXP_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_IOSTREAM_USART_EXP_CTS_PORT gpioPortA +#define SL_IOSTREAM_USART_EXP_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_IOSTREAM_USART_EXP_RTS_PORT gpioPortA +#define SL_IOSTREAM_USART_EXP_RTS_PIN 0 + +// [USART_SL_IOSTREAM_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4328b_brd4001a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd4328b_brd4001a/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..85da71b67b --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_iostream_usart_vcom_config.h @@ -0,0 +1,109 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortA +#define SL_IOSTREAM_USART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortA +#define SL_IOSTREAM_USART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortA +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortA +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 0 + +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4328b_brd4001a/sl_memlcd_eusart_config.h b/hardware/board/config/brd4328b_brd4001a/sl_memlcd_eusart_config.h new file mode 100644 index 0000000000..4b21c6f11e --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_memlcd_eusart_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief SPI abstraction used by memory lcd display + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[EUSART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL EUSART1 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 1 + +// EUSART1 TX on PC01 +#define SL_MEMLCD_SPI_TX_PORT gpioPortC +#define SL_MEMLCD_SPI_TX_PIN 1 + +// EUSART1 SCLK on PC03 +#define SL_MEMLCD_SPI_SCLK_PORT gpioPortC +#define SL_MEMLCD_SPI_SCLK_PIN 3 + +// [EUSART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT gpioPortC +#define SL_MEMLCD_SPI_CS_PIN 8 + +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT gpioPortC +#define SL_MEMLCD_EXTCOMIN_PIN 6 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4328b_brd4001a/sl_memlcd_usart_config.h b/hardware/board/config/brd4328b_brd4001a/sl_memlcd_usart_config.h new file mode 100644 index 0000000000..3490e3829e --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_memlcd_usart_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief SPI abstraction used by memory lcd display + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[USART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL USART0 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_MEMLCD_SPI_TX_PORT gpioPortC +#define SL_MEMLCD_SPI_TX_PIN 1 + +// USART0 CLK on PC03 +#define SL_MEMLCD_SPI_CLK_PORT gpioPortC +#define SL_MEMLCD_SPI_CLK_PIN 3 + +// [USART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT gpioPortC +#define SL_MEMLCD_SPI_CS_PIN 8 + +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT gpioPortC +#define SL_MEMLCD_EXTCOMIN_PIN 6 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4328b_brd4001a/sl_mx25_flash_shutdown_eusart_config.h b/hardware/board/config/brd4328b_brd4001a/sl_mx25_flash_shutdown_eusart_config.h new file mode 100644 index 0000000000..63d60d5510 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_mx25_flash_shutdown_eusart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {eusart signal=TX,RX,SCLK} SL_MX25_FLASH_SHUTDOWN +// [EUSART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL EUSART1 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 1 + +// EUSART1 TX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 1 + +// EUSART1 RX on PC02 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 2 + +// EUSART1 SCLK on PC03 +#define SL_MX25_FLASH_SHUTDOWN_SCLK_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_SCLK_PIN 3 + +// [EUSART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_mx25_flash_shutdown_usart_config.h b/hardware/board/config/brd4328b_brd4001a/sl_mx25_flash_shutdown_usart_config.h new file mode 100644 index 0000000000..3b217bb736 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_mx25_flash_shutdown_usart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 2 + +// USART0 CLK on PC03 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 3 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_ncp_spidrv_usart_config.h b/hardware/board/config/brd4328b_brd4001a/sl_ncp_spidrv_usart_config.h new file mode 100644 index 0000000000..3bd42bb9d8 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_ncp_spidrv_usart_config.h @@ -0,0 +1,94 @@ +/***************************************************************************//** + * @file + * @brief Open thread NCP spidrv usart configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_NCP_SPIDRV_USART_CONFIG_H +#define SL_NCP_SPIDRV_USART_CONFIG_H +#include "spidrv.h" + +// NCP spidrv usart Configuration + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_NCP_SPIDRV_USART_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_NCP_SPIDRV_USART_CLOCK_MODE spidrvClockMode0 + +// Chip Select Interrupt Number on Falling Edge +// Default: 10 +#define SL_NCP_SPIDRV_USART_CS_FALLING_EDGE_INT_NO 0 + +// Chip Select Interrupt Number on Rising Edge +// Default: 9 +#define SL_NCP_SPIDRV_USART_CS_RISING_EDGE_INT_NO 1 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_NCP_SPIDRV_USART_HOST_INT +// $[GPIO_SL_NCP_SPIDRV_USART_HOST_INT] +#define SL_NCP_SPIDRV_USART_HOST_INT_PORT gpioPortA +#define SL_NCP_SPIDRV_USART_HOST_INT_PIN 5 + +// [GPIO_SL_NCP_SPIDRV_USART_HOST_INT]$ + +// SL_NCP_SPIDRV_USART +// $[USART_SL_NCP_SPIDRV_USART] +#define SL_NCP_SPIDRV_USART_PERIPHERAL USART0 +#define SL_NCP_SPIDRV_USART_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_NCP_SPIDRV_USART_TX_PORT gpioPortC +#define SL_NCP_SPIDRV_USART_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_NCP_SPIDRV_USART_RX_PORT gpioPortC +#define SL_NCP_SPIDRV_USART_RX_PIN 2 + +// USART0 CLK on PC03 +#define SL_NCP_SPIDRV_USART_CLK_PORT gpioPortC +#define SL_NCP_SPIDRV_USART_CLK_PIN 3 + +// USART0 CS on PC00 +#define SL_NCP_SPIDRV_USART_CS_PORT gpioPortC +#define SL_NCP_SPIDRV_USART_CS_PIN 0 + +// [USART_SL_NCP_SPIDRV_USART]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_NCP_SPIDRV_USART_CONFIG_H */ diff --git a/hardware/board/config/brd4328b_brd4001a/sl_pwm_init_led0_config.h b/hardware/board/config/brd4328b_brd4001a/sl_pwm_init_led0_config.h new file mode 100644 index 0000000000..a86f33fec9 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_pwm_init_led0_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef PWM_INIT_LED0_CONFIG_H +#define PWM_INIT_LED0_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED0_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED0_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED0 +// $[TIMER_SL_PWM_LED0] +#define SL_PWM_LED0_PERIPHERAL TIMER0 +#define SL_PWM_LED0_PERIPHERAL_NO 0 + +#define SL_PWM_LED0_OUTPUT_CHANNEL 0 +// TIMER0 CC0 on PB02 +#define SL_PWM_LED0_OUTPUT_PORT gpioPortB +#define SL_PWM_LED0_OUTPUT_PIN 2 + +// [TIMER_SL_PWM_LED0]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_pwm_init_led1_config.h b/hardware/board/config/brd4328b_brd4001a/sl_pwm_init_led1_config.h new file mode 100644 index 0000000000..199e48f279 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_pwm_init_led1_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef PWM_INIT_LED1_CONFIG_H +#define PWM_INIT_LED1_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED1_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED1_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED1 +// $[TIMER_SL_PWM_LED1] +#define SL_PWM_LED1_PERIPHERAL TIMER1 +#define SL_PWM_LED1_PERIPHERAL_NO 1 + +#define SL_PWM_LED1_OUTPUT_CHANNEL 0 +// TIMER1 CC0 on PD03 +#define SL_PWM_LED1_OUTPUT_PORT gpioPortD +#define SL_PWM_LED1_OUTPUT_PIN 3 + +// [TIMER_SL_PWM_LED1]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // PWM_INIT_LED1_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_rail_util_pti_config.h b/hardware/board/config/brd4328b_brd4001a/sl_rail_util_pti_config.h new file mode 100644 index 0000000000..5165fc4204 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_rail_util_pti_config.h @@ -0,0 +1,73 @@ +/***************************************************************************//** + * @file + * @brief Packet Trace Information configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PTI_CONFIG_H +#define SL_RAIL_UTIL_PTI_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PTI Configuration + +// PTI mode +// UART +// UART onewire +// SPI +// Disabled +// Default: RAIL_PTI_MODE_UART +#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART + +// PTI Baud Rate (Hertz) +// <147800-20000000:1> +// Default: 1600000 +#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_RAIL_UTIL_PTI +// $[PTI_SL_RAIL_UTIL_PTI] +#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI + +// PTI DOUT on PD04 +#define SL_RAIL_UTIL_PTI_DOUT_PORT gpioPortD +#define SL_RAIL_UTIL_PTI_DOUT_PIN 4 + +// PTI DFRAME on PD05 +#define SL_RAIL_UTIL_PTI_DFRAME_PORT gpioPortD +#define SL_RAIL_UTIL_PTI_DFRAME_PIN 5 + + +// [PTI_SL_RAIL_UTIL_PTI]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_simple_button_btn0_config.h b/hardware/board/config/brd4328b_brd4001a/sl_simple_button_btn0_config.h new file mode 100644 index 0000000000..06f7fd29f5 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_simple_button_btn0_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H + +#include "em_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN0 +// $[GPIO_SL_SIMPLE_BUTTON_BTN0] +#define SL_SIMPLE_BUTTON_BTN0_PORT gpioPortB +#define SL_SIMPLE_BUTTON_BTN0_PIN 1 + +// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_simple_button_btn1_config.h b/hardware/board/config/brd4328b_brd4001a/sl_simple_button_btn1_config.h new file mode 100644 index 0000000000..ffd08203b6 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_simple_button_btn1_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN1_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN1_CONFIG_H + +#include "em_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN1_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN1 +// $[GPIO_SL_SIMPLE_BUTTON_BTN1] +#define SL_SIMPLE_BUTTON_BTN1_PORT gpioPortB +#define SL_SIMPLE_BUTTON_BTN1_PIN 3 + +// [GPIO_SL_SIMPLE_BUTTON_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN1_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_simple_led_led0_config.h b/hardware/board/config/brd4328b_brd4001a/sl_simple_led_led0_config.h new file mode 100644 index 0000000000..2e6c868888 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_simple_led_led0_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED0_CONFIG_H +#define SL_SIMPLE_LED_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED0_PORT gpioPortB +#define SL_SIMPLE_LED_LED0_PIN 2 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_simple_led_led1_config.h b/hardware/board/config/brd4328b_brd4001a/sl_simple_led_led1_config.h new file mode 100644 index 0000000000..baadcd50fd --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_simple_led_led1_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED1_CONFIG_H +#define SL_SIMPLE_LED_LED1_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED1 +// $[GPIO_SL_SIMPLE_LED_LED1] +#define SL_SIMPLE_LED_LED1_PORT gpioPortD +#define SL_SIMPLE_LED_LED1_PIN 3 + +// [GPIO_SL_SIMPLE_LED_LED1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_simple_led_led2_config.h b/hardware/board/config/brd4328b_brd4001a/sl_simple_led_led2_config.h new file mode 100644 index 0000000000..b20941f4a2 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_simple_led_led2_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED2_CONFIG_H +#define SL_SIMPLE_LED_LED2_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED2_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED2 +// $[GPIO_SL_SIMPLE_LED_LED2] +#define SL_SIMPLE_LED_LED2_PORT gpioPortB +#define SL_SIMPLE_LED_LED2_PIN 4 + +// [GPIO_SL_SIMPLE_LED_LED2]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED2_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_simple_led_led3_config.h b/hardware/board/config/brd4328b_brd4001a/sl_simple_led_led3_config.h new file mode 100644 index 0000000000..2ad6e07cea --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_simple_led_led3_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED3_CONFIG_H +#define SL_SIMPLE_LED_LED3_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED3_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED3 +// $[GPIO_SL_SIMPLE_LED_LED3] +#define SL_SIMPLE_LED_LED3_PORT gpioPortB +#define SL_SIMPLE_LED_LED3_PIN 5 + +// [GPIO_SL_SIMPLE_LED_LED3]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED3_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_simple_led_led4_config.h b/hardware/board/config/brd4328b_brd4001a/sl_simple_led_led4_config.h new file mode 100644 index 0000000000..a89bdb41d8 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_simple_led_led4_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED4_CONFIG_H +#define SL_SIMPLE_LED_LED4_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED4_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED4 +// $[GPIO_SL_SIMPLE_LED_LED4] +#define SL_SIMPLE_LED_LED4_PORT gpioPortB +#define SL_SIMPLE_LED_LED4_PIN 6 + +// [GPIO_SL_SIMPLE_LED_LED4]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED4_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4328b_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..7a76addbf5 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,97 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PB04 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 4 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PB05 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 5 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PB06 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 6 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_spidrv_eusart_exp_config.h b/hardware/board/config/brd4328b_brd4001a/sl_spidrv_eusart_exp_config.h new file mode 100644 index 0000000000..afe8ad9d26 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_spidrv_eusart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EUSART_EXP_CONFIG_H +#define SL_SPIDRV_EUSART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EUSART_EXP_BITRATE 1000000 + +// SPI frame length <7-16> +// Default: 8 +#define SL_SPIDRV_EUSART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EUSART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EUSART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EUSART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EUSART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EUSART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EUSART_EXP +// $[EUSART_SL_SPIDRV_EUSART_EXP] +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC01 +#define SL_SPIDRV_EUSART_EXP_TX_PORT gpioPortC +#define SL_SPIDRV_EUSART_EXP_TX_PIN 1 + +// EUSART1 RX on PC02 +#define SL_SPIDRV_EUSART_EXP_RX_PORT gpioPortC +#define SL_SPIDRV_EUSART_EXP_RX_PIN 2 + +// EUSART1 SCLK on PC03 +#define SL_SPIDRV_EUSART_EXP_SCLK_PORT gpioPortC +#define SL_SPIDRV_EUSART_EXP_SCLK_PIN 3 + +// EUSART1 CS on PC00 +#define SL_SPIDRV_EUSART_EXP_CS_PORT gpioPortC +#define SL_SPIDRV_EUSART_EXP_CS_PIN 0 + +// [EUSART_SL_SPIDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EUSART_EXP_CONFIG_HEUSART_ diff --git a/hardware/board/config/brd4328b_brd4001a/sl_spidrv_exp_config.h b/hardware/board/config/brd4328b_brd4001a/sl_spidrv_exp_config.h new file mode 100644 index 0000000000..eb6cae804a --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_spidrv_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EXP_CONFIG_H +#define SL_SPIDRV_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EXP +// $[USART_SL_SPIDRV_EXP] +#define SL_SPIDRV_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_SPIDRV_EXP_TX_PORT gpioPortC +#define SL_SPIDRV_EXP_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_SPIDRV_EXP_RX_PORT gpioPortC +#define SL_SPIDRV_EXP_RX_PIN 2 + +// USART0 CLK on PC03 +#define SL_SPIDRV_EXP_CLK_PORT gpioPortC +#define SL_SPIDRV_EXP_CLK_PIN 3 + +// USART0 CS on PC00 +#define SL_SPIDRV_EXP_CS_PORT gpioPortC +#define SL_SPIDRV_EXP_CS_PIN 0 + +// [USART_SL_SPIDRV_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_spidrv_usart_exp_config.h b/hardware/board/config/brd4328b_brd4001a/sl_spidrv_usart_exp_config.h new file mode 100644 index 0000000000..213750de5d --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_spidrv_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_USART_EXP_CONFIG_H +#define SL_SPIDRV_USART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_USART_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_USART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_USART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_USART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_USART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_USART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_USART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_USART_EXP +// $[USART_SL_SPIDRV_USART_EXP] +#define SL_SPIDRV_USART_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_SPIDRV_USART_EXP_TX_PORT gpioPortC +#define SL_SPIDRV_USART_EXP_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_SPIDRV_USART_EXP_RX_PORT gpioPortC +#define SL_SPIDRV_USART_EXP_RX_PIN 2 + +// USART0 CLK on PC03 +#define SL_SPIDRV_USART_EXP_CLK_PORT gpioPortC +#define SL_SPIDRV_USART_EXP_CLK_PIN 3 + +// USART0 CS on PC00 +#define SL_SPIDRV_USART_EXP_CS_PORT gpioPortC +#define SL_SPIDRV_USART_EXP_CS_PIN 0 + +// [USART_SL_SPIDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_eusart_exp_config.h new file mode 100644 index 0000000000..3554ed257e --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP +// $[EUSART_SL_UARTDRV_EUSART_EXP] +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUSART0 +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_UARTDRV_EUSART_EXP_TX_PORT gpioPortA +#define SL_UARTDRV_EUSART_EXP_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_UARTDRV_EUSART_EXP_RX_PORT gpioPortA +#define SL_UARTDRV_EUSART_EXP_RX_PIN 9 + + + +// [EUSART_SL_UARTDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_eusart_vcom_config.h new file mode 100644 index 0000000000..c4dc8e9cf0 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_eusart_vcom_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H +#define SL_UARTDRV_EUSART_VCOM_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_VCOM_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_VCOM +// $[EUSART_SL_UARTDRV_EUSART_VCOM] +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_UARTDRV_EUSART_VCOM_TX_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_UARTDRV_EUSART_VCOM_RX_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_UARTDRV_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_usart_exp_config.h new file mode 100644 index 0000000000..db65aeef71 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_usart_exp_config.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_CONFIG_H +#define SL_UARTDRV_USART_EXP_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP +// $[USART_SL_UARTDRV_USART_EXP] +#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 +#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_UARTDRV_USART_EXP_TX_PORT gpioPortA +#define SL_UARTDRV_USART_EXP_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_UARTDRV_USART_EXP_RX_PORT gpioPortA +#define SL_UARTDRV_USART_EXP_RX_PIN 9 + + + +// [USART_SL_UARTDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..b27591e686 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4001a/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 + +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/btl_euart_driver_cfg.h b/hardware/board/config/brd4328b_brd4002a/btl_euart_driver_cfg.h new file mode 100644 index 0000000000..9f7c84438c --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/btl_euart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader euart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EUART_DRIVER_CONFIG_H +#define BTL_EUART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_EUART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_EUART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_EUART +// $[EUSART_SL_SERIAL_EUART] +#define SL_SERIAL_EUART_PERIPHERAL EUSART0 +#define SL_SERIAL_EUART_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_SERIAL_EUART_TX_PORT gpioPortA +#define SL_SERIAL_EUART_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_SERIAL_EUART_RX_PORT gpioPortA +#define SL_SERIAL_EUART_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_SERIAL_EUART_CTS_PORT gpioPortA +#define SL_SERIAL_EUART_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_SERIAL_EUART_RTS_PORT gpioPortA +#define SL_SERIAL_EUART_RTS_PIN 0 + +// [EUSART_SL_SERIAL_EUART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT gpioPortB +#define SL_VCOM_ENABLE_PIN 0 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EUART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/btl_ezsp_gpio_activation_cfg.h b/hardware/board/config/brd4328b_brd4002a/btl_ezsp_gpio_activation_cfg.h new file mode 100644 index 0000000000..c8016ffd03 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/btl_ezsp_gpio_activation_cfg.h @@ -0,0 +1,52 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader EZSP GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EZSP_GPIO_ACTIVATION_CONFIG_H +#define BTL_EZSP_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of SPI NCP + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_EZSP_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EZSPSPI_HOST_INT +// $[GPIO_SL_EZSPSPI_HOST_INT] +#define SL_EZSPSPI_HOST_INT_PORT gpioPortA +#define SL_EZSPSPI_HOST_INT_PIN 5 + +// [GPIO_SL_EZSPSPI_HOST_INT]$ + +// SL_EZSPSPI_WAKE_INT +// $[GPIO_SL_EZSPSPI_WAKE_INT] +#define SL_EZSPSPI_WAKE_INT_PORT gpioPortD +#define SL_EZSPSPI_WAKE_INT_PIN 2 + +// [GPIO_SL_EZSPSPI_WAKE_INT]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EZSP_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/btl_gpio_activation_cfg.h b/hardware/board/config/brd4328b_brd4002a/btl_gpio_activation_cfg.h new file mode 100644 index 0000000000..f73756e2d5 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/btl_gpio_activation_cfg.h @@ -0,0 +1,47 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_GPIO_ACTIVATION_CONFIG_H +#define BTL_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of Bootloader Entry + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BTL_BUTTON + +// $[GPIO_SL_BTL_BUTTON] +#define SL_BTL_BUTTON_PORT gpioPortB +#define SL_BTL_BUTTON_PIN 1 + +// [GPIO_SL_BTL_BUTTON]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/btl_spi_controller_eusart_driver_cfg.h b/hardware/board/config/brd4328b_brd4002a/btl_spi_controller_eusart_driver_cfg.h new file mode 100644 index 0000000000..dfa2459451 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/btl_spi_controller_eusart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Eusart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller EUSART Driver + +// Frequency +// Default: 6400000 +#define SL_EUSART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EUSART_EXTFLASH +// $[EUSART_SL_EUSART_EXTFLASH] +#define SL_EUSART_EXTFLASH_PERIPHERAL EUSART1 +#define SL_EUSART_EXTFLASH_PERIPHERAL_NO 1 + +// EUSART1 TX on PC01 +#define SL_EUSART_EXTFLASH_TX_PORT gpioPortC +#define SL_EUSART_EXTFLASH_TX_PIN 1 + +// EUSART1 RX on PC02 +#define SL_EUSART_EXTFLASH_RX_PORT gpioPortC +#define SL_EUSART_EXTFLASH_RX_PIN 2 + +// EUSART1 SCLK on PC03 +#define SL_EUSART_EXTFLASH_SCLK_PORT gpioPortC +#define SL_EUSART_EXTFLASH_SCLK_PIN 3 + +// EUSART1 CS on PC04 +#define SL_EUSART_EXTFLASH_CS_PORT gpioPortC +#define SL_EUSART_EXTFLASH_CS_PIN 4 + +// [EUSART_SL_EUSART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/btl_spi_controller_usart_driver_cfg.h b/hardware/board/config/brd4328b_brd4002a/btl_spi_controller_usart_driver_cfg.h new file mode 100644 index 0000000000..a666144221 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/btl_spi_controller_usart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller USART Driver + +// Frequency +// Default: 6400000 +#define SL_USART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_EXTFLASH +// $[USART_SL_USART_EXTFLASH] +#define SL_USART_EXTFLASH_PERIPHERAL USART0 +#define SL_USART_EXTFLASH_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_USART_EXTFLASH_TX_PORT gpioPortC +#define SL_USART_EXTFLASH_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_USART_EXTFLASH_RX_PORT gpioPortC +#define SL_USART_EXTFLASH_RX_PIN 2 + +// USART0 CLK on PC03 +#define SL_USART_EXTFLASH_CLK_PORT gpioPortC +#define SL_USART_EXTFLASH_CLK_PIN 3 + +// USART0 CS on PC04 +#define SL_USART_EXTFLASH_CS_PORT gpioPortC +#define SL_USART_EXTFLASH_CS_PIN 4 + +// [USART_SL_USART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h b/hardware/board/config/brd4328b_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h new file mode 100644 index 0000000000..8bdc092f79 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Eusart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Eusart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_EUSART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_EUSART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EUSART_SPINCP + +// $[EUSART_SL_EUSART_SPINCP] +#define SL_EUSART_SPINCP_PERIPHERAL EUSART1 +#define SL_EUSART_SPINCP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC01 +#define SL_EUSART_SPINCP_TX_PORT gpioPortC +#define SL_EUSART_SPINCP_TX_PIN 1 + +// EUSART1 RX on PC02 +#define SL_EUSART_SPINCP_RX_PORT gpioPortC +#define SL_EUSART_SPINCP_RX_PIN 2 + +// EUSART1 CS on PC00 +#define SL_EUSART_SPINCP_CS_PORT gpioPortC +#define SL_EUSART_SPINCP_CS_PIN 0 + +// EUSART1 SCLK on PC03 +#define SL_EUSART_SPINCP_SCLK_PORT gpioPortC +#define SL_EUSART_SPINCP_SCLK_PIN 3 + +// [EUSART_SL_EUSART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/btl_spi_peripheral_usart_driver_cfg.h b/hardware/board/config/brd4328b_brd4002a/btl_spi_peripheral_usart_driver_cfg.h new file mode 100644 index 0000000000..4310485bc4 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/btl_spi_peripheral_usart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Usart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_USART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_USART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_USART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_USART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_SPINCP + +// $[USART_SL_USART_SPINCP] +#define SL_USART_SPINCP_PERIPHERAL USART0 +#define SL_USART_SPINCP_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_USART_SPINCP_TX_PORT gpioPortC +#define SL_USART_SPINCP_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_USART_SPINCP_RX_PORT gpioPortC +#define SL_USART_SPINCP_RX_PIN 2 + +// USART0 CS on PC00 +#define SL_USART_SPINCP_CS_PORT gpioPortC +#define SL_USART_SPINCP_CS_PIN 0 + +// USART0 CLK on PC03 +#define SL_USART_SPINCP_CLK_PORT gpioPortC +#define SL_USART_SPINCP_CLK_PIN 3 + +// [USART_SL_USART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/btl_uart_driver_cfg.h b/hardware/board/config/brd4328b_brd4002a/btl_uart_driver_cfg.h new file mode 100644 index 0000000000..42676179a9 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/btl_uart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Uart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_UART_DRIVER_CONFIG_H +#define BTL_UART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_UART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_UART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_UART +// $[USART_SL_SERIAL_UART] +#define SL_SERIAL_UART_PERIPHERAL USART0 +#define SL_SERIAL_UART_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_SERIAL_UART_TX_PORT gpioPortA +#define SL_SERIAL_UART_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_SERIAL_UART_RX_PORT gpioPortA +#define SL_SERIAL_UART_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_SERIAL_UART_CTS_PORT gpioPortA +#define SL_SERIAL_UART_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_SERIAL_UART_RTS_PORT gpioPortA +#define SL_SERIAL_UART_RTS_PIN 0 + +// [USART_SL_SERIAL_UART]$ + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT gpioPortB +#define SL_VCOM_ENABLE_PIN 0 + +// [GPIO_SL_VCOM_ENABLE]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_UART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/iot_flash_cfg_exp.h b/hardware/board/config/brd4328b_brd4002a/iot_flash_cfg_exp.h new file mode 100644 index 0000000000..e54999dcf3 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/iot_flash_cfg_exp.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_EXP_H_ +#define _IOT_FLASH_CFG_EXP_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_EXP_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_EXP_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_EXP_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_EXP_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_EXP_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_EXP_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_EXP_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_EXP_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_EXP_SPI +// $[USART_IOT_FLASH_CFG_EXP_SPI] +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define IOT_FLASH_CFG_EXP_SPI_TX_PORT gpioPortC +#define IOT_FLASH_CFG_EXP_SPI_TX_PIN 1 + +// USART0 RX on PC02 +#define IOT_FLASH_CFG_EXP_SPI_RX_PORT gpioPortC +#define IOT_FLASH_CFG_EXP_SPI_RX_PIN 2 + +// USART0 CLK on PC03 +#define IOT_FLASH_CFG_EXP_SPI_CLK_PORT gpioPortC +#define IOT_FLASH_CFG_EXP_SPI_CLK_PIN 3 + +// USART0 CS on PC00 +#define IOT_FLASH_CFG_EXP_SPI_CS_PORT gpioPortC +#define IOT_FLASH_CFG_EXP_SPI_CS_PIN 0 + +// [USART_IOT_FLASH_CFG_EXP_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4328b_brd4002a/iot_flash_cfg_msc.h b/hardware/board/config/brd4328b_brd4002a/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..c2af14bc7d --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/iot_flash_cfg_msc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_MSC_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/board/config/brd4328b_brd4002a/iot_flash_cfg_spiflash.h b/hardware/board/config/brd4328b_brd4002a/iot_flash_cfg_spiflash.h new file mode 100644 index 0000000000..0dd0bb9f60 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/iot_flash_cfg_spiflash.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_SPIFLASH_H_ +#define _IOT_FLASH_CFG_SPIFLASH_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_NUM 0 + +// External Flash Base Address +// Hex value of the base address of the external flash used. +// Default: 0x0 +#define IOT_FLASH_CFG_SPIFLASH_EXTERNAL_FLASH_BASE 0x0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_SPIFLASH_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_SPIFLASH_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_SPIFLASH_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_SPIFLASH_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_SPIFLASH_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_SPIFLASH_SPI +// $[USART_IOT_FLASH_CFG_SPIFLASH_SPI] +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PORT gpioPortC +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PIN 1 + +// USART0 RX on PC02 +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PORT gpioPortC +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PIN 2 + +// USART0 CLK on PC03 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PORT gpioPortC +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PIN 3 + +// USART0 CS on PC04 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PORT gpioPortC +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PIN 4 + +// [USART_IOT_FLASH_CFG_SPIFLASH_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_SPIFLASH_H_ */ diff --git a/hardware/board/config/brd4328b_brd4002a/iot_i2c_cfg_exp.h b/hardware/board/config/brd4328b_brd4002a/iot_i2c_cfg_exp.h new file mode 100644 index 0000000000..b538ec590e --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/iot_i2c_cfg_exp.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_EXP_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_EXP_H_ +#define _IOT_I2C_CFG_EXP_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_EXP_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_EXP_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_EXP_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_EXP_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_EXP_ENABLE +// $[GPIO_IOT_I2C_CFG_EXP_ENABLE] +#define IOT_I2C_CFG_EXP_ENABLE_PORT gpioPortA +#define IOT_I2C_CFG_EXP_ENABLE_PIN 5 + +// [GPIO_IOT_I2C_CFG_EXP_ENABLE]$ + +// IOT_I2C_CFG_EXP +// $[I2C_IOT_I2C_CFG_EXP] +#define IOT_I2C_CFG_EXP_PERIPHERAL I2C1 +#define IOT_I2C_CFG_EXP_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_EXP_SCL_PORT gpioPortC +#define IOT_I2C_CFG_EXP_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_EXP_SDA_PORT gpioPortC +#define IOT_I2C_CFG_EXP_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_EXP]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4328b_brd4002a/iot_i2c_cfg_sensor.h b/hardware/board/config/brd4328b_brd4002a/iot_i2c_cfg_sensor.h new file mode 100644 index 0000000000..0692295a6d --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/iot_i2c_cfg_sensor.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_SENSOR_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_SENSOR_H_ +#define _IOT_I2C_CFG_SENSOR_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_SENSOR_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_SENSOR_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_SENSOR_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_SENSOR_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_SENSOR_ENABLE +// $[GPIO_IOT_I2C_CFG_SENSOR_ENABLE] + +// [GPIO_IOT_I2C_CFG_SENSOR_ENABLE]$ + +// IOT_I2C_CFG_SENSOR +// $[I2C_IOT_I2C_CFG_SENSOR] +#define IOT_I2C_CFG_SENSOR_PERIPHERAL I2C1 +#define IOT_I2C_CFG_SENSOR_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_SENSOR_SCL_PORT gpioPortC +#define IOT_I2C_CFG_SENSOR_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_SENSOR_SDA_PORT gpioPortC +#define IOT_I2C_CFG_SENSOR_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_SENSOR]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_SENSOR_H_ */ diff --git a/hardware/board/config/brd4328b_brd4002a/iot_i2c_cfg_test.h b/hardware/board/config/brd4328b_brd4002a/iot_i2c_cfg_test.h new file mode 100644 index 0000000000..8fc615bc1e --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/iot_i2c_cfg_test.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_TEST_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_TEST_H_ +#define _IOT_I2C_CFG_TEST_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_TEST_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_TEST_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_TEST_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_TEST_ACCEPT_NACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_TEST_ENABLE +// $[GPIO_IOT_I2C_CFG_TEST_ENABLE] +#define IOT_I2C_CFG_TEST_ENABLE_PORT gpioPortA +#define IOT_I2C_CFG_TEST_ENABLE_PIN 5 + +// [GPIO_IOT_I2C_CFG_TEST_ENABLE]$ + +// IOT_I2C_CFG_TEST +// $[I2C_IOT_I2C_CFG_TEST] +#define IOT_I2C_CFG_TEST_PERIPHERAL I2C1 +#define IOT_I2C_CFG_TEST_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define IOT_I2C_CFG_TEST_SCL_PORT gpioPortC +#define IOT_I2C_CFG_TEST_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define IOT_I2C_CFG_TEST_SDA_PORT gpioPortC +#define IOT_I2C_CFG_TEST_SDA_PIN 7 + +// [I2C_IOT_I2C_CFG_TEST]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_TEST_H_ */ diff --git a/hardware/board/config/brd4328b_brd4002a/iot_pwm_cfg_exp.h b/hardware/board/config/brd4328b_brd4002a/iot_pwm_cfg_exp.h new file mode 100644 index 0000000000..07189e64c2 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/iot_pwm_cfg_exp.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_EXP_H_ +#define _IOT_PWM_CFG_EXP_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_EXP_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_EXP +// $[TIMER_IOT_PWM_CFG_EXP] +#define IOT_PWM_CFG_EXP_PERIPHERAL TIMER4 +#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 4 + +// TIMER4 CC0 on PA05 +#define IOT_PWM_CFG_EXP_CC0_PORT gpioPortA +#define IOT_PWM_CFG_EXP_CC0_PIN 5 + + + +// [TIMER_IOT_PWM_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4328b_brd4002a/iot_pwm_cfg_led0.h b/hardware/board/config/brd4328b_brd4002a/iot_pwm_cfg_led0.h new file mode 100644 index 0000000000..037f953d0f --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/iot_pwm_cfg_led0.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED0_H_ +#define _IOT_PWM_CFG_LED0_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED0_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED0 +// $[TIMER_IOT_PWM_CFG_LED0] +#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 +#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 + +// TIMER0 CC0 on PB02 +#define IOT_PWM_CFG_LED0_CC0_PORT gpioPortB +#define IOT_PWM_CFG_LED0_CC0_PIN 2 + + + +// [TIMER_IOT_PWM_CFG_LED0]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd4328b_brd4002a/iot_pwm_cfg_led1.h b/hardware/board/config/brd4328b_brd4002a/iot_pwm_cfg_led1.h new file mode 100644 index 0000000000..f290b8319e --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/iot_pwm_cfg_led1.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED1_H_ +#define _IOT_PWM_CFG_LED1_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED1_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED1 +// $[TIMER_IOT_PWM_CFG_LED1] +#define IOT_PWM_CFG_LED1_PERIPHERAL TIMER1 +#define IOT_PWM_CFG_LED1_PERIPHERAL_NO 1 + +// TIMER1 CC0 on PD03 +#define IOT_PWM_CFG_LED1_CC0_PORT gpioPortD +#define IOT_PWM_CFG_LED1_CC0_PIN 3 + + + +// [TIMER_IOT_PWM_CFG_LED1]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED1_H_ */ diff --git a/hardware/board/config/brd4328b_brd4002a/iot_spi_cfg_exp.h b/hardware/board/config/brd4328b_brd4002a/iot_spi_cfg_exp.h new file mode 100644 index 0000000000..d0dcc63132 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/iot_spi_cfg_exp.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_EXP_H_ +#define _IOT_SPI_CFG_EXP_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_EXP_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_EXP_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_EXP_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_EXP_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_EXP_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_EXP_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_EXP_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_EXP_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_EXP +// $[USART_IOT_SPI_CFG_EXP] +#define IOT_SPI_CFG_EXP_PERIPHERAL USART0 +#define IOT_SPI_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define IOT_SPI_CFG_EXP_TX_PORT gpioPortC +#define IOT_SPI_CFG_EXP_TX_PIN 1 + +// USART0 RX on PC02 +#define IOT_SPI_CFG_EXP_RX_PORT gpioPortC +#define IOT_SPI_CFG_EXP_RX_PIN 2 + +// USART0 CLK on PC03 +#define IOT_SPI_CFG_EXP_CLK_PORT gpioPortC +#define IOT_SPI_CFG_EXP_CLK_PIN 3 + +// USART0 CS on PC00 +#define IOT_SPI_CFG_EXP_CS_PORT gpioPortC +#define IOT_SPI_CFG_EXP_CS_PIN 0 + +// [USART_IOT_SPI_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4328b_brd4002a/iot_spi_cfg_loopback.h b/hardware/board/config/brd4328b_brd4002a/iot_spi_cfg_loopback.h new file mode 100644 index 0000000000..c5fe826e25 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/iot_spi_cfg_loopback.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_LOOPBACK_H_ +#define _IOT_SPI_CFG_LOOPBACK_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_LOOPBACK +// $[USART_IOT_SPI_CFG_LOOPBACK] +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define IOT_SPI_CFG_LOOPBACK_TX_PORT gpioPortC +#define IOT_SPI_CFG_LOOPBACK_TX_PIN 1 + +// USART0 RX on PC02 +#define IOT_SPI_CFG_LOOPBACK_RX_PORT gpioPortC +#define IOT_SPI_CFG_LOOPBACK_RX_PIN 2 + +// USART0 CLK on PC03 +#define IOT_SPI_CFG_LOOPBACK_CLK_PORT gpioPortC +#define IOT_SPI_CFG_LOOPBACK_CLK_PIN 3 + +// USART0 CS on PC00 +#define IOT_SPI_CFG_LOOPBACK_CS_PORT gpioPortC +#define IOT_SPI_CFG_LOOPBACK_CS_PIN 0 + +// [USART_IOT_SPI_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4328b_brd4002a/iot_uart_cfg_exp.h b/hardware/board/config/brd4328b_brd4002a/iot_uart_cfg_exp.h new file mode 100644 index 0000000000..b9a823f0fa --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/iot_uart_cfg_exp.h @@ -0,0 +1,126 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_EXP_H_ +#define _IOT_UART_CFG_EXP_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_EXP_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_EXP +// $[USART_IOT_UART_CFG_EXP] +#define IOT_UART_CFG_EXP_PERIPHERAL USART0 +#define IOT_UART_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define IOT_UART_CFG_EXP_TX_PORT gpioPortA +#define IOT_UART_CFG_EXP_TX_PIN 8 + +// USART0 RX on PA09 +#define IOT_UART_CFG_EXP_RX_PORT gpioPortA +#define IOT_UART_CFG_EXP_RX_PIN 9 + + + + + +// [USART_IOT_UART_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4328b_brd4002a/iot_uart_cfg_loopback.h b/hardware/board/config/brd4328b_brd4002a/iot_uart_cfg_loopback.h new file mode 100644 index 0000000000..b9d7759c50 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/iot_uart_cfg_loopback.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_LOOPBACK_H_ +#define _IOT_UART_CFG_LOOPBACK_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_LOOPBACK +// $[USART_IOT_UART_CFG_LOOPBACK] +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define IOT_UART_CFG_LOOPBACK_TX_PORT gpioPortA +#define IOT_UART_CFG_LOOPBACK_TX_PIN 8 + +// USART0 RX on PA09 +#define IOT_UART_CFG_LOOPBACK_RX_PORT gpioPortA +#define IOT_UART_CFG_LOOPBACK_RX_PIN 9 + + + +// USART0 RTS on PA00 +#define IOT_UART_CFG_LOOPBACK_RTS_PORT gpioPortA +#define IOT_UART_CFG_LOOPBACK_RTS_PIN 0 + +// USART0 CTS on PA10 +#define IOT_UART_CFG_LOOPBACK_CTS_PORT gpioPortA +#define IOT_UART_CFG_LOOPBACK_CTS_PIN 10 + +// [USART_IOT_UART_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4328b_brd4002a/iot_uart_cfg_vcom.h b/hardware/board/config/brd4328b_brd4002a/iot_uart_cfg_vcom.h new file mode 100644 index 0000000000..ea72497782 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/iot_uart_cfg_vcom.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_VCOM_H_ +#define _IOT_UART_CFG_VCOM_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_VCOM_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_VCOM_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_VCOM +// $[USART_IOT_UART_CFG_VCOM] +#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 +#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define IOT_UART_CFG_VCOM_TX_PORT gpioPortA +#define IOT_UART_CFG_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define IOT_UART_CFG_VCOM_RX_PORT gpioPortA +#define IOT_UART_CFG_VCOM_RX_PIN 9 + + + +// USART0 RTS on PA00 +#define IOT_UART_CFG_VCOM_RTS_PORT gpioPortA +#define IOT_UART_CFG_VCOM_RTS_PIN 0 + +// USART0 CTS on PA10 +#define IOT_UART_CFG_VCOM_CTS_PORT gpioPortA +#define IOT_UART_CFG_VCOM_CTS_PIN 10 + +// [USART_IOT_UART_CFG_VCOM]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd4328b_brd4002a/legacy_ncp_spi_config.h b/hardware/board/config/brd4328b_brd4002a/legacy_ncp_spi_config.h new file mode 100644 index 0000000000..d11f9eeb32 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/legacy_ncp_spi_config.h @@ -0,0 +1,60 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef LEGACY_NCP_SPI_CONFIG_H +#define LEGACY_NCP_SPI_CONFIG_H + +// <<< sl:start pin_tool >>> +// LEGACY_NCP_SPI +// $[USART_LEGACY_NCP_SPI] +#define LEGACY_NCP_SPI_PERIPHERAL USART0 +#define LEGACY_NCP_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define LEGACY_NCP_SPI_TX_PORT gpioPortC +#define LEGACY_NCP_SPI_TX_PIN 1 + +// USART0 RX on PC02 +#define LEGACY_NCP_SPI_RX_PORT gpioPortC +#define LEGACY_NCP_SPI_RX_PIN 2 + +// USART0 CLK on PC03 +#define LEGACY_NCP_SPI_CLK_PORT gpioPortC +#define LEGACY_NCP_SPI_CLK_PIN 3 + +// USART0 CS on PC00 +#define LEGACY_NCP_SPI_CS_PORT gpioPortC +#define LEGACY_NCP_SPI_CS_PIN 0 + +// [USART_LEGACY_NCP_SPI]$ + +// LEGACY_NCP_SPI_HOST_INT +// $[GPIO_LEGACY_NCP_SPI_HOST_INT] +#define LEGACY_NCP_SPI_HOST_INT_PORT gpioPortA +#define LEGACY_NCP_SPI_HOST_INT_PIN 5 + +// [GPIO_LEGACY_NCP_SPI_HOST_INT]$ + +// LEGACY_NCP_SPI_WAKE_INT +// $[GPIO_LEGACY_NCP_SPI_WAKE_INT] +#define LEGACY_NCP_SPI_WAKE_INT_PORT gpioPortD +#define LEGACY_NCP_SPI_WAKE_INT_PIN 2 + +// [GPIO_LEGACY_NCP_SPI_WAKE_INT]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_board_control_config.h b/hardware/board/config/brd4328b_brd4002a/sl_board_control_config.h new file mode 100644 index 0000000000..049d22e03a --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_board_control_config.h @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortB +#define SL_BOARD_ENABLE_VCOM_PIN 0 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortC +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 0 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_secondary_spi_eusart_exp_config.h b/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_secondary_spi_eusart_exp_config.h new file mode 100644 index 0000000000..e7b20e6571 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_secondary_spi_eusart_exp_config.h @@ -0,0 +1,120 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CPC_DRV_SPI_EUSART_EXP_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_EUSART_EXP_SECONDARY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// CPC-Secondary SPI Driver Configuration + +// Queues size configuration + +// Number of frame that can be queued in the driver receive queue +// A greater number decreases the chances of retransmission due to dropped frames at the cost of memory footprint +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// A greater number increases the transmission responsiveness at the cost of memory footprint +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 +// + +// LDMA SYNCTRIG bit configuration +// The LDMA SYNCTRIG bit number for the TX availability [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// Default : 7 +// 7 +#define SL_CPC_DRV_SPI_EXP_TX_AVAILABILITY_SYNCTRIG_CH 6 + +// The LDMA SYNCTRIG bit number for the CS PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 5 +// 5 +#define SL_CPC_DRV_SPI_EXP_CS_SYNCTRIG_PRS_CH 5 + +// The LDMA SYNCTRIG bit number for the TXC PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 6 +// 6 +#define SL_CPC_DRV_SPI_EXP_TXC_SYNCTRIG_PRS_CH 4 +// + +// Chip Select PRS Routing +// The Chip Select input to EXTernal Interrupt number <0-7> +// The CS input needs to be routed to a PRS channel in order to manipulate its LDMA SYNCTRIG bit. +// Modify this value to avoid collisions if any specific EXTI number needs to be used elsewhere in the project. +// Note that only EXTI0..7 can be used as input for a PRS channel, and only pins Px0..7 can be routed to those. +// Default : 0 (pin0..4 of any port) +// 0 +#define SL_CPC_DRV_SPI_EXP_CS_EXTI_NUMBER 0 +// + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_EXP_RX_IRQ +// $[GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ] +#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PORT gpioPortA +#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PIN 5 + +// [GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ]$ + +// SL_CPC_DRV_SPI_EXP +// $[EUSART_SL_CPC_DRV_SPI_EXP] +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL EUSART1 +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC01 +#define SL_CPC_DRV_SPI_EXP_TX_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_TX_PIN 1 + +// EUSART1 RX on PC02 +#define SL_CPC_DRV_SPI_EXP_RX_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_RX_PIN 2 + +// EUSART1 SCLK on PC03 +#define SL_CPC_DRV_SPI_EXP_SCLK_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_SCLK_PIN 3 + +// EUSART1 CS on PC00 +#define SL_CPC_DRV_SPI_EXP_CS_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_CS_PIN 0 + +// [EUSART_SL_CPC_DRV_SPI_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h b/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h new file mode 100644 index 0000000000..c69f5a5ed0 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h @@ -0,0 +1,110 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// CPC-Secondary SPI Driver Configuration + +// Queues size configuration + +// Number of frame that can be queued in the driver receive queue +// A greater number decreases the chances of retransmission due to dropped frames at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// A greater number increases the transmission responsiveness at the cost of memory footprint. +// Default : 10 +// 10 +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 +// + +// LDMA SYNCTRIG bit configuration +// The LDMA SYNCTRIG bit number for the TX availability [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// Default : 7 +// 7 +#define SL_CPC_DRV_SPI_EXP_TX_AVAILABILITY_SYNCTRIG_CH 6 + +// The LDMA SYNCTRIG bit number for the CS PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 5 +// 5 +#define SL_CPC_DRV_SPI_EXP_CS_SYNCTRIG_PRS_CH 5 + +// The LDMA SYNCTRIG bit number for the TXC PRS channel [bit] <0-7> +// Specify which SYNCTRIG bit is used. Modify this value to avoid collisions if specific LDMA SYNCTRIG bits need to be used elsewhere in the project. +// This bit number is tied to the equivalent PRS channel number. Keep that in mind if using PRS channels elsewhere in the project. +// Default : 6 +// 6 +#define SL_CPC_DRV_SPI_EXP_TXC_SYNCTRIG_PRS_CH 4 + +// +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_EXP_RX_IRQ +// $[GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ] +#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PORT gpioPortA +#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PIN 5 + +// [GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ]$ + +// SL_CPC_DRV_SPI_EXP +// $[USART_SL_CPC_DRV_SPI_EXP] +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_CPC_DRV_SPI_EXP_TX_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_CPC_DRV_SPI_EXP_RX_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_RX_PIN 2 + +// USART0 CLK on PC03 +#define SL_CPC_DRV_SPI_EXP_CLK_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_CLK_PIN 3 + +// USART0 CS on PC00 +#define SL_CPC_DRV_SPI_EXP_CS_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_CS_PIN 0 + +// [USART_SL_CPC_DRV_SPI_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h b/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h new file mode 100644 index 0000000000..d99b864969 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_EXP_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlNone +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[EUSART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUSART1 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC01 +#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_TX_PIN 1 + +// EUSART1 RX on PC02 +#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_RX_PIN 2 + +// EUSART1 CTS on PC03 +#define SL_CPC_DRV_UART_EXP_CTS_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_CTS_PIN 3 + +// EUSART1 RTS on PC00 +#define SL_CPC_DRV_UART_EXP_RTS_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_RTS_PIN 0 + +// [EUSART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h b/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h new file mode 100644 index 0000000000..6901c2ac47 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_VCOM_CONFIG_H + +// CPC - EUSART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlNone +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[EUSART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUSART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 + +// [EUSART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_uart_usart_exp_config.h b/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_uart_usart_exp_config.h new file mode 100644 index 0000000000..467312777c --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_uart_usart_exp_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_EXP_CONFIG_H +#define SL_CPC_DRV_UART_USART_EXP_CONFIG_H + +// CPC - UART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[USART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_RX_PIN 2 + +// USART0 CTS on PC03 +#define SL_CPC_DRV_UART_EXP_CTS_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_CTS_PIN 3 + +// USART0 RTS on PC00 +#define SL_CPC_DRV_UART_EXP_RTS_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_RTS_PIN 0 + +// [USART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_CONFIG_H */ diff --git a/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h b/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h new file mode 100644 index 0000000000..5e13497282 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief CPC UART driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_VCOM_CONFIG_H +#define SL_CPC_DRV_UART_USART_VCOM_CONFIG_H + +// CPC - UART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[USART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 + +// [USART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_CONFIG_H */ diff --git a/hardware/board/config/brd4328b_brd4002a/sl_cpc_gpio_expander_gpio_btn0_config.h b/hardware/board/config/brd4328b_brd4002a/sl_cpc_gpio_expander_gpio_btn0_config.h new file mode 100644 index 0000000000..331c3bc888 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_cpc_gpio_expander_gpio_btn0_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_NAME "BTN0" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN0 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PORT gpioPortB +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN0_PIN 1 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN0_CONFIG_H */ diff --git a/hardware/board/config/brd4328b_brd4002a/sl_cpc_gpio_expander_gpio_btn1_config.h b/hardware/board/config/brd4328b_brd4002a/sl_cpc_gpio_expander_gpio_btn1_config.h new file mode 100644 index 0000000000..74ef962318 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_cpc_gpio_expander_gpio_btn1_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief CPC GPIO Expander instance configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H + +// GPIO Pin Name +// Specify the name of the GPIO pin instance which is reported to the Host/Primary device +// Default: "UNDEFINED" +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_NAME "BTN1" + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_GPIO_EXPANDER_GPIO_BTN1 +// $[GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1] +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PORT gpioPortB +#define SL_CPC_GPIO_EXPANDER_GPIO_BTN1_PIN 3 + +// [GPIO_SL_CPC_GPIO_EXPANDER_GPIO_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_GPIO_EXPANDER_GPIO_BTN1_CONFIG_H */ diff --git a/hardware/board/config/brd4328b_brd4002a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4328b_brd4002a/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..78b14ee253 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_device_init_hfxo_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 39000000 +#define SL_DEVICE_INIT_HFXO_FREQ 39000000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 140 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_i2cspm_sensor_config.h b/hardware/board/config/brd4328b_brd4002a/sl_i2cspm_sensor_config.h new file mode 100644 index 0000000000..b5fedf050d --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_i2cspm_sensor_config.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief I2CSPM Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_I2CSPM_SENSOR_CONFIG_H +#define SL_I2CSPM_SENSOR_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu + +// I2CSPM settings + +// Reference clock frequency +// Frequency in Hz of the reference clock. +// Select 0 to use the frequency of the currently selected clock. +// Default: 0 +#define SL_I2CSPM_SENSOR_REFERENCE_CLOCK 0 + +// Speed mode +// <0=> Standard mode (100kbit/s) +// <1=> Fast mode (400kbit/s) +// <2=> Fast mode plus (1Mbit/s) +// Default: 0 +#define SL_I2CSPM_SENSOR_SPEED_MODE 0 +// end I2CSPM config + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_I2CSPM_SENSOR +// $[I2C_SL_I2CSPM_SENSOR] +#define SL_I2CSPM_SENSOR_PERIPHERAL I2C1 +#define SL_I2CSPM_SENSOR_PERIPHERAL_NO 1 + +// I2C1 SCL on PC05 +#define SL_I2CSPM_SENSOR_SCL_PORT gpioPortC +#define SL_I2CSPM_SENSOR_SCL_PIN 5 + +// I2C1 SDA on PC07 +#define SL_I2CSPM_SENSOR_SDA_PORT gpioPortC +#define SL_I2CSPM_SENSOR_SDA_PIN 7 + +// [I2C_SL_I2CSPM_SENSOR]$ +// <<< sl:end pin_tool >>> + +#endif // SL_I2CSPM_SENSOR_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4328b_brd4002a/sl_iostream_eusart_exp_config.h new file mode 100644 index 0000000000..cbe96bbdcb --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_iostream_eusart_exp_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_IOSTREAM_EUSART_EXP_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_IOSTREAM_EUSART_EXP_STOP_BITS eusartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: eusartHwFlowControlNone +#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP +// $[EUSART_SL_IOSTREAM_EUSART_EXP] +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUSART0 +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_IOSTREAM_EUSART_EXP_TX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_EXP_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_IOSTREAM_EUSART_EXP_RX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_EXP_RX_PIN 9 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4328b_brd4002a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4328b_brd4002a/sl_iostream_eusart_vcom_config.h new file mode 100644 index 0000000000..db8ecd8a79 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_iostream_eusart_vcom_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H +#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_IOSTREAM_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: eusartHwFlowControlNone +#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_VCOM +// $[EUSART_SL_IOSTREAM_EUSART_VCOM] +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_IOSTREAM_EUSART_VCOM_TX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_IOSTREAM_EUSART_VCOM_RX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4328b_brd4002a/sl_iostream_usart_exp_config.h b/hardware/board/config/brd4328b_brd4002a/sl_iostream_usart_exp_config.h new file mode 100644 index 0000000000..e5f8850848 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_iostream_usart_exp_config.h @@ -0,0 +1,109 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H +#define SL_IOSTREAM_USART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP +// $[USART_SL_IOSTREAM_USART_EXP] +#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_IOSTREAM_USART_EXP_TX_PORT gpioPortA +#define SL_IOSTREAM_USART_EXP_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_IOSTREAM_USART_EXP_RX_PORT gpioPortA +#define SL_IOSTREAM_USART_EXP_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_IOSTREAM_USART_EXP_CTS_PORT gpioPortA +#define SL_IOSTREAM_USART_EXP_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_IOSTREAM_USART_EXP_RTS_PORT gpioPortA +#define SL_IOSTREAM_USART_EXP_RTS_PIN 0 + +// [USART_SL_IOSTREAM_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4328b_brd4002a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd4328b_brd4002a/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..85da71b67b --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_iostream_usart_vcom_config.h @@ -0,0 +1,109 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortA +#define SL_IOSTREAM_USART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortA +#define SL_IOSTREAM_USART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortA +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortA +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 0 + +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4328b_brd4002a/sl_memlcd_eusart_config.h b/hardware/board/config/brd4328b_brd4002a/sl_memlcd_eusart_config.h new file mode 100644 index 0000000000..4b21c6f11e --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_memlcd_eusart_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief SPI abstraction used by memory lcd display + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[EUSART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL EUSART1 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 1 + +// EUSART1 TX on PC01 +#define SL_MEMLCD_SPI_TX_PORT gpioPortC +#define SL_MEMLCD_SPI_TX_PIN 1 + +// EUSART1 SCLK on PC03 +#define SL_MEMLCD_SPI_SCLK_PORT gpioPortC +#define SL_MEMLCD_SPI_SCLK_PIN 3 + +// [EUSART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT gpioPortC +#define SL_MEMLCD_SPI_CS_PIN 8 + +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT gpioPortC +#define SL_MEMLCD_EXTCOMIN_PIN 6 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4328b_brd4002a/sl_memlcd_usart_config.h b/hardware/board/config/brd4328b_brd4002a/sl_memlcd_usart_config.h new file mode 100644 index 0000000000..3490e3829e --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_memlcd_usart_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief SPI abstraction used by memory lcd display + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[USART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL USART0 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_MEMLCD_SPI_TX_PORT gpioPortC +#define SL_MEMLCD_SPI_TX_PIN 1 + +// USART0 CLK on PC03 +#define SL_MEMLCD_SPI_CLK_PORT gpioPortC +#define SL_MEMLCD_SPI_CLK_PIN 3 + +// [USART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT gpioPortC +#define SL_MEMLCD_SPI_CS_PIN 8 + +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT gpioPortC +#define SL_MEMLCD_EXTCOMIN_PIN 6 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4328b_brd4002a/sl_mx25_flash_shutdown_eusart_config.h b/hardware/board/config/brd4328b_brd4002a/sl_mx25_flash_shutdown_eusart_config.h new file mode 100644 index 0000000000..63d60d5510 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_mx25_flash_shutdown_eusart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {eusart signal=TX,RX,SCLK} SL_MX25_FLASH_SHUTDOWN +// [EUSART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL EUSART1 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 1 + +// EUSART1 TX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 1 + +// EUSART1 RX on PC02 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 2 + +// EUSART1 SCLK on PC03 +#define SL_MX25_FLASH_SHUTDOWN_SCLK_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_SCLK_PIN 3 + +// [EUSART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_mx25_flash_shutdown_usart_config.h b/hardware/board/config/brd4328b_brd4002a/sl_mx25_flash_shutdown_usart_config.h new file mode 100644 index 0000000000..3b217bb736 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_mx25_flash_shutdown_usart_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 2 + +// USART0 CLK on PC03 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 3 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_ncp_spidrv_usart_config.h b/hardware/board/config/brd4328b_brd4002a/sl_ncp_spidrv_usart_config.h new file mode 100644 index 0000000000..3bd42bb9d8 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_ncp_spidrv_usart_config.h @@ -0,0 +1,94 @@ +/***************************************************************************//** + * @file + * @brief Open thread NCP spidrv usart configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_NCP_SPIDRV_USART_CONFIG_H +#define SL_NCP_SPIDRV_USART_CONFIG_H +#include "spidrv.h" + +// NCP spidrv usart Configuration + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_NCP_SPIDRV_USART_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_NCP_SPIDRV_USART_CLOCK_MODE spidrvClockMode0 + +// Chip Select Interrupt Number on Falling Edge +// Default: 10 +#define SL_NCP_SPIDRV_USART_CS_FALLING_EDGE_INT_NO 0 + +// Chip Select Interrupt Number on Rising Edge +// Default: 9 +#define SL_NCP_SPIDRV_USART_CS_RISING_EDGE_INT_NO 1 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_NCP_SPIDRV_USART_HOST_INT +// $[GPIO_SL_NCP_SPIDRV_USART_HOST_INT] +#define SL_NCP_SPIDRV_USART_HOST_INT_PORT gpioPortA +#define SL_NCP_SPIDRV_USART_HOST_INT_PIN 5 + +// [GPIO_SL_NCP_SPIDRV_USART_HOST_INT]$ + +// SL_NCP_SPIDRV_USART +// $[USART_SL_NCP_SPIDRV_USART] +#define SL_NCP_SPIDRV_USART_PERIPHERAL USART0 +#define SL_NCP_SPIDRV_USART_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_NCP_SPIDRV_USART_TX_PORT gpioPortC +#define SL_NCP_SPIDRV_USART_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_NCP_SPIDRV_USART_RX_PORT gpioPortC +#define SL_NCP_SPIDRV_USART_RX_PIN 2 + +// USART0 CLK on PC03 +#define SL_NCP_SPIDRV_USART_CLK_PORT gpioPortC +#define SL_NCP_SPIDRV_USART_CLK_PIN 3 + +// USART0 CS on PC00 +#define SL_NCP_SPIDRV_USART_CS_PORT gpioPortC +#define SL_NCP_SPIDRV_USART_CS_PIN 0 + +// [USART_SL_NCP_SPIDRV_USART]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_NCP_SPIDRV_USART_CONFIG_H */ diff --git a/hardware/board/config/brd4328b_brd4002a/sl_pwm_init_led0_config.h b/hardware/board/config/brd4328b_brd4002a/sl_pwm_init_led0_config.h new file mode 100644 index 0000000000..a86f33fec9 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_pwm_init_led0_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef PWM_INIT_LED0_CONFIG_H +#define PWM_INIT_LED0_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED0_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED0_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED0 +// $[TIMER_SL_PWM_LED0] +#define SL_PWM_LED0_PERIPHERAL TIMER0 +#define SL_PWM_LED0_PERIPHERAL_NO 0 + +#define SL_PWM_LED0_OUTPUT_CHANNEL 0 +// TIMER0 CC0 on PB02 +#define SL_PWM_LED0_OUTPUT_PORT gpioPortB +#define SL_PWM_LED0_OUTPUT_PIN 2 + +// [TIMER_SL_PWM_LED0]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_pwm_init_led1_config.h b/hardware/board/config/brd4328b_brd4002a/sl_pwm_init_led1_config.h new file mode 100644 index 0000000000..199e48f279 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_pwm_init_led1_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef PWM_INIT_LED1_CONFIG_H +#define PWM_INIT_LED1_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED1_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED1_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED1 +// $[TIMER_SL_PWM_LED1] +#define SL_PWM_LED1_PERIPHERAL TIMER1 +#define SL_PWM_LED1_PERIPHERAL_NO 1 + +#define SL_PWM_LED1_OUTPUT_CHANNEL 0 +// TIMER1 CC0 on PD03 +#define SL_PWM_LED1_OUTPUT_PORT gpioPortD +#define SL_PWM_LED1_OUTPUT_PIN 3 + +// [TIMER_SL_PWM_LED1]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // PWM_INIT_LED1_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_rail_util_pti_config.h b/hardware/board/config/brd4328b_brd4002a/sl_rail_util_pti_config.h new file mode 100644 index 0000000000..5165fc4204 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_rail_util_pti_config.h @@ -0,0 +1,73 @@ +/***************************************************************************//** + * @file + * @brief Packet Trace Information configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PTI_CONFIG_H +#define SL_RAIL_UTIL_PTI_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PTI Configuration + +// PTI mode +// UART +// UART onewire +// SPI +// Disabled +// Default: RAIL_PTI_MODE_UART +#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART + +// PTI Baud Rate (Hertz) +// <147800-20000000:1> +// Default: 1600000 +#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_RAIL_UTIL_PTI +// $[PTI_SL_RAIL_UTIL_PTI] +#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI + +// PTI DOUT on PD04 +#define SL_RAIL_UTIL_PTI_DOUT_PORT gpioPortD +#define SL_RAIL_UTIL_PTI_DOUT_PIN 4 + +// PTI DFRAME on PD05 +#define SL_RAIL_UTIL_PTI_DFRAME_PORT gpioPortD +#define SL_RAIL_UTIL_PTI_DFRAME_PIN 5 + + +// [PTI_SL_RAIL_UTIL_PTI]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_simple_button_btn0_config.h b/hardware/board/config/brd4328b_brd4002a/sl_simple_button_btn0_config.h new file mode 100644 index 0000000000..06f7fd29f5 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_simple_button_btn0_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H + +#include "em_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN0 +// $[GPIO_SL_SIMPLE_BUTTON_BTN0] +#define SL_SIMPLE_BUTTON_BTN0_PORT gpioPortB +#define SL_SIMPLE_BUTTON_BTN0_PIN 1 + +// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_simple_button_btn1_config.h b/hardware/board/config/brd4328b_brd4002a/sl_simple_button_btn1_config.h new file mode 100644 index 0000000000..ffd08203b6 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_simple_button_btn1_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN1_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN1_CONFIG_H + +#include "em_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN1_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN1 +// $[GPIO_SL_SIMPLE_BUTTON_BTN1] +#define SL_SIMPLE_BUTTON_BTN1_PORT gpioPortB +#define SL_SIMPLE_BUTTON_BTN1_PIN 3 + +// [GPIO_SL_SIMPLE_BUTTON_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN1_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_simple_led_led0_config.h b/hardware/board/config/brd4328b_brd4002a/sl_simple_led_led0_config.h new file mode 100644 index 0000000000..2e6c868888 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_simple_led_led0_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED0_CONFIG_H +#define SL_SIMPLE_LED_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED0_PORT gpioPortB +#define SL_SIMPLE_LED_LED0_PIN 2 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_simple_led_led1_config.h b/hardware/board/config/brd4328b_brd4002a/sl_simple_led_led1_config.h new file mode 100644 index 0000000000..baadcd50fd --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_simple_led_led1_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED1_CONFIG_H +#define SL_SIMPLE_LED_LED1_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED1 +// $[GPIO_SL_SIMPLE_LED_LED1] +#define SL_SIMPLE_LED_LED1_PORT gpioPortD +#define SL_SIMPLE_LED_LED1_PIN 3 + +// [GPIO_SL_SIMPLE_LED_LED1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_simple_led_led2_config.h b/hardware/board/config/brd4328b_brd4002a/sl_simple_led_led2_config.h new file mode 100644 index 0000000000..b20941f4a2 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_simple_led_led2_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED2_CONFIG_H +#define SL_SIMPLE_LED_LED2_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED2_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED2 +// $[GPIO_SL_SIMPLE_LED_LED2] +#define SL_SIMPLE_LED_LED2_PORT gpioPortB +#define SL_SIMPLE_LED_LED2_PIN 4 + +// [GPIO_SL_SIMPLE_LED_LED2]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED2_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_simple_led_led3_config.h b/hardware/board/config/brd4328b_brd4002a/sl_simple_led_led3_config.h new file mode 100644 index 0000000000..2ad6e07cea --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_simple_led_led3_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED3_CONFIG_H +#define SL_SIMPLE_LED_LED3_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED3_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED3 +// $[GPIO_SL_SIMPLE_LED_LED3] +#define SL_SIMPLE_LED_LED3_PORT gpioPortB +#define SL_SIMPLE_LED_LED3_PIN 5 + +// [GPIO_SL_SIMPLE_LED_LED3]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED3_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_simple_led_led4_config.h b/hardware/board/config/brd4328b_brd4002a/sl_simple_led_led4_config.h new file mode 100644 index 0000000000..a89bdb41d8 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_simple_led_led4_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED4_CONFIG_H +#define SL_SIMPLE_LED_LED4_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED4_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED4 +// $[GPIO_SL_SIMPLE_LED_LED4] +#define SL_SIMPLE_LED_LED4_PORT gpioPortB +#define SL_SIMPLE_LED_LED4_PIN 6 + +// [GPIO_SL_SIMPLE_LED_LED4]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED4_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4328b_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..7a76addbf5 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,97 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PB04 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 4 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PB05 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 5 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PB06 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 6 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_spidrv_eusart_exp_config.h b/hardware/board/config/brd4328b_brd4002a/sl_spidrv_eusart_exp_config.h new file mode 100644 index 0000000000..afe8ad9d26 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_spidrv_eusart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EUSART_EXP_CONFIG_H +#define SL_SPIDRV_EUSART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EUSART_EXP_BITRATE 1000000 + +// SPI frame length <7-16> +// Default: 8 +#define SL_SPIDRV_EUSART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EUSART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EUSART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EUSART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EUSART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EUSART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EUSART_EXP +// $[EUSART_SL_SPIDRV_EUSART_EXP] +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC01 +#define SL_SPIDRV_EUSART_EXP_TX_PORT gpioPortC +#define SL_SPIDRV_EUSART_EXP_TX_PIN 1 + +// EUSART1 RX on PC02 +#define SL_SPIDRV_EUSART_EXP_RX_PORT gpioPortC +#define SL_SPIDRV_EUSART_EXP_RX_PIN 2 + +// EUSART1 SCLK on PC03 +#define SL_SPIDRV_EUSART_EXP_SCLK_PORT gpioPortC +#define SL_SPIDRV_EUSART_EXP_SCLK_PIN 3 + +// EUSART1 CS on PC00 +#define SL_SPIDRV_EUSART_EXP_CS_PORT gpioPortC +#define SL_SPIDRV_EUSART_EXP_CS_PIN 0 + +// [EUSART_SL_SPIDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EUSART_EXP_CONFIG_HEUSART_ diff --git a/hardware/board/config/brd4328b_brd4002a/sl_spidrv_exp_config.h b/hardware/board/config/brd4328b_brd4002a/sl_spidrv_exp_config.h new file mode 100644 index 0000000000..eb6cae804a --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_spidrv_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EXP_CONFIG_H +#define SL_SPIDRV_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EXP +// $[USART_SL_SPIDRV_EXP] +#define SL_SPIDRV_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_SPIDRV_EXP_TX_PORT gpioPortC +#define SL_SPIDRV_EXP_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_SPIDRV_EXP_RX_PORT gpioPortC +#define SL_SPIDRV_EXP_RX_PIN 2 + +// USART0 CLK on PC03 +#define SL_SPIDRV_EXP_CLK_PORT gpioPortC +#define SL_SPIDRV_EXP_CLK_PIN 3 + +// USART0 CS on PC00 +#define SL_SPIDRV_EXP_CS_PORT gpioPortC +#define SL_SPIDRV_EXP_CS_PIN 0 + +// [USART_SL_SPIDRV_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_spidrv_usart_exp_config.h b/hardware/board/config/brd4328b_brd4002a/sl_spidrv_usart_exp_config.h new file mode 100644 index 0000000000..213750de5d --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_spidrv_usart_exp_config.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_USART_EXP_CONFIG_H +#define SL_SPIDRV_USART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_USART_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_USART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_USART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_USART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_USART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_USART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_USART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_USART_EXP +// $[USART_SL_SPIDRV_USART_EXP] +#define SL_SPIDRV_USART_EXP_PERIPHERAL USART0 +#define SL_SPIDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_SPIDRV_USART_EXP_TX_PORT gpioPortC +#define SL_SPIDRV_USART_EXP_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_SPIDRV_USART_EXP_RX_PORT gpioPortC +#define SL_SPIDRV_USART_EXP_RX_PIN 2 + +// USART0 CLK on PC03 +#define SL_SPIDRV_USART_EXP_CLK_PORT gpioPortC +#define SL_SPIDRV_USART_EXP_CLK_PIN 3 + +// USART0 CS on PC00 +#define SL_SPIDRV_USART_EXP_CS_PORT gpioPortC +#define SL_SPIDRV_USART_EXP_CS_PIN 0 + +// [USART_SL_SPIDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_eusart_exp_config.h new file mode 100644 index 0000000000..3554ed257e --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP +// $[EUSART_SL_UARTDRV_EUSART_EXP] +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUSART0 +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_UARTDRV_EUSART_EXP_TX_PORT gpioPortA +#define SL_UARTDRV_EUSART_EXP_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_UARTDRV_EUSART_EXP_RX_PORT gpioPortA +#define SL_UARTDRV_EUSART_EXP_RX_PIN 9 + + + +// [EUSART_SL_UARTDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_eusart_vcom_config.h new file mode 100644 index 0000000000..c4dc8e9cf0 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_eusart_vcom_config.h @@ -0,0 +1,119 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H +#define SL_UARTDRV_EUSART_VCOM_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_VCOM_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_VCOM +// $[EUSART_SL_UARTDRV_EUSART_VCOM] +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_UARTDRV_EUSART_VCOM_TX_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_UARTDRV_EUSART_VCOM_RX_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_UARTDRV_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_usart_exp_config.h new file mode 100644 index 0000000000..db65aeef71 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_usart_exp_config.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_CONFIG_H +#define SL_UARTDRV_USART_EXP_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP +// $[USART_SL_UARTDRV_USART_EXP] +#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 +#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_UARTDRV_USART_EXP_TX_PORT gpioPortA +#define SL_UARTDRV_USART_EXP_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_UARTDRV_USART_EXP_RX_PORT gpioPortA +#define SL_UARTDRV_USART_EXP_RX_PIN 9 + + + +// [USART_SL_UARTDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..b27591e686 --- /dev/null +++ b/hardware/board/config/brd4328b_brd4002a/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA08 +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_TX_PIN 8 + +// USART0 RX on PA09 +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RX_PIN 9 + +// USART0 CTS on PA10 +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 10 + +// USART0 RTS on PA00 +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 + +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/component/brd4328b_config.slcc b/hardware/board/config/component/brd4328b_config.slcc new file mode 100644 index 0000000000..1ddb1996fe --- /dev/null +++ b/hardware/board/config/component/brd4328b_config.slcc @@ -0,0 +1,863 @@ +!!omap +- id: brd4328b_config +- label: brd4328b config +- description: Configuration files for BRD4328B +- package: platform +- category: Platform|Board|Config +- quality: production +- ui_hints: + visibility: never +- root_path: hardware/board/config +- requires: + - name: brd4328b +- provides: + - name: brd4328b_config +- config_file: + - condition: + - brd4001a + override: + component: board_control + file_id: board_control_config + path: brd4328b_brd4001a/sl_board_control_config.h + - condition: + - brd4002a + override: + component: board_control + file_id: board_control_config + path: brd4328b_brd4002a/sl_board_control_config.h + - condition: + - brd4001a + override: + component: bootloader_euart_driver + file_id: btl_euart_driver_cfg + path: brd4328b_brd4001a/btl_euart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_ezsp_gpio_activation + file_id: ezsp_gpio_activation_cfg + path: brd4328b_brd4001a/btl_ezsp_gpio_activation_cfg.h + - condition: + - brd4001a + override: + component: bootloader_gpio_activation + file_id: btl_gpio_activation_cfg + path: brd4328b_brd4001a/btl_gpio_activation_cfg.h + - condition: + - brd4001a + override: + component: bootloader_spi_controller_eusart_driver + file_id: btl_spi_controller_eusart_driver_cfg + path: brd4328b_brd4001a/btl_spi_controller_eusart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_spi_controller_usart_driver + file_id: btl_spi_controller_usart_driver_cfg + path: brd4328b_brd4001a/btl_spi_controller_usart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_spi_peripheral_eusart_driver + file_id: btl_spi_peripheral_eusart_driver_cfg + path: brd4328b_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_spi_peripheral_usart_driver + file_id: btl_spi_peripheral_usart_driver_cfg + path: brd4328b_brd4001a/btl_spi_peripheral_usart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_uart_driver + file_id: btl_uart_driver_cfg + path: brd4328b_brd4001a/btl_uart_driver_cfg.h + - condition: + - brd4001a + override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn0 + path: brd4328b_brd4001a/sl_cpc_gpio_expander_gpio_btn0_config.h + - condition: + - brd4001a + override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn1 + path: brd4328b_brd4001a/sl_cpc_gpio_expander_gpio_btn1_config.h + - condition: + - brd4001a + override: + component: cpc_primary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4328b_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_primary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4328b_brd4001a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_spi_eusart + file_id: cpc_drv_secondary_spi_eusart_config + instance: exp + path: brd4328b_brd4001a/sl_cpc_drv_secondary_spi_eusart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_spi_usart + file_id: cpc_drv_secondary_spi_usart_config + instance: exp + path: brd4328b_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: vcom + path: brd4328b_brd4001a/sl_cpc_drv_uart_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4328b_brd4001a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: vcom + path: brd4328b_brd4001a/sl_cpc_drv_uart_usart_vcom_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4328b_brd4001a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4001a + override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: brd4328b_brd4001a/sl_device_init_hfxo_config.h + - condition: + - brd4001a + override: + component: i2cspm + file_id: i2cspm_config + instance: sensor + path: brd4328b_brd4001a/sl_i2cspm_sensor_config.h + - condition: + - brd4001a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: vcom + path: brd4328b_brd4001a/sl_iostream_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp + path: brd4328b_brd4001a/sl_iostream_eusart_exp_config.h + - condition: + - brd4001a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: vcom + path: brd4328b_brd4001a/sl_iostream_usart_vcom_config.h + - condition: + - brd4001a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp + path: brd4328b_brd4001a/sl_iostream_usart_exp_config.h + - condition: + - brd4001a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: brd4328b_brd4001a/iot_flash_cfg_msc.h + - condition: + - brd4001a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: exp + path: brd4328b_brd4001a/iot_flash_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: spiflash + path: brd4328b_brd4001a/iot_flash_cfg_spiflash.h + - condition: + - brd4001a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: sensor + path: brd4328b_brd4001a/iot_i2c_cfg_sensor.h + - condition: + - brd4001a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: exp + path: brd4328b_brd4001a/iot_i2c_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: test + path: brd4328b_brd4001a/iot_i2c_cfg_test.h + - condition: + - brd4001a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led0 + path: brd4328b_brd4001a/iot_pwm_cfg_led0.h + - condition: + - brd4001a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led1 + path: brd4328b_brd4001a/iot_pwm_cfg_led1.h + - condition: + - brd4001a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: exp + path: brd4328b_brd4001a/iot_pwm_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_spi + file_id: iot_spi_cfg + instance: exp + path: brd4328b_brd4001a/iot_spi_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_spi + file_id: iot_spi_cfg + instance: loopback + path: brd4328b_brd4001a/iot_spi_cfg_loopback.h + - condition: + - brd4001a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: vcom + path: brd4328b_brd4001a/iot_uart_cfg_vcom.h + - condition: + - brd4001a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: exp + path: brd4328b_brd4001a/iot_uart_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: loopback + path: brd4328b_brd4001a/iot_uart_cfg_loopback.h + - condition: + - brd4001a + override: + component: legacy_ncp_spi + file_id: legacy_ncp_spi_config + path: brd4328b_brd4001a/legacy_ncp_spi_config.h + - condition: + - brd4001a + override: + component: memlcd_eusart + file_id: sl_memlcd_eusart_config + path: brd4328b_brd4001a/sl_memlcd_eusart_config.h + - condition: + - brd4001a + override: + component: memlcd_usart + file_id: sl_memlcd_usart_config + path: brd4328b_brd4001a/sl_memlcd_usart_config.h + - condition: + - brd4001a + override: + component: mx25_flash_shutdown_eusart + file_id: mx25_flash_shutdown_eusart_config + path: brd4328b_brd4001a/sl_mx25_flash_shutdown_eusart_config.h + - condition: + - brd4001a + override: + component: mx25_flash_shutdown_usart + file_id: mx25_flash_shutdown_usart_config + path: brd4328b_brd4001a/sl_mx25_flash_shutdown_usart_config.h + - condition: + - brd4001a + override: + component: ot_ncp_spidrv + file_id: sl_ncp_spidrv_usart_config + path: brd4328b_brd4001a/sl_ncp_spidrv_usart_config.h + - condition: + - brd4001a + override: + component: pwm + file_id: pwm_config + instance: led0 + path: brd4328b_brd4001a/sl_pwm_init_led0_config.h + - condition: + - brd4001a + override: + component: pwm + file_id: pwm_config + instance: led1 + path: brd4328b_brd4001a/sl_pwm_init_led1_config.h + - condition: + - brd4001a + override: + component: rail_util_pti + file_id: rail_util_pti_config + path: brd4328b_brd4001a/sl_rail_util_pti_config.h + - condition: + - brd4001a + override: + component: simple_button + file_id: simple_button_config + instance: btn0 + path: brd4328b_brd4001a/sl_simple_button_btn0_config.h + - condition: + - brd4001a + override: + component: simple_button + file_id: simple_button_config + instance: btn1 + path: brd4328b_brd4001a/sl_simple_button_btn1_config.h + - condition: + - brd4001a + override: + component: simple_led + file_id: simple_led_config + instance: led0 + path: brd4328b_brd4001a/sl_simple_led_led0_config.h + - condition: + - brd4001a + override: + component: simple_led + file_id: simple_led_config + instance: led1 + path: brd4328b_brd4001a/sl_simple_led_led1_config.h + - condition: + - brd4001a + override: + component: simple_led + file_id: simple_led_config + instance: led2 + path: brd4328b_brd4001a/sl_simple_led_led2_config.h + - condition: + - brd4001a + override: + component: simple_led + file_id: simple_led_config + instance: led3 + path: brd4328b_brd4001a/sl_simple_led_led3_config.h + - condition: + - brd4001a + override: + component: simple_led + file_id: simple_led_config + instance: led4 + path: brd4328b_brd4001a/sl_simple_led_led4_config.h + - condition: + - brd4001a + override: + component: simple_rgb_pwm_led + file_id: simple_rgb_pwm_led_config + instance: rgb_led0 + path: brd4328b_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h + - condition: + - brd4001a + override: + component: spidrv + file_id: spidrv_config + instance: exp + path: brd4328b_brd4001a/sl_spidrv_exp_config.h + - condition: + - brd4001a + override: + component: spidrv_eusart + file_id: spidrv_eusart_config + instance: exp + path: brd4328b_brd4001a/sl_spidrv_eusart_exp_config.h + - condition: + - brd4001a + override: + component: spidrv_usart + file_id: spidrv_usart_config + instance: exp + path: brd4328b_brd4001a/sl_spidrv_usart_exp_config.h + - condition: + - brd4001a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: vcom + path: brd4328b_brd4001a/sl_uartdrv_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp + path: brd4328b_brd4001a/sl_uartdrv_eusart_exp_config.h + - condition: + - brd4001a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: vcom + path: brd4328b_brd4001a/sl_uartdrv_usart_vcom_config.h + - condition: + - brd4001a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp + path: brd4328b_brd4001a/sl_uartdrv_usart_exp_config.h + - condition: + - brd4002a + override: + component: bootloader_euart_driver + file_id: btl_euart_driver_cfg + path: brd4328b_brd4002a/btl_euart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_ezsp_gpio_activation + file_id: ezsp_gpio_activation_cfg + path: brd4328b_brd4002a/btl_ezsp_gpio_activation_cfg.h + - condition: + - brd4002a + override: + component: bootloader_gpio_activation + file_id: btl_gpio_activation_cfg + path: brd4328b_brd4002a/btl_gpio_activation_cfg.h + - condition: + - brd4002a + override: + component: bootloader_spi_controller_eusart_driver + file_id: btl_spi_controller_eusart_driver_cfg + path: brd4328b_brd4002a/btl_spi_controller_eusart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_spi_controller_usart_driver + file_id: btl_spi_controller_usart_driver_cfg + path: brd4328b_brd4002a/btl_spi_controller_usart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_spi_peripheral_eusart_driver + file_id: btl_spi_peripheral_eusart_driver_cfg + path: brd4328b_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_spi_peripheral_usart_driver + file_id: btl_spi_peripheral_usart_driver_cfg + path: brd4328b_brd4002a/btl_spi_peripheral_usart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_uart_driver + file_id: btl_uart_driver_cfg + path: brd4328b_brd4002a/btl_uart_driver_cfg.h + - condition: + - brd4002a + override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn0 + path: brd4328b_brd4002a/sl_cpc_gpio_expander_gpio_btn0_config.h + - condition: + - brd4002a + override: + component: cpc_gpio_expander_gpio_instance + file_id: cpc_gpio_expander_gpio_config + instance: btn1 + path: brd4328b_brd4002a/sl_cpc_gpio_expander_gpio_btn1_config.h + - condition: + - brd4002a + override: + component: cpc_primary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4328b_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_primary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4328b_brd4002a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_spi_eusart + file_id: cpc_drv_secondary_spi_eusart_config + instance: exp + path: brd4328b_brd4002a/sl_cpc_drv_secondary_spi_eusart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_spi_usart + file_id: cpc_drv_secondary_spi_usart_config + instance: exp + path: brd4328b_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: vcom + path: brd4328b_brd4002a/sl_cpc_drv_uart_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_uart_eusart_config + instance: exp + path: brd4328b_brd4002a/sl_cpc_drv_uart_eusart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: vcom + path: brd4328b_brd4002a/sl_cpc_drv_uart_usart_vcom_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_uart_usart_config + instance: exp + path: brd4328b_brd4002a/sl_cpc_drv_uart_usart_exp_config.h + - condition: + - brd4002a + override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: brd4328b_brd4002a/sl_device_init_hfxo_config.h + - condition: + - brd4002a + override: + component: i2cspm + file_id: i2cspm_config + instance: sensor + path: brd4328b_brd4002a/sl_i2cspm_sensor_config.h + - condition: + - brd4002a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: vcom + path: brd4328b_brd4002a/sl_iostream_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp + path: brd4328b_brd4002a/sl_iostream_eusart_exp_config.h + - condition: + - brd4002a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: vcom + path: brd4328b_brd4002a/sl_iostream_usart_vcom_config.h + - condition: + - brd4002a + override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp + path: brd4328b_brd4002a/sl_iostream_usart_exp_config.h + - condition: + - brd4002a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: brd4328b_brd4002a/iot_flash_cfg_msc.h + - condition: + - brd4002a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: exp + path: brd4328b_brd4002a/iot_flash_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: spiflash + path: brd4328b_brd4002a/iot_flash_cfg_spiflash.h + - condition: + - brd4002a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: sensor + path: brd4328b_brd4002a/iot_i2c_cfg_sensor.h + - condition: + - brd4002a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: exp + path: brd4328b_brd4002a/iot_i2c_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: test + path: brd4328b_brd4002a/iot_i2c_cfg_test.h + - condition: + - brd4002a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led0 + path: brd4328b_brd4002a/iot_pwm_cfg_led0.h + - condition: + - brd4002a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led1 + path: brd4328b_brd4002a/iot_pwm_cfg_led1.h + - condition: + - brd4002a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: exp + path: brd4328b_brd4002a/iot_pwm_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_spi + file_id: iot_spi_cfg + instance: exp + path: brd4328b_brd4002a/iot_spi_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_spi + file_id: iot_spi_cfg + instance: loopback + path: brd4328b_brd4002a/iot_spi_cfg_loopback.h + - condition: + - brd4002a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: vcom + path: brd4328b_brd4002a/iot_uart_cfg_vcom.h + - condition: + - brd4002a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: exp + path: brd4328b_brd4002a/iot_uart_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_uart + file_id: iot_uart_cfg + instance: loopback + path: brd4328b_brd4002a/iot_uart_cfg_loopback.h + - condition: + - brd4002a + override: + component: legacy_ncp_spi + file_id: legacy_ncp_spi_config + path: brd4328b_brd4002a/legacy_ncp_spi_config.h + - condition: + - brd4002a + override: + component: memlcd_eusart + file_id: sl_memlcd_eusart_config + path: brd4328b_brd4002a/sl_memlcd_eusart_config.h + - condition: + - brd4002a + override: + component: memlcd_usart + file_id: sl_memlcd_usart_config + path: brd4328b_brd4002a/sl_memlcd_usart_config.h + - condition: + - brd4002a + override: + component: mx25_flash_shutdown_eusart + file_id: mx25_flash_shutdown_eusart_config + path: brd4328b_brd4002a/sl_mx25_flash_shutdown_eusart_config.h + - condition: + - brd4002a + override: + component: mx25_flash_shutdown_usart + file_id: mx25_flash_shutdown_usart_config + path: brd4328b_brd4002a/sl_mx25_flash_shutdown_usart_config.h + - condition: + - brd4002a + override: + component: ot_ncp_spidrv + file_id: sl_ncp_spidrv_usart_config + path: brd4328b_brd4002a/sl_ncp_spidrv_usart_config.h + - condition: + - brd4002a + override: + component: pwm + file_id: pwm_config + instance: led0 + path: brd4328b_brd4002a/sl_pwm_init_led0_config.h + - condition: + - brd4002a + override: + component: pwm + file_id: pwm_config + instance: led1 + path: brd4328b_brd4002a/sl_pwm_init_led1_config.h + - condition: + - brd4002a + override: + component: rail_util_pti + file_id: rail_util_pti_config + path: brd4328b_brd4002a/sl_rail_util_pti_config.h + - condition: + - brd4002a + override: + component: simple_button + file_id: simple_button_config + instance: btn0 + path: brd4328b_brd4002a/sl_simple_button_btn0_config.h + - condition: + - brd4002a + override: + component: simple_button + file_id: simple_button_config + instance: btn1 + path: brd4328b_brd4002a/sl_simple_button_btn1_config.h + - condition: + - brd4002a + override: + component: simple_led + file_id: simple_led_config + instance: led0 + path: brd4328b_brd4002a/sl_simple_led_led0_config.h + - condition: + - brd4002a + override: + component: simple_led + file_id: simple_led_config + instance: led1 + path: brd4328b_brd4002a/sl_simple_led_led1_config.h + - condition: + - brd4002a + override: + component: simple_led + file_id: simple_led_config + instance: led2 + path: brd4328b_brd4002a/sl_simple_led_led2_config.h + - condition: + - brd4002a + override: + component: simple_led + file_id: simple_led_config + instance: led3 + path: brd4328b_brd4002a/sl_simple_led_led3_config.h + - condition: + - brd4002a + override: + component: simple_led + file_id: simple_led_config + instance: led4 + path: brd4328b_brd4002a/sl_simple_led_led4_config.h + - condition: + - brd4002a + override: + component: simple_rgb_pwm_led + file_id: simple_rgb_pwm_led_config + instance: rgb_led0 + path: brd4328b_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h + - condition: + - brd4002a + override: + component: spidrv + file_id: spidrv_config + instance: exp + path: brd4328b_brd4002a/sl_spidrv_exp_config.h + - condition: + - brd4002a + override: + component: spidrv_eusart + file_id: spidrv_eusart_config + instance: exp + path: brd4328b_brd4002a/sl_spidrv_eusart_exp_config.h + - condition: + - brd4002a + override: + component: spidrv_usart + file_id: spidrv_usart_config + instance: exp + path: brd4328b_brd4002a/sl_spidrv_usart_exp_config.h + - condition: + - brd4002a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: vcom + path: brd4328b_brd4002a/sl_uartdrv_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp + path: brd4328b_brd4002a/sl_uartdrv_eusart_exp_config.h + - condition: + - brd4002a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: vcom + path: brd4328b_brd4002a/sl_uartdrv_usart_vcom_config.h + - condition: + - brd4002a + override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp + path: brd4328b_brd4002a/sl_uartdrv_usart_exp_config.h diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jif.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jif.h index 2ddf7df6d1..a63fc8fd9d 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jif.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jif.h @@ -4,7 +4,7 @@ * for BGM210LA22JIF ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jnf.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jnf.h index 246b2cf842..cb29729995 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jnf.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jnf.h @@ -4,7 +4,7 @@ * for BGM210LA22JNF ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210p022jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210p022jia.h index c3de1283da..fa1c352ecc 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210p022jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210p022jia.h @@ -4,7 +4,7 @@ * for BGM210P022JIA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210p032jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210p032jia.h index e575746c70..37442c7407 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210p032jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210p032jia.h @@ -4,7 +4,7 @@ * for BGM210P032JIA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210pa22jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210pa22jia.h index b5037910eb..c7f3cacf7b 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210pa22jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210pa22jia.h @@ -4,7 +4,7 @@ * for BGM210PA22JIA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210pa32jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210pa32jia.h index 81cb200c7e..a12ce5d433 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210pa32jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210pa32jia.h @@ -4,7 +4,7 @@ * for BGM210PA32JIA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210pb22jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210pb22jia.h index c6568de1c4..36053c8bd7 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210pb22jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210pb22jia.h @@ -4,7 +4,7 @@ * for BGM210PB22JIA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210pb32jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210pb32jia.h index 838ce0c0bd..8815d53fd5 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210pb32jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210pb32jia.h @@ -4,7 +4,7 @@ * for BGM210PB32JIA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_acmp.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_acmp.h index b373d3a912..3bb123bb2f 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_acmp.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_acmp.h @@ -3,7 +3,7 @@ * @brief BGM21 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_aes.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_aes.h index 5f8f1edf7f..9238d14fc8 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_aes.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_aes.h @@ -3,7 +3,7 @@ * @brief BGM21 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_bufc.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_bufc.h index bbfe5c8fe2..afc5c33de7 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_bufc.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_bufc.h @@ -3,7 +3,7 @@ * @brief BGM21 BUFC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_buram.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_buram.h index eda9a7fd00..471dc10844 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_buram.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_buram.h @@ -3,7 +3,7 @@ * @brief BGM21 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_burtc.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_burtc.h index c2eb36ab08..403d1aa9d5 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_burtc.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_burtc.h @@ -3,7 +3,7 @@ * @brief BGM21 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_cmu.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_cmu.h index 4dda445833..f43043e9f2 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_cmu.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_cmu.h @@ -3,7 +3,7 @@ * @brief BGM21 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_devinfo.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_devinfo.h index ffe44b4bcc..0e907b9b08 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_devinfo.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_devinfo.h @@ -3,7 +3,7 @@ * @brief BGM21 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_dma_descriptor.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_dma_descriptor.h index 7c1dcf2c3d..d006038538 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_dma_descriptor.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief BGM21 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_dpll.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_dpll.h index 81d0a0bb0c..b86fbcc7e2 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_dpll.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_dpll.h @@ -3,7 +3,7 @@ * @brief BGM21 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_emu.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_emu.h index 70bc5bdcf3..aa21ecd6a3 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_emu.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_emu.h @@ -3,7 +3,7 @@ * @brief BGM21 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_fsrco.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_fsrco.h index af17f2d769..7d2eeec0b0 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_fsrco.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_fsrco.h @@ -3,7 +3,7 @@ * @brief BGM21 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpcrc.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpcrc.h index 8ba7e87c9d..daebbf6273 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpcrc.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpcrc.h @@ -3,7 +3,7 @@ * @brief BGM21 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpio.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpio.h index 8ca2c9eeea..a6a64f5f6b 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpio.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpio.h @@ -3,7 +3,7 @@ * @brief BGM21 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpio_port.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpio_port.h index 23a5aca9b3..4a9d442038 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpio_port.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_gpio_port.h @@ -3,7 +3,7 @@ * @brief BGM21 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_hfrco.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_hfrco.h index 882e2a6a91..56118bf777 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_hfrco.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_hfrco.h @@ -3,7 +3,7 @@ * @brief BGM21 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_hfxo.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_hfxo.h index d8119dc19e..657e62397d 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_hfxo.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_hfxo.h @@ -3,7 +3,7 @@ * @brief BGM21 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_i2c.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_i2c.h index 5c6d799b14..b7cca93d62 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_i2c.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_i2c.h @@ -3,7 +3,7 @@ * @brief BGM21 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_iadc.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_iadc.h index 49effd2579..61c6fb5e7e 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_iadc.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_iadc.h @@ -3,7 +3,7 @@ * @brief BGM21 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_icache.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_icache.h index 2c59e7ca75..ec6f951c31 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_icache.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_icache.h @@ -3,7 +3,7 @@ * @brief BGM21 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldma.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldma.h index 7044ffe0df..cb945ac167 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldma.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldma.h @@ -3,7 +3,7 @@ * @brief BGM21 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar.h index 1f25dcab68..b31085c4a4 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief BGM21 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar_defines.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar_defines.h index f9d5925ec5..c6cbae48cf 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief BGM21 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_letimer.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_letimer.h index 7407a4d77a..5955225511 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_letimer.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_letimer.h @@ -3,7 +3,7 @@ * @brief BGM21 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_lfrco.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_lfrco.h index 0b5b09e8ac..229ab698bb 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_lfrco.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_lfrco.h @@ -3,7 +3,7 @@ * @brief BGM21 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_lfxo.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_lfxo.h index bb6a4da1e3..c8a8e5727d 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_lfxo.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_lfxo.h @@ -3,7 +3,7 @@ * @brief BGM21 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_lvgd.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_lvgd.h index a733c85bc9..7086523590 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_lvgd.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_lvgd.h @@ -3,7 +3,7 @@ * @brief BGM21 LVGD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_msc.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_msc.h index 985a10a600..d9bda935d7 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_msc.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_msc.h @@ -3,7 +3,7 @@ * @brief BGM21 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs.h index 3b249b857d..b13610d40a 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs.h @@ -3,7 +3,7 @@ * @brief BGM21 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs_signals.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs_signals.h index 3a1d7647f7..c3c4580d69 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs_signals.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs_signals.h @@ -3,7 +3,7 @@ * @brief BGM21 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_rtcc.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_rtcc.h index b39fae68e9..cc4fce8fa0 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_rtcc.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_rtcc.h @@ -3,7 +3,7 @@ * @brief BGM21 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_semailbox.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_semailbox.h index 2756e62503..fbb8725656 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_semailbox.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_semailbox.h @@ -3,7 +3,7 @@ * @brief BGM21 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_smu.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_smu.h index 5f62b42a08..66730bd01f 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_smu.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_smu.h @@ -3,7 +3,7 @@ * @brief BGM21 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_syscfg.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_syscfg.h index e81ac4329b..e1d266a060 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_syscfg.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_syscfg.h @@ -3,7 +3,7 @@ * @brief BGM21 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_timer.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_timer.h index 9b15ea8b85..fe73fdbbbe 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_timer.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_timer.h @@ -3,7 +3,7 @@ * @brief BGM21 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ulfrco.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ulfrco.h index c0053b37e0..422f79740c 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ulfrco.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ulfrco.h @@ -3,7 +3,7 @@ * @brief BGM21 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_usart.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_usart.h index 7a32882fb5..e0fa950fe2 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_usart.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_usart.h @@ -3,7 +3,7 @@ * @brief BGM21 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_wdog.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_wdog.h index c0b910d870..ab69615541 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_wdog.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_wdog.h @@ -3,7 +3,7 @@ * @brief BGM21 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/em_device.h b/platform/Device/SiliconLabs/BGM21/Include/em_device.h index 28628bf0c4..f7b2844fc0 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/em_device.h +++ b/platform/Device/SiliconLabs/BGM21/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Include/system_bgm21.h b/platform/Device/SiliconLabs/BGM21/Include/system_bgm21.h index c1f5dca462..7266e428ef 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/system_bgm21.h +++ b/platform/Device/SiliconLabs/BGM21/Include/system_bgm21.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for BGM21 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Source/GCC/bgm21.ld b/platform/Device/SiliconLabs/BGM21/Source/GCC/bgm21.ld index 6c1bca7b52..2200b9c957 100644 --- a/platform/Device/SiliconLabs/BGM21/Source/GCC/bgm21.ld +++ b/platform/Device/SiliconLabs/BGM21/Source/GCC/bgm21.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs BGM21 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM21/Source/IAR/startup_bgm21.s b/platform/Device/SiliconLabs/BGM21/Source/IAR/startup_bgm21.s index deb015588b..06657cd20c 100644 --- a/platform/Device/SiliconLabs/BGM21/Source/IAR/startup_bgm21.s +++ b/platform/Device/SiliconLabs/BGM21/Source/IAR/startup_bgm21.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/BGM21/Source/system_bgm21.c b/platform/Device/SiliconLabs/BGM21/Source/system_bgm21.c index 82db6c8d09..4b2f224787 100644 --- a/platform/Device/SiliconLabs/BGM21/Source/system_bgm21.c +++ b/platform/Device/SiliconLabs/BGM21/Source/system_bgm21.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for BGM21 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22hna.h b/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22hna.h index 30c03f08e1..cd33695bfe 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22hna.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22hna.h @@ -4,7 +4,7 @@ * for BGM220PC22HNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22wga.h b/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22wga.h index d54105dadb..391255ff02 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22wga.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22wga.h @@ -4,7 +4,7 @@ * for BGM220PC22WGA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc12wga.h b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc12wga.h index ecefceca4d..b14b6cb349 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc12wga.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc12wga.h @@ -4,7 +4,7 @@ * for BGM220SC12WGA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22hna.h b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22hna.h index 0b8f13e24f..a2ea4b9153 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22hna.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22hna.h @@ -4,7 +4,7 @@ * for BGM220SC22HNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22wga.h b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22wga.h index 304bd80d4e..b7d81f3886 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22wga.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22wga.h @@ -4,7 +4,7 @@ * for BGM220SC22WGA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc23hna.h b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc23hna.h index fb6485781b..2dc02c4b74 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc23hna.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc23hna.h @@ -4,7 +4,7 @@ * for BGM220SC23HNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_aes.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_aes.h index c9df47bfc4..f1858a4afd 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_aes.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_aes.h @@ -3,7 +3,7 @@ * @brief BGM22 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_buram.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_buram.h index 7de50d6201..4a2d7f3167 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_buram.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_buram.h @@ -3,7 +3,7 @@ * @brief BGM22 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_burtc.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_burtc.h index 42391e7f19..286be9696a 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_burtc.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_burtc.h @@ -3,7 +3,7 @@ * @brief BGM22 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_cmu.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_cmu.h index 3d695faff2..028ea72b93 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_cmu.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_cmu.h @@ -3,7 +3,7 @@ * @brief BGM22 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_cryptoacc.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_cryptoacc.h index 5bd3e85a9c..41c7841978 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_cryptoacc.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_cryptoacc.h @@ -3,7 +3,7 @@ * @brief BGM22 CRYPTOACC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_dcdc.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_dcdc.h index f75d5e9c5d..ae6e641016 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_dcdc.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_dcdc.h @@ -3,7 +3,7 @@ * @brief BGM22 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_devinfo.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_devinfo.h index d53b69e0e2..8e87e93832 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_devinfo.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_devinfo.h @@ -3,7 +3,7 @@ * @brief BGM22 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_dma_descriptor.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_dma_descriptor.h index 23c500cacd..1d76d336d5 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief BGM22 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_dpll.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_dpll.h index 01a70228ad..1e717cd8c2 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_dpll.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_dpll.h @@ -3,7 +3,7 @@ * @brief BGM22 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_emu.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_emu.h index 77945f858e..80256465c0 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_emu.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_emu.h @@ -3,7 +3,7 @@ * @brief BGM22 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_eusart.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_eusart.h index 9b19fd0e86..a3862878ea 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_eusart.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_eusart.h @@ -3,7 +3,7 @@ * @brief BGM22 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_fsrco.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_fsrco.h index 8d2c0808f7..be96c0d62f 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_fsrco.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_fsrco.h @@ -3,7 +3,7 @@ * @brief BGM22 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpcrc.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpcrc.h index 3d74212126..a3a211dd7e 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpcrc.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpcrc.h @@ -3,7 +3,7 @@ * @brief BGM22 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpio.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpio.h index e87dd014f4..c89154c5b1 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpio.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpio.h @@ -3,7 +3,7 @@ * @brief BGM22 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpio_port.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpio_port.h index 80fb48a3d1..727211a8bf 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpio_port.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_gpio_port.h @@ -3,7 +3,7 @@ * @brief BGM22 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_hfrco.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_hfrco.h index bfc7888b01..902da7a4af 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_hfrco.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_hfrco.h @@ -3,7 +3,7 @@ * @brief BGM22 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_hfxo.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_hfxo.h index 7fbcf5eb11..3e9c6f69ab 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_hfxo.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_hfxo.h @@ -3,7 +3,7 @@ * @brief BGM22 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_i2c.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_i2c.h index 5102feaf7e..e06ada24ba 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_i2c.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_i2c.h @@ -3,7 +3,7 @@ * @brief BGM22 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_iadc.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_iadc.h index 94ddb8aebb..ece43a41f0 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_iadc.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_iadc.h @@ -3,7 +3,7 @@ * @brief BGM22 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_icache.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_icache.h index 93a66d8df3..6745ef2377 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_icache.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_icache.h @@ -3,7 +3,7 @@ * @brief BGM22 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldma.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldma.h index 80b270fd32..a466637f19 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldma.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldma.h @@ -3,7 +3,7 @@ * @brief BGM22 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar.h index b85796a213..db78fdf9bc 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief BGM22 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar_defines.h index deed96d977..716684037f 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief BGM22 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_letimer.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_letimer.h index 17fc7bbdfd..2a6f95674a 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_letimer.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_letimer.h @@ -3,7 +3,7 @@ * @brief BGM22 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_lfrco.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_lfrco.h index 2f742fb1bd..7c78ddfdcd 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_lfrco.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_lfrco.h @@ -3,7 +3,7 @@ * @brief BGM22 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_lfxo.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_lfxo.h index d0e36c4767..e1cb8e0c6c 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_lfxo.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_lfxo.h @@ -3,7 +3,7 @@ * @brief BGM22 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_msc.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_msc.h index fdc39cb7b2..45c43304e2 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_msc.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_msc.h @@ -3,7 +3,7 @@ * @brief BGM22 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_pdm.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_pdm.h index fd98bd9067..ccfaca337c 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_pdm.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_pdm.h @@ -3,7 +3,7 @@ * @brief BGM22 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs.h index cd9b8eefd9..88bc505ad9 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs.h @@ -3,7 +3,7 @@ * @brief BGM22 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs_signals.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs_signals.h index 74c127abad..0a06e257f3 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs_signals.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs_signals.h @@ -3,7 +3,7 @@ * @brief BGM22 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_rtcc.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_rtcc.h index ee9fc88ac9..6cae74a06d 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_rtcc.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_rtcc.h @@ -3,7 +3,7 @@ * @brief BGM22 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_smu.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_smu.h index f2991561ba..f9101ee7b2 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_smu.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_smu.h @@ -3,7 +3,7 @@ * @brief BGM22 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_syscfg.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_syscfg.h index 963c9e9cbb..29c12ffc4d 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_syscfg.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_syscfg.h @@ -3,7 +3,7 @@ * @brief BGM22 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_timer.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_timer.h index 183d696c97..c881e30ed1 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_timer.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_timer.h @@ -3,7 +3,7 @@ * @brief BGM22 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ulfrco.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ulfrco.h index 905f005b1c..232a308cf9 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ulfrco.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ulfrco.h @@ -3,7 +3,7 @@ * @brief BGM22 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_usart.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_usart.h index d9a04b0401..9354826137 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_usart.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_usart.h @@ -3,7 +3,7 @@ * @brief BGM22 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_wdog.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_wdog.h index becf42da5b..469906852c 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_wdog.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_wdog.h @@ -3,7 +3,7 @@ * @brief BGM22 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/em_device.h b/platform/Device/SiliconLabs/BGM22/Include/em_device.h index 492b3edb46..9d72b53e0d 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/em_device.h +++ b/platform/Device/SiliconLabs/BGM22/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Include/system_bgm22.h b/platform/Device/SiliconLabs/BGM22/Include/system_bgm22.h index e559c36701..d57ddb9581 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/system_bgm22.h +++ b/platform/Device/SiliconLabs/BGM22/Include/system_bgm22.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for BGM22 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Source/GCC/bgm22.ld b/platform/Device/SiliconLabs/BGM22/Source/GCC/bgm22.ld index 24c87ea266..eaf43ee3c6 100644 --- a/platform/Device/SiliconLabs/BGM22/Source/GCC/bgm22.ld +++ b/platform/Device/SiliconLabs/BGM22/Source/GCC/bgm22.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs BGM22 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM22/Source/IAR/startup_bgm22.s b/platform/Device/SiliconLabs/BGM22/Source/IAR/startup_bgm22.s index c1d20c62d8..adb59ab536 100644 --- a/platform/Device/SiliconLabs/BGM22/Source/IAR/startup_bgm22.s +++ b/platform/Device/SiliconLabs/BGM22/Source/IAR/startup_bgm22.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/BGM22/Source/system_bgm22.c b/platform/Device/SiliconLabs/BGM22/Source/system_bgm22.c index 5e077d567c..b34a9b5e8b 100644 --- a/platform/Device/SiliconLabs/BGM22/Source/system_bgm22.c +++ b/platform/Device/SiliconLabs/BGM22/Source/system_bgm22.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for BGM22 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa22vna.h index 52c7fd74e9..a20ba4474b 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa22vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa22vna.h @@ -4,7 +4,7 @@ * for BGM240PA22VNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vna.h index c2f371b848..3f6946590e 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vna.h @@ -4,7 +4,7 @@ * for BGM240PA32VNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vnn.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vnn.h index 5c8ad6fcd6..31557763fc 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vnn.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vnn.h @@ -4,7 +4,7 @@ * for BGM240PA32VNN ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb22vna.h index 21b37e48de..3d3a014003 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb22vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb22vna.h @@ -4,7 +4,7 @@ * for BGM240PB22VNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vna.h index 4c5c5251ba..1f6e4cbbab 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vna.h @@ -4,7 +4,7 @@ * for BGM240PB32VNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vnn.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vnn.h index 3ae65e46c9..65e6eb5841 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vnn.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vnn.h @@ -4,7 +4,7 @@ * for BGM240PB32VNN ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240sa22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240sa22vna.h index d114844798..ee6c58a2a9 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240sa22vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240sa22vna.h @@ -4,7 +4,7 @@ * for BGM240SA22VNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240sb22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240sb22vna.h index 55684f3d1c..6111f40fe3 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240sb22vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240sb22vna.h @@ -4,7 +4,7 @@ * for BGM240SB22VNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm241sb22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm241sb22vna.h index 23229962c7..3c2f581ed2 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm241sb22vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm241sb22vna.h @@ -4,7 +4,7 @@ * for BGM241SB22VNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm241sd22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm241sd22vna.h index b890b2ffbd..e919d76943 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm241sd22vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm241sd22vna.h @@ -4,7 +4,7 @@ * for BGM241SD22VNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_acmp.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_acmp.h index ff3d25415c..4d54f3b7f5 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_acmp.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_acmp.h @@ -3,7 +3,7 @@ * @brief BGM24 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_aes.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_aes.h index fbf6eb007f..64a406eaa7 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_aes.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_aes.h @@ -3,7 +3,7 @@ * @brief BGM24 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_buram.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_buram.h index 4019f669c1..b9bb9b64b8 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_buram.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_buram.h @@ -3,7 +3,7 @@ * @brief BGM24 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_burtc.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_burtc.h index 68827186a4..b694e2e2e2 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_burtc.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_burtc.h @@ -3,7 +3,7 @@ * @brief BGM24 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_cmu.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_cmu.h index 6c69150fb2..168a7f649c 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_cmu.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_cmu.h @@ -3,7 +3,7 @@ * @brief BGM24 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_dcdc.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_dcdc.h index 65b5893994..b1202a4610 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_dcdc.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_dcdc.h @@ -3,7 +3,7 @@ * @brief BGM24 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_devinfo.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_devinfo.h index ff7fd8adb8..eeab4dd6a3 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_devinfo.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_devinfo.h @@ -3,7 +3,7 @@ * @brief BGM24 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_dma_descriptor.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_dma_descriptor.h index 85929c1679..4190b7d61c 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_dma_descriptor.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief BGM24 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_dpll.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_dpll.h index 3a1a217f02..dc57dfb2ce 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_dpll.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_dpll.h @@ -3,7 +3,7 @@ * @brief BGM24 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_emu.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_emu.h index bac55b97ac..10aaf92333 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_emu.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_emu.h @@ -3,7 +3,7 @@ * @brief BGM24 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_eusart.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_eusart.h index 8592edbe22..6ac525cd59 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_eusart.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_eusart.h @@ -3,7 +3,7 @@ * @brief BGM24 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_fsrco.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_fsrco.h index 92686e3d02..9db22ff8d5 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_fsrco.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_fsrco.h @@ -3,7 +3,7 @@ * @brief BGM24 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpcrc.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpcrc.h index 9d3196ae37..c1a81c7860 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpcrc.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpcrc.h @@ -3,7 +3,7 @@ * @brief BGM24 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpio.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpio.h index c6a0ee965c..aca8f2ec61 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpio.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpio.h @@ -3,7 +3,7 @@ * @brief BGM24 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpio_port.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpio_port.h index d1aacb4983..2e5a2d67dc 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpio_port.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_gpio_port.h @@ -3,7 +3,7 @@ * @brief BGM24 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_hfrco.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_hfrco.h index ba04d1574f..2012eeb4eb 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_hfrco.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_hfrco.h @@ -3,7 +3,7 @@ * @brief BGM24 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_hfxo.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_hfxo.h index bf65d291be..29a3606c30 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_hfxo.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_hfxo.h @@ -3,7 +3,7 @@ * @brief BGM24 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_i2c.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_i2c.h index 535ba0e8df..68cdd431f8 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_i2c.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_i2c.h @@ -3,7 +3,7 @@ * @brief BGM24 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_iadc.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_iadc.h index edb0767922..5246533c5b 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_iadc.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_iadc.h @@ -3,7 +3,7 @@ * @brief BGM24 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_icache.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_icache.h index ccdd4bb205..743e4c198e 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_icache.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_icache.h @@ -3,7 +3,7 @@ * @brief BGM24 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_keyscan.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_keyscan.h index a5b19a4aa0..32db6b68a5 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_keyscan.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_keyscan.h @@ -3,7 +3,7 @@ * @brief BGM24 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldma.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldma.h index 5ca4ff9253..8f04123efb 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldma.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldma.h @@ -3,7 +3,7 @@ * @brief BGM24 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar.h index 110c8cd803..ad575cb211 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief BGM24 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar_defines.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar_defines.h index 42edd38036..9d024973a3 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief BGM24 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_letimer.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_letimer.h index f1c829758a..3e42bebe97 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_letimer.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_letimer.h @@ -3,7 +3,7 @@ * @brief BGM24 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_lfrco.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_lfrco.h index 060f2809ab..31bfcd81f2 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_lfrco.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_lfrco.h @@ -3,7 +3,7 @@ * @brief BGM24 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_lfxo.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_lfxo.h index 0aa987ba9f..c9def5036c 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_lfxo.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_lfxo.h @@ -3,7 +3,7 @@ * @brief BGM24 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_mailbox.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_mailbox.h index 0909d59e3b..5f729e1f09 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_mailbox.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_mailbox.h @@ -3,7 +3,7 @@ * @brief BGM24 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_mpahbram.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_mpahbram.h index b4d430e3a6..a90fc7a84d 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_mpahbram.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_mpahbram.h @@ -3,7 +3,7 @@ * @brief BGM24 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_msc.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_msc.h index 45cd5adebf..e838e3b6cf 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_msc.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_msc.h @@ -3,7 +3,7 @@ * @brief BGM24 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_mvp.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_mvp.h index 9a7509c257..f3e0038b1a 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_mvp.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_mvp.h @@ -3,7 +3,7 @@ * @brief BGM24 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_pcnt.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_pcnt.h index 0657da1928..6451ff70aa 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_pcnt.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_pcnt.h @@ -3,7 +3,7 @@ * @brief BGM24 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs.h index fa7efe6b22..833aaf5522 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs.h @@ -3,7 +3,7 @@ * @brief BGM24 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs_signals.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs_signals.h index a7a7f8de53..228ab47b10 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs_signals.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs_signals.h @@ -3,7 +3,7 @@ * @brief BGM24 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_scratchpad.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_scratchpad.h index ad7a49aa74..ae1748c1a3 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_scratchpad.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_scratchpad.h @@ -3,7 +3,7 @@ * @brief BGM24 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_semailbox.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_semailbox.h index 18bd96fdc3..a8255de0ef 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_semailbox.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_semailbox.h @@ -3,7 +3,7 @@ * @brief BGM24 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_smu.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_smu.h index 813f615f39..eaef960be3 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_smu.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_smu.h @@ -3,7 +3,7 @@ * @brief BGM24 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_syscfg.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_syscfg.h index 7a0c62690c..d8103e50c8 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_syscfg.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_syscfg.h @@ -3,7 +3,7 @@ * @brief BGM24 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_sysrtc.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_sysrtc.h index 1abbd79f42..b716bac77e 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_sysrtc.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_sysrtc.h @@ -3,7 +3,7 @@ * @brief BGM24 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_timer.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_timer.h index 712f445dc0..376b5235e6 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_timer.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_timer.h @@ -3,7 +3,7 @@ * @brief BGM24 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ulfrco.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ulfrco.h index 0810ff8a76..e4585af6c2 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ulfrco.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ulfrco.h @@ -3,7 +3,7 @@ * @brief BGM24 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_usart.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_usart.h index 248a83c610..bc927bdbc4 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_usart.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_usart.h @@ -3,7 +3,7 @@ * @brief BGM24 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_vdac.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_vdac.h index bf517d9dfd..efc2108ebe 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_vdac.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_vdac.h @@ -3,7 +3,7 @@ * @brief BGM24 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_wdog.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_wdog.h index c2b1510b4e..03ee8a8bcb 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_wdog.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_wdog.h @@ -3,7 +3,7 @@ * @brief BGM24 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/em_device.h b/platform/Device/SiliconLabs/BGM24/Include/em_device.h index 0ba19d793e..71ae9d18a1 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/em_device.h +++ b/platform/Device/SiliconLabs/BGM24/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Include/system_bgm24.h b/platform/Device/SiliconLabs/BGM24/Include/system_bgm24.h index 15f4f0803d..37083b1860 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/system_bgm24.h +++ b/platform/Device/SiliconLabs/BGM24/Include/system_bgm24.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for BGM24 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Source/GCC/bgm24.ld b/platform/Device/SiliconLabs/BGM24/Source/GCC/bgm24.ld index bd9f2b54e0..c95b6fb581 100644 --- a/platform/Device/SiliconLabs/BGM24/Source/GCC/bgm24.ld +++ b/platform/Device/SiliconLabs/BGM24/Source/GCC/bgm24.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs BGM24 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/BGM24/Source/IAR/startup_bgm24.s b/platform/Device/SiliconLabs/BGM24/Source/IAR/startup_bgm24.s index 41607d7b26..4ae4264ebf 100644 --- a/platform/Device/SiliconLabs/BGM24/Source/IAR/startup_bgm24.s +++ b/platform/Device/SiliconLabs/BGM24/Source/IAR/startup_bgm24.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/BGM24/Source/system_bgm24.c b/platform/Device/SiliconLabs/BGM24/Source/system_bgm24.c index c98e471c6f..77c064e2fb 100644 --- a/platform/Device/SiliconLabs/BGM24/Source/system_bgm24.c +++ b/platform/Device/SiliconLabs/BGM24/Source/system_bgm24.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for BGM24 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_buram.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_buram.h index 5d7c27c038..398e87baf1 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_buram.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_buram.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_burtc.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_burtc.h index 2dcddbdbf0..07c74365cf 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_burtc.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_burtc.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_cmu.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_cmu.h index 82f81140d3..16e360dacf 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_cmu.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_cmu.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_cryptoacc.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_cryptoacc.h index eb1a9e9876..fb1f7e2846 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_cryptoacc.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_cryptoacc.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 CRYPTOACC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dcdc.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dcdc.h index e531e82a90..2066b2f893 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dcdc.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dcdc.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_devinfo.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_devinfo.h index 69d9ffd18a..208585959f 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_devinfo.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_devinfo.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dma_descriptor.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dma_descriptor.h index e4949a69ef..8b64f20f9e 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dpll.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dpll.h index b1ef3fb3a9..53406b093a 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dpll.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dpll.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_emu.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_emu.h index 665c058ca2..6fd8dbcc81 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_emu.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_emu.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_eusart.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_eusart.h index 18475baed0..205a552c99 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_eusart.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_eusart.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_fsrco.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_fsrco.h index 25d7c29504..5b0654d435 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_fsrco.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_fsrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpcrc.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpcrc.h index 766a4d4df9..eecbf78e21 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpcrc.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpio.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpio.h index da4b9fb065..2173e08aca 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpio.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpio.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpio_port.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpio_port.h index 136dc2c4d6..c4f29685d8 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpio_port.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_hfrco.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_hfrco.h index 18c49e81e1..e9e36981d6 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_hfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_hfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_hfxo.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_hfxo.h index 6eebb70d13..316b6a2171 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_hfxo.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_hfxo.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_i2c.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_i2c.h index dc7cdbd5f7..8a0537faad 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_i2c.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_i2c.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_iadc.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_iadc.h index beee901fed..a69fba8eb3 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_iadc.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_iadc.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_icache.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_icache.h index 3957e01a97..69452eb236 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_icache.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_icache.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldma.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldma.h index 16f1a5b4d6..2d196f4e2d 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldma.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldma.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar.h index 78cbc25f94..1a7f25c9ae 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar_defines.h index e8e52f56ef..bfefbad159 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_letimer.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_letimer.h index f70a427499..678695ad79 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_letimer.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_letimer.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_lfrco.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_lfrco.h index 8a3d5e3c51..1536863e48 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_lfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_lfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_lfxo.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_lfxo.h index 49cea6820a..6111a7c7dd 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_lfxo.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_lfxo.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_msc.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_msc.h index ace2d8d04a..99b67c8e5d 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_msc.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_msc.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_pdm.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_pdm.h index 18f5d13a68..1984410d12 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_pdm.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_pdm.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs.h index 8f56363021..30b4eda783 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs_signals.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs_signals.h index 25853800be..6422d63468 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs_signals.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_rtcc.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_rtcc.h index bff19697c4..6b942a18ec 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_rtcc.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_rtcc.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_smu.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_smu.h index 08b9508b5c..fc6b92bab4 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_smu.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_smu.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_syscfg.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_syscfg.h index 88a6cd8da7..c919308741 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_syscfg.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_syscfg.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_timer.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_timer.h index 39039ce8e7..0246e89e23 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_timer.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_timer.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ulfrco.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ulfrco.h index 721a20175b..46bbc558df 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ulfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_usart.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_usart.h index 5184beac8c..f4a67678bb 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_usart.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_usart.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_wdog.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_wdog.h index 7f9140a4b4..ab3b8182e5 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_wdog.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_wdog.h @@ -3,7 +3,7 @@ * @brief EFM32PG22 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im32.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im32.h index 8bd793fde6..48a7faa215 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im32.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im32.h @@ -4,7 +4,7 @@ * for EFM32PG22C200F128IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im40.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im40.h index c97bec3a66..ad79c054ab 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im40.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im40.h @@ -4,7 +4,7 @@ * for EFM32PG22C200F128IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im32.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im32.h index 9c393608c1..90a15adfa6 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im32.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im32.h @@ -4,7 +4,7 @@ * for EFM32PG22C200F256IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im40.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im40.h index 7f0424ef7a..8eaec9be9b 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im40.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im40.h @@ -4,7 +4,7 @@ * for EFM32PG22C200F256IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im32.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im32.h index 8bd5402843..fdf2abfecd 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im32.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im32.h @@ -4,7 +4,7 @@ * for EFM32PG22C200F512IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im40.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im40.h index 885b702e05..979e20a5fa 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im40.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im40.h @@ -4,7 +4,7 @@ * for EFM32PG22C200F512IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im32.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im32.h index 3e306b2ca5..5d8032a1a3 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im32.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im32.h @@ -4,7 +4,7 @@ * for EFM32PG22C200F64IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im40.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im40.h index 0cfbdf7142..7569e50231 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im40.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im40.h @@ -4,7 +4,7 @@ * for EFM32PG22C200F64IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/em_device.h b/platform/Device/SiliconLabs/EFM32PG22/Include/em_device.h index d1232f6862..311ca4ba1c 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/system_efm32pg22.h b/platform/Device/SiliconLabs/EFM32PG22/Include/system_efm32pg22.h index 50a2a5058c..660c1ac579 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/system_efm32pg22.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/system_efm32pg22.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFM32PG22 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Source/GCC/efm32pg22.ld b/platform/Device/SiliconLabs/EFM32PG22/Source/GCC/efm32pg22.ld index 0fa25d12ef..1203eb9a82 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Source/GCC/efm32pg22.ld +++ b/platform/Device/SiliconLabs/EFM32PG22/Source/GCC/efm32pg22.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs EFM32PG22 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG22/Source/IAR/startup_efm32pg22.s b/platform/Device/SiliconLabs/EFM32PG22/Source/IAR/startup_efm32pg22.s index 074be35e54..42d57ba5f9 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Source/IAR/startup_efm32pg22.s +++ b/platform/Device/SiliconLabs/EFM32PG22/Source/IAR/startup_efm32pg22.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFM32PG22/Source/system_efm32pg22.c b/platform/Device/SiliconLabs/EFM32PG22/Source/system_efm32pg22.c index 8e9f808746..302fe08805 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Source/system_efm32pg22.c +++ b/platform/Device/SiliconLabs/EFM32PG22/Source/system_efm32pg22.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFM32PG22 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_acmp.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_acmp.h index 0e77bdd614..0cfc127eab 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_acmp.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_acmp.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_buram.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_buram.h index 02bd5d4cc7..a39eaf76cb 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_buram.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_buram.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_burtc.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_burtc.h index 7c6a9cbcd9..b3d10432d3 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_burtc.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_burtc.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_cmu.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_cmu.h index f9db8161ba..55391f77de 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_cmu.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_cmu.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dcdc.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dcdc.h index 16a4f06fd7..e22300bdb9 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dcdc.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dcdc.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_devinfo.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_devinfo.h index 8f7644258d..df4084b95b 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_devinfo.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_devinfo.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dma_descriptor.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dma_descriptor.h index 4048f8f47a..41d8d8ca89 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dpll.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dpll.h index 88967fcb32..409f7339a5 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dpll.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dpll.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_emu.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_emu.h index 17903806b0..7c863041c9 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_emu.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_emu.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_eusart.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_eusart.h index 49f6e22d6c..f298775eb7 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_eusart.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_eusart.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_fsrco.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_fsrco.h index 9fd9ce703a..305fcf51a5 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_fsrco.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_fsrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpcrc.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpcrc.h index de5a70af47..103641d84e 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpcrc.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpio.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpio.h index 4ff2862d3f..81c4cf2b63 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpio.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpio.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpio_port.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpio_port.h index 4bed0607b0..addc223b82 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpio_port.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_hfrco.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_hfrco.h index dad151c679..97792e9396 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_hfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_hfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_hfxo.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_hfxo.h index a530dfeb51..3df36c0d05 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_hfxo.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_hfxo.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_i2c.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_i2c.h index 01a7626dfa..d4e3e4e183 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_i2c.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_i2c.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_iadc.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_iadc.h index 833e3e4251..9a7c4887ad 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_iadc.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_iadc.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_icache.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_icache.h index 845f93fbe9..944ef5cdd6 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_icache.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_icache.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_keyscan.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_keyscan.h index 3ac6664760..c487fd6008 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_keyscan.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_keyscan.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lcd.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lcd.h index 44900604e4..7157d7f1e2 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lcd.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lcd.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lcdrf.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lcdrf.h index f875168753..cd22dfc424 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lcdrf.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lcdrf.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldma.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldma.h index 92a38bb8e8..abfb7d00be 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldma.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldma.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar.h index 7fb5b41d40..ebf33451ea 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar_defines.h index 7db8205061..37623bd31d 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lesense.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lesense.h index 464979ee64..82bbd06706 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lesense.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lesense.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_letimer.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_letimer.h index fb43635288..b0fc5487cf 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_letimer.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_letimer.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lfrco.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lfrco.h index 4337ec85fc..9212622b32 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lfxo.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lfxo.h index 1ac5f28dfa..72cd9dd585 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lfxo.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_lfxo.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_mailbox.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_mailbox.h index 127abf5d8d..6fdec6c815 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_mailbox.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_mailbox.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_mpahbram.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_mpahbram.h index a30757a560..b58960ffc0 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_mpahbram.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_msc.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_msc.h index 6d7b51e624..35cdb845d4 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_msc.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_msc.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_pcnt.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_pcnt.h index a14a013952..4c18c3eadc 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_pcnt.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_pcnt.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs.h index eb89285d79..faad8a0b3b 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs_signals.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs_signals.h index a414fa90a3..619076692d 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs_signals.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_scratchpad.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_scratchpad.h index a8855891f7..cc5b97a617 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_scratchpad.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_semailbox.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_semailbox.h index 884334a7f6..e02ac4e6d3 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_semailbox.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_semailbox.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_smu.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_smu.h index a257ef15b9..2622c64775 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_smu.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_smu.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_syscfg.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_syscfg.h index a7ec7b0559..5c0b79fe24 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_syscfg.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_syscfg.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_sysrtc.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_sysrtc.h index 779900be9e..226734f087 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_sysrtc.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_timer.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_timer.h index 09809c65e9..365cf8e4d4 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_timer.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_timer.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ulfrco.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ulfrco.h index 558354fb87..437e09e329 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ulfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_usart.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_usart.h index afe354d6c4..28da5ab3e4 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_usart.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_usart.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_vdac.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_vdac.h index bcf9a33416..1e44acad7e 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_vdac.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_vdac.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_wdog.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_wdog.h index d7eff1134b..0467a7b21a 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_wdog.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_wdog.h @@ -3,7 +3,7 @@ * @brief EFM32PG23 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f128im40.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f128im40.h index 63b26d9692..3fd61d1d9e 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f128im40.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f128im40.h @@ -4,7 +4,7 @@ * for EFM32PG23B200F128IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f256im40.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f256im40.h index 89cf0898f2..4563f517e7 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f256im40.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f256im40.h @@ -4,7 +4,7 @@ * for EFM32PG23B200F256IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f512im40.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f512im40.h index f824ccfa73..882b36a9bd 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f512im40.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f512im40.h @@ -4,7 +4,7 @@ * for EFM32PG23B200F512IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f64im40.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f64im40.h index 6e50ec1567..c67e4b7ba0 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f64im40.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f64im40.h @@ -4,7 +4,7 @@ * for EFM32PG23B200F64IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f128im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f128im48.h index dd17d5f19f..565108cb1e 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f128im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f128im48.h @@ -4,7 +4,7 @@ * for EFM32PG23B210F128IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f256im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f256im48.h index 205ff8a8d2..b5f3919259 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f256im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f256im48.h @@ -4,7 +4,7 @@ * for EFM32PG23B210F256IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f512im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f512im48.h index bf1e0e7d39..ba7980dd43 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f512im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f512im48.h @@ -4,7 +4,7 @@ * for EFM32PG23B210F512IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f64im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f64im48.h index b2e5e9d007..37f215bd46 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f64im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f64im48.h @@ -4,7 +4,7 @@ * for EFM32PG23B210F64IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f128im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f128im48.h index 311e8090ed..eda04a8fed 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f128im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f128im48.h @@ -4,7 +4,7 @@ * for EFM32PG23B310F128IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f256im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f256im48.h index df543435f9..2d292d7eb9 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f256im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f256im48.h @@ -4,7 +4,7 @@ * for EFM32PG23B310F256IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f512im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f512im48.h index c45f910de7..15e94845d2 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f512im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f512im48.h @@ -4,7 +4,7 @@ * for EFM32PG23B310F512IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f64im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f64im48.h index 4602d1aad7..282d1de33f 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f64im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f64im48.h @@ -4,7 +4,7 @@ * for EFM32PG23B310F64IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/em_device.h b/platform/Device/SiliconLabs/EFM32PG23/Include/em_device.h index 7a6f7c8111..48166f3ae0 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/system_efm32pg23.h b/platform/Device/SiliconLabs/EFM32PG23/Include/system_efm32pg23.h index 167ca90539..f6f87fbd3a 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/system_efm32pg23.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/system_efm32pg23.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFM32PG23 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Source/GCC/efm32pg23.ld b/platform/Device/SiliconLabs/EFM32PG23/Source/GCC/efm32pg23.ld index a22b093643..7012697b96 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Source/GCC/efm32pg23.ld +++ b/platform/Device/SiliconLabs/EFM32PG23/Source/GCC/efm32pg23.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs EFM32PG23 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG23/Source/IAR/startup_efm32pg23.s b/platform/Device/SiliconLabs/EFM32PG23/Source/IAR/startup_efm32pg23.s index 7ab7914b32..809a17cb9e 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Source/IAR/startup_efm32pg23.s +++ b/platform/Device/SiliconLabs/EFM32PG23/Source/IAR/startup_efm32pg23.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFM32PG23/Source/system_efm32pg23.c b/platform/Device/SiliconLabs/EFM32PG23/Source/system_efm32pg23.c index 5ab4b5b843..bd9b28e689 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Source/system_efm32pg23.c +++ b/platform/Device/SiliconLabs/EFM32PG23/Source/system_efm32pg23.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFM32PG23 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_acmp.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_acmp.h index 64b4d0298f..f257b72516 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_acmp.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_acmp.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_buram.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_buram.h index 64d56407b2..ed0341f1e3 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_buram.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_buram.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_burtc.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_burtc.h index 124b101fb8..e01a9b3b80 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_burtc.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_burtc.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_cmu.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_cmu.h index aedf3bf38f..85a175d3b3 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_cmu.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_cmu.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dcdc.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dcdc.h index 86caa28fbd..b628d14cd7 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dcdc.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dcdc.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_devinfo.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_devinfo.h index defda3a6f8..b517d11d22 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_devinfo.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_devinfo.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dma_descriptor.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dma_descriptor.h index dcc16723c4..f0a3f76d24 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dpll.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dpll.h index a504cd3e23..f23f2bb7bb 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dpll.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_dpll.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_emu.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_emu.h index 6a9e2d9985..7ccc2653e9 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_emu.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_emu.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_eusart.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_eusart.h index 130c98006c..316a9f7345 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_eusart.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_eusart.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_fsrco.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_fsrco.h index 46cac7d1ce..ef9b0ea315 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_fsrco.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_fsrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpcrc.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpcrc.h index 9377b82c0c..73a631741c 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpcrc.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpio.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpio.h index 7923dadca3..b986bb51d4 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpio.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpio.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpio_port.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpio_port.h index 0a24cf7c12..c7563bacb6 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpio_port.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_hfrco.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_hfrco.h index 94222df2c1..92b75d4aa8 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_hfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_hfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_hfxo.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_hfxo.h index 865e95b331..89c9e7db82 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_hfxo.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_hfxo.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_i2c.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_i2c.h index fa05d5deb0..7d757aa61d 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_i2c.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_i2c.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_iadc.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_iadc.h index 8f88efa38e..f29431f759 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_iadc.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_iadc.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_icache.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_icache.h index 7bdd6b932b..ca355e80c2 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_icache.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_icache.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_keyscan.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_keyscan.h index f65f5a43b2..e031a161c4 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_keyscan.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_keyscan.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lcd.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lcd.h index c88383bbdd..693561a351 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lcd.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lcd.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldma.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldma.h index 796b897ef4..b600f04a1a 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldma.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldma.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldmaxbar.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldmaxbar.h index 9923c579a0..d489a33820 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldmaxbar_defines.h index d7e69d2d58..244ef8d408 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lesense.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lesense.h index 0a7d2025e4..ca281be434 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lesense.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lesense.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_letimer.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_letimer.h index 8bcf99b20c..049aa450e9 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_letimer.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_letimer.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lfrco.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lfrco.h index a39937d555..4059ce548b 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lfxo.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lfxo.h index e404c1b2f8..707a796e29 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lfxo.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_lfxo.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mailbox.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mailbox.h index be5c6cbc38..43ca0e2298 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mailbox.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mailbox.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mpahbram.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mpahbram.h index 3b91e89788..dd33328ea1 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mpahbram.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_msc.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_msc.h index 23727a05b4..2ad7bf6cca 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_msc.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_msc.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mvp.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mvp.h index 22ca3c16e5..75fc96d8f9 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mvp.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_mvp.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_pcnt.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_pcnt.h index 166a90b6af..ecfd0b3192 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_pcnt.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_pcnt.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_prs.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_prs.h index 25b43e77cd..ab51cda391 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_prs.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_prs.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_prs_signals.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_prs_signals.h index 32bf003a01..79da127cf6 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_prs_signals.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_scratchpad.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_scratchpad.h index 88c0d5576e..99c8272073 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_scratchpad.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_semailbox.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_semailbox.h index ce72b1e640..76d54d0bbd 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_semailbox.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_semailbox.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_smu.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_smu.h index 53a650cf88..9f5ef5e09b 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_smu.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_smu.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_syscfg.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_syscfg.h index 61c90b5e63..a3efcf362f 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_syscfg.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_syscfg.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_sysrtc.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_sysrtc.h index cfee7d3383..7c286510f4 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_sysrtc.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_timer.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_timer.h index 8526c603a4..13e46e7567 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_timer.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_timer.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ulfrco.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ulfrco.h index 1f3d820b88..6030743d14 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ulfrco.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_usart.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_usart.h index 216618d3fb..916bce4acb 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_usart.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_usart.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_vdac.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_vdac.h index 3d91ab4d99..5ff389fb33 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_vdac.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_vdac.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_wdog.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_wdog.h index db114de9ef..3986eafdaf 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_wdog.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28_wdog.h @@ -3,7 +3,7 @@ * @brief EFM32PG28 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b200f512im68.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b200f512im68.h index 40f34d57d5..d9a8c9eaa8 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b200f512im68.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b200f512im68.h @@ -4,7 +4,7 @@ * for EFM32PG28B200F512IM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b210f1024im68.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b210f1024im68.h index 7bbf6be9bf..a40604d5d8 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b210f1024im68.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b210f1024im68.h @@ -4,7 +4,7 @@ * for EFM32PG28B210F1024IM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b300f512im68.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b300f512im68.h index fbbbca4f4a..b5c930222c 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b300f512im68.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b300f512im68.h @@ -4,7 +4,7 @@ * for EFM32PG28B300F512IM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b310f1024im68.h b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b310f1024im68.h index 299e72bf0d..56c14b2644 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b310f1024im68.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/efm32pg28b310f1024im68.h @@ -4,7 +4,7 @@ * for EFM32PG28B310F1024IM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/em_device.h b/platform/Device/SiliconLabs/EFM32PG28/Include/em_device.h index 32a6193d89..2aac030ded 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Include/system_efm32pg28.h b/platform/Device/SiliconLabs/EFM32PG28/Include/system_efm32pg28.h index a0c4415060..9914e85372 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Include/system_efm32pg28.h +++ b/platform/Device/SiliconLabs/EFM32PG28/Include/system_efm32pg28.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFM32PG28 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFM32PG28/Source/system_efm32pg28.c b/platform/Device/SiliconLabs/EFM32PG28/Source/system_efm32pg28.c index 5c005c6fed..29b520cc06 100644 --- a/platform/Device/SiliconLabs/EFM32PG28/Source/system_efm32pg28.c +++ b/platform/Device/SiliconLabs/EFM32PG28/Source/system_efm32pg28.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFM32PG28 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_acmp.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_acmp.h index a8899c1cc7..90d11e989c 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_acmp.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_aes.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_aes.h index 2f6bedc071..48e58ed2e1 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_aes.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_aes.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_bufc.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_bufc.h index 23245684ce..d8185d11a8 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_bufc.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_bufc.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 BUFC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_buram.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_buram.h index d50d505b34..694cb363b3 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_buram.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_buram.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_burtc.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_burtc.h index 41d8fb0004..8205fd67cb 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_burtc.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_cmu.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_cmu.h index c2ebf5f42f..5834cc0c8d 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_cmu.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_devinfo.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_devinfo.h index 1958c6f71e..b73b9d4cff 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dma_descriptor.h index 1aedeac102..5934d9f25d 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dpll.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dpll.h index c613e246c9..9bea534f5a 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dpll.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_emu.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_emu.h index 4912257691..af572866d6 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_emu.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_emu.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_fsrco.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_fsrco.h index 3f41df6140..c5edc4f373 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpcrc.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpcrc.h index bf2d8cb943..ed9c29587d 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpio.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpio.h index 7c846e1477..ea7426664c 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpio.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpio_port.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpio_port.h index 4a23dca18f..6eafdfc349 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_hfrco.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_hfrco.h index 49482d15db..ba5dcebfab 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_hfxo.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_hfxo.h index 9d84d3827d..72226103f2 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_i2c.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_i2c.h index 5bb718d09d..4cc90fe9f8 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_i2c.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_iadc.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_iadc.h index f76dc708d8..fe6dc18226 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_iadc.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_icache.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_icache.h index ea0821fda9..6ddb234084 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_icache.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_icache.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldma.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldma.h index 85aec28a5b..727b1d786b 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldma.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar.h index 9f13ace6a1..1e95595512 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar_defines.h index 926146535b..ca61c182fa 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_letimer.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_letimer.h index dcb4665487..346d1edece 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_letimer.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lfrco.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lfrco.h index d7406fd6f9..71eb01ea09 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lfxo.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lfxo.h index 5a00901002..1cfebc42b2 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lvgd.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lvgd.h index 36032318f0..651ff39ec7 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lvgd.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_lvgd.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 LVGD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_msc.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_msc.h index 97811c0dee..ef51042a5e 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_msc.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_msc.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs.h index 5b79ee441b..d0079b1805 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs_signals.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs_signals.h index f9405131a8..44abe2c9ea 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_rtcc.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_rtcc.h index 1ac11dec02..49b086ca86 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_semailbox.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_semailbox.h index 77a6163dec..11de60226b 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_smu.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_smu.h index fc25b89109..a3c23f100e 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_smu.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_smu.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_syscfg.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_syscfg.h index 0b90b0cd99..8376be2aa3 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_timer.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_timer.h index e4b71b00ef..f2fe35be90 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_timer.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_timer.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ulfrco.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ulfrco.h index b749445d6e..90e7c08ba3 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_usart.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_usart.h index d92e320b5b..4182c3c935 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_usart.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_usart.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_wdog.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_wdog.h index fb49500fca..1523496b02 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_wdog.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32BG21 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f1024im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f1024im32.h index 3982147ae0..e4291e4552 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f1024im32.h @@ -4,7 +4,7 @@ * for EFR32BG21A010F1024IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f512im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f512im32.h index 559dba42a6..06f3af4b95 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f512im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f512im32.h @@ -4,7 +4,7 @@ * for EFR32BG21A010F512IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f768im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f768im32.h index 7bb1fc1f27..dfa9c8ec81 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f768im32.h @@ -4,7 +4,7 @@ * for EFR32BG21A010F768IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f1024im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f1024im32.h index 4d286e33bc..0722bc586f 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f1024im32.h @@ -4,7 +4,7 @@ * for EFR32BG21A020F1024IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f512im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f512im32.h index f1fab0ceee..b09827887a 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f512im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f512im32.h @@ -4,7 +4,7 @@ * for EFR32BG21A020F512IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f768im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f768im32.h index cf961e94d0..9daafa14d1 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f768im32.h @@ -4,7 +4,7 @@ * for EFR32BG21A020F768IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f1024im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f1024im32.h index 2999170d81..3e6d296acb 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f1024im32.h @@ -4,7 +4,7 @@ * for EFR32BG21B010F1024IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f512im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f512im32.h index c6b53af36a..4a84cc4b8c 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f512im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f512im32.h @@ -4,7 +4,7 @@ * for EFR32BG21B010F512IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f768im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f768im32.h index c17043dc3a..2fffcd894e 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f768im32.h @@ -4,7 +4,7 @@ * for EFR32BG21B010F768IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f1024im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f1024im32.h index 0058067c55..30103314a6 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f1024im32.h @@ -4,7 +4,7 @@ * for EFR32BG21B020F1024IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f512im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f512im32.h index 16512e5ee0..1096bb9904 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f512im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f512im32.h @@ -4,7 +4,7 @@ * for EFR32BG21B020F512IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f768im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f768im32.h index 89338f7286..c34bbc4933 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f768im32.h @@ -4,7 +4,7 @@ * for EFR32BG21B020F768IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/em_device.h b/platform/Device/SiliconLabs/EFR32BG21/Include/em_device.h index aa2b13d775..e2ef677953 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/system_efr32bg21.h b/platform/Device/SiliconLabs/EFR32BG21/Include/system_efr32bg21.h index 3e0f68176b..59b8f94422 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/system_efr32bg21.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/system_efr32bg21.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32BG21 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Source/GCC/efr32bg21.ld b/platform/Device/SiliconLabs/EFR32BG21/Source/GCC/efr32bg21.ld index 2835062bbe..680b6a1e23 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Source/GCC/efr32bg21.ld +++ b/platform/Device/SiliconLabs/EFR32BG21/Source/GCC/efr32bg21.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs EFR32BG21 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG21/Source/IAR/startup_efr32bg21.s b/platform/Device/SiliconLabs/EFR32BG21/Source/IAR/startup_efr32bg21.s index 10a8c544fc..a9524aad79 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Source/IAR/startup_efr32bg21.s +++ b/platform/Device/SiliconLabs/EFR32BG21/Source/IAR/startup_efr32bg21.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFR32BG21/Source/system_efr32bg21.c b/platform/Device/SiliconLabs/EFR32BG21/Source/system_efr32bg21.c index 5a94ff31bf..c85a918b9a 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Source/system_efr32bg21.c +++ b/platform/Device/SiliconLabs/EFR32BG21/Source/system_efr32bg21.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32BG21 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_aes.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_aes.h index 9fc611ffe9..3a56b7f482 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_aes.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_aes.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_buram.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_buram.h index 1194ecf5b8..4a9aa171e0 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_buram.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_buram.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_burtc.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_burtc.h index 418263af6a..c588fd1877 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_burtc.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cmu.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cmu.h index d318dc1bc3..a78eb293ad 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cmu.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cryptoacc.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cryptoacc.h index e08c701720..1e2ae330a5 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cryptoacc.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cryptoacc.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 CRYPTOACC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dcdc.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dcdc.h index ee12df234f..20f59e7e56 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_devinfo.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_devinfo.h index 6789781bc0..3aabea7ef2 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dma_descriptor.h index 4fab470db8..434b64c565 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dpll.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dpll.h index 710cc24964..031748860c 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dpll.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_emu.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_emu.h index 18bbb8b3cd..9fd7a99cf8 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_emu.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_emu.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_eusart.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_eusart.h index 40469cf6e6..6e8387853e 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_eusart.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_fsrco.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_fsrco.h index 3a6aefe480..e1caa6845c 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpcrc.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpcrc.h index a9a4058207..a67999d763 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio.h index 2495ae66d2..b9e572b81b 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio_port.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio_port.h index 25080faa3c..a31a165ec7 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfrco.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfrco.h index b077d9f05d..319ab414ae 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfxo.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfxo.h index 140d70d1cf..4928e90451 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_i2c.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_i2c.h index 7ce18e73dc..1611982640 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_i2c.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_iadc.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_iadc.h index 27ff1b3369..26fcf691d2 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_iadc.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_icache.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_icache.h index d8a31d8a0e..0bc510b210 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_icache.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_icache.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldma.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldma.h index 2a45b783d8..f65624e5d5 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldma.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar.h index c9a1a24d7f..ff66dd2f61 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar_defines.h index fe35ebc624..de3fc8494f 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_letimer.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_letimer.h index b1e0cf0f86..128dc9c6b2 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_letimer.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfrco.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfrco.h index 6da2e7f2d0..962258f348 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfxo.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfxo.h index 74f92db11d..3cfce283e0 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_msc.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_msc.h index a85b8c25f9..d3b8f09d31 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_msc.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_msc.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_pdm.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_pdm.h index fa1cb9b969..8ce8308f91 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_pdm.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_pdm.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs.h index 42e0ddc077..53df672872 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs_signals.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs_signals.h index 86f568958e..32f2603334 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_rtcc.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_rtcc.h index 4f4b967392..2789ad35d8 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_smu.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_smu.h index f12bab3620..20b8b4b768 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_smu.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_smu.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_syscfg.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_syscfg.h index 2d3b0f321a..86f160bc85 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_timer.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_timer.h index 82631a7ad6..821643a393 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_timer.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_timer.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ulfrco.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ulfrco.h index a6781bf5cd..f7f4262b4a 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_usart.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_usart.h index 54061cc096..ba3cfc0920 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_usart.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_usart.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_wdog.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_wdog.h index 5beb6d3caa..9f9ebef829 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_wdog.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32BG22 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm32.h index af6e956148..e9bc7b0a85 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm32.h @@ -4,7 +4,7 @@ * for EFR32BG22C112F352GM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm40.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm40.h index eafb94f3bc..ba9ad6b28e 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm40.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm40.h @@ -4,7 +4,7 @@ * for EFR32BG22C112F352GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm32.h index 2e0ea5fa2b..574e1e4b0f 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm32.h @@ -4,7 +4,7 @@ * for EFR32BG22C222F352GM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm40.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm40.h index 98e839ab0d..97612a1887 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm40.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm40.h @@ -4,7 +4,7 @@ * for EFR32BG22C222F352GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gn32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gn32.h index 5d878dba48..9cc55ff884 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gn32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gn32.h @@ -4,7 +4,7 @@ * for EFR32BG22C222F352GN32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm32.h index d9c78f0504..9c20679130 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm32.h @@ -4,7 +4,7 @@ * for EFR32BG22C224F512GM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm40.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm40.h index 1a564f35d7..4a357dac99 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm40.h @@ -4,7 +4,7 @@ * for EFR32BG22C224F512GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gn32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gn32.h index 8e0d5c6856..65d55af831 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gn32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gn32.h @@ -4,7 +4,7 @@ * for EFR32BG22C224F512GN32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im32.h index 6a02b857d6..d3e19f96f4 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im32.h @@ -4,7 +4,7 @@ * for EFR32BG22C224F512IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h index c155f31e54..df5c9f7778 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h @@ -4,7 +4,7 @@ * for EFR32BG22C224F512IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/em_device.h b/platform/Device/SiliconLabs/EFR32BG22/Include/em_device.h index b8ca91e970..773bc5e962 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/system_efr32bg22.h b/platform/Device/SiliconLabs/EFR32BG22/Include/system_efr32bg22.h index 969bd8cec1..09609a3f76 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/system_efr32bg22.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/system_efr32bg22.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32BG22 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Source/GCC/efr32bg22.ld b/platform/Device/SiliconLabs/EFR32BG22/Source/GCC/efr32bg22.ld index 05ad35bec9..190e43ca53 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Source/GCC/efr32bg22.ld +++ b/platform/Device/SiliconLabs/EFR32BG22/Source/GCC/efr32bg22.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs EFR32BG22 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG22/Source/IAR/startup_efr32bg22.s b/platform/Device/SiliconLabs/EFR32BG22/Source/IAR/startup_efr32bg22.s index 56140b63d5..ab2b02ed4a 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Source/IAR/startup_efr32bg22.s +++ b/platform/Device/SiliconLabs/EFR32BG22/Source/IAR/startup_efr32bg22.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c b/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c index 318271f33d..83d19fb36e 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c +++ b/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32BG22 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_acmp.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_acmp.h index 2e6f2ade28..bfe8da25dc 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_acmp.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_aes.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_aes.h index 9a2e9e7de6..2a37d78ce6 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_aes.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_aes.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_buram.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_buram.h index 3f1e64422e..eb5a3755bf 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_buram.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_buram.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_burtc.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_burtc.h index 937057a5e8..d7ac094683 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_burtc.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_cmu.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_cmu.h index ca43e9c58d..54c40eb037 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_cmu.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dcdc.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dcdc.h index 0e93541e3c..b25429df9b 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_devinfo.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_devinfo.h index ad493a221f..a0ba298d4e 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dma_descriptor.h index 95514c6c84..44ef9cebca 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dpll.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dpll.h index 58f100e38f..3888c5f102 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dpll.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_emu.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_emu.h index f4b2b5fe06..ad8d4fea40 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_emu.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_emu.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_eusart.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_eusart.h index 6f08ce6d88..0f8d1e006d 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_eusart.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_fsrco.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_fsrco.h index 9f78c5c41b..015d51b418 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpcrc.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpcrc.h index 8a79f0114a..490385982d 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpio.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpio.h index e197b64111..d8e6cf5aae 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpio.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpio_port.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpio_port.h index a069a54e75..0de7dc509b 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_hfrco.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_hfrco.h index a5d816b8a9..0e6aa8d98f 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_hfxo.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_hfxo.h index 5f84fae648..6667c2ddc9 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_i2c.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_i2c.h index 9ce274178f..bfa6465ced 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_i2c.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_iadc.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_iadc.h index 5fd4cdabcf..9df0657bd6 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_iadc.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_icache.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_icache.h index 12012476f4..bbbdab129e 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_icache.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_icache.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_keyscan.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_keyscan.h index 9aac7860c4..4f750f12b4 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_keyscan.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldma.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldma.h index 635d06070f..0213cbde05 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldma.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar.h index 237bf70d09..5e7eddb6c7 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar_defines.h index 77c169fa98..a4c7caccad 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_letimer.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_letimer.h index 9f5a612517..57e4634489 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_letimer.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_lfrco.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_lfrco.h index 724d2621c5..73accf0d1b 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_lfxo.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_lfxo.h index 42fb851a75..76dc30c0df 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mailbox.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mailbox.h index 53ca9763f3..08e2b7ef65 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mpahbram.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mpahbram.h index 6177d9f5ff..94408fd25c 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_msc.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_msc.h index d5dab5339c..52532aa849 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_msc.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_msc.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mvp.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mvp.h index b7b68039ea..959117822e 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mvp.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_mvp.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_pcnt.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_pcnt.h index 0d311aa761..0eb9bfa866 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs.h index e2d04b2bf5..06637c3246 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs_signals.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs_signals.h index 02a9bac11a..f26cd7c63b 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_scratchpad.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_scratchpad.h index bec266cc59..1b75eb332f 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_semailbox.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_semailbox.h index 23f1b6901b..a65d35433d 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_smu.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_smu.h index 17a64e0cdd..a37d2d58c1 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_smu.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_smu.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_syscfg.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_syscfg.h index ad21b4e565..af560ef037 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_sysrtc.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_sysrtc.h index 374eb5a0d8..08b2d45b3a 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_timer.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_timer.h index 7081981650..8c5765f406 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_timer.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_timer.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ulfrco.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ulfrco.h index 36ee3d49f1..1694f4fdff 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_usart.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_usart.h index a67189a307..4459dec6b6 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_usart.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_usart.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_vdac.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_vdac.h index 68cb0b7e74..cbf7e226d8 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_vdac.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_wdog.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_wdog.h index d91596026b..7416215183 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_wdog.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32BG24 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024gj42.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024gj42.h index f973153e98..6a0d046aeb 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024gj42.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024gj42.h @@ -4,7 +4,7 @@ * for EFR32BG24A010F1024GJ42 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im40.h index f166be4b0c..0f4177bfae 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im40.h @@ -4,7 +4,7 @@ * for EFR32BG24A010F1024IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im48.h index eca55ae1c2..063097a309 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im48.h @@ -4,7 +4,7 @@ * for EFR32BG24A010F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im40.h index 21c38b0f68..7e80b84693 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im40.h @@ -4,7 +4,7 @@ * for EFR32BG24A010F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im48.h index f46a0e1d51..cbcee1fd71 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im48.h @@ -4,7 +4,7 @@ * for EFR32BG24A010F1536IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im40.h index 17503627c0..5e8e8e1bfb 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im40.h @@ -4,7 +4,7 @@ * for EFR32BG24A020F1024IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im48.h index 42b6205eb5..5a5341c274 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im48.h @@ -4,7 +4,7 @@ * for EFR32BG24A020F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1536im40.h index 0c9ddf9be5..ff27775e9f 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1536im40.h @@ -4,7 +4,7 @@ * for EFR32BG24A020F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a610f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a610f1536im40.h index 158deecd4e..02140a8f9c 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a610f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a610f1536im40.h @@ -4,7 +4,7 @@ * for EFR32BG24A610F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a620f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a620f1536im40.h index de9afae171..9a49b9821a 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a620f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a620f1536im40.h @@ -4,7 +4,7 @@ * for EFR32BG24A620F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1024gj42.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1024gj42.h index 3fcd4fcf63..a3e13974f6 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1024gj42.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1024gj42.h @@ -4,7 +4,7 @@ * for EFR32BG24B010F1024GJ42 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im40.h index d705df2189..701b81af66 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im40.h @@ -4,7 +4,7 @@ * for EFR32BG24B010F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im48.h index 23b57836fd..86dd6244bf 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im48.h @@ -4,7 +4,7 @@ * for EFR32BG24B010F1536IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b020f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b020f1536im40.h index 181e0fbaa8..3374617221 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b020f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b020f1536im40.h @@ -4,7 +4,7 @@ * for EFR32BG24B020F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b110f1536im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b110f1536im48.h index 0c43c69e58..8c5ee77859 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b110f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b110f1536im48.h @@ -4,7 +4,7 @@ * for EFR32BG24B110F1536IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1024im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1024im48.h index b8f2384ca6..dbd60227fa 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1024im48.h @@ -4,7 +4,7 @@ * for EFR32BG24B210F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1536im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1536im48.h index cce3285470..ecb599df98 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1536im48.h @@ -4,7 +4,7 @@ * for EFR32BG24B210F1536IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b220f1024im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b220f1024im48.h index 080a35885b..364c2ddf75 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b220f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b220f1024im48.h @@ -4,7 +4,7 @@ * for EFR32BG24B220F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b310f1536ij42.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b310f1536ij42.h index fc5afa85c6..280bedc131 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b310f1536ij42.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b310f1536ij42.h @@ -4,7 +4,7 @@ * for EFR32BG24B310F1536IJ42 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b410f1536ij42.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b410f1536ij42.h index b3eabd8b73..2feaf72b6c 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b410f1536ij42.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b410f1536ij42.h @@ -4,7 +4,7 @@ * for EFR32BG24B410F1536IJ42 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b610f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b610f1536im40.h index c5114199b6..8bc97b97c1 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b610f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b610f1536im40.h @@ -4,7 +4,7 @@ * for EFR32BG24B610F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b620f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b620f1536im40.h index dd5f9cdad8..d1fc102512 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b620f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b620f1536im40.h @@ -4,7 +4,7 @@ * for EFR32BG24B620F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/em_device.h b/platform/Device/SiliconLabs/EFR32BG24/Include/em_device.h index 038447b977..8f8661513b 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/system_efr32bg24.h b/platform/Device/SiliconLabs/EFR32BG24/Include/system_efr32bg24.h index b7db40b82d..562688b18c 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/system_efr32bg24.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/system_efr32bg24.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32BG24 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Source/GCC/efr32bg24.ld b/platform/Device/SiliconLabs/EFR32BG24/Source/GCC/efr32bg24.ld index 0b8b1ba92c..f6dc7c9717 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Source/GCC/efr32bg24.ld +++ b/platform/Device/SiliconLabs/EFR32BG24/Source/GCC/efr32bg24.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs EFR32BG24 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG24/Source/IAR/startup_efr32bg24.s b/platform/Device/SiliconLabs/EFR32BG24/Source/IAR/startup_efr32bg24.s index fe00b9ae98..3532842906 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Source/IAR/startup_efr32bg24.s +++ b/platform/Device/SiliconLabs/EFR32BG24/Source/IAR/startup_efr32bg24.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFR32BG24/Source/system_efr32bg24.c b/platform/Device/SiliconLabs/EFR32BG24/Source/system_efr32bg24.c index db5462d260..a7f5cd9331 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Source/system_efr32bg24.c +++ b/platform/Device/SiliconLabs/EFR32BG24/Source/system_efr32bg24.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32BG24 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_acmp.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_acmp.h index 2e66623eec..0cda55a098 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_acmp.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_aes.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_aes.h index 34a7bf1a80..b5077ea5c8 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_aes.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_aes.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_buram.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_buram.h index b27025959a..c169b91e36 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_buram.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_buram.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_burtc.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_burtc.h index cf94100e8b..b2d62a426a 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_burtc.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_cmu.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_cmu.h index e08086d4f3..3d29431343 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_cmu.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_cryptoacc.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_cryptoacc.h index 180dfc183e..2b8cf304f3 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_cryptoacc.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_cryptoacc.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 CRYPTOACC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dcdc.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dcdc.h index 15dd5fb5ac..ffd72a5af1 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_devinfo.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_devinfo.h index 97acd0ab35..db0dc98653 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dma_descriptor.h index 2d97fdaa30..ee56805ebc 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dpll.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dpll.h index fdf434f506..299d73e006 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dpll.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_emu.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_emu.h index 608ad200d7..f4ae75a261 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_emu.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_emu.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_etampdet.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_etampdet.h index fbedf49f46..530208b0ea 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_etampdet.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_etampdet.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 ETAMPDET register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_eusart.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_eusart.h index 61ee472147..3e1dbbe7de 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_eusart.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_fsrco.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_fsrco.h index 6bf15cd504..c47f21282d 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpcrc.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpcrc.h index 06fb80672f..42b9528b06 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio.h index 4faf1e3c35..4598f407e0 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio_port.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio_port.h index cc93a49265..1a432b0077 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_hfrco.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_hfrco.h index d94eb6744c..8f3e788e8e 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_hfxo.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_hfxo.h index a42ce0341d..f7d75e437f 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_i2c.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_i2c.h index f1e510ef85..b4f0f919de 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_i2c.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_iadc.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_iadc.h index 0f300c70e2..02464ca028 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_iadc.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_icache.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_icache.h index b27df723eb..ad50a5a661 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_icache.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_icache.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldma.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldma.h index 780bf36a2a..60894fdc3f 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldma.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar.h index ec0984b2e2..1059a384db 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar_defines.h index 63aac0f221..115d9e9cbf 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_letimer.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_letimer.h index f6a01e04a1..fc5e9f455e 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_letimer.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_lfrco.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_lfrco.h index 84d76c8e84..5b0e131fef 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_lfxo.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_lfxo.h index fc37a1608d..9f61dabc70 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_msc.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_msc.h index 501f5c24f9..8be462cd7d 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_msc.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_msc.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_pdm.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_pdm.h index ce1104a0b8..fb0071d2bb 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_pdm.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_pdm.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs.h index 4fa7894ec6..355ac4b5c8 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs_signals.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs_signals.h index 781c9461b2..c0064417b3 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_rtcc.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_rtcc.h index 750875d0bd..66ced87a8c 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_sepuf.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_sepuf.h index e0582a95cc..ff01dcf898 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_sepuf.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_sepuf.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 SEPUF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_smu.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_smu.h index 13ca4ba1a6..8ab9bd5120 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_smu.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_smu.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_syscfg.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_syscfg.h index 7b4f354add..f006231ddb 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_timer.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_timer.h index dd85cb6419..24f57bec41 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_timer.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_timer.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ulfrco.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ulfrco.h index 5353be47c7..9ae53f4ba7 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_usart.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_usart.h index e212c3ba32..52f3ed5fa0 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_usart.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_usart.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_wdog.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_wdog.h index 1bbdf8cc80..c26ec21e44 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_wdog.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32BG27 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im32.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im32.h index eea195889f..4aa1343b98 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im32.h @@ -4,7 +4,7 @@ * for EFR32BG27C140F768IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im40.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im40.h index d5650eb9ee..ce6f4c2bb9 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im40.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im40.h @@ -4,7 +4,7 @@ * for EFR32BG27C140F768IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im32.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im32.h index 1a213f1304..cca891ce9e 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im32.h @@ -4,7 +4,7 @@ * for EFR32BG27C230F768IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im40.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im40.h index babd67dc81..5f64c20ff6 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im40.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im40.h @@ -4,7 +4,7 @@ * for EFR32BG27C230F768IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768gj39.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768gj39.h index e22edc352f..b09d65ae0d 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768gj39.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768gj39.h @@ -4,7 +4,7 @@ * for EFR32BG27C320F768GJ39 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/em_device.h b/platform/Device/SiliconLabs/EFR32BG27/Include/em_device.h index 4a57cf7876..33188ff1d5 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/system_efr32bg27.h b/platform/Device/SiliconLabs/EFR32BG27/Include/system_efr32bg27.h index 6e5e634223..576477408f 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/system_efr32bg27.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/system_efr32bg27.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32BG27 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Source/GCC/efr32bg27.ld b/platform/Device/SiliconLabs/EFR32BG27/Source/GCC/efr32bg27.ld index e3bfd93357..3712f3e052 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Source/GCC/efr32bg27.ld +++ b/platform/Device/SiliconLabs/EFR32BG27/Source/GCC/efr32bg27.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs EFR32BG27 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32BG27/Source/IAR/startup_efr32bg27.s b/platform/Device/SiliconLabs/EFR32BG27/Source/IAR/startup_efr32bg27.s index ebf4739e41..2f3ccf37a8 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Source/IAR/startup_efr32bg27.s +++ b/platform/Device/SiliconLabs/EFR32BG27/Source/IAR/startup_efr32bg27.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFR32BG27/Source/system_efr32bg27.c b/platform/Device/SiliconLabs/EFR32BG27/Source/system_efr32bg27.c index 6c9073ced0..40663db729 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Source/system_efr32bg27.c +++ b/platform/Device/SiliconLabs/EFR32BG27/Source/system_efr32bg27.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32BG27 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_aes.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_aes.h index d9e84cc138..ca08571ac3 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_aes.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_aes.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_buram.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_buram.h index 1948cf1694..91d80f4d33 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_buram.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_buram.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_burtc.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_burtc.h index 31a98c3fcd..4971efaa98 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_burtc.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_cmu.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_cmu.h index 9cc485d5b2..03ee8ba585 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_cmu.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_cryptoacc.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_cryptoacc.h index 19fe883830..b24c723d17 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_cryptoacc.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_cryptoacc.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 CRYPTOACC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dcdc.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dcdc.h index a48ba9aeed..f6f119f8e8 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_devinfo.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_devinfo.h index 83ff0c8c29..e918cedb65 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dma_descriptor.h index 90f2c15008..49ee014705 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dpll.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dpll.h index 37a4f7eccc..39f88b59ef 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dpll.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_emu.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_emu.h index 7a0a6b2847..16ed8977c9 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_emu.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_emu.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_eusart.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_eusart.h index 04813f3e5a..a551c4167a 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_eusart.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_fsrco.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_fsrco.h index 850c6eb567..29785d5ee2 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpcrc.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpcrc.h index f9cc0fb157..9db8635039 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpio.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpio.h index 7a1cd7aa8d..8c925cc5bf 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpio.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpio_port.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpio_port.h index 81c82b43fc..f8fb6fb3fa 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_hfrco.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_hfrco.h index 7627a6472a..c9a6a02b91 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_hfxo.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_hfxo.h index df8947df86..1ed89e3fb6 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_i2c.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_i2c.h index 23708a3285..ed7d3504fe 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_i2c.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_iadc.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_iadc.h index 8f29df511b..293e64bed4 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_iadc.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_icache.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_icache.h index 17a813ad83..712b194e58 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_icache.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_icache.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldma.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldma.h index 2393836891..1c2296d2a8 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldma.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar.h index 78733dbb45..e63dad2542 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar_defines.h index e96c4745b7..3e52837c9f 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_letimer.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_letimer.h index 9225cf3efa..849c58b55d 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_letimer.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_lfrco.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_lfrco.h index 6d1d1277d0..3523c8e60f 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_lfxo.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_lfxo.h index c40f76eec4..eeb91b079f 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_msc.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_msc.h index 1c2319be65..8e6ff00a1f 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_msc.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_msc.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_pdm.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_pdm.h index 07488ea071..0dc77ac228 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_pdm.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_pdm.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs.h index a458d930bd..9376824525 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs_signals.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs_signals.h index 13b25d7cb5..3e7f6fed6c 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_rtcc.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_rtcc.h index 7a8998317b..8f5b588eaf 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_smu.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_smu.h index 0d04abf488..98acfb2c2d 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_smu.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_smu.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_syscfg.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_syscfg.h index 2094b6cefd..99afbb3768 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_timer.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_timer.h index 91d705bf55..5748f9fd2e 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_timer.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_timer.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ulfrco.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ulfrco.h index 4349316334..d8cfab0446 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_usart.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_usart.h index 132c9e8846..450c2ca96b 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_usart.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_usart.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_wdog.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_wdog.h index 764ce9cb93..16dbc623bd 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_wdog.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32FG22 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm32.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm32.h index 71aab01fe8..6167ba612e 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm32.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm32.h @@ -4,7 +4,7 @@ * for EFR32FG22C121F256GM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm40.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm40.h index 6448dcc4a0..4301bfd568 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm40.h @@ -4,7 +4,7 @@ * for EFR32FG22C121F256GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm32.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm32.h index 3291ad593f..9d8f68c30c 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm32.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm32.h @@ -4,7 +4,7 @@ * for EFR32FG22C121F512GM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm40.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm40.h index 16cb6a9139..35ec90d70b 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm40.h @@ -4,7 +4,7 @@ * for EFR32FG22C121F512GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/em_device.h b/platform/Device/SiliconLabs/EFR32FG22/Include/em_device.h index a801cd692e..33fac22de8 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/system_efr32fg22.h b/platform/Device/SiliconLabs/EFR32FG22/Include/system_efr32fg22.h index 6a493579dd..b79fb2c280 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/system_efr32fg22.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/system_efr32fg22.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32FG22 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Source/GCC/efr32fg22.ld b/platform/Device/SiliconLabs/EFR32FG22/Source/GCC/efr32fg22.ld index 710f1c68af..14256b6ebd 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Source/GCC/efr32fg22.ld +++ b/platform/Device/SiliconLabs/EFR32FG22/Source/GCC/efr32fg22.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs EFR32FG22 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG22/Source/IAR/startup_efr32fg22.s b/platform/Device/SiliconLabs/EFR32FG22/Source/IAR/startup_efr32fg22.s index 28ba428716..395b4d1ab3 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Source/IAR/startup_efr32fg22.s +++ b/platform/Device/SiliconLabs/EFR32FG22/Source/IAR/startup_efr32fg22.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFR32FG22/Source/system_efr32fg22.c b/platform/Device/SiliconLabs/EFR32FG22/Source/system_efr32fg22.c index 8b48d34391..5c410d7dcc 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Source/system_efr32fg22.c +++ b/platform/Device/SiliconLabs/EFR32FG22/Source/system_efr32fg22.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32FG22 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_acmp.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_acmp.h index c2e901f5de..371e0e8727 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_acmp.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_aes.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_aes.h index ddafc71eca..8e98691bf1 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_aes.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_aes.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_buram.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_buram.h index 022db804ae..c5ff0ec052 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_buram.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_buram.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_burtc.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_burtc.h index 8af6639fd2..e732656e4a 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_burtc.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_cmu.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_cmu.h index 623eeaa8d9..756eca5e12 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_cmu.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dcdc.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dcdc.h index fe783c3b74..d8a06d94dc 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_devinfo.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_devinfo.h index 5ea44e1041..78103d4882 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dma_descriptor.h index 115c9dae48..21ee5daa05 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dpll.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dpll.h index 2b1970b1b8..009ae9f8dd 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dpll.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_emu.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_emu.h index 8d5e8d1ff0..b64705e4a8 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_emu.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_emu.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_eusart.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_eusart.h index 43f79dbe62..bac7376f4f 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_eusart.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_fsrco.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_fsrco.h index 85635985fb..011ef653e0 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpcrc.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpcrc.h index b6eb7fe05b..c3a0acc22a 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpio.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpio.h index 6ee06c02b1..e6754e03f8 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpio.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpio_port.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpio_port.h index 9c3068c8a9..6ac66812cd 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_hfrco.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_hfrco.h index f833692a4c..20e43167b4 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_hfxo.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_hfxo.h index b104171706..666eb946ea 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_i2c.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_i2c.h index d3a35b1e1e..ffc9639252 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_i2c.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_iadc.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_iadc.h index d0a0b59dfd..81bfc74986 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_iadc.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_icache.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_icache.h index 323859abd0..70b282e1ec 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_icache.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_icache.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_keyscan.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_keyscan.h index f94c644734..de575adcc7 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_keyscan.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lcd.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lcd.h index c02a88f86f..a5d850ee4f 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lcd.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lcd.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lcdrf.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lcdrf.h index 76b9a769bd..990a9cd121 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lcdrf.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lcdrf.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldma.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldma.h index d685391cbd..2068c2e232 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldma.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar.h index 3fffef84e0..0d9cd2a24b 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar_defines.h index db89caf7b7..d2ce132ae7 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lesense.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lesense.h index 78863029bf..09a85de7a2 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lesense.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lesense.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_letimer.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_letimer.h index 7bd49e56f8..671863a751 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_letimer.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lfrco.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lfrco.h index 4334d65ff9..81d2b0c8db 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lfxo.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lfxo.h index e0054074e1..6ad3a211ee 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_mailbox.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_mailbox.h index eadd317ef0..2310cfed3a 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_mpahbram.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_mpahbram.h index 3a41aa57a3..c23dd598e1 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_msc.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_msc.h index e74e7529b8..f53c70fd16 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_msc.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_msc.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_pcnt.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_pcnt.h index e13eba81af..91ff180cc2 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_pfmxpprf.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_pfmxpprf.h index 6bd5a43be9..bcab2ac67f 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_pfmxpprf.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_pfmxpprf.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs.h index 00df6ed2cf..0c464bd81c 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs_signals.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs_signals.h index 166ecbd405..05ba58c252 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_scratchpad.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_scratchpad.h index 57cfba56fe..e94e5e4e5c 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_semailbox.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_semailbox.h index d085fdad78..b961cb27a9 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_smu.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_smu.h index a4b5937994..3e9bfed2cb 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_smu.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_smu.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_syscfg.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_syscfg.h index e1698b05a1..d739a1d677 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_sysrtc.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_sysrtc.h index 948dbeaeb9..62b5179007 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_timer.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_timer.h index 13ffd9a766..27865c1032 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_timer.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_timer.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ulfrco.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ulfrco.h index 3bc81623f7..4c7d51485c 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_usart.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_usart.h index 27384e5ebf..9a3f24f5e0 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_usart.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_usart.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_vdac.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_vdac.h index cd90560ea7..645021374b 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_vdac.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_wdog.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_wdog.h index 610c37e2e1..a8a9dfd2be 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_wdog.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32FG23 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f128gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f128gm40.h index f7e8d1d8ee..b0a39139b2 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f128gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f128gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23A010F128GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm40.h index 52a4eca6c3..4f0c608456 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23A010F256GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm48.h index 917f7e8095..933ef22554 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm48.h @@ -4,7 +4,7 @@ * for EFR32FG23A010F256GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm40.h index 5ea7d2391b..abfb0089d5 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23A010F512GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm48.h index 6b52e7c455..cb6a1e34e2 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm48.h @@ -4,7 +4,7 @@ * for EFR32FG23A010F512GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a011f512gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a011f512gm40.h index cf4ab63052..95d08abc8d 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a011f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a011f512gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23A011F512GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f128gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f128gm40.h index 672d27d2d1..09051cfc5b 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f128gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f128gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23A020F128GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm40.h index e1bad885e0..e8cf753535 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23A020F256GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm48.h index 237731a845..5164cb861e 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm48.h @@ -4,7 +4,7 @@ * for EFR32FG23A020F256GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm40.h index 2ef516ee9f..dc49f03942 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23A020F512GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm48.h index bb095b53ac..8eb6a12f70 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm48.h @@ -4,7 +4,7 @@ * for EFR32FG23A020F512GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a021f512gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a021f512gm40.h index 93de15490b..ccf7dd55cc 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a021f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a021f512gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23A021F512GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f128gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f128gm40.h index caf50f8be4..c7d62f86ca 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f128gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f128gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23B010F128GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512gm48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512gm48.h index 4f268d2517..660e427ef8 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512gm48.h @@ -4,7 +4,7 @@ * for EFR32FG23B010F512GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im40.h index c4540b5835..38c7c1cb6a 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im40.h @@ -4,7 +4,7 @@ * for EFR32FG23B010F512IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im48.h index 932551ce3d..957008d536 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im48.h @@ -4,7 +4,7 @@ * for EFR32FG23B010F512IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f128gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f128gm40.h index 8dd03fb149..30a3d55258 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f128gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f128gm40.h @@ -4,7 +4,7 @@ * for EFR32FG23B020F128GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im40.h index 62b0bcd65d..e0b2cf20e0 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im40.h @@ -4,7 +4,7 @@ * for EFR32FG23B020F512IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im48.h index f167b4ee8b..f1fb611edf 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im48.h @@ -4,7 +4,7 @@ * for EFR32FG23B020F512IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im40.h index 21bb6e4089..2f906a3257 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im40.h @@ -4,7 +4,7 @@ * for EFR32FG23B021F512IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im48.h index c618bcc311..6278805ac9 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im48.h @@ -4,7 +4,7 @@ * for EFR32FG23B021F512IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/em_device.h b/platform/Device/SiliconLabs/EFR32FG23/Include/em_device.h index ce6f6b78e8..5d4e7c384c 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/system_efr32fg23.h b/platform/Device/SiliconLabs/EFR32FG23/Include/system_efr32fg23.h index de48614e5a..fc76490e30 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/system_efr32fg23.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/system_efr32fg23.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32FG23 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Source/GCC/efr32fg23.ld b/platform/Device/SiliconLabs/EFR32FG23/Source/GCC/efr32fg23.ld index 9be38ba35e..b8911189dc 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Source/GCC/efr32fg23.ld +++ b/platform/Device/SiliconLabs/EFR32FG23/Source/GCC/efr32fg23.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs EFR32FG23 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG23/Source/IAR/startup_efr32fg23.s b/platform/Device/SiliconLabs/EFR32FG23/Source/IAR/startup_efr32fg23.s index 4cf1daeffd..960005b4c2 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Source/IAR/startup_efr32fg23.s +++ b/platform/Device/SiliconLabs/EFR32FG23/Source/IAR/startup_efr32fg23.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFR32FG23/Source/system_efr32fg23.c b/platform/Device/SiliconLabs/EFR32FG23/Source/system_efr32fg23.c index 95bb749795..0d8fcb46ed 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Source/system_efr32fg23.c +++ b/platform/Device/SiliconLabs/EFR32FG23/Source/system_efr32fg23.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32FG23 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_acmp.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_acmp.h index 5319f72571..790c67f4f9 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_acmp.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_aes.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_aes.h index bda2d7c55f..75f4f410f0 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_aes.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_aes.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_bufc.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_bufc.h index 342a842022..7409246b7b 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_bufc.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_bufc.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 BUFC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_buram.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_buram.h index 1a760c4aa0..31d49f870c 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_buram.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_buram.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_burtc.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_burtc.h index 217fdcea72..5d463a07ba 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_burtc.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_cmu.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_cmu.h index 36ab9add70..2392fa7fa9 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_cmu.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dcdc.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dcdc.h index edfd852e3b..38a634c622 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_devinfo.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_devinfo.h index 99f9535a1d..3cfcee223c 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dma_descriptor.h index 66bd947d65..85e7dbd469 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dpll.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dpll.h index a0cf3285ce..40cef4ad7c 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dpll.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_emu.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_emu.h index 0382fb9c52..982e2fb971 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_emu.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_emu.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_etampdet.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_etampdet.h index a56536c375..71854505ea 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_etampdet.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_etampdet.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 ETAMPDET register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_eusart.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_eusart.h index 40d6012357..5647bce680 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_eusart.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_fsrco.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_fsrco.h index 28756935b1..0b10538b12 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpcrc.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpcrc.h index c28eeffe3b..604595a659 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpio.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpio.h index 79acc03f9a..cd8c307adb 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpio.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpio_port.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpio_port.h index cc015600cc..e5f2264e6b 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_hfrco.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_hfrco.h index 5bdf026062..f591dcb500 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_hfxo.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_hfxo.h index 2efa2df8d0..434b144ca7 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_i2c.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_i2c.h index 4da0efb0cd..a9f479a4a7 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_i2c.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_iadc.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_iadc.h index 6f67cd258a..5a241b4d7c 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_iadc.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_icache.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_icache.h index fd4c7f655d..90ecf78d90 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_icache.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_icache.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldma.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldma.h index d3d61ca7e6..fee1e4a99d 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldma.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar.h index 3022901b35..b755664633 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar_defines.h index 271f102e58..bf08a8b41a 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lesense.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lesense.h index 611ca06886..a7ed846441 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lesense.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lesense.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_letimer.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_letimer.h index bf2c61ad81..5cad005470 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_letimer.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lfrco.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lfrco.h index 265bcbd0c2..384efbff62 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lfxo.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lfxo.h index 0a101fa07c..06db6fd76f 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_mailbox.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_mailbox.h index e2c49de90e..fb79db6f2c 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_mpahbram.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_mpahbram.h index 0f2c7abeed..f1dc8f7d68 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_msc.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_msc.h index f74eaefa0c..82cc4d3b01 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_msc.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_msc.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_pcnt.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_pcnt.h index 2226cd3b18..efb1d05541 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_pfmxpprf.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_pfmxpprf.h index 0a70aeb295..453eb8a8ab 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_pfmxpprf.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_pfmxpprf.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs.h index 58e87e52b0..0b69939ed9 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs_signals.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs_signals.h index 06281f0287..36c16b0b25 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_rffpll.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_rffpll.h index 69be619718..160d5ca783 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_rffpll.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_rffpll.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 RFFPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_scratchpad.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_scratchpad.h index 2d287fa00f..7612940ef8 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_semailbox.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_semailbox.h index bf8cbf54dd..71b71b2162 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_smu.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_smu.h index bcc71fe9f0..a81c40110c 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_smu.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_smu.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_syscfg.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_syscfg.h index c2f0654d3e..7a5c9b1749 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_sysrtc.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_sysrtc.h index 304ad2c4b1..7aef43dee8 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_timer.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_timer.h index 8cfaf31113..3e8a4cd9f0 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_timer.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_timer.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ulfrco.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ulfrco.h index 5f9a98286b..d1d933648a 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usb.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usb.h index 98eb517476..e316d135c9 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usb.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usb.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 USB register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usbahb.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usbahb.h index c3c6a6114d..bd01d94c4e 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usbahb.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usbahb.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 USBAHB register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usbpll.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usbpll.h index ad64cb89c1..ca0987bbf2 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usbpll.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_usbpll.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 USBPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_vdac.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_vdac.h index ab8a62f99d..4d6934b2e1 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_vdac.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_wdog.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_wdog.h index e760940308..5c78dcd0c5 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_wdog.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32FG25 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a111f1152im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a111f1152im56.h index 2fce4cea69..a941b16f28 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a111f1152im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a111f1152im56.h @@ -4,7 +4,7 @@ * for EFR32FG25A111F1152IM56 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a121f1152im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a121f1152im56.h index 35afb4e6f3..05e1ebb40d 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a121f1152im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a121f1152im56.h @@ -4,7 +4,7 @@ * for EFR32FG25A121F1152IM56 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1152im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1152im56.h index 2c33679b37..50f3f9b19a 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1152im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1152im56.h @@ -4,7 +4,7 @@ * for EFR32FG25A211F1152IM56 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1920im56.h index f97b69871a..9c6fb87657 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1920im56.h @@ -4,7 +4,7 @@ * for EFR32FG25A211F1920IM56 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1152im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1152im56.h index f245da6497..ac87a75e9e 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1152im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1152im56.h @@ -4,7 +4,7 @@ * for EFR32FG25A221F1152IM56 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1920im56.h index 50d5b207eb..d5a6a0059d 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1920im56.h @@ -4,7 +4,7 @@ * for EFR32FG25A221F1920IM56 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b111f1152im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b111f1152im56.h index e9d8e5bed5..e97c50d7a6 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b111f1152im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b111f1152im56.h @@ -4,7 +4,7 @@ * for EFR32FG25B111F1152IM56 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b121f1152im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b121f1152im56.h index 6d8e1b9776..80c04b1384 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b121f1152im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b121f1152im56.h @@ -4,7 +4,7 @@ * for EFR32FG25B121F1152IM56 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b211f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b211f1920im56.h index 4b19965c04..f5ebfcff09 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b211f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b211f1920im56.h @@ -4,7 +4,7 @@ * for EFR32FG25B211F1920IM56 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b212f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b212f1920im56.h index fd09a14e29..baf255392f 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b212f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b212f1920im56.h @@ -4,7 +4,7 @@ * for EFR32FG25B212F1920IM56 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b221f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b221f1920im56.h index 89d9746aae..e277afe906 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b221f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b221f1920im56.h @@ -4,7 +4,7 @@ * for EFR32FG25B221F1920IM56 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b222f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b222f1920im56.h index 14c41f35b5..498f509f67 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b222f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b222f1920im56.h @@ -4,7 +4,7 @@ * for EFR32FG25B222F1920IM56 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/em_device.h b/platform/Device/SiliconLabs/EFR32FG25/Include/em_device.h index 25b6a67ee4..f0a71af3d7 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/system_efr32fg25.h b/platform/Device/SiliconLabs/EFR32FG25/Include/system_efr32fg25.h index dcc992fd09..d42194b03c 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/system_efr32fg25.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/system_efr32fg25.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32FG25 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Source/GCC/efr32fg25.ld b/platform/Device/SiliconLabs/EFR32FG25/Source/GCC/efr32fg25.ld index a74e674792..74736928a5 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Source/GCC/efr32fg25.ld +++ b/platform/Device/SiliconLabs/EFR32FG25/Source/GCC/efr32fg25.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs EFR32FG25 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG25/Source/IAR/startup_efr32fg25.s b/platform/Device/SiliconLabs/EFR32FG25/Source/IAR/startup_efr32fg25.s index 236b7cb855..176733c836 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Source/IAR/startup_efr32fg25.s +++ b/platform/Device/SiliconLabs/EFR32FG25/Source/IAR/startup_efr32fg25.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFR32FG25/Source/system_efr32fg25.c b/platform/Device/SiliconLabs/EFR32FG25/Source/system_efr32fg25.c index 9121abb7a7..1be6789cf3 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Source/system_efr32fg25.c +++ b/platform/Device/SiliconLabs/EFR32FG25/Source/system_efr32fg25.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32FG25 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_acmp.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_acmp.h index 65652a2db4..85ff1dad9b 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_acmp.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_aes.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_aes.h index 6abf95a6ad..592ee834f3 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_aes.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_aes.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_buram.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_buram.h index 6cfa188034..4d514b64f1 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_buram.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_buram.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_burtc.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_burtc.h index c2cd07a228..9b9eefcd61 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_burtc.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_cmu.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_cmu.h index 7a63ac62fd..4b305b20ba 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_cmu.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dcdc.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dcdc.h index daf88ebf89..c0f218b2d4 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_devinfo.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_devinfo.h index 4cc6fe95f6..424eaa1b02 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dma_descriptor.h index 5940c67ba8..d8ea527c07 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dpll.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dpll.h index 63a0170f3c..8febfb6748 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dpll.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_emu.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_emu.h index 68ff0c9a98..999bb19869 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_emu.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_emu.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_eusart.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_eusart.h index 5c251c94ce..8d4ba0734c 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_eusart.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_fsrco.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_fsrco.h index 1882370f5d..d3e33f8191 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpcrc.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpcrc.h index 0e47e1e3c3..46a39278ea 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpio.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpio.h index 65ddf1c24d..be4f5a54fd 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpio.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpio_port.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpio_port.h index 8cae40632d..798eeace5f 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_hfrco.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_hfrco.h index cd4f94ce54..5a3140dca2 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_hfxo.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_hfxo.h index 7bdb199bff..6c114e1a4a 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_i2c.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_i2c.h index face1aa0e3..8101293800 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_i2c.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_iadc.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_iadc.h index c246bbbffd..c5275c7e31 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_iadc.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_icache.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_icache.h index ff938c41f4..38519cc57c 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_icache.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_icache.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_keyscan.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_keyscan.h index 767c74f1d2..c8084cf71e 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_keyscan.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lcd.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lcd.h index 95c5bc0d2a..6f07009d43 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lcd.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lcd.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lcdrf.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lcdrf.h index 851797cfee..e5ff1515fb 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lcdrf.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lcdrf.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldma.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldma.h index 6eb7475af2..0672ccdcb1 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldma.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldmaxbar.h index af770a9d52..079173ffbd 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldmaxbar_defines.h index 96d4060443..fa317b10a2 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lesense.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lesense.h index bddb294804..ea7afb3885 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lesense.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lesense.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_letimer.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_letimer.h index 0c2a762763..ea86be409f 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_letimer.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lfrco.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lfrco.h index 3180210d2e..691bbc820e 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lfxo.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lfxo.h index 629e7b7a08..fc18eab434 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mailbox.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mailbox.h index eef419f49d..1310452c40 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mpahbram.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mpahbram.h index 8eeeb30d97..40435e3c96 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_msc.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_msc.h index 474e283ad0..43c8f34bcb 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_msc.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_msc.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mvp.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mvp.h index c81bb2725a..f3656443f7 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mvp.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_mvp.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_pcnt.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_pcnt.h index 3eac087937..6f141960aa 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_pfmxpprf.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_pfmxpprf.h index ce849d613d..86b8a69536 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_pfmxpprf.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_pfmxpprf.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_prs.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_prs.h index 011d37d04e..812fe4fe7a 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_prs.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_prs.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_prs_signals.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_prs_signals.h index 95a4fdb82e..2e822ff753 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_scratchpad.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_scratchpad.h index 2fbcb84d11..7799d5de33 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_semailbox.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_semailbox.h index 892e80c854..62e53a8ed3 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_smu.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_smu.h index b79534e435..6afe428f99 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_smu.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_smu.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_syscfg.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_syscfg.h index d080cff070..b679260175 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_sysrtc.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_sysrtc.h index ddc54bfe1d..b5d472c8e6 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_timer.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_timer.h index 912011024f..90eed01156 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_timer.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_timer.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ulfrco.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ulfrco.h index 68a740b793..93c56cb1bc 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_usart.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_usart.h index 6471050f05..e651a324be 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_usart.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_usart.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_vdac.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_vdac.h index e3d380b7ca..6b0de7b730 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_vdac.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_wdog.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_wdog.h index 82b7a326e5..2495df71c8 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_wdog.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32FG28 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a010f1024gm48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a010f1024gm48.h index 1cbe33e473..7cf8ccae37 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a010f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a010f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32FG28A010F1024GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a010f1024gm68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a010f1024gm68.h index 4a7860499d..d2da2bf4e0 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a010f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a010f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32FG28A010F1024GM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a110f1024gm48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a110f1024gm48.h index c52035e5d8..135432984d 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a110f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a110f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32FG28A110F1024GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a110f1024gm68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a110f1024gm68.h index 9bace1d62d..ce2df74d62 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a110f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a110f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32FG28A110F1024GM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a112f1024gm48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a112f1024gm48.h index fc4c771ded..83f42bf3de 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a112f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a112f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32FG28A112F1024GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a112f1024gm68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a112f1024gm68.h index 859ec07144..7d5940a2f7 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a112f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a112f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32FG28A112F1024GM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a120f1024gm48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a120f1024gm48.h index 74dc3fb23d..eefe49d4c2 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a120f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a120f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32FG28A120F1024GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a120f1024gm68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a120f1024gm68.h index 001e3f90ef..be4caf32a0 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a120f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a120f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32FG28A120F1024GM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a122f1024gm48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a122f1024gm48.h index 2004ac1756..2618aae88b 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a122f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a122f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32FG28A122F1024GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a122f1024gm68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a122f1024gm68.h index cee8017a08..df0d55833a 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a122f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28a122f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32FG28A122F1024GM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b310f1024im48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b310f1024im48.h index e320bf52aa..6bf92a27ef 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b310f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b310f1024im48.h @@ -4,7 +4,7 @@ * for EFR32FG28B310F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b310f1024im68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b310f1024im68.h index a6a8cee94d..0aaedda97f 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b310f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b310f1024im68.h @@ -4,7 +4,7 @@ * for EFR32FG28B310F1024IM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b312f1024im48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b312f1024im48.h index d83e38c0b7..7832592247 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b312f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b312f1024im48.h @@ -4,7 +4,7 @@ * for EFR32FG28B312F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b312f1024im68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b312f1024im68.h index 1dc2ceca9c..9648fc4012 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b312f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b312f1024im68.h @@ -4,7 +4,7 @@ * for EFR32FG28B312F1024IM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b320f1024im48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b320f1024im48.h index eb38e5443a..3a17722f67 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b320f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b320f1024im48.h @@ -4,7 +4,7 @@ * for EFR32FG28B320F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b320f1024im68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b320f1024im68.h index 0cb9cb51ee..e5262e6ccb 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b320f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b320f1024im68.h @@ -4,7 +4,7 @@ * for EFR32FG28B320F1024IM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b322f1024im48.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b322f1024im48.h index 388bb52294..6af05cfa8e 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b322f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b322f1024im48.h @@ -4,7 +4,7 @@ * for EFR32FG28B322F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b322f1024im68.h b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b322f1024im68.h index e33d1e1e11..af180d0e9e 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b322f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28b322f1024im68.h @@ -4,7 +4,7 @@ * for EFR32FG28B322F1024IM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/em_device.h b/platform/Device/SiliconLabs/EFR32FG28/Include/em_device.h index 537d0ef1e9..fb793ff64e 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Include/system_efr32fg28.h b/platform/Device/SiliconLabs/EFR32FG28/Include/system_efr32fg28.h index a667a10531..77a80c1c23 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Include/system_efr32fg28.h +++ b/platform/Device/SiliconLabs/EFR32FG28/Include/system_efr32fg28.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32FG28 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Source/GCC/efr32fg28.ld b/platform/Device/SiliconLabs/EFR32FG28/Source/GCC/efr32fg28.ld index f46ad7998a..743cdfeb76 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Source/GCC/efr32fg28.ld +++ b/platform/Device/SiliconLabs/EFR32FG28/Source/GCC/efr32fg28.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs EFR32FG28 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32FG28/Source/IAR/startup_efr32fg28.s b/platform/Device/SiliconLabs/EFR32FG28/Source/IAR/startup_efr32fg28.s index 7134278183..cddc79ffc9 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Source/IAR/startup_efr32fg28.s +++ b/platform/Device/SiliconLabs/EFR32FG28/Source/IAR/startup_efr32fg28.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFR32FG28/Source/system_efr32fg28.c b/platform/Device/SiliconLabs/EFR32FG28/Source/system_efr32fg28.c index 44d80c9e04..dfb9bc24fa 100644 --- a/platform/Device/SiliconLabs/EFR32FG28/Source/system_efr32fg28.c +++ b/platform/Device/SiliconLabs/EFR32FG28/Source/system_efr32fg28.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32FG28 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_acmp.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_acmp.h index 3357b1cf90..86a0adcd28 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_acmp.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_aes.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_aes.h index 94fc4015a8..ff4090de5b 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_aes.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_aes.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_bufc.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_bufc.h index 180022dfbb..e3d3335f47 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_bufc.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_bufc.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 BUFC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_buram.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_buram.h index 9803b00eed..b0e85c1781 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_buram.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_buram.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_burtc.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_burtc.h index 2cde107c5e..d5ecb6d5be 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_burtc.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_cmu.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_cmu.h index 5449a8525e..e20b8b1760 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_cmu.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_devinfo.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_devinfo.h index 30b7bbb005..01a1f0476a 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dma_descriptor.h index ce305f372d..af3eed766c 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dpll.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dpll.h index 2601d308de..ebea97b763 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dpll.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_emu.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_emu.h index 0eb2eb23a8..907f89ab1d 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_emu.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_emu.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_fsrco.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_fsrco.h index a5f46b53b7..cffb4f0729 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpcrc.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpcrc.h index 1d6976d135..7df9055ab2 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpio.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpio.h index 49335dfac5..c24b7a68fe 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpio.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpio_port.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpio_port.h index 40a47cf65b..5d1272ecba 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_hfrco.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_hfrco.h index 2769370630..5025debd0b 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_hfxo.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_hfxo.h index 6bd640c357..aaec60db03 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_i2c.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_i2c.h index 0a5baaea48..e781ca6a3e 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_i2c.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_iadc.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_iadc.h index 8313bc2745..07e6e16e69 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_iadc.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_icache.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_icache.h index 01d1c8f6a3..b132129f62 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_icache.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_icache.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldma.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldma.h index 0384c9154e..2bf1d19f0b 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldma.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar.h index fb4aad6fc2..05dcde0706 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar_defines.h index 7fd39ee878..86f2b63cbc 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_letimer.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_letimer.h index 05176f4eaa..816c909584 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_letimer.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lfrco.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lfrco.h index 8a38f0a6b1..b514d3b1e6 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lfxo.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lfxo.h index 4d0ded9abf..0f8f7fda1c 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lvgd.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lvgd.h index 020b8b0f38..ce6691ce84 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lvgd.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_lvgd.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 LVGD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_msc.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_msc.h index ec87bf2a22..4b4bbc0fdc 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_msc.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_msc.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs.h index a2b9e9f92a..9ddb9cc997 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs_signals.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs_signals.h index 60ce772d0f..70ea7cbd19 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_rtcc.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_rtcc.h index 57faab46b0..03c2c9fbf9 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_semailbox.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_semailbox.h index ca65b72d57..3637a13c25 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_smu.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_smu.h index 69346f02c5..d446a49140 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_smu.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_smu.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_syscfg.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_syscfg.h index ebd8e1be5b..eb1c9b9364 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_timer.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_timer.h index d4941791b7..7baa258f1d 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_timer.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_timer.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ulfrco.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ulfrco.h index a4e69c235e..c72d12ff7b 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_usart.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_usart.h index 69795012b4..f2644bc505 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_usart.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_usart.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_wdog.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_wdog.h index 492011e262..3fd72a2668 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_wdog.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32MG21 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f1024im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f1024im32.h index 75d66e8e91..1c15b69f58 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f1024im32.h @@ -4,7 +4,7 @@ * for EFR32MG21A010F1024IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f512im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f512im32.h index c827623e1b..fc5756777f 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f512im32.h @@ -4,7 +4,7 @@ * for EFR32MG21A010F512IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f768im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f768im32.h index d7e7825748..6b8c4fea49 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f768im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f768im32.h @@ -4,7 +4,7 @@ * for EFR32MG21A010F768IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f1024im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f1024im32.h index 1e3021aa82..c23633feff 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f1024im32.h @@ -4,7 +4,7 @@ * for EFR32MG21A020F1024IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f512im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f512im32.h index b8a8d8a09c..5b38d88c68 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f512im32.h @@ -4,7 +4,7 @@ * for EFR32MG21A020F512IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f768im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f768im32.h index e67a38077f..01978f3d32 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f768im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f768im32.h @@ -4,7 +4,7 @@ * for EFR32MG21A020F768IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f1024im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f1024im32.h index 18686563c8..f8c1e6deeb 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f1024im32.h @@ -4,7 +4,7 @@ * for EFR32MG21B010F1024IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f512im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f512im32.h index 938d13a7db..95c109432b 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f512im32.h @@ -4,7 +4,7 @@ * for EFR32MG21B010F512IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f768im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f768im32.h index 512b1f1f27..b269be1850 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f768im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f768im32.h @@ -4,7 +4,7 @@ * for EFR32MG21B010F768IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f1024im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f1024im32.h index 35835ce452..5194f466c7 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f1024im32.h @@ -4,7 +4,7 @@ * for EFR32MG21B020F1024IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f512im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f512im32.h index d476335dba..bf76578095 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f512im32.h @@ -4,7 +4,7 @@ * for EFR32MG21B020F512IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f768im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f768im32.h index 5c5cbc5f4c..4d0d1872d7 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f768im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f768im32.h @@ -4,7 +4,7 @@ * for EFR32MG21B020F768IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/em_device.h b/platform/Device/SiliconLabs/EFR32MG21/Include/em_device.h index f9e53a6c5d..42b4490095 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/rm21z000f1024im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/rm21z000f1024im32.h index 927ecd603c..731692a763 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/rm21z000f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/rm21z000f1024im32.h @@ -4,7 +4,7 @@ * for RM21Z000F1024IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/system_efr32mg21.h b/platform/Device/SiliconLabs/EFR32MG21/Include/system_efr32mg21.h index e74c416540..2657ad168f 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/system_efr32mg21.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/system_efr32mg21.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32MG21 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Source/GCC/efr32mg21.ld b/platform/Device/SiliconLabs/EFR32MG21/Source/GCC/efr32mg21.ld index 366c58161d..961e30936c 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Source/GCC/efr32mg21.ld +++ b/platform/Device/SiliconLabs/EFR32MG21/Source/GCC/efr32mg21.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs EFR32MG21 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG21/Source/IAR/startup_efr32mg21.s b/platform/Device/SiliconLabs/EFR32MG21/Source/IAR/startup_efr32mg21.s index f94e98da5d..7918deb4a6 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Source/IAR/startup_efr32mg21.s +++ b/platform/Device/SiliconLabs/EFR32MG21/Source/IAR/startup_efr32mg21.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFR32MG21/Source/system_efr32mg21.c b/platform/Device/SiliconLabs/EFR32MG21/Source/system_efr32mg21.c index 72ccd201c8..9c59d6b146 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Source/system_efr32mg21.c +++ b/platform/Device/SiliconLabs/EFR32MG21/Source/system_efr32mg21.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32MG21 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_aes.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_aes.h index b07648fe3c..14c45647b9 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_aes.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_aes.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_buram.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_buram.h index d756e6cfda..6e0ca2502f 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_buram.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_buram.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_burtc.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_burtc.h index 7caf7e236a..767b3dcd90 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_burtc.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_cmu.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_cmu.h index 41b48d29d1..d6d476fbdc 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_cmu.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_cryptoacc.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_cryptoacc.h index 2984f7afa6..6abd97ff8f 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_cryptoacc.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_cryptoacc.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 CRYPTOACC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dcdc.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dcdc.h index 926586607e..6f4bc5e2cd 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_devinfo.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_devinfo.h index 318963b1ef..6a20df8742 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dma_descriptor.h index 580a8ce871..0026f6e60b 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dpll.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dpll.h index 818efdc40a..2037a794e1 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dpll.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_emu.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_emu.h index 2eabd5e031..456f2e13e9 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_emu.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_emu.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_eusart.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_eusart.h index 135ebdd5be..7954923fd8 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_eusart.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_fsrco.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_fsrco.h index 76e2ffa870..44bb13c49a 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpcrc.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpcrc.h index f7077947f1..498d4d1c95 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpio.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpio.h index 8aac474589..87eac05956 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpio.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpio_port.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpio_port.h index a0f5333f37..402627a35a 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_hfrco.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_hfrco.h index 70a9aaa8b2..b10e21e073 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_hfxo.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_hfxo.h index 5f7483f59a..4858da5917 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_i2c.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_i2c.h index 2f40b75206..cf59af6d5f 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_i2c.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_iadc.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_iadc.h index a26a13c4ba..fb704d21a0 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_iadc.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_icache.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_icache.h index f15eed17da..2617914366 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_icache.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_icache.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldma.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldma.h index 5defdd37ca..2cce25f384 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldma.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar.h index b08d05bf2f..548ad07ab6 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar_defines.h index 501ca1777b..44bb829525 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_letimer.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_letimer.h index ce9ca6fcf0..51c2bcb47b 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_letimer.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_lfrco.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_lfrco.h index 8e67708ce2..3ebb7c7e06 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_lfxo.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_lfxo.h index cc831f85b1..0cc44848d7 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_msc.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_msc.h index 6b79813f10..db61da7eb1 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_msc.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_msc.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_pdm.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_pdm.h index 4f4b5149bf..3f8b2e6ede 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_pdm.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_pdm.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs.h index 0ac54a0b03..b6812e63aa 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs_signals.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs_signals.h index aecaaee7a9..2a452024c8 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_rtcc.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_rtcc.h index 2bf9fdfc9a..54a5d18cde 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_smu.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_smu.h index c515db0a17..8d95b02dd7 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_smu.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_smu.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_syscfg.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_syscfg.h index fc648f552d..3db24e8f65 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_timer.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_timer.h index 3ef527bdf2..3be03fadff 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_timer.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_timer.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ulfrco.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ulfrco.h index d96e0ce505..081fb2f4e0 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_usart.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_usart.h index 2e57969685..07115b41a1 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_usart.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_usart.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_wdog.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_wdog.h index 1e8a84da53..7181bfd36b 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_wdog.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32MG22 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22a224f512im40.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22a224f512im40.h index ce889e197c..d023285eea 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22a224f512im40.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22a224f512im40.h @@ -4,7 +4,7 @@ * for EFR32MG22A224F512IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512gn32.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512gn32.h index d32d11536b..5ade4c4e12 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512gn32.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512gn32.h @@ -4,7 +4,7 @@ * for EFR32MG22C224F512GN32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im32.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im32.h index a97223873c..3ed968ba31 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im32.h @@ -4,7 +4,7 @@ * for EFR32MG22C224F512IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im40.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im40.h index 4edf94c742..87819bae8b 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im40.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im40.h @@ -4,7 +4,7 @@ * for EFR32MG22C224F512IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/em_device.h b/platform/Device/SiliconLabs/EFR32MG22/Include/em_device.h index 9f2d0fb0ff..f2b88faa6a 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/system_efr32mg22.h b/platform/Device/SiliconLabs/EFR32MG22/Include/system_efr32mg22.h index 2b47db71c7..d423914ad0 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/system_efr32mg22.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/system_efr32mg22.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32MG22 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Source/GCC/efr32mg22.ld b/platform/Device/SiliconLabs/EFR32MG22/Source/GCC/efr32mg22.ld index 3f6c25f1a2..6de9e41631 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Source/GCC/efr32mg22.ld +++ b/platform/Device/SiliconLabs/EFR32MG22/Source/GCC/efr32mg22.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs EFR32MG22 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG22/Source/IAR/startup_efr32mg22.s b/platform/Device/SiliconLabs/EFR32MG22/Source/IAR/startup_efr32mg22.s index d504adb9dc..9e6c52cb6b 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Source/IAR/startup_efr32mg22.s +++ b/platform/Device/SiliconLabs/EFR32MG22/Source/IAR/startup_efr32mg22.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFR32MG22/Source/system_efr32mg22.c b/platform/Device/SiliconLabs/EFR32MG22/Source/system_efr32mg22.c index 25f26e4cc4..26adbc8e3b 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Source/system_efr32mg22.c +++ b/platform/Device/SiliconLabs/EFR32MG22/Source/system_efr32mg22.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32MG22 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_acmp.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_acmp.h index 9b04234150..a06dbe6c4a 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_acmp.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_aes.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_aes.h index fc5928f054..5c6a13b56b 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_aes.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_aes.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_buram.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_buram.h index a1259b668f..e9fb2dcbdb 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_buram.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_buram.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_burtc.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_burtc.h index 90968d4529..634c41d0cd 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_burtc.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_cmu.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_cmu.h index 7c3971ed02..0c5e1c1a2b 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_cmu.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dcdc.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dcdc.h index 6ffc79bbee..c71a3ca536 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_devinfo.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_devinfo.h index 21aa898e11..58aaca12d2 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dma_descriptor.h index c7f5d1519f..dd3ff5b607 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dpll.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dpll.h index f1f1e3e3c0..6b2cc388fe 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dpll.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_emu.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_emu.h index c3c159395a..1e0e59ea40 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_emu.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_emu.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_eusart.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_eusart.h index c8e54c99f2..42ce2890db 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_eusart.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_fsrco.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_fsrco.h index 39ccc52b54..8819b1d681 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpcrc.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpcrc.h index c3fbd52f17..30c9a4d071 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio.h index df8d784200..78077eb164 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio_port.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio_port.h index 3177d5b1c0..893f40a5ea 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfrco.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfrco.h index 8e54f9f7af..4076829899 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfxo.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfxo.h index 10f2971be0..1295a50a6a 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_i2c.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_i2c.h index 5ca0065d61..2540544d30 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_i2c.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_iadc.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_iadc.h index 0adf097103..3977d59284 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_iadc.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_icache.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_icache.h index 4d41609299..bedf0f25c4 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_icache.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_icache.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_keyscan.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_keyscan.h index b1ed2994c4..8ede6d8902 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_keyscan.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldma.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldma.h index 890cb379ef..4d0303a806 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldma.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar.h index 98874c7c30..2cb886d20b 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar_defines.h index 21648435ee..60f0472824 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_letimer.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_letimer.h index 1fa36ec0c5..f18ee61b64 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_letimer.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfrco.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfrco.h index d89c987870..d35a232aa5 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfxo.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfxo.h index d916139b9f..88552f2bcd 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mailbox.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mailbox.h index 2697da0abd..b494c51ae8 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mpahbram.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mpahbram.h index 9eca4c1074..cad7c8172e 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_msc.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_msc.h index 6b2ab4fa89..dda366af7b 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_msc.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_msc.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mvp.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mvp.h index 111b80342a..0083443456 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mvp.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mvp.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_pcnt.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_pcnt.h index c2ba4e8cca..eeabf9af43 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs.h index 0692d2db6b..360f7bd6e0 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs_signals.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs_signals.h index 6dbf41a2a0..f646b9e1d2 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_scratchpad.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_scratchpad.h index abbe22e686..dae1b617d2 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_semailbox.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_semailbox.h index eca814b0ac..bd296600bc 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_smu.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_smu.h index 09c83b6667..0cd0d08b8a 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_smu.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_smu.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_syscfg.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_syscfg.h index 9cdc793fc3..c966d84c3a 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_sysrtc.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_sysrtc.h index 16b2c316ca..cbd93b7bf7 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_timer.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_timer.h index 7848198f4d..0f7ebfc26b 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_timer.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_timer.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ulfrco.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ulfrco.h index bc1f4fdfff..9179f30824 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_usart.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_usart.h index d80e44ad4b..05dab88bf4 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_usart.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_usart.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_vdac.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_vdac.h index 29863a2317..5c8bff29ed 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_vdac.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_wdog.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_wdog.h index 4955724250..6bb1189732 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_wdog.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32MG24 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im40.h index 8542a97a0c..c07c40f115 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A010F1024IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im48.h index 5f67c545fb..5a3ebe807b 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im48.h @@ -4,7 +4,7 @@ * for EFR32MG24A010F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm40.h index 4ee983e1a6..b23ee4bcd1 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm40.h @@ -4,7 +4,7 @@ * for EFR32MG24A010F1536GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm48.h index 70af2fcdc4..69a7205720 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm48.h @@ -4,7 +4,7 @@ * for EFR32MG24A010F1536GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im40.h index 3bcac28691..e10d4248ef 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A010F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im48.h index ed0aa4de3c..a935bfc9bc 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24A010F1536IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im40.h index 2af257c7e9..dd9fec3461 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A010F768IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im48.h index 7e7191b847..644aafc373 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im48.h @@ -4,7 +4,7 @@ * for EFR32MG24A010F768IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im40.h index 249abb1315..4ee41c696e 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A020F1024IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im48.h index 7129614693..4e936340aa 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im48.h @@ -4,7 +4,7 @@ * for EFR32MG24A020F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm40.h index d23a32fae9..f4d5dde721 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm40.h @@ -4,7 +4,7 @@ * for EFR32MG24A020F1536GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm48.h index fabf5bea5e..1ea9c1f6f2 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm48.h @@ -4,7 +4,7 @@ * for EFR32MG24A020F1536GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im40.h index 0ae30d1ce0..edc19df0a8 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A020F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im48.h index 600c1ae205..d925e54052 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24A020F1536IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f768im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f768im40.h index 345c129a07..b80f7f98c0 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f768im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f768im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A020F768IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a021f1024im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a021f1024im40.h index 064d7f8468..e2c98ca1f6 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a021f1024im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a021f1024im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A021F1024IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1024im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1024im48.h index e818043ee3..e809b3a3b2 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1024im48.h @@ -4,7 +4,7 @@ * for EFR32MG24A110F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1536gm48.h index 72503bf29f..f2f193f1bd 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1536gm48.h @@ -4,7 +4,7 @@ * for EFR32MG24A110F1536GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a111f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a111f1536gm48.h index a79dc71f29..14926808fb 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a111f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a111f1536gm48.h @@ -4,7 +4,7 @@ * for EFR32MG24A111F1536GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a120f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a120f1536gm48.h index ac4d0bcec2..5db8244cf7 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a120f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a120f1536gm48.h @@ -4,7 +4,7 @@ * for EFR32MG24A120F1536GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a121f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a121f1536gm48.h index 9c9588d6fb..b1acdb661e 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a121f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a121f1536gm48.h @@ -4,7 +4,7 @@ * for EFR32MG24A121F1536GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im40.h index f479713648..7caff77a4e 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A410F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im48.h index 721e5e7934..0346516568 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24A410F1536IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im40.h index 3545a64dc0..c9e4856d8b 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A420F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im48.h index cced092193..6f2097e371 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24A420F1536IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a610f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a610f1536im40.h index 18a82b39c3..0caa35404e 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a610f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a610f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A610F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a620f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a620f1536im40.h index 6b870344fb..2e9758e73d 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a620f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a620f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24A620F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1024im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1024im48.h index 37811b2729..401c27492b 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1024im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B010F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im40.h index 66dbace78c..bbee8c7c93 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24B010F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im48.h index a182b39b7f..723903a710 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B010F1536IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1024im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1024im48.h index 30c82b8df0..34fbb3b851 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1024im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B020F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im40.h index bbb39e69f7..91d9b952ba 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24B020F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im48.h index f904163dcc..ccfd9e52ae 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B020F1536IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536gm48.h index 78466dcc87..f5f6d802a6 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536gm48.h @@ -4,7 +4,7 @@ * for EFR32MG24B110F1536GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536im48.h index ce8ea15120..b55815d558 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B110F1536IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b120f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b120f1536im48.h index 7c3bd30124..283403f503 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b120f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b120f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B120F1536IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im40.h index aac87fa79f..7a8dd10449 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24B210F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im48.h index b816d054f1..9fd83fd97f 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B210F1536IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h index 25a82af643..dc25051f0e 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B220F1536IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b310f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b310f1536im48.h index 41fcc86043..cdb5ad1669 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b310f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b310f1536im48.h @@ -4,7 +4,7 @@ * for EFR32MG24B310F1536IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b610f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b610f1536im40.h index bec92c1f36..b164f222b5 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b610f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b610f1536im40.h @@ -4,7 +4,7 @@ * for EFR32MG24B610F1536IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/em_device.h b/platform/Device/SiliconLabs/EFR32MG24/Include/em_device.h index 33f7652b26..ebcaeabe10 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/system_efr32mg24.h b/platform/Device/SiliconLabs/EFR32MG24/Include/system_efr32mg24.h index 12474398b1..c25f3d3cd3 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/system_efr32mg24.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/system_efr32mg24.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32MG24 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Source/GCC/efr32mg24.ld b/platform/Device/SiliconLabs/EFR32MG24/Source/GCC/efr32mg24.ld index 3bb689f093..a2f4b2f134 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Source/GCC/efr32mg24.ld +++ b/platform/Device/SiliconLabs/EFR32MG24/Source/GCC/efr32mg24.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs EFR32MG24 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG24/Source/IAR/startup_efr32mg24.s b/platform/Device/SiliconLabs/EFR32MG24/Source/IAR/startup_efr32mg24.s index 1e09e5132f..a82f24da96 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Source/IAR/startup_efr32mg24.s +++ b/platform/Device/SiliconLabs/EFR32MG24/Source/IAR/startup_efr32mg24.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c b/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c index 97b0f97eee..189af5bb55 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c +++ b/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32MG24 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_acmp.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_acmp.h index 2d0468056d..e1631d19ad 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_acmp.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_aes.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_aes.h index fe957f7b13..ac2b55adaf 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_aes.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_aes.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_buram.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_buram.h index dd4a68421d..64025412c1 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_buram.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_buram.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_burtc.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_burtc.h index 16c8929780..de81a5b130 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_burtc.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_cmu.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_cmu.h index 269f3417cb..0ad4304ebd 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_cmu.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_cryptoacc.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_cryptoacc.h index 6c036767bb..1c1a9f98d9 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_cryptoacc.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_cryptoacc.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 CRYPTOACC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dcdc.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dcdc.h index 10e46831c9..c97647642f 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_devinfo.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_devinfo.h index 57355a8d2d..8d6a3f408a 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dma_descriptor.h index 7c5cea321e..45c745a4be 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dpll.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dpll.h index c6e1ffa7c6..2dcffad727 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dpll.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_emu.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_emu.h index a2610c2993..c59707c56b 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_emu.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_emu.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_etampdet.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_etampdet.h index 71aff201e8..efe717f736 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_etampdet.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_etampdet.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 ETAMPDET register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_eusart.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_eusart.h index 885eb87f97..428e74704e 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_eusart.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_fsrco.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_fsrco.h index 97192c45ec..154fed7f73 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpcrc.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpcrc.h index 4f91dc9861..92fc1190de 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio.h index 031a2255bc..91d554cc02 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio_port.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio_port.h index 433625017e..bd4a01055d 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_hfrco.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_hfrco.h index de0c79a599..b51b4b7bd7 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_hfxo.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_hfxo.h index 332836934f..6b962ec17f 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_i2c.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_i2c.h index e2ab1fdf93..3cb1931c2c 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_i2c.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_iadc.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_iadc.h index 41abae4b5a..ec6403747e 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_iadc.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_icache.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_icache.h index a731f3d613..549c675687 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_icache.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_icache.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldma.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldma.h index 14f696aea9..3f85ed10a3 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldma.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar.h index c58dd035a0..6a1120b449 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar_defines.h index 5bb70dd448..4f3dcc829d 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_letimer.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_letimer.h index a775c25164..1691957c7c 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_letimer.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_lfrco.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_lfrco.h index 1aeb92e1fd..f709fd4e67 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_lfxo.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_lfxo.h index 0d6e21ca20..6447d5ba93 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_msc.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_msc.h index 9fcca7c5e2..30896048d5 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_msc.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_msc.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_pdm.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_pdm.h index 81cc4cca39..87a951f4f7 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_pdm.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_pdm.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs.h index caa69f70ab..02b9e2ba84 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs_signals.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs_signals.h index 12ea470a26..3a0b92aaae 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_rtcc.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_rtcc.h index a3bca32cde..bd790b1ad3 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_sepuf.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_sepuf.h index 037a031ee8..3e4b16e536 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_sepuf.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_sepuf.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 SEPUF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_smu.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_smu.h index 9d156c66d7..ea429bff25 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_smu.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_smu.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_syscfg.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_syscfg.h index 08f89782ee..56edc157ba 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_timer.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_timer.h index cb0934f1bc..4ce452377e 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_timer.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_timer.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ulfrco.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ulfrco.h index 1e9d670012..a07c6f4fbe 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_usart.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_usart.h index 87f42eb702..18335b4c54 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_usart.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_usart.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_wdog.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_wdog.h index ab16b2ae3a..8250228225 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_wdog.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32MG27 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im32.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im32.h index 174d611e04..2a455bbc49 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im32.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im32.h @@ -4,7 +4,7 @@ * for EFR32MG27C140F768IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im40.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im40.h index cc9afae831..88fd9c40ad 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im40.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im40.h @@ -4,7 +4,7 @@ * for EFR32MG27C140F768IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c230f768im32.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c230f768im32.h index 87bdb77286..40ddd500a9 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c230f768im32.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c230f768im32.h @@ -4,7 +4,7 @@ * for EFR32MG27C230F768IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c230f768im40.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c230f768im40.h index 150cde541c..06f3c21bd0 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c230f768im40.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c230f768im40.h @@ -4,7 +4,7 @@ * for EFR32MG27C230F768IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/em_device.h b/platform/Device/SiliconLabs/EFR32MG27/Include/em_device.h index c60f9345e6..5f3b12c4e6 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/system_efr32mg27.h b/platform/Device/SiliconLabs/EFR32MG27/Include/system_efr32mg27.h index 3077524676..03955e651f 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/system_efr32mg27.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/system_efr32mg27.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32MG27 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Source/GCC/efr32mg27.ld b/platform/Device/SiliconLabs/EFR32MG27/Source/GCC/efr32mg27.ld index 796c0a4e1e..b596599d3c 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Source/GCC/efr32mg27.ld +++ b/platform/Device/SiliconLabs/EFR32MG27/Source/GCC/efr32mg27.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs EFR32MG27 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MG27/Source/IAR/startup_efr32mg27.s b/platform/Device/SiliconLabs/EFR32MG27/Source/IAR/startup_efr32mg27.s index 2b315c70bc..28d11d3013 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Source/IAR/startup_efr32mg27.s +++ b/platform/Device/SiliconLabs/EFR32MG27/Source/IAR/startup_efr32mg27.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFR32MG27/Source/system_efr32mg27.c b/platform/Device/SiliconLabs/EFR32MG27/Source/system_efr32mg27.c index d9c1a1f03d..e3598a3e61 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Source/system_efr32mg27.c +++ b/platform/Device/SiliconLabs/EFR32MG27/Source/system_efr32mg27.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32MG27 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_aes.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_aes.h index be80041bd5..4df7e110ea 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_aes.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_aes.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_bufc.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_bufc.h index 69221b001b..4c5e30c820 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_bufc.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_bufc.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 BUFC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_buram.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_buram.h index aa41b493a8..f1a67a4ea4 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_buram.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_buram.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_burtc.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_burtc.h index 7e52e93e06..6a6e487fa7 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_burtc.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_cmu.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_cmu.h index 57a441aa0b..361a472f54 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_cmu.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_devinfo.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_devinfo.h index 0aa173946b..84d094c968 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dma_descriptor.h index 7e761bbea1..4679e2418a 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dpll.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dpll.h index 3983376ed6..da4583d404 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dpll.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_emu.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_emu.h index c0818aeff6..67243e0a40 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_emu.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_emu.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_fsrco.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_fsrco.h index 85267cd832..6ab97fb9a9 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpcrc.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpcrc.h index 19c6b2ac2e..d656ad4e27 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpio.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpio.h index c254a51d79..f680efbbd9 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpio.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpio_port.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpio_port.h index ae53514bcf..435793af22 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_hfrco.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_hfrco.h index ff3fff6ddc..e98cd61350 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_hfxo.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_hfxo.h index cae3d94286..7a4bfd9251 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_icache.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_icache.h index 29e4c0a88b..c58bb649e6 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_icache.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_icache.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldma.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldma.h index 68bcf2fd28..37d372f608 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldma.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar.h index 8fdf266663..35e7cb04eb 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar_defines.h index 5f8d1ee05c..d707d0c250 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_letimer.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_letimer.h index f1a2805645..846b356f01 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_letimer.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lfrco.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lfrco.h index d3f29492e3..2d8409e67e 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lfxo.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lfxo.h index c5377eda4e..11e8d9ccb6 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lvgd.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lvgd.h index 40634e30d8..3daec852a6 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lvgd.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_lvgd.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 LVGD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_msc.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_msc.h index e07905e564..9ec710da29 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_msc.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_msc.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs.h index 72815b7dca..1e1f05e564 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs_signals.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs_signals.h index d28392a77a..0be72cf4c3 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_rtcc.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_rtcc.h index baf1408931..423fef50c4 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_rtcc.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_rtcc.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_semailbox.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_semailbox.h index d9898d9019..7466b2ec66 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_smu.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_smu.h index 7907389993..86652cb0dc 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_smu.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_smu.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_syscfg.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_syscfg.h index 9103d541b8..842114a5ae 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_timer.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_timer.h index 7169667176..aaaee4f24b 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_timer.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_timer.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ulfrco.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ulfrco.h index d4c6eb0f90..897ba633da 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_usart.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_usart.h index c7997b3326..ba196f8414 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_usart.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_usart.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_wdog.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_wdog.h index e3c4a116e8..a061e06ef4 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_wdog.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32MR21 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21a020f512im32.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21a020f512im32.h index 78c26744fe..159898caa6 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21a020f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21a020f512im32.h @@ -4,7 +4,7 @@ * for EFR32MR21A020F512IM32 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/em_device.h b/platform/Device/SiliconLabs/EFR32MR21/Include/em_device.h index f6c3e5d26a..7378e038ea 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/system_efr32mr21.h b/platform/Device/SiliconLabs/EFR32MR21/Include/system_efr32mr21.h index fcff4dd8bd..0bac0832e3 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/system_efr32mr21.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/system_efr32mr21.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32MR21 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Source/GCC/efr32mr21.ld b/platform/Device/SiliconLabs/EFR32MR21/Source/GCC/efr32mr21.ld index 53b1436c28..510c565bbc 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Source/GCC/efr32mr21.ld +++ b/platform/Device/SiliconLabs/EFR32MR21/Source/GCC/efr32mr21.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs EFR32MR21 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32MR21/Source/IAR/startup_efr32mr21.s b/platform/Device/SiliconLabs/EFR32MR21/Source/IAR/startup_efr32mr21.s index 43e4adf1ad..d4d4497b07 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Source/IAR/startup_efr32mr21.s +++ b/platform/Device/SiliconLabs/EFR32MR21/Source/IAR/startup_efr32mr21.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFR32MR21/Source/system_efr32mr21.c b/platform/Device/SiliconLabs/EFR32MR21/Source/system_efr32mr21.c index cc611d1afd..99ab4e5f32 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Source/system_efr32mr21.c +++ b/platform/Device/SiliconLabs/EFR32MR21/Source/system_efr32mr21.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32MR21 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_acmp.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_acmp.h index 958e4f14bc..d9ef4a9cd6 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_acmp.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_acmp.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_ACMP_H #define EFR32SG23_ACMP_H - #define ACMP_HAS_SET_CLEAR /**************************************************************************//** @@ -43,51 +42,50 @@ *****************************************************************************/ /** ACMP Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t EN; /**< ACMP enable */ - __IOM uint32_t SWRST; /**< Software reset */ - __IOM uint32_t CFG; /**< Configuration register */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t INPUTCTRL; /**< Input Control Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY; /**< Syncbusy */ - uint32_t RESERVED0[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t EN_SET; /**< ACMP enable */ - __IOM uint32_t SWRST_SET; /**< Software reset */ - __IOM uint32_t CFG_SET; /**< Configuration register */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t INPUTCTRL_SET; /**< Input Control Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_SET; /**< Syncbusy */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t EN_CLR; /**< ACMP enable */ - __IOM uint32_t SWRST_CLR; /**< Software reset */ - __IOM uint32_t CFG_CLR; /**< Configuration register */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t INPUTCTRL_CLR; /**< Input Control Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy */ - uint32_t RESERVED2[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t EN_TGL; /**< ACMP enable */ - __IOM uint32_t SWRST_TGL; /**< Software reset */ - __IOM uint32_t CFG_TGL; /**< Configuration register */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t INPUTCTRL_TGL; /**< Input Control Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< ACMP enable */ + __IOM uint32_t SWRST; /**< Software reset */ + __IOM uint32_t CFG; /**< Configuration register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t INPUTCTRL; /**< Input Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Syncbusy */ + uint32_t RESERVED0[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< ACMP enable */ + __IOM uint32_t SWRST_SET; /**< Software reset */ + __IOM uint32_t CFG_SET; /**< Configuration register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t INPUTCTRL_SET; /**< Input Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Syncbusy */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< ACMP enable */ + __IOM uint32_t SWRST_CLR; /**< Software reset */ + __IOM uint32_t CFG_CLR; /**< Configuration register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t INPUTCTRL_CLR; /**< Input Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy */ + uint32_t RESERVED2[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< ACMP enable */ + __IOM uint32_t SWRST_TGL; /**< Software reset */ + __IOM uint32_t CFG_TGL; /**< Configuration register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t INPUTCTRL_TGL; /**< Input Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy */ } ACMP_TypeDef; /** @} End of group EFR32SG23_ACMP */ @@ -99,555 +97,555 @@ typedef struct *****************************************************************************/ /* Bit fields for ACMP IPVERSION */ -#define _ACMP_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ACMP_IPVERSION */ -#define _ACMP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ACMP_IPVERSION */ -#define _ACMP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ACMP_IPVERSION */ -#define _ACMP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ACMP_IPVERSION */ -#define _ACMP_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_IPVERSION */ -#define ACMP_IPVERSION_IPVERSION_DEFAULT (_ACMP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_IPVERSION */ +#define ACMP_IPVERSION_IPVERSION_DEFAULT (_ACMP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IPVERSION */ /* Bit fields for ACMP EN */ -#define _ACMP_EN_RESETVALUE 0x00000000UL /**< Default value for ACMP_EN */ -#define _ACMP_EN_MASK 0x00000003UL /**< Mask for ACMP_EN */ -#define ACMP_EN_EN (0x1UL << 0) /**< Module enable */ -#define _ACMP_EN_EN_SHIFT 0 /**< Shift value for ACMP_EN */ -#define _ACMP_EN_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ -#define _ACMP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ -#define ACMP_EN_EN_DEFAULT (_ACMP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EN */ -#define ACMP_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _ACMP_EN_DISABLING_SHIFT 1 /**< Shift value for ACMP_DISABLING */ -#define _ACMP_EN_DISABLING_MASK 0x2UL /**< Bit mask for ACMP_DISABLING */ -#define _ACMP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ -#define ACMP_EN_DISABLING_DEFAULT (_ACMP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_EN */ +#define _ACMP_EN_RESETVALUE 0x00000000UL /**< Default value for ACMP_EN */ +#define _ACMP_EN_MASK 0x00000003UL /**< Mask for ACMP_EN */ +#define ACMP_EN_EN (0x1UL << 0) /**< Module enable */ +#define _ACMP_EN_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_EN_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ +#define ACMP_EN_EN_DEFAULT (_ACMP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EN */ +#define ACMP_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _ACMP_EN_DISABLING_SHIFT 1 /**< Shift value for ACMP_DISABLING */ +#define _ACMP_EN_DISABLING_MASK 0x2UL /**< Bit mask for ACMP_DISABLING */ +#define _ACMP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ +#define ACMP_EN_DISABLING_DEFAULT (_ACMP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_EN */ /* Bit fields for ACMP SWRST */ -#define _ACMP_SWRST_RESETVALUE 0x00000000UL /**< Default value for ACMP_SWRST */ -#define _ACMP_SWRST_MASK 0x00000003UL /**< Mask for ACMP_SWRST */ -#define ACMP_SWRST_SWRST (0x1UL << 0) /**< Software reset */ -#define _ACMP_SWRST_SWRST_SHIFT 0 /**< Shift value for ACMP_SWRST */ -#define _ACMP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for ACMP_SWRST */ -#define _ACMP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ -#define ACMP_SWRST_SWRST_DEFAULT (_ACMP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SWRST */ -#define ACMP_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ -#define _ACMP_SWRST_RESETTING_SHIFT 1 /**< Shift value for ACMP_RESETTING */ -#define _ACMP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for ACMP_RESETTING */ -#define _ACMP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ -#define ACMP_SWRST_RESETTING_DEFAULT (_ACMP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_SWRST */ +#define _ACMP_SWRST_RESETVALUE 0x00000000UL /**< Default value for ACMP_SWRST */ +#define _ACMP_SWRST_MASK 0x00000003UL /**< Mask for ACMP_SWRST */ +#define ACMP_SWRST_SWRST (0x1UL << 0) /**< Software reset */ +#define _ACMP_SWRST_SWRST_SHIFT 0 /**< Shift value for ACMP_SWRST */ +#define _ACMP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for ACMP_SWRST */ +#define _ACMP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_SWRST_DEFAULT (_ACMP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _ACMP_SWRST_RESETTING_SHIFT 1 /**< Shift value for ACMP_RESETTING */ +#define _ACMP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for ACMP_RESETTING */ +#define _ACMP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_RESETTING_DEFAULT (_ACMP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_SWRST */ /* Bit fields for ACMP CFG */ -#define _ACMP_CFG_RESETVALUE 0x00000004UL /**< Default value for ACMP_CFG */ -#define _ACMP_CFG_MASK 0x00030F07UL /**< Mask for ACMP_CFG */ -#define _ACMP_CFG_BIAS_SHIFT 0 /**< Shift value for ACMP_BIAS */ -#define _ACMP_CFG_BIAS_MASK 0x7UL /**< Bit mask for ACMP_BIAS */ -#define _ACMP_CFG_BIAS_DEFAULT 0x00000004UL /**< Mode DEFAULT for ACMP_CFG */ -#define ACMP_CFG_BIAS_DEFAULT (_ACMP_CFG_BIAS_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CFG */ -#define _ACMP_CFG_HYST_SHIFT 8 /**< Shift value for ACMP_HYST */ -#define _ACMP_CFG_HYST_MASK 0xF00UL /**< Bit mask for ACMP_HYST */ -#define _ACMP_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ -#define _ACMP_CFG_HYST_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CFG */ -#define _ACMP_CFG_HYST_SYM10MV 0x00000001UL /**< Mode SYM10MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_SYM20MV 0x00000002UL /**< Mode SYM20MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_SYM30MV 0x00000003UL /**< Mode SYM30MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_POS10MV 0x00000004UL /**< Mode POS10MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_POS20MV 0x00000005UL /**< Mode POS20MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_POS30MV 0x00000006UL /**< Mode POS30MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_NEG10MV 0x00000008UL /**< Mode NEG10MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_NEG20MV 0x00000009UL /**< Mode NEG20MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_NEG30MV 0x0000000AUL /**< Mode NEG30MV for ACMP_CFG */ -#define ACMP_CFG_HYST_DEFAULT (_ACMP_CFG_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CFG */ -#define ACMP_CFG_HYST_DISABLED (_ACMP_CFG_HYST_DISABLED << 8) /**< Shifted mode DISABLED for ACMP_CFG */ -#define ACMP_CFG_HYST_SYM10MV (_ACMP_CFG_HYST_SYM10MV << 8) /**< Shifted mode SYM10MV for ACMP_CFG */ -#define ACMP_CFG_HYST_SYM20MV (_ACMP_CFG_HYST_SYM20MV << 8) /**< Shifted mode SYM20MV for ACMP_CFG */ -#define ACMP_CFG_HYST_SYM30MV (_ACMP_CFG_HYST_SYM30MV << 8) /**< Shifted mode SYM30MV for ACMP_CFG */ -#define ACMP_CFG_HYST_POS10MV (_ACMP_CFG_HYST_POS10MV << 8) /**< Shifted mode POS10MV for ACMP_CFG */ -#define ACMP_CFG_HYST_POS20MV (_ACMP_CFG_HYST_POS20MV << 8) /**< Shifted mode POS20MV for ACMP_CFG */ -#define ACMP_CFG_HYST_POS30MV (_ACMP_CFG_HYST_POS30MV << 8) /**< Shifted mode POS30MV for ACMP_CFG */ -#define ACMP_CFG_HYST_NEG10MV (_ACMP_CFG_HYST_NEG10MV << 8) /**< Shifted mode NEG10MV for ACMP_CFG */ -#define ACMP_CFG_HYST_NEG20MV (_ACMP_CFG_HYST_NEG20MV << 8) /**< Shifted mode NEG20MV for ACMP_CFG */ -#define ACMP_CFG_HYST_NEG30MV (_ACMP_CFG_HYST_NEG30MV << 8) /**< Shifted mode NEG30MV for ACMP_CFG */ -#define ACMP_CFG_INPUTRANGE (0x1UL << 16) /**< Input Range */ -#define _ACMP_CFG_INPUTRANGE_SHIFT 16 /**< Shift value for ACMP_INPUTRANGE */ -#define _ACMP_CFG_INPUTRANGE_MASK 0x10000UL /**< Bit mask for ACMP_INPUTRANGE */ -#define _ACMP_CFG_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ -#define _ACMP_CFG_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CFG */ -#define _ACMP_CFG_INPUTRANGE_REDUCED 0x00000001UL /**< Mode REDUCED for ACMP_CFG */ -#define ACMP_CFG_INPUTRANGE_DEFAULT (_ACMP_CFG_INPUTRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CFG */ -#define ACMP_CFG_INPUTRANGE_FULL (_ACMP_CFG_INPUTRANGE_FULL << 16) /**< Shifted mode FULL for ACMP_CFG */ -#define ACMP_CFG_INPUTRANGE_REDUCED (_ACMP_CFG_INPUTRANGE_REDUCED << 16) /**< Shifted mode REDUCED for ACMP_CFG */ -#define ACMP_CFG_ACCURACY (0x1UL << 17) /**< ACMP accuracy mode */ -#define _ACMP_CFG_ACCURACY_SHIFT 17 /**< Shift value for ACMP_ACCURACY */ -#define _ACMP_CFG_ACCURACY_MASK 0x20000UL /**< Bit mask for ACMP_ACCURACY */ -#define _ACMP_CFG_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ -#define _ACMP_CFG_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CFG */ -#define _ACMP_CFG_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CFG */ -#define ACMP_CFG_ACCURACY_DEFAULT (_ACMP_CFG_ACCURACY_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CFG */ -#define ACMP_CFG_ACCURACY_LOW (_ACMP_CFG_ACCURACY_LOW << 17) /**< Shifted mode LOW for ACMP_CFG */ -#define ACMP_CFG_ACCURACY_HIGH (_ACMP_CFG_ACCURACY_HIGH << 17) /**< Shifted mode HIGH for ACMP_CFG */ +#define _ACMP_CFG_RESETVALUE 0x00000004UL /**< Default value for ACMP_CFG */ +#define _ACMP_CFG_MASK 0x00030F07UL /**< Mask for ACMP_CFG */ +#define _ACMP_CFG_BIAS_SHIFT 0 /**< Shift value for ACMP_BIAS */ +#define _ACMP_CFG_BIAS_MASK 0x7UL /**< Bit mask for ACMP_BIAS */ +#define _ACMP_CFG_BIAS_DEFAULT 0x00000004UL /**< Mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_BIAS_DEFAULT (_ACMP_CFG_BIAS_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_HYST_SHIFT 8 /**< Shift value for ACMP_HYST */ +#define _ACMP_CFG_HYST_MASK 0xF00UL /**< Bit mask for ACMP_HYST */ +#define _ACMP_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_HYST_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM10MV 0x00000001UL /**< Mode SYM10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM20MV 0x00000002UL /**< Mode SYM20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM30MV 0x00000003UL /**< Mode SYM30MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS10MV 0x00000004UL /**< Mode POS10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS20MV 0x00000005UL /**< Mode POS20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS30MV 0x00000006UL /**< Mode POS30MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG10MV 0x00000008UL /**< Mode NEG10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG20MV 0x00000009UL /**< Mode NEG20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG30MV 0x0000000AUL /**< Mode NEG30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_DEFAULT (_ACMP_CFG_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_HYST_DISABLED (_ACMP_CFG_HYST_DISABLED << 8) /**< Shifted mode DISABLED for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM10MV (_ACMP_CFG_HYST_SYM10MV << 8) /**< Shifted mode SYM10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM20MV (_ACMP_CFG_HYST_SYM20MV << 8) /**< Shifted mode SYM20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM30MV (_ACMP_CFG_HYST_SYM30MV << 8) /**< Shifted mode SYM30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS10MV (_ACMP_CFG_HYST_POS10MV << 8) /**< Shifted mode POS10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS20MV (_ACMP_CFG_HYST_POS20MV << 8) /**< Shifted mode POS20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS30MV (_ACMP_CFG_HYST_POS30MV << 8) /**< Shifted mode POS30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG10MV (_ACMP_CFG_HYST_NEG10MV << 8) /**< Shifted mode NEG10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG20MV (_ACMP_CFG_HYST_NEG20MV << 8) /**< Shifted mode NEG20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG30MV (_ACMP_CFG_HYST_NEG30MV << 8) /**< Shifted mode NEG30MV for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE (0x1UL << 16) /**< Input Range */ +#define _ACMP_CFG_INPUTRANGE_SHIFT 16 /**< Shift value for ACMP_INPUTRANGE */ +#define _ACMP_CFG_INPUTRANGE_MASK 0x10000UL /**< Bit mask for ACMP_INPUTRANGE */ +#define _ACMP_CFG_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CFG */ +#define _ACMP_CFG_INPUTRANGE_REDUCED 0x00000001UL /**< Mode REDUCED for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_DEFAULT (_ACMP_CFG_INPUTRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_FULL (_ACMP_CFG_INPUTRANGE_FULL << 16) /**< Shifted mode FULL for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_REDUCED (_ACMP_CFG_INPUTRANGE_REDUCED << 16) /**< Shifted mode REDUCED for ACMP_CFG */ +#define ACMP_CFG_ACCURACY (0x1UL << 17) /**< ACMP accuracy mode */ +#define _ACMP_CFG_ACCURACY_SHIFT 17 /**< Shift value for ACMP_ACCURACY */ +#define _ACMP_CFG_ACCURACY_MASK 0x20000UL /**< Bit mask for ACMP_ACCURACY */ +#define _ACMP_CFG_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CFG */ +#define _ACMP_CFG_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_DEFAULT (_ACMP_CFG_ACCURACY_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_LOW (_ACMP_CFG_ACCURACY_LOW << 17) /**< Shifted mode LOW for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_HIGH (_ACMP_CFG_ACCURACY_HIGH << 17) /**< Shifted mode HIGH for ACMP_CFG */ /* Bit fields for ACMP CTRL */ -#define _ACMP_CTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_CTRL */ -#define _ACMP_CTRL_MASK 0x00000003UL /**< Mask for ACMP_CTRL */ -#define ACMP_CTRL_NOTRDYVAL (0x1UL << 0) /**< Not Ready Value */ -#define _ACMP_CTRL_NOTRDYVAL_SHIFT 0 /**< Shift value for ACMP_NOTRDYVAL */ -#define _ACMP_CTRL_NOTRDYVAL_MASK 0x1UL /**< Bit mask for ACMP_NOTRDYVAL */ -#define _ACMP_CTRL_NOTRDYVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ -#define _ACMP_CTRL_NOTRDYVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ -#define _ACMP_CTRL_NOTRDYVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ -#define ACMP_CTRL_NOTRDYVAL_DEFAULT (_ACMP_CTRL_NOTRDYVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ -#define ACMP_CTRL_NOTRDYVAL_LOW (_ACMP_CTRL_NOTRDYVAL_LOW << 0) /**< Shifted mode LOW for ACMP_CTRL */ -#define ACMP_CTRL_NOTRDYVAL_HIGH (_ACMP_CTRL_NOTRDYVAL_HIGH << 0) /**< Shifted mode HIGH for ACMP_CTRL */ -#define ACMP_CTRL_GPIOINV (0x1UL << 1) /**< Comparator GPIO Output Invert */ -#define _ACMP_CTRL_GPIOINV_SHIFT 1 /**< Shift value for ACMP_GPIOINV */ -#define _ACMP_CTRL_GPIOINV_MASK 0x2UL /**< Bit mask for ACMP_GPIOINV */ -#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ -#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ -#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ -#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */ -#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 1) /**< Shifted mode NOTINV for ACMP_CTRL */ -#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 1) /**< Shifted mode INV for ACMP_CTRL */ +#define _ACMP_CTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_CTRL */ +#define _ACMP_CTRL_MASK 0x00000003UL /**< Mask for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL (0x1UL << 0) /**< Not Ready Value */ +#define _ACMP_CTRL_NOTRDYVAL_SHIFT 0 /**< Shift value for ACMP_NOTRDYVAL */ +#define _ACMP_CTRL_NOTRDYVAL_MASK 0x1UL /**< Bit mask for ACMP_NOTRDYVAL */ +#define _ACMP_CTRL_NOTRDYVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_NOTRDYVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_NOTRDYVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_DEFAULT (_ACMP_CTRL_NOTRDYVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_LOW (_ACMP_CTRL_NOTRDYVAL_LOW << 0) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_HIGH (_ACMP_CTRL_NOTRDYVAL_HIGH << 0) /**< Shifted mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV (0x1UL << 1) /**< Comparator GPIO Output Invert */ +#define _ACMP_CTRL_GPIOINV_SHIFT 1 /**< Shift value for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_MASK 0x2UL /**< Bit mask for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 1) /**< Shifted mode NOTINV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 1) /**< Shifted mode INV for ACMP_CTRL */ /* Bit fields for ACMP INPUTCTRL */ -#define _ACMP_INPUTCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_MASK 0x703FFFFFUL /**< Mask for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ -#define _ACMP_INPUTCTRL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */ -#define _ACMP_INPUTCTRL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VDACOUT0 0x00000040UL /**< Mode VDACOUT0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VDACOUT1 0x00000041UL /**< Mode VDACOUT1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_EXTPA 0x00000050UL /**< Mode EXTPA for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_EXTPB 0x00000051UL /**< Mode EXTPB for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_EXTPC 0x00000052UL /**< Mode EXTPC for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_EXTPD 0x00000053UL /**< Mode EXTPD for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_DEFAULT (_ACMP_INPUTCTRL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VSS (_ACMP_INPUTCTRL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD << 0) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP << 0) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 << 0) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP << 0) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 << 0) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP << 0) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 << 0) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP << 0) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 << 0) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP << 0) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VDACOUT0 (_ACMP_INPUTCTRL_POSSEL_VDACOUT0 << 0) /**< Shifted mode VDACOUT0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VDACOUT1 (_ACMP_INPUTCTRL_POSSEL_VDACOUT1 << 0) /**< Shifted mode VDACOUT1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_EXTPA (_ACMP_INPUTCTRL_POSSEL_EXTPA << 0) /**< Shifted mode EXTPA for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_EXTPB (_ACMP_INPUTCTRL_POSSEL_EXTPB << 0) /**< Shifted mode EXTPB for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_EXTPC (_ACMP_INPUTCTRL_POSSEL_EXTPC << 0) /**< Shifted mode EXTPC for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_EXTPD (_ACMP_INPUTCTRL_POSSEL_EXTPD << 0) /**< Shifted mode EXTPD for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA0 (_ACMP_INPUTCTRL_POSSEL_PA0 << 0) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA1 (_ACMP_INPUTCTRL_POSSEL_PA1 << 0) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA2 (_ACMP_INPUTCTRL_POSSEL_PA2 << 0) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA3 (_ACMP_INPUTCTRL_POSSEL_PA3 << 0) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA4 (_ACMP_INPUTCTRL_POSSEL_PA4 << 0) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA5 (_ACMP_INPUTCTRL_POSSEL_PA5 << 0) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA6 (_ACMP_INPUTCTRL_POSSEL_PA6 << 0) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA7 (_ACMP_INPUTCTRL_POSSEL_PA7 << 0) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA8 (_ACMP_INPUTCTRL_POSSEL_PA8 << 0) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA9 (_ACMP_INPUTCTRL_POSSEL_PA9 << 0) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA10 (_ACMP_INPUTCTRL_POSSEL_PA10 << 0) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA11 (_ACMP_INPUTCTRL_POSSEL_PA11 << 0) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA12 (_ACMP_INPUTCTRL_POSSEL_PA12 << 0) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA13 (_ACMP_INPUTCTRL_POSSEL_PA13 << 0) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA14 (_ACMP_INPUTCTRL_POSSEL_PA14 << 0) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA15 (_ACMP_INPUTCTRL_POSSEL_PA15 << 0) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB0 (_ACMP_INPUTCTRL_POSSEL_PB0 << 0) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB1 (_ACMP_INPUTCTRL_POSSEL_PB1 << 0) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB2 (_ACMP_INPUTCTRL_POSSEL_PB2 << 0) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB3 (_ACMP_INPUTCTRL_POSSEL_PB3 << 0) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB4 (_ACMP_INPUTCTRL_POSSEL_PB4 << 0) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB5 (_ACMP_INPUTCTRL_POSSEL_PB5 << 0) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB6 (_ACMP_INPUTCTRL_POSSEL_PB6 << 0) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB7 (_ACMP_INPUTCTRL_POSSEL_PB7 << 0) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB8 (_ACMP_INPUTCTRL_POSSEL_PB8 << 0) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB9 (_ACMP_INPUTCTRL_POSSEL_PB9 << 0) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB10 (_ACMP_INPUTCTRL_POSSEL_PB10 << 0) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB11 (_ACMP_INPUTCTRL_POSSEL_PB11 << 0) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB12 (_ACMP_INPUTCTRL_POSSEL_PB12 << 0) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB13 (_ACMP_INPUTCTRL_POSSEL_PB13 << 0) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB14 (_ACMP_INPUTCTRL_POSSEL_PB14 << 0) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB15 (_ACMP_INPUTCTRL_POSSEL_PB15 << 0) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC0 (_ACMP_INPUTCTRL_POSSEL_PC0 << 0) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC1 (_ACMP_INPUTCTRL_POSSEL_PC1 << 0) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC2 (_ACMP_INPUTCTRL_POSSEL_PC2 << 0) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC3 (_ACMP_INPUTCTRL_POSSEL_PC3 << 0) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC4 (_ACMP_INPUTCTRL_POSSEL_PC4 << 0) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC5 (_ACMP_INPUTCTRL_POSSEL_PC5 << 0) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC6 (_ACMP_INPUTCTRL_POSSEL_PC6 << 0) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC7 (_ACMP_INPUTCTRL_POSSEL_PC7 << 0) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC8 (_ACMP_INPUTCTRL_POSSEL_PC8 << 0) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC9 (_ACMP_INPUTCTRL_POSSEL_PC9 << 0) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC10 (_ACMP_INPUTCTRL_POSSEL_PC10 << 0) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC11 (_ACMP_INPUTCTRL_POSSEL_PC11 << 0) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC12 (_ACMP_INPUTCTRL_POSSEL_PC12 << 0) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC13 (_ACMP_INPUTCTRL_POSSEL_PC13 << 0) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC14 (_ACMP_INPUTCTRL_POSSEL_PC14 << 0) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC15 (_ACMP_INPUTCTRL_POSSEL_PC15 << 0) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD0 (_ACMP_INPUTCTRL_POSSEL_PD0 << 0) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD1 (_ACMP_INPUTCTRL_POSSEL_PD1 << 0) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD2 (_ACMP_INPUTCTRL_POSSEL_PD2 << 0) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD3 (_ACMP_INPUTCTRL_POSSEL_PD3 << 0) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD4 (_ACMP_INPUTCTRL_POSSEL_PD4 << 0) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD5 (_ACMP_INPUTCTRL_POSSEL_PD5 << 0) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD6 (_ACMP_INPUTCTRL_POSSEL_PD6 << 0) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD7 (_ACMP_INPUTCTRL_POSSEL_PD7 << 0) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD8 (_ACMP_INPUTCTRL_POSSEL_PD8 << 0) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD9 (_ACMP_INPUTCTRL_POSSEL_PD9 << 0) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD10 (_ACMP_INPUTCTRL_POSSEL_PD10 << 0) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD11 (_ACMP_INPUTCTRL_POSSEL_PD11 << 0) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD12 (_ACMP_INPUTCTRL_POSSEL_PD12 << 0) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD13 (_ACMP_INPUTCTRL_POSSEL_PD13 << 0) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD14 (_ACMP_INPUTCTRL_POSSEL_PD14 << 0) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD15 (_ACMP_INPUTCTRL_POSSEL_PD15 << 0) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */ -#define _ACMP_INPUTCTRL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */ -#define _ACMP_INPUTCTRL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_CAPSENSE 0x00000030UL /**< Mode CAPSENSE for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VDACOUT0 0x00000040UL /**< Mode VDACOUT0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VDACOUT1 0x00000041UL /**< Mode VDACOUT1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_DEFAULT (_ACMP_INPUTCTRL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VSS (_ACMP_INPUTCTRL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD << 8) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP << 8) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 << 8) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP << 8) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 << 8) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP << 8) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 << 8) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP << 8) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 << 8) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP << 8) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_CAPSENSE (_ACMP_INPUTCTRL_NEGSEL_CAPSENSE << 8) /**< Shifted mode CAPSENSE for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VDACOUT0 (_ACMP_INPUTCTRL_NEGSEL_VDACOUT0 << 8) /**< Shifted mode VDACOUT0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VDACOUT1 (_ACMP_INPUTCTRL_NEGSEL_VDACOUT1 << 8) /**< Shifted mode VDACOUT1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA0 (_ACMP_INPUTCTRL_NEGSEL_PA0 << 8) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA1 (_ACMP_INPUTCTRL_NEGSEL_PA1 << 8) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA2 (_ACMP_INPUTCTRL_NEGSEL_PA2 << 8) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA3 (_ACMP_INPUTCTRL_NEGSEL_PA3 << 8) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA4 (_ACMP_INPUTCTRL_NEGSEL_PA4 << 8) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA5 (_ACMP_INPUTCTRL_NEGSEL_PA5 << 8) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA6 (_ACMP_INPUTCTRL_NEGSEL_PA6 << 8) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA7 (_ACMP_INPUTCTRL_NEGSEL_PA7 << 8) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA8 (_ACMP_INPUTCTRL_NEGSEL_PA8 << 8) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA9 (_ACMP_INPUTCTRL_NEGSEL_PA9 << 8) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA10 (_ACMP_INPUTCTRL_NEGSEL_PA10 << 8) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA11 (_ACMP_INPUTCTRL_NEGSEL_PA11 << 8) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA12 (_ACMP_INPUTCTRL_NEGSEL_PA12 << 8) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA13 (_ACMP_INPUTCTRL_NEGSEL_PA13 << 8) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA14 (_ACMP_INPUTCTRL_NEGSEL_PA14 << 8) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA15 (_ACMP_INPUTCTRL_NEGSEL_PA15 << 8) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB0 (_ACMP_INPUTCTRL_NEGSEL_PB0 << 8) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB1 (_ACMP_INPUTCTRL_NEGSEL_PB1 << 8) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB2 (_ACMP_INPUTCTRL_NEGSEL_PB2 << 8) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB3 (_ACMP_INPUTCTRL_NEGSEL_PB3 << 8) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB4 (_ACMP_INPUTCTRL_NEGSEL_PB4 << 8) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB5 (_ACMP_INPUTCTRL_NEGSEL_PB5 << 8) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB6 (_ACMP_INPUTCTRL_NEGSEL_PB6 << 8) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB7 (_ACMP_INPUTCTRL_NEGSEL_PB7 << 8) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB8 (_ACMP_INPUTCTRL_NEGSEL_PB8 << 8) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB9 (_ACMP_INPUTCTRL_NEGSEL_PB9 << 8) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB10 (_ACMP_INPUTCTRL_NEGSEL_PB10 << 8) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB11 (_ACMP_INPUTCTRL_NEGSEL_PB11 << 8) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB12 (_ACMP_INPUTCTRL_NEGSEL_PB12 << 8) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB13 (_ACMP_INPUTCTRL_NEGSEL_PB13 << 8) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB14 (_ACMP_INPUTCTRL_NEGSEL_PB14 << 8) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB15 (_ACMP_INPUTCTRL_NEGSEL_PB15 << 8) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC0 (_ACMP_INPUTCTRL_NEGSEL_PC0 << 8) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC1 (_ACMP_INPUTCTRL_NEGSEL_PC1 << 8) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC2 (_ACMP_INPUTCTRL_NEGSEL_PC2 << 8) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC3 (_ACMP_INPUTCTRL_NEGSEL_PC3 << 8) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC4 (_ACMP_INPUTCTRL_NEGSEL_PC4 << 8) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC5 (_ACMP_INPUTCTRL_NEGSEL_PC5 << 8) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC6 (_ACMP_INPUTCTRL_NEGSEL_PC6 << 8) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC7 (_ACMP_INPUTCTRL_NEGSEL_PC7 << 8) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC8 (_ACMP_INPUTCTRL_NEGSEL_PC8 << 8) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC9 (_ACMP_INPUTCTRL_NEGSEL_PC9 << 8) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC10 (_ACMP_INPUTCTRL_NEGSEL_PC10 << 8) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC11 (_ACMP_INPUTCTRL_NEGSEL_PC11 << 8) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC12 (_ACMP_INPUTCTRL_NEGSEL_PC12 << 8) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC13 (_ACMP_INPUTCTRL_NEGSEL_PC13 << 8) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC14 (_ACMP_INPUTCTRL_NEGSEL_PC14 << 8) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC15 (_ACMP_INPUTCTRL_NEGSEL_PC15 << 8) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD0 (_ACMP_INPUTCTRL_NEGSEL_PD0 << 8) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD1 (_ACMP_INPUTCTRL_NEGSEL_PD1 << 8) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD2 (_ACMP_INPUTCTRL_NEGSEL_PD2 << 8) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD3 (_ACMP_INPUTCTRL_NEGSEL_PD3 << 8) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD4 (_ACMP_INPUTCTRL_NEGSEL_PD4 << 8) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD5 (_ACMP_INPUTCTRL_NEGSEL_PD5 << 8) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD6 (_ACMP_INPUTCTRL_NEGSEL_PD6 << 8) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD7 (_ACMP_INPUTCTRL_NEGSEL_PD7 << 8) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD8 (_ACMP_INPUTCTRL_NEGSEL_PD8 << 8) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD9 (_ACMP_INPUTCTRL_NEGSEL_PD9 << 8) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD10 (_ACMP_INPUTCTRL_NEGSEL_PD10 << 8) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD11 (_ACMP_INPUTCTRL_NEGSEL_PD11 << 8) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD12 (_ACMP_INPUTCTRL_NEGSEL_PD12 << 8) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD13 (_ACMP_INPUTCTRL_NEGSEL_PD13 << 8) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD14 (_ACMP_INPUTCTRL_NEGSEL_PD14 << 8) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD15 (_ACMP_INPUTCTRL_NEGSEL_PD15 << 8) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_VREFDIV_SHIFT 16 /**< Shift value for ACMP_VREFDIV */ -#define _ACMP_INPUTCTRL_VREFDIV_MASK 0x3F0000UL /**< Bit mask for ACMP_VREFDIV */ -#define _ACMP_INPUTCTRL_VREFDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_VREFDIV_DEFAULT (_ACMP_INPUTCTRL_VREFDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ -#define _ACMP_INPUTCTRL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */ -#define _ACMP_INPUTCTRL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_DEFAULT (_ACMP_INPUTCTRL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES0 (_ACMP_INPUTCTRL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES1 (_ACMP_INPUTCTRL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES2 (_ACMP_INPUTCTRL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES3 (_ACMP_INPUTCTRL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES4 (_ACMP_INPUTCTRL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES5 (_ACMP_INPUTCTRL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES6 (_ACMP_INPUTCTRL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_MASK 0x703FFFFFUL /**< Mask for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ +#define _ACMP_INPUTCTRL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */ +#define _ACMP_INPUTCTRL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VDACOUT0 0x00000040UL /**< Mode VDACOUT0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VDACOUT1 0x00000041UL /**< Mode VDACOUT1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPA 0x00000050UL /**< Mode EXTPA for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPB 0x00000051UL /**< Mode EXTPB for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPC 0x00000052UL /**< Mode EXTPC for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPD 0x00000053UL /**< Mode EXTPD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_DEFAULT (_ACMP_INPUTCTRL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VSS (_ACMP_INPUTCTRL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD << 0) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP << 0) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 << 0) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP << 0) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 << 0) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP << 0) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 << 0) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP << 0) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 << 0) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP << 0) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VDACOUT0 (_ACMP_INPUTCTRL_POSSEL_VDACOUT0 << 0) /**< Shifted mode VDACOUT0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VDACOUT1 (_ACMP_INPUTCTRL_POSSEL_VDACOUT1 << 0) /**< Shifted mode VDACOUT1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPA (_ACMP_INPUTCTRL_POSSEL_EXTPA << 0) /**< Shifted mode EXTPA for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPB (_ACMP_INPUTCTRL_POSSEL_EXTPB << 0) /**< Shifted mode EXTPB for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPC (_ACMP_INPUTCTRL_POSSEL_EXTPC << 0) /**< Shifted mode EXTPC for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPD (_ACMP_INPUTCTRL_POSSEL_EXTPD << 0) /**< Shifted mode EXTPD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA0 (_ACMP_INPUTCTRL_POSSEL_PA0 << 0) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA1 (_ACMP_INPUTCTRL_POSSEL_PA1 << 0) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA2 (_ACMP_INPUTCTRL_POSSEL_PA2 << 0) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA3 (_ACMP_INPUTCTRL_POSSEL_PA3 << 0) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA4 (_ACMP_INPUTCTRL_POSSEL_PA4 << 0) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA5 (_ACMP_INPUTCTRL_POSSEL_PA5 << 0) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA6 (_ACMP_INPUTCTRL_POSSEL_PA6 << 0) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA7 (_ACMP_INPUTCTRL_POSSEL_PA7 << 0) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA8 (_ACMP_INPUTCTRL_POSSEL_PA8 << 0) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA9 (_ACMP_INPUTCTRL_POSSEL_PA9 << 0) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA10 (_ACMP_INPUTCTRL_POSSEL_PA10 << 0) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA11 (_ACMP_INPUTCTRL_POSSEL_PA11 << 0) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA12 (_ACMP_INPUTCTRL_POSSEL_PA12 << 0) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA13 (_ACMP_INPUTCTRL_POSSEL_PA13 << 0) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA14 (_ACMP_INPUTCTRL_POSSEL_PA14 << 0) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA15 (_ACMP_INPUTCTRL_POSSEL_PA15 << 0) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB0 (_ACMP_INPUTCTRL_POSSEL_PB0 << 0) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB1 (_ACMP_INPUTCTRL_POSSEL_PB1 << 0) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB2 (_ACMP_INPUTCTRL_POSSEL_PB2 << 0) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB3 (_ACMP_INPUTCTRL_POSSEL_PB3 << 0) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB4 (_ACMP_INPUTCTRL_POSSEL_PB4 << 0) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB5 (_ACMP_INPUTCTRL_POSSEL_PB5 << 0) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB6 (_ACMP_INPUTCTRL_POSSEL_PB6 << 0) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB7 (_ACMP_INPUTCTRL_POSSEL_PB7 << 0) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB8 (_ACMP_INPUTCTRL_POSSEL_PB8 << 0) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB9 (_ACMP_INPUTCTRL_POSSEL_PB9 << 0) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB10 (_ACMP_INPUTCTRL_POSSEL_PB10 << 0) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB11 (_ACMP_INPUTCTRL_POSSEL_PB11 << 0) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB12 (_ACMP_INPUTCTRL_POSSEL_PB12 << 0) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB13 (_ACMP_INPUTCTRL_POSSEL_PB13 << 0) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB14 (_ACMP_INPUTCTRL_POSSEL_PB14 << 0) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB15 (_ACMP_INPUTCTRL_POSSEL_PB15 << 0) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC0 (_ACMP_INPUTCTRL_POSSEL_PC0 << 0) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC1 (_ACMP_INPUTCTRL_POSSEL_PC1 << 0) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC2 (_ACMP_INPUTCTRL_POSSEL_PC2 << 0) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC3 (_ACMP_INPUTCTRL_POSSEL_PC3 << 0) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC4 (_ACMP_INPUTCTRL_POSSEL_PC4 << 0) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC5 (_ACMP_INPUTCTRL_POSSEL_PC5 << 0) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC6 (_ACMP_INPUTCTRL_POSSEL_PC6 << 0) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC7 (_ACMP_INPUTCTRL_POSSEL_PC7 << 0) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC8 (_ACMP_INPUTCTRL_POSSEL_PC8 << 0) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC9 (_ACMP_INPUTCTRL_POSSEL_PC9 << 0) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC10 (_ACMP_INPUTCTRL_POSSEL_PC10 << 0) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC11 (_ACMP_INPUTCTRL_POSSEL_PC11 << 0) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC12 (_ACMP_INPUTCTRL_POSSEL_PC12 << 0) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC13 (_ACMP_INPUTCTRL_POSSEL_PC13 << 0) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC14 (_ACMP_INPUTCTRL_POSSEL_PC14 << 0) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC15 (_ACMP_INPUTCTRL_POSSEL_PC15 << 0) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD0 (_ACMP_INPUTCTRL_POSSEL_PD0 << 0) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD1 (_ACMP_INPUTCTRL_POSSEL_PD1 << 0) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD2 (_ACMP_INPUTCTRL_POSSEL_PD2 << 0) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD3 (_ACMP_INPUTCTRL_POSSEL_PD3 << 0) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD4 (_ACMP_INPUTCTRL_POSSEL_PD4 << 0) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD5 (_ACMP_INPUTCTRL_POSSEL_PD5 << 0) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD6 (_ACMP_INPUTCTRL_POSSEL_PD6 << 0) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD7 (_ACMP_INPUTCTRL_POSSEL_PD7 << 0) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD8 (_ACMP_INPUTCTRL_POSSEL_PD8 << 0) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD9 (_ACMP_INPUTCTRL_POSSEL_PD9 << 0) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD10 (_ACMP_INPUTCTRL_POSSEL_PD10 << 0) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD11 (_ACMP_INPUTCTRL_POSSEL_PD11 << 0) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD12 (_ACMP_INPUTCTRL_POSSEL_PD12 << 0) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD13 (_ACMP_INPUTCTRL_POSSEL_PD13 << 0) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD14 (_ACMP_INPUTCTRL_POSSEL_PD14 << 0) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD15 (_ACMP_INPUTCTRL_POSSEL_PD15 << 0) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */ +#define _ACMP_INPUTCTRL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */ +#define _ACMP_INPUTCTRL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_CAPSENSE 0x00000030UL /**< Mode CAPSENSE for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VDACOUT0 0x00000040UL /**< Mode VDACOUT0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VDACOUT1 0x00000041UL /**< Mode VDACOUT1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_DEFAULT (_ACMP_INPUTCTRL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VSS (_ACMP_INPUTCTRL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD << 8) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP << 8) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 << 8) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP << 8) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 << 8) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP << 8) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 << 8) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP << 8) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 << 8) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP << 8) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_CAPSENSE (_ACMP_INPUTCTRL_NEGSEL_CAPSENSE << 8) /**< Shifted mode CAPSENSE for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VDACOUT0 (_ACMP_INPUTCTRL_NEGSEL_VDACOUT0 << 8) /**< Shifted mode VDACOUT0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VDACOUT1 (_ACMP_INPUTCTRL_NEGSEL_VDACOUT1 << 8) /**< Shifted mode VDACOUT1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA0 (_ACMP_INPUTCTRL_NEGSEL_PA0 << 8) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA1 (_ACMP_INPUTCTRL_NEGSEL_PA1 << 8) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA2 (_ACMP_INPUTCTRL_NEGSEL_PA2 << 8) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA3 (_ACMP_INPUTCTRL_NEGSEL_PA3 << 8) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA4 (_ACMP_INPUTCTRL_NEGSEL_PA4 << 8) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA5 (_ACMP_INPUTCTRL_NEGSEL_PA5 << 8) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA6 (_ACMP_INPUTCTRL_NEGSEL_PA6 << 8) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA7 (_ACMP_INPUTCTRL_NEGSEL_PA7 << 8) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA8 (_ACMP_INPUTCTRL_NEGSEL_PA8 << 8) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA9 (_ACMP_INPUTCTRL_NEGSEL_PA9 << 8) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA10 (_ACMP_INPUTCTRL_NEGSEL_PA10 << 8) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA11 (_ACMP_INPUTCTRL_NEGSEL_PA11 << 8) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA12 (_ACMP_INPUTCTRL_NEGSEL_PA12 << 8) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA13 (_ACMP_INPUTCTRL_NEGSEL_PA13 << 8) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA14 (_ACMP_INPUTCTRL_NEGSEL_PA14 << 8) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA15 (_ACMP_INPUTCTRL_NEGSEL_PA15 << 8) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB0 (_ACMP_INPUTCTRL_NEGSEL_PB0 << 8) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB1 (_ACMP_INPUTCTRL_NEGSEL_PB1 << 8) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB2 (_ACMP_INPUTCTRL_NEGSEL_PB2 << 8) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB3 (_ACMP_INPUTCTRL_NEGSEL_PB3 << 8) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB4 (_ACMP_INPUTCTRL_NEGSEL_PB4 << 8) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB5 (_ACMP_INPUTCTRL_NEGSEL_PB5 << 8) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB6 (_ACMP_INPUTCTRL_NEGSEL_PB6 << 8) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB7 (_ACMP_INPUTCTRL_NEGSEL_PB7 << 8) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB8 (_ACMP_INPUTCTRL_NEGSEL_PB8 << 8) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB9 (_ACMP_INPUTCTRL_NEGSEL_PB9 << 8) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB10 (_ACMP_INPUTCTRL_NEGSEL_PB10 << 8) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB11 (_ACMP_INPUTCTRL_NEGSEL_PB11 << 8) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB12 (_ACMP_INPUTCTRL_NEGSEL_PB12 << 8) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB13 (_ACMP_INPUTCTRL_NEGSEL_PB13 << 8) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB14 (_ACMP_INPUTCTRL_NEGSEL_PB14 << 8) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB15 (_ACMP_INPUTCTRL_NEGSEL_PB15 << 8) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC0 (_ACMP_INPUTCTRL_NEGSEL_PC0 << 8) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC1 (_ACMP_INPUTCTRL_NEGSEL_PC1 << 8) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC2 (_ACMP_INPUTCTRL_NEGSEL_PC2 << 8) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC3 (_ACMP_INPUTCTRL_NEGSEL_PC3 << 8) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC4 (_ACMP_INPUTCTRL_NEGSEL_PC4 << 8) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC5 (_ACMP_INPUTCTRL_NEGSEL_PC5 << 8) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC6 (_ACMP_INPUTCTRL_NEGSEL_PC6 << 8) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC7 (_ACMP_INPUTCTRL_NEGSEL_PC7 << 8) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC8 (_ACMP_INPUTCTRL_NEGSEL_PC8 << 8) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC9 (_ACMP_INPUTCTRL_NEGSEL_PC9 << 8) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC10 (_ACMP_INPUTCTRL_NEGSEL_PC10 << 8) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC11 (_ACMP_INPUTCTRL_NEGSEL_PC11 << 8) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC12 (_ACMP_INPUTCTRL_NEGSEL_PC12 << 8) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC13 (_ACMP_INPUTCTRL_NEGSEL_PC13 << 8) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC14 (_ACMP_INPUTCTRL_NEGSEL_PC14 << 8) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC15 (_ACMP_INPUTCTRL_NEGSEL_PC15 << 8) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD0 (_ACMP_INPUTCTRL_NEGSEL_PD0 << 8) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD1 (_ACMP_INPUTCTRL_NEGSEL_PD1 << 8) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD2 (_ACMP_INPUTCTRL_NEGSEL_PD2 << 8) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD3 (_ACMP_INPUTCTRL_NEGSEL_PD3 << 8) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD4 (_ACMP_INPUTCTRL_NEGSEL_PD4 << 8) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD5 (_ACMP_INPUTCTRL_NEGSEL_PD5 << 8) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD6 (_ACMP_INPUTCTRL_NEGSEL_PD6 << 8) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD7 (_ACMP_INPUTCTRL_NEGSEL_PD7 << 8) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD8 (_ACMP_INPUTCTRL_NEGSEL_PD8 << 8) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD9 (_ACMP_INPUTCTRL_NEGSEL_PD9 << 8) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD10 (_ACMP_INPUTCTRL_NEGSEL_PD10 << 8) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD11 (_ACMP_INPUTCTRL_NEGSEL_PD11 << 8) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD12 (_ACMP_INPUTCTRL_NEGSEL_PD12 << 8) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD13 (_ACMP_INPUTCTRL_NEGSEL_PD13 << 8) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD14 (_ACMP_INPUTCTRL_NEGSEL_PD14 << 8) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD15 (_ACMP_INPUTCTRL_NEGSEL_PD15 << 8) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_VREFDIV_SHIFT 16 /**< Shift value for ACMP_VREFDIV */ +#define _ACMP_INPUTCTRL_VREFDIV_MASK 0x3F0000UL /**< Bit mask for ACMP_VREFDIV */ +#define _ACMP_INPUTCTRL_VREFDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_VREFDIV_DEFAULT (_ACMP_INPUTCTRL_VREFDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ +#define _ACMP_INPUTCTRL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */ +#define _ACMP_INPUTCTRL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_DEFAULT (_ACMP_INPUTCTRL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES0 (_ACMP_INPUTCTRL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES1 (_ACMP_INPUTCTRL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES2 (_ACMP_INPUTCTRL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES3 (_ACMP_INPUTCTRL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES4 (_ACMP_INPUTCTRL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES5 (_ACMP_INPUTCTRL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES6 (_ACMP_INPUTCTRL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTCTRL */ /* Bit fields for ACMP STATUS */ -#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ -#define _ACMP_STATUS_MASK 0x0000001DUL /**< Mask for ACMP_STATUS */ -#define ACMP_STATUS_ACMPOUT (0x1UL << 0) /**< Analog Comparator Output */ -#define _ACMP_STATUS_ACMPOUT_SHIFT 0 /**< Shift value for ACMP_ACMPOUT */ -#define _ACMP_STATUS_ACMPOUT_MASK 0x1UL /**< Bit mask for ACMP_ACMPOUT */ -#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_ACMPRDY (0x1UL << 2) /**< Analog Comparator Ready */ -#define _ACMP_STATUS_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ -#define _ACMP_STATUS_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ -#define _ACMP_STATUS_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_ACMPRDY_DEFAULT (_ACMP_STATUS_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_INPUTCONFLICT (0x1UL << 3) /**< INPUT conflict */ -#define _ACMP_STATUS_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ -#define _ACMP_STATUS_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ -#define _ACMP_STATUS_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_INPUTCONFLICT_DEFAULT (_ACMP_STATUS_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ -#define _ACMP_STATUS_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ -#define _ACMP_STATUS_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ -#define _ACMP_STATUS_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_PORTALLOCERR_DEFAULT (_ACMP_STATUS_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ +#define _ACMP_STATUS_MASK 0x0000001DUL /**< Mask for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT (0x1UL << 0) /**< Analog Comparator Output */ +#define _ACMP_STATUS_ACMPOUT_SHIFT 0 /**< Shift value for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_MASK 0x1UL /**< Bit mask for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPRDY (0x1UL << 2) /**< Analog Comparator Ready */ +#define _ACMP_STATUS_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_STATUS_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_STATUS_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPRDY_DEFAULT (_ACMP_STATUS_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_INPUTCONFLICT (0x1UL << 3) /**< INPUT conflict */ +#define _ACMP_STATUS_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_STATUS_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_STATUS_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_INPUTCONFLICT_DEFAULT (_ACMP_STATUS_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ +#define _ACMP_STATUS_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_STATUS_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_STATUS_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_PORTALLOCERR_DEFAULT (_ACMP_STATUS_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_STATUS */ /* Bit fields for ACMP IF */ -#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ -#define _ACMP_IF_MASK 0x0000001FUL /**< Mask for ACMP_IF */ -#define ACMP_IF_RISE (0x1UL << 0) /**< Rising Edge Triggered Interrupt Flag */ -#define _ACMP_IF_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ -#define _ACMP_IF_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ -#define _ACMP_IF_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ -#define ACMP_IF_RISE_DEFAULT (_ACMP_IF_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ -#define ACMP_IF_FALL (0x1UL << 1) /**< Falling Edge Triggered Interrupt Flag */ -#define _ACMP_IF_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ -#define _ACMP_IF_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ -#define _ACMP_IF_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ -#define ACMP_IF_FALL_DEFAULT (_ACMP_IF_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ -#define ACMP_IF_ACMPRDY (0x1UL << 2) /**< ACMP ready Interrupt flag */ -#define _ACMP_IF_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ -#define _ACMP_IF_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ -#define _ACMP_IF_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ -#define ACMP_IF_ACMPRDY_DEFAULT (_ACMP_IF_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */ -#define ACMP_IF_INPUTCONFLICT (0x1UL << 3) /**< Input conflict */ -#define _ACMP_IF_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ -#define _ACMP_IF_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ -#define _ACMP_IF_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ -#define ACMP_IF_INPUTCONFLICT_DEFAULT (_ACMP_IF_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IF */ -#define ACMP_IF_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ -#define _ACMP_IF_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ -#define _ACMP_IF_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ -#define _ACMP_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ -#define ACMP_IF_PORTALLOCERR_DEFAULT (_ACMP_IF_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IF */ +#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ +#define _ACMP_IF_MASK 0x0000001FUL /**< Mask for ACMP_IF */ +#define ACMP_IF_RISE (0x1UL << 0) /**< Rising Edge Triggered Interrupt Flag */ +#define _ACMP_IF_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ +#define _ACMP_IF_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ +#define _ACMP_IF_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_RISE_DEFAULT (_ACMP_IF_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_FALL (0x1UL << 1) /**< Falling Edge Triggered Interrupt Flag */ +#define _ACMP_IF_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ +#define _ACMP_IF_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ +#define _ACMP_IF_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_FALL_DEFAULT (_ACMP_IF_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_ACMPRDY (0x1UL << 2) /**< ACMP ready Interrupt flag */ +#define _ACMP_IF_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_IF_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_IF_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_ACMPRDY_DEFAULT (_ACMP_IF_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_INPUTCONFLICT (0x1UL << 3) /**< Input conflict */ +#define _ACMP_IF_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_IF_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_IF_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_INPUTCONFLICT_DEFAULT (_ACMP_IF_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ +#define _ACMP_IF_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_IF_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_PORTALLOCERR_DEFAULT (_ACMP_IF_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IF */ /* Bit fields for ACMP IEN */ -#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ -#define _ACMP_IEN_MASK 0x0000001FUL /**< Mask for ACMP_IEN */ -#define ACMP_IEN_RISE (0x1UL << 0) /**< Rising edge interrupt enable */ -#define _ACMP_IEN_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ -#define _ACMP_IEN_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ -#define _ACMP_IEN_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_RISE_DEFAULT (_ACMP_IEN_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_FALL (0x1UL << 1) /**< Falling edge interrupt enable */ -#define _ACMP_IEN_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ -#define _ACMP_IEN_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ -#define _ACMP_IEN_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_FALL_DEFAULT (_ACMP_IEN_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_ACMPRDY (0x1UL << 2) /**< ACMP ready interrupt enable */ -#define _ACMP_IEN_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ -#define _ACMP_IEN_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ -#define _ACMP_IEN_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_ACMPRDY_DEFAULT (_ACMP_IEN_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_INPUTCONFLICT (0x1UL << 3) /**< Input conflict interrupt enable */ -#define _ACMP_IEN_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ -#define _ACMP_IEN_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ -#define _ACMP_IEN_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_INPUTCONFLICT_DEFAULT (_ACMP_IEN_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_PORTALLOCERR (0x1UL << 4) /**< Port allocation error interrupt enable */ -#define _ACMP_IEN_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ -#define _ACMP_IEN_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ -#define _ACMP_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_PORTALLOCERR_DEFAULT (_ACMP_IEN_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ +#define _ACMP_IEN_MASK 0x0000001FUL /**< Mask for ACMP_IEN */ +#define ACMP_IEN_RISE (0x1UL << 0) /**< Rising edge interrupt enable */ +#define _ACMP_IEN_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ +#define _ACMP_IEN_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ +#define _ACMP_IEN_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_RISE_DEFAULT (_ACMP_IEN_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_FALL (0x1UL << 1) /**< Falling edge interrupt enable */ +#define _ACMP_IEN_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ +#define _ACMP_IEN_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ +#define _ACMP_IEN_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_FALL_DEFAULT (_ACMP_IEN_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_ACMPRDY (0x1UL << 2) /**< ACMP ready interrupt enable */ +#define _ACMP_IEN_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_IEN_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_IEN_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_ACMPRDY_DEFAULT (_ACMP_IEN_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_INPUTCONFLICT (0x1UL << 3) /**< Input conflict interrupt enable */ +#define _ACMP_IEN_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_IEN_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_IEN_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_INPUTCONFLICT_DEFAULT (_ACMP_IEN_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_PORTALLOCERR (0x1UL << 4) /**< Port allocation error interrupt enable */ +#define _ACMP_IEN_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_IEN_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_PORTALLOCERR_DEFAULT (_ACMP_IEN_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IEN */ /* Bit fields for ACMP SYNCBUSY */ -#define _ACMP_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for ACMP_SYNCBUSY */ -#define _ACMP_SYNCBUSY_MASK 0x00000001UL /**< Mask for ACMP_SYNCBUSY */ -#define ACMP_SYNCBUSY_INPUTCTRL (0x1UL << 0) /**< Syncbusy for INPUTCTRL */ -#define _ACMP_SYNCBUSY_INPUTCTRL_SHIFT 0 /**< Shift value for ACMP_INPUTCTRL */ -#define _ACMP_SYNCBUSY_INPUTCTRL_MASK 0x1UL /**< Bit mask for ACMP_INPUTCTRL */ -#define _ACMP_SYNCBUSY_INPUTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SYNCBUSY */ -#define ACMP_SYNCBUSY_INPUTCTRL_DEFAULT (_ACMP_SYNCBUSY_INPUTCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SYNCBUSY */ +#define _ACMP_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for ACMP_SYNCBUSY */ +#define _ACMP_SYNCBUSY_MASK 0x00000001UL /**< Mask for ACMP_SYNCBUSY */ +#define ACMP_SYNCBUSY_INPUTCTRL (0x1UL << 0) /**< Syncbusy for INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_SHIFT 0 /**< Shift value for ACMP_INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_MASK 0x1UL /**< Bit mask for ACMP_INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SYNCBUSY */ +#define ACMP_SYNCBUSY_INPUTCTRL_DEFAULT (_ACMP_SYNCBUSY_INPUTCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SYNCBUSY */ /** @} End of group EFR32SG23_ACMP_BitFields */ /** @} End of group EFR32SG23_ACMP */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_aes.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_aes.h index 50786e3103..8953a4f084 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_aes.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_aes.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -41,30 +41,29 @@ *****************************************************************************/ /** AES Register Declaration. */ -typedef struct -{ - __IOM uint32_t FETCHADDR; /**< Fetcher Address */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t FETCHLEN; /**< Fetcher Length */ - __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ - __IOM uint32_t PUSHADDR; /**< Pusher Address */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t PUSHLEN; /**< Pusher Length */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IM uint32_t IF; /**< Interrupt Flags */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt status clear */ - __IOM uint32_t CTRL; /**< Control register */ - __IOM uint32_t CMD; /**< Command register */ - __IM uint32_t STATUS; /**< Status register */ - uint32_t RESERVED4[240U]; /**< Reserved for future use */ - __IM uint32_t INCL_IPS_HW_CFG; /**< INCL_IPS_HW_CFG */ - __IM uint32_t BA411E_HW_CFG_1; /**< BA411E_HW_CFG_1 */ - __IM uint32_t BA411E_HW_CFG_2; /**< BA411E_HW_CFG_2 */ - __IM uint32_t BA413_HW_CFG; /**< BA413_HW_CFG */ - __IM uint32_t BA418_HW_CFG; /**< BA418_HW_CFG */ - __IM uint32_t BA419_HW_CFG; /**< BA419_HW_CFG */ +typedef struct { + __IOM uint32_t FETCHADDR; /**< Fetcher Address */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t FETCHLEN; /**< Fetcher Length */ + __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ + __IOM uint32_t PUSHADDR; /**< Pusher Address */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t PUSHLEN; /**< Pusher Length */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IM uint32_t IF; /**< Interrupt Flags */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt status clear */ + __IOM uint32_t CTRL; /**< Control register */ + __IOM uint32_t CMD; /**< Command register */ + __IM uint32_t STATUS; /**< Status register */ + uint32_t RESERVED4[240U]; /**< Reserved for future use */ + __IM uint32_t INCL_IPS_HW_CFG; /**< INCL_IPS_HW_CFG */ + __IM uint32_t BA411E_HW_CFG_1; /**< BA411E_HW_CFG_1 */ + __IM uint32_t BA411E_HW_CFG_2; /**< BA411E_HW_CFG_2 */ + __IM uint32_t BA413_HW_CFG; /**< BA413_HW_CFG */ + __IM uint32_t BA418_HW_CFG; /**< BA418_HW_CFG */ + __IM uint32_t BA419_HW_CFG; /**< BA419_HW_CFG */ } AES_TypeDef; /** @} End of group EFR32SG23_AES */ @@ -76,376 +75,376 @@ typedef struct *****************************************************************************/ /* Bit fields for AES FETCHADDR */ -#define _AES_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHADDR */ -#define _AES_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHADDR */ -#define _AES_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ -#define _AES_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ -#define _AES_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHADDR */ -#define AES_FETCHADDR_ADDR_DEFAULT (_AES_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHADDR */ +#define _AES_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHADDR */ +#define _AES_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHADDR */ +#define _AES_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHADDR */ +#define AES_FETCHADDR_ADDR_DEFAULT (_AES_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHADDR */ /* Bit fields for AES FETCHLEN */ -#define _AES_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHLEN */ -#define _AES_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for AES_FETCHLEN */ -#define _AES_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ -#define _AES_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ -#define _AES_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_LENGTH_DEFAULT (_AES_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ -#define _AES_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ -#define _AES_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ -#define _AES_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_CONSTADDR_DEFAULT (_AES_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign lengh */ -#define _AES_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ -#define _AES_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ -#define _AES_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_REALIGN_DEFAULT (_AES_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define _AES_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHLEN */ +#define _AES_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for AES_FETCHLEN */ +#define _AES_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_LENGTH_DEFAULT (_AES_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR_DEFAULT (_AES_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign lengh */ +#define _AES_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN_DEFAULT (_AES_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_FETCHLEN */ /* Bit fields for AES FETCHTAG */ -#define _AES_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHTAG */ -#define _AES_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHTAG */ -#define _AES_FETCHTAG_TAG_SHIFT 0 /**< Shift value for AES_TAG */ -#define _AES_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for AES_TAG */ -#define _AES_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHTAG */ -#define AES_FETCHTAG_TAG_DEFAULT (_AES_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHTAG */ +#define _AES_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHTAG */ +#define _AES_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHTAG */ +#define _AES_FETCHTAG_TAG_SHIFT 0 /**< Shift value for AES_TAG */ +#define _AES_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for AES_TAG */ +#define _AES_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHTAG */ +#define AES_FETCHTAG_TAG_DEFAULT (_AES_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHTAG */ /* Bit fields for AES PUSHADDR */ -#define _AES_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHADDR */ -#define _AES_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHADDR */ -#define _AES_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ -#define _AES_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ -#define _AES_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHADDR */ -#define AES_PUSHADDR_ADDR_DEFAULT (_AES_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHADDR */ +#define _AES_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHADDR */ +#define _AES_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHADDR */ +#define _AES_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHADDR */ +#define AES_PUSHADDR_ADDR_DEFAULT (_AES_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHADDR */ /* Bit fields for AES PUSHLEN */ -#define _AES_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHLEN */ -#define _AES_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for AES_PUSHLEN */ -#define _AES_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ -#define _AES_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ -#define _AES_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_LENGTH_DEFAULT (_AES_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ -#define _AES_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ -#define _AES_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ -#define _AES_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_CONSTADDR_DEFAULT (_AES_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ -#define _AES_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ -#define _AES_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ -#define _AES_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_REALIGN_DEFAULT (_AES_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ -#define _AES_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for AES_DISCARD */ -#define _AES_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for AES_DISCARD */ -#define _AES_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_DISCARD_DEFAULT (_AES_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define _AES_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHLEN */ +#define _AES_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for AES_PUSHLEN */ +#define _AES_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_LENGTH_DEFAULT (_AES_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR_DEFAULT (_AES_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ +#define _AES_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN_DEFAULT (_AES_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ +#define _AES_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD_DEFAULT (_AES_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for AES_PUSHLEN */ /* Bit fields for AES IEN */ -#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ -#define _AES_IEN_MASK 0x0000003FUL /**< Mask for AES_IEN */ -#define AES_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ -#define _AES_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ -#define _AES_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ -#define _AES_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERENDOFBLOCK_DEFAULT (_AES_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ -#define _AES_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ -#define _AES_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ -#define _AES_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERSTOPPED_DEFAULT (_AES_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ -#define _AES_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ -#define _AES_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ -#define _AES_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERERROR_DEFAULT (_AES_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ -#define _AES_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ -#define _AES_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ -#define _AES_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERENDOFBLOCK_DEFAULT (_AES_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ -#define _AES_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ -#define _AES_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ -#define _AES_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERSTOPPED_DEFAULT (_AES_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ -#define _AES_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ -#define _AES_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ -#define _AES_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERERROR_DEFAULT (_AES_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IEN */ +#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ +#define _AES_IEN_MASK 0x0000003FUL /**< Mask for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ +#define _AES_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK_DEFAULT (_AES_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ +#define _AES_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED_DEFAULT (_AES_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ +#define _AES_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR_DEFAULT (_AES_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ +#define _AES_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK_DEFAULT (_AES_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ +#define _AES_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED_DEFAULT (_AES_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ +#define _AES_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR_DEFAULT (_AES_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IEN */ /* Bit fields for AES IF */ -#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ -#define _AES_IF_MASK 0x0000003FUL /**< Mask for AES_IF */ -#define AES_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ -#define _AES_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ -#define _AES_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ -#define _AES_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ -#define _AES_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ -#define _AES_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ -#define _AES_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERSTOPPED_DEFAULT (_AES_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ -#define _AES_IF_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ -#define _AES_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ -#define _AES_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERERROR_DEFAULT (_AES_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ -#define _AES_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ -#define _AES_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ -#define _AES_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ -#define _AES_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ -#define _AES_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ -#define _AES_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERSTOPPED_DEFAULT (_AES_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ -#define _AES_IF_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ -#define _AES_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ -#define _AES_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERERROR_DEFAULT (_AES_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF */ +#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ +#define _AES_IF_MASK 0x0000003FUL /**< Mask for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ +#define _AES_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ +#define _AES_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED_DEFAULT (_AES_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ +#define _AES_IF_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR_DEFAULT (_AES_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ +#define _AES_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ +#define _AES_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED_DEFAULT (_AES_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ +#define _AES_IF_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR_DEFAULT (_AES_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF */ /* Bit fields for AES IF_CLR */ -#define _AES_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for AES_IF_CLR */ -#define _AES_IF_CLR_MASK 0x0000003FUL /**< Mask for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ -#define _AES_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ -#define _AES_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ -#define _AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ -#define _AES_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ -#define _AES_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ -#define _AES_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERSTOPPED_DEFAULT (_AES_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ -#define _AES_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ -#define _AES_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ -#define _AES_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERERROR_DEFAULT (_AES_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< FETCHERENDOFBLOCKIFC */ -#define _AES_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ -#define _AES_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ -#define _AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< FETCHERSTOPPEDIFC */ -#define _AES_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ -#define _AES_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ -#define _AES_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERSTOPPED_DEFAULT (_AES_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERERROR (0x1UL << 5) /**< FETCHERERRORIFC */ -#define _AES_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ -#define _AES_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ -#define _AES_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERERROR_DEFAULT (_AES_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define _AES_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for AES_IF_CLR */ +#define _AES_IF_CLR_MASK 0x0000003FUL /**< Mask for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ +#define _AES_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED_DEFAULT (_AES_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ +#define _AES_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR_DEFAULT (_AES_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< FETCHERENDOFBLOCKIFC */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< FETCHERSTOPPEDIFC */ +#define _AES_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED_DEFAULT (_AES_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR (0x1UL << 5) /**< FETCHERERRORIFC */ +#define _AES_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR_DEFAULT (_AES_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF_CLR */ /* Bit fields for AES CTRL */ -#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ -#define _AES_CTRL_MASK 0x0000001FUL /**< Mask for AES_CTRL */ -#define AES_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ -#define _AES_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for AES_FETCHERSCATTERGATHER */ -#define _AES_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for AES_FETCHERSCATTERGATHER */ -#define _AES_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_FETCHERSCATTERGATHER_DEFAULT (_AES_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */ -#define AES_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ -#define _AES_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for AES_PUSHERSCATTERGATHER */ -#define _AES_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for AES_PUSHERSCATTERGATHER */ -#define _AES_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_PUSHERSCATTERGATHER_DEFAULT (_AES_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */ -#define AES_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ -#define _AES_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for AES_STOPFETCHER */ -#define _AES_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for AES_STOPFETCHER */ -#define _AES_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_STOPFETCHER_DEFAULT (_AES_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */ -#define AES_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ -#define _AES_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for AES_STOPPUSHER */ -#define _AES_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for AES_STOPPUSHER */ -#define _AES_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_STOPPUSHER_DEFAULT (_AES_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_CTRL */ -#define AES_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ -#define _AES_CTRL_SWRESET_SHIFT 4 /**< Shift value for AES_SWRESET */ -#define _AES_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for AES_SWRESET */ -#define _AES_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_SWRESET_DEFAULT (_AES_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */ +#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ +#define _AES_CTRL_MASK 0x0000001FUL /**< Mask for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ +#define _AES_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER_DEFAULT (_AES_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ +#define _AES_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER_DEFAULT (_AES_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ +#define _AES_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER_DEFAULT (_AES_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ +#define _AES_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER_DEFAULT (_AES_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ +#define _AES_CTRL_SWRESET_SHIFT 4 /**< Shift value for AES_SWRESET */ +#define _AES_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for AES_SWRESET */ +#define _AES_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET_DEFAULT (_AES_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */ /* Bit fields for AES CMD */ -#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ -#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ -#define AES_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ -#define _AES_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for AES_STARTFETCHER */ -#define _AES_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for AES_STARTFETCHER */ -#define _AES_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ -#define AES_CMD_STARTFETCHER_DEFAULT (_AES_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */ -#define AES_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ -#define _AES_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for AES_STARTPUSHER */ -#define _AES_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for AES_STARTPUSHER */ -#define _AES_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ -#define AES_CMD_STARTPUSHER_DEFAULT (_AES_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */ +#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ +#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ +#define AES_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ +#define _AES_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTFETCHER_DEFAULT (_AES_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ +#define _AES_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER_DEFAULT (_AES_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */ /* Bit fields for AES STATUS */ -#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ -#define _AES_STATUS_MASK 0xFFFF0073UL /**< Mask for AES_STATUS */ -#define AES_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ -#define _AES_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for AES_FETCHERBSY */ -#define _AES_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for AES_FETCHERBSY */ -#define _AES_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_FETCHERBSY_DEFAULT (_AES_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */ -#define AES_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ -#define _AES_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for AES_PUSHERBSY */ -#define _AES_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for AES_PUSHERBSY */ -#define _AES_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_PUSHERBSY_DEFAULT (_AES_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_STATUS */ -#define AES_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ -#define _AES_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for AES_NOTEMPTY */ -#define _AES_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for AES_NOTEMPTY */ -#define _AES_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_NOTEMPTY_DEFAULT (_AES_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_STATUS */ -#define AES_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ -#define _AES_STATUS_WAITING_SHIFT 5 /**< Shift value for AES_WAITING */ -#define _AES_STATUS_WAITING_MASK 0x20UL /**< Bit mask for AES_WAITING */ -#define _AES_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_WAITING_DEFAULT (_AES_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_STATUS */ -#define AES_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ -#define _AES_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for AES_SOFTRSTBSY */ -#define _AES_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for AES_SOFTRSTBSY */ -#define _AES_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_SOFTRSTBSY_DEFAULT (_AES_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_STATUS */ -#define _AES_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for AES_FIFODATANUM */ -#define _AES_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for AES_FIFODATANUM */ -#define _AES_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_FIFODATANUM_DEFAULT (_AES_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_STATUS */ +#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ +#define _AES_STATUS_MASK 0xFFFF0073UL /**< Mask for AES_STATUS */ +#define AES_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ +#define _AES_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FETCHERBSY_DEFAULT (_AES_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ +#define _AES_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY_DEFAULT (_AES_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ +#define _AES_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY_DEFAULT (_AES_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ +#define _AES_STATUS_WAITING_SHIFT 5 /**< Shift value for AES_WAITING */ +#define _AES_STATUS_WAITING_MASK 0x20UL /**< Bit mask for AES_WAITING */ +#define _AES_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING_DEFAULT (_AES_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ +#define _AES_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY_DEFAULT (_AES_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_STATUS */ +#define _AES_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FIFODATANUM_DEFAULT (_AES_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_STATUS */ /* Bit fields for AES INCL_IPS_HW_CFG */ -#define _AES_INCL_IPS_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_INCL_IPS_HW_CFG */ -#define _AES_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for AES_g_IncludeAES */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for AES_g_IncludeAES */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for AES_g_IncludeAESGCM */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for AES_g_IncludeAESGCM */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for AES_g_IncludeAESXTS */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for AES_g_IncludeAESXTS */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for AES_g_IncludeDES */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for AES_g_IncludeDES */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for AES_g_IncludeHASH */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for AES_g_IncludeHASH */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for AES_g_IncludeChachaPoly */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for AES_g_IncludeChachaPoly */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for AES_g_IncludeSHA3 */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for AES_g_IncludeSHA3 */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for AES_g_IncludeZUC */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for AES_g_IncludeZUC */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for AES_g_IncludeSM4 */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for AES_g_IncludeSM4 */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for AES_g_IncludePKE */ -#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for AES_g_IncludePKE */ -#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for AES_g_IncludeNDRNG */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for AES_g_IncludeNDRNG */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define _AES_INCL_IPS_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_INCL_IPS_HW_CFG */ +#define _AES_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ /* Bit fields for AES BA411E_HW_CFG_1 */ -#define _AES_BA411E_HW_CFG_1_RESETVALUE 0x05010127UL /**< Default value for AES_BA411E_HW_CFG_1 */ -#define _AES_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for AES_BA411E_HW_CFG_1 */ -#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for AES_g_AesModesPoss */ -#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for AES_g_AesModesPoss */ -#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x00000127UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ -#define AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ -#define AES_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */ -#define _AES_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for AES_g_CS */ -#define _AES_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for AES_g_CS */ -#define _AES_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ -#define AES_BA411E_HW_CFG_1_g_CS_DEFAULT (_AES_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ -#define AES_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */ -#define _AES_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for AES_g_UseMasking */ -#define _AES_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for AES_g_UseMasking */ -#define _AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ -#define AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ -#define _AES_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for AES_g_Keysize */ -#define _AES_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for AES_g_Keysize */ -#define _AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000005UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ -#define AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define _AES_BA411E_HW_CFG_1_RESETVALUE 0x05010127UL /**< Default value for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x00000127UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */ +#define _AES_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_CS_DEFAULT (_AES_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define _AES_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000005UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ /* Bit fields for AES BA411E_HW_CFG_2 */ -#define _AES_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for AES_BA411E_HW_CFG_2 */ -#define _AES_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for AES_BA411E_HW_CFG_2 */ -#define _AES_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for AES_g_CtrSize */ -#define _AES_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for AES_g_CtrSize */ -#define _AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_2 */ -#define AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_2*/ +#define _AES_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_2 */ +#define AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_2*/ /* Bit fields for AES BA413_HW_CFG */ -#define _AES_BA413_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA413_HW_CFG */ -#define _AES_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for AES_BA413_HW_CFG */ -#define _AES_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for AES_g_HashMaskFunc */ -#define _AES_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for AES_g_HashMaskFunc */ -#define _AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */ -#define _AES_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for AES_g_HashPadding */ -#define _AES_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for AES_g_HashPadding */ -#define _AES_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashPadding_DEFAULT (_AES_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */ -#define _AES_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for AES_g_HMAC_enabled */ -#define _AES_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for AES_g_HMAC_enabled */ -#define _AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */ -#define _AES_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for AES_g_HashVerifyDigest */ -#define _AES_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for AES_g_HashVerifyDigest */ -#define _AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */ +#define _AES_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding_DEFAULT (_AES_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ /* Bit fields for AES BA418_HW_CFG */ -#define _AES_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_BA418_HW_CFG */ -#define _AES_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for AES_BA418_HW_CFG */ -#define AES_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */ -#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for AES_g_Sha3CtxtEn */ -#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for AES_g_Sha3CtxtEn */ -#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA418_HW_CFG */ -#define AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA418_HW_CFG */ /* Bit fields for AES BA419_HW_CFG */ -#define _AES_BA419_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA419_HW_CFG */ -#define _AES_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for AES_BA419_HW_CFG */ -#define _AES_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for AES_g_SM4ModesPoss */ -#define _AES_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for AES_g_SM4ModesPoss */ -#define _AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA419_HW_CFG */ -#define AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA419_HW_CFG */ +#define AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA419_HW_CFG */ /** @} End of group EFR32SG23_AES_BitFields */ /** @} End of group EFR32SG23_AES */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_buram.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_buram.h index 4a33f3fe32..3761f68884 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_buram.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_buram.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_BURAM_H #define EFR32SG23_BURAM_H - #define BURAM_HAS_SET_CLEAR /**************************************************************************//** @@ -43,22 +42,19 @@ *****************************************************************************/ /** BURAM RET Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t REG; /**< Retention Register */ +typedef struct { + __IOM uint32_t REG; /**< Retention Register */ } BURAM_RET_TypeDef; - /** BURAM Register Declaration. */ -typedef struct -{ - BURAM_RET_TypeDef RET[32U]; /**< RetentionReg */ - uint32_t RESERVED0[992U]; /**< Reserved for future use */ - BURAM_RET_TypeDef RET_SET[32U]; /**< RetentionReg */ - uint32_t RESERVED1[992U]; /**< Reserved for future use */ - BURAM_RET_TypeDef RET_CLR[32U]; /**< RetentionReg */ - uint32_t RESERVED2[992U]; /**< Reserved for future use */ - BURAM_RET_TypeDef RET_TGL[32U]; /**< RetentionReg */ +typedef struct { + BURAM_RET_TypeDef RET[32U]; /**< RetentionReg */ + uint32_t RESERVED0[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_SET[32U]; /**< RetentionReg */ + uint32_t RESERVED1[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_CLR[32U]; /**< RetentionReg */ + uint32_t RESERVED2[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_TGL[32U]; /**< RetentionReg */ } BURAM_TypeDef; /** @} End of group EFR32SG23_BURAM */ @@ -70,12 +66,12 @@ typedef struct *****************************************************************************/ /* Bit fields for BURAM RET_REG */ -#define _BURAM_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURAM_RET_REG */ -#define _BURAM_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURAM_RET_REG */ -#define _BURAM_RET_REG_RETREG_SHIFT 0 /**< Shift value for BURAM_RETREG */ -#define _BURAM_RET_REG_RETREG_MASK 0xFFFFFFFFUL /**< Bit mask for BURAM_RETREG */ -#define _BURAM_RET_REG_RETREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURAM_RET_REG */ -#define BURAM_RET_REG_RETREG_DEFAULT (_BURAM_RET_REG_RETREG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURAM_RET_REG */ +#define _BURAM_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURAM_RET_REG */ +#define _BURAM_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURAM_RET_REG */ +#define _BURAM_RET_REG_RETREG_SHIFT 0 /**< Shift value for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_MASK 0xFFFFFFFFUL /**< Bit mask for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURAM_RET_REG */ +#define BURAM_RET_REG_RETREG_DEFAULT (_BURAM_RET_REG_RETREG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURAM_RET_REG */ /** @} End of group EFR32SG23_BURAM_BitFields */ /** @} End of group EFR32SG23_BURAM */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_burtc.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_burtc.h index faed7154d9..6dce6b274d 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_burtc.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_burtc.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_BURTC_H #define EFR32SG23_BURTC_H - #define BURTC_HAS_SET_CLEAR /**************************************************************************//** @@ -43,63 +42,62 @@ *****************************************************************************/ /** BURTC Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t EN; /**< Module Enable Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT; /**< Counter Value Register */ - __IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - __IOM uint32_t COMP; /**< Compare Value Register */ - uint32_t RESERVED0[1011U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t EN_SET; /**< Module Enable Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT_SET; /**< Counter Value Register */ - __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - __IOM uint32_t COMP_SET; /**< Compare Value Register */ - uint32_t RESERVED1[1011U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t EN_CLR; /**< Module Enable Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT_CLR; /**< Counter Value Register */ - __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - __IOM uint32_t COMP_CLR; /**< Compare Value Register */ - uint32_t RESERVED2[1011U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t EN_TGL; /**< Module Enable Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT_TGL; /**< Counter Value Register */ - __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - __IOM uint32_t COMP_TGL; /**< Compare Value Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t COMP; /**< Compare Value Register */ + uint32_t RESERVED0[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t COMP_SET; /**< Compare Value Register */ + uint32_t RESERVED1[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t COMP_CLR; /**< Compare Value Register */ + uint32_t RESERVED2[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t COMP_TGL; /**< Compare Value Register */ } BURTC_TypeDef; /** @} End of group EFR32SG23_BURTC */ @@ -111,221 +109,221 @@ typedef struct *****************************************************************************/ /* Bit fields for BURTC IPVERSION */ -#define _BURTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for BURTC_IPVERSION */ -#define _BURTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BURTC_IPVERSION */ -#define _BURTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BURTC_IPVERSION */ -#define _BURTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_IPVERSION */ -#define _BURTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for BURTC_IPVERSION */ -#define BURTC_IPVERSION_IPVERSION_DEFAULT (_BURTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for BURTC_IPVERSION */ +#define BURTC_IPVERSION_IPVERSION_DEFAULT (_BURTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IPVERSION */ /* Bit fields for BURTC EN */ -#define _BURTC_EN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EN */ -#define _BURTC_EN_MASK 0x00000003UL /**< Mask for BURTC_EN */ -#define BURTC_EN_EN (0x1UL << 0) /**< BURTC Enable */ -#define _BURTC_EN_EN_SHIFT 0 /**< Shift value for BURTC_EN */ -#define _BURTC_EN_EN_MASK 0x1UL /**< Bit mask for BURTC_EN */ -#define _BURTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ -#define BURTC_EN_EN_DEFAULT (_BURTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EN */ -#define BURTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _BURTC_EN_DISABLING_SHIFT 1 /**< Shift value for BURTC_DISABLING */ -#define _BURTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for BURTC_DISABLING */ -#define _BURTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ -#define BURTC_EN_DISABLING_DEFAULT (_BURTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EN */ +#define _BURTC_EN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EN */ +#define _BURTC_EN_MASK 0x00000003UL /**< Mask for BURTC_EN */ +#define BURTC_EN_EN (0x1UL << 0) /**< BURTC Enable */ +#define _BURTC_EN_EN_SHIFT 0 /**< Shift value for BURTC_EN */ +#define _BURTC_EN_EN_MASK 0x1UL /**< Bit mask for BURTC_EN */ +#define _BURTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ +#define BURTC_EN_EN_DEFAULT (_BURTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EN */ +#define BURTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _BURTC_EN_DISABLING_SHIFT 1 /**< Shift value for BURTC_DISABLING */ +#define _BURTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for BURTC_DISABLING */ +#define _BURTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ +#define BURTC_EN_DISABLING_DEFAULT (_BURTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EN */ /* Bit fields for BURTC CFG */ -#define _BURTC_CFG_RESETVALUE 0x00000000UL /**< Default value for BURTC_CFG */ -#define _BURTC_CFG_MASK 0x000000F3UL /**< Mask for BURTC_CFG */ -#define BURTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ -#define _BURTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for BURTC_DEBUGRUN */ -#define _BURTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for BURTC_DEBUGRUN */ -#define _BURTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ -#define _BURTC_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for BURTC_CFG */ -#define _BURTC_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for BURTC_CFG */ -#define BURTC_CFG_DEBUGRUN_DEFAULT (_BURTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CFG */ -#define BURTC_CFG_DEBUGRUN_X0 (_BURTC_CFG_DEBUGRUN_X0 << 0) /**< Shifted mode X0 for BURTC_CFG */ -#define BURTC_CFG_DEBUGRUN_X1 (_BURTC_CFG_DEBUGRUN_X1 << 0) /**< Shifted mode X1 for BURTC_CFG */ -#define BURTC_CFG_COMPTOP (0x1UL << 1) /**< Compare Channel is Top Value */ -#define _BURTC_CFG_COMPTOP_SHIFT 1 /**< Shift value for BURTC_COMPTOP */ -#define _BURTC_CFG_COMPTOP_MASK 0x2UL /**< Bit mask for BURTC_COMPTOP */ -#define _BURTC_CFG_COMPTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ -#define _BURTC_CFG_COMPTOP_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ -#define _BURTC_CFG_COMPTOP_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ -#define BURTC_CFG_COMPTOP_DEFAULT (_BURTC_CFG_COMPTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CFG */ -#define BURTC_CFG_COMPTOP_DISABLE (_BURTC_CFG_COMPTOP_DISABLE << 1) /**< Shifted mode DISABLE for BURTC_CFG */ -#define BURTC_CFG_COMPTOP_ENABLE (_BURTC_CFG_COMPTOP_ENABLE << 1) /**< Shifted mode ENABLE for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for BURTC_CNTPRESC */ -#define _BURTC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for BURTC_CNTPRESC */ -#define _BURTC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DEFAULT (_BURTC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV1 (_BURTC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV2 (_BURTC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV4 (_BURTC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV8 (_BURTC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV16 (_BURTC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV32 (_BURTC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV64 (_BURTC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV128 (_BURTC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV256 (_BURTC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV512 (_BURTC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV1024 (_BURTC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV2048 (_BURTC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV4096 (_BURTC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV8192 (_BURTC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV16384 (_BURTC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV32768 (_BURTC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for BURTC_CFG */ +#define _BURTC_CFG_RESETVALUE 0x00000000UL /**< Default value for BURTC_CFG */ +#define _BURTC_CFG_MASK 0x000000F3UL /**< Mask for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _BURTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_DEFAULT (_BURTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_X0 (_BURTC_CFG_DEBUGRUN_X0 << 0) /**< Shifted mode X0 for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_X1 (_BURTC_CFG_DEBUGRUN_X1 << 0) /**< Shifted mode X1 for BURTC_CFG */ +#define BURTC_CFG_COMPTOP (0x1UL << 1) /**< Compare Channel is Top Value */ +#define _BURTC_CFG_COMPTOP_SHIFT 1 /**< Shift value for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_MASK 0x2UL /**< Bit mask for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DEFAULT (_BURTC_CFG_COMPTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DISABLE (_BURTC_CFG_COMPTOP_DISABLE << 1) /**< Shifted mode DISABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_ENABLE (_BURTC_CFG_COMPTOP_ENABLE << 1) /**< Shifted mode ENABLE for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DEFAULT (_BURTC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1 (_BURTC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2 (_BURTC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4 (_BURTC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8 (_BURTC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16 (_BURTC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32 (_BURTC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV64 (_BURTC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV128 (_BURTC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV256 (_BURTC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV512 (_BURTC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1024 (_BURTC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2048 (_BURTC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4096 (_BURTC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8192 (_BURTC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16384 (_BURTC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32768 (_BURTC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for BURTC_CFG */ /* Bit fields for BURTC CMD */ -#define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */ -#define _BURTC_CMD_MASK 0x00000003UL /**< Mask for BURTC_CMD */ -#define BURTC_CMD_START (0x1UL << 0) /**< Start BURTC counter */ -#define _BURTC_CMD_START_SHIFT 0 /**< Shift value for BURTC_START */ -#define _BURTC_CMD_START_MASK 0x1UL /**< Bit mask for BURTC_START */ -#define _BURTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ -#define BURTC_CMD_START_DEFAULT (_BURTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */ -#define BURTC_CMD_STOP (0x1UL << 1) /**< Stop BURTC counter */ -#define _BURTC_CMD_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ -#define _BURTC_CMD_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ -#define _BURTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ -#define BURTC_CMD_STOP_DEFAULT (_BURTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CMD */ +#define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */ +#define _BURTC_CMD_MASK 0x00000003UL /**< Mask for BURTC_CMD */ +#define BURTC_CMD_START (0x1UL << 0) /**< Start BURTC counter */ +#define _BURTC_CMD_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_CMD_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_START_DEFAULT (_BURTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP (0x1UL << 1) /**< Stop BURTC counter */ +#define _BURTC_CMD_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_CMD_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP_DEFAULT (_BURTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CMD */ /* Bit fields for BURTC STATUS */ -#define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */ -#define _BURTC_STATUS_MASK 0x00000003UL /**< Mask for BURTC_STATUS */ -#define BURTC_STATUS_RUNNING (0x1UL << 0) /**< BURTC running status */ -#define _BURTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for BURTC_RUNNING */ -#define _BURTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for BURTC_RUNNING */ -#define _BURTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ -#define BURTC_STATUS_RUNNING_DEFAULT (_BURTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */ -#define BURTC_STATUS_LOCK (0x1UL << 1) /**< Configuration Lock Status */ -#define _BURTC_STATUS_LOCK_SHIFT 1 /**< Shift value for BURTC_LOCK */ -#define _BURTC_STATUS_LOCK_MASK 0x2UL /**< Bit mask for BURTC_LOCK */ -#define _BURTC_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ -#define _BURTC_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_STATUS */ -#define _BURTC_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_STATUS */ -#define BURTC_STATUS_LOCK_DEFAULT (_BURTC_STATUS_LOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */ -#define BURTC_STATUS_LOCK_UNLOCKED (_BURTC_STATUS_LOCK_UNLOCKED << 1) /**< Shifted mode UNLOCKED for BURTC_STATUS */ -#define BURTC_STATUS_LOCK_LOCKED (_BURTC_STATUS_LOCK_LOCKED << 1) /**< Shifted mode LOCKED for BURTC_STATUS */ +#define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */ +#define _BURTC_STATUS_MASK 0x00000003UL /**< Mask for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING (0x1UL << 0) /**< BURTC running status */ +#define _BURTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING_DEFAULT (_BURTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK (0x1UL << 1) /**< Configuration Lock Status */ +#define _BURTC_STATUS_LOCK_SHIFT 1 /**< Shift value for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_MASK 0x2UL /**< Bit mask for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_DEFAULT (_BURTC_STATUS_LOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_UNLOCKED (_BURTC_STATUS_LOCK_UNLOCKED << 1) /**< Shifted mode UNLOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_LOCKED (_BURTC_STATUS_LOCK_LOCKED << 1) /**< Shifted mode LOCKED for BURTC_STATUS */ /* Bit fields for BURTC IF */ -#define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */ -#define _BURTC_IF_MASK 0x00000003UL /**< Mask for BURTC_IF */ -#define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ -#define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */ -#define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ -#define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ -#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */ -#define BURTC_IF_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ -#define _BURTC_IF_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ -#define _BURTC_IF_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ -#define _BURTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ -#define BURTC_IF_COMP_DEFAULT (_BURTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */ +#define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */ +#define _BURTC_IF_MASK 0x00000003UL /**< Mask for BURTC_IF */ +#define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IF_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IF_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP_DEFAULT (_BURTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */ /* Bit fields for BURTC IEN */ -#define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */ -#define _BURTC_IEN_MASK 0x00000003UL /**< Mask for BURTC_IEN */ -#define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ -#define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */ -#define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ -#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ -#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */ -#define BURTC_IEN_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ -#define _BURTC_IEN_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ -#define _BURTC_IEN_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ -#define _BURTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ -#define BURTC_IEN_COMP_DEFAULT (_BURTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */ +#define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */ +#define _BURTC_IEN_MASK 0x00000003UL /**< Mask for BURTC_IEN */ +#define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IEN_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IEN_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP_DEFAULT (_BURTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */ /* Bit fields for BURTC PRECNT */ -#define _BURTC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_PRECNT */ -#define _BURTC_PRECNT_MASK 0x00007FFFUL /**< Mask for BURTC_PRECNT */ -#define _BURTC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for BURTC_PRECNT */ -#define _BURTC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for BURTC_PRECNT */ -#define _BURTC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_PRECNT */ -#define BURTC_PRECNT_PRECNT_DEFAULT (_BURTC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_PRECNT */ +#define _BURTC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_PRECNT */ +#define _BURTC_PRECNT_MASK 0x00007FFFUL /**< Mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_PRECNT */ +#define BURTC_PRECNT_PRECNT_DEFAULT (_BURTC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_PRECNT */ /* Bit fields for BURTC CNT */ -#define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */ -#define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */ -#define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */ -#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */ -#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */ -#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */ +#define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */ +#define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */ +#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */ +#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */ /* Bit fields for BURTC EM4WUEN */ -#define _BURTC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EM4WUEN */ -#define _BURTC_EM4WUEN_MASK 0x00000003UL /**< Mask for BURTC_EM4WUEN */ -#define BURTC_EM4WUEN_OFEM4WUEN (0x1UL << 0) /**< Overflow EM4 Wakeup Enable */ -#define _BURTC_EM4WUEN_OFEM4WUEN_SHIFT 0 /**< Shift value for BURTC_OFEM4WUEN */ -#define _BURTC_EM4WUEN_OFEM4WUEN_MASK 0x1UL /**< Bit mask for BURTC_OFEM4WUEN */ -#define _BURTC_EM4WUEN_OFEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ -#define BURTC_EM4WUEN_OFEM4WUEN_DEFAULT (_BURTC_EM4WUEN_OFEM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ -#define BURTC_EM4WUEN_COMPEM4WUEN (0x1UL << 1) /**< Compare Match EM4 Wakeup Enable */ -#define _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT 1 /**< Shift value for BURTC_COMPEM4WUEN */ -#define _BURTC_EM4WUEN_COMPEM4WUEN_MASK 0x2UL /**< Bit mask for BURTC_COMPEM4WUEN */ -#define _BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ -#define BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT (_BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ +#define _BURTC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EM4WUEN */ +#define _BURTC_EM4WUEN_MASK 0x00000003UL /**< Mask for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN (0x1UL << 0) /**< Overflow EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_OFEM4WUEN_SHIFT 0 /**< Shift value for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_MASK 0x1UL /**< Bit mask for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN_DEFAULT (_BURTC_EM4WUEN_OFEM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN (0x1UL << 1) /**< Compare Match EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT 1 /**< Shift value for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_MASK 0x2UL /**< Bit mask for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT (_BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ /* Bit fields for BURTC SYNCBUSY */ -#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */ -#define _BURTC_SYNCBUSY_MASK 0x0000001FUL /**< Mask for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ -#define _BURTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for BURTC_START */ -#define _BURTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for BURTC_START */ -#define _BURTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_START_DEFAULT (_BURTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ -#define _BURTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ -#define _BURTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ -#define _BURTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_STOP_DEFAULT (_BURTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ -#define _BURTC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for BURTC_PRECNT */ -#define _BURTC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for BURTC_PRECNT */ -#define _BURTC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_PRECNT_DEFAULT (_BURTC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ -#define _BURTC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for BURTC_CNT */ -#define _BURTC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for BURTC_CNT */ -#define _BURTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_CNT_DEFAULT (_BURTC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_COMP (0x1UL << 4) /**< Sync busy for COMP */ -#define _BURTC_SYNCBUSY_COMP_SHIFT 4 /**< Shift value for BURTC_COMP */ -#define _BURTC_SYNCBUSY_COMP_MASK 0x10UL /**< Bit mask for BURTC_COMP */ -#define _BURTC_SYNCBUSY_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_COMP_DEFAULT (_BURTC_SYNCBUSY_COMP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */ +#define _BURTC_SYNCBUSY_MASK 0x0000001FUL /**< Mask for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ +#define _BURTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START_DEFAULT (_BURTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ +#define _BURTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP_DEFAULT (_BURTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT_DEFAULT (_BURTC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ +#define _BURTC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT_DEFAULT (_BURTC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP (0x1UL << 4) /**< Sync busy for COMP */ +#define _BURTC_SYNCBUSY_COMP_SHIFT 4 /**< Shift value for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_MASK 0x10UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP_DEFAULT (_BURTC_SYNCBUSY_COMP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ /* Bit fields for BURTC LOCK */ -#define _BURTC_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for BURTC_LOCK */ -#define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */ -#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */ -#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */ -#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for BURTC_LOCK */ -#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */ -#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */ -#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */ +#define _BURTC_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for BURTC_LOCK */ +#define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */ /* Bit fields for BURTC COMP */ -#define _BURTC_COMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP */ -#define _BURTC_COMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP */ -#define _BURTC_COMP_COMP_SHIFT 0 /**< Shift value for BURTC_COMP */ -#define _BURTC_COMP_COMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP */ -#define _BURTC_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP */ -#define BURTC_COMP_COMP_DEFAULT (_BURTC_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP */ +#define _BURTC_COMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP */ +#define _BURTC_COMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_SHIFT 0 /**< Shift value for BURTC_COMP */ +#define _BURTC_COMP_COMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP */ +#define BURTC_COMP_COMP_DEFAULT (_BURTC_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP */ /** @} End of group EFR32SG23_BURTC_BitFields */ /** @} End of group EFR32SG23_BURTC */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_cmu.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_cmu.h index f37302d272..1c848c4ea6 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_cmu.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_cmu.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_CMU_H #define EFR32SG23_CMU_H - #define CMU_HAS_SET_CLEAR /**************************************************************************//** @@ -43,223 +42,222 @@ *****************************************************************************/ /** CMU Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version ID */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - __IOM uint32_t WDOGLOCK; /**< WDOG Configuration Lock Register */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED3[10U]; /**< Reserved for future use */ - __IOM uint32_t CALCMD; /**< Calibration Command Register */ - __IOM uint32_t CALCTRL; /**< Calibration Control Register */ - __IM uint32_t CALCNT; /**< Calibration Result Counter Register */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t CLKEN0; /**< Clock Enable Register 0 */ - __IOM uint32_t CLKEN1; /**< Clock Enable Register 1 */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IOM uint32_t SYSCLKCTRL; /**< System Clock Control */ - uint32_t RESERVED6[3U]; /**< Reserved for future use */ - __IOM uint32_t TRACECLKCTRL; /**< Debug Trace Clock Control */ - uint32_t RESERVED7[3U]; /**< Reserved for future use */ - __IOM uint32_t EXPORTCLKCTRL; /**< Export Clock Control */ - uint32_t RESERVED8[27U]; /**< Reserved for future use */ - __IOM uint32_t DPLLREFCLKCTRL; /**< Digital PLL Reference Clock Control */ - uint32_t RESERVED9[7U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPACLKCTRL; /**< EM01 Peripheral Group A Clock Control */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPCCLKCTRL; /**< EM01 Peripheral Group C Clock Control */ - uint32_t RESERVED11[5U]; /**< Reserved for future use */ - __IOM uint32_t EM23GRPACLKCTRL; /**< EM23 Peripheral Group A Clock Control */ - uint32_t RESERVED12[7U]; /**< Reserved for future use */ - __IOM uint32_t EM4GRPACLKCTRL; /**< EM4 Peripheral Group A Clock Control */ - uint32_t RESERVED13[7U]; /**< Reserved for future use */ - __IOM uint32_t IADCCLKCTRL; /**< IADC Clock Control */ - uint32_t RESERVED14[31U]; /**< Reserved for future use */ - __IOM uint32_t WDOG0CLKCTRL; /**< Watchdog0 Clock Control */ - uint32_t RESERVED15[1U]; /**< Reserved for future use */ - __IOM uint32_t WDOG1CLKCTRL; /**< Watchdog1 Clock Control */ - uint32_t RESERVED16[5U]; /**< Reserved for future use */ - __IOM uint32_t EUSART0CLKCTRL; /**< EUSART0 Clock Control */ - uint32_t RESERVED17[7U]; /**< Reserved for future use */ - __IOM uint32_t SYSRTC0CLKCTRL; /**< System RTC0 Clock Control */ - uint32_t RESERVED18[3U]; /**< Reserved for future use */ - __IOM uint32_t LCDCLKCTRL; /**< LCD Clock Control */ - uint32_t RESERVED19[3U]; /**< Reserved for future use */ - __IOM uint32_t VDAC0CLKCTRL; /**< VDAC0 Clock Control */ - uint32_t RESERVED20[3U]; /**< Reserved for future use */ - __IOM uint32_t PCNT0CLKCTRL; /**< Pulse counter 0 Clock Control */ - uint32_t RESERVED21[3U]; /**< Reserved for future use */ - __IOM uint32_t RADIOCLKCTRL; /**< Radio Clock Control */ - uint32_t RESERVED22[3U]; /**< Reserved for future use */ - __IOM uint32_t LESENSEHFCLKCTRL; /**< LESENSE HF Clock Control */ - uint32_t RESERVED23[1U]; /**< Reserved for future use */ - uint32_t RESERVED24[858U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - uint32_t RESERVED25[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - uint32_t RESERVED26[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - __IOM uint32_t WDOGLOCK_SET; /**< WDOG Configuration Lock Register */ - uint32_t RESERVED27[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED28[10U]; /**< Reserved for future use */ - __IOM uint32_t CALCMD_SET; /**< Calibration Command Register */ - __IOM uint32_t CALCTRL_SET; /**< Calibration Control Register */ - __IM uint32_t CALCNT_SET; /**< Calibration Result Counter Register */ - uint32_t RESERVED29[2U]; /**< Reserved for future use */ - __IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 */ - __IOM uint32_t CLKEN1_SET; /**< Clock Enable Register 1 */ - uint32_t RESERVED30[1U]; /**< Reserved for future use */ - __IOM uint32_t SYSCLKCTRL_SET; /**< System Clock Control */ - uint32_t RESERVED31[3U]; /**< Reserved for future use */ - __IOM uint32_t TRACECLKCTRL_SET; /**< Debug Trace Clock Control */ - uint32_t RESERVED32[3U]; /**< Reserved for future use */ - __IOM uint32_t EXPORTCLKCTRL_SET; /**< Export Clock Control */ - uint32_t RESERVED33[27U]; /**< Reserved for future use */ - __IOM uint32_t DPLLREFCLKCTRL_SET; /**< Digital PLL Reference Clock Control */ - uint32_t RESERVED34[7U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPACLKCTRL_SET; /**< EM01 Peripheral Group A Clock Control */ - uint32_t RESERVED35[1U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPCCLKCTRL_SET; /**< EM01 Peripheral Group C Clock Control */ - uint32_t RESERVED36[5U]; /**< Reserved for future use */ - __IOM uint32_t EM23GRPACLKCTRL_SET; /**< EM23 Peripheral Group A Clock Control */ - uint32_t RESERVED37[7U]; /**< Reserved for future use */ - __IOM uint32_t EM4GRPACLKCTRL_SET; /**< EM4 Peripheral Group A Clock Control */ - uint32_t RESERVED38[7U]; /**< Reserved for future use */ - __IOM uint32_t IADCCLKCTRL_SET; /**< IADC Clock Control */ - uint32_t RESERVED39[31U]; /**< Reserved for future use */ - __IOM uint32_t WDOG0CLKCTRL_SET; /**< Watchdog0 Clock Control */ - uint32_t RESERVED40[1U]; /**< Reserved for future use */ - __IOM uint32_t WDOG1CLKCTRL_SET; /**< Watchdog1 Clock Control */ - uint32_t RESERVED41[5U]; /**< Reserved for future use */ - __IOM uint32_t EUSART0CLKCTRL_SET; /**< EUSART0 Clock Control */ - uint32_t RESERVED42[7U]; /**< Reserved for future use */ - __IOM uint32_t SYSRTC0CLKCTRL_SET; /**< System RTC0 Clock Control */ - uint32_t RESERVED43[3U]; /**< Reserved for future use */ - __IOM uint32_t LCDCLKCTRL_SET; /**< LCD Clock Control */ - uint32_t RESERVED44[3U]; /**< Reserved for future use */ - __IOM uint32_t VDAC0CLKCTRL_SET; /**< VDAC0 Clock Control */ - uint32_t RESERVED45[3U]; /**< Reserved for future use */ - __IOM uint32_t PCNT0CLKCTRL_SET; /**< Pulse counter 0 Clock Control */ - uint32_t RESERVED46[3U]; /**< Reserved for future use */ - __IOM uint32_t RADIOCLKCTRL_SET; /**< Radio Clock Control */ - uint32_t RESERVED47[3U]; /**< Reserved for future use */ - __IOM uint32_t LESENSEHFCLKCTRL_SET; /**< LESENSE HF Clock Control */ - uint32_t RESERVED48[1U]; /**< Reserved for future use */ - uint32_t RESERVED49[858U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - uint32_t RESERVED50[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - uint32_t RESERVED51[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - __IOM uint32_t WDOGLOCK_CLR; /**< WDOG Configuration Lock Register */ - uint32_t RESERVED52[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED53[10U]; /**< Reserved for future use */ - __IOM uint32_t CALCMD_CLR; /**< Calibration Command Register */ - __IOM uint32_t CALCTRL_CLR; /**< Calibration Control Register */ - __IM uint32_t CALCNT_CLR; /**< Calibration Result Counter Register */ - uint32_t RESERVED54[2U]; /**< Reserved for future use */ - __IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 */ - __IOM uint32_t CLKEN1_CLR; /**< Clock Enable Register 1 */ - uint32_t RESERVED55[1U]; /**< Reserved for future use */ - __IOM uint32_t SYSCLKCTRL_CLR; /**< System Clock Control */ - uint32_t RESERVED56[3U]; /**< Reserved for future use */ - __IOM uint32_t TRACECLKCTRL_CLR; /**< Debug Trace Clock Control */ - uint32_t RESERVED57[3U]; /**< Reserved for future use */ - __IOM uint32_t EXPORTCLKCTRL_CLR; /**< Export Clock Control */ - uint32_t RESERVED58[27U]; /**< Reserved for future use */ - __IOM uint32_t DPLLREFCLKCTRL_CLR; /**< Digital PLL Reference Clock Control */ - uint32_t RESERVED59[7U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPACLKCTRL_CLR; /**< EM01 Peripheral Group A Clock Control */ - uint32_t RESERVED60[1U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPCCLKCTRL_CLR; /**< EM01 Peripheral Group C Clock Control */ - uint32_t RESERVED61[5U]; /**< Reserved for future use */ - __IOM uint32_t EM23GRPACLKCTRL_CLR; /**< EM23 Peripheral Group A Clock Control */ - uint32_t RESERVED62[7U]; /**< Reserved for future use */ - __IOM uint32_t EM4GRPACLKCTRL_CLR; /**< EM4 Peripheral Group A Clock Control */ - uint32_t RESERVED63[7U]; /**< Reserved for future use */ - __IOM uint32_t IADCCLKCTRL_CLR; /**< IADC Clock Control */ - uint32_t RESERVED64[31U]; /**< Reserved for future use */ - __IOM uint32_t WDOG0CLKCTRL_CLR; /**< Watchdog0 Clock Control */ - uint32_t RESERVED65[1U]; /**< Reserved for future use */ - __IOM uint32_t WDOG1CLKCTRL_CLR; /**< Watchdog1 Clock Control */ - uint32_t RESERVED66[5U]; /**< Reserved for future use */ - __IOM uint32_t EUSART0CLKCTRL_CLR; /**< EUSART0 Clock Control */ - uint32_t RESERVED67[7U]; /**< Reserved for future use */ - __IOM uint32_t SYSRTC0CLKCTRL_CLR; /**< System RTC0 Clock Control */ - uint32_t RESERVED68[3U]; /**< Reserved for future use */ - __IOM uint32_t LCDCLKCTRL_CLR; /**< LCD Clock Control */ - uint32_t RESERVED69[3U]; /**< Reserved for future use */ - __IOM uint32_t VDAC0CLKCTRL_CLR; /**< VDAC0 Clock Control */ - uint32_t RESERVED70[3U]; /**< Reserved for future use */ - __IOM uint32_t PCNT0CLKCTRL_CLR; /**< Pulse counter 0 Clock Control */ - uint32_t RESERVED71[3U]; /**< Reserved for future use */ - __IOM uint32_t RADIOCLKCTRL_CLR; /**< Radio Clock Control */ - uint32_t RESERVED72[3U]; /**< Reserved for future use */ - __IOM uint32_t LESENSEHFCLKCTRL_CLR; /**< LESENSE HF Clock Control */ - uint32_t RESERVED73[1U]; /**< Reserved for future use */ - uint32_t RESERVED74[858U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - uint32_t RESERVED75[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - uint32_t RESERVED76[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - __IOM uint32_t WDOGLOCK_TGL; /**< WDOG Configuration Lock Register */ - uint32_t RESERVED77[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED78[10U]; /**< Reserved for future use */ - __IOM uint32_t CALCMD_TGL; /**< Calibration Command Register */ - __IOM uint32_t CALCTRL_TGL; /**< Calibration Control Register */ - __IM uint32_t CALCNT_TGL; /**< Calibration Result Counter Register */ - uint32_t RESERVED79[2U]; /**< Reserved for future use */ - __IOM uint32_t CLKEN0_TGL; /**< Clock Enable Register 0 */ - __IOM uint32_t CLKEN1_TGL; /**< Clock Enable Register 1 */ - uint32_t RESERVED80[1U]; /**< Reserved for future use */ - __IOM uint32_t SYSCLKCTRL_TGL; /**< System Clock Control */ - uint32_t RESERVED81[3U]; /**< Reserved for future use */ - __IOM uint32_t TRACECLKCTRL_TGL; /**< Debug Trace Clock Control */ - uint32_t RESERVED82[3U]; /**< Reserved for future use */ - __IOM uint32_t EXPORTCLKCTRL_TGL; /**< Export Clock Control */ - uint32_t RESERVED83[27U]; /**< Reserved for future use */ - __IOM uint32_t DPLLREFCLKCTRL_TGL; /**< Digital PLL Reference Clock Control */ - uint32_t RESERVED84[7U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPACLKCTRL_TGL; /**< EM01 Peripheral Group A Clock Control */ - uint32_t RESERVED85[1U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPCCLKCTRL_TGL; /**< EM01 Peripheral Group C Clock Control */ - uint32_t RESERVED86[5U]; /**< Reserved for future use */ - __IOM uint32_t EM23GRPACLKCTRL_TGL; /**< EM23 Peripheral Group A Clock Control */ - uint32_t RESERVED87[7U]; /**< Reserved for future use */ - __IOM uint32_t EM4GRPACLKCTRL_TGL; /**< EM4 Peripheral Group A Clock Control */ - uint32_t RESERVED88[7U]; /**< Reserved for future use */ - __IOM uint32_t IADCCLKCTRL_TGL; /**< IADC Clock Control */ - uint32_t RESERVED89[31U]; /**< Reserved for future use */ - __IOM uint32_t WDOG0CLKCTRL_TGL; /**< Watchdog0 Clock Control */ - uint32_t RESERVED90[1U]; /**< Reserved for future use */ - __IOM uint32_t WDOG1CLKCTRL_TGL; /**< Watchdog1 Clock Control */ - uint32_t RESERVED91[5U]; /**< Reserved for future use */ - __IOM uint32_t EUSART0CLKCTRL_TGL; /**< EUSART0 Clock Control */ - uint32_t RESERVED92[7U]; /**< Reserved for future use */ - __IOM uint32_t SYSRTC0CLKCTRL_TGL; /**< System RTC0 Clock Control */ - uint32_t RESERVED93[3U]; /**< Reserved for future use */ - __IOM uint32_t LCDCLKCTRL_TGL; /**< LCD Clock Control */ - uint32_t RESERVED94[3U]; /**< Reserved for future use */ - __IOM uint32_t VDAC0CLKCTRL_TGL; /**< VDAC0 Clock Control */ - uint32_t RESERVED95[3U]; /**< Reserved for future use */ - __IOM uint32_t PCNT0CLKCTRL_TGL; /**< Pulse counter 0 Clock Control */ - uint32_t RESERVED96[3U]; /**< Reserved for future use */ - __IOM uint32_t RADIOCLKCTRL_TGL; /**< Radio Clock Control */ - uint32_t RESERVED97[3U]; /**< Reserved for future use */ - __IOM uint32_t LESENSEHFCLKCTRL_TGL; /**< LESENSE HF Clock Control */ - uint32_t RESERVED98[1U]; /**< Reserved for future use */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED3[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IM uint32_t CALCNT; /**< Calibration Result Counter Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1; /**< Clock Enable Register 1 */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL; /**< System Clock Control */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL; /**< Debug Trace Clock Control */ + uint32_t RESERVED7[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL; /**< Export Clock Control */ + uint32_t RESERVED8[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED11[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL; /**< IADC Clock Control */ + uint32_t RESERVED14[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL; /**< Watchdog1 Clock Control */ + uint32_t RESERVED16[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL; /**< EUSART0 Clock Control */ + uint32_t RESERVED17[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL; /**< System RTC0 Clock Control */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCLKCTRL; /**< LCD Clock Control */ + uint32_t RESERVED19[3U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL; /**< VDAC0 Clock Control */ + uint32_t RESERVED20[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED21[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL; /**< Radio Clock Control */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + __IOM uint32_t LESENSEHFCLKCTRL; /**< LESENSE HF Clock Control */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + uint32_t RESERVED24[858U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_SET; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED27[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED28[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_SET; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_SET; /**< Calibration Control Register */ + __IM uint32_t CALCNT_SET; /**< Calibration Result Counter Register */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_SET; /**< Clock Enable Register 1 */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_SET; /**< System Clock Control */ + uint32_t RESERVED31[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_SET; /**< Debug Trace Clock Control */ + uint32_t RESERVED32[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_SET; /**< Export Clock Control */ + uint32_t RESERVED33[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_SET; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED34[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_SET; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_SET; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED36[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_SET; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED37[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_SET; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED38[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_SET; /**< IADC Clock Control */ + uint32_t RESERVED39[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_SET; /**< Watchdog0 Clock Control */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_SET; /**< Watchdog1 Clock Control */ + uint32_t RESERVED41[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_SET; /**< EUSART0 Clock Control */ + uint32_t RESERVED42[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_SET; /**< System RTC0 Clock Control */ + uint32_t RESERVED43[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCLKCTRL_SET; /**< LCD Clock Control */ + uint32_t RESERVED44[3U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_SET; /**< VDAC0 Clock Control */ + uint32_t RESERVED45[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_SET; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED46[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_SET; /**< Radio Clock Control */ + uint32_t RESERVED47[3U]; /**< Reserved for future use */ + __IOM uint32_t LESENSEHFCLKCTRL_SET; /**< LESENSE HF Clock Control */ + uint32_t RESERVED48[1U]; /**< Reserved for future use */ + uint32_t RESERVED49[858U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED50[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED51[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_CLR; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED52[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED53[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_CLR; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_CLR; /**< Calibration Control Register */ + __IM uint32_t CALCNT_CLR; /**< Calibration Result Counter Register */ + uint32_t RESERVED54[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_CLR; /**< Clock Enable Register 1 */ + uint32_t RESERVED55[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_CLR; /**< System Clock Control */ + uint32_t RESERVED56[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_CLR; /**< Debug Trace Clock Control */ + uint32_t RESERVED57[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_CLR; /**< Export Clock Control */ + uint32_t RESERVED58[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_CLR; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED59[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_CLR; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED60[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_CLR; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED61[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_CLR; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED62[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_CLR; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED63[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_CLR; /**< IADC Clock Control */ + uint32_t RESERVED64[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_CLR; /**< Watchdog0 Clock Control */ + uint32_t RESERVED65[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_CLR; /**< Watchdog1 Clock Control */ + uint32_t RESERVED66[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_CLR; /**< EUSART0 Clock Control */ + uint32_t RESERVED67[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_CLR; /**< System RTC0 Clock Control */ + uint32_t RESERVED68[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCLKCTRL_CLR; /**< LCD Clock Control */ + uint32_t RESERVED69[3U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_CLR; /**< VDAC0 Clock Control */ + uint32_t RESERVED70[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_CLR; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED71[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_CLR; /**< Radio Clock Control */ + uint32_t RESERVED72[3U]; /**< Reserved for future use */ + __IOM uint32_t LESENSEHFCLKCTRL_CLR; /**< LESENSE HF Clock Control */ + uint32_t RESERVED73[1U]; /**< Reserved for future use */ + uint32_t RESERVED74[858U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED75[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED76[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_TGL; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED77[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED78[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_TGL; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_TGL; /**< Calibration Control Register */ + __IM uint32_t CALCNT_TGL; /**< Calibration Result Counter Register */ + uint32_t RESERVED79[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_TGL; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_TGL; /**< Clock Enable Register 1 */ + uint32_t RESERVED80[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_TGL; /**< System Clock Control */ + uint32_t RESERVED81[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_TGL; /**< Debug Trace Clock Control */ + uint32_t RESERVED82[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_TGL; /**< Export Clock Control */ + uint32_t RESERVED83[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_TGL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED84[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_TGL; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED85[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_TGL; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED86[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_TGL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED87[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_TGL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED88[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_TGL; /**< IADC Clock Control */ + uint32_t RESERVED89[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_TGL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED90[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_TGL; /**< Watchdog1 Clock Control */ + uint32_t RESERVED91[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_TGL; /**< EUSART0 Clock Control */ + uint32_t RESERVED92[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_TGL; /**< System RTC0 Clock Control */ + uint32_t RESERVED93[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCLKCTRL_TGL; /**< LCD Clock Control */ + uint32_t RESERVED94[3U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_TGL; /**< VDAC0 Clock Control */ + uint32_t RESERVED95[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_TGL; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED96[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_TGL; /**< Radio Clock Control */ + uint32_t RESERVED97[3U]; /**< Reserved for future use */ + __IOM uint32_t LESENSEHFCLKCTRL_TGL; /**< LESENSE HF Clock Control */ + uint32_t RESERVED98[1U]; /**< Reserved for future use */ } CMU_TypeDef; /** @} End of group EFR32SG23_CMU */ @@ -271,857 +269,857 @@ typedef struct *****************************************************************************/ /* Bit fields for CMU IPVERSION */ -#define _CMU_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for CMU_IPVERSION */ -#define _CMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for CMU_IPVERSION */ -#define _CMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for CMU_IPVERSION */ -#define _CMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for CMU_IPVERSION */ -#define _CMU_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_IPVERSION */ -#define CMU_IPVERSION_IPVERSION_DEFAULT (_CMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IPVERSION */ +#define _CMU_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for CMU_IPVERSION */ +#define _CMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_IPVERSION */ +#define CMU_IPVERSION_IPVERSION_DEFAULT (_CMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IPVERSION */ /* Bit fields for CMU STATUS */ -#define _CMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_STATUS */ -#define _CMU_STATUS_MASK 0xC0038001UL /**< Mask for CMU_STATUS */ -#define CMU_STATUS_CALRDY (0x1UL << 0) /**< Calibration Ready */ -#define _CMU_STATUS_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ -#define _CMU_STATUS_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ -#define _CMU_STATUS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ -#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ -#define CMU_STATUS_WDOGLOCK (0x1UL << 30) /**< Configuration Lock Status for WDOG */ -#define _CMU_STATUS_WDOGLOCK_SHIFT 30 /**< Shift value for CMU_WDOGLOCK */ -#define _CMU_STATUS_WDOGLOCK_MASK 0x40000000UL /**< Bit mask for CMU_WDOGLOCK */ -#define _CMU_STATUS_WDOGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ -#define _CMU_STATUS_WDOGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ -#define _CMU_STATUS_WDOGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ -#define CMU_STATUS_WDOGLOCK_DEFAULT (_CMU_STATUS_WDOGLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_STATUS */ -#define CMU_STATUS_WDOGLOCK_UNLOCKED (_CMU_STATUS_WDOGLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for CMU_STATUS */ -#define CMU_STATUS_WDOGLOCK_LOCKED (_CMU_STATUS_WDOGLOCK_LOCKED << 30) /**< Shifted mode LOCKED for CMU_STATUS */ -#define CMU_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ -#define _CMU_STATUS_LOCK_SHIFT 31 /**< Shift value for CMU_LOCK */ -#define _CMU_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for CMU_LOCK */ -#define _CMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ -#define _CMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ -#define _CMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ -#define CMU_STATUS_LOCK_DEFAULT (_CMU_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_STATUS */ -#define CMU_STATUS_LOCK_UNLOCKED (_CMU_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for CMU_STATUS */ -#define CMU_STATUS_LOCK_LOCKED (_CMU_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for CMU_STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0xC0038001UL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 0) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK (0x1UL << 30) /**< Configuration Lock Status for WDOG */ +#define _CMU_STATUS_WDOGLOCK_SHIFT 30 /**< Shift value for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_MASK 0x40000000UL /**< Bit mask for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_DEFAULT (_CMU_STATUS_WDOGLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_UNLOCKED (_CMU_STATUS_WDOGLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_LOCKED (_CMU_STATUS_WDOGLOCK_LOCKED << 30) /**< Shifted mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _CMU_STATUS_LOCK_SHIFT 31 /**< Shift value for CMU_LOCK */ +#define _CMU_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for CMU_LOCK */ +#define _CMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_DEFAULT (_CMU_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LOCK_UNLOCKED (_CMU_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_LOCKED (_CMU_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for CMU_STATUS */ /* Bit fields for CMU LOCK */ -#define _CMU_LOCK_RESETVALUE 0x000093F7UL /**< Default value for CMU_LOCK */ -#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ -#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ -#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ -#define _CMU_LOCK_LOCKKEY_DEFAULT 0x000093F7UL /**< Mode DEFAULT for CMU_LOCK */ -#define _CMU_LOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_LOCK */ -#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ -#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ +#define _CMU_LOCK_RESETVALUE 0x000093F7UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x000093F7UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ /* Bit fields for CMU WDOGLOCK */ -#define _CMU_WDOGLOCK_RESETVALUE 0x00005257UL /**< Default value for CMU_WDOGLOCK */ -#define _CMU_WDOGLOCK_MASK 0x0000FFFFUL /**< Mask for CMU_WDOGLOCK */ -#define _CMU_WDOGLOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ -#define _CMU_WDOGLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ -#define _CMU_WDOGLOCK_LOCKKEY_DEFAULT 0x00005257UL /**< Mode DEFAULT for CMU_WDOGLOCK */ -#define _CMU_WDOGLOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_WDOGLOCK */ -#define CMU_WDOGLOCK_LOCKKEY_DEFAULT (_CMU_WDOGLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOGLOCK */ -#define CMU_WDOGLOCK_LOCKKEY_UNLOCK (_CMU_WDOGLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_RESETVALUE 0x00005257UL /**< Default value for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_MASK 0x0000FFFFUL /**< Mask for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_DEFAULT 0x00005257UL /**< Mode DEFAULT for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_DEFAULT (_CMU_WDOGLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_UNLOCK (_CMU_WDOGLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_WDOGLOCK */ /* Bit fields for CMU IF */ -#define _CMU_IF_RESETVALUE 0x00000000UL /**< Default value for CMU_IF */ -#define _CMU_IF_MASK 0x00000003UL /**< Mask for CMU_IF */ -#define CMU_IF_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Flag */ -#define _CMU_IF_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ -#define _CMU_IF_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ -#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ -#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ -#define CMU_IF_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Flag */ -#define _CMU_IF_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ -#define _CMU_IF_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ -#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ -#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define _CMU_IF_RESETVALUE 0x00000000UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0x00000003UL /**< Mask for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ /* Bit fields for CMU IEN */ -#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ -#define _CMU_IEN_MASK 0x00000003UL /**< Mask for CMU_IEN */ -#define CMU_IEN_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Enable */ -#define _CMU_IEN_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ -#define _CMU_IEN_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ -#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ -#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ -#define CMU_IEN_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Enable */ -#define _CMU_IEN_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ -#define _CMU_IEN_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ -#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ -#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0x00000003UL /**< Mask for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ /* Bit fields for CMU CALCMD */ -#define _CMU_CALCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCMD */ -#define _CMU_CALCMD_MASK 0x00000003UL /**< Mask for CMU_CALCMD */ -#define CMU_CALCMD_CALSTART (0x1UL << 0) /**< Calibration Start */ -#define _CMU_CALCMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ -#define _CMU_CALCMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ -#define _CMU_CALCMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ -#define CMU_CALCMD_CALSTART_DEFAULT (_CMU_CALCMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCMD */ -#define CMU_CALCMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ -#define _CMU_CALCMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ -#define _CMU_CALCMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ -#define _CMU_CALCMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ -#define CMU_CALCMD_CALSTOP_DEFAULT (_CMU_CALCMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CALCMD */ +#define _CMU_CALCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCMD */ +#define _CMU_CALCMD_MASK 0x00000003UL /**< Mask for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CALCMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART_DEFAULT (_CMU_CALCMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CALCMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP_DEFAULT (_CMU_CALCMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CALCMD */ /* Bit fields for CMU CALCTRL */ -#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ -#define _CMU_CALCTRL_MASK 0xFF8FFFFFUL /**< Mask for CMU_CALCTRL */ -#define _CMU_CALCTRL_CALTOP_SHIFT 0 /**< Shift value for CMU_CALTOP */ -#define _CMU_CALCTRL_CALTOP_MASK 0xFFFFFUL /**< Bit mask for CMU_CALTOP */ -#define _CMU_CALCTRL_CALTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_CALTOP_DEFAULT (_CMU_CALCTRL_CALTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_CONT (0x1UL << 23) /**< Continuous Calibration */ -#define _CMU_CALCTRL_CONT_SHIFT 23 /**< Shift value for CMU_CONT */ -#define _CMU_CALCTRL_CONT_MASK 0x800000UL /**< Bit mask for CMU_CONT */ -#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_SHIFT 24 /**< Shift value for CMU_UPSEL */ -#define _CMU_CALCTRL_UPSEL_MASK 0xF000000UL /**< Bit mask for CMU_UPSEL */ -#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_PRS 0x00000001UL /**< Mode PRS for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_LFXO 0x00000003UL /**< Mode LFXO for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_HFRCODPLL 0x00000004UL /**< Mode HFRCODPLL for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_HFRCOEM23 0x00000005UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000009UL /**< Mode LFRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_ULFRCO 0x0000000AUL /**< Mode ULFRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_DISABLED (_CMU_CALCTRL_UPSEL_DISABLED << 24) /**< Shifted mode DISABLED for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 24) /**< Shifted mode PRS for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 24) /**< Shifted mode HFXO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 24) /**< Shifted mode LFXO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_HFRCODPLL (_CMU_CALCTRL_UPSEL_HFRCODPLL << 24) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_HFRCOEM23 (_CMU_CALCTRL_UPSEL_HFRCOEM23 << 24) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_FSRCO (_CMU_CALCTRL_UPSEL_FSRCO << 24) /**< Shifted mode FSRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 24) /**< Shifted mode LFRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_ULFRCO (_CMU_CALCTRL_UPSEL_ULFRCO << 24) /**< Shifted mode ULFRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_SHIFT 28 /**< Shift value for CMU_DOWNSEL */ -#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0000000UL /**< Bit mask for CMU_DOWNSEL */ -#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_HCLK 0x00000001UL /**< Mode HCLK for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000002UL /**< Mode PRS for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_HFRCODPLL 0x00000005UL /**< Mode HFRCODPLL for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_HFRCOEM23 0x00000006UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x0000000AUL /**< Mode LFRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_ULFRCO 0x0000000BUL /**< Mode ULFRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_DISABLED (_CMU_CALCTRL_DOWNSEL_DISABLED << 28) /**< Shifted mode DISABLED for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_HCLK (_CMU_CALCTRL_DOWNSEL_HCLK << 28) /**< Shifted mode HCLK for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 28) /**< Shifted mode PRS for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 28) /**< Shifted mode HFXO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 28) /**< Shifted mode LFXO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_HFRCODPLL (_CMU_CALCTRL_DOWNSEL_HFRCODPLL << 28) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_HFRCOEM23 (_CMU_CALCTRL_DOWNSEL_HFRCOEM23 << 28) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_FSRCO (_CMU_CALCTRL_DOWNSEL_FSRCO << 28) /**< Shifted mode FSRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 28) /**< Shifted mode LFRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_ULFRCO (_CMU_CALCTRL_DOWNSEL_ULFRCO << 28) /**< Shifted mode ULFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0xFF8FFFFFUL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_CALTOP_SHIFT 0 /**< Shift value for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_MASK 0xFFFFFUL /**< Bit mask for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CALTOP_DEFAULT (_CMU_CALCTRL_CALTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 23) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 23 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x800000UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 24 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0xF000000UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000001UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000003UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCODPLL 0x00000004UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCOEM23 0x00000005UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000009UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_ULFRCO 0x0000000AUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DISABLED (_CMU_CALCTRL_UPSEL_DISABLED << 24) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 24) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 24) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 24) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCODPLL (_CMU_CALCTRL_UPSEL_HFRCODPLL << 24) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCOEM23 (_CMU_CALCTRL_UPSEL_HFRCOEM23 << 24) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_FSRCO (_CMU_CALCTRL_UPSEL_FSRCO << 24) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 24) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_ULFRCO (_CMU_CALCTRL_UPSEL_ULFRCO << 24) /**< Shifted mode ULFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 28 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0000000UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HCLK 0x00000001UL /**< Mode HCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000002UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCODPLL 0x00000005UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCOEM23 0x00000006UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x0000000AUL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_ULFRCO 0x0000000BUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DISABLED (_CMU_CALCTRL_DOWNSEL_DISABLED << 28) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HCLK (_CMU_CALCTRL_DOWNSEL_HCLK << 28) /**< Shifted mode HCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 28) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 28) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 28) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCODPLL (_CMU_CALCTRL_DOWNSEL_HFRCODPLL << 28) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCOEM23 (_CMU_CALCTRL_DOWNSEL_HFRCOEM23 << 28) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_FSRCO (_CMU_CALCTRL_DOWNSEL_FSRCO << 28) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 28) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_ULFRCO (_CMU_CALCTRL_DOWNSEL_ULFRCO << 28) /**< Shifted mode ULFRCO for CMU_CALCTRL */ /* Bit fields for CMU CALCNT */ -#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ -#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ -#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ -#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ -#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ -#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ /* Bit fields for CMU CLKEN0 */ -#define _CMU_CLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN0 */ -#define _CMU_CLKEN0_MASK 0xFFFFFFFFUL /**< Mask for CMU_CLKEN0 */ -#define CMU_CLKEN0_LDMA (0x1UL << 0) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LDMA_SHIFT 0 /**< Shift value for CMU_LDMA */ -#define _CMU_CLKEN0_LDMA_MASK 0x1UL /**< Bit mask for CMU_LDMA */ -#define _CMU_CLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LDMA_DEFAULT (_CMU_CLKEN0_LDMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LDMAXBAR (0x1UL << 1) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LDMAXBAR_SHIFT 1 /**< Shift value for CMU_LDMAXBAR */ -#define _CMU_CLKEN0_LDMAXBAR_MASK 0x2UL /**< Bit mask for CMU_LDMAXBAR */ -#define _CMU_CLKEN0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LDMAXBAR_DEFAULT (_CMU_CLKEN0_LDMAXBAR_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_RADIOAES (0x1UL << 2) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_RADIOAES_SHIFT 2 /**< Shift value for CMU_RADIOAES */ -#define _CMU_CLKEN0_RADIOAES_MASK 0x4UL /**< Bit mask for CMU_RADIOAES */ -#define _CMU_CLKEN0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_RADIOAES_DEFAULT (_CMU_CLKEN0_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_GPCRC (0x1UL << 3) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_GPCRC_SHIFT 3 /**< Shift value for CMU_GPCRC */ -#define _CMU_CLKEN0_GPCRC_MASK 0x8UL /**< Bit mask for CMU_GPCRC */ -#define _CMU_CLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_GPCRC_DEFAULT (_CMU_CLKEN0_GPCRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER0 (0x1UL << 4) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER0_SHIFT 4 /**< Shift value for CMU_TIMER0 */ -#define _CMU_CLKEN0_TIMER0_MASK 0x10UL /**< Bit mask for CMU_TIMER0 */ -#define _CMU_CLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER0_DEFAULT (_CMU_CLKEN0_TIMER0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER1 (0x1UL << 5) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER1_SHIFT 5 /**< Shift value for CMU_TIMER1 */ -#define _CMU_CLKEN0_TIMER1_MASK 0x20UL /**< Bit mask for CMU_TIMER1 */ -#define _CMU_CLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER1_DEFAULT (_CMU_CLKEN0_TIMER1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER2 (0x1UL << 6) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER2_SHIFT 6 /**< Shift value for CMU_TIMER2 */ -#define _CMU_CLKEN0_TIMER2_MASK 0x40UL /**< Bit mask for CMU_TIMER2 */ -#define _CMU_CLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER2_DEFAULT (_CMU_CLKEN0_TIMER2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER3 (0x1UL << 7) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER3_SHIFT 7 /**< Shift value for CMU_TIMER3 */ -#define _CMU_CLKEN0_TIMER3_MASK 0x80UL /**< Bit mask for CMU_TIMER3 */ -#define _CMU_CLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER3_DEFAULT (_CMU_CLKEN0_TIMER3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER4 (0x1UL << 8) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER4_SHIFT 8 /**< Shift value for CMU_TIMER4 */ -#define _CMU_CLKEN0_TIMER4_MASK 0x100UL /**< Bit mask for CMU_TIMER4 */ -#define _CMU_CLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER4_DEFAULT (_CMU_CLKEN0_TIMER4_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_USART0 (0x1UL << 9) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_USART0_SHIFT 9 /**< Shift value for CMU_USART0 */ -#define _CMU_CLKEN0_USART0_MASK 0x200UL /**< Bit mask for CMU_USART0 */ -#define _CMU_CLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_USART0_DEFAULT (_CMU_CLKEN0_USART0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_IADC0 (0x1UL << 10) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_IADC0_SHIFT 10 /**< Shift value for CMU_IADC0 */ -#define _CMU_CLKEN0_IADC0_MASK 0x400UL /**< Bit mask for CMU_IADC0 */ -#define _CMU_CLKEN0_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_IADC0_DEFAULT (_CMU_CLKEN0_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_AMUXCP0 (0x1UL << 11) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_AMUXCP0_SHIFT 11 /**< Shift value for CMU_AMUXCP0 */ -#define _CMU_CLKEN0_AMUXCP0_MASK 0x800UL /**< Bit mask for CMU_AMUXCP0 */ -#define _CMU_CLKEN0_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_AMUXCP0_DEFAULT (_CMU_CLKEN0_AMUXCP0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LETIMER0 (0x1UL << 12) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LETIMER0_SHIFT 12 /**< Shift value for CMU_LETIMER0 */ -#define _CMU_CLKEN0_LETIMER0_MASK 0x1000UL /**< Bit mask for CMU_LETIMER0 */ -#define _CMU_CLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LETIMER0_DEFAULT (_CMU_CLKEN0_LETIMER0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_WDOG0 (0x1UL << 13) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_WDOG0_SHIFT 13 /**< Shift value for CMU_WDOG0 */ -#define _CMU_CLKEN0_WDOG0_MASK 0x2000UL /**< Bit mask for CMU_WDOG0 */ -#define _CMU_CLKEN0_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_WDOG0_DEFAULT (_CMU_CLKEN0_WDOG0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_I2C0 (0x1UL << 14) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_I2C0_SHIFT 14 /**< Shift value for CMU_I2C0 */ -#define _CMU_CLKEN0_I2C0_MASK 0x4000UL /**< Bit mask for CMU_I2C0 */ -#define _CMU_CLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_I2C0_DEFAULT (_CMU_CLKEN0_I2C0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_I2C1 (0x1UL << 15) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_I2C1_SHIFT 15 /**< Shift value for CMU_I2C1 */ -#define _CMU_CLKEN0_I2C1_MASK 0x8000UL /**< Bit mask for CMU_I2C1 */ -#define _CMU_CLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_I2C1_DEFAULT (_CMU_CLKEN0_I2C1_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_SYSCFG (0x1UL << 16) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_SYSCFG_SHIFT 16 /**< Shift value for CMU_SYSCFG */ -#define _CMU_CLKEN0_SYSCFG_MASK 0x10000UL /**< Bit mask for CMU_SYSCFG */ -#define _CMU_CLKEN0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_SYSCFG_DEFAULT (_CMU_CLKEN0_SYSCFG_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_DPLL0 (0x1UL << 17) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_DPLL0_SHIFT 17 /**< Shift value for CMU_DPLL0 */ -#define _CMU_CLKEN0_DPLL0_MASK 0x20000UL /**< Bit mask for CMU_DPLL0 */ -#define _CMU_CLKEN0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_DPLL0_DEFAULT (_CMU_CLKEN0_DPLL0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFRCO0 (0x1UL << 18) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_HFRCO0_SHIFT 18 /**< Shift value for CMU_HFRCO0 */ -#define _CMU_CLKEN0_HFRCO0_MASK 0x40000UL /**< Bit mask for CMU_HFRCO0 */ -#define _CMU_CLKEN0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFRCO0_DEFAULT (_CMU_CLKEN0_HFRCO0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFRCOEM23 (0x1UL << 19) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_HFRCOEM23_SHIFT 19 /**< Shift value for CMU_HFRCOEM23 */ -#define _CMU_CLKEN0_HFRCOEM23_MASK 0x80000UL /**< Bit mask for CMU_HFRCOEM23 */ -#define _CMU_CLKEN0_HFRCOEM23_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFRCOEM23_DEFAULT (_CMU_CLKEN0_HFRCOEM23_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFXO0 (0x1UL << 20) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_HFXO0_SHIFT 20 /**< Shift value for CMU_HFXO0 */ -#define _CMU_CLKEN0_HFXO0_MASK 0x100000UL /**< Bit mask for CMU_HFXO0 */ -#define _CMU_CLKEN0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFXO0_DEFAULT (_CMU_CLKEN0_HFXO0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_FSRCO (0x1UL << 21) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_FSRCO_SHIFT 21 /**< Shift value for CMU_FSRCO */ -#define _CMU_CLKEN0_FSRCO_MASK 0x200000UL /**< Bit mask for CMU_FSRCO */ -#define _CMU_CLKEN0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_FSRCO_DEFAULT (_CMU_CLKEN0_FSRCO_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LFRCO (0x1UL << 22) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LFRCO_SHIFT 22 /**< Shift value for CMU_LFRCO */ -#define _CMU_CLKEN0_LFRCO_MASK 0x400000UL /**< Bit mask for CMU_LFRCO */ -#define _CMU_CLKEN0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LFRCO_DEFAULT (_CMU_CLKEN0_LFRCO_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LFXO (0x1UL << 23) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LFXO_SHIFT 23 /**< Shift value for CMU_LFXO */ -#define _CMU_CLKEN0_LFXO_MASK 0x800000UL /**< Bit mask for CMU_LFXO */ -#define _CMU_CLKEN0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LFXO_DEFAULT (_CMU_CLKEN0_LFXO_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_ULFRCO (0x1UL << 24) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_ULFRCO_SHIFT 24 /**< Shift value for CMU_ULFRCO */ -#define _CMU_CLKEN0_ULFRCO_MASK 0x1000000UL /**< Bit mask for CMU_ULFRCO */ -#define _CMU_CLKEN0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_ULFRCO_DEFAULT (_CMU_CLKEN0_ULFRCO_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LESENSE (0x1UL << 25) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LESENSE_SHIFT 25 /**< Shift value for CMU_LESENSE */ -#define _CMU_CLKEN0_LESENSE_MASK 0x2000000UL /**< Bit mask for CMU_LESENSE */ -#define _CMU_CLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LESENSE_DEFAULT (_CMU_CLKEN0_LESENSE_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_GPIO (0x1UL << 26) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_GPIO_SHIFT 26 /**< Shift value for CMU_GPIO */ -#define _CMU_CLKEN0_GPIO_MASK 0x4000000UL /**< Bit mask for CMU_GPIO */ -#define _CMU_CLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_GPIO_DEFAULT (_CMU_CLKEN0_GPIO_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_PRS (0x1UL << 27) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_PRS_SHIFT 27 /**< Shift value for CMU_PRS */ -#define _CMU_CLKEN0_PRS_MASK 0x8000000UL /**< Bit mask for CMU_PRS */ -#define _CMU_CLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_PRS_DEFAULT (_CMU_CLKEN0_PRS_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_BURAM (0x1UL << 28) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_BURAM_SHIFT 28 /**< Shift value for CMU_BURAM */ -#define _CMU_CLKEN0_BURAM_MASK 0x10000000UL /**< Bit mask for CMU_BURAM */ -#define _CMU_CLKEN0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_BURAM_DEFAULT (_CMU_CLKEN0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_BURTC (0x1UL << 29) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_BURTC_SHIFT 29 /**< Shift value for CMU_BURTC */ -#define _CMU_CLKEN0_BURTC_MASK 0x20000000UL /**< Bit mask for CMU_BURTC */ -#define _CMU_CLKEN0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_BURTC_DEFAULT (_CMU_CLKEN0_BURTC_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_SYSRTC0 (0x1UL << 30) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_SYSRTC0_SHIFT 30 /**< Shift value for CMU_SYSRTC0 */ -#define _CMU_CLKEN0_SYSRTC0_MASK 0x40000000UL /**< Bit mask for CMU_SYSRTC0 */ -#define _CMU_CLKEN0_SYSRTC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_SYSRTC0_DEFAULT (_CMU_CLKEN0_SYSRTC0_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_DCDC (0x1UL << 31) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_DCDC_SHIFT 31 /**< Shift value for CMU_DCDC */ -#define _CMU_CLKEN0_DCDC_MASK 0x80000000UL /**< Bit mask for CMU_DCDC */ -#define _CMU_CLKEN0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_DCDC_DEFAULT (_CMU_CLKEN0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define _CMU_CLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN0 */ +#define _CMU_CLKEN0_MASK 0xFFFFFFFFUL /**< Mask for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMA_SHIFT 0 /**< Shift value for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_MASK 0x1UL /**< Bit mask for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA_DEFAULT (_CMU_CLKEN0_LDMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMAXBAR_SHIFT 1 /**< Shift value for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_MASK 0x2UL /**< Bit mask for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR_DEFAULT (_CMU_CLKEN0_LDMAXBAR_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_RADIOAES_SHIFT 2 /**< Shift value for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_MASK 0x4UL /**< Bit mask for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES_DEFAULT (_CMU_CLKEN0_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPCRC_SHIFT 3 /**< Shift value for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_MASK 0x8UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC_DEFAULT (_CMU_CLKEN0_GPCRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0 (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER0_SHIFT 4 /**< Shift value for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_MASK 0x10UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0_DEFAULT (_CMU_CLKEN0_TIMER0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1 (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER1_SHIFT 5 /**< Shift value for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_MASK 0x20UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1_DEFAULT (_CMU_CLKEN0_TIMER1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2 (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER2_SHIFT 6 /**< Shift value for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_MASK 0x40UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2_DEFAULT (_CMU_CLKEN0_TIMER2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3 (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER3_SHIFT 7 /**< Shift value for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_MASK 0x80UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3_DEFAULT (_CMU_CLKEN0_TIMER3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER4 (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER4_SHIFT 8 /**< Shift value for CMU_TIMER4 */ +#define _CMU_CLKEN0_TIMER4_MASK 0x100UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_CLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER4_DEFAULT (_CMU_CLKEN0_TIMER4_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0 (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_USART0_SHIFT 9 /**< Shift value for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_MASK 0x200UL /**< Bit mask for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0_DEFAULT (_CMU_CLKEN0_USART0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0 (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_IADC0_SHIFT 10 /**< Shift value for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_MASK 0x400UL /**< Bit mask for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0_DEFAULT (_CMU_CLKEN0_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0 (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_AMUXCP0_SHIFT 11 /**< Shift value for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_MASK 0x800UL /**< Bit mask for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0_DEFAULT (_CMU_CLKEN0_AMUXCP0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0 (0x1UL << 12) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LETIMER0_SHIFT 12 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_MASK 0x1000UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0_DEFAULT (_CMU_CLKEN0_LETIMER0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0 (0x1UL << 13) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_WDOG0_SHIFT 13 /**< Shift value for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_MASK 0x2000UL /**< Bit mask for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0_DEFAULT (_CMU_CLKEN0_WDOG0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0 (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C0_SHIFT 14 /**< Shift value for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_MASK 0x4000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0_DEFAULT (_CMU_CLKEN0_I2C0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1 (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C1_SHIFT 15 /**< Shift value for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_MASK 0x8000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1_DEFAULT (_CMU_CLKEN0_I2C1_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_SYSCFG_SHIFT 16 /**< Shift value for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_MASK 0x10000UL /**< Bit mask for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG_DEFAULT (_CMU_CLKEN0_SYSCFG_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0 (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DPLL0_SHIFT 17 /**< Shift value for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_MASK 0x20000UL /**< Bit mask for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0_DEFAULT (_CMU_CLKEN0_DPLL0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFRCO0_SHIFT 18 /**< Shift value for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_MASK 0x40000UL /**< Bit mask for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0_DEFAULT (_CMU_CLKEN0_HFRCO0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCOEM23 (0x1UL << 19) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFRCOEM23_SHIFT 19 /**< Shift value for CMU_HFRCOEM23 */ +#define _CMU_CLKEN0_HFRCOEM23_MASK 0x80000UL /**< Bit mask for CMU_HFRCOEM23 */ +#define _CMU_CLKEN0_HFRCOEM23_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCOEM23_DEFAULT (_CMU_CLKEN0_HFRCOEM23_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0 (0x1UL << 20) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFXO0_SHIFT 20 /**< Shift value for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_MASK 0x100000UL /**< Bit mask for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0_DEFAULT (_CMU_CLKEN0_HFXO0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO (0x1UL << 21) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_FSRCO_SHIFT 21 /**< Shift value for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_MASK 0x200000UL /**< Bit mask for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO_DEFAULT (_CMU_CLKEN0_FSRCO_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO (0x1UL << 22) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFRCO_SHIFT 22 /**< Shift value for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_MASK 0x400000UL /**< Bit mask for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO_DEFAULT (_CMU_CLKEN0_LFRCO_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO (0x1UL << 23) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFXO_SHIFT 23 /**< Shift value for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_MASK 0x800000UL /**< Bit mask for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO_DEFAULT (_CMU_CLKEN0_LFXO_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO (0x1UL << 24) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_ULFRCO_SHIFT 24 /**< Shift value for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_MASK 0x1000000UL /**< Bit mask for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO_DEFAULT (_CMU_CLKEN0_ULFRCO_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LESENSE (0x1UL << 25) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LESENSE_SHIFT 25 /**< Shift value for CMU_LESENSE */ +#define _CMU_CLKEN0_LESENSE_MASK 0x2000000UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_CLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LESENSE_DEFAULT (_CMU_CLKEN0_LESENSE_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO (0x1UL << 26) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPIO_SHIFT 26 /**< Shift value for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_MASK 0x4000000UL /**< Bit mask for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO_DEFAULT (_CMU_CLKEN0_GPIO_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS (0x1UL << 27) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_PRS_SHIFT 27 /**< Shift value for CMU_PRS */ +#define _CMU_CLKEN0_PRS_MASK 0x8000000UL /**< Bit mask for CMU_PRS */ +#define _CMU_CLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS_DEFAULT (_CMU_CLKEN0_PRS_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM (0x1UL << 28) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURAM_SHIFT 28 /**< Shift value for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_MASK 0x10000000UL /**< Bit mask for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM_DEFAULT (_CMU_CLKEN0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC (0x1UL << 29) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURTC_SHIFT 29 /**< Shift value for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_MASK 0x20000000UL /**< Bit mask for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC_DEFAULT (_CMU_CLKEN0_BURTC_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSRTC0 (0x1UL << 30) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_SYSRTC0_SHIFT 30 /**< Shift value for CMU_SYSRTC0 */ +#define _CMU_CLKEN0_SYSRTC0_MASK 0x40000000UL /**< Bit mask for CMU_SYSRTC0 */ +#define _CMU_CLKEN0_SYSRTC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSRTC0_DEFAULT (_CMU_CLKEN0_SYSRTC0_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC (0x1UL << 31) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DCDC_SHIFT 31 /**< Shift value for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_MASK 0x80000000UL /**< Bit mask for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC_DEFAULT (_CMU_CLKEN0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ /* Bit fields for CMU CLKEN1 */ -#define _CMU_CLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN1 */ -#define _CMU_CLKEN1_MASK 0x1FFFFFFFUL /**< Mask for CMU_CLKEN1 */ -#define CMU_CLKEN1_AGC (0x1UL << 0) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_AGC_SHIFT 0 /**< Shift value for CMU_AGC */ -#define _CMU_CLKEN1_AGC_MASK 0x1UL /**< Bit mask for CMU_AGC */ -#define _CMU_CLKEN1_AGC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_AGC_DEFAULT (_CMU_CLKEN1_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MODEM (0x1UL << 1) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_MODEM_SHIFT 1 /**< Shift value for CMU_MODEM */ -#define _CMU_CLKEN1_MODEM_MASK 0x2UL /**< Bit mask for CMU_MODEM */ -#define _CMU_CLKEN1_MODEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MODEM_DEFAULT (_CMU_CLKEN1_MODEM_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFCRC (0x1UL << 2) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RFCRC_SHIFT 2 /**< Shift value for CMU_RFCRC */ -#define _CMU_CLKEN1_RFCRC_MASK 0x4UL /**< Bit mask for CMU_RFCRC */ -#define _CMU_CLKEN1_RFCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFCRC_DEFAULT (_CMU_CLKEN1_RFCRC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_FRC (0x1UL << 3) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_FRC_SHIFT 3 /**< Shift value for CMU_FRC */ -#define _CMU_CLKEN1_FRC_MASK 0x8UL /**< Bit mask for CMU_FRC */ -#define _CMU_CLKEN1_FRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_FRC_DEFAULT (_CMU_CLKEN1_FRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_PROTIMER (0x1UL << 4) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_PROTIMER_SHIFT 4 /**< Shift value for CMU_PROTIMER */ -#define _CMU_CLKEN1_PROTIMER_MASK 0x10UL /**< Bit mask for CMU_PROTIMER */ -#define _CMU_CLKEN1_PROTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_PROTIMER_DEFAULT (_CMU_CLKEN1_PROTIMER_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RAC (0x1UL << 5) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RAC_SHIFT 5 /**< Shift value for CMU_RAC */ -#define _CMU_CLKEN1_RAC_MASK 0x20UL /**< Bit mask for CMU_RAC */ -#define _CMU_CLKEN1_RAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RAC_DEFAULT (_CMU_CLKEN1_RAC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SYNTH (0x1UL << 6) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_SYNTH_SHIFT 6 /**< Shift value for CMU_SYNTH */ -#define _CMU_CLKEN1_SYNTH_MASK 0x40UL /**< Bit mask for CMU_SYNTH */ -#define _CMU_CLKEN1_SYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SYNTH_DEFAULT (_CMU_CLKEN1_SYNTH_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFSCRATCHPAD (0x1UL << 7) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RFSCRATCHPAD_SHIFT 7 /**< Shift value for CMU_RFSCRATCHPAD */ -#define _CMU_CLKEN1_RFSCRATCHPAD_MASK 0x80UL /**< Bit mask for CMU_RFSCRATCHPAD */ -#define _CMU_CLKEN1_RFSCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFSCRATCHPAD_DEFAULT (_CMU_CLKEN1_RFSCRATCHPAD_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_HOSTMAILBOX (0x1UL << 8) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_HOSTMAILBOX_SHIFT 8 /**< Shift value for CMU_HOSTMAILBOX */ -#define _CMU_CLKEN1_HOSTMAILBOX_MASK 0x100UL /**< Bit mask for CMU_HOSTMAILBOX */ -#define _CMU_CLKEN1_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_HOSTMAILBOX_DEFAULT (_CMU_CLKEN1_HOSTMAILBOX_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFMAILBOX (0x1UL << 9) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RFMAILBOX_SHIFT 9 /**< Shift value for CMU_RFMAILBOX */ -#define _CMU_CLKEN1_RFMAILBOX_MASK 0x200UL /**< Bit mask for CMU_RFMAILBOX */ -#define _CMU_CLKEN1_RFMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFMAILBOX_DEFAULT (_CMU_CLKEN1_RFMAILBOX_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SEMAILBOXHOST (0x1UL << 10) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_SEMAILBOXHOST_SHIFT 10 /**< Shift value for CMU_SEMAILBOXHOST */ -#define _CMU_CLKEN1_SEMAILBOXHOST_MASK 0x400UL /**< Bit mask for CMU_SEMAILBOXHOST */ -#define _CMU_CLKEN1_SEMAILBOXHOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SEMAILBOXHOST_DEFAULT (_CMU_CLKEN1_SEMAILBOXHOST_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_BUFC (0x1UL << 11) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_BUFC_SHIFT 11 /**< Shift value for CMU_BUFC */ -#define _CMU_CLKEN1_BUFC_MASK 0x800UL /**< Bit mask for CMU_BUFC */ -#define _CMU_CLKEN1_BUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_BUFC_DEFAULT (_CMU_CLKEN1_BUFC_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_LCD (0x1UL << 12) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ -#define _CMU_CLKEN1_LCD_MASK 0x1000UL /**< Bit mask for CMU_LCD */ -#define _CMU_CLKEN1_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_LCD_DEFAULT (_CMU_CLKEN1_LCD_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_KEYSCAN (0x1UL << 13) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_KEYSCAN_SHIFT 13 /**< Shift value for CMU_KEYSCAN */ -#define _CMU_CLKEN1_KEYSCAN_MASK 0x2000UL /**< Bit mask for CMU_KEYSCAN */ -#define _CMU_CLKEN1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_KEYSCAN_DEFAULT (_CMU_CLKEN1_KEYSCAN_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SMU (0x1UL << 14) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_SMU_SHIFT 14 /**< Shift value for CMU_SMU */ -#define _CMU_CLKEN1_SMU_MASK 0x4000UL /**< Bit mask for CMU_SMU */ -#define _CMU_CLKEN1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SMU_DEFAULT (_CMU_CLKEN1_SMU_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ICACHE0 (0x1UL << 15) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_ICACHE0_SHIFT 15 /**< Shift value for CMU_ICACHE0 */ -#define _CMU_CLKEN1_ICACHE0_MASK 0x8000UL /**< Bit mask for CMU_ICACHE0 */ -#define _CMU_CLKEN1_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ICACHE0_DEFAULT (_CMU_CLKEN1_ICACHE0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MSC (0x1UL << 16) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_MSC_SHIFT 16 /**< Shift value for CMU_MSC */ -#define _CMU_CLKEN1_MSC_MASK 0x10000UL /**< Bit mask for CMU_MSC */ -#define _CMU_CLKEN1_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MSC_DEFAULT (_CMU_CLKEN1_MSC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_WDOG1 (0x1UL << 17) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_WDOG1_SHIFT 17 /**< Shift value for CMU_WDOG1 */ -#define _CMU_CLKEN1_WDOG1_MASK 0x20000UL /**< Bit mask for CMU_WDOG1 */ -#define _CMU_CLKEN1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_WDOG1_DEFAULT (_CMU_CLKEN1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ACMP0 (0x1UL << 18) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_ACMP0_SHIFT 18 /**< Shift value for CMU_ACMP0 */ -#define _CMU_CLKEN1_ACMP0_MASK 0x40000UL /**< Bit mask for CMU_ACMP0 */ -#define _CMU_CLKEN1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ACMP0_DEFAULT (_CMU_CLKEN1_ACMP0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ACMP1 (0x1UL << 19) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_ACMP1_SHIFT 19 /**< Shift value for CMU_ACMP1 */ -#define _CMU_CLKEN1_ACMP1_MASK 0x80000UL /**< Bit mask for CMU_ACMP1 */ -#define _CMU_CLKEN1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ACMP1_DEFAULT (_CMU_CLKEN1_ACMP1_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_VDAC0 (0x1UL << 20) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_VDAC0_SHIFT 20 /**< Shift value for CMU_VDAC0 */ -#define _CMU_CLKEN1_VDAC0_MASK 0x100000UL /**< Bit mask for CMU_VDAC0 */ -#define _CMU_CLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_VDAC0_DEFAULT (_CMU_CLKEN1_VDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_PCNT0 (0x1UL << 21) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_PCNT0_SHIFT 21 /**< Shift value for CMU_PCNT0 */ -#define _CMU_CLKEN1_PCNT0_MASK 0x200000UL /**< Bit mask for CMU_PCNT0 */ -#define _CMU_CLKEN1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_PCNT0_DEFAULT (_CMU_CLKEN1_PCNT0_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_EUSART0 (0x1UL << 22) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_EUSART0_SHIFT 22 /**< Shift value for CMU_EUSART0 */ -#define _CMU_CLKEN1_EUSART0_MASK 0x400000UL /**< Bit mask for CMU_EUSART0 */ -#define _CMU_CLKEN1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_EUSART0_DEFAULT (_CMU_CLKEN1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_EUSART1 (0x1UL << 23) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_EUSART1_SHIFT 23 /**< Shift value for CMU_EUSART1 */ -#define _CMU_CLKEN1_EUSART1_MASK 0x800000UL /**< Bit mask for CMU_EUSART1 */ -#define _CMU_CLKEN1_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_EUSART1_DEFAULT (_CMU_CLKEN1_EUSART1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_EUSART2 (0x1UL << 24) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_EUSART2_SHIFT 24 /**< Shift value for CMU_EUSART2 */ -#define _CMU_CLKEN1_EUSART2_MASK 0x1000000UL /**< Bit mask for CMU_EUSART2 */ -#define _CMU_CLKEN1_EUSART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_EUSART2_DEFAULT (_CMU_CLKEN1_EUSART2_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFECA0 (0x1UL << 25) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RFECA0_SHIFT 25 /**< Shift value for CMU_RFECA0 */ -#define _CMU_CLKEN1_RFECA0_MASK 0x2000000UL /**< Bit mask for CMU_RFECA0 */ -#define _CMU_CLKEN1_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFECA0_DEFAULT (_CMU_CLKEN1_RFECA0_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFECA1 (0x1UL << 26) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RFECA1_SHIFT 26 /**< Shift value for CMU_RFECA1 */ -#define _CMU_CLKEN1_RFECA1_MASK 0x4000000UL /**< Bit mask for CMU_RFECA1 */ -#define _CMU_CLKEN1_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFECA1_DEFAULT (_CMU_CLKEN1_RFECA1_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_DMEM (0x1UL << 27) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_DMEM_SHIFT 27 /**< Shift value for CMU_DMEM */ -#define _CMU_CLKEN1_DMEM_MASK 0x8000000UL /**< Bit mask for CMU_DMEM */ -#define _CMU_CLKEN1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_DMEM_DEFAULT (_CMU_CLKEN1_DMEM_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ECAIFADC (0x1UL << 28) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_ECAIFADC_SHIFT 28 /**< Shift value for CMU_ECAIFADC */ -#define _CMU_CLKEN1_ECAIFADC_MASK 0x10000000UL /**< Bit mask for CMU_ECAIFADC */ -#define _CMU_CLKEN1_ECAIFADC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ECAIFADC_DEFAULT (_CMU_CLKEN1_ECAIFADC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define _CMU_CLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN1 */ +#define _CMU_CLKEN1_MASK 0x1FFFFFFFUL /**< Mask for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_AGC_SHIFT 0 /**< Shift value for CMU_AGC */ +#define _CMU_CLKEN1_AGC_MASK 0x1UL /**< Bit mask for CMU_AGC */ +#define _CMU_CLKEN1_AGC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC_DEFAULT (_CMU_CLKEN1_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MODEM_SHIFT 1 /**< Shift value for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_MASK 0x2UL /**< Bit mask for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM_DEFAULT (_CMU_CLKEN1_MODEM_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFCRC_SHIFT 2 /**< Shift value for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_MASK 0x4UL /**< Bit mask for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC_DEFAULT (_CMU_CLKEN1_RFCRC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_FRC_SHIFT 3 /**< Shift value for CMU_FRC */ +#define _CMU_CLKEN1_FRC_MASK 0x8UL /**< Bit mask for CMU_FRC */ +#define _CMU_CLKEN1_FRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC_DEFAULT (_CMU_CLKEN1_FRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PROTIMER_SHIFT 4 /**< Shift value for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_MASK 0x10UL /**< Bit mask for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER_DEFAULT (_CMU_CLKEN1_PROTIMER_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RAC_SHIFT 5 /**< Shift value for CMU_RAC */ +#define _CMU_CLKEN1_RAC_MASK 0x20UL /**< Bit mask for CMU_RAC */ +#define _CMU_CLKEN1_RAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC_DEFAULT (_CMU_CLKEN1_RAC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SYNTH_SHIFT 6 /**< Shift value for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_MASK 0x40UL /**< Bit mask for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH_DEFAULT (_CMU_CLKEN1_SYNTH_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSCRATCHPAD (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFSCRATCHPAD_SHIFT 7 /**< Shift value for CMU_RFSCRATCHPAD */ +#define _CMU_CLKEN1_RFSCRATCHPAD_MASK 0x80UL /**< Bit mask for CMU_RFSCRATCHPAD */ +#define _CMU_CLKEN1_RFSCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSCRATCHPAD_DEFAULT (_CMU_CLKEN1_RFSCRATCHPAD_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_HOSTMAILBOX (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_HOSTMAILBOX_SHIFT 8 /**< Shift value for CMU_HOSTMAILBOX */ +#define _CMU_CLKEN1_HOSTMAILBOX_MASK 0x100UL /**< Bit mask for CMU_HOSTMAILBOX */ +#define _CMU_CLKEN1_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_HOSTMAILBOX_DEFAULT (_CMU_CLKEN1_HOSTMAILBOX_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFMAILBOX (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFMAILBOX_SHIFT 9 /**< Shift value for CMU_RFMAILBOX */ +#define _CMU_CLKEN1_RFMAILBOX_MASK 0x200UL /**< Bit mask for CMU_RFMAILBOX */ +#define _CMU_CLKEN1_RFMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFMAILBOX_DEFAULT (_CMU_CLKEN1_RFMAILBOX_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SEMAILBOXHOST (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SEMAILBOXHOST_SHIFT 10 /**< Shift value for CMU_SEMAILBOXHOST */ +#define _CMU_CLKEN1_SEMAILBOXHOST_MASK 0x400UL /**< Bit mask for CMU_SEMAILBOXHOST */ +#define _CMU_CLKEN1_SEMAILBOXHOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SEMAILBOXHOST_DEFAULT (_CMU_CLKEN1_SEMAILBOXHOST_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_BUFC_SHIFT 11 /**< Shift value for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_MASK 0x800UL /**< Bit mask for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC_DEFAULT (_CMU_CLKEN1_BUFC_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_LCD (0x1UL << 12) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_CLKEN1_LCD_MASK 0x1000UL /**< Bit mask for CMU_LCD */ +#define _CMU_CLKEN1_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_LCD_DEFAULT (_CMU_CLKEN1_LCD_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_KEYSCAN (0x1UL << 13) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_KEYSCAN_SHIFT 13 /**< Shift value for CMU_KEYSCAN */ +#define _CMU_CLKEN1_KEYSCAN_MASK 0x2000UL /**< Bit mask for CMU_KEYSCAN */ +#define _CMU_CLKEN1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_KEYSCAN_DEFAULT (_CMU_CLKEN1_KEYSCAN_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SMU_SHIFT 14 /**< Shift value for CMU_SMU */ +#define _CMU_CLKEN1_SMU_MASK 0x4000UL /**< Bit mask for CMU_SMU */ +#define _CMU_CLKEN1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU_DEFAULT (_CMU_CLKEN1_SMU_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0 (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ICACHE0_SHIFT 15 /**< Shift value for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_MASK 0x8000UL /**< Bit mask for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0_DEFAULT (_CMU_CLKEN1_ICACHE0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MSC_SHIFT 16 /**< Shift value for CMU_MSC */ +#define _CMU_CLKEN1_MSC_MASK 0x10000UL /**< Bit mask for CMU_MSC */ +#define _CMU_CLKEN1_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC_DEFAULT (_CMU_CLKEN1_MSC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_WDOG1 (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_WDOG1_SHIFT 17 /**< Shift value for CMU_WDOG1 */ +#define _CMU_CLKEN1_WDOG1_MASK 0x20000UL /**< Bit mask for CMU_WDOG1 */ +#define _CMU_CLKEN1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_WDOG1_DEFAULT (_CMU_CLKEN1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP0 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ACMP0_SHIFT 18 /**< Shift value for CMU_ACMP0 */ +#define _CMU_CLKEN1_ACMP0_MASK 0x40000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_CLKEN1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP0_DEFAULT (_CMU_CLKEN1_ACMP0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP1 (0x1UL << 19) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ACMP1_SHIFT 19 /**< Shift value for CMU_ACMP1 */ +#define _CMU_CLKEN1_ACMP1_MASK 0x80000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_CLKEN1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP1_DEFAULT (_CMU_CLKEN1_ACMP1_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC0 (0x1UL << 20) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_VDAC0_SHIFT 20 /**< Shift value for CMU_VDAC0 */ +#define _CMU_CLKEN1_VDAC0_MASK 0x100000UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_CLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC0_DEFAULT (_CMU_CLKEN1_VDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PCNT0 (0x1UL << 21) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PCNT0_SHIFT 21 /**< Shift value for CMU_PCNT0 */ +#define _CMU_CLKEN1_PCNT0_MASK 0x200000UL /**< Bit mask for CMU_PCNT0 */ +#define _CMU_CLKEN1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PCNT0_DEFAULT (_CMU_CLKEN1_PCNT0_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART0 (0x1UL << 22) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART0_SHIFT 22 /**< Shift value for CMU_EUSART0 */ +#define _CMU_CLKEN1_EUSART0_MASK 0x400000UL /**< Bit mask for CMU_EUSART0 */ +#define _CMU_CLKEN1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART0_DEFAULT (_CMU_CLKEN1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART1 (0x1UL << 23) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART1_SHIFT 23 /**< Shift value for CMU_EUSART1 */ +#define _CMU_CLKEN1_EUSART1_MASK 0x800000UL /**< Bit mask for CMU_EUSART1 */ +#define _CMU_CLKEN1_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART1_DEFAULT (_CMU_CLKEN1_EUSART1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART2 (0x1UL << 24) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART2_SHIFT 24 /**< Shift value for CMU_EUSART2 */ +#define _CMU_CLKEN1_EUSART2_MASK 0x1000000UL /**< Bit mask for CMU_EUSART2 */ +#define _CMU_CLKEN1_EUSART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART2_DEFAULT (_CMU_CLKEN1_EUSART2_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA0 (0x1UL << 25) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFECA0_SHIFT 25 /**< Shift value for CMU_RFECA0 */ +#define _CMU_CLKEN1_RFECA0_MASK 0x2000000UL /**< Bit mask for CMU_RFECA0 */ +#define _CMU_CLKEN1_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA0_DEFAULT (_CMU_CLKEN1_RFECA0_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA1 (0x1UL << 26) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFECA1_SHIFT 26 /**< Shift value for CMU_RFECA1 */ +#define _CMU_CLKEN1_RFECA1_MASK 0x4000000UL /**< Bit mask for CMU_RFECA1 */ +#define _CMU_CLKEN1_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA1_DEFAULT (_CMU_CLKEN1_RFECA1_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_DMEM (0x1UL << 27) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_DMEM_SHIFT 27 /**< Shift value for CMU_DMEM */ +#define _CMU_CLKEN1_DMEM_MASK 0x8000000UL /**< Bit mask for CMU_DMEM */ +#define _CMU_CLKEN1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_DMEM_DEFAULT (_CMU_CLKEN1_DMEM_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ECAIFADC (0x1UL << 28) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ECAIFADC_SHIFT 28 /**< Shift value for CMU_ECAIFADC */ +#define _CMU_CLKEN1_ECAIFADC_MASK 0x10000000UL /**< Bit mask for CMU_ECAIFADC */ +#define _CMU_CLKEN1_ECAIFADC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ECAIFADC_DEFAULT (_CMU_CLKEN1_ECAIFADC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ /* Bit fields for CMU SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_MASK 0x0001F507UL /**< Mask for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_SYSCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_SYSCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL 0x00000002UL /**< Mode HFRCODPLL for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_DEFAULT (_CMU_SYSCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_FSRCO (_CMU_SYSCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL (_CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_HFXO (_CMU_SYSCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_CLKIN0 (_CMU_SYSCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_PCLKPRESC (0x1UL << 10) /**< PCLK Prescaler */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT 10 /**< Shift value for CMU_PCLKPRESC */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_MASK 0x400UL /**< Bit mask for CMU_PCLKPRESC */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_PCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV1 << 10) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_PCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV2 << 10) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT 12 /**< Shift value for CMU_HCLKPRESC */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_MASK 0xF000UL /**< Bit mask for CMU_HCLKPRESC */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV8 0x00000007UL /**< Mode DIV8 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV16 0x0000000FUL /**< Mode DIV16 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV1 << 12) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV2 << 12) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV4 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV4 << 12) /**< Shifted mode DIV4 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV8 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV8 << 12) /**< Shifted mode DIV8 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV16 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV16 << 12) /**< Shifted mode DIV16 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_RHCLKPRESC (0x1UL << 16) /**< Radio HCLK Prescaler */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_SHIFT 16 /**< Shift value for CMU_RHCLKPRESC */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_MASK 0x10000UL /**< Bit mask for CMU_RHCLKPRESC */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_MASK 0x0001F507UL /**< Mask for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL 0x00000002UL /**< Mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_DEFAULT (_CMU_SYSCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_FSRCO (_CMU_SYSCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL (_CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFXO (_CMU_SYSCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_CLKIN0 (_CMU_SYSCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC (0x1UL << 10) /**< PCLK Prescaler */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT 10 /**< Shift value for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_MASK 0x400UL /**< Bit mask for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV1 << 10) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV2 << 10) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT 12 /**< Shift value for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_MASK 0xF000UL /**< Bit mask for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV8 0x00000007UL /**< Mode DIV8 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV16 0x0000000FUL /**< Mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV1 << 12) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV2 << 12) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV4 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV4 << 12) /**< Shifted mode DIV4 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV8 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV8 << 12) /**< Shifted mode DIV8 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV16 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV16 << 12) /**< Shifted mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC (0x1UL << 16) /**< Radio HCLK Prescaler */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_SHIFT 16 /**< Shift value for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_MASK 0x10000UL /**< Bit mask for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ /* Bit fields for CMU TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_MASK 0x00000030UL /**< Mask for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_PRESC_SHIFT 4 /**< Shift value for CMU_PRESC */ -#define _CMU_TRACECLKCTRL_PRESC_MASK 0x30UL /**< Bit mask for CMU_PRESC */ -#define _CMU_TRACECLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DEFAULT (_CMU_TRACECLKCTRL_PRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DIV1 (_CMU_TRACECLKCTRL_PRESC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DIV2 (_CMU_TRACECLKCTRL_PRESC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DIV4 (_CMU_TRACECLKCTRL_PRESC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_MASK 0x00000030UL /**< Mask for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_SHIFT 4 /**< Shift value for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_MASK 0x30UL /**< Bit mask for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DEFAULT (_CMU_TRACECLKCTRL_PRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV1 (_CMU_TRACECLKCTRL_PRESC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV2 (_CMU_TRACECLKCTRL_PRESC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV4 (_CMU_TRACECLKCTRL_PRESC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_TRACECLKCTRL */ /* Bit fields for CMU EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_MASK 0x1F0F0F0FUL /**< Mask for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK << 0) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT 8 /**< Shift value for CMU_CLKOUTSEL1 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK 0xF00UL /**< Bit mask for CMU_CLKOUTSEL1 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED << 8) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK << 8) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK << 8) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO << 8) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO << 8) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO << 8) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL << 8) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO << 8) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO << 8) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 << 8) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_SHIFT 16 /**< Shift value for CMU_CLKOUTSEL2 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK 0xF0000UL /**< Bit mask for CMU_CLKOUTSEL2 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED << 16) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK << 16) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK << 16) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO << 16) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO << 16) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL << 16) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO << 16) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO << 16) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 << 16) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ -#define _CMU_EXPORTCLKCTRL_PRESC_SHIFT 24 /**< Shift value for CMU_PRESC */ -#define _CMU_EXPORTCLKCTRL_PRESC_MASK 0x1F000000UL /**< Bit mask for CMU_PRESC */ -#define _CMU_EXPORTCLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_PRESC_DEFAULT (_CMU_EXPORTCLKCTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_MASK 0x1F0F0F0FUL /**< Mask for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK << 0) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT 8 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK 0xF00UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED << 8) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK << 8) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK << 8) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO << 8) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO << 8) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO << 8) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL << 8) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO << 8) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO << 8) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 << 8) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_SHIFT 16 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK 0xF0000UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED << 16) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK << 16) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK << 16) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO << 16) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO << 16) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL << 16) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO << 16) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO << 16) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 << 16) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_PRESC_SHIFT 24 /**< Shift value for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_MASK 0x1F000000UL /**< Bit mask for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_PRESC_DEFAULT (_CMU_EXPORTCLKCTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ /* Bit fields for CMU DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLREFCLKCTRL */ -#define CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT (_CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLREFCLKCTRL */ -#define CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED (_CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_DPLLREFCLKCTRL*/ -#define CMU_DPLLREFCLKCTRL_CLKSEL_HFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_DPLLREFCLKCTRL */ -#define CMU_DPLLREFCLKCTRL_CLKSEL_LFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_DPLLREFCLKCTRL */ -#define CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 (_CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT (_CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED (_CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_DPLLREFCLKCTRL*/ +#define CMU_DPLLREFCLKCTRL_CLKSEL_HFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_LFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 (_CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_DPLLREFCLKCTRL */ /* Bit fields for CMU EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPACLKCTRL */ -#define CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPACLKCTRL*/ -#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPACLKCTRL*/ -#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPACLKCTRL */ -#define CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPACLKCTRL */ -#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPACLKCTRL*/ -#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL*/ -#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPACLKCTRL */ /* Bit fields for CMU EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPCCLKCTRL */ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPCCLKCTRL*/ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPCCLKCTRL*/ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPCCLKCTRL */ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPCCLKCTRL */ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL*/ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL*/ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPCCLKCTRL */ /* Bit fields for CMU EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM23GRPACLKCTRL */ -#define CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM23GRPACLKCTRL*/ -#define CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM23GRPACLKCTRL */ -#define CMU_EM23GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM23GRPACLKCTRL */ -#define CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM23GRPACLKCTRL*/ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM23GRPACLKCTRL */ /* Bit fields for CMU EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM4GRPACLKCTRL */ /* Bit fields for CMU IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_IADCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_IADCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_CLKSEL_FSRCO 0x00000002UL /**< Mode FSRCO for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 0x00000003UL /**< Mode HFRCOEM23 for CMU_IADCCLKCTRL */ -#define CMU_IADCCLKCTRL_CLKSEL_DEFAULT (_CMU_IADCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IADCCLKCTRL */ -#define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_IADCCLKCTRL*/ -#define CMU_IADCCLKCTRL_CLKSEL_FSRCO (_CMU_IADCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_IADCCLKCTRL */ -#define CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_FSRCO 0x00000002UL /**< Mode FSRCO for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 0x00000003UL /**< Mode HFRCOEM23 for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_DEFAULT (_CMU_IADCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_IADCCLKCTRL*/ +#define CMU_IADCCLKCTRL_CLKSEL_FSRCO (_CMU_IADCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_IADCCLKCTRL */ /* Bit fields for CMU WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_LFXO (_CMU_WDOG0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG0CLKCTRL*/ +#define _CMU_WDOG0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFXO (_CMU_WDOG0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG0CLKCTRL*/ /* Bit fields for CMU WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG1CLKCTRL */ -#define CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG1CLKCTRL */ -#define CMU_WDOG1CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG1CLKCTRL */ -#define CMU_WDOG1CLKCTRL_CLKSEL_LFXO (_CMU_WDOG1CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG1CLKCTRL */ -#define CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG1CLKCTRL */ -#define CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG1CLKCTRL*/ +#define _CMU_WDOG1CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_LFXO (_CMU_WDOG1CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG1CLKCTRL*/ /* Bit fields for CMU EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK 0x00000001UL /**< Mode EM01GRPCCLK for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_EUSART0CLKCTRL */ -#define CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT (_CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EUSART0CLKCTRL */ -#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/ -#define CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK (_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK << 0) /**< Shifted mode EM01GRPCCLK for CMU_EUSART0CLKCTRL*/ -#define CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EUSART0CLKCTRL*/ -#define CMU_EUSART0CLKCTRL_CLKSEL_LFRCO (_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EUSART0CLKCTRL */ -#define CMU_EUSART0CLKCTRL_CLKSEL_LFXO (_CMU_EUSART0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK 0x00000001UL /**< Mode EM01GRPCCLK for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT (_CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK (_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK << 0) /**< Shifted mode EM01GRPCCLK for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_LFRCO (_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_LFXO (_CMU_EUSART0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EUSART0CLKCTRL */ /* Bit fields for CMU SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_SYSRTC0CLKCTRL */ -#define CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT (_CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSRTC0CLKCTRL */ -#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_SYSRTC0CLKCTRL */ -#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_SYSRTC0CLKCTRL */ -#define CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT (_CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_SYSRTC0CLKCTRL */ /* Bit fields for CMU LCDCLKCTRL */ -#define _CMU_LCDCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_LCDCLKCTRL */ -#define _CMU_LCDCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_LCDCLKCTRL */ -#define _CMU_LCDCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_LCDCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_LCDCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LCDCLKCTRL */ -#define _CMU_LCDCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LCDCLKCTRL */ -#define _CMU_LCDCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_LCDCLKCTRL */ -#define _CMU_LCDCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_LCDCLKCTRL */ -#define CMU_LCDCLKCTRL_CLKSEL_DEFAULT (_CMU_LCDCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCLKCTRL */ -#define CMU_LCDCLKCTRL_CLKSEL_LFRCO (_CMU_LCDCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LCDCLKCTRL */ -#define CMU_LCDCLKCTRL_CLKSEL_LFXO (_CMU_LCDCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_LCDCLKCTRL */ -#define CMU_LCDCLKCTRL_CLKSEL_ULFRCO (_CMU_LCDCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_LCDCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_LCDCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_LCDCLKCTRL */ +#define CMU_LCDCLKCTRL_CLKSEL_DEFAULT (_CMU_LCDCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCLKCTRL */ +#define CMU_LCDCLKCTRL_CLKSEL_LFRCO (_CMU_LCDCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LCDCLKCTRL */ +#define CMU_LCDCLKCTRL_CLKSEL_LFXO (_CMU_LCDCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_LCDCLKCTRL */ +#define CMU_LCDCLKCTRL_CLKSEL_ULFRCO (_CMU_LCDCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LCDCLKCTRL */ /* Bit fields for CMU VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ -#define CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT (_CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_VDAC0CLKCTRL */ -#define CMU_VDAC0CLKCTRL_CLKSEL_DISABLED (_CMU_VDAC0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_VDAC0CLKCTRL */ -#define CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_VDAC0CLKCTRL*/ -#define CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_VDAC0CLKCTRL*/ -#define CMU_VDAC0CLKCTRL_CLKSEL_FSRCO (_CMU_VDAC0CLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_VDAC0CLKCTRL */ -#define CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT (_CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_DISABLED (_CMU_VDAC0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_VDAC0CLKCTRL*/ +#define CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_VDAC0CLKCTRL*/ +#define CMU_VDAC0CLKCTRL_CLKSEL_FSRCO (_CMU_VDAC0CLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ /* Bit fields for CMU PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000001UL /**< Mode EM23GRPACLK for CMU_PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 0x00000002UL /**< Mode PCNTS0 for CMU_PCNT0CLKCTRL */ -#define CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT (_CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNT0CLKCTRL */ -#define CMU_PCNT0CLKCTRL_CLKSEL_DISABLED (_CMU_PCNT0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_PCNT0CLKCTRL */ -#define CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_PCNT0CLKCTRL*/ -#define CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 (_CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 << 0) /**< Shifted mode PCNTS0 for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000001UL /**< Mode EM23GRPACLK for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 0x00000002UL /**< Mode PCNTS0 for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT (_CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_DISABLED (_CMU_PCNT0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_PCNT0CLKCTRL*/ +#define CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 (_CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 << 0) /**< Shifted mode PCNTS0 for CMU_PCNT0CLKCTRL */ /* Bit fields for CMU RADIOCLKCTRL */ -#define _CMU_RADIOCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_RADIOCLKCTRL */ -#define _CMU_RADIOCLKCTRL_MASK 0x80000003UL /**< Mask for CMU_RADIOCLKCTRL */ -#define CMU_RADIOCLKCTRL_EN (0x1UL << 0) /**< Enable */ -#define _CMU_RADIOCLKCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */ -#define _CMU_RADIOCLKCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */ -#define _CMU_RADIOCLKCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ -#define CMU_RADIOCLKCTRL_EN_DEFAULT (_CMU_RADIOCLKCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ -#define CMU_RADIOCLKCTRL_DBGCLK (0x1UL << 31) /**< Enable Clock for Debugger */ -#define _CMU_RADIOCLKCTRL_DBGCLK_SHIFT 31 /**< Shift value for CMU_DBGCLK */ -#define _CMU_RADIOCLKCTRL_DBGCLK_MASK 0x80000000UL /**< Bit mask for CMU_DBGCLK */ -#define _CMU_RADIOCLKCTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ -#define CMU_RADIOCLKCTRL_DBGCLK_DEFAULT (_CMU_RADIOCLKCTRL_DBGCLK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_MASK 0x80000003UL /**< Mask for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN (0x1UL << 0) /**< Enable */ +#define _CMU_RADIOCLKCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN_DEFAULT (_CMU_RADIOCLKCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK (0x1UL << 31) /**< Enable Clock for Debugger */ +#define _CMU_RADIOCLKCTRL_DBGCLK_SHIFT 31 /**< Shift value for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_MASK 0x80000000UL /**< Bit mask for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK_DEFAULT (_CMU_RADIOCLKCTRL_DBGCLK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ /* Bit fields for CMU LESENSEHFCLKCTRL */ -#define _CMU_LESENSEHFCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_LESENSEHFCLKCTRL */ -#define _CMU_LESENSEHFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_LESENSEHFCLKCTRL */ -#define _CMU_LESENSEHFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_LESENSEHFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_LESENSEHFCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LESENSEHFCLKCTRL */ -#define _CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_LESENSEHFCLKCTRL */ -#define _CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_LESENSEHFCLKCTRL */ -#define CMU_LESENSEHFCLKCTRL_CLKSEL_DEFAULT (_CMU_LESENSEHFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LESENSEHFCLKCTRL*/ -#define CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO (_CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_LESENSEHFCLKCTRL */ -#define CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_LESENSEHFCLKCTRL*/ +#define _CMU_LESENSEHFCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_LESENSEHFCLKCTRL */ +#define _CMU_LESENSEHFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_LESENSEHFCLKCTRL */ +#define _CMU_LESENSEHFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_LESENSEHFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_LESENSEHFCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LESENSEHFCLKCTRL */ +#define _CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_LESENSEHFCLKCTRL */ +#define _CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_LESENSEHFCLKCTRL */ +#define CMU_LESENSEHFCLKCTRL_CLKSEL_DEFAULT (_CMU_LESENSEHFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LESENSEHFCLKCTRL*/ +#define CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO (_CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_LESENSEHFCLKCTRL */ +#define CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_LESENSEHFCLKCTRL*/ /** @} End of group EFR32SG23_CMU_BitFields */ /** @} End of group EFR32SG23_CMU */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dcdc.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dcdc.h index 1095e51009..51098e1376 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_devinfo.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_devinfo.h index 03667d8516..ce2257734f 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dma_descriptor.h index de6d3bc1d2..5a7f78425e 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dma_descriptor.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dpll.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dpll.h index 446eefa7f7..db5fe81fa0 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dpll.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_dpll.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_DPLL_H #define EFR32SG23_DPLL_H - #define DPLL_HAS_SET_CLEAR /**************************************************************************//** @@ -43,47 +42,46 @@ *****************************************************************************/ /** DPLL Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP Version */ - __IOM uint32_t EN; /**< Enable */ - __IOM uint32_t CFG; /**< Config */ - __IOM uint32_t CFG1; /**< Config1 */ - __IOM uint32_t IF; /**< Interrupt Flag */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - __IM uint32_t STATUS; /**< Status */ - uint32_t RESERVED0[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Lock */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - __IOM uint32_t EN_SET; /**< Enable */ - __IOM uint32_t CFG_SET; /**< Config */ - __IOM uint32_t CFG1_SET; /**< Config1 */ - __IOM uint32_t IF_SET; /**< Interrupt Flag */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - __IM uint32_t STATUS_SET; /**< Status */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Lock */ - uint32_t RESERVED3[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - __IOM uint32_t EN_CLR; /**< Enable */ - __IOM uint32_t CFG_CLR; /**< Config */ - __IOM uint32_t CFG1_CLR; /**< Config1 */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - __IM uint32_t STATUS_CLR; /**< Status */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Lock */ - uint32_t RESERVED5[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ - __IOM uint32_t EN_TGL; /**< Enable */ - __IOM uint32_t CFG_TGL; /**< Config */ - __IOM uint32_t CFG1_TGL; /**< Config1 */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - __IM uint32_t STATUS_TGL; /**< Status */ - uint32_t RESERVED6[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Lock */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CFG; /**< Config */ + __IOM uint32_t CFG1; /**< Config1 */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IM uint32_t STATUS; /**< Status */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CFG_SET; /**< Config */ + __IOM uint32_t CFG1_SET; /**< Config1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IM uint32_t STATUS_SET; /**< Status */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CFG_CLR; /**< Config */ + __IOM uint32_t CFG1_CLR; /**< Config1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IM uint32_t STATUS_CLR; /**< Status */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CFG_TGL; /**< Config */ + __IOM uint32_t CFG1_TGL; /**< Config1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IM uint32_t STATUS_TGL; /**< Status */ + uint32_t RESERVED6[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock */ } DPLL_TypeDef; /** @} End of group EFR32SG23_DPLL */ @@ -95,137 +93,137 @@ typedef struct *****************************************************************************/ /* Bit fields for DPLL IPVERSION */ -#define _DPLL_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for DPLL_IPVERSION */ -#define _DPLL_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DPLL_IPVERSION */ -#define _DPLL_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DPLL_IPVERSION */ -#define _DPLL_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DPLL_IPVERSION */ -#define _DPLL_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for DPLL_IPVERSION */ -#define DPLL_IPVERSION_IPVERSION_DEFAULT (_DPLL_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for DPLL_IPVERSION */ +#define DPLL_IPVERSION_IPVERSION_DEFAULT (_DPLL_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IPVERSION */ /* Bit fields for DPLL EN */ -#define _DPLL_EN_RESETVALUE 0x00000000UL /**< Default value for DPLL_EN */ -#define _DPLL_EN_MASK 0x00000003UL /**< Mask for DPLL_EN */ -#define DPLL_EN_EN (0x1UL << 0) /**< Module Enable */ -#define _DPLL_EN_EN_SHIFT 0 /**< Shift value for DPLL_EN */ -#define _DPLL_EN_EN_MASK 0x1UL /**< Bit mask for DPLL_EN */ -#define _DPLL_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ -#define DPLL_EN_EN_DEFAULT (_DPLL_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_EN */ -#define DPLL_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ -#define _DPLL_EN_DISABLING_SHIFT 1 /**< Shift value for DPLL_DISABLING */ -#define _DPLL_EN_DISABLING_MASK 0x2UL /**< Bit mask for DPLL_DISABLING */ -#define _DPLL_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ -#define DPLL_EN_DISABLING_DEFAULT (_DPLL_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_EN */ +#define _DPLL_EN_RESETVALUE 0x00000000UL /**< Default value for DPLL_EN */ +#define _DPLL_EN_MASK 0x00000003UL /**< Mask for DPLL_EN */ +#define DPLL_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _DPLL_EN_EN_SHIFT 0 /**< Shift value for DPLL_EN */ +#define _DPLL_EN_EN_MASK 0x1UL /**< Bit mask for DPLL_EN */ +#define _DPLL_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ +#define DPLL_EN_EN_DEFAULT (_DPLL_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_EN */ +#define DPLL_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ +#define _DPLL_EN_DISABLING_SHIFT 1 /**< Shift value for DPLL_DISABLING */ +#define _DPLL_EN_DISABLING_MASK 0x2UL /**< Bit mask for DPLL_DISABLING */ +#define _DPLL_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ +#define DPLL_EN_DISABLING_DEFAULT (_DPLL_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_EN */ /* Bit fields for DPLL CFG */ -#define _DPLL_CFG_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG */ -#define _DPLL_CFG_MASK 0x00000047UL /**< Mask for DPLL_CFG */ -#define DPLL_CFG_MODE (0x1UL << 0) /**< Operating Mode Control */ -#define _DPLL_CFG_MODE_SHIFT 0 /**< Shift value for DPLL_MODE */ -#define _DPLL_CFG_MODE_MASK 0x1UL /**< Bit mask for DPLL_MODE */ -#define _DPLL_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ -#define _DPLL_CFG_MODE_FLL 0x00000000UL /**< Mode FLL for DPLL_CFG */ -#define _DPLL_CFG_MODE_PLL 0x00000001UL /**< Mode PLL for DPLL_CFG */ -#define DPLL_CFG_MODE_DEFAULT (_DPLL_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_MODE_FLL (_DPLL_CFG_MODE_FLL << 0) /**< Shifted mode FLL for DPLL_CFG */ -#define DPLL_CFG_MODE_PLL (_DPLL_CFG_MODE_PLL << 0) /**< Shifted mode PLL for DPLL_CFG */ -#define DPLL_CFG_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ -#define _DPLL_CFG_EDGESEL_SHIFT 1 /**< Shift value for DPLL_EDGESEL */ -#define _DPLL_CFG_EDGESEL_MASK 0x2UL /**< Bit mask for DPLL_EDGESEL */ -#define _DPLL_CFG_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_EDGESEL_DEFAULT (_DPLL_CFG_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Control */ -#define _DPLL_CFG_AUTORECOVER_SHIFT 2 /**< Shift value for DPLL_AUTORECOVER */ -#define _DPLL_CFG_AUTORECOVER_MASK 0x4UL /**< Bit mask for DPLL_AUTORECOVER */ -#define _DPLL_CFG_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_AUTORECOVER_DEFAULT (_DPLL_CFG_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_DITHEN (0x1UL << 6) /**< Dither Enable Control */ -#define _DPLL_CFG_DITHEN_SHIFT 6 /**< Shift value for DPLL_DITHEN */ -#define _DPLL_CFG_DITHEN_MASK 0x40UL /**< Bit mask for DPLL_DITHEN */ -#define _DPLL_CFG_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_DITHEN_DEFAULT (_DPLL_CFG_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define _DPLL_CFG_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG */ +#define _DPLL_CFG_MASK 0x00000047UL /**< Mask for DPLL_CFG */ +#define DPLL_CFG_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _DPLL_CFG_MODE_SHIFT 0 /**< Shift value for DPLL_MODE */ +#define _DPLL_CFG_MODE_MASK 0x1UL /**< Bit mask for DPLL_MODE */ +#define _DPLL_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define _DPLL_CFG_MODE_FLL 0x00000000UL /**< Mode FLL for DPLL_CFG */ +#define _DPLL_CFG_MODE_PLL 0x00000001UL /**< Mode PLL for DPLL_CFG */ +#define DPLL_CFG_MODE_DEFAULT (_DPLL_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_MODE_FLL (_DPLL_CFG_MODE_FLL << 0) /**< Shifted mode FLL for DPLL_CFG */ +#define DPLL_CFG_MODE_PLL (_DPLL_CFG_MODE_PLL << 0) /**< Shifted mode PLL for DPLL_CFG */ +#define DPLL_CFG_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _DPLL_CFG_EDGESEL_SHIFT 1 /**< Shift value for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_MASK 0x2UL /**< Bit mask for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_EDGESEL_DEFAULT (_DPLL_CFG_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Control */ +#define _DPLL_CFG_AUTORECOVER_SHIFT 2 /**< Shift value for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_MASK 0x4UL /**< Bit mask for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER_DEFAULT (_DPLL_CFG_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _DPLL_CFG_DITHEN_SHIFT 6 /**< Shift value for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_MASK 0x40UL /**< Bit mask for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN_DEFAULT (_DPLL_CFG_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for DPLL_CFG */ /* Bit fields for DPLL CFG1 */ -#define _DPLL_CFG1_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG1 */ -#define _DPLL_CFG1_MASK 0x0FFF0FFFUL /**< Mask for DPLL_CFG1 */ -#define _DPLL_CFG1_M_SHIFT 0 /**< Shift value for DPLL_M */ -#define _DPLL_CFG1_M_MASK 0xFFFUL /**< Bit mask for DPLL_M */ -#define _DPLL_CFG1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ -#define DPLL_CFG1_M_DEFAULT (_DPLL_CFG1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG1 */ -#define _DPLL_CFG1_N_SHIFT 16 /**< Shift value for DPLL_N */ -#define _DPLL_CFG1_N_MASK 0xFFF0000UL /**< Bit mask for DPLL_N */ -#define _DPLL_CFG1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ -#define DPLL_CFG1_N_DEFAULT (_DPLL_CFG1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for DPLL_CFG1 */ +#define _DPLL_CFG1_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG1 */ +#define _DPLL_CFG1_MASK 0x0FFF0FFFUL /**< Mask for DPLL_CFG1 */ +#define _DPLL_CFG1_M_SHIFT 0 /**< Shift value for DPLL_M */ +#define _DPLL_CFG1_M_MASK 0xFFFUL /**< Bit mask for DPLL_M */ +#define _DPLL_CFG1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_M_DEFAULT (_DPLL_CFG1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG1 */ +#define _DPLL_CFG1_N_SHIFT 16 /**< Shift value for DPLL_N */ +#define _DPLL_CFG1_N_MASK 0xFFF0000UL /**< Bit mask for DPLL_N */ +#define _DPLL_CFG1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_N_DEFAULT (_DPLL_CFG1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for DPLL_CFG1 */ /* Bit fields for DPLL IF */ -#define _DPLL_IF_RESETVALUE 0x00000000UL /**< Default value for DPLL_IF */ -#define _DPLL_IF_MASK 0x00000007UL /**< Mask for DPLL_IF */ -#define DPLL_IF_LOCK (0x1UL << 0) /**< Lock Interrupt Flag */ -#define _DPLL_IF_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ -#define _DPLL_IF_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ -#define _DPLL_IF_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCK_DEFAULT (_DPLL_IF_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCKFAILLOW (0x1UL << 1) /**< Lock Failure Low Interrupt Flag */ -#define _DPLL_IF_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ -#define _DPLL_IF_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ -#define _DPLL_IF_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCKFAILLOW_DEFAULT (_DPLL_IF_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCKFAILHIGH (0x1UL << 2) /**< Lock Failure High Interrupt Flag */ -#define _DPLL_IF_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ -#define _DPLL_IF_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ -#define _DPLL_IF_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCKFAILHIGH_DEFAULT (_DPLL_IF_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IF */ +#define _DPLL_IF_RESETVALUE 0x00000000UL /**< Default value for DPLL_IF */ +#define _DPLL_IF_MASK 0x00000007UL /**< Mask for DPLL_IF */ +#define DPLL_IF_LOCK (0x1UL << 0) /**< Lock Interrupt Flag */ +#define _DPLL_IF_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IF_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IF_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCK_DEFAULT (_DPLL_IF_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW (0x1UL << 1) /**< Lock Failure Low Interrupt Flag */ +#define _DPLL_IF_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW_DEFAULT (_DPLL_IF_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH (0x1UL << 2) /**< Lock Failure High Interrupt Flag */ +#define _DPLL_IF_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH_DEFAULT (_DPLL_IF_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IF */ /* Bit fields for DPLL IEN */ -#define _DPLL_IEN_RESETVALUE 0x00000000UL /**< Default value for DPLL_IEN */ -#define _DPLL_IEN_MASK 0x00000007UL /**< Mask for DPLL_IEN */ -#define DPLL_IEN_LOCK (0x1UL << 0) /**< LOCK interrupt Enable */ -#define _DPLL_IEN_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ -#define _DPLL_IEN_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ -#define _DPLL_IEN_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCK_DEFAULT (_DPLL_IEN_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCKFAILLOW (0x1UL << 1) /**< LOCKFAILLOW Interrupe Enable */ -#define _DPLL_IEN_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ -#define _DPLL_IEN_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ -#define _DPLL_IEN_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCKFAILLOW_DEFAULT (_DPLL_IEN_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCKFAILHIGH (0x1UL << 2) /**< LOCKFAILHIGH Interrupt Enable */ -#define _DPLL_IEN_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ -#define _DPLL_IEN_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ -#define _DPLL_IEN_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCKFAILHIGH_DEFAULT (_DPLL_IEN_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define _DPLL_IEN_RESETVALUE 0x00000000UL /**< Default value for DPLL_IEN */ +#define _DPLL_IEN_MASK 0x00000007UL /**< Mask for DPLL_IEN */ +#define DPLL_IEN_LOCK (0x1UL << 0) /**< LOCK interrupt Enable */ +#define _DPLL_IEN_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCK_DEFAULT (_DPLL_IEN_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW (0x1UL << 1) /**< LOCKFAILLOW Interrupe Enable */ +#define _DPLL_IEN_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW_DEFAULT (_DPLL_IEN_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH (0x1UL << 2) /**< LOCKFAILHIGH Interrupt Enable */ +#define _DPLL_IEN_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH_DEFAULT (_DPLL_IEN_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IEN */ /* Bit fields for DPLL STATUS */ -#define _DPLL_STATUS_RESETVALUE 0x00000000UL /**< Default value for DPLL_STATUS */ -#define _DPLL_STATUS_MASK 0x80000003UL /**< Mask for DPLL_STATUS */ -#define DPLL_STATUS_RDY (0x1UL << 0) /**< Ready Status */ -#define _DPLL_STATUS_RDY_SHIFT 0 /**< Shift value for DPLL_RDY */ -#define _DPLL_STATUS_RDY_MASK 0x1UL /**< Bit mask for DPLL_RDY */ -#define _DPLL_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_RDY_DEFAULT (_DPLL_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_ENS (0x1UL << 1) /**< Enable Status */ -#define _DPLL_STATUS_ENS_SHIFT 1 /**< Shift value for DPLL_ENS */ -#define _DPLL_STATUS_ENS_MASK 0x2UL /**< Bit mask for DPLL_ENS */ -#define _DPLL_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_ENS_DEFAULT (_DPLL_STATUS_ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ -#define _DPLL_STATUS_LOCK_SHIFT 31 /**< Shift value for DPLL_LOCK */ -#define _DPLL_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for DPLL_LOCK */ -#define _DPLL_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ -#define _DPLL_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DPLL_STATUS */ -#define _DPLL_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DPLL_STATUS */ -#define DPLL_STATUS_LOCK_DEFAULT (_DPLL_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_LOCK_UNLOCKED (_DPLL_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for DPLL_STATUS */ -#define DPLL_STATUS_LOCK_LOCKED (_DPLL_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for DPLL_STATUS */ +#define _DPLL_STATUS_RESETVALUE 0x00000000UL /**< Default value for DPLL_STATUS */ +#define _DPLL_STATUS_MASK 0x80000003UL /**< Mask for DPLL_STATUS */ +#define DPLL_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _DPLL_STATUS_RDY_SHIFT 0 /**< Shift value for DPLL_RDY */ +#define _DPLL_STATUS_RDY_MASK 0x1UL /**< Bit mask for DPLL_RDY */ +#define _DPLL_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_RDY_DEFAULT (_DPLL_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS (0x1UL << 1) /**< Enable Status */ +#define _DPLL_STATUS_ENS_SHIFT 1 /**< Shift value for DPLL_ENS */ +#define _DPLL_STATUS_ENS_MASK 0x2UL /**< Bit mask for DPLL_ENS */ +#define _DPLL_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS_DEFAULT (_DPLL_STATUS_ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _DPLL_STATUS_LOCK_SHIFT 31 /**< Shift value for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_DEFAULT (_DPLL_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_UNLOCKED (_DPLL_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_LOCKED (_DPLL_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for DPLL_STATUS */ /* Bit fields for DPLL LOCK */ -#define _DPLL_LOCK_RESETVALUE 0x00007102UL /**< Default value for DPLL_LOCK */ -#define _DPLL_LOCK_MASK 0x0000FFFFUL /**< Mask for DPLL_LOCK */ -#define _DPLL_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DPLL_LOCKKEY */ -#define _DPLL_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DPLL_LOCKKEY */ -#define _DPLL_LOCK_LOCKKEY_DEFAULT 0x00007102UL /**< Mode DEFAULT for DPLL_LOCK */ -#define _DPLL_LOCK_LOCKKEY_UNLOCK 0x00007102UL /**< Mode UNLOCK for DPLL_LOCK */ -#define DPLL_LOCK_LOCKKEY_DEFAULT (_DPLL_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_LOCK */ -#define DPLL_LOCK_LOCKKEY_UNLOCK (_DPLL_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for DPLL_LOCK */ +#define _DPLL_LOCK_RESETVALUE 0x00007102UL /**< Default value for DPLL_LOCK */ +#define _DPLL_LOCK_MASK 0x0000FFFFUL /**< Mask for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_DEFAULT 0x00007102UL /**< Mode DEFAULT for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_UNLOCK 0x00007102UL /**< Mode UNLOCK for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_DEFAULT (_DPLL_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_UNLOCK (_DPLL_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for DPLL_LOCK */ /** @} End of group EFR32SG23_DPLL_BitFields */ /** @} End of group EFR32SG23_DPLL */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_emu.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_emu.h index 2d6ba7ff3b..394a84a7e4 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_emu.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_emu.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_EMU_H #define EFR32SG23_EMU_H - #define EMU_HAS_SET_CLEAR /**************************************************************************//** @@ -43,151 +42,150 @@ *****************************************************************************/ /** EMU Register Declaration. */ -typedef struct -{ - uint32_t RESERVED0[4U]; /**< Reserved for future use */ - __IOM uint32_t DECBOD; /**< DECOUPLE LVBOD Control register */ - uint32_t RESERVED1[3U]; /**< Reserved for future use */ - __IOM uint32_t BOD3SENSE; /**< BOD3SENSE Control register */ - uint32_t RESERVED2[6U]; /**< Reserved for future use */ - __IOM uint32_t VREGVDDCMPCTRL; /**< DC-DC VREGVDD Comparator Control Register */ - __IOM uint32_t PD1PARETCTRL; /**< PD1 Partial Retention Control */ - uint32_t RESERVED3[6U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION; /**< IP Version */ - __IOM uint32_t LOCK; /**< EMU Configuration lock register */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enables */ - __IOM uint32_t EM4CTRL; /**< EM4 Control */ - __IOM uint32_t CMD; /**< EMU Command register */ - __IOM uint32_t CTRL; /**< EMU Control register */ - __IOM uint32_t TEMPLIMITS; /**< EMU Temperature thresholds */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< EMU Status register */ - __IM uint32_t TEMP; /**< Temperature */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IOM uint32_t RSTCTRL; /**< Reset Management Control register */ - __IM uint32_t RSTCAUSE; /**< Reset cause */ - __IM uint32_t TAMPERRSTCAUSE; /**< Tamper Reset cause */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IOM uint32_t DGIF; /**< Interrupt Flags Debug */ - __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */ - uint32_t RESERVED7[6U]; /**< Reserved for future use */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - uint32_t RESERVED9[15U]; /**< Reserved for future use */ - __IOM uint32_t EFPIF; /**< EFP Interrupt Register */ - __IOM uint32_t EFPIEN; /**< EFP Interrupt Enable Register */ - uint32_t RESERVED10[14U]; /**< Reserved for future use */ - uint32_t RESERVED11[1U]; /**< Reserved for future use */ - uint32_t RESERVED12[18U]; /**< Reserved for future use */ - uint32_t RESERVED13[1U]; /**< Reserved for future use */ - uint32_t RESERVED14[924U]; /**< Reserved for future use */ - uint32_t RESERVED15[4U]; /**< Reserved for future use */ - __IOM uint32_t DECBOD_SET; /**< DECOUPLE LVBOD Control register */ - uint32_t RESERVED16[3U]; /**< Reserved for future use */ - __IOM uint32_t BOD3SENSE_SET; /**< BOD3SENSE Control register */ - uint32_t RESERVED17[6U]; /**< Reserved for future use */ - __IOM uint32_t VREGVDDCMPCTRL_SET; /**< DC-DC VREGVDD Comparator Control Register */ - __IOM uint32_t PD1PARETCTRL_SET; /**< PD1 Partial Retention Control */ - uint32_t RESERVED18[6U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - __IOM uint32_t LOCK_SET; /**< EMU Configuration lock register */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enables */ - __IOM uint32_t EM4CTRL_SET; /**< EM4 Control */ - __IOM uint32_t CMD_SET; /**< EMU Command register */ - __IOM uint32_t CTRL_SET; /**< EMU Control register */ - __IOM uint32_t TEMPLIMITS_SET; /**< EMU Temperature thresholds */ - uint32_t RESERVED19[2U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< EMU Status register */ - __IM uint32_t TEMP_SET; /**< Temperature */ - uint32_t RESERVED20[1U]; /**< Reserved for future use */ - __IOM uint32_t RSTCTRL_SET; /**< Reset Management Control register */ - __IM uint32_t RSTCAUSE_SET; /**< Reset cause */ - __IM uint32_t TAMPERRSTCAUSE_SET; /**< Tamper Reset cause */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */ - __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */ - uint32_t RESERVED22[6U]; /**< Reserved for future use */ - uint32_t RESERVED23[1U]; /**< Reserved for future use */ - uint32_t RESERVED24[15U]; /**< Reserved for future use */ - __IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */ - __IOM uint32_t EFPIEN_SET; /**< EFP Interrupt Enable Register */ - uint32_t RESERVED25[14U]; /**< Reserved for future use */ - uint32_t RESERVED26[1U]; /**< Reserved for future use */ - uint32_t RESERVED27[18U]; /**< Reserved for future use */ - uint32_t RESERVED28[1U]; /**< Reserved for future use */ - uint32_t RESERVED29[924U]; /**< Reserved for future use */ - uint32_t RESERVED30[4U]; /**< Reserved for future use */ - __IOM uint32_t DECBOD_CLR; /**< DECOUPLE LVBOD Control register */ - uint32_t RESERVED31[3U]; /**< Reserved for future use */ - __IOM uint32_t BOD3SENSE_CLR; /**< BOD3SENSE Control register */ - uint32_t RESERVED32[6U]; /**< Reserved for future use */ - __IOM uint32_t VREGVDDCMPCTRL_CLR; /**< DC-DC VREGVDD Comparator Control Register */ - __IOM uint32_t PD1PARETCTRL_CLR; /**< PD1 Partial Retention Control */ - uint32_t RESERVED33[6U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - __IOM uint32_t LOCK_CLR; /**< EMU Configuration lock register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ - __IOM uint32_t EM4CTRL_CLR; /**< EM4 Control */ - __IOM uint32_t CMD_CLR; /**< EMU Command register */ - __IOM uint32_t CTRL_CLR; /**< EMU Control register */ - __IOM uint32_t TEMPLIMITS_CLR; /**< EMU Temperature thresholds */ - uint32_t RESERVED34[2U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< EMU Status register */ - __IM uint32_t TEMP_CLR; /**< Temperature */ - uint32_t RESERVED35[1U]; /**< Reserved for future use */ - __IOM uint32_t RSTCTRL_CLR; /**< Reset Management Control register */ - __IM uint32_t RSTCAUSE_CLR; /**< Reset cause */ - __IM uint32_t TAMPERRSTCAUSE_CLR; /**< Tamper Reset cause */ - uint32_t RESERVED36[1U]; /**< Reserved for future use */ - __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */ - __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */ - uint32_t RESERVED37[6U]; /**< Reserved for future use */ - uint32_t RESERVED38[1U]; /**< Reserved for future use */ - uint32_t RESERVED39[15U]; /**< Reserved for future use */ - __IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */ - __IOM uint32_t EFPIEN_CLR; /**< EFP Interrupt Enable Register */ - uint32_t RESERVED40[14U]; /**< Reserved for future use */ - uint32_t RESERVED41[1U]; /**< Reserved for future use */ - uint32_t RESERVED42[18U]; /**< Reserved for future use */ - uint32_t RESERVED43[1U]; /**< Reserved for future use */ - uint32_t RESERVED44[924U]; /**< Reserved for future use */ - uint32_t RESERVED45[4U]; /**< Reserved for future use */ - __IOM uint32_t DECBOD_TGL; /**< DECOUPLE LVBOD Control register */ - uint32_t RESERVED46[3U]; /**< Reserved for future use */ - __IOM uint32_t BOD3SENSE_TGL; /**< BOD3SENSE Control register */ - uint32_t RESERVED47[6U]; /**< Reserved for future use */ - __IOM uint32_t VREGVDDCMPCTRL_TGL; /**< DC-DC VREGVDD Comparator Control Register */ - __IOM uint32_t PD1PARETCTRL_TGL; /**< PD1 Partial Retention Control */ - uint32_t RESERVED48[6U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ - __IOM uint32_t LOCK_TGL; /**< EMU Configuration lock register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ - __IOM uint32_t EM4CTRL_TGL; /**< EM4 Control */ - __IOM uint32_t CMD_TGL; /**< EMU Command register */ - __IOM uint32_t CTRL_TGL; /**< EMU Control register */ - __IOM uint32_t TEMPLIMITS_TGL; /**< EMU Temperature thresholds */ - uint32_t RESERVED49[2U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< EMU Status register */ - __IM uint32_t TEMP_TGL; /**< Temperature */ - uint32_t RESERVED50[1U]; /**< Reserved for future use */ - __IOM uint32_t RSTCTRL_TGL; /**< Reset Management Control register */ - __IM uint32_t RSTCAUSE_TGL; /**< Reset cause */ - __IM uint32_t TAMPERRSTCAUSE_TGL; /**< Tamper Reset cause */ - uint32_t RESERVED51[1U]; /**< Reserved for future use */ - __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */ - __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */ - uint32_t RESERVED52[6U]; /**< Reserved for future use */ - uint32_t RESERVED53[1U]; /**< Reserved for future use */ - uint32_t RESERVED54[15U]; /**< Reserved for future use */ - __IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */ - __IOM uint32_t EFPIEN_TGL; /**< EFP Interrupt Enable Register */ - uint32_t RESERVED55[14U]; /**< Reserved for future use */ - uint32_t RESERVED56[1U]; /**< Reserved for future use */ - uint32_t RESERVED57[18U]; /**< Reserved for future use */ - uint32_t RESERVED58[1U]; /**< Reserved for future use */ +typedef struct { + uint32_t RESERVED0[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE; /**< BOD3SENSE Control register */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED3[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t LOCK; /**< EMU Configuration lock register */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL; /**< EM4 Control */ + __IOM uint32_t CMD; /**< EMU Command register */ + __IOM uint32_t CTRL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS; /**< EMU Temperature thresholds */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< EMU Status register */ + __IM uint32_t TEMP; /**< Temperature */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE; /**< Tamper Reset cause */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */ + uint32_t RESERVED7[6U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED10[14U]; /**< Reserved for future use */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[18U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + uint32_t RESERVED14[924U]; /**< Reserved for future use */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_SET; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED16[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_SET; /**< BOD3SENSE Control register */ + uint32_t RESERVED17[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_SET; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_SET; /**< PD1 Partial Retention Control */ + uint32_t RESERVED18[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t LOCK_SET; /**< EMU Configuration lock register */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_SET; /**< EM4 Control */ + __IOM uint32_t CMD_SET; /**< EMU Command register */ + __IOM uint32_t CTRL_SET; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_SET; /**< EMU Temperature thresholds */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< EMU Status register */ + __IM uint32_t TEMP_SET; /**< Temperature */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_SET; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_SET; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_SET; /**< Tamper Reset cause */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */ + uint32_t RESERVED22[6U]; /**< Reserved for future use */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + uint32_t RESERVED24[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_SET; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED25[14U]; /**< Reserved for future use */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + uint32_t RESERVED27[18U]; /**< Reserved for future use */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + uint32_t RESERVED29[924U]; /**< Reserved for future use */ + uint32_t RESERVED30[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_CLR; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED31[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_CLR; /**< BOD3SENSE Control register */ + uint32_t RESERVED32[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_CLR; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_CLR; /**< PD1 Partial Retention Control */ + uint32_t RESERVED33[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t LOCK_CLR; /**< EMU Configuration lock register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_CLR; /**< EM4 Control */ + __IOM uint32_t CMD_CLR; /**< EMU Command register */ + __IOM uint32_t CTRL_CLR; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_CLR; /**< EMU Temperature thresholds */ + uint32_t RESERVED34[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< EMU Status register */ + __IM uint32_t TEMP_CLR; /**< Temperature */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_CLR; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_CLR; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_CLR; /**< Tamper Reset cause */ + uint32_t RESERVED36[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */ + uint32_t RESERVED37[6U]; /**< Reserved for future use */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + uint32_t RESERVED39[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_CLR; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED40[14U]; /**< Reserved for future use */ + uint32_t RESERVED41[1U]; /**< Reserved for future use */ + uint32_t RESERVED42[18U]; /**< Reserved for future use */ + uint32_t RESERVED43[1U]; /**< Reserved for future use */ + uint32_t RESERVED44[924U]; /**< Reserved for future use */ + uint32_t RESERVED45[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_TGL; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED46[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_TGL; /**< BOD3SENSE Control register */ + uint32_t RESERVED47[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_TGL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_TGL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED48[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t LOCK_TGL; /**< EMU Configuration lock register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_TGL; /**< EM4 Control */ + __IOM uint32_t CMD_TGL; /**< EMU Command register */ + __IOM uint32_t CTRL_TGL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_TGL; /**< EMU Temperature thresholds */ + uint32_t RESERVED49[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< EMU Status register */ + __IM uint32_t TEMP_TGL; /**< Temperature */ + uint32_t RESERVED50[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_TGL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_TGL; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_TGL; /**< Tamper Reset cause */ + uint32_t RESERVED51[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */ + uint32_t RESERVED52[6U]; /**< Reserved for future use */ + uint32_t RESERVED53[1U]; /**< Reserved for future use */ + uint32_t RESERVED54[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_TGL; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED55[14U]; /**< Reserved for future use */ + uint32_t RESERVED56[1U]; /**< Reserved for future use */ + uint32_t RESERVED57[18U]; /**< Reserved for future use */ + uint32_t RESERVED58[1U]; /**< Reserved for future use */ } EMU_TypeDef; /** @} End of group EFR32SG23_EMU */ @@ -199,580 +197,580 @@ typedef struct *****************************************************************************/ /* Bit fields for EMU DECBOD */ -#define _EMU_DECBOD_RESETVALUE 0x00000022UL /**< Default value for EMU_DECBOD */ -#define _EMU_DECBOD_MASK 0x00000033UL /**< Mask for EMU_DECBOD */ -#define EMU_DECBOD_DECBODEN (0x1UL << 0) /**< DECBOD enable */ -#define _EMU_DECBOD_DECBODEN_SHIFT 0 /**< Shift value for EMU_DECBODEN */ -#define _EMU_DECBOD_DECBODEN_MASK 0x1UL /**< Bit mask for EMU_DECBODEN */ -#define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECBODEN_DEFAULT (_EMU_DECBOD_DECBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECBODMASK (0x1UL << 1) /**< DECBOD Mask */ -#define _EMU_DECBOD_DECBODMASK_SHIFT 1 /**< Shift value for EMU_DECBODMASK */ -#define _EMU_DECBOD_DECBODMASK_MASK 0x2UL /**< Bit mask for EMU_DECBODMASK */ -#define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECBODMASK_DEFAULT (_EMU_DECBOD_DECBODMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECOVMBODEN (0x1UL << 4) /**< Over Voltage Monitor enable */ -#define _EMU_DECBOD_DECOVMBODEN_SHIFT 4 /**< Shift value for EMU_DECOVMBODEN */ -#define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL /**< Bit mask for EMU_DECOVMBODEN */ -#define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECOVMBODEN_DEFAULT (_EMU_DECBOD_DECOVMBODEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5) /**< Over Voltage Monitor Mask */ -#define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5 /**< Shift value for EMU_DECOVMBODMASK */ -#define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL /**< Bit mask for EMU_DECOVMBODMASK */ -#define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECOVMBODMASK_DEFAULT (_EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define _EMU_DECBOD_RESETVALUE 0x00000022UL /**< Default value for EMU_DECBOD */ +#define _EMU_DECBOD_MASK 0x00000033UL /**< Mask for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN (0x1UL << 0) /**< DECBOD enable */ +#define _EMU_DECBOD_DECBODEN_SHIFT 0 /**< Shift value for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_MASK 0x1UL /**< Bit mask for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN_DEFAULT (_EMU_DECBOD_DECBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK (0x1UL << 1) /**< DECBOD Mask */ +#define _EMU_DECBOD_DECBODMASK_SHIFT 1 /**< Shift value for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_MASK 0x2UL /**< Bit mask for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK_DEFAULT (_EMU_DECBOD_DECBODMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN (0x1UL << 4) /**< Over Voltage Monitor enable */ +#define _EMU_DECBOD_DECOVMBODEN_SHIFT 4 /**< Shift value for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL /**< Bit mask for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN_DEFAULT (_EMU_DECBOD_DECOVMBODEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5) /**< Over Voltage Monitor Mask */ +#define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5 /**< Shift value for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL /**< Bit mask for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK_DEFAULT (_EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DECBOD */ /* Bit fields for EMU BOD3SENSE */ -#define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL /**< Default value for EMU_BOD3SENSE */ -#define _EMU_BOD3SENSE_MASK 0x00000077UL /**< Mask for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0) /**< AVDD BOD enable */ -#define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0 /**< Shift value for EMU_AVDDBODEN */ -#define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL /**< Bit mask for EMU_AVDDBODEN */ -#define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_AVDDBODEN_DEFAULT (_EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_VDDIO0BODEN (0x1UL << 1) /**< VDDIO0 BOD enable */ -#define _EMU_BOD3SENSE_VDDIO0BODEN_SHIFT 1 /**< Shift value for EMU_VDDIO0BODEN */ -#define _EMU_BOD3SENSE_VDDIO0BODEN_MASK 0x2UL /**< Bit mask for EMU_VDDIO0BODEN */ -#define _EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_VDDIO1BODEN (0x1UL << 2) /**< VDDIO1 BOD enable */ -#define _EMU_BOD3SENSE_VDDIO1BODEN_SHIFT 2 /**< Shift value for EMU_VDDIO1BODEN */ -#define _EMU_BOD3SENSE_VDDIO1BODEN_MASK 0x4UL /**< Bit mask for EMU_VDDIO1BODEN */ -#define _EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL /**< Default value for EMU_BOD3SENSE */ +#define _EMU_BOD3SENSE_MASK 0x00000077UL /**< Mask for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0) /**< AVDD BOD enable */ +#define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0 /**< Shift value for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL /**< Bit mask for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN_DEFAULT (_EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN (0x1UL << 1) /**< VDDIO0 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_SHIFT 1 /**< Shift value for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_MASK 0x2UL /**< Bit mask for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN (0x1UL << 2) /**< VDDIO1 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_SHIFT 2 /**< Shift value for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_MASK 0x4UL /**< Bit mask for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ /* Bit fields for EMU VREGVDDCMPCTRL */ -#define _EMU_VREGVDDCMPCTRL_RESETVALUE 0x00000006UL /**< Default value for EMU_VREGVDDCMPCTRL */ -#define _EMU_VREGVDDCMPCTRL_MASK 0x00000007UL /**< Mask for EMU_VREGVDDCMPCTRL */ -#define EMU_VREGVDDCMPCTRL_VREGINCMPEN (0x1UL << 0) /**< VREGVDD comparator enable */ -#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_SHIFT 0 /**< Shift value for EMU_VREGINCMPEN */ -#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_MASK 0x1UL /**< Bit mask for EMU_VREGINCMPEN */ -#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ -#define EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT (_EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ -#define _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT 1 /**< Shift value for EMU_THRESSEL */ -#define _EMU_VREGVDDCMPCTRL_THRESSEL_MASK 0x6UL /**< Bit mask for EMU_THRESSEL */ -#define _EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ -#define EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT (_EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_RESETVALUE 0x00000006UL /**< Default value for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_MASK 0x00000007UL /**< Mask for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN (0x1UL << 0) /**< VREGVDD comparator enable */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_SHIFT 0 /**< Shift value for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_MASK 0x1UL /**< Bit mask for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT (_EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT 1 /**< Shift value for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_MASK 0x6UL /**< Bit mask for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT (_EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ /* Bit fields for EMU PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_SHIFT 0 /**< Shift value for EMU_PD1PARETDIS */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_MASK 0xFFFFUL /**< Bit mask for EMU_PD1PARETDIS */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN 0x00000001UL /**< Mode PERIPHNORETAIN for EMU_PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN 0x00000002UL /**< Mode RADIONORETAIN for EMU_PD1PARETCTRL */ -#define EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT (_EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PD1PARETCTRL */ -#define EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN << 0) /**< Shifted mode PERIPHNORETAIN for EMU_PD1PARETCTRL*/ -#define EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN << 0) /**< Shifted mode RADIONORETAIN for EMU_PD1PARETCTRL*/ +#define _EMU_PD1PARETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_SHIFT 0 /**< Shift value for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_MASK 0xFFFFUL /**< Bit mask for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN 0x00000001UL /**< Mode PERIPHNORETAIN for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN 0x00000002UL /**< Mode RADIONORETAIN for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT (_EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN << 0) /**< Shifted mode PERIPHNORETAIN for EMU_PD1PARETCTRL*/ +#define EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN << 0) /**< Shifted mode RADIONORETAIN for EMU_PD1PARETCTRL*/ /* Bit fields for EMU IPVERSION */ -#define _EMU_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for EMU_IPVERSION */ -#define _EMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EMU_IPVERSION */ -#define _EMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EMU_IPVERSION */ -#define _EMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_IPVERSION */ -#define _EMU_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_IPVERSION */ -#define EMU_IPVERSION_IPVERSION_DEFAULT (_EMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IPVERSION */ +#define _EMU_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for EMU_IPVERSION */ +#define _EMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_IPVERSION */ +#define EMU_IPVERSION_IPVERSION_DEFAULT (_EMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IPVERSION */ /* Bit fields for EMU LOCK */ -#define _EMU_LOCK_RESETVALUE 0x0000ADE8UL /**< Default value for EMU_LOCK */ -#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ -#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ -#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ -#define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL /**< Mode DEFAULT for EMU_LOCK */ -#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ -#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ -#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ +#define _EMU_LOCK_RESETVALUE 0x0000ADE8UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ /* Bit fields for EMU IF */ -#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ -#define _EMU_IF_MASK 0xEB070000UL /**< Mask for EMU_IF */ -#define EMU_IF_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt flag */ -#define _EMU_IF_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ -#define _EMU_IF_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ -#define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_AVDDBOD_DEFAULT (_EMU_IF_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt flag */ -#define _EMU_IF_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ -#define _EMU_IF_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ -#define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_IOVDD0BOD_DEFAULT (_EMU_IF_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ -#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ -#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ -#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt flag */ -#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ -#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ -#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPAVG (0x1UL << 27) /**< Temperature Average Interrupt flag */ -#define _EMU_IF_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ -#define _EMU_IF_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ -#define _EMU_IF_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPAVG_DEFAULT (_EMU_IF_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ -#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ -#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ -#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */ -#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ -#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ -#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */ -#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ -#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ -#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xEB070000UL /**< Mask for EMU_IF */ +#define EMU_IF_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt flag */ +#define _EMU_IF_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_AVDDBOD_DEFAULT (_EMU_IF_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt flag */ +#define _EMU_IF_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD_DEFAULT (_EMU_IF_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt flag */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG (0x1UL << 27) /**< Temperature Average Interrupt flag */ +#define _EMU_IF_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG_DEFAULT (_EMU_IF_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ /* Bit fields for EMU IEN */ -#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ -#define _EMU_IEN_MASK 0xEB070000UL /**< Mask for EMU_IEN */ -#define EMU_IEN_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt enable */ -#define _EMU_IEN_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ -#define _EMU_IEN_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ -#define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_AVDDBOD_DEFAULT (_EMU_IEN_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt enable */ -#define _EMU_IEN_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ -#define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ -#define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_IOVDD0BOD_DEFAULT (_EMU_IEN_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ -#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ -#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ -#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt enable */ -#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ -#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ -#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPAVG (0x1UL << 27) /**< Temperature Interrupt enable */ -#define _EMU_IEN_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ -#define _EMU_IEN_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ -#define _EMU_IEN_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPAVG_DEFAULT (_EMU_IEN_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ -#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ -#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ -#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ -#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ -#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ -#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ -#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ -#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ -#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xEB070000UL /**< Mask for EMU_IEN */ +#define EMU_IEN_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt enable */ +#define _EMU_IEN_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_AVDDBOD_DEFAULT (_EMU_IEN_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt enable */ +#define _EMU_IEN_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD_DEFAULT (_EMU_IEN_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG (0x1UL << 27) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG_DEFAULT (_EMU_IEN_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ /* Bit fields for EMU EM4CTRL */ -#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_MASK 0x00000133UL /**< Mask for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0 /**< Shift value for EMU_EM4ENTRY */ -#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL /**< Bit mask for EMU_EM4ENTRY */ -#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ -#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ -#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ -#define EMU_EM4CTRL_BOD3SENSEEM4WU (0x1UL << 8) /**< Set BOD3SENSE as EM4 wakeup */ -#define _EMU_EM4CTRL_BOD3SENSEEM4WU_SHIFT 8 /**< Shift value for EMU_BOD3SENSEEM4WU */ -#define _EMU_EM4CTRL_BOD3SENSEEM4WU_MASK 0x100UL /**< Bit mask for EMU_BOD3SENSEEM4WU */ -#define _EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ -#define EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT (_EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x00000133UL /**< Mask for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU (0x1UL << 8) /**< Set BOD3SENSE as EM4 wakeup */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_SHIFT 8 /**< Shift value for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_MASK 0x100UL /**< Bit mask for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT (_EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ /* Bit fields for EMU CMD */ -#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ -#define _EMU_CMD_MASK 0x00060E12UL /**< Mask for EMU_CMD */ -#define EMU_CMD_EM4UNLATCH (0x1UL << 1) /**< EM4 unlatch */ -#define _EMU_CMD_EM4UNLATCH_SHIFT 1 /**< Shift value for EMU_EM4UNLATCH */ -#define _EMU_CMD_EM4UNLATCH_MASK 0x2UL /**< Bit mask for EMU_EM4UNLATCH */ -#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_TEMPAVGREQ (0x1UL << 4) /**< Temperature Average Request */ -#define _EMU_CMD_TEMPAVGREQ_SHIFT 4 /**< Shift value for EMU_TEMPAVGREQ */ -#define _EMU_CMD_TEMPAVGREQ_MASK 0x10UL /**< Bit mask for EMU_TEMPAVGREQ */ -#define _EMU_CMD_TEMPAVGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_TEMPAVGREQ_DEFAULT (_EMU_CMD_TEMPAVGREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM01VSCALE1 (0x1UL << 10) /**< Scale voltage to Vscale1 */ -#define _EMU_CMD_EM01VSCALE1_SHIFT 10 /**< Shift value for EMU_EM01VSCALE1 */ -#define _EMU_CMD_EM01VSCALE1_MASK 0x400UL /**< Bit mask for EMU_EM01VSCALE1 */ -#define _EMU_CMD_EM01VSCALE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM01VSCALE1_DEFAULT (_EMU_CMD_EM01VSCALE1_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM01VSCALE2 (0x1UL << 11) /**< Scale voltage to Vscale2 */ -#define _EMU_CMD_EM01VSCALE2_SHIFT 11 /**< Shift value for EMU_EM01VSCALE2 */ -#define _EMU_CMD_EM01VSCALE2_MASK 0x800UL /**< Bit mask for EMU_EM01VSCALE2 */ -#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_RSTCAUSECLR (0x1UL << 17) /**< Reset Cause Clear */ -#define _EMU_CMD_RSTCAUSECLR_SHIFT 17 /**< Shift value for EMU_RSTCAUSECLR */ -#define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL /**< Bit mask for EMU_RSTCAUSECLR */ -#define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_RSTCAUSECLR_DEFAULT (_EMU_CMD_RSTCAUSECLR_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_TAMPERRCCLR (0x1UL << 18) /**< Tamper Reset Cause Clear */ -#define _EMU_CMD_TAMPERRCCLR_SHIFT 18 /**< Shift value for EMU_TAMPERRCCLR */ -#define _EMU_CMD_TAMPERRCCLR_MASK 0x40000UL /**< Bit mask for EMU_TAMPERRCCLR */ -#define _EMU_CMD_TAMPERRCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_TAMPERRCCLR_DEFAULT (_EMU_CMD_TAMPERRCCLR_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00060E12UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 1) /**< EM4 unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 1 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x2UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ (0x1UL << 4) /**< Temperature Average Request */ +#define _EMU_CMD_TEMPAVGREQ_SHIFT 4 /**< Shift value for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_MASK 0x10UL /**< Bit mask for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ_DEFAULT (_EMU_CMD_TEMPAVGREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1 (0x1UL << 10) /**< Scale voltage to Vscale1 */ +#define _EMU_CMD_EM01VSCALE1_SHIFT 10 /**< Shift value for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_MASK 0x400UL /**< Bit mask for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1_DEFAULT (_EMU_CMD_EM01VSCALE1_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 11) /**< Scale voltage to Vscale2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 11 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x800UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR (0x1UL << 17) /**< Reset Cause Clear */ +#define _EMU_CMD_RSTCAUSECLR_SHIFT 17 /**< Shift value for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL /**< Bit mask for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR_DEFAULT (_EMU_CMD_RSTCAUSECLR_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TAMPERRCCLR (0x1UL << 18) /**< Tamper Reset Cause Clear */ +#define _EMU_CMD_TAMPERRCCLR_SHIFT 18 /**< Shift value for EMU_TAMPERRCCLR */ +#define _EMU_CMD_TAMPERRCCLR_MASK 0x40000UL /**< Bit mask for EMU_TAMPERRCCLR */ +#define _EMU_CMD_TAMPERRCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TAMPERRCCLR_DEFAULT (_EMU_CMD_TAMPERRCCLR_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_CMD */ /* Bit fields for EMU CTRL */ -#define _EMU_CTRL_RESETVALUE 0x00000200UL /**< Default value for EMU_CTRL */ -#define _EMU_CTRL_MASK 0xE0010309UL /**< Mask for EMU_CTRL */ -#define EMU_CTRL_EM2DBGEN (0x1UL << 0) /**< Enable debugging in EM2 */ -#define _EMU_CTRL_EM2DBGEN_SHIFT 0 /**< Shift value for EMU_EM2DBGEN */ -#define _EMU_CTRL_EM2DBGEN_MASK 0x1UL /**< Bit mask for EMU_EM2DBGEN */ -#define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EM2DBGEN_DEFAULT (_EMU_CTRL_EM2DBGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_TEMPAVGNUM (0x1UL << 3) /**< Averaged Temperature samples num */ -#define _EMU_CTRL_TEMPAVGNUM_SHIFT 3 /**< Shift value for EMU_TEMPAVGNUM */ -#define _EMU_CTRL_TEMPAVGNUM_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGNUM */ -#define _EMU_CTRL_TEMPAVGNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define _EMU_CTRL_TEMPAVGNUM_N16 0x00000000UL /**< Mode N16 for EMU_CTRL */ -#define _EMU_CTRL_TEMPAVGNUM_N64 0x00000001UL /**< Mode N64 for EMU_CTRL */ -#define EMU_CTRL_TEMPAVGNUM_DEFAULT (_EMU_CTRL_TEMPAVGNUM_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_TEMPAVGNUM_N16 (_EMU_CTRL_TEMPAVGNUM_N16 << 3) /**< Shifted mode N16 for EMU_CTRL */ -#define EMU_CTRL_TEMPAVGNUM_N64 (_EMU_CTRL_TEMPAVGNUM_N64 << 3) /**< Shifted mode N64 for EMU_CTRL */ -#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ -#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ -#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_CTRL */ -#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_CTRL */ -#define _EMU_CTRL_EM23VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_CTRL */ -#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_CTRL */ -#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ -#define EMU_CTRL_EM23VSCALE_VSCALE1 (_EMU_CTRL_EM23VSCALE_VSCALE1 << 8) /**< Shifted mode VSCALE1 for EMU_CTRL */ -#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ -#define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16) /**< Enable flash on demand wakeup */ -#define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16 /**< Shift value for EMU_FLASHPWRUPONDEMAND */ -#define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL /**< Bit mask for EMU_FLASHPWRUPONDEMAND */ -#define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT (_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDIRECTMODEEN (0x1UL << 29) /**< EFP Direct Mode Enable */ -#define _EMU_CTRL_EFPDIRECTMODEEN_SHIFT 29 /**< Shift value for EMU_EFPDIRECTMODEEN */ -#define _EMU_CTRL_EFPDIRECTMODEEN_MASK 0x20000000UL /**< Bit mask for EMU_EFPDIRECTMODEEN */ -#define _EMU_CTRL_EFPDIRECTMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDIRECTMODEEN_DEFAULT (_EMU_CTRL_EFPDIRECTMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDRVDECOUPLE (0x1UL << 30) /**< EFP drives DECOUPLE */ -#define _EMU_CTRL_EFPDRVDECOUPLE_SHIFT 30 /**< Shift value for EMU_EFPDRVDECOUPLE */ -#define _EMU_CTRL_EFPDRVDECOUPLE_MASK 0x40000000UL /**< Bit mask for EMU_EFPDRVDECOUPLE */ -#define _EMU_CTRL_EFPDRVDECOUPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDRVDECOUPLE_DEFAULT (_EMU_CTRL_EFPDRVDECOUPLE_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDRVDVDD (0x1UL << 31) /**< EFP drives DVDD */ -#define _EMU_CTRL_EFPDRVDVDD_SHIFT 31 /**< Shift value for EMU_EFPDRVDVDD */ -#define _EMU_CTRL_EFPDRVDVDD_MASK 0x80000000UL /**< Bit mask for EMU_EFPDRVDVDD */ -#define _EMU_CTRL_EFPDRVDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDRVDVDD_DEFAULT (_EMU_CTRL_EFPDRVDVDD_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000200UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0xE0010309UL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN (0x1UL << 0) /**< Enable debugging in EM2 */ +#define _EMU_CTRL_EM2DBGEN_SHIFT 0 /**< Shift value for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_MASK 0x1UL /**< Bit mask for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN_DEFAULT (_EMU_CTRL_EM2DBGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM (0x1UL << 3) /**< Averaged Temperature samples num */ +#define _EMU_CTRL_TEMPAVGNUM_SHIFT 3 /**< Shift value for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N16 0x00000000UL /**< Mode N16 for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N64 0x00000001UL /**< Mode N64 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_DEFAULT (_EMU_CTRL_TEMPAVGNUM_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N16 (_EMU_CTRL_TEMPAVGNUM_N16 << 3) /**< Shifted mode N16 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N64 (_EMU_CTRL_TEMPAVGNUM_N64 << 3) /**< Shifted mode N64 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE1 (_EMU_CTRL_EM23VSCALE_VSCALE1 << 8) /**< Shifted mode VSCALE1 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16) /**< Enable flash on demand wakeup */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16 /**< Shift value for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL /**< Bit mask for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT (_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN (0x1UL << 29) /**< EFP Direct Mode Enable */ +#define _EMU_CTRL_EFPDIRECTMODEEN_SHIFT 29 /**< Shift value for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_MASK 0x20000000UL /**< Bit mask for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN_DEFAULT (_EMU_CTRL_EFPDIRECTMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE (0x1UL << 30) /**< EFP drives DECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_SHIFT 30 /**< Shift value for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_MASK 0x40000000UL /**< Bit mask for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE_DEFAULT (_EMU_CTRL_EFPDRVDECOUPLE_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD (0x1UL << 31) /**< EFP drives DVDD */ +#define _EMU_CTRL_EFPDRVDVDD_SHIFT 31 /**< Shift value for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_MASK 0x80000000UL /**< Bit mask for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD_DEFAULT (_EMU_CTRL_EFPDRVDVDD_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_CTRL */ /* Bit fields for EMU TEMPLIMITS */ -#define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL /**< Default value for EMU_TEMPLIMITS */ -#define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL /**< Mask for EMU_TEMPLIMITS */ -#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ -#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL /**< Bit mask for EMU_TEMPLOW */ -#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ -#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ -#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16 /**< Shift value for EMU_TEMPHIGH */ -#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL /**< Bit mask for EMU_TEMPHIGH */ -#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ -#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ /* Bit fields for EMU STATUS */ -#define _EMU_STATUS_RESETVALUE 0x00000080UL /**< Default value for EMU_STATUS */ -#define _EMU_STATUS_MASK 0xFFFFD4FFUL /**< Mask for EMU_STATUS */ -#define EMU_STATUS_LOCK (0x1UL << 0) /**< Lock status */ -#define _EMU_STATUS_LOCK_SHIFT 0 /**< Shift value for EMU_LOCK */ -#define _EMU_STATUS_LOCK_MASK 0x1UL /**< Bit mask for EMU_LOCK */ -#define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_STATUS */ -#define _EMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_STATUS */ -#define EMU_STATUS_LOCK_DEFAULT (_EMU_STATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_LOCK_UNLOCKED (_EMU_STATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_STATUS */ -#define EMU_STATUS_LOCK_LOCKED (_EMU_STATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for EMU_STATUS */ -#define EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1) /**< First Temp done */ -#define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1 /**< Shift value for EMU_FIRSTTEMPDONE */ -#define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL /**< Bit mask for EMU_FIRSTTEMPDONE */ -#define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_FIRSTTEMPDONE_DEFAULT (_EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_TEMPACTIVE (0x1UL << 2) /**< Temp active */ -#define _EMU_STATUS_TEMPACTIVE_SHIFT 2 /**< Shift value for EMU_TEMPACTIVE */ -#define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL /**< Bit mask for EMU_TEMPACTIVE */ -#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_TEMPAVGACTIVE (0x1UL << 3) /**< Temp Average active */ -#define _EMU_STATUS_TEMPAVGACTIVE_SHIFT 3 /**< Shift value for EMU_TEMPAVGACTIVE */ -#define _EMU_STATUS_TEMPAVGACTIVE_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGACTIVE */ -#define _EMU_STATUS_TEMPAVGACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_TEMPAVGACTIVE_DEFAULT (_EMU_STATUS_TEMPAVGACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALEBUSY (0x1UL << 4) /**< Vscale busy */ -#define _EMU_STATUS_VSCALEBUSY_SHIFT 4 /**< Shift value for EMU_VSCALEBUSY */ -#define _EMU_STATUS_VSCALEBUSY_MASK 0x10UL /**< Bit mask for EMU_VSCALEBUSY */ -#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALEFAILED (0x1UL << 5) /**< Vscale failed */ -#define _EMU_STATUS_VSCALEFAILED_SHIFT 5 /**< Shift value for EMU_VSCALEFAILED */ -#define _EMU_STATUS_VSCALEFAILED_MASK 0x20UL /**< Bit mask for EMU_VSCALEFAILED */ -#define _EMU_STATUS_VSCALEFAILED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALEFAILED_DEFAULT (_EMU_STATUS_VSCALEFAILED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define _EMU_STATUS_VSCALE_SHIFT 6 /**< Shift value for EMU_VSCALE */ -#define _EMU_STATUS_VSCALE_MASK 0xC0UL /**< Bit mask for EMU_VSCALE */ -#define _EMU_STATUS_VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_STATUS */ -#define _EMU_STATUS_VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_STATUS */ -#define _EMU_STATUS_VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_STATUS */ -#define _EMU_STATUS_VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_STATUS */ -#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 6) /**< Shifted mode VSCALE0 for EMU_STATUS */ -#define EMU_STATUS_VSCALE_VSCALE1 (_EMU_STATUS_VSCALE_VSCALE1 << 6) /**< Shifted mode VSCALE1 for EMU_STATUS */ -#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 6) /**< Shifted mode VSCALE2 for EMU_STATUS */ -#define EMU_STATUS_RACACTIVE (0x1UL << 10) /**< RAC active */ -#define _EMU_STATUS_RACACTIVE_SHIFT 10 /**< Shift value for EMU_RACACTIVE */ -#define _EMU_STATUS_RACACTIVE_MASK 0x400UL /**< Bit mask for EMU_RACACTIVE */ -#define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_RACACTIVE_DEFAULT (_EMU_STATUS_RACACTIVE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_EM4IORET (0x1UL << 12) /**< EM4 IO retention status */ -#define _EMU_STATUS_EM4IORET_SHIFT 12 /**< Shift value for EMU_EM4IORET */ -#define _EMU_STATUS_EM4IORET_MASK 0x1000UL /**< Bit mask for EMU_EM4IORET */ -#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_EM2ENTERED (0x1UL << 14) /**< EM2 entered */ -#define _EMU_STATUS_EM2ENTERED_SHIFT 14 /**< Shift value for EMU_EM2ENTERED */ -#define _EMU_STATUS_EM2ENTERED_MASK 0x4000UL /**< Bit mask for EMU_EM2ENTERED */ -#define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_EM2ENTERED_DEFAULT (_EMU_STATUS_EM2ENTERED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000080UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0xFFFFD4FFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_LOCK (0x1UL << 0) /**< Lock status */ +#define _EMU_STATUS_LOCK_SHIFT 0 /**< Shift value for EMU_LOCK */ +#define _EMU_STATUS_LOCK_MASK 0x1UL /**< Bit mask for EMU_LOCK */ +#define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_STATUS */ +#define _EMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_DEFAULT (_EMU_STATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_LOCK_UNLOCKED (_EMU_STATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_LOCKED (_EMU_STATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1) /**< First Temp done */ +#define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1 /**< Shift value for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL /**< Bit mask for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE_DEFAULT (_EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 2) /**< Temp active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 2 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE (0x1UL << 3) /**< Temp Average active */ +#define _EMU_STATUS_TEMPAVGACTIVE_SHIFT 3 /**< Shift value for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE_DEFAULT (_EMU_STATUS_TEMPAVGACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 4) /**< Vscale busy */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 4 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x10UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED (0x1UL << 5) /**< Vscale failed */ +#define _EMU_STATUS_VSCALEFAILED_SHIFT 5 /**< Shift value for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_MASK 0x20UL /**< Bit mask for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED_DEFAULT (_EMU_STATUS_VSCALEFAILED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 6 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0xC0UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 6) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE1 (_EMU_STATUS_VSCALE_VSCALE1 << 6) /**< Shifted mode VSCALE1 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 6) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE (0x1UL << 10) /**< RAC active */ +#define _EMU_STATUS_RACACTIVE_SHIFT 10 /**< Shift value for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_MASK 0x400UL /**< Bit mask for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE_DEFAULT (_EMU_STATUS_RACACTIVE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 12) /**< EM4 IO retention status */ +#define _EMU_STATUS_EM4IORET_SHIFT 12 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x1000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED (0x1UL << 14) /**< EM2 entered */ +#define _EMU_STATUS_EM2ENTERED_SHIFT 14 /**< Shift value for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_MASK 0x4000UL /**< Bit mask for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED_DEFAULT (_EMU_STATUS_EM2ENTERED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_STATUS */ /* Bit fields for EMU TEMP */ -#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ -#define _EMU_TEMP_MASK 0x07FF07FFUL /**< Mask for EMU_TEMP */ -#define _EMU_TEMP_TEMPLSB_SHIFT 0 /**< Shift value for EMU_TEMPLSB */ -#define _EMU_TEMP_TEMPLSB_MASK 0x3UL /**< Bit mask for EMU_TEMPLSB */ -#define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ -#define EMU_TEMP_TEMPLSB_DEFAULT (_EMU_TEMP_TEMPLSB_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ -#define _EMU_TEMP_TEMP_SHIFT 2 /**< Shift value for EMU_TEMP */ -#define _EMU_TEMP_TEMP_MASK 0x7FCUL /**< Bit mask for EMU_TEMP */ -#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ -#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_TEMP */ -#define _EMU_TEMP_TEMPAVG_SHIFT 16 /**< Shift value for EMU_TEMPAVG */ -#define _EMU_TEMP_TEMPAVG_MASK 0x7FF0000UL /**< Bit mask for EMU_TEMPAVG */ -#define _EMU_TEMP_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ -#define EMU_TEMP_TEMPAVG_DEFAULT (_EMU_TEMP_TEMPAVG_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x07FF07FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMPLSB_SHIFT 0 /**< Shift value for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_MASK 0x3UL /**< Bit mask for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPLSB_DEFAULT (_EMU_TEMP_TEMPLSB_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 2 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0x7FCUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMPAVG_SHIFT 16 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_MASK 0x7FF0000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPAVG_DEFAULT (_EMU_TEMP_TEMPAVG_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMP */ /* Bit fields for EMU RSTCTRL */ -#define _EMU_RSTCTRL_RESETVALUE 0x00060407UL /**< Default value for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_MASK 0xC006C5CFUL /**< Mask for EMU_RSTCTRL */ -#define EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0) /**< Enable WDOG0 reset */ -#define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0 /**< Shift value for EMU_WDOG0RMODE */ -#define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL /**< Bit mask for EMU_WDOG0RMODE */ -#define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_WDOG0RMODE_DEFAULT (_EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_WDOG0RMODE_DISABLED (_EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_WDOG0RMODE_ENABLED (_EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_SYSRMODE (0x1UL << 2) /**< Enable M33 System reset */ -#define _EMU_RSTCTRL_SYSRMODE_SHIFT 2 /**< Shift value for EMU_SYSRMODE */ -#define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL /**< Bit mask for EMU_SYSRMODE */ -#define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_SYSRMODE_DEFAULT (_EMU_RSTCTRL_SYSRMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_SYSRMODE_DISABLED (_EMU_RSTCTRL_SYSRMODE_DISABLED << 2) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_SYSRMODE_ENABLED (_EMU_RSTCTRL_SYSRMODE_ENABLED << 2) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3) /**< Enable M33 Lockup reset */ -#define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3 /**< Shift value for EMU_LOCKUPRMODE */ -#define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL /**< Bit mask for EMU_LOCKUPRMODE */ -#define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_LOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_LOCKUPRMODE_DISABLED (_EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_LOCKUPRMODE_ENABLED (_EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6) /**< Enable AVDD BOD reset */ -#define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6 /**< Shift value for EMU_AVDDBODRMODE */ -#define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL /**< Bit mask for EMU_AVDDBODRMODE */ -#define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_AVDDBODRMODE_DEFAULT (_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_AVDDBODRMODE_DISABLED (_EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_AVDDBODRMODE_ENABLED (_EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7) /**< Enable VDDIO0 BOD reset */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7 /**< Shift value for EMU_IOVDD0BODRMODE */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL /**< Bit mask for EMU_IOVDD0BODRMODE */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT (_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DECBODRMODE (0x1UL << 10) /**< Enable DECBOD reset */ -#define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10 /**< Shift value for EMU_DECBODRMODE */ -#define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL /**< Bit mask for EMU_DECBODRMODE */ -#define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DECBODRMODE_DEFAULT (_EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DECBODRMODE_DISABLED (_EMU_RSTCTRL_DECBODRMODE_DISABLED << 10) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DECBODRMODE_ENABLED (_EMU_RSTCTRL_DECBODRMODE_ENABLED << 10) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_RESETVALUE 0x00060407UL /**< Default value for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_MASK 0xC006C5CFUL /**< Mask for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0) /**< Enable WDOG0 reset */ +#define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0 /**< Shift value for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL /**< Bit mask for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DEFAULT (_EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DISABLED (_EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_ENABLED (_EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE (0x1UL << 2) /**< Enable M33 System reset */ +#define _EMU_RSTCTRL_SYSRMODE_SHIFT 2 /**< Shift value for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL /**< Bit mask for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DEFAULT (_EMU_RSTCTRL_SYSRMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DISABLED (_EMU_RSTCTRL_SYSRMODE_DISABLED << 2) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_ENABLED (_EMU_RSTCTRL_SYSRMODE_ENABLED << 2) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3) /**< Enable M33 Lockup reset */ +#define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3 /**< Shift value for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL /**< Bit mask for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DISABLED (_EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_ENABLED (_EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6) /**< Enable AVDD BOD reset */ +#define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6 /**< Shift value for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL /**< Bit mask for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DEFAULT (_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DISABLED (_EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_ENABLED (_EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7) /**< Enable VDDIO0 BOD reset */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7 /**< Shift value for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL /**< Bit mask for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT (_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE (0x1UL << 10) /**< Enable DECBOD reset */ +#define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10 /**< Shift value for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL /**< Bit mask for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DEFAULT (_EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DISABLED (_EMU_RSTCTRL_DECBODRMODE_DISABLED << 10) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_ENABLED (_EMU_RSTCTRL_DECBODRMODE_ENABLED << 10) /**< Shifted mode ENABLED for EMU_RSTCTRL */ /* Bit fields for EMU RSTCAUSE */ -#define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_RSTCAUSE */ -#define _EMU_RSTCAUSE_MASK 0x8006FFFFUL /**< Mask for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_POR (0x1UL << 0) /**< Power On Reset */ -#define _EMU_RSTCAUSE_POR_SHIFT 0 /**< Shift value for EMU_POR */ -#define _EMU_RSTCAUSE_POR_MASK 0x1UL /**< Bit mask for EMU_POR */ -#define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_POR_DEFAULT (_EMU_RSTCAUSE_POR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_PIN (0x1UL << 1) /**< Pin Reset */ -#define _EMU_RSTCAUSE_PIN_SHIFT 1 /**< Shift value for EMU_PIN */ -#define _EMU_RSTCAUSE_PIN_MASK 0x2UL /**< Bit mask for EMU_PIN */ -#define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_PIN_DEFAULT (_EMU_RSTCAUSE_PIN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_EM4 (0x1UL << 2) /**< EM4 Wakeup Reset */ -#define _EMU_RSTCAUSE_EM4_SHIFT 2 /**< Shift value for EMU_EM4 */ -#define _EMU_RSTCAUSE_EM4_MASK 0x4UL /**< Bit mask for EMU_EM4 */ -#define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_EM4_DEFAULT (_EMU_RSTCAUSE_EM4_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_WDOG0 (0x1UL << 3) /**< Watchdog 0 Reset */ -#define _EMU_RSTCAUSE_WDOG0_SHIFT 3 /**< Shift value for EMU_WDOG0 */ -#define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL /**< Bit mask for EMU_WDOG0 */ -#define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_WDOG0_DEFAULT (_EMU_RSTCAUSE_WDOG0_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_WDOG1 (0x1UL << 4) /**< Watchdog 1 Reset */ -#define _EMU_RSTCAUSE_WDOG1_SHIFT 4 /**< Shift value for EMU_WDOG1 */ -#define _EMU_RSTCAUSE_WDOG1_MASK 0x10UL /**< Bit mask for EMU_WDOG1 */ -#define _EMU_RSTCAUSE_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_WDOG1_DEFAULT (_EMU_RSTCAUSE_WDOG1_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_LOCKUP (0x1UL << 5) /**< M33 Core Lockup Reset */ -#define _EMU_RSTCAUSE_LOCKUP_SHIFT 5 /**< Shift value for EMU_LOCKUP */ -#define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL /**< Bit mask for EMU_LOCKUP */ -#define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_LOCKUP_DEFAULT (_EMU_RSTCAUSE_LOCKUP_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_SYSREQ (0x1UL << 6) /**< M33 Core Sys Reset */ -#define _EMU_RSTCAUSE_SYSREQ_SHIFT 6 /**< Shift value for EMU_SYSREQ */ -#define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL /**< Bit mask for EMU_SYSREQ */ -#define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_SYSREQ_DEFAULT (_EMU_RSTCAUSE_SYSREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DVDDBOD (0x1UL << 7) /**< HVBOD Reset */ -#define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7 /**< Shift value for EMU_DVDDBOD */ -#define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL /**< Bit mask for EMU_DVDDBOD */ -#define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DVDDBOD_DEFAULT (_EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8) /**< LEBOD Reset */ -#define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8 /**< Shift value for EMU_DVDDLEBOD */ -#define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL /**< Bit mask for EMU_DVDDLEBOD */ -#define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DVDDLEBOD_DEFAULT (_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DECBOD (0x1UL << 9) /**< LVBOD Reset */ -#define _EMU_RSTCAUSE_DECBOD_SHIFT 9 /**< Shift value for EMU_DECBOD */ -#define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL /**< Bit mask for EMU_DECBOD */ -#define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DECBOD_DEFAULT (_EMU_RSTCAUSE_DECBOD_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10) /**< LEBOD1 Reset */ -#define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10 /**< Shift value for EMU_AVDDBOD */ -#define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL /**< Bit mask for EMU_AVDDBOD */ -#define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_AVDDBOD_DEFAULT (_EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11) /**< LEBOD2 Reset */ -#define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11 /**< Shift value for EMU_IOVDD0BOD */ -#define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL /**< Bit mask for EMU_IOVDD0BOD */ -#define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_IOVDD0BOD_DEFAULT (_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_SETAMPER (0x1UL << 13) /**< SE Tamper event Reset */ -#define _EMU_RSTCAUSE_SETAMPER_SHIFT 13 /**< Shift value for EMU_SETAMPER */ -#define _EMU_RSTCAUSE_SETAMPER_MASK 0x2000UL /**< Bit mask for EMU_SETAMPER */ -#define _EMU_RSTCAUSE_SETAMPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_SETAMPER_DEFAULT (_EMU_RSTCAUSE_SETAMPER_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_VREGIN (0x1UL << 31) /**< DCDC VREGIN comparator */ -#define _EMU_RSTCAUSE_VREGIN_SHIFT 31 /**< Shift value for EMU_VREGIN */ -#define _EMU_RSTCAUSE_VREGIN_MASK 0x80000000UL /**< Bit mask for EMU_VREGIN */ -#define _EMU_RSTCAUSE_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_VREGIN_DEFAULT (_EMU_RSTCAUSE_VREGIN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_RSTCAUSE */ +#define _EMU_RSTCAUSE_MASK 0x8006FFFFUL /**< Mask for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR (0x1UL << 0) /**< Power On Reset */ +#define _EMU_RSTCAUSE_POR_SHIFT 0 /**< Shift value for EMU_POR */ +#define _EMU_RSTCAUSE_POR_MASK 0x1UL /**< Bit mask for EMU_POR */ +#define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR_DEFAULT (_EMU_RSTCAUSE_POR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN (0x1UL << 1) /**< Pin Reset */ +#define _EMU_RSTCAUSE_PIN_SHIFT 1 /**< Shift value for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_MASK 0x2UL /**< Bit mask for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN_DEFAULT (_EMU_RSTCAUSE_PIN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4 (0x1UL << 2) /**< EM4 Wakeup Reset */ +#define _EMU_RSTCAUSE_EM4_SHIFT 2 /**< Shift value for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_MASK 0x4UL /**< Bit mask for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4_DEFAULT (_EMU_RSTCAUSE_EM4_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0 (0x1UL << 3) /**< Watchdog 0 Reset */ +#define _EMU_RSTCAUSE_WDOG0_SHIFT 3 /**< Shift value for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL /**< Bit mask for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0_DEFAULT (_EMU_RSTCAUSE_WDOG0_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG1 (0x1UL << 4) /**< Watchdog 1 Reset */ +#define _EMU_RSTCAUSE_WDOG1_SHIFT 4 /**< Shift value for EMU_WDOG1 */ +#define _EMU_RSTCAUSE_WDOG1_MASK 0x10UL /**< Bit mask for EMU_WDOG1 */ +#define _EMU_RSTCAUSE_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG1_DEFAULT (_EMU_RSTCAUSE_WDOG1_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP (0x1UL << 5) /**< M33 Core Lockup Reset */ +#define _EMU_RSTCAUSE_LOCKUP_SHIFT 5 /**< Shift value for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL /**< Bit mask for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP_DEFAULT (_EMU_RSTCAUSE_LOCKUP_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ (0x1UL << 6) /**< M33 Core Sys Reset */ +#define _EMU_RSTCAUSE_SYSREQ_SHIFT 6 /**< Shift value for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL /**< Bit mask for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ_DEFAULT (_EMU_RSTCAUSE_SYSREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD (0x1UL << 7) /**< HVBOD Reset */ +#define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7 /**< Shift value for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL /**< Bit mask for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD_DEFAULT (_EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8) /**< LEBOD Reset */ +#define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8 /**< Shift value for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL /**< Bit mask for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD_DEFAULT (_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD (0x1UL << 9) /**< LVBOD Reset */ +#define _EMU_RSTCAUSE_DECBOD_SHIFT 9 /**< Shift value for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL /**< Bit mask for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD_DEFAULT (_EMU_RSTCAUSE_DECBOD_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10) /**< LEBOD1 Reset */ +#define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD_DEFAULT (_EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11) /**< LEBOD2 Reset */ +#define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD_DEFAULT (_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SETAMPER (0x1UL << 13) /**< SE Tamper event Reset */ +#define _EMU_RSTCAUSE_SETAMPER_SHIFT 13 /**< Shift value for EMU_SETAMPER */ +#define _EMU_RSTCAUSE_SETAMPER_MASK 0x2000UL /**< Bit mask for EMU_SETAMPER */ +#define _EMU_RSTCAUSE_SETAMPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SETAMPER_DEFAULT (_EMU_RSTCAUSE_SETAMPER_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN (0x1UL << 31) /**< DCDC VREGIN comparator */ +#define _EMU_RSTCAUSE_VREGIN_SHIFT 31 /**< Shift value for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_MASK 0x80000000UL /**< Bit mask for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN_DEFAULT (_EMU_RSTCAUSE_VREGIN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ /* Bit fields for EMU TAMPERRSTCAUSE */ -#define _EMU_TAMPERRSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_TAMPERRSTCAUSE */ -#define _EMU_TAMPERRSTCAUSE_MASK 0xFFFFFFFFUL /**< Mask for EMU_TAMPERRSTCAUSE */ -#define _EMU_TAMPERRSTCAUSE_TAMPERRST_SHIFT 0 /**< Shift value for EMU_TAMPERRST */ -#define _EMU_TAMPERRSTCAUSE_TAMPERRST_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_TAMPERRST */ -#define _EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TAMPERRSTCAUSE */ -#define EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT (_EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_MASK 0xFFFFFFFFUL /**< Mask for EMU_TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_SHIFT 0 /**< Shift value for EMU_TAMPERRST */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_TAMPERRST */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TAMPERRSTCAUSE */ +#define EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT (_EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TAMPERRSTCAUSE */ /* Bit fields for EMU DGIF */ -#define _EMU_DGIF_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIF */ -#define _EMU_DGIF_MASK 0xE1000000UL /**< Mask for EMU_DGIF */ -#define EMU_DGIF_EM23WAKEUPDGIF (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ -#define _EMU_DGIF_EM23WAKEUPDGIF_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIF */ -#define _EMU_DGIF_EM23WAKEUPDGIF_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIF */ -#define _EMU_DGIF_EM23WAKEUPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_EM23WAKEUPDGIF_DEFAULT (_EMU_DGIF_EM23WAKEUPDGIF_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPDGIF (0x1UL << 29) /**< Temperature Interrupt flag */ -#define _EMU_DGIF_TEMPDGIF_SHIFT 29 /**< Shift value for EMU_TEMPDGIF */ -#define _EMU_DGIF_TEMPDGIF_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIF */ -#define _EMU_DGIF_TEMPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPDGIF_DEFAULT (_EMU_DGIF_TEMPDGIF_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPLOWDGIF (0x1UL << 30) /**< Temperature low Interrupt flag */ -#define _EMU_DGIF_TEMPLOWDGIF_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIF */ -#define _EMU_DGIF_TEMPLOWDGIF_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIF */ -#define _EMU_DGIF_TEMPLOWDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPLOWDGIF_DEFAULT (_EMU_DGIF_TEMPLOWDGIF_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPHIGHDGIF (0x1UL << 31) /**< Temperature high Interrupt flag */ -#define _EMU_DGIF_TEMPHIGHDGIF_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIF */ -#define _EMU_DGIF_TEMPHIGHDGIF_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIF */ -#define _EMU_DGIF_TEMPHIGHDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPHIGHDGIF_DEFAULT (_EMU_DGIF_TEMPHIGHDGIF_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define _EMU_DGIF_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIF */ +#define _EMU_DGIF_MASK 0xE1000000UL /**< Mask for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_DGIF_EM23WAKEUPDGIF_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF_DEFAULT (_EMU_DGIF_EM23WAKEUPDGIF_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_DGIF_TEMPDGIF_SHIFT 29 /**< Shift value for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF_DEFAULT (_EMU_DGIF_TEMPDGIF_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_DGIF_TEMPLOWDGIF_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF_DEFAULT (_EMU_DGIF_TEMPLOWDGIF_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_DGIF_TEMPHIGHDGIF_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF_DEFAULT (_EMU_DGIF_TEMPHIGHDGIF_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIF */ /* Bit fields for EMU DGIEN */ -#define _EMU_DGIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIEN */ -#define _EMU_DGIEN_MASK 0xE1000000UL /**< Mask for EMU_DGIEN */ -#define EMU_DGIEN_EM23WAKEUPDGIEN (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ -#define _EMU_DGIEN_EM23WAKEUPDGIEN_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIEN */ -#define _EMU_DGIEN_EM23WAKEUPDGIEN_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIEN */ -#define _EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT (_EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPDGIEN (0x1UL << 29) /**< Temperature Interrupt enable */ -#define _EMU_DGIEN_TEMPDGIEN_SHIFT 29 /**< Shift value for EMU_TEMPDGIEN */ -#define _EMU_DGIEN_TEMPDGIEN_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIEN */ -#define _EMU_DGIEN_TEMPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPDGIEN_DEFAULT (_EMU_DGIEN_TEMPDGIEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPLOWDGIEN (0x1UL << 30) /**< Temperature low Interrupt enable */ -#define _EMU_DGIEN_TEMPLOWDGIEN_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIEN */ -#define _EMU_DGIEN_TEMPLOWDGIEN_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIEN */ -#define _EMU_DGIEN_TEMPLOWDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPLOWDGIEN_DEFAULT (_EMU_DGIEN_TEMPLOWDGIEN_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPHIGHDGIEN (0x1UL << 31) /**< Temperature high Interrupt enable */ -#define _EMU_DGIEN_TEMPHIGHDGIEN_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIEN */ -#define _EMU_DGIEN_TEMPHIGHDGIEN_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIEN */ -#define _EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT (_EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define _EMU_DGIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIEN */ +#define _EMU_DGIEN_MASK 0xE1000000UL /**< Mask for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT (_EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_DGIEN_TEMPDGIEN_SHIFT 29 /**< Shift value for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN_DEFAULT (_EMU_DGIEN_TEMPDGIEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_DGIEN_TEMPLOWDGIEN_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN_DEFAULT (_EMU_DGIEN_TEMPLOWDGIEN_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT (_EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIEN */ /* Bit fields for EMU EFPIF */ -#define _EMU_EFPIF_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIF */ -#define _EMU_EFPIF_MASK 0x00000001UL /**< Mask for EMU_EFPIF */ -#define EMU_EFPIF_EFPIF (0x1UL << 0) /**< EFP Interrupt Flag */ -#define _EMU_EFPIF_EFPIF_SHIFT 0 /**< Shift value for EMU_EFPIF */ -#define _EMU_EFPIF_EFPIF_MASK 0x1UL /**< Bit mask for EMU_EFPIF */ -#define _EMU_EFPIF_EFPIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIF */ -#define EMU_EFPIF_EFPIF_DEFAULT (_EMU_EFPIF_EFPIF_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIF */ +#define _EMU_EFPIF_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIF */ +#define _EMU_EFPIF_MASK 0x00000001UL /**< Mask for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF (0x1UL << 0) /**< EFP Interrupt Flag */ +#define _EMU_EFPIF_EFPIF_SHIFT 0 /**< Shift value for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_MASK 0x1UL /**< Bit mask for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF_DEFAULT (_EMU_EFPIF_EFPIF_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIF */ /* Bit fields for EMU EFPIEN */ -#define _EMU_EFPIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIEN */ -#define _EMU_EFPIEN_MASK 0x00000001UL /**< Mask for EMU_EFPIEN */ -#define EMU_EFPIEN_EFPIEN (0x1UL << 0) /**< EFP Interrupt enable */ -#define _EMU_EFPIEN_EFPIEN_SHIFT 0 /**< Shift value for EMU_EFPIEN */ -#define _EMU_EFPIEN_EFPIEN_MASK 0x1UL /**< Bit mask for EMU_EFPIEN */ -#define _EMU_EFPIEN_EFPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIEN */ -#define EMU_EFPIEN_EFPIEN_DEFAULT (_EMU_EFPIEN_EFPIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIEN */ +#define _EMU_EFPIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIEN */ +#define _EMU_EFPIEN_MASK 0x00000001UL /**< Mask for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN (0x1UL << 0) /**< EFP Interrupt enable */ +#define _EMU_EFPIEN_EFPIEN_SHIFT 0 /**< Shift value for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_MASK 0x1UL /**< Bit mask for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN_DEFAULT (_EMU_EFPIEN_EFPIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIEN */ /** @} End of group EFR32SG23_EMU_BitFields */ /** @} End of group EFR32SG23_EMU */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_eusart.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_eusart.h index 18b04eac04..2796a29b15 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_eusart.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_eusart.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_EUSART_H #define EFR32SG23_EUSART_H - #define EUSART_HAS_SET_CLEAR /**************************************************************************//** @@ -43,107 +42,106 @@ *****************************************************************************/ /** EUSART Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t EN; /**< Enable Register */ - __IOM uint32_t CFG0; /**< Configuration 0 Register */ - __IOM uint32_t CFG1; /**< Configuration 1 Register */ - __IOM uint32_t CFG2; /**< Configuration 2 Register */ - __IOM uint32_t FRAMECFG; /**< Frame Format Register */ - __IOM uint32_t DTXDATCFG; /**< Default TX DATA Register */ - __IOM uint32_t IRHFCFG; /**< HF IrDA Mod Config Register */ - __IOM uint32_t IRLFCFG; /**< LF IrDA Pulse Config Register */ - __IOM uint32_t TIMINGCFG; /**< Timing Register */ - __IOM uint32_t STARTFRAMECFG; /**< Start Frame Register */ - __IOM uint32_t SIGFRAMECFG; /**< Signal Frame Register */ - __IOM uint32_t CLKDIV; /**< Clock Divider Register */ - __IOM uint32_t TRIGCTRL; /**< Trigger Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t RXDATA; /**< RX Data Register */ - __IM uint32_t RXDATAP; /**< RX Data Peek Register */ - __IOM uint32_t TXDATA; /**< TX Data Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - uint32_t RESERVED0[42U]; /**< Reserved for future use */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - uint32_t RESERVED2[959U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t EN_SET; /**< Enable Register */ - __IOM uint32_t CFG0_SET; /**< Configuration 0 Register */ - __IOM uint32_t CFG1_SET; /**< Configuration 1 Register */ - __IOM uint32_t CFG2_SET; /**< Configuration 2 Register */ - __IOM uint32_t FRAMECFG_SET; /**< Frame Format Register */ - __IOM uint32_t DTXDATCFG_SET; /**< Default TX DATA Register */ - __IOM uint32_t IRHFCFG_SET; /**< HF IrDA Mod Config Register */ - __IOM uint32_t IRLFCFG_SET; /**< LF IrDA Pulse Config Register */ - __IOM uint32_t TIMINGCFG_SET; /**< Timing Register */ - __IOM uint32_t STARTFRAMECFG_SET; /**< Start Frame Register */ - __IOM uint32_t SIGFRAMECFG_SET; /**< Signal Frame Register */ - __IOM uint32_t CLKDIV_SET; /**< Clock Divider Register */ - __IOM uint32_t TRIGCTRL_SET; /**< Trigger Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t RXDATA_SET; /**< RX Data Register */ - __IM uint32_t RXDATAP_SET; /**< RX Data Peek Register */ - __IOM uint32_t TXDATA_SET; /**< TX Data Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - uint32_t RESERVED3[42U]; /**< Reserved for future use */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - uint32_t RESERVED5[959U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t EN_CLR; /**< Enable Register */ - __IOM uint32_t CFG0_CLR; /**< Configuration 0 Register */ - __IOM uint32_t CFG1_CLR; /**< Configuration 1 Register */ - __IOM uint32_t CFG2_CLR; /**< Configuration 2 Register */ - __IOM uint32_t FRAMECFG_CLR; /**< Frame Format Register */ - __IOM uint32_t DTXDATCFG_CLR; /**< Default TX DATA Register */ - __IOM uint32_t IRHFCFG_CLR; /**< HF IrDA Mod Config Register */ - __IOM uint32_t IRLFCFG_CLR; /**< LF IrDA Pulse Config Register */ - __IOM uint32_t TIMINGCFG_CLR; /**< Timing Register */ - __IOM uint32_t STARTFRAMECFG_CLR; /**< Start Frame Register */ - __IOM uint32_t SIGFRAMECFG_CLR; /**< Signal Frame Register */ - __IOM uint32_t CLKDIV_CLR; /**< Clock Divider Register */ - __IOM uint32_t TRIGCTRL_CLR; /**< Trigger Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t RXDATA_CLR; /**< RX Data Register */ - __IM uint32_t RXDATAP_CLR; /**< RX Data Peek Register */ - __IOM uint32_t TXDATA_CLR; /**< TX Data Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - uint32_t RESERVED6[42U]; /**< Reserved for future use */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - uint32_t RESERVED8[959U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t EN_TGL; /**< Enable Register */ - __IOM uint32_t CFG0_TGL; /**< Configuration 0 Register */ - __IOM uint32_t CFG1_TGL; /**< Configuration 1 Register */ - __IOM uint32_t CFG2_TGL; /**< Configuration 2 Register */ - __IOM uint32_t FRAMECFG_TGL; /**< Frame Format Register */ - __IOM uint32_t DTXDATCFG_TGL; /**< Default TX DATA Register */ - __IOM uint32_t IRHFCFG_TGL; /**< HF IrDA Mod Config Register */ - __IOM uint32_t IRLFCFG_TGL; /**< LF IrDA Pulse Config Register */ - __IOM uint32_t TIMINGCFG_TGL; /**< Timing Register */ - __IOM uint32_t STARTFRAMECFG_TGL; /**< Start Frame Register */ - __IOM uint32_t SIGFRAMECFG_TGL; /**< Signal Frame Register */ - __IOM uint32_t CLKDIV_TGL; /**< Clock Divider Register */ - __IOM uint32_t TRIGCTRL_TGL; /**< Trigger Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t RXDATA_TGL; /**< RX Data Register */ - __IM uint32_t RXDATAP_TGL; /**< RX Data Peek Register */ - __IOM uint32_t TXDATA_TGL; /**< TX Data Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - uint32_t RESERVED9[42U]; /**< Reserved for future use */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG0; /**< Configuration 0 Register */ + __IOM uint32_t CFG1; /**< Configuration 1 Register */ + __IOM uint32_t CFG2; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL; /**< Trigger Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t RXDATA; /**< RX Data Register */ + __IM uint32_t RXDATAP; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA; /**< TX Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED0[42U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG0_SET; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_SET; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_SET; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_SET; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_SET; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_SET; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_SET; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_SET; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_SET; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_SET; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_SET; /**< Trigger Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t RXDATA_SET; /**< RX Data Register */ + __IM uint32_t RXDATAP_SET; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< TX Data Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED3[42U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG0_CLR; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_CLR; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_CLR; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_CLR; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_CLR; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_CLR; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_CLR; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_CLR; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_CLR; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_CLR; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< Trigger Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t RXDATA_CLR; /**< RX Data Register */ + __IM uint32_t RXDATAP_CLR; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Data Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED6[42U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG0_TGL; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_TGL; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_TGL; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_TGL; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_TGL; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_TGL; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_TGL; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_TGL; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_TGL; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_TGL; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< Trigger Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t RXDATA_TGL; /**< RX Data Register */ + __IM uint32_t RXDATAP_TGL; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Data Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + uint32_t RESERVED9[42U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ } EUSART_TypeDef; /** @} End of group EFR32SG23_EUSART */ @@ -155,1038 +153,1038 @@ typedef struct *****************************************************************************/ /* Bit fields for EUSART IPVERSION */ -#define _EUSART_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for EUSART_IPVERSION */ -#define _EUSART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EUSART_IPVERSION */ -#define _EUSART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EUSART_IPVERSION */ -#define _EUSART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_IPVERSION */ -#define _EUSART_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_IPVERSION */ -#define EUSART_IPVERSION_IPVERSION_DEFAULT (_EUSART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_IPVERSION */ +#define EUSART_IPVERSION_IPVERSION_DEFAULT (_EUSART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IPVERSION */ /* Bit fields for EUSART EN */ -#define _EUSART_EN_RESETVALUE 0x00000000UL /**< Default value for EUSART_EN */ -#define _EUSART_EN_MASK 0x00000003UL /**< Mask for EUSART_EN */ -#define EUSART_EN_EN (0x1UL << 0) /**< Module enable */ -#define _EUSART_EN_EN_SHIFT 0 /**< Shift value for EUSART_EN */ -#define _EUSART_EN_EN_MASK 0x1UL /**< Bit mask for EUSART_EN */ -#define _EUSART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ -#define EUSART_EN_EN_DEFAULT (_EUSART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_EN */ -#define EUSART_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _EUSART_EN_DISABLING_SHIFT 1 /**< Shift value for EUSART_DISABLING */ -#define _EUSART_EN_DISABLING_MASK 0x2UL /**< Bit mask for EUSART_DISABLING */ -#define _EUSART_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ -#define EUSART_EN_DISABLING_DEFAULT (_EUSART_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_EN */ +#define _EUSART_EN_RESETVALUE 0x00000000UL /**< Default value for EUSART_EN */ +#define _EUSART_EN_MASK 0x00000003UL /**< Mask for EUSART_EN */ +#define EUSART_EN_EN (0x1UL << 0) /**< Module enable */ +#define _EUSART_EN_EN_SHIFT 0 /**< Shift value for EUSART_EN */ +#define _EUSART_EN_EN_MASK 0x1UL /**< Bit mask for EUSART_EN */ +#define _EUSART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ +#define EUSART_EN_EN_DEFAULT (_EUSART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_EN */ +#define EUSART_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _EUSART_EN_DISABLING_SHIFT 1 /**< Shift value for EUSART_DISABLING */ +#define _EUSART_EN_DISABLING_MASK 0x2UL /**< Bit mask for EUSART_DISABLING */ +#define _EUSART_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ +#define EUSART_EN_DISABLING_DEFAULT (_EUSART_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_EN */ /* Bit fields for EUSART CFG0 */ -#define _EUSART_CFG0_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG0 */ -#define _EUSART_CFG0_MASK 0xC1D264FFUL /**< Mask for EUSART_CFG0 */ -#define EUSART_CFG0_SYNC (0x1UL << 0) /**< Synchronous Mode */ -#define _EUSART_CFG0_SYNC_SHIFT 0 /**< Shift value for EUSART_SYNC */ -#define _EUSART_CFG0_SYNC_MASK 0x1UL /**< Bit mask for EUSART_SYNC */ -#define _EUSART_CFG0_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_SYNC_ASYNC 0x00000000UL /**< Mode ASYNC for EUSART_CFG0 */ -#define _EUSART_CFG0_SYNC_SYNC 0x00000001UL /**< Mode SYNC for EUSART_CFG0 */ -#define EUSART_CFG0_SYNC_DEFAULT (_EUSART_CFG0_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_SYNC_ASYNC (_EUSART_CFG0_SYNC_ASYNC << 0) /**< Shifted mode ASYNC for EUSART_CFG0 */ -#define EUSART_CFG0_SYNC_SYNC (_EUSART_CFG0_SYNC_SYNC << 0) /**< Shifted mode SYNC for EUSART_CFG0 */ -#define EUSART_CFG0_LOOPBK (0x1UL << 1) /**< Loopback Enable */ -#define _EUSART_CFG0_LOOPBK_SHIFT 1 /**< Shift value for EUSART_LOOPBK */ -#define _EUSART_CFG0_LOOPBK_MASK 0x2UL /**< Bit mask for EUSART_LOOPBK */ -#define _EUSART_CFG0_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_LOOPBK_DEFAULT (_EUSART_CFG0_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_LOOPBK_DISABLE (_EUSART_CFG0_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_LOOPBK_ENABLE (_EUSART_CFG0_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_CCEN (0x1UL << 2) /**< Collision Check Enable */ -#define _EUSART_CFG0_CCEN_SHIFT 2 /**< Shift value for EUSART_CCEN */ -#define _EUSART_CFG0_CCEN_MASK 0x4UL /**< Bit mask for EUSART_CCEN */ -#define _EUSART_CFG0_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_CCEN_DEFAULT (_EUSART_CFG0_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_CCEN_DISABLE (_EUSART_CFG0_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_CCEN_ENABLE (_EUSART_CFG0_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MPM (0x1UL << 3) /**< Multi-Processor Mode */ -#define _EUSART_CFG0_MPM_SHIFT 3 /**< Shift value for EUSART_MPM */ -#define _EUSART_CFG0_MPM_MASK 0x8UL /**< Bit mask for EUSART_MPM */ -#define _EUSART_CFG0_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MPM_DEFAULT (_EUSART_CFG0_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_MPM_DISABLE (_EUSART_CFG0_MPM_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MPM_ENABLE (_EUSART_CFG0_MPM_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ -#define _EUSART_CFG0_MPAB_SHIFT 4 /**< Shift value for EUSART_MPAB */ -#define _EUSART_CFG0_MPAB_MASK 0x10UL /**< Bit mask for EUSART_MPAB */ -#define _EUSART_CFG0_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_MPAB_DEFAULT (_EUSART_CFG0_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_SHIFT 5 /**< Shift value for EUSART_OVS */ -#define _EUSART_CFG0_OVS_MASK 0xE0UL /**< Bit mask for EUSART_OVS */ -#define _EUSART_CFG0_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_X16 0x00000000UL /**< Mode X16 for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_X8 0x00000001UL /**< Mode X8 for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_X6 0x00000002UL /**< Mode X6 for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_X4 0x00000003UL /**< Mode X4 for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_DISABLE 0x00000004UL /**< Mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_DEFAULT (_EUSART_CFG0_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_X16 (_EUSART_CFG0_OVS_X16 << 5) /**< Shifted mode X16 for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_X8 (_EUSART_CFG0_OVS_X8 << 5) /**< Shifted mode X8 for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_X6 (_EUSART_CFG0_OVS_X6 << 5) /**< Shifted mode X6 for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_X4 (_EUSART_CFG0_OVS_X4 << 5) /**< Shifted mode X4 for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_DISABLE (_EUSART_CFG0_OVS_DISABLE << 5) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MSBF (0x1UL << 10) /**< Most Significant Bit First */ -#define _EUSART_CFG0_MSBF_SHIFT 10 /**< Shift value for EUSART_MSBF */ -#define _EUSART_CFG0_MSBF_MASK 0x400UL /**< Bit mask for EUSART_MSBF */ -#define _EUSART_CFG0_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MSBF_DEFAULT (_EUSART_CFG0_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_MSBF_DISABLE (_EUSART_CFG0_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MSBF_ENABLE (_EUSART_CFG0_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_RXINV (0x1UL << 13) /**< Receiver Input Invert */ -#define _EUSART_CFG0_RXINV_SHIFT 13 /**< Shift value for EUSART_RXINV */ -#define _EUSART_CFG0_RXINV_MASK 0x2000UL /**< Bit mask for EUSART_RXINV */ -#define _EUSART_CFG0_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_RXINV_DEFAULT (_EUSART_CFG0_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_RXINV_DISABLE (_EUSART_CFG0_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_RXINV_ENABLE (_EUSART_CFG0_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_TXINV (0x1UL << 14) /**< Transmitter output Invert */ -#define _EUSART_CFG0_TXINV_SHIFT 14 /**< Shift value for EUSART_TXINV */ -#define _EUSART_CFG0_TXINV_MASK 0x4000UL /**< Bit mask for EUSART_TXINV */ -#define _EUSART_CFG0_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_TXINV_DEFAULT (_EUSART_CFG0_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_TXINV_DISABLE (_EUSART_CFG0_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_TXINV_ENABLE (_EUSART_CFG0_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ -#define _EUSART_CFG0_AUTOTRI_SHIFT 17 /**< Shift value for EUSART_AUTOTRI */ -#define _EUSART_CFG0_AUTOTRI_MASK 0x20000UL /**< Bit mask for EUSART_AUTOTRI */ -#define _EUSART_CFG0_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOTRI_DEFAULT (_EUSART_CFG0_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOTRI_DISABLE (_EUSART_CFG0_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOTRI_ENABLE (_EUSART_CFG0_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ -#define _EUSART_CFG0_SKIPPERRF_SHIFT 20 /**< Shift value for EUSART_SKIPPERRF */ -#define _EUSART_CFG0_SKIPPERRF_MASK 0x100000UL /**< Bit mask for EUSART_SKIPPERRF */ -#define _EUSART_CFG0_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_SKIPPERRF_DEFAULT (_EUSART_CFG0_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSDMA (0x1UL << 22) /**< Halt DMA Read On Error */ -#define _EUSART_CFG0_ERRSDMA_SHIFT 22 /**< Shift value for EUSART_ERRSDMA */ -#define _EUSART_CFG0_ERRSDMA_MASK 0x400000UL /**< Bit mask for EUSART_ERRSDMA */ -#define _EUSART_CFG0_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSDMA_DEFAULT (_EUSART_CFG0_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSDMA_DISABLE (_EUSART_CFG0_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSDMA_ENABLE (_EUSART_CFG0_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ -#define _EUSART_CFG0_ERRSRX_SHIFT 23 /**< Shift value for EUSART_ERRSRX */ -#define _EUSART_CFG0_ERRSRX_MASK 0x800000UL /**< Bit mask for EUSART_ERRSRX */ -#define _EUSART_CFG0_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSRX_DEFAULT (_EUSART_CFG0_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSRX_DISABLE (_EUSART_CFG0_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSRX_ENABLE (_EUSART_CFG0_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ -#define _EUSART_CFG0_ERRSTX_SHIFT 24 /**< Shift value for EUSART_ERRSTX */ -#define _EUSART_CFG0_ERRSTX_MASK 0x1000000UL /**< Bit mask for EUSART_ERRSTX */ -#define _EUSART_CFG0_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSTX_DEFAULT (_EUSART_CFG0_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSTX_DISABLE (_EUSART_CFG0_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSTX_ENABLE (_EUSART_CFG0_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ -#define _EUSART_CFG0_MVDIS_SHIFT 30 /**< Shift value for EUSART_MVDIS */ -#define _EUSART_CFG0_MVDIS_MASK 0x40000000UL /**< Bit mask for EUSART_MVDIS */ -#define _EUSART_CFG0_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_MVDIS_DEFAULT (_EUSART_CFG0_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ -#define _EUSART_CFG0_AUTOBAUDEN_SHIFT 31 /**< Shift value for EUSART_AUTOBAUDEN */ -#define _EUSART_CFG0_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for EUSART_AUTOBAUDEN */ -#define _EUSART_CFG0_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOBAUDEN_DEFAULT (_EUSART_CFG0_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG0 */ +#define _EUSART_CFG0_MASK 0xC1D264FFUL /**< Mask for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC (0x1UL << 0) /**< Synchronous Mode */ +#define _EUSART_CFG0_SYNC_SHIFT 0 /**< Shift value for EUSART_SYNC */ +#define _EUSART_CFG0_SYNC_MASK 0x1UL /**< Bit mask for EUSART_SYNC */ +#define _EUSART_CFG0_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_SYNC_ASYNC 0x00000000UL /**< Mode ASYNC for EUSART_CFG0 */ +#define _EUSART_CFG0_SYNC_SYNC 0x00000001UL /**< Mode SYNC for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_DEFAULT (_EUSART_CFG0_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_ASYNC (_EUSART_CFG0_SYNC_ASYNC << 0) /**< Shifted mode ASYNC for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_SYNC (_EUSART_CFG0_SYNC_SYNC << 0) /**< Shifted mode SYNC for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _EUSART_CFG0_LOOPBK_SHIFT 1 /**< Shift value for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_MASK 0x2UL /**< Bit mask for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DEFAULT (_EUSART_CFG0_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DISABLE (_EUSART_CFG0_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_ENABLE (_EUSART_CFG0_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _EUSART_CFG0_CCEN_SHIFT 2 /**< Shift value for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_MASK 0x4UL /**< Bit mask for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DEFAULT (_EUSART_CFG0_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DISABLE (_EUSART_CFG0_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_ENABLE (_EUSART_CFG0_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _EUSART_CFG0_MPM_SHIFT 3 /**< Shift value for EUSART_MPM */ +#define _EUSART_CFG0_MPM_MASK 0x8UL /**< Bit mask for EUSART_MPM */ +#define _EUSART_CFG0_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DEFAULT (_EUSART_CFG0_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DISABLE (_EUSART_CFG0_MPM_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_ENABLE (_EUSART_CFG0_MPM_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _EUSART_CFG0_MPAB_SHIFT 4 /**< Shift value for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_MASK 0x10UL /**< Bit mask for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB_DEFAULT (_EUSART_CFG0_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_SHIFT 5 /**< Shift value for EUSART_OVS */ +#define _EUSART_CFG0_OVS_MASK 0xE0UL /**< Bit mask for EUSART_OVS */ +#define _EUSART_CFG0_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X16 0x00000000UL /**< Mode X16 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X8 0x00000001UL /**< Mode X8 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X6 0x00000002UL /**< Mode X6 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X4 0x00000003UL /**< Mode X4 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_DISABLE 0x00000004UL /**< Mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DEFAULT (_EUSART_CFG0_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X16 (_EUSART_CFG0_OVS_X16 << 5) /**< Shifted mode X16 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X8 (_EUSART_CFG0_OVS_X8 << 5) /**< Shifted mode X8 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X6 (_EUSART_CFG0_OVS_X6 << 5) /**< Shifted mode X6 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X4 (_EUSART_CFG0_OVS_X4 << 5) /**< Shifted mode X4 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DISABLE (_EUSART_CFG0_OVS_DISABLE << 5) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _EUSART_CFG0_MSBF_SHIFT 10 /**< Shift value for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_MASK 0x400UL /**< Bit mask for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DEFAULT (_EUSART_CFG0_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DISABLE (_EUSART_CFG0_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_ENABLE (_EUSART_CFG0_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _EUSART_CFG0_RXINV_SHIFT 13 /**< Shift value for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_MASK 0x2000UL /**< Bit mask for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DEFAULT (_EUSART_CFG0_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DISABLE (_EUSART_CFG0_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_ENABLE (_EUSART_CFG0_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _EUSART_CFG0_TXINV_SHIFT 14 /**< Shift value for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_MASK 0x4000UL /**< Bit mask for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DEFAULT (_EUSART_CFG0_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DISABLE (_EUSART_CFG0_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_ENABLE (_EUSART_CFG0_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _EUSART_CFG0_AUTOTRI_SHIFT 17 /**< Shift value for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_MASK 0x20000UL /**< Bit mask for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DEFAULT (_EUSART_CFG0_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DISABLE (_EUSART_CFG0_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_ENABLE (_EUSART_CFG0_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _EUSART_CFG0_SKIPPERRF_SHIFT 20 /**< Shift value for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_MASK 0x100000UL /**< Bit mask for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF_DEFAULT (_EUSART_CFG0_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA (0x1UL << 22) /**< Halt DMA Read On Error */ +#define _EUSART_CFG0_ERRSDMA_SHIFT 22 /**< Shift value for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_MASK 0x400000UL /**< Bit mask for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DEFAULT (_EUSART_CFG0_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DISABLE (_EUSART_CFG0_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_ENABLE (_EUSART_CFG0_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _EUSART_CFG0_ERRSRX_SHIFT 23 /**< Shift value for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_MASK 0x800000UL /**< Bit mask for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DEFAULT (_EUSART_CFG0_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DISABLE (_EUSART_CFG0_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_ENABLE (_EUSART_CFG0_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _EUSART_CFG0_ERRSTX_SHIFT 24 /**< Shift value for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_MASK 0x1000000UL /**< Bit mask for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DEFAULT (_EUSART_CFG0_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DISABLE (_EUSART_CFG0_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_ENABLE (_EUSART_CFG0_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _EUSART_CFG0_MVDIS_SHIFT 30 /**< Shift value for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_MASK 0x40000000UL /**< Bit mask for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS_DEFAULT (_EUSART_CFG0_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _EUSART_CFG0_AUTOBAUDEN_SHIFT 31 /**< Shift value for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN_DEFAULT (_EUSART_CFG0_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EUSART_CFG0 */ /* Bit fields for EUSART CFG1 */ -#define _EUSART_CFG1_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG1 */ -#define _EUSART_CFG1_MASK 0x7BCF8E7FUL /**< Mask for EUSART_CFG1 */ -#define EUSART_CFG1_DBGHALT (0x1UL << 0) /**< Debug halt */ -#define _EUSART_CFG1_DBGHALT_SHIFT 0 /**< Shift value for EUSART_DBGHALT */ -#define _EUSART_CFG1_DBGHALT_MASK 0x1UL /**< Bit mask for EUSART_DBGHALT */ -#define _EUSART_CFG1_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_DBGHALT_DEFAULT (_EUSART_CFG1_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_DBGHALT_DISABLE (_EUSART_CFG1_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for EUSART_CFG1 */ -#define EUSART_CFG1_DBGHALT_ENABLE (_EUSART_CFG1_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSINV (0x1UL << 1) /**< Clear-to-send Invert Enable */ -#define _EUSART_CFG1_CTSINV_SHIFT 1 /**< Shift value for EUSART_CTSINV */ -#define _EUSART_CFG1_CTSINV_MASK 0x2UL /**< Bit mask for EUSART_CTSINV */ -#define _EUSART_CFG1_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSINV_DEFAULT (_EUSART_CFG1_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_CTSINV_DISABLE (_EUSART_CFG1_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSINV_ENABLE (_EUSART_CFG1_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSEN (0x1UL << 2) /**< Clear-to-send Enable */ -#define _EUSART_CFG1_CTSEN_SHIFT 2 /**< Shift value for EUSART_CTSEN */ -#define _EUSART_CFG1_CTSEN_MASK 0x4UL /**< Bit mask for EUSART_CTSEN */ -#define _EUSART_CFG1_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSEN_DEFAULT (_EUSART_CFG1_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_CTSEN_DISABLE (_EUSART_CFG1_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSEN_ENABLE (_EUSART_CFG1_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_RTSINV (0x1UL << 3) /**< Request-to-send Invert Enable */ -#define _EUSART_CFG1_RTSINV_SHIFT 3 /**< Shift value for EUSART_RTSINV */ -#define _EUSART_CFG1_RTSINV_MASK 0x8UL /**< Bit mask for EUSART_RTSINV */ -#define _EUSART_CFG1_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_RTSINV_DEFAULT (_EUSART_CFG1_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RTSINV_DISABLE (_EUSART_CFG1_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG1 */ -#define EUSART_CFG1_RTSINV_ENABLE (_EUSART_CFG1_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_SHIFT 4 /**< Shift value for EUSART_RXTIMEOUT */ -#define _EUSART_CFG1_RXTIMEOUT_MASK 0x70UL /**< Bit mask for EUSART_RXTIMEOUT */ -#define _EUSART_CFG1_RXTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_DISABLED 0x00000000UL /**< Mode DISABLED for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_ONEFRAME 0x00000001UL /**< Mode ONEFRAME for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_TWOFRAMES 0x00000002UL /**< Mode TWOFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_THREEFRAMES 0x00000003UL /**< Mode THREEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_FOURFRAMES 0x00000004UL /**< Mode FOURFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_FIVEFRAMES 0x00000005UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_SIXFRAMES 0x00000006UL /**< Mode SIXFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_SEVENFRAMES 0x00000007UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_DEFAULT (_EUSART_CFG1_RXTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_DISABLED (_EUSART_CFG1_RXTIMEOUT_DISABLED << 4) /**< Shifted mode DISABLED for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_ONEFRAME (_EUSART_CFG1_RXTIMEOUT_ONEFRAME << 4) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_TWOFRAMES (_EUSART_CFG1_RXTIMEOUT_TWOFRAMES << 4) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_THREEFRAMES (_EUSART_CFG1_RXTIMEOUT_THREEFRAMES << 4) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_FOURFRAMES (_EUSART_CFG1_RXTIMEOUT_FOURFRAMES << 4) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_FIVEFRAMES (_EUSART_CFG1_RXTIMEOUT_FIVEFRAMES << 4) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_SIXFRAMES (_EUSART_CFG1_RXTIMEOUT_SIXFRAMES << 4) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_SEVENFRAMES (_EUSART_CFG1_RXTIMEOUT_SEVENFRAMES << 4) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXDMAWU (0x1UL << 9) /**< Transmitter DMA Wakeup */ -#define _EUSART_CFG1_TXDMAWU_SHIFT 9 /**< Shift value for EUSART_TXDMAWU */ -#define _EUSART_CFG1_TXDMAWU_MASK 0x200UL /**< Bit mask for EUSART_TXDMAWU */ -#define _EUSART_CFG1_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_TXDMAWU_DEFAULT (_EUSART_CFG1_TXDMAWU_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXDMAWU (0x1UL << 10) /**< Receiver DMA Wakeup */ -#define _EUSART_CFG1_RXDMAWU_SHIFT 10 /**< Shift value for EUSART_RXDMAWU */ -#define _EUSART_CFG1_RXDMAWU_MASK 0x400UL /**< Bit mask for EUSART_RXDMAWU */ -#define _EUSART_CFG1_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXDMAWU_DEFAULT (_EUSART_CFG1_RXDMAWU_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_SFUBRX (0x1UL << 11) /**< Start Frame Unblock Receiver */ -#define _EUSART_CFG1_SFUBRX_SHIFT 11 /**< Shift value for EUSART_SFUBRX */ -#define _EUSART_CFG1_SFUBRX_MASK 0x800UL /**< Bit mask for EUSART_SFUBRX */ -#define _EUSART_CFG1_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_SFUBRX_DEFAULT (_EUSART_CFG1_SFUBRX_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXPRSEN (0x1UL << 15) /**< PRS RX Enable */ -#define _EUSART_CFG1_RXPRSEN_SHIFT 15 /**< Shift value for EUSART_RXPRSEN */ -#define _EUSART_CFG1_RXPRSEN_MASK 0x8000UL /**< Bit mask for EUSART_RXPRSEN */ -#define _EUSART_CFG1_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXPRSEN_DEFAULT (_EUSART_CFG1_RXPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_SHIFT 16 /**< Shift value for EUSART_TXFIW */ -#define _EUSART_CFG1_TXFIW_MASK 0xF0000UL /**< Bit mask for EUSART_TXFIW */ -#define _EUSART_CFG1_TXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_DEFAULT (_EUSART_CFG1_TXFIW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_ONEFRAME (_EUSART_CFG1_TXFIW_ONEFRAME << 16) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_TWOFRAMES (_EUSART_CFG1_TXFIW_TWOFRAMES << 16) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_THREEFRAMES (_EUSART_CFG1_TXFIW_THREEFRAMES << 16) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_FOURFRAMES (_EUSART_CFG1_TXFIW_FOURFRAMES << 16) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_FIVEFRAMES (_EUSART_CFG1_TXFIW_FIVEFRAMES << 16) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_SIXFRAMES (_EUSART_CFG1_TXFIW_SIXFRAMES << 16) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_SEVENFRAMES (_EUSART_CFG1_TXFIW_SEVENFRAMES << 16) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_EIGHTFRAMES (_EUSART_CFG1_TXFIW_EIGHTFRAMES << 16) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_NINEFRAMES (_EUSART_CFG1_TXFIW_NINEFRAMES << 16) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_TENFRAMES (_EUSART_CFG1_TXFIW_TENFRAMES << 16) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_ELEVENFRAMES (_EUSART_CFG1_TXFIW_ELEVENFRAMES << 16) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_TWELVEFRAMES (_EUSART_CFG1_TXFIW_TWELVEFRAMES << 16) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_THIRTEENFRAMES (_EUSART_CFG1_TXFIW_THIRTEENFRAMES << 16) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_FOURTEENFRAMES (_EUSART_CFG1_TXFIW_FOURTEENFRAMES << 16) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_FIFTEENFRAMES (_EUSART_CFG1_TXFIW_FIFTEENFRAMES << 16) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_SIXTEENFRAMES (_EUSART_CFG1_TXFIW_SIXTEENFRAMES << 16) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_SHIFT 22 /**< Shift value for EUSART_RTSRXFW */ -#define _EUSART_CFG1_RTSRXFW_MASK 0x3C00000UL /**< Bit mask for EUSART_RTSRXFW */ -#define _EUSART_CFG1_RTSRXFW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_DEFAULT (_EUSART_CFG1_RTSRXFW_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_ONEFRAME (_EUSART_CFG1_RTSRXFW_ONEFRAME << 22) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_TWOFRAMES (_EUSART_CFG1_RTSRXFW_TWOFRAMES << 22) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_THREEFRAMES (_EUSART_CFG1_RTSRXFW_THREEFRAMES << 22) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_FOURFRAMES (_EUSART_CFG1_RTSRXFW_FOURFRAMES << 22) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_FIVEFRAMES (_EUSART_CFG1_RTSRXFW_FIVEFRAMES << 22) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_SIXFRAMES (_EUSART_CFG1_RTSRXFW_SIXFRAMES << 22) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_SEVENFRAMES (_EUSART_CFG1_RTSRXFW_SEVENFRAMES << 22) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_EIGHTFRAMES (_EUSART_CFG1_RTSRXFW_EIGHTFRAMES << 22) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_NINEFRAMES (_EUSART_CFG1_RTSRXFW_NINEFRAMES << 22) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_TENFRAMES (_EUSART_CFG1_RTSRXFW_TENFRAMES << 22) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_ELEVENFRAMES (_EUSART_CFG1_RTSRXFW_ELEVENFRAMES << 22) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_TWELVEFRAMES (_EUSART_CFG1_RTSRXFW_TWELVEFRAMES << 22) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_THIRTEENFRAMES (_EUSART_CFG1_RTSRXFW_THIRTEENFRAMES << 22) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_FOURTEENFRAMES (_EUSART_CFG1_RTSRXFW_FOURTEENFRAMES << 22) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_FIFTEENFRAMES (_EUSART_CFG1_RTSRXFW_FIFTEENFRAMES << 22) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_SIXTEENFRAMES (_EUSART_CFG1_RTSRXFW_SIXTEENFRAMES << 22) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_SHIFT 27 /**< Shift value for EUSART_RXFIW */ -#define _EUSART_CFG1_RXFIW_MASK 0x78000000UL /**< Bit mask for EUSART_RXFIW */ -#define _EUSART_CFG1_RXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_DEFAULT (_EUSART_CFG1_RXFIW_DEFAULT << 27) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_ONEFRAME (_EUSART_CFG1_RXFIW_ONEFRAME << 27) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_TWOFRAMES (_EUSART_CFG1_RXFIW_TWOFRAMES << 27) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_THREEFRAMES (_EUSART_CFG1_RXFIW_THREEFRAMES << 27) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_FOURFRAMES (_EUSART_CFG1_RXFIW_FOURFRAMES << 27) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_FIVEFRAMES (_EUSART_CFG1_RXFIW_FIVEFRAMES << 27) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_SIXFRAMES (_EUSART_CFG1_RXFIW_SIXFRAMES << 27) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_SEVENFRAMES (_EUSART_CFG1_RXFIW_SEVENFRAMES << 27) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_EIGHTFRAMES (_EUSART_CFG1_RXFIW_EIGHTFRAMES << 27) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_NINEFRAMES (_EUSART_CFG1_RXFIW_NINEFRAMES << 27) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_TENFRAMES (_EUSART_CFG1_RXFIW_TENFRAMES << 27) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_ELEVENFRAMES (_EUSART_CFG1_RXFIW_ELEVENFRAMES << 27) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_TWELVEFRAMES (_EUSART_CFG1_RXFIW_TWELVEFRAMES << 27) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_THIRTEENFRAMES (_EUSART_CFG1_RXFIW_THIRTEENFRAMES << 27) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_FOURTEENFRAMES (_EUSART_CFG1_RXFIW_FOURTEENFRAMES << 27) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_FIFTEENFRAMES (_EUSART_CFG1_RXFIW_FIFTEENFRAMES << 27) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_SIXTEENFRAMES (_EUSART_CFG1_RXFIW_SIXTEENFRAMES << 27) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG1 */ +#define _EUSART_CFG1_MASK 0x7BCF8E7FUL /**< Mask for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _EUSART_CFG1_DBGHALT_SHIFT 0 /**< Shift value for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_MASK 0x1UL /**< Bit mask for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DEFAULT (_EUSART_CFG1_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DISABLE (_EUSART_CFG1_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_ENABLE (_EUSART_CFG1_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV (0x1UL << 1) /**< Clear-to-send Invert Enable */ +#define _EUSART_CFG1_CTSINV_SHIFT 1 /**< Shift value for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_MASK 0x2UL /**< Bit mask for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DEFAULT (_EUSART_CFG1_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DISABLE (_EUSART_CFG1_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_ENABLE (_EUSART_CFG1_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN (0x1UL << 2) /**< Clear-to-send Enable */ +#define _EUSART_CFG1_CTSEN_SHIFT 2 /**< Shift value for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_MASK 0x4UL /**< Bit mask for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DEFAULT (_EUSART_CFG1_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DISABLE (_EUSART_CFG1_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_ENABLE (_EUSART_CFG1_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV (0x1UL << 3) /**< Request-to-send Invert Enable */ +#define _EUSART_CFG1_RTSINV_SHIFT 3 /**< Shift value for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_MASK 0x8UL /**< Bit mask for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DEFAULT (_EUSART_CFG1_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DISABLE (_EUSART_CFG1_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_ENABLE (_EUSART_CFG1_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SHIFT 4 /**< Shift value for EUSART_RXTIMEOUT */ +#define _EUSART_CFG1_RXTIMEOUT_MASK 0x70UL /**< Bit mask for EUSART_RXTIMEOUT */ +#define _EUSART_CFG1_RXTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_DISABLED 0x00000000UL /**< Mode DISABLED for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_ONEFRAME 0x00000001UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_TWOFRAMES 0x00000002UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_THREEFRAMES 0x00000003UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_FOURFRAMES 0x00000004UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_FIVEFRAMES 0x00000005UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SIXFRAMES 0x00000006UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SEVENFRAMES 0x00000007UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_DEFAULT (_EUSART_CFG1_RXTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_DISABLED (_EUSART_CFG1_RXTIMEOUT_DISABLED << 4) /**< Shifted mode DISABLED for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_ONEFRAME (_EUSART_CFG1_RXTIMEOUT_ONEFRAME << 4) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_TWOFRAMES (_EUSART_CFG1_RXTIMEOUT_TWOFRAMES << 4) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_THREEFRAMES (_EUSART_CFG1_RXTIMEOUT_THREEFRAMES << 4) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_FOURFRAMES (_EUSART_CFG1_RXTIMEOUT_FOURFRAMES << 4) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_FIVEFRAMES (_EUSART_CFG1_RXTIMEOUT_FIVEFRAMES << 4) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_SIXFRAMES (_EUSART_CFG1_RXTIMEOUT_SIXFRAMES << 4) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_SEVENFRAMES (_EUSART_CFG1_RXTIMEOUT_SEVENFRAMES << 4) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU (0x1UL << 9) /**< Transmitter DMA Wakeup */ +#define _EUSART_CFG1_TXDMAWU_SHIFT 9 /**< Shift value for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_MASK 0x200UL /**< Bit mask for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU_DEFAULT (_EUSART_CFG1_TXDMAWU_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU (0x1UL << 10) /**< Receiver DMA Wakeup */ +#define _EUSART_CFG1_RXDMAWU_SHIFT 10 /**< Shift value for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_MASK 0x400UL /**< Bit mask for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU_DEFAULT (_EUSART_CFG1_RXDMAWU_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX (0x1UL << 11) /**< Start Frame Unblock Receiver */ +#define _EUSART_CFG1_SFUBRX_SHIFT 11 /**< Shift value for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_MASK 0x800UL /**< Bit mask for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX_DEFAULT (_EUSART_CFG1_SFUBRX_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN (0x1UL << 15) /**< PRS RX Enable */ +#define _EUSART_CFG1_RXPRSEN_SHIFT 15 /**< Shift value for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_MASK 0x8000UL /**< Bit mask for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN_DEFAULT (_EUSART_CFG1_RXPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SHIFT 16 /**< Shift value for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_MASK 0xF0000UL /**< Bit mask for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_DEFAULT (_EUSART_CFG1_TXFIW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_ONEFRAME (_EUSART_CFG1_TXFIW_ONEFRAME << 16) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TWOFRAMES (_EUSART_CFG1_TXFIW_TWOFRAMES << 16) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_THREEFRAMES (_EUSART_CFG1_TXFIW_THREEFRAMES << 16) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FOURFRAMES (_EUSART_CFG1_TXFIW_FOURFRAMES << 16) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FIVEFRAMES (_EUSART_CFG1_TXFIW_FIVEFRAMES << 16) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SIXFRAMES (_EUSART_CFG1_TXFIW_SIXFRAMES << 16) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SEVENFRAMES (_EUSART_CFG1_TXFIW_SEVENFRAMES << 16) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_EIGHTFRAMES (_EUSART_CFG1_TXFIW_EIGHTFRAMES << 16) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_NINEFRAMES (_EUSART_CFG1_TXFIW_NINEFRAMES << 16) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TENFRAMES (_EUSART_CFG1_TXFIW_TENFRAMES << 16) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_ELEVENFRAMES (_EUSART_CFG1_TXFIW_ELEVENFRAMES << 16) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TWELVEFRAMES (_EUSART_CFG1_TXFIW_TWELVEFRAMES << 16) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_THIRTEENFRAMES (_EUSART_CFG1_TXFIW_THIRTEENFRAMES << 16) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FOURTEENFRAMES (_EUSART_CFG1_TXFIW_FOURTEENFRAMES << 16) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FIFTEENFRAMES (_EUSART_CFG1_TXFIW_FIFTEENFRAMES << 16) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SIXTEENFRAMES (_EUSART_CFG1_TXFIW_SIXTEENFRAMES << 16) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SHIFT 22 /**< Shift value for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_MASK 0x3C00000UL /**< Bit mask for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_DEFAULT (_EUSART_CFG1_RTSRXFW_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_ONEFRAME (_EUSART_CFG1_RTSRXFW_ONEFRAME << 22) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TWOFRAMES (_EUSART_CFG1_RTSRXFW_TWOFRAMES << 22) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_THREEFRAMES (_EUSART_CFG1_RTSRXFW_THREEFRAMES << 22) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FOURFRAMES (_EUSART_CFG1_RTSRXFW_FOURFRAMES << 22) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FIVEFRAMES (_EUSART_CFG1_RTSRXFW_FIVEFRAMES << 22) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SIXFRAMES (_EUSART_CFG1_RTSRXFW_SIXFRAMES << 22) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SEVENFRAMES (_EUSART_CFG1_RTSRXFW_SEVENFRAMES << 22) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_EIGHTFRAMES (_EUSART_CFG1_RTSRXFW_EIGHTFRAMES << 22) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_NINEFRAMES (_EUSART_CFG1_RTSRXFW_NINEFRAMES << 22) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TENFRAMES (_EUSART_CFG1_RTSRXFW_TENFRAMES << 22) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_ELEVENFRAMES (_EUSART_CFG1_RTSRXFW_ELEVENFRAMES << 22) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TWELVEFRAMES (_EUSART_CFG1_RTSRXFW_TWELVEFRAMES << 22) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_THIRTEENFRAMES (_EUSART_CFG1_RTSRXFW_THIRTEENFRAMES << 22) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FOURTEENFRAMES (_EUSART_CFG1_RTSRXFW_FOURTEENFRAMES << 22) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FIFTEENFRAMES (_EUSART_CFG1_RTSRXFW_FIFTEENFRAMES << 22) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SIXTEENFRAMES (_EUSART_CFG1_RTSRXFW_SIXTEENFRAMES << 22) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SHIFT 27 /**< Shift value for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_MASK 0x78000000UL /**< Bit mask for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_DEFAULT (_EUSART_CFG1_RXFIW_DEFAULT << 27) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_ONEFRAME (_EUSART_CFG1_RXFIW_ONEFRAME << 27) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TWOFRAMES (_EUSART_CFG1_RXFIW_TWOFRAMES << 27) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_THREEFRAMES (_EUSART_CFG1_RXFIW_THREEFRAMES << 27) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FOURFRAMES (_EUSART_CFG1_RXFIW_FOURFRAMES << 27) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FIVEFRAMES (_EUSART_CFG1_RXFIW_FIVEFRAMES << 27) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SIXFRAMES (_EUSART_CFG1_RXFIW_SIXFRAMES << 27) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SEVENFRAMES (_EUSART_CFG1_RXFIW_SEVENFRAMES << 27) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_EIGHTFRAMES (_EUSART_CFG1_RXFIW_EIGHTFRAMES << 27) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_NINEFRAMES (_EUSART_CFG1_RXFIW_NINEFRAMES << 27) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TENFRAMES (_EUSART_CFG1_RXFIW_TENFRAMES << 27) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_ELEVENFRAMES (_EUSART_CFG1_RXFIW_ELEVENFRAMES << 27) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TWELVEFRAMES (_EUSART_CFG1_RXFIW_TWELVEFRAMES << 27) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_THIRTEENFRAMES (_EUSART_CFG1_RXFIW_THIRTEENFRAMES << 27) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FOURTEENFRAMES (_EUSART_CFG1_RXFIW_FOURTEENFRAMES << 27) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FIFTEENFRAMES (_EUSART_CFG1_RXFIW_FIFTEENFRAMES << 27) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SIXTEENFRAMES (_EUSART_CFG1_RXFIW_SIXTEENFRAMES << 27) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ /* Bit fields for EUSART CFG2 */ -#define _EUSART_CFG2_RESETVALUE 0x00000020UL /**< Default value for EUSART_CFG2 */ -#define _EUSART_CFG2_MASK 0xFF0000FFUL /**< Mask for EUSART_CFG2 */ -#define EUSART_CFG2_MASTER (0x1UL << 0) /**< Main mode */ -#define _EUSART_CFG2_MASTER_SHIFT 0 /**< Shift value for EUSART_MASTER */ -#define _EUSART_CFG2_MASTER_MASK 0x1UL /**< Bit mask for EUSART_MASTER */ -#define _EUSART_CFG2_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define _EUSART_CFG2_MASTER_SLAVE 0x00000000UL /**< Mode SLAVE for EUSART_CFG2 */ -#define _EUSART_CFG2_MASTER_MASTER 0x00000001UL /**< Mode MASTER for EUSART_CFG2 */ -#define EUSART_CFG2_MASTER_DEFAULT (_EUSART_CFG2_MASTER_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_MASTER_SLAVE (_EUSART_CFG2_MASTER_SLAVE << 0) /**< Shifted mode SLAVE for EUSART_CFG2 */ -#define EUSART_CFG2_MASTER_MASTER (_EUSART_CFG2_MASTER_MASTER << 0) /**< Shifted mode MASTER for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPOL (0x1UL << 1) /**< Clock Polarity */ -#define _EUSART_CFG2_CLKPOL_SHIFT 1 /**< Shift value for EUSART_CLKPOL */ -#define _EUSART_CFG2_CLKPOL_MASK 0x2UL /**< Bit mask for EUSART_CLKPOL */ -#define _EUSART_CFG2_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define _EUSART_CFG2_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for EUSART_CFG2 */ -#define _EUSART_CFG2_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPOL_DEFAULT (_EUSART_CFG2_CLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPOL_IDLELOW (_EUSART_CFG2_CLKPOL_IDLELOW << 1) /**< Shifted mode IDLELOW for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPOL_IDLEHIGH (_EUSART_CFG2_CLKPOL_IDLEHIGH << 1) /**< Shifted mode IDLEHIGH for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPHA (0x1UL << 2) /**< Clock Edge for Setup/Sample */ -#define _EUSART_CFG2_CLKPHA_SHIFT 2 /**< Shift value for EUSART_CLKPHA */ -#define _EUSART_CFG2_CLKPHA_MASK 0x4UL /**< Bit mask for EUSART_CLKPHA */ -#define _EUSART_CFG2_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define _EUSART_CFG2_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for EUSART_CFG2 */ -#define _EUSART_CFG2_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPHA_DEFAULT (_EUSART_CFG2_CLKPHA_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPHA_SAMPLELEADING (_EUSART_CFG2_CLKPHA_SAMPLELEADING << 2) /**< Shifted mode SAMPLELEADING for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPHA_SAMPLETRAILING (_EUSART_CFG2_CLKPHA_SAMPLETRAILING << 2) /**< Shifted mode SAMPLETRAILING for EUSART_CFG2 */ -#define EUSART_CFG2_CSINV (0x1UL << 3) /**< Chip Select Invert */ -#define _EUSART_CFG2_CSINV_SHIFT 3 /**< Shift value for EUSART_CSINV */ -#define _EUSART_CFG2_CSINV_MASK 0x8UL /**< Bit mask for EUSART_CSINV */ -#define _EUSART_CFG2_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define _EUSART_CFG2_CSINV_AL 0x00000000UL /**< Mode AL for EUSART_CFG2 */ -#define _EUSART_CFG2_CSINV_AH 0x00000001UL /**< Mode AH for EUSART_CFG2 */ -#define EUSART_CFG2_CSINV_DEFAULT (_EUSART_CFG2_CSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_CSINV_AL (_EUSART_CFG2_CSINV_AL << 3) /**< Shifted mode AL for EUSART_CFG2 */ -#define EUSART_CFG2_CSINV_AH (_EUSART_CFG2_CSINV_AH << 3) /**< Shifted mode AH for EUSART_CFG2 */ -#define EUSART_CFG2_AUTOTX (0x1UL << 4) /**< Always Transmit When RXFIFO Not Full */ -#define _EUSART_CFG2_AUTOTX_SHIFT 4 /**< Shift value for EUSART_AUTOTX */ -#define _EUSART_CFG2_AUTOTX_MASK 0x10UL /**< Bit mask for EUSART_AUTOTX */ -#define _EUSART_CFG2_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_AUTOTX_DEFAULT (_EUSART_CFG2_AUTOTX_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_AUTOCS (0x1UL << 5) /**< Automatic Chip Select */ -#define _EUSART_CFG2_AUTOCS_SHIFT 5 /**< Shift value for EUSART_AUTOCS */ -#define _EUSART_CFG2_AUTOCS_MASK 0x20UL /**< Bit mask for EUSART_AUTOCS */ -#define _EUSART_CFG2_AUTOCS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_AUTOCS_DEFAULT (_EUSART_CFG2_AUTOCS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPRSEN (0x1UL << 6) /**< PRS CLK Enable */ -#define _EUSART_CFG2_CLKPRSEN_SHIFT 6 /**< Shift value for EUSART_CLKPRSEN */ -#define _EUSART_CFG2_CLKPRSEN_MASK 0x40UL /**< Bit mask for EUSART_CLKPRSEN */ -#define _EUSART_CFG2_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPRSEN_DEFAULT (_EUSART_CFG2_CLKPRSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_FORCELOAD (0x1UL << 7) /**< Force Load to Shift Register */ -#define _EUSART_CFG2_FORCELOAD_SHIFT 7 /**< Shift value for EUSART_FORCELOAD */ -#define _EUSART_CFG2_FORCELOAD_MASK 0x80UL /**< Bit mask for EUSART_FORCELOAD */ -#define _EUSART_CFG2_FORCELOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_FORCELOAD_DEFAULT (_EUSART_CFG2_FORCELOAD_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define _EUSART_CFG2_SDIV_SHIFT 24 /**< Shift value for EUSART_SDIV */ -#define _EUSART_CFG2_SDIV_MASK 0xFF000000UL /**< Bit mask for EUSART_SDIV */ -#define _EUSART_CFG2_SDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_SDIV_DEFAULT (_EUSART_CFG2_SDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_RESETVALUE 0x00000020UL /**< Default value for EUSART_CFG2 */ +#define _EUSART_CFG2_MASK 0xFF0000FFUL /**< Mask for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER (0x1UL << 0) /**< Main mode */ +#define _EUSART_CFG2_MASTER_SHIFT 0 /**< Shift value for EUSART_MASTER */ +#define _EUSART_CFG2_MASTER_MASK 0x1UL /**< Bit mask for EUSART_MASTER */ +#define _EUSART_CFG2_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_MASTER_SLAVE 0x00000000UL /**< Mode SLAVE for EUSART_CFG2 */ +#define _EUSART_CFG2_MASTER_MASTER 0x00000001UL /**< Mode MASTER for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_DEFAULT (_EUSART_CFG2_MASTER_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_SLAVE (_EUSART_CFG2_MASTER_SLAVE << 0) /**< Shifted mode SLAVE for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_MASTER (_EUSART_CFG2_MASTER_MASTER << 0) /**< Shifted mode MASTER for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL (0x1UL << 1) /**< Clock Polarity */ +#define _EUSART_CFG2_CLKPOL_SHIFT 1 /**< Shift value for EUSART_CLKPOL */ +#define _EUSART_CFG2_CLKPOL_MASK 0x2UL /**< Bit mask for EUSART_CLKPOL */ +#define _EUSART_CFG2_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_DEFAULT (_EUSART_CFG2_CLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_IDLELOW (_EUSART_CFG2_CLKPOL_IDLELOW << 1) /**< Shifted mode IDLELOW for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_IDLEHIGH (_EUSART_CFG2_CLKPOL_IDLEHIGH << 1) /**< Shifted mode IDLEHIGH for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA (0x1UL << 2) /**< Clock Edge for Setup/Sample */ +#define _EUSART_CFG2_CLKPHA_SHIFT 2 /**< Shift value for EUSART_CLKPHA */ +#define _EUSART_CFG2_CLKPHA_MASK 0x4UL /**< Bit mask for EUSART_CLKPHA */ +#define _EUSART_CFG2_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_DEFAULT (_EUSART_CFG2_CLKPHA_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_SAMPLELEADING (_EUSART_CFG2_CLKPHA_SAMPLELEADING << 2) /**< Shifted mode SAMPLELEADING for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_SAMPLETRAILING (_EUSART_CFG2_CLKPHA_SAMPLETRAILING << 2) /**< Shifted mode SAMPLETRAILING for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV (0x1UL << 3) /**< Chip Select Invert */ +#define _EUSART_CFG2_CSINV_SHIFT 3 /**< Shift value for EUSART_CSINV */ +#define _EUSART_CFG2_CSINV_MASK 0x8UL /**< Bit mask for EUSART_CSINV */ +#define _EUSART_CFG2_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CSINV_AL 0x00000000UL /**< Mode AL for EUSART_CFG2 */ +#define _EUSART_CFG2_CSINV_AH 0x00000001UL /**< Mode AH for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_DEFAULT (_EUSART_CFG2_CSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_AL (_EUSART_CFG2_CSINV_AL << 3) /**< Shifted mode AL for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_AH (_EUSART_CFG2_CSINV_AH << 3) /**< Shifted mode AH for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOTX (0x1UL << 4) /**< Always Transmit When RXFIFO Not Full */ +#define _EUSART_CFG2_AUTOTX_SHIFT 4 /**< Shift value for EUSART_AUTOTX */ +#define _EUSART_CFG2_AUTOTX_MASK 0x10UL /**< Bit mask for EUSART_AUTOTX */ +#define _EUSART_CFG2_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOTX_DEFAULT (_EUSART_CFG2_AUTOTX_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOCS (0x1UL << 5) /**< Automatic Chip Select */ +#define _EUSART_CFG2_AUTOCS_SHIFT 5 /**< Shift value for EUSART_AUTOCS */ +#define _EUSART_CFG2_AUTOCS_MASK 0x20UL /**< Bit mask for EUSART_AUTOCS */ +#define _EUSART_CFG2_AUTOCS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOCS_DEFAULT (_EUSART_CFG2_AUTOCS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPRSEN (0x1UL << 6) /**< PRS CLK Enable */ +#define _EUSART_CFG2_CLKPRSEN_SHIFT 6 /**< Shift value for EUSART_CLKPRSEN */ +#define _EUSART_CFG2_CLKPRSEN_MASK 0x40UL /**< Bit mask for EUSART_CLKPRSEN */ +#define _EUSART_CFG2_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPRSEN_DEFAULT (_EUSART_CFG2_CLKPRSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_FORCELOAD (0x1UL << 7) /**< Force Load to Shift Register */ +#define _EUSART_CFG2_FORCELOAD_SHIFT 7 /**< Shift value for EUSART_FORCELOAD */ +#define _EUSART_CFG2_FORCELOAD_MASK 0x80UL /**< Bit mask for EUSART_FORCELOAD */ +#define _EUSART_CFG2_FORCELOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_FORCELOAD_DEFAULT (_EUSART_CFG2_FORCELOAD_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_SDIV_SHIFT 24 /**< Shift value for EUSART_SDIV */ +#define _EUSART_CFG2_SDIV_MASK 0xFF000000UL /**< Bit mask for EUSART_SDIV */ +#define _EUSART_CFG2_SDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_SDIV_DEFAULT (_EUSART_CFG2_SDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG2 */ /* Bit fields for EUSART FRAMECFG */ -#define _EUSART_FRAMECFG_RESETVALUE 0x00001002UL /**< Default value for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_MASK 0x0000330FUL /**< Mask for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_SHIFT 0 /**< Shift value for EUSART_DATABITS */ -#define _EUSART_FRAMECFG_DATABITS_MASK 0xFUL /**< Bit mask for EUSART_DATABITS */ -#define _EUSART_FRAMECFG_DATABITS_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_SEVEN 0x00000001UL /**< Mode SEVEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_EIGHT 0x00000002UL /**< Mode EIGHT for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_NINE 0x00000003UL /**< Mode NINE for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_TEN 0x00000004UL /**< Mode TEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_ELEVEN 0x00000005UL /**< Mode ELEVEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_TWELVE 0x00000006UL /**< Mode TWELVE for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_THIRTEEN 0x00000007UL /**< Mode THIRTEEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_FOURTEEN 0x00000008UL /**< Mode FOURTEEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_FIFTEEN 0x00000009UL /**< Mode FIFTEEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_SIXTEEN 0x0000000AUL /**< Mode SIXTEEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_DEFAULT (_EUSART_FRAMECFG_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_SEVEN (_EUSART_FRAMECFG_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_EIGHT (_EUSART_FRAMECFG_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_NINE (_EUSART_FRAMECFG_DATABITS_NINE << 0) /**< Shifted mode NINE for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_TEN (_EUSART_FRAMECFG_DATABITS_TEN << 0) /**< Shifted mode TEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_ELEVEN (_EUSART_FRAMECFG_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_TWELVE (_EUSART_FRAMECFG_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_THIRTEEN (_EUSART_FRAMECFG_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_FOURTEEN (_EUSART_FRAMECFG_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_FIFTEEN (_EUSART_FRAMECFG_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_SIXTEEN (_EUSART_FRAMECFG_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_PARITY_SHIFT 8 /**< Shift value for EUSART_PARITY */ -#define _EUSART_FRAMECFG_PARITY_MASK 0x300UL /**< Bit mask for EUSART_PARITY */ -#define _EUSART_FRAMECFG_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_PARITY_NONE 0x00000000UL /**< Mode NONE for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_PARITY_EVEN 0x00000002UL /**< Mode EVEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_PARITY_ODD 0x00000003UL /**< Mode ODD for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_PARITY_DEFAULT (_EUSART_FRAMECFG_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_PARITY_NONE (_EUSART_FRAMECFG_PARITY_NONE << 8) /**< Shifted mode NONE for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_PARITY_EVEN (_EUSART_FRAMECFG_PARITY_EVEN << 8) /**< Shifted mode EVEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_PARITY_ODD (_EUSART_FRAMECFG_PARITY_ODD << 8) /**< Shifted mode ODD for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_SHIFT 12 /**< Shift value for EUSART_STOPBITS */ -#define _EUSART_FRAMECFG_STOPBITS_MASK 0x3000UL /**< Bit mask for EUSART_STOPBITS */ -#define _EUSART_FRAMECFG_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_HALF 0x00000000UL /**< Mode HALF for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_ONE 0x00000001UL /**< Mode ONE for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_TWO 0x00000003UL /**< Mode TWO for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_STOPBITS_DEFAULT (_EUSART_FRAMECFG_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_STOPBITS_HALF (_EUSART_FRAMECFG_STOPBITS_HALF << 12) /**< Shifted mode HALF for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_STOPBITS_ONE (_EUSART_FRAMECFG_STOPBITS_ONE << 12) /**< Shifted mode ONE for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_STOPBITS_ONEANDAHALF (_EUSART_FRAMECFG_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for EUSART_FRAMECFG*/ -#define EUSART_FRAMECFG_STOPBITS_TWO (_EUSART_FRAMECFG_STOPBITS_TWO << 12) /**< Shifted mode TWO for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_RESETVALUE 0x00001002UL /**< Default value for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_MASK 0x0000330FUL /**< Mask for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SHIFT 0 /**< Shift value for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_MASK 0xFUL /**< Bit mask for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SEVEN 0x00000001UL /**< Mode SEVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_EIGHT 0x00000002UL /**< Mode EIGHT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_NINE 0x00000003UL /**< Mode NINE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_TEN 0x00000004UL /**< Mode TEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_ELEVEN 0x00000005UL /**< Mode ELEVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_TWELVE 0x00000006UL /**< Mode TWELVE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_THIRTEEN 0x00000007UL /**< Mode THIRTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_FOURTEEN 0x00000008UL /**< Mode FOURTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_FIFTEEN 0x00000009UL /**< Mode FIFTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SIXTEEN 0x0000000AUL /**< Mode SIXTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_DEFAULT (_EUSART_FRAMECFG_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_SEVEN (_EUSART_FRAMECFG_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_EIGHT (_EUSART_FRAMECFG_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_NINE (_EUSART_FRAMECFG_DATABITS_NINE << 0) /**< Shifted mode NINE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_TEN (_EUSART_FRAMECFG_DATABITS_TEN << 0) /**< Shifted mode TEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_ELEVEN (_EUSART_FRAMECFG_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_TWELVE (_EUSART_FRAMECFG_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_THIRTEEN (_EUSART_FRAMECFG_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_FOURTEEN (_EUSART_FRAMECFG_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_FIFTEEN (_EUSART_FRAMECFG_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_SIXTEEN (_EUSART_FRAMECFG_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_SHIFT 8 /**< Shift value for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_MASK 0x300UL /**< Bit mask for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_NONE 0x00000000UL /**< Mode NONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_EVEN 0x00000002UL /**< Mode EVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_ODD 0x00000003UL /**< Mode ODD for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_DEFAULT (_EUSART_FRAMECFG_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_NONE (_EUSART_FRAMECFG_PARITY_NONE << 8) /**< Shifted mode NONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_EVEN (_EUSART_FRAMECFG_PARITY_EVEN << 8) /**< Shifted mode EVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_ODD (_EUSART_FRAMECFG_PARITY_ODD << 8) /**< Shifted mode ODD for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_SHIFT 12 /**< Shift value for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_MASK 0x3000UL /**< Bit mask for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_HALF 0x00000000UL /**< Mode HALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONE 0x00000001UL /**< Mode ONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_TWO 0x00000003UL /**< Mode TWO for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_DEFAULT (_EUSART_FRAMECFG_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_HALF (_EUSART_FRAMECFG_STOPBITS_HALF << 12) /**< Shifted mode HALF for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONE (_EUSART_FRAMECFG_STOPBITS_ONE << 12) /**< Shifted mode ONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONEANDAHALF (_EUSART_FRAMECFG_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for EUSART_FRAMECFG*/ +#define EUSART_FRAMECFG_STOPBITS_TWO (_EUSART_FRAMECFG_STOPBITS_TWO << 12) /**< Shifted mode TWO for EUSART_FRAMECFG */ /* Bit fields for EUSART DTXDATCFG */ -#define _EUSART_DTXDATCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DTXDATCFG */ -#define _EUSART_DTXDATCFG_MASK 0x0000FFFFUL /**< Mask for EUSART_DTXDATCFG */ -#define _EUSART_DTXDATCFG_DTXDAT_SHIFT 0 /**< Shift value for EUSART_DTXDAT */ -#define _EUSART_DTXDATCFG_DTXDAT_MASK 0xFFFFUL /**< Bit mask for EUSART_DTXDAT */ -#define _EUSART_DTXDATCFG_DTXDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DTXDATCFG */ -#define EUSART_DTXDATCFG_DTXDAT_DEFAULT (_EUSART_DTXDATCFG_DTXDAT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_MASK 0x0000FFFFUL /**< Mask for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_DTXDAT_SHIFT 0 /**< Shift value for EUSART_DTXDAT */ +#define _EUSART_DTXDATCFG_DTXDAT_MASK 0xFFFFUL /**< Bit mask for EUSART_DTXDAT */ +#define _EUSART_DTXDATCFG_DTXDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DTXDATCFG */ +#define EUSART_DTXDATCFG_DTXDAT_DEFAULT (_EUSART_DTXDATCFG_DTXDAT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DTXDATCFG */ /* Bit fields for EUSART IRHFCFG */ -#define _EUSART_IRHFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_MASK 0x0000000FUL /**< Mask for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFEN (0x1UL << 0) /**< Enable IrDA Module */ -#define _EUSART_IRHFCFG_IRHFEN_SHIFT 0 /**< Shift value for EUSART_IRHFEN */ -#define _EUSART_IRHFCFG_IRHFEN_MASK 0x1UL /**< Bit mask for EUSART_IRHFEN */ -#define _EUSART_IRHFCFG_IRHFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFEN_DEFAULT (_EUSART_IRHFCFG_IRHFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_SHIFT 1 /**< Shift value for EUSART_IRHFPW */ -#define _EUSART_IRHFCFG_IRHFPW_MASK 0x6UL /**< Bit mask for EUSART_IRHFPW */ -#define _EUSART_IRHFCFG_IRHFPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_ONE 0x00000000UL /**< Mode ONE for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_TWO 0x00000001UL /**< Mode TWO for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_THREE 0x00000002UL /**< Mode THREE for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_FOUR 0x00000003UL /**< Mode FOUR for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_DEFAULT (_EUSART_IRHFCFG_IRHFPW_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_ONE (_EUSART_IRHFCFG_IRHFPW_ONE << 1) /**< Shifted mode ONE for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_TWO (_EUSART_IRHFCFG_IRHFPW_TWO << 1) /**< Shifted mode TWO for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_THREE (_EUSART_IRHFCFG_IRHFPW_THREE << 1) /**< Shifted mode THREE for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_FOUR (_EUSART_IRHFCFG_IRHFPW_FOUR << 1) /**< Shifted mode FOUR for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFFILT (0x1UL << 3) /**< IrDA RX Filter */ -#define _EUSART_IRHFCFG_IRHFFILT_SHIFT 3 /**< Shift value for EUSART_IRHFFILT */ -#define _EUSART_IRHFCFG_IRHFFILT_MASK 0x8UL /**< Bit mask for EUSART_IRHFFILT */ -#define _EUSART_IRHFCFG_IRHFFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFFILT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFFILT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFFILT_DEFAULT (_EUSART_IRHFCFG_IRHFFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFFILT_DISABLE (_EUSART_IRHFCFG_IRHFFILT_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFFILT_ENABLE (_EUSART_IRHFCFG_IRHFFILT_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_MASK 0x0000000FUL /**< Mask for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN (0x1UL << 0) /**< Enable IrDA Module */ +#define _EUSART_IRHFCFG_IRHFEN_SHIFT 0 /**< Shift value for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_MASK 0x1UL /**< Bit mask for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN_DEFAULT (_EUSART_IRHFCFG_IRHFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_SHIFT 1 /**< Shift value for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_MASK 0x6UL /**< Bit mask for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_ONE 0x00000000UL /**< Mode ONE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_TWO 0x00000001UL /**< Mode TWO for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_THREE 0x00000002UL /**< Mode THREE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_FOUR 0x00000003UL /**< Mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_DEFAULT (_EUSART_IRHFCFG_IRHFPW_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_ONE (_EUSART_IRHFCFG_IRHFPW_ONE << 1) /**< Shifted mode ONE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_TWO (_EUSART_IRHFCFG_IRHFPW_TWO << 1) /**< Shifted mode TWO for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_THREE (_EUSART_IRHFCFG_IRHFPW_THREE << 1) /**< Shifted mode THREE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_FOUR (_EUSART_IRHFCFG_IRHFPW_FOUR << 1) /**< Shifted mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _EUSART_IRHFCFG_IRHFFILT_SHIFT 3 /**< Shift value for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_MASK 0x8UL /**< Bit mask for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DEFAULT (_EUSART_IRHFCFG_IRHFFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DISABLE (_EUSART_IRHFCFG_IRHFFILT_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_ENABLE (_EUSART_IRHFCFG_IRHFFILT_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_IRHFCFG */ /* Bit fields for EUSART IRLFCFG */ -#define _EUSART_IRLFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRLFCFG */ -#define _EUSART_IRLFCFG_MASK 0x00000001UL /**< Mask for EUSART_IRLFCFG */ -#define EUSART_IRLFCFG_IRLFEN (0x1UL << 0) /**< Pulse Generator/Extender Enable */ -#define _EUSART_IRLFCFG_IRLFEN_SHIFT 0 /**< Shift value for EUSART_IRLFEN */ -#define _EUSART_IRLFCFG_IRLFEN_MASK 0x1UL /**< Bit mask for EUSART_IRLFEN */ -#define _EUSART_IRLFCFG_IRLFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRLFCFG */ -#define EUSART_IRLFCFG_IRLFEN_DEFAULT (_EUSART_IRLFCFG_IRLFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRLFCFG */ +#define _EUSART_IRLFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRLFCFG */ +#define _EUSART_IRLFCFG_MASK 0x00000001UL /**< Mask for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN (0x1UL << 0) /**< Pulse Generator/Extender Enable */ +#define _EUSART_IRLFCFG_IRLFEN_SHIFT 0 /**< Shift value for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_MASK 0x1UL /**< Bit mask for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN_DEFAULT (_EUSART_IRLFCFG_IRLFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRLFCFG */ /* Bit fields for EUSART TIMINGCFG */ -#define _EUSART_TIMINGCFG_RESETVALUE 0x00050000UL /**< Default value for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_MASK 0x000F7773UL /**< Mask for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_SHIFT 0 /**< Shift value for EUSART_TXDELAY */ -#define _EUSART_TIMINGCFG_TXDELAY_MASK 0x3UL /**< Bit mask for EUSART_TXDELAY */ -#define _EUSART_TIMINGCFG_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_NONE 0x00000000UL /**< Mode NONE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_TRIPPLE 0x00000003UL /**< Mode TRIPPLE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_DEFAULT (_EUSART_TIMINGCFG_TXDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_NONE (_EUSART_TIMINGCFG_TXDELAY_NONE << 0) /**< Shifted mode NONE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_SINGLE (_EUSART_TIMINGCFG_TXDELAY_SINGLE << 0) /**< Shifted mode SINGLE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_DOUBLE (_EUSART_TIMINGCFG_TXDELAY_DOUBLE << 0) /**< Shifted mode DOUBLE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_TRIPPLE (_EUSART_TIMINGCFG_TXDELAY_TRIPPLE << 0) /**< Shifted mode TRIPPLE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_SHIFT 4 /**< Shift value for EUSART_CSSETUP */ -#define _EUSART_TIMINGCFG_CSSETUP_MASK 0x70UL /**< Bit mask for EUSART_CSSETUP */ -#define _EUSART_TIMINGCFG_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_DEFAULT (_EUSART_TIMINGCFG_CSSETUP_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_ZERO (_EUSART_TIMINGCFG_CSSETUP_ZERO << 4) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_ONE (_EUSART_TIMINGCFG_CSSETUP_ONE << 4) /**< Shifted mode ONE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_TWO (_EUSART_TIMINGCFG_CSSETUP_TWO << 4) /**< Shifted mode TWO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_THREE (_EUSART_TIMINGCFG_CSSETUP_THREE << 4) /**< Shifted mode THREE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_FOUR (_EUSART_TIMINGCFG_CSSETUP_FOUR << 4) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_FIVE (_EUSART_TIMINGCFG_CSSETUP_FIVE << 4) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_SIX (_EUSART_TIMINGCFG_CSSETUP_SIX << 4) /**< Shifted mode SIX for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_SEVEN (_EUSART_TIMINGCFG_CSSETUP_SEVEN << 4) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_SHIFT 8 /**< Shift value for EUSART_CSHOLD */ -#define _EUSART_TIMINGCFG_CSHOLD_MASK 0x700UL /**< Bit mask for EUSART_CSHOLD */ -#define _EUSART_TIMINGCFG_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_DEFAULT (_EUSART_TIMINGCFG_CSHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_ZERO (_EUSART_TIMINGCFG_CSHOLD_ZERO << 8) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_ONE (_EUSART_TIMINGCFG_CSHOLD_ONE << 8) /**< Shifted mode ONE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_TWO (_EUSART_TIMINGCFG_CSHOLD_TWO << 8) /**< Shifted mode TWO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_THREE (_EUSART_TIMINGCFG_CSHOLD_THREE << 8) /**< Shifted mode THREE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_FOUR (_EUSART_TIMINGCFG_CSHOLD_FOUR << 8) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_FIVE (_EUSART_TIMINGCFG_CSHOLD_FIVE << 8) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_SIX (_EUSART_TIMINGCFG_CSHOLD_SIX << 8) /**< Shifted mode SIX for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_SEVEN (_EUSART_TIMINGCFG_CSHOLD_SEVEN << 8) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_SHIFT 12 /**< Shift value for EUSART_ICS */ -#define _EUSART_TIMINGCFG_ICS_MASK 0x7000UL /**< Bit mask for EUSART_ICS */ -#define _EUSART_TIMINGCFG_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_DEFAULT (_EUSART_TIMINGCFG_ICS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_ZERO (_EUSART_TIMINGCFG_ICS_ZERO << 12) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_ONE (_EUSART_TIMINGCFG_ICS_ONE << 12) /**< Shifted mode ONE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_TWO (_EUSART_TIMINGCFG_ICS_TWO << 12) /**< Shifted mode TWO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_THREE (_EUSART_TIMINGCFG_ICS_THREE << 12) /**< Shifted mode THREE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_FOUR (_EUSART_TIMINGCFG_ICS_FOUR << 12) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_FIVE (_EUSART_TIMINGCFG_ICS_FIVE << 12) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_SIX (_EUSART_TIMINGCFG_ICS_SIX << 12) /**< Shifted mode SIX for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_SEVEN (_EUSART_TIMINGCFG_ICS_SEVEN << 12) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT 16 /**< Shift value for EUSART_SETUPWINDOW */ -#define _EUSART_TIMINGCFG_SETUPWINDOW_MASK 0xF0000UL /**< Bit mask for EUSART_SETUPWINDOW */ -#define _EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT 0x00000005UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT (_EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_RESETVALUE 0x00050000UL /**< Default value for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_MASK 0x000F7773UL /**< Mask for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SHIFT 0 /**< Shift value for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_MASK 0x3UL /**< Bit mask for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_NONE 0x00000000UL /**< Mode NONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_TRIPPLE 0x00000003UL /**< Mode TRIPPLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DEFAULT (_EUSART_TIMINGCFG_TXDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_NONE (_EUSART_TIMINGCFG_TXDELAY_NONE << 0) /**< Shifted mode NONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_SINGLE (_EUSART_TIMINGCFG_TXDELAY_SINGLE << 0) /**< Shifted mode SINGLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DOUBLE (_EUSART_TIMINGCFG_TXDELAY_DOUBLE << 0) /**< Shifted mode DOUBLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_TRIPPLE (_EUSART_TIMINGCFG_TXDELAY_TRIPPLE << 0) /**< Shifted mode TRIPPLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SHIFT 4 /**< Shift value for EUSART_CSSETUP */ +#define _EUSART_TIMINGCFG_CSSETUP_MASK 0x70UL /**< Bit mask for EUSART_CSSETUP */ +#define _EUSART_TIMINGCFG_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_DEFAULT (_EUSART_TIMINGCFG_CSSETUP_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_ZERO (_EUSART_TIMINGCFG_CSSETUP_ZERO << 4) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_ONE (_EUSART_TIMINGCFG_CSSETUP_ONE << 4) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_TWO (_EUSART_TIMINGCFG_CSSETUP_TWO << 4) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_THREE (_EUSART_TIMINGCFG_CSSETUP_THREE << 4) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_FOUR (_EUSART_TIMINGCFG_CSSETUP_FOUR << 4) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_FIVE (_EUSART_TIMINGCFG_CSSETUP_FIVE << 4) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_SIX (_EUSART_TIMINGCFG_CSSETUP_SIX << 4) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_SEVEN (_EUSART_TIMINGCFG_CSSETUP_SEVEN << 4) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SHIFT 8 /**< Shift value for EUSART_CSHOLD */ +#define _EUSART_TIMINGCFG_CSHOLD_MASK 0x700UL /**< Bit mask for EUSART_CSHOLD */ +#define _EUSART_TIMINGCFG_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_DEFAULT (_EUSART_TIMINGCFG_CSHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_ZERO (_EUSART_TIMINGCFG_CSHOLD_ZERO << 8) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_ONE (_EUSART_TIMINGCFG_CSHOLD_ONE << 8) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_TWO (_EUSART_TIMINGCFG_CSHOLD_TWO << 8) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_THREE (_EUSART_TIMINGCFG_CSHOLD_THREE << 8) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_FOUR (_EUSART_TIMINGCFG_CSHOLD_FOUR << 8) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_FIVE (_EUSART_TIMINGCFG_CSHOLD_FIVE << 8) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_SIX (_EUSART_TIMINGCFG_CSHOLD_SIX << 8) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_SEVEN (_EUSART_TIMINGCFG_CSHOLD_SEVEN << 8) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SHIFT 12 /**< Shift value for EUSART_ICS */ +#define _EUSART_TIMINGCFG_ICS_MASK 0x7000UL /**< Bit mask for EUSART_ICS */ +#define _EUSART_TIMINGCFG_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_DEFAULT (_EUSART_TIMINGCFG_ICS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_ZERO (_EUSART_TIMINGCFG_ICS_ZERO << 12) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_ONE (_EUSART_TIMINGCFG_ICS_ONE << 12) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_TWO (_EUSART_TIMINGCFG_ICS_TWO << 12) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_THREE (_EUSART_TIMINGCFG_ICS_THREE << 12) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_FOUR (_EUSART_TIMINGCFG_ICS_FOUR << 12) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_FIVE (_EUSART_TIMINGCFG_ICS_FIVE << 12) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_SIX (_EUSART_TIMINGCFG_ICS_SIX << 12) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_SEVEN (_EUSART_TIMINGCFG_ICS_SEVEN << 12) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT 16 /**< Shift value for EUSART_SETUPWINDOW */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_MASK 0xF0000UL /**< Bit mask for EUSART_SETUPWINDOW */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT 0x00000005UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT (_EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ /* Bit fields for EUSART STARTFRAMECFG */ -#define _EUSART_STARTFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_STARTFRAMECFG */ -#define _EUSART_STARTFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_STARTFRAMECFG */ -#define _EUSART_STARTFRAMECFG_STARTFRAME_SHIFT 0 /**< Shift value for EUSART_STARTFRAME */ -#define _EUSART_STARTFRAMECFG_STARTFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_STARTFRAME */ -#define _EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STARTFRAMECFG */ -#define EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT (_EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STARTFRAMECFG*/ +#define _EUSART_STARTFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_SHIFT 0 /**< Shift value for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STARTFRAMECFG */ +#define EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT (_EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STARTFRAMECFG*/ /* Bit fields for EUSART SIGFRAMECFG */ -#define _EUSART_SIGFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_SIGFRAMECFG */ -#define _EUSART_SIGFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_SIGFRAMECFG */ -#define _EUSART_SIGFRAMECFG_SIGFRAME_SHIFT 0 /**< Shift value for EUSART_SIGFRAME */ -#define _EUSART_SIGFRAMECFG_SIGFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_SIGFRAME */ -#define _EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SIGFRAMECFG */ -#define EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT (_EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_SHIFT 0 /**< Shift value for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SIGFRAMECFG */ +#define EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT (_EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SIGFRAMECFG */ /* Bit fields for EUSART CLKDIV */ -#define _EUSART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for EUSART_CLKDIV */ -#define _EUSART_CLKDIV_MASK 0x007FFFF8UL /**< Mask for EUSART_CLKDIV */ -#define _EUSART_CLKDIV_DIV_SHIFT 3 /**< Shift value for EUSART_DIV */ -#define _EUSART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for EUSART_DIV */ -#define _EUSART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CLKDIV */ -#define EUSART_CLKDIV_DIV_DEFAULT (_EUSART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_MASK 0x007FFFF8UL /**< Mask for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_DIV_SHIFT 3 /**< Shift value for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CLKDIV */ +#define EUSART_CLKDIV_DIV_DEFAULT (_EUSART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CLKDIV */ /* Bit fields for EUSART TRIGCTRL */ -#define _EUSART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for EUSART_TRIGCTRL */ -#define _EUSART_TRIGCTRL_MASK 0x00000007UL /**< Mask for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_RXTEN (0x1UL << 0) /**< Receive Trigger Enable */ -#define _EUSART_TRIGCTRL_RXTEN_SHIFT 0 /**< Shift value for EUSART_RXTEN */ -#define _EUSART_TRIGCTRL_RXTEN_MASK 0x1UL /**< Bit mask for EUSART_RXTEN */ -#define _EUSART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_RXTEN_DEFAULT (_EUSART_TRIGCTRL_RXTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_TXTEN (0x1UL << 1) /**< Transmit Trigger Enable */ -#define _EUSART_TRIGCTRL_TXTEN_SHIFT 1 /**< Shift value for EUSART_TXTEN */ -#define _EUSART_TRIGCTRL_TXTEN_MASK 0x2UL /**< Bit mask for EUSART_TXTEN */ -#define _EUSART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_TXTEN_DEFAULT (_EUSART_TRIGCTRL_TXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_AUTOTXTEN (0x1UL << 2) /**< AUTOTX Trigger Enable */ -#define _EUSART_TRIGCTRL_AUTOTXTEN_SHIFT 2 /**< Shift value for EUSART_AUTOTXTEN */ -#define _EUSART_TRIGCTRL_AUTOTXTEN_MASK 0x4UL /**< Bit mask for EUSART_AUTOTXTEN */ -#define _EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT (_EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define _EUSART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for EUSART_TRIGCTRL */ +#define _EUSART_TRIGCTRL_MASK 0x00000007UL /**< Mask for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN (0x1UL << 0) /**< Receive Trigger Enable */ +#define _EUSART_TRIGCTRL_RXTEN_SHIFT 0 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_MASK 0x1UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN_DEFAULT (_EUSART_TRIGCTRL_RXTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN (0x1UL << 1) /**< Transmit Trigger Enable */ +#define _EUSART_TRIGCTRL_TXTEN_SHIFT 1 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_MASK 0x2UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN_DEFAULT (_EUSART_TRIGCTRL_TXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_AUTOTXTEN (0x1UL << 2) /**< AUTOTX Trigger Enable */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_SHIFT 2 /**< Shift value for EUSART_AUTOTXTEN */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_MASK 0x4UL /**< Bit mask for EUSART_AUTOTXTEN */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT (_EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ /* Bit fields for EUSART CMD */ -#define _EUSART_CMD_RESETVALUE 0x00000000UL /**< Default value for EUSART_CMD */ -#define _EUSART_CMD_MASK 0x000001FFUL /**< Mask for EUSART_CMD */ -#define EUSART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ -#define _EUSART_CMD_RXEN_SHIFT 0 /**< Shift value for EUSART_RXEN */ -#define _EUSART_CMD_RXEN_MASK 0x1UL /**< Bit mask for EUSART_RXEN */ -#define _EUSART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXEN_DEFAULT (_EUSART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ -#define _EUSART_CMD_RXDIS_SHIFT 1 /**< Shift value for EUSART_RXDIS */ -#define _EUSART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for EUSART_RXDIS */ -#define _EUSART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXDIS_DEFAULT (_EUSART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ -#define _EUSART_CMD_TXEN_SHIFT 2 /**< Shift value for EUSART_TXEN */ -#define _EUSART_CMD_TXEN_MASK 0x4UL /**< Bit mask for EUSART_TXEN */ -#define _EUSART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXEN_DEFAULT (_EUSART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ -#define _EUSART_CMD_TXDIS_SHIFT 3 /**< Shift value for EUSART_TXDIS */ -#define _EUSART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for EUSART_TXDIS */ -#define _EUSART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXDIS_DEFAULT (_EUSART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ -#define _EUSART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for EUSART_RXBLOCKEN */ -#define _EUSART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for EUSART_RXBLOCKEN */ -#define _EUSART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXBLOCKEN_DEFAULT (_EUSART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ -#define _EUSART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for EUSART_RXBLOCKDIS */ -#define _EUSART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for EUSART_RXBLOCKDIS */ -#define _EUSART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXBLOCKDIS_DEFAULT (_EUSART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXTRIEN (0x1UL << 6) /**< Transmitter Tristate Enable */ -#define _EUSART_CMD_TXTRIEN_SHIFT 6 /**< Shift value for EUSART_TXTRIEN */ -#define _EUSART_CMD_TXTRIEN_MASK 0x40UL /**< Bit mask for EUSART_TXTRIEN */ -#define _EUSART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXTRIEN_DEFAULT (_EUSART_CMD_TXTRIEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXTRIDIS (0x1UL << 7) /**< Transmitter Tristate Disable */ -#define _EUSART_CMD_TXTRIDIS_SHIFT 7 /**< Shift value for EUSART_TXTRIDIS */ -#define _EUSART_CMD_TXTRIDIS_MASK 0x80UL /**< Bit mask for EUSART_TXTRIDIS */ -#define _EUSART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXTRIDIS_DEFAULT (_EUSART_CMD_TXTRIDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_CLEARTX (0x1UL << 8) /**< Clear TX FIFO */ -#define _EUSART_CMD_CLEARTX_SHIFT 8 /**< Shift value for EUSART_CLEARTX */ -#define _EUSART_CMD_CLEARTX_MASK 0x100UL /**< Bit mask for EUSART_CLEARTX */ -#define _EUSART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_CLEARTX_DEFAULT (_EUSART_CMD_CLEARTX_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define _EUSART_CMD_RESETVALUE 0x00000000UL /**< Default value for EUSART_CMD */ +#define _EUSART_CMD_MASK 0x000001FFUL /**< Mask for EUSART_CMD */ +#define EUSART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _EUSART_CMD_RXEN_SHIFT 0 /**< Shift value for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_MASK 0x1UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXEN_DEFAULT (_EUSART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _EUSART_CMD_RXDIS_SHIFT 1 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS_DEFAULT (_EUSART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _EUSART_CMD_TXEN_SHIFT 2 /**< Shift value for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_MASK 0x4UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN_DEFAULT (_EUSART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _EUSART_CMD_TXDIS_SHIFT 3 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS_DEFAULT (_EUSART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ +#define _EUSART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN_DEFAULT (_EUSART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ +#define _EUSART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS_DEFAULT (_EUSART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN (0x1UL << 6) /**< Transmitter Tristate Enable */ +#define _EUSART_CMD_TXTRIEN_SHIFT 6 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_MASK 0x40UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN_DEFAULT (_EUSART_CMD_TXTRIEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS (0x1UL << 7) /**< Transmitter Tristate Disable */ +#define _EUSART_CMD_TXTRIDIS_SHIFT 7 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_MASK 0x80UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS_DEFAULT (_EUSART_CMD_TXTRIDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX (0x1UL << 8) /**< Clear TX FIFO */ +#define _EUSART_CMD_CLEARTX_SHIFT 8 /**< Shift value for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_MASK 0x100UL /**< Bit mask for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX_DEFAULT (_EUSART_CMD_CLEARTX_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_CMD */ /* Bit fields for EUSART RXDATA */ -#define _EUSART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATA */ -#define _EUSART_RXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATA */ -#define _EUSART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for EUSART_RXDATA */ -#define _EUSART_RXDATA_RXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATA */ -#define _EUSART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ -#define EUSART_RXDATA_RXDATA_DEFAULT (_EUSART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATA */ +#define _EUSART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATA */ +#define _EUSART_RXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ +#define EUSART_RXDATA_RXDATA_DEFAULT (_EUSART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATA */ /* Bit fields for EUSART RXDATAP */ -#define _EUSART_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATAP */ -#define _EUSART_RXDATAP_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATAP */ -#define _EUSART_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for EUSART_RXDATAP */ -#define _EUSART_RXDATAP_RXDATAP_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATAP */ -#define _EUSART_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ -#define EUSART_RXDATAP_RXDATAP_DEFAULT (_EUSART_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ +#define EUSART_RXDATAP_RXDATAP_DEFAULT (_EUSART_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ /* Bit fields for EUSART TXDATA */ -#define _EUSART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_TXDATA */ -#define _EUSART_TXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_TXDATA */ -#define _EUSART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for EUSART_TXDATA */ -#define _EUSART_TXDATA_TXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_TXDATA */ -#define _EUSART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ -#define EUSART_TXDATA_TXDATA_DEFAULT (_EUSART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TXDATA */ +#define _EUSART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_TXDATA */ +#define _EUSART_TXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_TXDATA_DEFAULT (_EUSART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TXDATA */ /* Bit fields for EUSART STATUS */ -#define _EUSART_STATUS_RESETVALUE 0x00003040UL /**< Default value for EUSART_STATUS */ -#define _EUSART_STATUS_MASK 0x031F31FBUL /**< Mask for EUSART_STATUS */ -#define EUSART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ -#define _EUSART_STATUS_RXENS_SHIFT 0 /**< Shift value for EUSART_RXENS */ -#define _EUSART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for EUSART_RXENS */ -#define _EUSART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXENS_DEFAULT (_EUSART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ -#define _EUSART_STATUS_TXENS_SHIFT 1 /**< Shift value for EUSART_TXENS */ -#define _EUSART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for EUSART_TXENS */ -#define _EUSART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXENS_DEFAULT (_EUSART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ -#define _EUSART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for EUSART_RXBLOCK */ -#define _EUSART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for EUSART_RXBLOCK */ -#define _EUSART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXBLOCK_DEFAULT (_EUSART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ -#define _EUSART_STATUS_TXTRI_SHIFT 4 /**< Shift value for EUSART_TXTRI */ -#define _EUSART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for EUSART_TXTRI */ -#define _EUSART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXTRI_DEFAULT (_EUSART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ -#define _EUSART_STATUS_TXC_SHIFT 5 /**< Shift value for EUSART_TXC */ -#define _EUSART_STATUS_TXC_MASK 0x20UL /**< Bit mask for EUSART_TXC */ -#define _EUSART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXC_DEFAULT (_EUSART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXFL (0x1UL << 6) /**< TX FIFO Level */ -#define _EUSART_STATUS_TXFL_SHIFT 6 /**< Shift value for EUSART_TXFL */ -#define _EUSART_STATUS_TXFL_MASK 0x40UL /**< Bit mask for EUSART_TXFL */ -#define _EUSART_STATUS_TXFL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXFL_DEFAULT (_EUSART_STATUS_TXFL_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXFL (0x1UL << 7) /**< RX FIFO Level */ -#define _EUSART_STATUS_RXFL_SHIFT 7 /**< Shift value for EUSART_RXFL */ -#define _EUSART_STATUS_RXFL_MASK 0x80UL /**< Bit mask for EUSART_RXFL */ -#define _EUSART_STATUS_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXFL_DEFAULT (_EUSART_STATUS_RXFL_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ -#define _EUSART_STATUS_RXFULL_SHIFT 8 /**< Shift value for EUSART_RXFULL */ -#define _EUSART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for EUSART_RXFULL */ -#define _EUSART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXFULL_DEFAULT (_EUSART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXIDLE (0x1UL << 12) /**< RX Idle */ -#define _EUSART_STATUS_RXIDLE_SHIFT 12 /**< Shift value for EUSART_RXIDLE */ -#define _EUSART_STATUS_RXIDLE_MASK 0x1000UL /**< Bit mask for EUSART_RXIDLE */ -#define _EUSART_STATUS_RXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXIDLE_DEFAULT (_EUSART_STATUS_RXIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ -#define _EUSART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ -#define _EUSART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ -#define _EUSART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXIDLE_DEFAULT (_EUSART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define _EUSART_STATUS_TXFCNT_SHIFT 16 /**< Shift value for EUSART_TXFCNT */ -#define _EUSART_STATUS_TXFCNT_MASK 0x1F0000UL /**< Bit mask for EUSART_TXFCNT */ -#define _EUSART_STATUS_TXFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXFCNT_DEFAULT (_EUSART_STATUS_TXFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Rate Detection Completed */ -#define _EUSART_STATUS_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ -#define _EUSART_STATUS_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ -#define _EUSART_STATUS_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_AUTOBAUDDONE_DEFAULT (_EUSART_STATUS_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_CLEARTXBUSY (0x1UL << 25) /**< TX FIFO Clear Busy */ -#define _EUSART_STATUS_CLEARTXBUSY_SHIFT 25 /**< Shift value for EUSART_CLEARTXBUSY */ -#define _EUSART_STATUS_CLEARTXBUSY_MASK 0x2000000UL /**< Bit mask for EUSART_CLEARTXBUSY */ -#define _EUSART_STATUS_CLEARTXBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_CLEARTXBUSY_DEFAULT (_EUSART_STATUS_CLEARTXBUSY_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define _EUSART_STATUS_RESETVALUE 0x00003040UL /**< Default value for EUSART_STATUS */ +#define _EUSART_STATUS_MASK 0x031F31FBUL /**< Mask for EUSART_STATUS */ +#define EUSART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _EUSART_STATUS_RXENS_SHIFT 0 /**< Shift value for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXENS_DEFAULT (_EUSART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _EUSART_STATUS_TXENS_SHIFT 1 /**< Shift value for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS_DEFAULT (_EUSART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _EUSART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK_DEFAULT (_EUSART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _EUSART_STATUS_TXTRI_SHIFT 4 /**< Shift value for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI_DEFAULT (_EUSART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _EUSART_STATUS_TXC_SHIFT 5 /**< Shift value for EUSART_TXC */ +#define _EUSART_STATUS_TXC_MASK 0x20UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC_DEFAULT (_EUSART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL (0x1UL << 6) /**< TX FIFO Level */ +#define _EUSART_STATUS_TXFL_SHIFT 6 /**< Shift value for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_MASK 0x40UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL_DEFAULT (_EUSART_STATUS_TXFL_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL (0x1UL << 7) /**< RX FIFO Level */ +#define _EUSART_STATUS_RXFL_SHIFT 7 /**< Shift value for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_MASK 0x80UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL_DEFAULT (_EUSART_STATUS_RXFL_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _EUSART_STATUS_RXFULL_SHIFT 8 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL_DEFAULT (_EUSART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE (0x1UL << 12) /**< RX Idle */ +#define _EUSART_STATUS_RXIDLE_SHIFT 12 /**< Shift value for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_MASK 0x1000UL /**< Bit mask for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE_DEFAULT (_EUSART_STATUS_RXIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _EUSART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE_DEFAULT (_EUSART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define _EUSART_STATUS_TXFCNT_SHIFT 16 /**< Shift value for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_MASK 0x1F0000UL /**< Bit mask for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFCNT_DEFAULT (_EUSART_STATUS_TXFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Rate Detection Completed */ +#define _EUSART_STATUS_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE_DEFAULT (_EUSART_STATUS_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY (0x1UL << 25) /**< TX FIFO Clear Busy */ +#define _EUSART_STATUS_CLEARTXBUSY_SHIFT 25 /**< Shift value for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_MASK 0x2000000UL /**< Bit mask for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY_DEFAULT (_EUSART_STATUS_CLEARTXBUSY_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_STATUS */ /* Bit fields for EUSART IF */ -#define _EUSART_IF_RESETVALUE 0x00000000UL /**< Default value for EUSART_IF */ -#define _EUSART_IF_MASK 0x030D3FFFUL /**< Mask for EUSART_IF */ -#define EUSART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ -#define _EUSART_IF_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ -#define _EUSART_IF_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ -#define _EUSART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXC_DEFAULT (_EUSART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXFL (0x1UL << 1) /**< TX FIFO Level Interrupt Flag */ -#define _EUSART_IF_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ -#define _EUSART_IF_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ -#define _EUSART_IF_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXFL_DEFAULT (_EUSART_IF_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXFL (0x1UL << 2) /**< RX FIFO Level Interrupt Flag */ -#define _EUSART_IF_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ -#define _EUSART_IF_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ -#define _EUSART_IF_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXFL_DEFAULT (_EUSART_IF_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXFULL (0x1UL << 3) /**< RX FIFO Full Interrupt Flag */ -#define _EUSART_IF_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ -#define _EUSART_IF_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ -#define _EUSART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXFULL_DEFAULT (_EUSART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXOF (0x1UL << 4) /**< RX FIFO Overflow Interrupt Flag */ -#define _EUSART_IF_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ -#define _EUSART_IF_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ -#define _EUSART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXOF_DEFAULT (_EUSART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXUF (0x1UL << 5) /**< RX FIFO Underflow Interrupt Flag */ -#define _EUSART_IF_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ -#define _EUSART_IF_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ -#define _EUSART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXUF_DEFAULT (_EUSART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXOF (0x1UL << 6) /**< TX FIFO Overflow Interrupt Flag */ -#define _EUSART_IF_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ -#define _EUSART_IF_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ -#define _EUSART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXOF_DEFAULT (_EUSART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXUF (0x1UL << 7) /**< TX FIFO Underflow Interrupt Flag */ -#define _EUSART_IF_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ -#define _EUSART_IF_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ -#define _EUSART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXUF_DEFAULT (_EUSART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ -#define _EUSART_IF_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ -#define _EUSART_IF_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ -#define _EUSART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_PERR_DEFAULT (_EUSART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ -#define _EUSART_IF_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ -#define _EUSART_IF_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ -#define _EUSART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_FERR_DEFAULT (_EUSART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ -#define _EUSART_IF_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ -#define _EUSART_IF_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ -#define _EUSART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_MPAF_DEFAULT (_EUSART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_LOADERR (0x1UL << 11) /**< Load Error Interrupt Flag */ -#define _EUSART_IF_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ -#define _EUSART_IF_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ -#define _EUSART_IF_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_LOADERR_DEFAULT (_EUSART_IF_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ -#define _EUSART_IF_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ -#define _EUSART_IF_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ -#define _EUSART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_CCF_DEFAULT (_EUSART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ -#define _EUSART_IF_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ -#define _EUSART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ -#define _EUSART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXIDLE_DEFAULT (_EUSART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_CSWU (0x1UL << 16) /**< CS Wake-up Interrupt Flag */ -#define _EUSART_IF_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ -#define _EUSART_IF_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ -#define _EUSART_IF_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_CSWU_DEFAULT (_EUSART_IF_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_STARTF (0x1UL << 18) /**< Start Frame Interrupt Flag */ -#define _EUSART_IF_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ -#define _EUSART_IF_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ -#define _EUSART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_STARTF_DEFAULT (_EUSART_IF_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_SIGF (0x1UL << 19) /**< Signal Frame Interrupt Flag */ -#define _EUSART_IF_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ -#define _EUSART_IF_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ -#define _EUSART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_SIGF_DEFAULT (_EUSART_IF_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Interrupt Flag */ -#define _EUSART_IF_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ -#define _EUSART_IF_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ -#define _EUSART_IF_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_AUTOBAUDDONE_DEFAULT (_EUSART_IF_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXTO (0x1UL << 25) /**< RX Timeout Interrupt Flag */ -#define _EUSART_IF_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ -#define _EUSART_IF_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ -#define _EUSART_IF_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXTO_DEFAULT (_EUSART_IF_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IF */ +#define _EUSART_IF_RESETVALUE 0x00000000UL /**< Default value for EUSART_IF */ +#define _EUSART_IF_MASK 0x030D3FFFUL /**< Mask for EUSART_IF */ +#define EUSART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _EUSART_IF_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IF_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXC_DEFAULT (_EUSART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL (0x1UL << 1) /**< TX FIFO Level Interrupt Flag */ +#define _EUSART_IF_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IF_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IF_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL_DEFAULT (_EUSART_IF_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL (0x1UL << 2) /**< RX FIFO Level Interrupt Flag */ +#define _EUSART_IF_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IF_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IF_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL_DEFAULT (_EUSART_IF_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL (0x1UL << 3) /**< RX FIFO Full Interrupt Flag */ +#define _EUSART_IF_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL_DEFAULT (_EUSART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF (0x1UL << 4) /**< RX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IF_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF_DEFAULT (_EUSART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF (0x1UL << 5) /**< RX FIFO Underflow Interrupt Flag */ +#define _EUSART_IF_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IF_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF_DEFAULT (_EUSART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF (0x1UL << 6) /**< TX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IF_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF_DEFAULT (_EUSART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXUF (0x1UL << 7) /**< TX FIFO Underflow Interrupt Flag */ +#define _EUSART_IF_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ +#define _EUSART_IF_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ +#define _EUSART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXUF_DEFAULT (_EUSART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _EUSART_IF_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IF_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR_DEFAULT (_EUSART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _EUSART_IF_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IF_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR_DEFAULT (_EUSART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _EUSART_IF_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IF_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF_DEFAULT (_EUSART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_LOADERR (0x1UL << 11) /**< Load Error Interrupt Flag */ +#define _EUSART_IF_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ +#define _EUSART_IF_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ +#define _EUSART_IF_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_LOADERR_DEFAULT (_EUSART_IF_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _EUSART_IF_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IF_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF_DEFAULT (_EUSART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _EUSART_IF_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE_DEFAULT (_EUSART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CSWU (0x1UL << 16) /**< CS Wake-up Interrupt Flag */ +#define _EUSART_IF_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ +#define _EUSART_IF_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ +#define _EUSART_IF_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CSWU_DEFAULT (_EUSART_IF_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF (0x1UL << 18) /**< Start Frame Interrupt Flag */ +#define _EUSART_IF_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IF_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF_DEFAULT (_EUSART_IF_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF (0x1UL << 19) /**< Signal Frame Interrupt Flag */ +#define _EUSART_IF_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IF_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF_DEFAULT (_EUSART_IF_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Interrupt Flag */ +#define _EUSART_IF_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE_DEFAULT (_EUSART_IF_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXTO (0x1UL << 25) /**< RX Timeout Interrupt Flag */ +#define _EUSART_IF_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ +#define _EUSART_IF_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ +#define _EUSART_IF_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXTO_DEFAULT (_EUSART_IF_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IF */ /* Bit fields for EUSART IEN */ -#define _EUSART_IEN_RESETVALUE 0x00000000UL /**< Default value for EUSART_IEN */ -#define _EUSART_IEN_MASK 0x030D3FFFUL /**< Mask for EUSART_IEN */ -#define EUSART_IEN_TXC (0x1UL << 0) /**< TX Complete Enable */ -#define _EUSART_IEN_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ -#define _EUSART_IEN_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ -#define _EUSART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXC_DEFAULT (_EUSART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXFL (0x1UL << 1) /**< TX FIFO Level Enable */ -#define _EUSART_IEN_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ -#define _EUSART_IEN_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ -#define _EUSART_IEN_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXFL_DEFAULT (_EUSART_IEN_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXFL (0x1UL << 2) /**< RX FIFO Level Enable */ -#define _EUSART_IEN_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ -#define _EUSART_IEN_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ -#define _EUSART_IEN_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXFL_DEFAULT (_EUSART_IEN_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXFULL (0x1UL << 3) /**< RX FIFO Full Enable */ -#define _EUSART_IEN_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ -#define _EUSART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ -#define _EUSART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXFULL_DEFAULT (_EUSART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXOF (0x1UL << 4) /**< RX FIFO Overflow Enable */ -#define _EUSART_IEN_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ -#define _EUSART_IEN_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ -#define _EUSART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXOF_DEFAULT (_EUSART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXUF (0x1UL << 5) /**< RX FIFO Underflow Enable */ -#define _EUSART_IEN_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ -#define _EUSART_IEN_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ -#define _EUSART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXUF_DEFAULT (_EUSART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXOF (0x1UL << 6) /**< TX FIFO Overflow Enable */ -#define _EUSART_IEN_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ -#define _EUSART_IEN_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ -#define _EUSART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXOF_DEFAULT (_EUSART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXUF (0x1UL << 7) /**< TX FIFO Underflow Enable */ -#define _EUSART_IEN_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ -#define _EUSART_IEN_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ -#define _EUSART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXUF_DEFAULT (_EUSART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_PERR (0x1UL << 8) /**< Parity Error Enable */ -#define _EUSART_IEN_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ -#define _EUSART_IEN_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ -#define _EUSART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_PERR_DEFAULT (_EUSART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_FERR (0x1UL << 9) /**< Framing Error Enable */ -#define _EUSART_IEN_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ -#define _EUSART_IEN_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ -#define _EUSART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_FERR_DEFAULT (_EUSART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Addr Frame Enable */ -#define _EUSART_IEN_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ -#define _EUSART_IEN_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ -#define _EUSART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_MPAF_DEFAULT (_EUSART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_LOADERR (0x1UL << 11) /**< Load Error Enable */ -#define _EUSART_IEN_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ -#define _EUSART_IEN_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ -#define _EUSART_IEN_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_LOADERR_DEFAULT (_EUSART_IEN_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Enable */ -#define _EUSART_IEN_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ -#define _EUSART_IEN_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ -#define _EUSART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_CCF_DEFAULT (_EUSART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXIDLE (0x1UL << 13) /**< TX IDLE Enable */ -#define _EUSART_IEN_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ -#define _EUSART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ -#define _EUSART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXIDLE_DEFAULT (_EUSART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_CSWU (0x1UL << 16) /**< CS Wake-up Enable */ -#define _EUSART_IEN_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ -#define _EUSART_IEN_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ -#define _EUSART_IEN_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_CSWU_DEFAULT (_EUSART_IEN_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_STARTF (0x1UL << 18) /**< Start Frame Enable */ -#define _EUSART_IEN_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ -#define _EUSART_IEN_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ -#define _EUSART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_STARTF_DEFAULT (_EUSART_IEN_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_SIGF (0x1UL << 19) /**< Signal Frame Enable */ -#define _EUSART_IEN_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ -#define _EUSART_IEN_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ -#define _EUSART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_SIGF_DEFAULT (_EUSART_IEN_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Enable */ -#define _EUSART_IEN_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ -#define _EUSART_IEN_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ -#define _EUSART_IEN_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_AUTOBAUDDONE_DEFAULT (_EUSART_IEN_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXTO (0x1UL << 25) /**< RX Timeout Enable */ -#define _EUSART_IEN_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ -#define _EUSART_IEN_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ -#define _EUSART_IEN_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXTO_DEFAULT (_EUSART_IEN_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define _EUSART_IEN_RESETVALUE 0x00000000UL /**< Default value for EUSART_IEN */ +#define _EUSART_IEN_MASK 0x030D3FFFUL /**< Mask for EUSART_IEN */ +#define EUSART_IEN_TXC (0x1UL << 0) /**< TX Complete Enable */ +#define _EUSART_IEN_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IEN_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXC_DEFAULT (_EUSART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL (0x1UL << 1) /**< TX FIFO Level Enable */ +#define _EUSART_IEN_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL_DEFAULT (_EUSART_IEN_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL (0x1UL << 2) /**< RX FIFO Level Enable */ +#define _EUSART_IEN_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL_DEFAULT (_EUSART_IEN_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL (0x1UL << 3) /**< RX FIFO Full Enable */ +#define _EUSART_IEN_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL_DEFAULT (_EUSART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF (0x1UL << 4) /**< RX FIFO Overflow Enable */ +#define _EUSART_IEN_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF_DEFAULT (_EUSART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF (0x1UL << 5) /**< RX FIFO Underflow Enable */ +#define _EUSART_IEN_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF_DEFAULT (_EUSART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF (0x1UL << 6) /**< TX FIFO Overflow Enable */ +#define _EUSART_IEN_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF_DEFAULT (_EUSART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXUF (0x1UL << 7) /**< TX FIFO Underflow Enable */ +#define _EUSART_IEN_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ +#define _EUSART_IEN_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ +#define _EUSART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXUF_DEFAULT (_EUSART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR (0x1UL << 8) /**< Parity Error Enable */ +#define _EUSART_IEN_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IEN_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR_DEFAULT (_EUSART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR (0x1UL << 9) /**< Framing Error Enable */ +#define _EUSART_IEN_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IEN_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR_DEFAULT (_EUSART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Addr Frame Enable */ +#define _EUSART_IEN_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF_DEFAULT (_EUSART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_LOADERR (0x1UL << 11) /**< Load Error Enable */ +#define _EUSART_IEN_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ +#define _EUSART_IEN_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ +#define _EUSART_IEN_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_LOADERR_DEFAULT (_EUSART_IEN_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Enable */ +#define _EUSART_IEN_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IEN_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF_DEFAULT (_EUSART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE (0x1UL << 13) /**< TX IDLE Enable */ +#define _EUSART_IEN_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE_DEFAULT (_EUSART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CSWU (0x1UL << 16) /**< CS Wake-up Enable */ +#define _EUSART_IEN_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ +#define _EUSART_IEN_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ +#define _EUSART_IEN_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CSWU_DEFAULT (_EUSART_IEN_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF (0x1UL << 18) /**< Start Frame Enable */ +#define _EUSART_IEN_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF_DEFAULT (_EUSART_IEN_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF (0x1UL << 19) /**< Signal Frame Enable */ +#define _EUSART_IEN_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF_DEFAULT (_EUSART_IEN_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Enable */ +#define _EUSART_IEN_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE_DEFAULT (_EUSART_IEN_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXTO (0x1UL << 25) /**< RX Timeout Enable */ +#define _EUSART_IEN_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ +#define _EUSART_IEN_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ +#define _EUSART_IEN_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXTO_DEFAULT (_EUSART_IEN_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IEN */ /* Bit fields for EUSART SYNCBUSY */ -#define _EUSART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for EUSART_SYNCBUSY */ -#define _EUSART_SYNCBUSY_MASK 0x00000FFFUL /**< Mask for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_DIV (0x1UL << 0) /**< SYNCBUSY for DIV in CLKDIV */ -#define _EUSART_SYNCBUSY_DIV_SHIFT 0 /**< Shift value for EUSART_DIV */ -#define _EUSART_SYNCBUSY_DIV_MASK 0x1UL /**< Bit mask for EUSART_DIV */ -#define _EUSART_SYNCBUSY_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_DIV_DEFAULT (_EUSART_SYNCBUSY_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXTEN (0x1UL << 1) /**< SYNCBUSY for RXTEN in TRIGCTRL */ -#define _EUSART_SYNCBUSY_RXTEN_SHIFT 1 /**< Shift value for EUSART_RXTEN */ -#define _EUSART_SYNCBUSY_RXTEN_MASK 0x2UL /**< Bit mask for EUSART_RXTEN */ -#define _EUSART_SYNCBUSY_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXTEN_DEFAULT (_EUSART_SYNCBUSY_RXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTEN (0x1UL << 2) /**< SYNCBUSY for TXTEN in TRIGCTRL */ -#define _EUSART_SYNCBUSY_TXTEN_SHIFT 2 /**< Shift value for EUSART_TXTEN */ -#define _EUSART_SYNCBUSY_TXTEN_MASK 0x4UL /**< Bit mask for EUSART_TXTEN */ -#define _EUSART_SYNCBUSY_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTEN_DEFAULT (_EUSART_SYNCBUSY_TXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXEN (0x1UL << 3) /**< SYNCBUSY for RXEN in CMD */ -#define _EUSART_SYNCBUSY_RXEN_SHIFT 3 /**< Shift value for EUSART_RXEN */ -#define _EUSART_SYNCBUSY_RXEN_MASK 0x8UL /**< Bit mask for EUSART_RXEN */ -#define _EUSART_SYNCBUSY_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXEN_DEFAULT (_EUSART_SYNCBUSY_RXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXDIS (0x1UL << 4) /**< SYNCBUSY for RXDIS in CMD */ -#define _EUSART_SYNCBUSY_RXDIS_SHIFT 4 /**< Shift value for EUSART_RXDIS */ -#define _EUSART_SYNCBUSY_RXDIS_MASK 0x10UL /**< Bit mask for EUSART_RXDIS */ -#define _EUSART_SYNCBUSY_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXDIS_DEFAULT (_EUSART_SYNCBUSY_RXDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXEN (0x1UL << 5) /**< SYNCBUSY for TXEN in CMD */ -#define _EUSART_SYNCBUSY_TXEN_SHIFT 5 /**< Shift value for EUSART_TXEN */ -#define _EUSART_SYNCBUSY_TXEN_MASK 0x20UL /**< Bit mask for EUSART_TXEN */ -#define _EUSART_SYNCBUSY_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXEN_DEFAULT (_EUSART_SYNCBUSY_TXEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXDIS (0x1UL << 6) /**< SYNCBUSY for TXDIS in CMD */ -#define _EUSART_SYNCBUSY_TXDIS_SHIFT 6 /**< Shift value for EUSART_TXDIS */ -#define _EUSART_SYNCBUSY_TXDIS_MASK 0x40UL /**< Bit mask for EUSART_TXDIS */ -#define _EUSART_SYNCBUSY_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXDIS_DEFAULT (_EUSART_SYNCBUSY_TXDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXBLOCKEN (0x1UL << 7) /**< SYNCBUSY for RXBLOCKEN in CMD */ -#define _EUSART_SYNCBUSY_RXBLOCKEN_SHIFT 7 /**< Shift value for EUSART_RXBLOCKEN */ -#define _EUSART_SYNCBUSY_RXBLOCKEN_MASK 0x80UL /**< Bit mask for EUSART_RXBLOCKEN */ -#define _EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXBLOCKDIS (0x1UL << 8) /**< SYNCBUSY for RXBLOCKDIS in CMD */ -#define _EUSART_SYNCBUSY_RXBLOCKDIS_SHIFT 8 /**< Shift value for EUSART_RXBLOCKDIS */ -#define _EUSART_SYNCBUSY_RXBLOCKDIS_MASK 0x100UL /**< Bit mask for EUSART_RXBLOCKDIS */ -#define _EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTRIEN (0x1UL << 9) /**< SYNCBUSY for TXTRIEN in CMD */ -#define _EUSART_SYNCBUSY_TXTRIEN_SHIFT 9 /**< Shift value for EUSART_TXTRIEN */ -#define _EUSART_SYNCBUSY_TXTRIEN_MASK 0x200UL /**< Bit mask for EUSART_TXTRIEN */ -#define _EUSART_SYNCBUSY_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTRIEN_DEFAULT (_EUSART_SYNCBUSY_TXTRIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTRIDIS (0x1UL << 10) /**< SYNCBUSY in TXTRIDIS in CMD */ -#define _EUSART_SYNCBUSY_TXTRIDIS_SHIFT 10 /**< Shift value for EUSART_TXTRIDIS */ -#define _EUSART_SYNCBUSY_TXTRIDIS_MASK 0x400UL /**< Bit mask for EUSART_TXTRIDIS */ -#define _EUSART_SYNCBUSY_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTRIDIS_DEFAULT (_EUSART_SYNCBUSY_TXTRIDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_AUTOTXTEN (0x1UL << 11) /**< SYNCBUSY for AUTOTXTEN in TRIGCTRL */ -#define _EUSART_SYNCBUSY_AUTOTXTEN_SHIFT 11 /**< Shift value for EUSART_AUTOTXTEN */ -#define _EUSART_SYNCBUSY_AUTOTXTEN_MASK 0x800UL /**< Bit mask for EUSART_AUTOTXTEN */ -#define _EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT (_EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define _EUSART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for EUSART_SYNCBUSY */ +#define _EUSART_SYNCBUSY_MASK 0x00000FFFUL /**< Mask for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV (0x1UL << 0) /**< SYNCBUSY for DIV in CLKDIV */ +#define _EUSART_SYNCBUSY_DIV_SHIFT 0 /**< Shift value for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_MASK 0x1UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV_DEFAULT (_EUSART_SYNCBUSY_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN (0x1UL << 1) /**< SYNCBUSY for RXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_RXTEN_SHIFT 1 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_MASK 0x2UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN_DEFAULT (_EUSART_SYNCBUSY_RXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN (0x1UL << 2) /**< SYNCBUSY for TXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_TXTEN_SHIFT 2 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_MASK 0x4UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN_DEFAULT (_EUSART_SYNCBUSY_TXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN (0x1UL << 3) /**< SYNCBUSY for RXEN in CMD */ +#define _EUSART_SYNCBUSY_RXEN_SHIFT 3 /**< Shift value for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_MASK 0x8UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN_DEFAULT (_EUSART_SYNCBUSY_RXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS (0x1UL << 4) /**< SYNCBUSY for RXDIS in CMD */ +#define _EUSART_SYNCBUSY_RXDIS_SHIFT 4 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_MASK 0x10UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS_DEFAULT (_EUSART_SYNCBUSY_RXDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN (0x1UL << 5) /**< SYNCBUSY for TXEN in CMD */ +#define _EUSART_SYNCBUSY_TXEN_SHIFT 5 /**< Shift value for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_MASK 0x20UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN_DEFAULT (_EUSART_SYNCBUSY_TXEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS (0x1UL << 6) /**< SYNCBUSY for TXDIS in CMD */ +#define _EUSART_SYNCBUSY_TXDIS_SHIFT 6 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_MASK 0x40UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS_DEFAULT (_EUSART_SYNCBUSY_TXDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN (0x1UL << 7) /**< SYNCBUSY for RXBLOCKEN in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_SHIFT 7 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_MASK 0x80UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS (0x1UL << 8) /**< SYNCBUSY for RXBLOCKDIS in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_SHIFT 8 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_MASK 0x100UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN (0x1UL << 9) /**< SYNCBUSY for TXTRIEN in CMD */ +#define _EUSART_SYNCBUSY_TXTRIEN_SHIFT 9 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_MASK 0x200UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN_DEFAULT (_EUSART_SYNCBUSY_TXTRIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS (0x1UL << 10) /**< SYNCBUSY in TXTRIDIS in CMD */ +#define _EUSART_SYNCBUSY_TXTRIDIS_SHIFT 10 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_MASK 0x400UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS_DEFAULT (_EUSART_SYNCBUSY_TXTRIDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_AUTOTXTEN (0x1UL << 11) /**< SYNCBUSY for AUTOTXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_SHIFT 11 /**< Shift value for EUSART_AUTOTXTEN */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_MASK 0x800UL /**< Bit mask for EUSART_AUTOTXTEN */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT (_EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ /** @} End of group EFR32SG23_EUSART_BitFields */ /** @} End of group EFR32SG23_EUSART */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_fsrco.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_fsrco.h index 7e46e11619..62fa6fd359 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_fsrco.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_FSRCO_H #define EFR32SG23_FSRCO_H - #define FSRCO_HAS_SET_CLEAR /**************************************************************************//** @@ -43,15 +42,14 @@ *****************************************************************************/ /** FSRCO Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP Version */ - uint32_t RESERVED0[1023U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - uint32_t RESERVED1[1023U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - uint32_t RESERVED2[1023U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + uint32_t RESERVED0[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + uint32_t RESERVED1[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + uint32_t RESERVED2[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ } FSRCO_TypeDef; /** @} End of group EFR32SG23_FSRCO */ @@ -63,12 +61,12 @@ typedef struct *****************************************************************************/ /* Bit fields for FSRCO IPVERSION */ -#define _FSRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for FSRCO_IPVERSION */ -#define _FSRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for FSRCO_IPVERSION */ -#define _FSRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for FSRCO_IPVERSION */ -#define _FSRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for FSRCO_IPVERSION */ -#define _FSRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for FSRCO_IPVERSION */ -#define FSRCO_IPVERSION_IPVERSION_DEFAULT (_FSRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for FSRCO_IPVERSION */ +#define FSRCO_IPVERSION_IPVERSION_DEFAULT (_FSRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for FSRCO_IPVERSION */ /** @} End of group EFR32SG23_FSRCO_BitFields */ /** @} End of group EFR32SG23_FSRCO */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpcrc.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpcrc.h index 654aaf0c3e..270d3d65ef 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpcrc.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_GPCRC_H #define EFR32SG23_GPCRC_H - #define GPCRC_HAS_SET_CLEAR /**************************************************************************//** @@ -43,59 +42,58 @@ *****************************************************************************/ /** GPCRC Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP Version ID */ - __IOM uint32_t EN; /**< CRC Enable */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IOM uint32_t INIT; /**< CRC Init Value */ - __IOM uint32_t POLY; /**< CRC Polynomial Value */ - __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ - __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ - __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ - __IM uint32_t DATA; /**< CRC Data Register */ - __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ - __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ - uint32_t RESERVED0[1012U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version ID */ - __IOM uint32_t EN_SET; /**< CRC Enable */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IOM uint32_t INIT_SET; /**< CRC Init Value */ - __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */ - __IOM uint32_t INPUTDATA_SET; /**< Input 32-bit Data Register */ - __IOM uint32_t INPUTDATAHWORD_SET; /**< Input 16-bit Data Register */ - __IOM uint32_t INPUTDATABYTE_SET; /**< Input 8-bit Data Register */ - __IM uint32_t DATA_SET; /**< CRC Data Register */ - __IM uint32_t DATAREV_SET; /**< CRC Data Reverse Register */ - __IM uint32_t DATABYTEREV_SET; /**< CRC Data Byte Reverse Register */ - uint32_t RESERVED1[1012U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ - __IOM uint32_t EN_CLR; /**< CRC Enable */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IOM uint32_t INIT_CLR; /**< CRC Init Value */ - __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */ - __IOM uint32_t INPUTDATA_CLR; /**< Input 32-bit Data Register */ - __IOM uint32_t INPUTDATAHWORD_CLR; /**< Input 16-bit Data Register */ - __IOM uint32_t INPUTDATABYTE_CLR; /**< Input 8-bit Data Register */ - __IM uint32_t DATA_CLR; /**< CRC Data Register */ - __IM uint32_t DATAREV_CLR; /**< CRC Data Reverse Register */ - __IM uint32_t DATABYTEREV_CLR; /**< CRC Data Byte Reverse Register */ - uint32_t RESERVED2[1012U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ - __IOM uint32_t EN_TGL; /**< CRC Enable */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IOM uint32_t INIT_TGL; /**< CRC Init Value */ - __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */ - __IOM uint32_t INPUTDATA_TGL; /**< Input 32-bit Data Register */ - __IOM uint32_t INPUTDATAHWORD_TGL; /**< Input 16-bit Data Register */ - __IOM uint32_t INPUTDATABYTE_TGL; /**< Input 8-bit Data Register */ - __IM uint32_t DATA_TGL; /**< CRC Data Register */ - __IM uint32_t DATAREV_TGL; /**< CRC Data Reverse Register */ - __IM uint32_t DATABYTEREV_TGL; /**< CRC Data Byte Reverse Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t EN; /**< CRC Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t INIT; /**< CRC Init Value */ + __IOM uint32_t POLY; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ + __IM uint32_t DATA; /**< CRC Data Register */ + __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED0[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t EN_SET; /**< CRC Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t INIT_SET; /**< CRC Init Value */ + __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_SET; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_SET; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_SET; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_SET; /**< CRC Data Register */ + __IM uint32_t DATAREV_SET; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_SET; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED1[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t EN_CLR; /**< CRC Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t INIT_CLR; /**< CRC Init Value */ + __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_CLR; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_CLR; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_CLR; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_CLR; /**< CRC Data Register */ + __IM uint32_t DATAREV_CLR; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_CLR; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED2[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t EN_TGL; /**< CRC Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t INIT_TGL; /**< CRC Init Value */ + __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_TGL; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_TGL; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_TGL; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_TGL; /**< CRC Data Register */ + __IM uint32_t DATAREV_TGL; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_TGL; /**< CRC Data Byte Reverse Register */ } GPCRC_TypeDef; /** @} End of group EFR32SG23_GPCRC */ @@ -107,139 +105,139 @@ typedef struct *****************************************************************************/ /* Bit fields for GPCRC IPVERSION */ -#define _GPCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for GPCRC_IPVERSION */ -#define _GPCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_IPVERSION */ -#define _GPCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPCRC_IPVERSION */ -#define _GPCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_IPVERSION */ -#define _GPCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_IPVERSION */ -#define GPCRC_IPVERSION_IPVERSION_DEFAULT (_GPCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_IPVERSION */ +#define GPCRC_IPVERSION_IPVERSION_DEFAULT (_GPCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_IPVERSION */ /* Bit fields for GPCRC EN */ -#define _GPCRC_EN_RESETVALUE 0x00000000UL /**< Default value for GPCRC_EN */ -#define _GPCRC_EN_MASK 0x00000001UL /**< Mask for GPCRC_EN */ -#define GPCRC_EN_EN (0x1UL << 0) /**< CRC Enable */ -#define _GPCRC_EN_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ -#define _GPCRC_EN_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ -#define _GPCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_EN */ -#define _GPCRC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_EN */ -#define _GPCRC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_EN */ -#define GPCRC_EN_EN_DEFAULT (_GPCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_EN */ -#define GPCRC_EN_EN_DISABLE (_GPCRC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_EN */ -#define GPCRC_EN_EN_ENABLE (_GPCRC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_EN */ +#define _GPCRC_EN_RESETVALUE 0x00000000UL /**< Default value for GPCRC_EN */ +#define _GPCRC_EN_MASK 0x00000001UL /**< Mask for GPCRC_EN */ +#define GPCRC_EN_EN (0x1UL << 0) /**< CRC Enable */ +#define _GPCRC_EN_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ +#define _GPCRC_EN_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ +#define _GPCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_EN */ +#define _GPCRC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_EN */ +#define _GPCRC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_EN */ +#define GPCRC_EN_EN_DEFAULT (_GPCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_EN */ +#define GPCRC_EN_EN_DISABLE (_GPCRC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_EN */ +#define GPCRC_EN_EN_ENABLE (_GPCRC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_EN */ /* Bit fields for GPCRC CTRL */ -#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ -#define _GPCRC_CTRL_MASK 0x00002710UL /**< Mask for GPCRC_CTRL */ -#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ -#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ -#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ -#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ -#define _GPCRC_CTRL_POLYSEL_CRC16 0x00000001UL /**< Mode CRC16 for GPCRC_CTRL */ -#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ -#define GPCRC_CTRL_POLYSEL_CRC16 (_GPCRC_CTRL_POLYSEL_CRC16 << 4) /**< Shifted mode CRC16 for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ -#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ -#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ -#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ -#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ -#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ -#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ -#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ -#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ -#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ -#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ -#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ -#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ -#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ -#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ -#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ -#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ -#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ +#define _GPCRC_CTRL_MASK 0x00002710UL /**< Mask for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ +#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC16 0x00000001UL /**< Mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC16 (_GPCRC_CTRL_POLYSEL_CRC16 << 4) /**< Shifted mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ +#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ +#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ +#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ +#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ /* Bit fields for GPCRC CMD */ -#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ -#define _GPCRC_CMD_MASK 0x80000001UL /**< Mask for GPCRC_CMD */ -#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ -#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ -#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ -#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ -#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ +#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ +#define _GPCRC_CMD_MASK 0x80000001UL /**< Mask for GPCRC_CMD */ +#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ +#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ +#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ /* Bit fields for GPCRC INIT */ -#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ -#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ -#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ -#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ -#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ -#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ +#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ +#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ +#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ /* Bit fields for GPCRC POLY */ -#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ -#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ -#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ -#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ -#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ -#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ +#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ +#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ +#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ /* Bit fields for GPCRC INPUTDATA */ -#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ -#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ -#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ -#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ -#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ -#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ +#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ /* Bit fields for GPCRC INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ -#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD*/ +#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ +#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD*/ /* Bit fields for GPCRC INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ -#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE*/ +#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ +#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE*/ /* Bit fields for GPCRC DATA */ -#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ -#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ -#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ -#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ -#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ -#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ +#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ +#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ +#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ /* Bit fields for GPCRC DATAREV */ -#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ -#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ -#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ -#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ -#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ -#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ +#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ /* Bit fields for GPCRC DATABYTEREV */ -#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ -#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ -#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ -#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ -#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ -#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ +#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ /** @} End of group EFR32SG23_GPCRC_BitFields */ /** @} End of group EFR32SG23_GPCRC */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpio.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpio.h index 594bd23f5c..ceb2f1c41a 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpio.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpio.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_GPIO_H #define EFR32SG23_GPIO_H - #define GPIO_HAS_SET_CLEAR /**************************************************************************//** @@ -39,2817 +38,2787 @@ #include "efr32sg23_gpio_port.h" - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< ACMP0 pin enable */ - __IOM uint32_t ACMPOUTROUTE; /**< ACMPOUT port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< ACMP0 pin enable */ + __IOM uint32_t ACMPOUTROUTE; /**< ACMPOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_ACMPROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< CMU pin enable */ - __IOM uint32_t CLKIN0ROUTE; /**< CLKIN0 port/pin select */ - __IOM uint32_t CLKOUT0ROUTE; /**< CLKOUT0 port/pin select */ - __IOM uint32_t CLKOUT1ROUTE; /**< CLKOUT1 port/pin select */ - __IOM uint32_t CLKOUT2ROUTE; /**< CLKOUT2 port/pin select */ - uint32_t RESERVED0[2U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< CMU pin enable */ + __IOM uint32_t CLKIN0ROUTE; /**< CLKIN0 port/pin select */ + __IOM uint32_t CLKOUT0ROUTE; /**< CLKOUT0 port/pin select */ + __IOM uint32_t CLKOUT1ROUTE; /**< CLKOUT1 port/pin select */ + __IOM uint32_t CLKOUT2ROUTE; /**< CLKOUT2 port/pin select */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ } GPIO_CMUROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< EUSART0 pin enable */ - __IOM uint32_t CSROUTE; /**< CS port/pin select */ - __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ - __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ - __IOM uint32_t RXROUTE; /**< RX port/pin select */ - __IOM uint32_t SCLKROUTE; /**< SCLK port/pin select */ - __IOM uint32_t TXROUTE; /**< TX port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< EUSART0 pin enable */ + __IOM uint32_t CSROUTE; /**< CS port/pin select */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t SCLKROUTE; /**< SCLK port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_EUSARTROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< FRC pin enable */ - __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ - __IOM uint32_t DFRAMEROUTE; /**< DFRAME port/pin select */ - __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< FRC pin enable */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DFRAMEROUTE; /**< DFRAME port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_FRCROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< I2C0 pin enable */ - __IOM uint32_t SCLROUTE; /**< SCL port/pin select */ - __IOM uint32_t SDAROUTE; /**< SDA port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< I2C0 pin enable */ + __IOM uint32_t SCLROUTE; /**< SCL port/pin select */ + __IOM uint32_t SDAROUTE; /**< SDA port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_I2CROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< KEYSCAN pin enable */ - __IOM uint32_t COLOUT0ROUTE; /**< COLOUT0 port/pin select */ - __IOM uint32_t COLOUT1ROUTE; /**< COLOUT1 port/pin select */ - __IOM uint32_t COLOUT2ROUTE; /**< COLOUT2 port/pin select */ - __IOM uint32_t COLOUT3ROUTE; /**< COLOUT3 port/pin select */ - __IOM uint32_t COLOUT4ROUTE; /**< COLOUT4 port/pin select */ - __IOM uint32_t COLOUT5ROUTE; /**< COLOUT5 port/pin select */ - __IOM uint32_t COLOUT6ROUTE; /**< COLOUT6 port/pin select */ - __IOM uint32_t COLOUT7ROUTE; /**< COLOUT7 port/pin select */ - __IOM uint32_t ROWSENSE0ROUTE; /**< ROWSENSE0 port/pin select */ - __IOM uint32_t ROWSENSE1ROUTE; /**< ROWSENSE1 port/pin select */ - __IOM uint32_t ROWSENSE2ROUTE; /**< ROWSENSE2 port/pin select */ - __IOM uint32_t ROWSENSE3ROUTE; /**< ROWSENSE3 port/pin select */ - __IOM uint32_t ROWSENSE4ROUTE; /**< ROWSENSE4 port/pin select */ - __IOM uint32_t ROWSENSE5ROUTE; /**< ROWSENSE5 port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< KEYSCAN pin enable */ + __IOM uint32_t COLOUT0ROUTE; /**< COLOUT0 port/pin select */ + __IOM uint32_t COLOUT1ROUTE; /**< COLOUT1 port/pin select */ + __IOM uint32_t COLOUT2ROUTE; /**< COLOUT2 port/pin select */ + __IOM uint32_t COLOUT3ROUTE; /**< COLOUT3 port/pin select */ + __IOM uint32_t COLOUT4ROUTE; /**< COLOUT4 port/pin select */ + __IOM uint32_t COLOUT5ROUTE; /**< COLOUT5 port/pin select */ + __IOM uint32_t COLOUT6ROUTE; /**< COLOUT6 port/pin select */ + __IOM uint32_t COLOUT7ROUTE; /**< COLOUT7 port/pin select */ + __IOM uint32_t ROWSENSE0ROUTE; /**< ROWSENSE0 port/pin select */ + __IOM uint32_t ROWSENSE1ROUTE; /**< ROWSENSE1 port/pin select */ + __IOM uint32_t ROWSENSE2ROUTE; /**< ROWSENSE2 port/pin select */ + __IOM uint32_t ROWSENSE3ROUTE; /**< ROWSENSE3 port/pin select */ + __IOM uint32_t ROWSENSE4ROUTE; /**< ROWSENSE4 port/pin select */ + __IOM uint32_t ROWSENSE5ROUTE; /**< ROWSENSE5 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_KEYSCANROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< LESENSE pin enable */ - __IOM uint32_t CH0OUTROUTE; /**< CH0OUT port/pin select */ - __IOM uint32_t CH1OUTROUTE; /**< CH1OUT port/pin select */ - __IOM uint32_t CH2OUTROUTE; /**< CH2OUT port/pin select */ - __IOM uint32_t CH3OUTROUTE; /**< CH3OUT port/pin select */ - __IOM uint32_t CH4OUTROUTE; /**< CH4OUT port/pin select */ - __IOM uint32_t CH5OUTROUTE; /**< CH5OUT port/pin select */ - __IOM uint32_t CH6OUTROUTE; /**< CH6OUT port/pin select */ - __IOM uint32_t CH7OUTROUTE; /**< CH7OUT port/pin select */ - __IOM uint32_t CH8OUTROUTE; /**< CH8OUT port/pin select */ - __IOM uint32_t CH9OUTROUTE; /**< CH9OUT port/pin select */ - __IOM uint32_t CH10OUTROUTE; /**< CH10OUT port/pin select */ - __IOM uint32_t CH11OUTROUTE; /**< CH11OUT port/pin select */ - __IOM uint32_t CH12OUTROUTE; /**< CH12OUT port/pin select */ - __IOM uint32_t CH13OUTROUTE; /**< CH13OUT port/pin select */ - __IOM uint32_t CH14OUTROUTE; /**< CH14OUT port/pin select */ - __IOM uint32_t CH15OUTROUTE; /**< CH15OUT port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< LESENSE pin enable */ + __IOM uint32_t CH0OUTROUTE; /**< CH0OUT port/pin select */ + __IOM uint32_t CH1OUTROUTE; /**< CH1OUT port/pin select */ + __IOM uint32_t CH2OUTROUTE; /**< CH2OUT port/pin select */ + __IOM uint32_t CH3OUTROUTE; /**< CH3OUT port/pin select */ + __IOM uint32_t CH4OUTROUTE; /**< CH4OUT port/pin select */ + __IOM uint32_t CH5OUTROUTE; /**< CH5OUT port/pin select */ + __IOM uint32_t CH6OUTROUTE; /**< CH6OUT port/pin select */ + __IOM uint32_t CH7OUTROUTE; /**< CH7OUT port/pin select */ + __IOM uint32_t CH8OUTROUTE; /**< CH8OUT port/pin select */ + __IOM uint32_t CH9OUTROUTE; /**< CH9OUT port/pin select */ + __IOM uint32_t CH10OUTROUTE; /**< CH10OUT port/pin select */ + __IOM uint32_t CH11OUTROUTE; /**< CH11OUT port/pin select */ + __IOM uint32_t CH12OUTROUTE; /**< CH12OUT port/pin select */ + __IOM uint32_t CH13OUTROUTE; /**< CH13OUT port/pin select */ + __IOM uint32_t CH14OUTROUTE; /**< CH14OUT port/pin select */ + __IOM uint32_t CH15OUTROUTE; /**< CH15OUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_LESENSEROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< LETIMER pin enable */ - __IOM uint32_t OUT0ROUTE; /**< OUT0 port/pin select */ - __IOM uint32_t OUT1ROUTE; /**< OUT1 port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< LETIMER pin enable */ + __IOM uint32_t OUT0ROUTE; /**< OUT0 port/pin select */ + __IOM uint32_t OUT1ROUTE; /**< OUT1 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_LETIMERROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< MODEM pin enable */ - __IOM uint32_t ANT0ROUTE; /**< ANT0 port/pin select */ - __IOM uint32_t ANT1ROUTE; /**< ANT1 port/pin select */ - __IOM uint32_t ANTROLLOVERROUTE; /**< ANTROLLOVER port/pin select */ - __IOM uint32_t ANTRR0ROUTE; /**< ANTRR0 port/pin select */ - __IOM uint32_t ANTRR1ROUTE; /**< ANTRR1 port/pin select */ - __IOM uint32_t ANTRR2ROUTE; /**< ANTRR2 port/pin select */ - __IOM uint32_t ANTRR3ROUTE; /**< ANTRR3 port/pin select */ - __IOM uint32_t ANTRR4ROUTE; /**< ANTRR4 port/pin select */ - __IOM uint32_t ANTRR5ROUTE; /**< ANTRR5 port/pin select */ - __IOM uint32_t ANTSWENROUTE; /**< ANTSWEN port/pin select */ - __IOM uint32_t ANTSWUSROUTE; /**< ANTSWUS port/pin select */ - __IOM uint32_t ANTTRIGROUTE; /**< ANTTRIG port/pin select */ - __IOM uint32_t ANTTRIGSTOPROUTE; /**< ANTTRIGSTOP port/pin select */ - __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ - __IOM uint32_t DINROUTE; /**< DIN port/pin select */ - __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< MODEM pin enable */ + __IOM uint32_t ANT0ROUTE; /**< ANT0 port/pin select */ + __IOM uint32_t ANT1ROUTE; /**< ANT1 port/pin select */ + __IOM uint32_t ANTROLLOVERROUTE; /**< ANTROLLOVER port/pin select */ + __IOM uint32_t ANTRR0ROUTE; /**< ANTRR0 port/pin select */ + __IOM uint32_t ANTRR1ROUTE; /**< ANTRR1 port/pin select */ + __IOM uint32_t ANTRR2ROUTE; /**< ANTRR2 port/pin select */ + __IOM uint32_t ANTRR3ROUTE; /**< ANTRR3 port/pin select */ + __IOM uint32_t ANTRR4ROUTE; /**< ANTRR4 port/pin select */ + __IOM uint32_t ANTRR5ROUTE; /**< ANTRR5 port/pin select */ + __IOM uint32_t ANTSWENROUTE; /**< ANTSWEN port/pin select */ + __IOM uint32_t ANTSWUSROUTE; /**< ANTSWUS port/pin select */ + __IOM uint32_t ANTTRIGROUTE; /**< ANTTRIG port/pin select */ + __IOM uint32_t ANTTRIGSTOPROUTE; /**< ANTTRIGSTOP port/pin select */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DINROUTE; /**< DIN port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_MODEMROUTE_TypeDef; - -typedef struct -{ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t S0INROUTE; /**< S0IN port/pin select */ - __IOM uint32_t S1INROUTE; /**< S1IN port/pin select */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t S0INROUTE; /**< S0IN port/pin select */ + __IOM uint32_t S1INROUTE; /**< S1IN port/pin select */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ } GPIO_PCNTROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< PRS0 pin enable */ - __IOM uint32_t ASYNCH0ROUTE; /**< ASYNCH0 port/pin select */ - __IOM uint32_t ASYNCH1ROUTE; /**< ASYNCH1 port/pin select */ - __IOM uint32_t ASYNCH2ROUTE; /**< ASYNCH2 port/pin select */ - __IOM uint32_t ASYNCH3ROUTE; /**< ASYNCH3 port/pin select */ - __IOM uint32_t ASYNCH4ROUTE; /**< ASYNCH4 port/pin select */ - __IOM uint32_t ASYNCH5ROUTE; /**< ASYNCH5 port/pin select */ - __IOM uint32_t ASYNCH6ROUTE; /**< ASYNCH6 port/pin select */ - __IOM uint32_t ASYNCH7ROUTE; /**< ASYNCH7 port/pin select */ - __IOM uint32_t ASYNCH8ROUTE; /**< ASYNCH8 port/pin select */ - __IOM uint32_t ASYNCH9ROUTE; /**< ASYNCH9 port/pin select */ - __IOM uint32_t ASYNCH10ROUTE; /**< ASYNCH10 port/pin select */ - __IOM uint32_t ASYNCH11ROUTE; /**< ASYNCH11 port/pin select */ - __IOM uint32_t SYNCH0ROUTE; /**< SYNCH0 port/pin select */ - __IOM uint32_t SYNCH1ROUTE; /**< SYNCH1 port/pin select */ - __IOM uint32_t SYNCH2ROUTE; /**< SYNCH2 port/pin select */ - __IOM uint32_t SYNCH3ROUTE; /**< SYNCH3 port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< PRS0 pin enable */ + __IOM uint32_t ASYNCH0ROUTE; /**< ASYNCH0 port/pin select */ + __IOM uint32_t ASYNCH1ROUTE; /**< ASYNCH1 port/pin select */ + __IOM uint32_t ASYNCH2ROUTE; /**< ASYNCH2 port/pin select */ + __IOM uint32_t ASYNCH3ROUTE; /**< ASYNCH3 port/pin select */ + __IOM uint32_t ASYNCH4ROUTE; /**< ASYNCH4 port/pin select */ + __IOM uint32_t ASYNCH5ROUTE; /**< ASYNCH5 port/pin select */ + __IOM uint32_t ASYNCH6ROUTE; /**< ASYNCH6 port/pin select */ + __IOM uint32_t ASYNCH7ROUTE; /**< ASYNCH7 port/pin select */ + __IOM uint32_t ASYNCH8ROUTE; /**< ASYNCH8 port/pin select */ + __IOM uint32_t ASYNCH9ROUTE; /**< ASYNCH9 port/pin select */ + __IOM uint32_t ASYNCH10ROUTE; /**< ASYNCH10 port/pin select */ + __IOM uint32_t ASYNCH11ROUTE; /**< ASYNCH11 port/pin select */ + __IOM uint32_t SYNCH0ROUTE; /**< SYNCH0 port/pin select */ + __IOM uint32_t SYNCH1ROUTE; /**< SYNCH1 port/pin select */ + __IOM uint32_t SYNCH2ROUTE; /**< SYNCH2 port/pin select */ + __IOM uint32_t SYNCH3ROUTE; /**< SYNCH3 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_PRSROUTE_TypeDef; - -typedef struct -{ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t BUFOUTREQINASYNCROUTE; /**< BUFOUTREQINASYNC port/pin select */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTREQINASYNCROUTE; /**< BUFOUTREQINASYNC port/pin select */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ } GPIO_SYXOROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< TIMER0 pin enable */ - __IOM uint32_t CC0ROUTE; /**< CC0 port/pin select */ - __IOM uint32_t CC1ROUTE; /**< CC1 port/pin select */ - __IOM uint32_t CC2ROUTE; /**< CC2 port/pin select */ - __IOM uint32_t CDTI0ROUTE; /**< CDTI0 port/pin select */ - __IOM uint32_t CDTI1ROUTE; /**< CDTI1 port/pin select */ - __IOM uint32_t CDTI2ROUTE; /**< CDTI2 port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< TIMER0 pin enable */ + __IOM uint32_t CC0ROUTE; /**< CC0 port/pin select */ + __IOM uint32_t CC1ROUTE; /**< CC1 port/pin select */ + __IOM uint32_t CC2ROUTE; /**< CC2 port/pin select */ + __IOM uint32_t CDTI0ROUTE; /**< CDTI0 port/pin select */ + __IOM uint32_t CDTI1ROUTE; /**< CDTI1 port/pin select */ + __IOM uint32_t CDTI2ROUTE; /**< CDTI2 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_TIMERROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< USART0 pin enable */ - __IOM uint32_t CSROUTE; /**< CS port/pin select */ - __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ - __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ - __IOM uint32_t RXROUTE; /**< RX port/pin select */ - __IOM uint32_t CLKROUTE; /**< SCLK port/pin select */ - __IOM uint32_t TXROUTE; /**< TX port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< USART0 pin enable */ + __IOM uint32_t CSROUTE; /**< CS port/pin select */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t CLKROUTE; /**< SCLK port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_USARTROUTE_TypeDef; -typedef struct -{ - __IM uint32_t IPVERSION; /**< main */ - uint32_t RESERVED0[11U]; /**< Reserved for future use */ - GPIO_PORT_TypeDef P[4U]; /**< */ - uint32_t RESERVED1[132U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Lock Register */ - uint32_t RESERVED2[3U]; /**< Reserved for future use */ - __IM uint32_t GPIOLOCKSTATUS; /**< Lock Status */ - uint32_t RESERVED3[3U]; /**< Reserved for future use */ - __IOM uint32_t ABUSALLOC; /**< A Bus allocation */ - __IOM uint32_t BBUSALLOC; /**< B Bus allocation */ - __IOM uint32_t CDBUSALLOC; /**< CD Bus allocation */ - uint32_t RESERVED4[53U]; /**< Reserved for future use */ - __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low */ - __IOM uint32_t EXTIPSELH; /**< External interrupt Port Select High */ - __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low */ - __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High */ - __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger */ - __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger */ - uint32_t RESERVED5[2U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IOM uint32_t EM4WUEN; /**< EM4 wakeup enable */ - __IOM uint32_t EM4WUPOL; /**< EM4 wakeup polarity */ - uint32_t RESERVED7[3U]; /**< Reserved for future use */ - __IOM uint32_t DBGROUTEPEN; /**< Debugger Route Pin enable */ - __IOM uint32_t TRACEROUTEPEN; /**< Trace Route Pin Enable */ - uint32_t RESERVED8[2U]; /**< Reserved for future use */ - uint32_t RESERVED9[4U]; /**< Reserved for future use */ - __IOM uint32_t LCDSEG; /**< LCD Segment Enable */ - uint32_t RESERVED10[3U]; /**< Reserved for future use */ - __IOM uint32_t LCDCOM; /**< LCD Common Enable */ - uint32_t RESERVED11[3U]; /**< Reserved for future use */ - GPIO_ACMPROUTE_TypeDef ACMPROUTE[2U]; /**< acmp0 DBUS config registers */ - GPIO_CMUROUTE_TypeDef CMUROUTE; /**< cmu DBUS config registers */ - uint32_t RESERVED12[4U]; /**< Reserved for future use */ - GPIO_EUSARTROUTE_TypeDef EUSARTROUTE[3U]; /**< eusart0 DBUS config registers */ - GPIO_FRCROUTE_TypeDef FRCROUTE; /**< frc DBUS config registers */ - GPIO_I2CROUTE_TypeDef I2CROUTE[2U]; /**< i2c0 DBUS config registers */ - GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE; /**< keyscan DBUS config registers */ - GPIO_LESENSEROUTE_TypeDef LESENSEROUTE; /**< lesense DBUS config registers */ - GPIO_LETIMERROUTE_TypeDef LETIMERROUTE; /**< letimer DBUS config registers */ - GPIO_MODEMROUTE_TypeDef MODEMROUTE; /**< modem DBUS config registers */ - GPIO_PCNTROUTE_TypeDef PCNTROUTE[1U]; /**< pcnt0 DBUS config registers */ - GPIO_PRSROUTE_TypeDef PRSROUTE[1U]; /**< prs0 DBUS config registers */ - uint32_t RESERVED13[23U]; /**< Reserved for future use */ - GPIO_SYXOROUTE_TypeDef SYXOROUTE[1U]; /**< syxo0 DBUS config registers */ - GPIO_TIMERROUTE_TypeDef TIMERROUTE[5U]; /**< timer0 DBUS config registers */ - GPIO_USARTROUTE_TypeDef USARTROUTE[1U]; /**< usart0 DBUS config registers */ - uint32_t RESERVED14[530U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< main */ - uint32_t RESERVED15[11U]; /**< Reserved for future use */ - GPIO_PORT_TypeDef P_SET[4U]; /**< */ - uint32_t RESERVED16[132U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Lock Register */ - uint32_t RESERVED17[3U]; /**< Reserved for future use */ - __IM uint32_t GPIOLOCKSTATUS_SET; /**< Lock Status */ - uint32_t RESERVED18[3U]; /**< Reserved for future use */ - __IOM uint32_t ABUSALLOC_SET; /**< A Bus allocation */ - __IOM uint32_t BBUSALLOC_SET; /**< B Bus allocation */ - __IOM uint32_t CDBUSALLOC_SET; /**< CD Bus allocation */ - uint32_t RESERVED19[53U]; /**< Reserved for future use */ - __IOM uint32_t EXTIPSELL_SET; /**< External Interrupt Port Select Low */ - __IOM uint32_t EXTIPSELH_SET; /**< External interrupt Port Select High */ - __IOM uint32_t EXTIPINSELL_SET; /**< External Interrupt Pin Select Low */ - __IOM uint32_t EXTIPINSELH_SET; /**< External Interrupt Pin Select High */ - __IOM uint32_t EXTIRISE_SET; /**< External Interrupt Rising Edge Trigger */ - __IOM uint32_t EXTIFALL_SET; /**< External Interrupt Falling Edge Trigger */ - uint32_t RESERVED20[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup enable */ - __IOM uint32_t EM4WUPOL_SET; /**< EM4 wakeup polarity */ - uint32_t RESERVED22[3U]; /**< Reserved for future use */ - __IOM uint32_t DBGROUTEPEN_SET; /**< Debugger Route Pin enable */ - __IOM uint32_t TRACEROUTEPEN_SET; /**< Trace Route Pin Enable */ - uint32_t RESERVED23[2U]; /**< Reserved for future use */ - uint32_t RESERVED24[4U]; /**< Reserved for future use */ - __IOM uint32_t LCDSEG_SET; /**< LCD Segment Enable */ - uint32_t RESERVED25[3U]; /**< Reserved for future use */ - __IOM uint32_t LCDCOM_SET; /**< LCD Common Enable */ - uint32_t RESERVED26[3U]; /**< Reserved for future use */ - GPIO_ACMPROUTE_TypeDef ACMPROUTE_SET[2U]; /**< acmp0 DBUS config registers */ - GPIO_CMUROUTE_TypeDef CMUROUTE_SET; /**< cmu DBUS config registers */ - uint32_t RESERVED27[4U]; /**< Reserved for future use */ - GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_SET[3U]; /**< eusart0 DBUS config registers */ - GPIO_FRCROUTE_TypeDef FRCROUTE_SET; /**< frc DBUS config registers */ - GPIO_I2CROUTE_TypeDef I2CROUTE_SET[2U]; /**< i2c0 DBUS config registers */ - GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_SET; /**< keyscan DBUS config registers */ - GPIO_LESENSEROUTE_TypeDef LESENSEROUTE_SET; /**< lesense DBUS config registers */ - GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_SET; /**< letimer DBUS config registers */ - GPIO_MODEMROUTE_TypeDef MODEMROUTE_SET; /**< modem DBUS config registers */ - GPIO_PCNTROUTE_TypeDef PCNTROUTE_SET[1U]; /**< pcnt0 DBUS config registers */ - GPIO_PRSROUTE_TypeDef PRSROUTE_SET[1U]; /**< prs0 DBUS config registers */ - uint32_t RESERVED28[23U]; /**< Reserved for future use */ - GPIO_SYXOROUTE_TypeDef SYXOROUTE_SET[1U]; /**< syxo0 DBUS config registers */ - GPIO_TIMERROUTE_TypeDef TIMERROUTE_SET[5U]; /**< timer0 DBUS config registers */ - GPIO_USARTROUTE_TypeDef USARTROUTE_SET[1U]; /**< usart0 DBUS config registers */ - uint32_t RESERVED29[530U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< main */ - uint32_t RESERVED30[11U]; /**< Reserved for future use */ - GPIO_PORT_TypeDef P_CLR[4U]; /**< */ - uint32_t RESERVED31[132U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Lock Register */ - uint32_t RESERVED32[3U]; /**< Reserved for future use */ - __IM uint32_t GPIOLOCKSTATUS_CLR; /**< Lock Status */ - uint32_t RESERVED33[3U]; /**< Reserved for future use */ - __IOM uint32_t ABUSALLOC_CLR; /**< A Bus allocation */ - __IOM uint32_t BBUSALLOC_CLR; /**< B Bus allocation */ - __IOM uint32_t CDBUSALLOC_CLR; /**< CD Bus allocation */ - uint32_t RESERVED34[53U]; /**< Reserved for future use */ - __IOM uint32_t EXTIPSELL_CLR; /**< External Interrupt Port Select Low */ - __IOM uint32_t EXTIPSELH_CLR; /**< External interrupt Port Select High */ - __IOM uint32_t EXTIPINSELL_CLR; /**< External Interrupt Pin Select Low */ - __IOM uint32_t EXTIPINSELH_CLR; /**< External Interrupt Pin Select High */ - __IOM uint32_t EXTIRISE_CLR; /**< External Interrupt Rising Edge Trigger */ - __IOM uint32_t EXTIFALL_CLR; /**< External Interrupt Falling Edge Trigger */ - uint32_t RESERVED35[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - uint32_t RESERVED36[1U]; /**< Reserved for future use */ - __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup enable */ - __IOM uint32_t EM4WUPOL_CLR; /**< EM4 wakeup polarity */ - uint32_t RESERVED37[3U]; /**< Reserved for future use */ - __IOM uint32_t DBGROUTEPEN_CLR; /**< Debugger Route Pin enable */ - __IOM uint32_t TRACEROUTEPEN_CLR; /**< Trace Route Pin Enable */ - uint32_t RESERVED38[2U]; /**< Reserved for future use */ - uint32_t RESERVED39[4U]; /**< Reserved for future use */ - __IOM uint32_t LCDSEG_CLR; /**< LCD Segment Enable */ - uint32_t RESERVED40[3U]; /**< Reserved for future use */ - __IOM uint32_t LCDCOM_CLR; /**< LCD Common Enable */ - uint32_t RESERVED41[3U]; /**< Reserved for future use */ - GPIO_ACMPROUTE_TypeDef ACMPROUTE_CLR[2U]; /**< acmp0 DBUS config registers */ - GPIO_CMUROUTE_TypeDef CMUROUTE_CLR; /**< cmu DBUS config registers */ - uint32_t RESERVED42[4U]; /**< Reserved for future use */ - GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_CLR[3U]; /**< eusart0 DBUS config registers */ - GPIO_FRCROUTE_TypeDef FRCROUTE_CLR; /**< frc DBUS config registers */ - GPIO_I2CROUTE_TypeDef I2CROUTE_CLR[2U]; /**< i2c0 DBUS config registers */ - GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_CLR; /**< keyscan DBUS config registers */ - GPIO_LESENSEROUTE_TypeDef LESENSEROUTE_CLR; /**< lesense DBUS config registers */ - GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_CLR; /**< letimer DBUS config registers */ - GPIO_MODEMROUTE_TypeDef MODEMROUTE_CLR; /**< modem DBUS config registers */ - GPIO_PCNTROUTE_TypeDef PCNTROUTE_CLR[1U]; /**< pcnt0 DBUS config registers */ - GPIO_PRSROUTE_TypeDef PRSROUTE_CLR[1U]; /**< prs0 DBUS config registers */ - uint32_t RESERVED43[23U]; /**< Reserved for future use */ - GPIO_SYXOROUTE_TypeDef SYXOROUTE_CLR[1U]; /**< syxo0 DBUS config registers */ - GPIO_TIMERROUTE_TypeDef TIMERROUTE_CLR[5U]; /**< timer0 DBUS config registers */ - GPIO_USARTROUTE_TypeDef USARTROUTE_CLR[1U]; /**< usart0 DBUS config registers */ - uint32_t RESERVED44[530U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< main */ - uint32_t RESERVED45[11U]; /**< Reserved for future use */ - GPIO_PORT_TypeDef P_TGL[4U]; /**< */ - uint32_t RESERVED46[132U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Lock Register */ - uint32_t RESERVED47[3U]; /**< Reserved for future use */ - __IM uint32_t GPIOLOCKSTATUS_TGL; /**< Lock Status */ - uint32_t RESERVED48[3U]; /**< Reserved for future use */ - __IOM uint32_t ABUSALLOC_TGL; /**< A Bus allocation */ - __IOM uint32_t BBUSALLOC_TGL; /**< B Bus allocation */ - __IOM uint32_t CDBUSALLOC_TGL; /**< CD Bus allocation */ - uint32_t RESERVED49[53U]; /**< Reserved for future use */ - __IOM uint32_t EXTIPSELL_TGL; /**< External Interrupt Port Select Low */ - __IOM uint32_t EXTIPSELH_TGL; /**< External interrupt Port Select High */ - __IOM uint32_t EXTIPINSELL_TGL; /**< External Interrupt Pin Select Low */ - __IOM uint32_t EXTIPINSELH_TGL; /**< External Interrupt Pin Select High */ - __IOM uint32_t EXTIRISE_TGL; /**< External Interrupt Rising Edge Trigger */ - __IOM uint32_t EXTIFALL_TGL; /**< External Interrupt Falling Edge Trigger */ - uint32_t RESERVED50[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - uint32_t RESERVED51[1U]; /**< Reserved for future use */ - __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup enable */ - __IOM uint32_t EM4WUPOL_TGL; /**< EM4 wakeup polarity */ - uint32_t RESERVED52[3U]; /**< Reserved for future use */ - __IOM uint32_t DBGROUTEPEN_TGL; /**< Debugger Route Pin enable */ - __IOM uint32_t TRACEROUTEPEN_TGL; /**< Trace Route Pin Enable */ - uint32_t RESERVED53[2U]; /**< Reserved for future use */ - uint32_t RESERVED54[4U]; /**< Reserved for future use */ - __IOM uint32_t LCDSEG_TGL; /**< LCD Segment Enable */ - uint32_t RESERVED55[3U]; /**< Reserved for future use */ - __IOM uint32_t LCDCOM_TGL; /**< LCD Common Enable */ - uint32_t RESERVED56[3U]; /**< Reserved for future use */ - GPIO_ACMPROUTE_TypeDef ACMPROUTE_TGL[2U]; /**< acmp0 DBUS config registers */ - GPIO_CMUROUTE_TypeDef CMUROUTE_TGL; /**< cmu DBUS config registers */ - uint32_t RESERVED57[4U]; /**< Reserved for future use */ - GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_TGL[3U]; /**< eusart0 DBUS config registers */ - GPIO_FRCROUTE_TypeDef FRCROUTE_TGL; /**< frc DBUS config registers */ - GPIO_I2CROUTE_TypeDef I2CROUTE_TGL[2U]; /**< i2c0 DBUS config registers */ - GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_TGL; /**< keyscan DBUS config registers */ - GPIO_LESENSEROUTE_TypeDef LESENSEROUTE_TGL; /**< lesense DBUS config registers */ - GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_TGL; /**< letimer DBUS config registers */ - GPIO_MODEMROUTE_TypeDef MODEMROUTE_TGL; /**< modem DBUS config registers */ - GPIO_PCNTROUTE_TypeDef PCNTROUTE_TGL[1U]; /**< pcnt0 DBUS config registers */ - GPIO_PRSROUTE_TypeDef PRSROUTE_TGL[1U]; /**< prs0 DBUS config registers */ - uint32_t RESERVED58[23U]; /**< Reserved for future use */ - GPIO_SYXOROUTE_TypeDef SYXOROUTE_TGL[1U]; /**< syxo0 DBUS config registers */ - GPIO_TIMERROUTE_TypeDef TIMERROUTE_TGL[5U]; /**< timer0 DBUS config registers */ - GPIO_USARTROUTE_TypeDef USARTROUTE_TGL[1U]; /**< usart0 DBUS config registers */ +typedef struct { + __IM uint32_t IPVERSION; /**< main */ + uint32_t RESERVED0[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P[4U]; /**< */ + uint32_t RESERVED1[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS; /**< Lock Status */ + uint32_t RESERVED3[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC; /**< CD Bus allocation */ + uint32_t RESERVED4[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED5[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL; /**< EM4 wakeup polarity */ + uint32_t RESERVED7[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN; /**< Trace Route Pin Enable */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + uint32_t RESERVED9[4U]; /**< Reserved for future use */ + __IOM uint32_t LCDSEG; /**< LCD Segment Enable */ + uint32_t RESERVED10[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCOM; /**< LCD Common Enable */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE; /**< cmu DBUS config registers */ + uint32_t RESERVED12[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE[3U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE; /**< keyscan DBUS config registers */ + GPIO_LESENSEROUTE_TypeDef LESENSEROUTE; /**< lesense DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE[1U]; /**< prs0 DBUS config registers */ + uint32_t RESERVED13[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE[1U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED14[530U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< main */ + uint32_t RESERVED15[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_SET[4U]; /**< */ + uint32_t RESERVED16[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED17[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_SET; /**< Lock Status */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_SET; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_SET; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_SET; /**< CD Bus allocation */ + uint32_t RESERVED19[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_SET; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_SET; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_SET; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_SET; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_SET; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_SET; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_SET; /**< EM4 wakeup polarity */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_SET; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_SET; /**< Trace Route Pin Enable */ + uint32_t RESERVED23[2U]; /**< Reserved for future use */ + uint32_t RESERVED24[4U]; /**< Reserved for future use */ + __IOM uint32_t LCDSEG_SET; /**< LCD Segment Enable */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCOM_SET; /**< LCD Common Enable */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_SET[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_SET; /**< cmu DBUS config registers */ + uint32_t RESERVED27[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_SET[3U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_SET; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_SET[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_SET; /**< keyscan DBUS config registers */ + GPIO_LESENSEROUTE_TypeDef LESENSEROUTE_SET; /**< lesense DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_SET; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_SET; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_SET[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_SET[1U]; /**< prs0 DBUS config registers */ + uint32_t RESERVED28[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_SET[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_SET[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_SET[1U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED29[530U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< main */ + uint32_t RESERVED30[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_CLR[4U]; /**< */ + uint32_t RESERVED31[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED32[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_CLR; /**< Lock Status */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_CLR; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_CLR; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_CLR; /**< CD Bus allocation */ + uint32_t RESERVED34[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_CLR; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_CLR; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_CLR; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_CLR; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_CLR; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_CLR; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED35[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED36[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_CLR; /**< EM4 wakeup polarity */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_CLR; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_CLR; /**< Trace Route Pin Enable */ + uint32_t RESERVED38[2U]; /**< Reserved for future use */ + uint32_t RESERVED39[4U]; /**< Reserved for future use */ + __IOM uint32_t LCDSEG_CLR; /**< LCD Segment Enable */ + uint32_t RESERVED40[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCOM_CLR; /**< LCD Common Enable */ + uint32_t RESERVED41[3U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_CLR[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_CLR; /**< cmu DBUS config registers */ + uint32_t RESERVED42[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_CLR[3U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_CLR; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_CLR[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_CLR; /**< keyscan DBUS config registers */ + GPIO_LESENSEROUTE_TypeDef LESENSEROUTE_CLR; /**< lesense DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_CLR; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_CLR; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_CLR[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_CLR[1U]; /**< prs0 DBUS config registers */ + uint32_t RESERVED43[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_CLR[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_CLR[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_CLR[1U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED44[530U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< main */ + uint32_t RESERVED45[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_TGL[4U]; /**< */ + uint32_t RESERVED46[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + uint32_t RESERVED47[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_TGL; /**< Lock Status */ + uint32_t RESERVED48[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_TGL; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_TGL; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_TGL; /**< CD Bus allocation */ + uint32_t RESERVED49[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_TGL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_TGL; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_TGL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_TGL; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_TGL; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_TGL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED50[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED51[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_TGL; /**< EM4 wakeup polarity */ + uint32_t RESERVED52[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_TGL; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_TGL; /**< Trace Route Pin Enable */ + uint32_t RESERVED53[2U]; /**< Reserved for future use */ + uint32_t RESERVED54[4U]; /**< Reserved for future use */ + __IOM uint32_t LCDSEG_TGL; /**< LCD Segment Enable */ + uint32_t RESERVED55[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCOM_TGL; /**< LCD Common Enable */ + uint32_t RESERVED56[3U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_TGL[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_TGL; /**< cmu DBUS config registers */ + uint32_t RESERVED57[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_TGL[3U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_TGL; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_TGL[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_TGL; /**< keyscan DBUS config registers */ + GPIO_LESENSEROUTE_TypeDef LESENSEROUTE_TGL; /**< lesense DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_TGL; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_TGL; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_TGL[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_TGL[1U]; /**< prs0 DBUS config registers */ + uint32_t RESERVED58[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_TGL[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_TGL[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_TGL[1U]; /**< usart0 DBUS config registers */ } GPIO_TypeDef; - /* Bit fields for GPIO IPVERSION */ -#define _GPIO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for GPIO_IPVERSION */ -#define _GPIO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IPVERSION */ -#define _GPIO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPIO_IPVERSION */ -#define _GPIO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPIO_IPVERSION */ -#define _GPIO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_IPVERSION */ -#define GPIO_IPVERSION_IPVERSION_DEFAULT (_GPIO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IPVERSION */ -#define GPIO_PORTA 0x00000000UL /**< PORTA index */ -#define GPIO_PORTB 0x00000001UL /**< PORTB index */ -#define GPIO_PORTC 0x00000002UL /**< PORTC index */ -#define GPIO_PORTD 0x00000003UL /**< PORTD index */ +#define _GPIO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_IPVERSION */ +#define GPIO_IPVERSION_IPVERSION_DEFAULT (_GPIO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IPVERSION */ +#define GPIO_PORTA 0x00000000UL /**< PORTA index */ +#define GPIO_PORTB 0x00000001UL /**< PORTB index */ +#define GPIO_PORTC 0x00000002UL /**< PORTC index */ +#define GPIO_PORTD 0x00000003UL /**< PORTD index */ /* Bit fields for GPIO LOCK */ -#define _GPIO_LOCK_RESETVALUE 0x0000A534UL /**< Default value for GPIO_LOCK */ -#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ -#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ -#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ -#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x0000A534UL /**< Mode DEFAULT for GPIO_LOCK */ -#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ -#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ -#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ +#define _GPIO_LOCK_RESETVALUE 0x0000A534UL /**< Default value for GPIO_LOCK */ +#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x0000A534UL /**< Mode DEFAULT for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ /* Bit fields for GPIO GPIOLOCKSTATUS */ -#define _GPIO_GPIOLOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for GPIO_GPIOLOCKSTATUS */ -#define _GPIO_GPIOLOCKSTATUS_MASK 0x00000001UL /**< Mask for GPIO_GPIOLOCKSTATUS */ -#define GPIO_GPIOLOCKSTATUS_LOCK (0x1UL << 0) /**< GPIO LOCK status */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for GPIO_LOCK */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for GPIO_LOCK */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_GPIOLOCKSTATUS */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_GPIOLOCKSTATUS */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_GPIOLOCKSTATUS */ -#define GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT (_GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_GPIOLOCKSTATUS*/ -#define GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_GPIOLOCKSTATUS*/ -#define GPIO_GPIOLOCKSTATUS_LOCK_LOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_MASK 0x00000001UL /**< Mask for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK (0x1UL << 0) /**< GPIO LOCK status */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT (_GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_LOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_GPIOLOCKSTATUS */ /* Bit fields for GPIO ABUSALLOC */ -#define _GPIO_ABUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_SHIFT 0 /**< Shift value for GPIO_AEVEN0 */ -#define _GPIO_ABUSALLOC_AEVEN0_MASK 0xFUL /**< Bit mask for GPIO_AEVEN0 */ -#define _GPIO_ABUSALLOC_AEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_DEFAULT (_GPIO_ABUSALLOC_AEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_TRISTATE (_GPIO_ABUSALLOC_AEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_ADC0 (_GPIO_ABUSALLOC_AEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_ACMP0 (_GPIO_ABUSALLOC_AEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_ACMP1 (_GPIO_ABUSALLOC_AEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 (_GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_SHIFT 8 /**< Shift value for GPIO_AEVEN1 */ -#define _GPIO_ABUSALLOC_AEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_AEVEN1 */ -#define _GPIO_ABUSALLOC_AEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_DEFAULT (_GPIO_ABUSALLOC_AEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_TRISTATE (_GPIO_ABUSALLOC_AEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_ADC0 (_GPIO_ABUSALLOC_AEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_ACMP0 (_GPIO_ABUSALLOC_AEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_ACMP1 (_GPIO_ABUSALLOC_AEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 (_GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_SHIFT 16 /**< Shift value for GPIO_AODD0 */ -#define _GPIO_ABUSALLOC_AODD0_MASK 0xF0000UL /**< Bit mask for GPIO_AODD0 */ -#define _GPIO_ABUSALLOC_AODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_DEFAULT (_GPIO_ABUSALLOC_AODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_TRISTATE (_GPIO_ABUSALLOC_AODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_ADC0 (_GPIO_ABUSALLOC_AODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_ACMP0 (_GPIO_ABUSALLOC_AODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_ACMP1 (_GPIO_ABUSALLOC_AODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_VDAC0CH0 (_GPIO_ABUSALLOC_AODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_SHIFT 24 /**< Shift value for GPIO_AODD1 */ -#define _GPIO_ABUSALLOC_AODD1_MASK 0xF000000UL /**< Bit mask for GPIO_AODD1 */ -#define _GPIO_ABUSALLOC_AODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_DEFAULT (_GPIO_ABUSALLOC_AODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_TRISTATE (_GPIO_ABUSALLOC_AODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_ADC0 (_GPIO_ABUSALLOC_AODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_ACMP0 (_GPIO_ABUSALLOC_AODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_ACMP1 (_GPIO_ABUSALLOC_AODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_VDAC0CH1 (_GPIO_ABUSALLOC_AODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_SHIFT 0 /**< Shift value for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_MASK 0xFUL /**< Bit mask for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_DEFAULT (_GPIO_ABUSALLOC_AEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_TRISTATE (_GPIO_ABUSALLOC_AEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ADC0 (_GPIO_ABUSALLOC_AEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ACMP0 (_GPIO_ABUSALLOC_AEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ACMP1 (_GPIO_ABUSALLOC_AEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 (_GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_SHIFT 8 /**< Shift value for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_DEFAULT (_GPIO_ABUSALLOC_AEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_TRISTATE (_GPIO_ABUSALLOC_AEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ADC0 (_GPIO_ABUSALLOC_AEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ACMP0 (_GPIO_ABUSALLOC_AEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ACMP1 (_GPIO_ABUSALLOC_AEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 (_GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_SHIFT 16 /**< Shift value for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_MASK 0xF0000UL /**< Bit mask for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_DEFAULT (_GPIO_ABUSALLOC_AODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_TRISTATE (_GPIO_ABUSALLOC_AODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ADC0 (_GPIO_ABUSALLOC_AODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ACMP0 (_GPIO_ABUSALLOC_AODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ACMP1 (_GPIO_ABUSALLOC_AODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_VDAC0CH0 (_GPIO_ABUSALLOC_AODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_SHIFT 24 /**< Shift value for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_MASK 0xF000000UL /**< Bit mask for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_DEFAULT (_GPIO_ABUSALLOC_AODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_TRISTATE (_GPIO_ABUSALLOC_AODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ADC0 (_GPIO_ABUSALLOC_AODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ACMP0 (_GPIO_ABUSALLOC_AODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ACMP1 (_GPIO_ABUSALLOC_AODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_VDAC0CH1 (_GPIO_ABUSALLOC_AODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ /* Bit fields for GPIO BBUSALLOC */ -#define _GPIO_BBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_SHIFT 0 /**< Shift value for GPIO_BEVEN0 */ -#define _GPIO_BBUSALLOC_BEVEN0_MASK 0xFUL /**< Bit mask for GPIO_BEVEN0 */ -#define _GPIO_BBUSALLOC_BEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_DEFAULT (_GPIO_BBUSALLOC_BEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_TRISTATE (_GPIO_BBUSALLOC_BEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_ADC0 (_GPIO_BBUSALLOC_BEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_ACMP0 (_GPIO_BBUSALLOC_BEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_ACMP1 (_GPIO_BBUSALLOC_BEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 (_GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_SHIFT 8 /**< Shift value for GPIO_BEVEN1 */ -#define _GPIO_BBUSALLOC_BEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_BEVEN1 */ -#define _GPIO_BBUSALLOC_BEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_DEFAULT (_GPIO_BBUSALLOC_BEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_TRISTATE (_GPIO_BBUSALLOC_BEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_ADC0 (_GPIO_BBUSALLOC_BEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_ACMP0 (_GPIO_BBUSALLOC_BEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_ACMP1 (_GPIO_BBUSALLOC_BEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 (_GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_SHIFT 16 /**< Shift value for GPIO_BODD0 */ -#define _GPIO_BBUSALLOC_BODD0_MASK 0xF0000UL /**< Bit mask for GPIO_BODD0 */ -#define _GPIO_BBUSALLOC_BODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_DEFAULT (_GPIO_BBUSALLOC_BODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_TRISTATE (_GPIO_BBUSALLOC_BODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_ADC0 (_GPIO_BBUSALLOC_BODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_ACMP0 (_GPIO_BBUSALLOC_BODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_ACMP1 (_GPIO_BBUSALLOC_BODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_VDAC0CH0 (_GPIO_BBUSALLOC_BODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_SHIFT 24 /**< Shift value for GPIO_BODD1 */ -#define _GPIO_BBUSALLOC_BODD1_MASK 0xF000000UL /**< Bit mask for GPIO_BODD1 */ -#define _GPIO_BBUSALLOC_BODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_DEFAULT (_GPIO_BBUSALLOC_BODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_TRISTATE (_GPIO_BBUSALLOC_BODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_ADC0 (_GPIO_BBUSALLOC_BODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_ACMP0 (_GPIO_BBUSALLOC_BODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_ACMP1 (_GPIO_BBUSALLOC_BODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_VDAC0CH1 (_GPIO_BBUSALLOC_BODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_SHIFT 0 /**< Shift value for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_MASK 0xFUL /**< Bit mask for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_DEFAULT (_GPIO_BBUSALLOC_BEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_TRISTATE (_GPIO_BBUSALLOC_BEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ADC0 (_GPIO_BBUSALLOC_BEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ACMP0 (_GPIO_BBUSALLOC_BEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ACMP1 (_GPIO_BBUSALLOC_BEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 (_GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_SHIFT 8 /**< Shift value for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_DEFAULT (_GPIO_BBUSALLOC_BEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_TRISTATE (_GPIO_BBUSALLOC_BEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ADC0 (_GPIO_BBUSALLOC_BEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ACMP0 (_GPIO_BBUSALLOC_BEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ACMP1 (_GPIO_BBUSALLOC_BEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 (_GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_SHIFT 16 /**< Shift value for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_MASK 0xF0000UL /**< Bit mask for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_DEFAULT (_GPIO_BBUSALLOC_BODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_TRISTATE (_GPIO_BBUSALLOC_BODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ADC0 (_GPIO_BBUSALLOC_BODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ACMP0 (_GPIO_BBUSALLOC_BODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ACMP1 (_GPIO_BBUSALLOC_BODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_VDAC0CH0 (_GPIO_BBUSALLOC_BODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_SHIFT 24 /**< Shift value for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_MASK 0xF000000UL /**< Bit mask for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_DEFAULT (_GPIO_BBUSALLOC_BODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_TRISTATE (_GPIO_BBUSALLOC_BODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ADC0 (_GPIO_BBUSALLOC_BODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ACMP0 (_GPIO_BBUSALLOC_BODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ACMP1 (_GPIO_BBUSALLOC_BODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_VDAC0CH1 (_GPIO_BBUSALLOC_BODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ /* Bit fields for GPIO CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_SHIFT 0 /**< Shift value for GPIO_CDEVEN0 */ -#define _GPIO_CDBUSALLOC_CDEVEN0_MASK 0xFUL /**< Bit mask for GPIO_CDEVEN0 */ -#define _GPIO_CDBUSALLOC_CDEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_ADC0 (_GPIO_CDBUSALLOC_CDEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_SHIFT 8 /**< Shift value for GPIO_CDEVEN1 */ -#define _GPIO_CDBUSALLOC_CDEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_CDEVEN1 */ -#define _GPIO_CDBUSALLOC_CDEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_ADC0 (_GPIO_CDBUSALLOC_CDEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_SHIFT 16 /**< Shift value for GPIO_CDODD0 */ -#define _GPIO_CDBUSALLOC_CDODD0_MASK 0xF0000UL /**< Bit mask for GPIO_CDODD0 */ -#define _GPIO_CDBUSALLOC_CDODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_DEFAULT (_GPIO_CDBUSALLOC_CDODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_TRISTATE (_GPIO_CDBUSALLOC_CDODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_ADC0 (_GPIO_CDBUSALLOC_CDODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_ACMP0 (_GPIO_CDBUSALLOC_CDODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_ACMP1 (_GPIO_CDBUSALLOC_CDODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_SHIFT 24 /**< Shift value for GPIO_CDODD1 */ -#define _GPIO_CDBUSALLOC_CDODD1_MASK 0xF000000UL /**< Bit mask for GPIO_CDODD1 */ -#define _GPIO_CDBUSALLOC_CDODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_DEFAULT (_GPIO_CDBUSALLOC_CDODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_TRISTATE (_GPIO_CDBUSALLOC_CDODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_ADC0 (_GPIO_CDBUSALLOC_CDODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_ACMP0 (_GPIO_CDBUSALLOC_CDODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_ACMP1 (_GPIO_CDBUSALLOC_CDODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_SHIFT 0 /**< Shift value for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_MASK 0xFUL /**< Bit mask for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ADC0 (_GPIO_CDBUSALLOC_CDEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_SHIFT 8 /**< Shift value for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ADC0 (_GPIO_CDBUSALLOC_CDEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_SHIFT 16 /**< Shift value for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_MASK 0xF0000UL /**< Bit mask for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_DEFAULT (_GPIO_CDBUSALLOC_CDODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_TRISTATE (_GPIO_CDBUSALLOC_CDODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ADC0 (_GPIO_CDBUSALLOC_CDODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ACMP0 (_GPIO_CDBUSALLOC_CDODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ACMP1 (_GPIO_CDBUSALLOC_CDODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_SHIFT 24 /**< Shift value for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_MASK 0xF000000UL /**< Bit mask for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_DEFAULT (_GPIO_CDBUSALLOC_CDODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_TRISTATE (_GPIO_CDBUSALLOC_CDODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ADC0 (_GPIO_CDBUSALLOC_CDODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ACMP0 (_GPIO_CDBUSALLOC_CDODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ACMP1 (_GPIO_CDBUSALLOC_CDODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ /* Bit fields for GPIO EXTIPSELL */ -#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPSEL4 */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPSEL5 */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ /* Bit fields for GPIO EXTIPSELH */ -#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_PORTA (_GPIO_EXTIPSELH_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_PORTB (_GPIO_EXTIPSELH_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_PORTC (_GPIO_EXTIPSELH_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_PORTD (_GPIO_EXTIPSELH_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_PORTA (_GPIO_EXTIPSELH_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_PORTB (_GPIO_EXTIPSELH_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_PORTC (_GPIO_EXTIPSELH_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_PORTD (_GPIO_EXTIPSELH_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_PORTA (_GPIO_EXTIPSELH_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_PORTB (_GPIO_EXTIPSELH_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_PORTC (_GPIO_EXTIPSELH_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_PORTD (_GPIO_EXTIPSELH_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_PORTA (_GPIO_EXTIPSELH_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_PORTB (_GPIO_EXTIPSELH_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_PORTC (_GPIO_EXTIPSELH_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_PORTD (_GPIO_EXTIPSELH_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTA (_GPIO_EXTIPSELH_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTB (_GPIO_EXTIPSELH_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTC (_GPIO_EXTIPSELH_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTD (_GPIO_EXTIPSELH_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTA (_GPIO_EXTIPSELH_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTB (_GPIO_EXTIPSELH_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTC (_GPIO_EXTIPSELH_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTD (_GPIO_EXTIPSELH_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTA (_GPIO_EXTIPSELH_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTB (_GPIO_EXTIPSELH_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTC (_GPIO_EXTIPSELH_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTD (_GPIO_EXTIPSELH_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTA (_GPIO_EXTIPSELH_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTB (_GPIO_EXTIPSELH_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTC (_GPIO_EXTIPSELH_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTD (_GPIO_EXTIPSELH_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ /* Bit fields for GPIO EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 << 16) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 << 16) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 << 16) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 << 16) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 << 20) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 << 20) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 << 20) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 << 20) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 << 24) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 << 24) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 << 24) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 << 24) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 << 28) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 << 28) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 << 28) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 << 28) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 << 16) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 << 16) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 << 16) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 << 16) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 << 20) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 << 20) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 << 20) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 << 20) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 << 24) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 << 24) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 << 24) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 << 24) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 << 28) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 << 28) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 << 28) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 << 28) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ /* Bit fields for GPIO EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ /* Bit fields for GPIO EXTIRISE */ -#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ -#define _GPIO_EXTIRISE_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIRISE */ -#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ -#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIRISE */ -#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ -#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ +#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ /* Bit fields for GPIO EXTIFALL */ -#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ -#define _GPIO_EXTIFALL_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIFALL */ -#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ -#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIFALL */ -#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ -#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ +#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ /* Bit fields for GPIO IF */ -#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ -#define _GPIO_IF_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IF */ -#define GPIO_IF_EXTIF0 (0x1UL << 0) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF0_SHIFT 0 /**< Shift value for GPIO_EXTIF0 */ -#define _GPIO_IF_EXTIF0_MASK 0x1UL /**< Bit mask for GPIO_EXTIF0 */ -#define _GPIO_IF_EXTIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF0_DEFAULT (_GPIO_IF_EXTIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF1 (0x1UL << 1) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF1_SHIFT 1 /**< Shift value for GPIO_EXTIF1 */ -#define _GPIO_IF_EXTIF1_MASK 0x2UL /**< Bit mask for GPIO_EXTIF1 */ -#define _GPIO_IF_EXTIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF1_DEFAULT (_GPIO_IF_EXTIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF2 (0x1UL << 2) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF2_SHIFT 2 /**< Shift value for GPIO_EXTIF2 */ -#define _GPIO_IF_EXTIF2_MASK 0x4UL /**< Bit mask for GPIO_EXTIF2 */ -#define _GPIO_IF_EXTIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF2_DEFAULT (_GPIO_IF_EXTIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF3 (0x1UL << 3) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF3_SHIFT 3 /**< Shift value for GPIO_EXTIF3 */ -#define _GPIO_IF_EXTIF3_MASK 0x8UL /**< Bit mask for GPIO_EXTIF3 */ -#define _GPIO_IF_EXTIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF3_DEFAULT (_GPIO_IF_EXTIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF4 (0x1UL << 4) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF4_SHIFT 4 /**< Shift value for GPIO_EXTIF4 */ -#define _GPIO_IF_EXTIF4_MASK 0x10UL /**< Bit mask for GPIO_EXTIF4 */ -#define _GPIO_IF_EXTIF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF4_DEFAULT (_GPIO_IF_EXTIF4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF5 (0x1UL << 5) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF5_SHIFT 5 /**< Shift value for GPIO_EXTIF5 */ -#define _GPIO_IF_EXTIF5_MASK 0x20UL /**< Bit mask for GPIO_EXTIF5 */ -#define _GPIO_IF_EXTIF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF5_DEFAULT (_GPIO_IF_EXTIF5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF6 (0x1UL << 6) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF6_SHIFT 6 /**< Shift value for GPIO_EXTIF6 */ -#define _GPIO_IF_EXTIF6_MASK 0x40UL /**< Bit mask for GPIO_EXTIF6 */ -#define _GPIO_IF_EXTIF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF6_DEFAULT (_GPIO_IF_EXTIF6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF7 (0x1UL << 7) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF7_SHIFT 7 /**< Shift value for GPIO_EXTIF7 */ -#define _GPIO_IF_EXTIF7_MASK 0x80UL /**< Bit mask for GPIO_EXTIF7 */ -#define _GPIO_IF_EXTIF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF7_DEFAULT (_GPIO_IF_EXTIF7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF8 (0x1UL << 8) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF8_SHIFT 8 /**< Shift value for GPIO_EXTIF8 */ -#define _GPIO_IF_EXTIF8_MASK 0x100UL /**< Bit mask for GPIO_EXTIF8 */ -#define _GPIO_IF_EXTIF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF8_DEFAULT (_GPIO_IF_EXTIF8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF9 (0x1UL << 9) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF9_SHIFT 9 /**< Shift value for GPIO_EXTIF9 */ -#define _GPIO_IF_EXTIF9_MASK 0x200UL /**< Bit mask for GPIO_EXTIF9 */ -#define _GPIO_IF_EXTIF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF9_DEFAULT (_GPIO_IF_EXTIF9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF10 (0x1UL << 10) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF10_SHIFT 10 /**< Shift value for GPIO_EXTIF10 */ -#define _GPIO_IF_EXTIF10_MASK 0x400UL /**< Bit mask for GPIO_EXTIF10 */ -#define _GPIO_IF_EXTIF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF10_DEFAULT (_GPIO_IF_EXTIF10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF11 (0x1UL << 11) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF11_SHIFT 11 /**< Shift value for GPIO_EXTIF11 */ -#define _GPIO_IF_EXTIF11_MASK 0x800UL /**< Bit mask for GPIO_EXTIF11 */ -#define _GPIO_IF_EXTIF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF11_DEFAULT (_GPIO_IF_EXTIF11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IF */ -#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ -#define _GPIO_IF_EM4WU_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WU */ -#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ +#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ +#define _GPIO_IF_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IF */ +#define GPIO_IF_EXTIF0 (0x1UL << 0) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF0_SHIFT 0 /**< Shift value for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_MASK 0x1UL /**< Bit mask for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF0_DEFAULT (_GPIO_IF_EXTIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1 (0x1UL << 1) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF1_SHIFT 1 /**< Shift value for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_MASK 0x2UL /**< Bit mask for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1_DEFAULT (_GPIO_IF_EXTIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2 (0x1UL << 2) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF2_SHIFT 2 /**< Shift value for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_MASK 0x4UL /**< Bit mask for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2_DEFAULT (_GPIO_IF_EXTIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3 (0x1UL << 3) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF3_SHIFT 3 /**< Shift value for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_MASK 0x8UL /**< Bit mask for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3_DEFAULT (_GPIO_IF_EXTIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4 (0x1UL << 4) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF4_SHIFT 4 /**< Shift value for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_MASK 0x10UL /**< Bit mask for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4_DEFAULT (_GPIO_IF_EXTIF4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5 (0x1UL << 5) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF5_SHIFT 5 /**< Shift value for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_MASK 0x20UL /**< Bit mask for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5_DEFAULT (_GPIO_IF_EXTIF5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6 (0x1UL << 6) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF6_SHIFT 6 /**< Shift value for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_MASK 0x40UL /**< Bit mask for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6_DEFAULT (_GPIO_IF_EXTIF6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7 (0x1UL << 7) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF7_SHIFT 7 /**< Shift value for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_MASK 0x80UL /**< Bit mask for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7_DEFAULT (_GPIO_IF_EXTIF7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8 (0x1UL << 8) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF8_SHIFT 8 /**< Shift value for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_MASK 0x100UL /**< Bit mask for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8_DEFAULT (_GPIO_IF_EXTIF8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9 (0x1UL << 9) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF9_SHIFT 9 /**< Shift value for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_MASK 0x200UL /**< Bit mask for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9_DEFAULT (_GPIO_IF_EXTIF9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10 (0x1UL << 10) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF10_SHIFT 10 /**< Shift value for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_MASK 0x400UL /**< Bit mask for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10_DEFAULT (_GPIO_IF_EXTIF10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11 (0x1UL << 11) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF11_SHIFT 11 /**< Shift value for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_MASK 0x800UL /**< Bit mask for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11_DEFAULT (_GPIO_IF_EXTIF11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IF */ +#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ /* Bit fields for GPIO IEN */ -#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ -#define _GPIO_IEN_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IEN */ -#define GPIO_IEN_EXTIEN0 (0x1UL << 0) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN0_SHIFT 0 /**< Shift value for GPIO_EXTIEN0 */ -#define _GPIO_IEN_EXTIEN0_MASK 0x1UL /**< Bit mask for GPIO_EXTIEN0 */ -#define _GPIO_IEN_EXTIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN0_DEFAULT (_GPIO_IEN_EXTIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN1 (0x1UL << 1) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN1_SHIFT 1 /**< Shift value for GPIO_EXTIEN1 */ -#define _GPIO_IEN_EXTIEN1_MASK 0x2UL /**< Bit mask for GPIO_EXTIEN1 */ -#define _GPIO_IEN_EXTIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN1_DEFAULT (_GPIO_IEN_EXTIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN2 (0x1UL << 2) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN2_SHIFT 2 /**< Shift value for GPIO_EXTIEN2 */ -#define _GPIO_IEN_EXTIEN2_MASK 0x4UL /**< Bit mask for GPIO_EXTIEN2 */ -#define _GPIO_IEN_EXTIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN2_DEFAULT (_GPIO_IEN_EXTIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN3 (0x1UL << 3) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN3_SHIFT 3 /**< Shift value for GPIO_EXTIEN3 */ -#define _GPIO_IEN_EXTIEN3_MASK 0x8UL /**< Bit mask for GPIO_EXTIEN3 */ -#define _GPIO_IEN_EXTIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN3_DEFAULT (_GPIO_IEN_EXTIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN4 (0x1UL << 4) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN4_SHIFT 4 /**< Shift value for GPIO_EXTIEN4 */ -#define _GPIO_IEN_EXTIEN4_MASK 0x10UL /**< Bit mask for GPIO_EXTIEN4 */ -#define _GPIO_IEN_EXTIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN4_DEFAULT (_GPIO_IEN_EXTIEN4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN5 (0x1UL << 5) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN5_SHIFT 5 /**< Shift value for GPIO_EXTIEN5 */ -#define _GPIO_IEN_EXTIEN5_MASK 0x20UL /**< Bit mask for GPIO_EXTIEN5 */ -#define _GPIO_IEN_EXTIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN5_DEFAULT (_GPIO_IEN_EXTIEN5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN6 (0x1UL << 6) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN6_SHIFT 6 /**< Shift value for GPIO_EXTIEN6 */ -#define _GPIO_IEN_EXTIEN6_MASK 0x40UL /**< Bit mask for GPIO_EXTIEN6 */ -#define _GPIO_IEN_EXTIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN6_DEFAULT (_GPIO_IEN_EXTIEN6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN7 (0x1UL << 7) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN7_SHIFT 7 /**< Shift value for GPIO_EXTIEN7 */ -#define _GPIO_IEN_EXTIEN7_MASK 0x80UL /**< Bit mask for GPIO_EXTIEN7 */ -#define _GPIO_IEN_EXTIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN7_DEFAULT (_GPIO_IEN_EXTIEN7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN8 (0x1UL << 8) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN8_SHIFT 8 /**< Shift value for GPIO_EXTIEN8 */ -#define _GPIO_IEN_EXTIEN8_MASK 0x100UL /**< Bit mask for GPIO_EXTIEN8 */ -#define _GPIO_IEN_EXTIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN8_DEFAULT (_GPIO_IEN_EXTIEN8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN9 (0x1UL << 9) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN9_SHIFT 9 /**< Shift value for GPIO_EXTIEN9 */ -#define _GPIO_IEN_EXTIEN9_MASK 0x200UL /**< Bit mask for GPIO_EXTIEN9 */ -#define _GPIO_IEN_EXTIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN9_DEFAULT (_GPIO_IEN_EXTIEN9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN10 (0x1UL << 10) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN10_SHIFT 10 /**< Shift value for GPIO_EXTIEN10 */ -#define _GPIO_IEN_EXTIEN10_MASK 0x400UL /**< Bit mask for GPIO_EXTIEN10 */ -#define _GPIO_IEN_EXTIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN10_DEFAULT (_GPIO_IEN_EXTIEN10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN11 (0x1UL << 11) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN11_SHIFT 11 /**< Shift value for GPIO_EXTIEN11 */ -#define _GPIO_IEN_EXTIEN11_MASK 0x800UL /**< Bit mask for GPIO_EXTIEN11 */ -#define _GPIO_IEN_EXTIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN11_DEFAULT (_GPIO_IEN_EXTIEN11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN0 (0x1UL << 16) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN0_SHIFT 16 /**< Shift value for GPIO_EM4WUIEN0 */ -#define _GPIO_IEN_EM4WUIEN0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WUIEN0 */ -#define _GPIO_IEN_EM4WUIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN0_DEFAULT (_GPIO_IEN_EM4WUIEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN1 (0x1UL << 17) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN1_SHIFT 17 /**< Shift value for GPIO_EM4WUIEN1 */ -#define _GPIO_IEN_EM4WUIEN1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WUIEN1 */ -#define _GPIO_IEN_EM4WUIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN1_DEFAULT (_GPIO_IEN_EM4WUIEN1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN2 (0x1UL << 18) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN2_SHIFT 18 /**< Shift value for GPIO_EM4WUIEN2 */ -#define _GPIO_IEN_EM4WUIEN2_MASK 0x40000UL /**< Bit mask for GPIO_EM4WUIEN2 */ -#define _GPIO_IEN_EM4WUIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN2_DEFAULT (_GPIO_IEN_EM4WUIEN2_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN3 (0x1UL << 19) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN3_SHIFT 19 /**< Shift value for GPIO_EM4WUIEN3 */ -#define _GPIO_IEN_EM4WUIEN3_MASK 0x80000UL /**< Bit mask for GPIO_EM4WUIEN3 */ -#define _GPIO_IEN_EM4WUIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN3_DEFAULT (_GPIO_IEN_EM4WUIEN3_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN4 (0x1UL << 20) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN4_SHIFT 20 /**< Shift value for GPIO_EM4WUIEN4 */ -#define _GPIO_IEN_EM4WUIEN4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WUIEN4 */ -#define _GPIO_IEN_EM4WUIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN4_DEFAULT (_GPIO_IEN_EM4WUIEN4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN5 (0x1UL << 21) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN5_SHIFT 21 /**< Shift value for GPIO_EM4WUIEN5 */ -#define _GPIO_IEN_EM4WUIEN5_MASK 0x200000UL /**< Bit mask for GPIO_EM4WUIEN5 */ -#define _GPIO_IEN_EM4WUIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN5_DEFAULT (_GPIO_IEN_EM4WUIEN5_DEFAULT << 21) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN6 (0x1UL << 22) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN6_SHIFT 22 /**< Shift value for GPIO_EM4WUIEN6 */ -#define _GPIO_IEN_EM4WUIEN6_MASK 0x400000UL /**< Bit mask for GPIO_EM4WUIEN6 */ -#define _GPIO_IEN_EM4WUIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN6_DEFAULT (_GPIO_IEN_EM4WUIEN6_DEFAULT << 22) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN7 (0x1UL << 23) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN7_SHIFT 23 /**< Shift value for GPIO_EM4WUIEN7 */ -#define _GPIO_IEN_EM4WUIEN7_MASK 0x800000UL /**< Bit mask for GPIO_EM4WUIEN7 */ -#define _GPIO_IEN_EM4WUIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN7_DEFAULT (_GPIO_IEN_EM4WUIEN7_DEFAULT << 23) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN8 (0x1UL << 24) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN8_SHIFT 24 /**< Shift value for GPIO_EM4WUIEN8 */ -#define _GPIO_IEN_EM4WUIEN8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WUIEN8 */ -#define _GPIO_IEN_EM4WUIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN8_DEFAULT (_GPIO_IEN_EM4WUIEN8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN9 (0x1UL << 25) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN9_SHIFT 25 /**< Shift value for GPIO_EM4WUIEN9 */ -#define _GPIO_IEN_EM4WUIEN9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WUIEN9 */ -#define _GPIO_IEN_EM4WUIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN9_DEFAULT (_GPIO_IEN_EM4WUIEN9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN10 (0x1UL << 26) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN10_SHIFT 26 /**< Shift value for GPIO_EM4WUIEN10 */ -#define _GPIO_IEN_EM4WUIEN10_MASK 0x4000000UL /**< Bit mask for GPIO_EM4WUIEN10 */ -#define _GPIO_IEN_EM4WUIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN10_DEFAULT (_GPIO_IEN_EM4WUIEN10_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN11 (0x1UL << 27) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN11_SHIFT 27 /**< Shift value for GPIO_EM4WUIEN11 */ -#define _GPIO_IEN_EM4WUIEN11_MASK 0x8000000UL /**< Bit mask for GPIO_EM4WUIEN11 */ -#define _GPIO_IEN_EM4WUIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN11_DEFAULT (_GPIO_IEN_EM4WUIEN11_DEFAULT << 27) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ +#define _GPIO_IEN_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0 (0x1UL << 0) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN0_SHIFT 0 /**< Shift value for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_MASK 0x1UL /**< Bit mask for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0_DEFAULT (_GPIO_IEN_EXTIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1 (0x1UL << 1) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN1_SHIFT 1 /**< Shift value for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_MASK 0x2UL /**< Bit mask for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1_DEFAULT (_GPIO_IEN_EXTIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2 (0x1UL << 2) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN2_SHIFT 2 /**< Shift value for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_MASK 0x4UL /**< Bit mask for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2_DEFAULT (_GPIO_IEN_EXTIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3 (0x1UL << 3) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN3_SHIFT 3 /**< Shift value for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_MASK 0x8UL /**< Bit mask for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3_DEFAULT (_GPIO_IEN_EXTIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4 (0x1UL << 4) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN4_SHIFT 4 /**< Shift value for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_MASK 0x10UL /**< Bit mask for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4_DEFAULT (_GPIO_IEN_EXTIEN4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5 (0x1UL << 5) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN5_SHIFT 5 /**< Shift value for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_MASK 0x20UL /**< Bit mask for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5_DEFAULT (_GPIO_IEN_EXTIEN5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6 (0x1UL << 6) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN6_SHIFT 6 /**< Shift value for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_MASK 0x40UL /**< Bit mask for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6_DEFAULT (_GPIO_IEN_EXTIEN6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7 (0x1UL << 7) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN7_SHIFT 7 /**< Shift value for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_MASK 0x80UL /**< Bit mask for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7_DEFAULT (_GPIO_IEN_EXTIEN7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8 (0x1UL << 8) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN8_SHIFT 8 /**< Shift value for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_MASK 0x100UL /**< Bit mask for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8_DEFAULT (_GPIO_IEN_EXTIEN8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9 (0x1UL << 9) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN9_SHIFT 9 /**< Shift value for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_MASK 0x200UL /**< Bit mask for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9_DEFAULT (_GPIO_IEN_EXTIEN9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10 (0x1UL << 10) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN10_SHIFT 10 /**< Shift value for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_MASK 0x400UL /**< Bit mask for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10_DEFAULT (_GPIO_IEN_EXTIEN10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11 (0x1UL << 11) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN11_SHIFT 11 /**< Shift value for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_MASK 0x800UL /**< Bit mask for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11_DEFAULT (_GPIO_IEN_EXTIEN11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0 (0x1UL << 16) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN0_SHIFT 16 /**< Shift value for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0_DEFAULT (_GPIO_IEN_EM4WUIEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1 (0x1UL << 17) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN1_SHIFT 17 /**< Shift value for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1_DEFAULT (_GPIO_IEN_EM4WUIEN1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2 (0x1UL << 18) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN2_SHIFT 18 /**< Shift value for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_MASK 0x40000UL /**< Bit mask for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2_DEFAULT (_GPIO_IEN_EM4WUIEN2_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3 (0x1UL << 19) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN3_SHIFT 19 /**< Shift value for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_MASK 0x80000UL /**< Bit mask for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3_DEFAULT (_GPIO_IEN_EM4WUIEN3_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4 (0x1UL << 20) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN4_SHIFT 20 /**< Shift value for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4_DEFAULT (_GPIO_IEN_EM4WUIEN4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5 (0x1UL << 21) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN5_SHIFT 21 /**< Shift value for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_MASK 0x200000UL /**< Bit mask for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5_DEFAULT (_GPIO_IEN_EM4WUIEN5_DEFAULT << 21) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6 (0x1UL << 22) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN6_SHIFT 22 /**< Shift value for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_MASK 0x400000UL /**< Bit mask for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6_DEFAULT (_GPIO_IEN_EM4WUIEN6_DEFAULT << 22) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7 (0x1UL << 23) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN7_SHIFT 23 /**< Shift value for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_MASK 0x800000UL /**< Bit mask for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7_DEFAULT (_GPIO_IEN_EM4WUIEN7_DEFAULT << 23) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8 (0x1UL << 24) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN8_SHIFT 24 /**< Shift value for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8_DEFAULT (_GPIO_IEN_EM4WUIEN8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9 (0x1UL << 25) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN9_SHIFT 25 /**< Shift value for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9_DEFAULT (_GPIO_IEN_EM4WUIEN9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10 (0x1UL << 26) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN10_SHIFT 26 /**< Shift value for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_MASK 0x4000000UL /**< Bit mask for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10_DEFAULT (_GPIO_IEN_EM4WUIEN10_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11 (0x1UL << 27) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN11_SHIFT 27 /**< Shift value for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_MASK 0x8000000UL /**< Bit mask for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11_DEFAULT (_GPIO_IEN_EM4WUIEN11_DEFAULT << 27) /**< Shifted mode DEFAULT for GPIO_IEN */ /* Bit fields for GPIO EM4WUEN */ -#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ -#define _GPIO_EM4WUEN_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUEN */ -#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ -#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ -#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ -#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ +#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ /* Bit fields for GPIO EM4WUPOL */ -#define _GPIO_EM4WUPOL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUPOL */ -#define _GPIO_EM4WUPOL_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUPOL */ -#define _GPIO_EM4WUPOL_EM4WUPOL_SHIFT 16 /**< Shift value for GPIO_EM4WUPOL */ -#define _GPIO_EM4WUPOL_EM4WUPOL_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUPOL */ -#define _GPIO_EM4WUPOL_EM4WUPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUPOL */ -#define GPIO_EM4WUPOL_EM4WUPOL_DEFAULT (_GPIO_EM4WUPOL_EM4WUPOL_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_SHIFT 16 /**< Shift value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUPOL */ +#define GPIO_EM4WUPOL_EM4WUPOL_DEFAULT (_GPIO_EM4WUPOL_EM4WUPOL_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUPOL */ /* Bit fields for GPIO DBGROUTEPEN */ -#define _GPIO_DBGROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_DBGROUTEPEN */ -#define _GPIO_DBGROUTEPEN_MASK 0x0000000FUL /**< Mask for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Route Pin Enable */ -#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ -#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ -#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Route Location 0 */ -#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ -#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ -#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ -#define _GPIO_DBGROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ -#define _GPIO_DBGROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ -#define _GPIO_DBGROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_TDOPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ -#define _GPIO_DBGROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ -#define _GPIO_DBGROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ -#define _GPIO_DBGROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_TDIPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_MASK 0x0000000FUL /**< Mask for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Route Pin Enable */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Route Location 0 */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ /* Bit fields for GPIO TRACEROUTEPEN */ -#define _GPIO_TRACEROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TRACEROUTEPEN */ -#define _GPIO_TRACEROUTEPEN_MASK 0x0000003FUL /**< Mask for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_SWVPEN (0x1UL << 0) /**< Serial Wire Viewer Output Pin Enable */ -#define _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT 0 /**< Shift value for GPIO_SWVPEN */ -#define _GPIO_TRACEROUTEPEN_SWVPEN_MASK 0x1UL /**< Bit mask for GPIO_SWVPEN */ -#define _GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT (_GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACECLKPEN (0x1UL << 1) /**< Trace Clk Pin Enable */ -#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_SHIFT 1 /**< Shift value for GPIO_TRACECLKPEN */ -#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_MASK 0x2UL /**< Bit mask for GPIO_TRACECLKPEN */ -#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN (0x1UL << 2) /**< Trace Data0 Pin Enable */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_SHIFT 2 /**< Shift value for GPIO_TRACEDATA0PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_MASK 0x4UL /**< Bit mask for GPIO_TRACEDATA0PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN (0x1UL << 3) /**< Trace Data1 Pin Enable */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_SHIFT 3 /**< Shift value for GPIO_TRACEDATA1PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_MASK 0x8UL /**< Bit mask for GPIO_TRACEDATA1PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN (0x1UL << 4) /**< Trace Data2 Pin Enable */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_SHIFT 4 /**< Shift value for GPIO_TRACEDATA2PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_MASK 0x10UL /**< Bit mask for GPIO_TRACEDATA2PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN (0x1UL << 5) /**< Trace Data3 Pin Enable */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_SHIFT 5 /**< Shift value for GPIO_TRACEDATA3PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_MASK 0x20UL /**< Bit mask for GPIO_TRACEDATA3PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_MASK 0x0000003FUL /**< Mask for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN (0x1UL << 0) /**< Serial Wire Viewer Output Pin Enable */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT 0 /**< Shift value for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_MASK 0x1UL /**< Bit mask for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT (_GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN (0x1UL << 1) /**< Trace Clk Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_SHIFT 1 /**< Shift value for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_MASK 0x2UL /**< Bit mask for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN (0x1UL << 2) /**< Trace Data0 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_SHIFT 2 /**< Shift value for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_MASK 0x4UL /**< Bit mask for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN (0x1UL << 3) /**< Trace Data1 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_SHIFT 3 /**< Shift value for GPIO_TRACEDATA1PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_MASK 0x8UL /**< Bit mask for GPIO_TRACEDATA1PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN (0x1UL << 4) /**< Trace Data2 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_SHIFT 4 /**< Shift value for GPIO_TRACEDATA2PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_MASK 0x10UL /**< Bit mask for GPIO_TRACEDATA2PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN (0x1UL << 5) /**< Trace Data3 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_SHIFT 5 /**< Shift value for GPIO_TRACEDATA3PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_MASK 0x20UL /**< Bit mask for GPIO_TRACEDATA3PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ /* Bit fields for GPIO LCDSEG */ -#define _GPIO_LCDSEG_RESETVALUE 0x00000000UL /**< Default value for GPIO_LCDSEG */ -#define _GPIO_LCDSEG_MASK 0x000FFFFFUL /**< Mask for GPIO_LCDSEG */ -#define _GPIO_LCDSEG_LCDSEGALLOC_SHIFT 0 /**< Shift value for GPIO_LCDSEGALLOC */ -#define _GPIO_LCDSEG_LCDSEGALLOC_MASK 0xFFFFFUL /**< Bit mask for GPIO_LCDSEGALLOC */ -#define _GPIO_LCDSEG_LCDSEGALLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LCDSEG */ -#define GPIO_LCDSEG_LCDSEGALLOC_DEFAULT (_GPIO_LCDSEG_LCDSEGALLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LCDSEG */ +#define _GPIO_LCDSEG_RESETVALUE 0x00000000UL /**< Default value for GPIO_LCDSEG */ +#define _GPIO_LCDSEG_MASK 0x000FFFFFUL /**< Mask for GPIO_LCDSEG */ +#define _GPIO_LCDSEG_LCDSEGALLOC_SHIFT 0 /**< Shift value for GPIO_LCDSEGALLOC */ +#define _GPIO_LCDSEG_LCDSEGALLOC_MASK 0xFFFFFUL /**< Bit mask for GPIO_LCDSEGALLOC */ +#define _GPIO_LCDSEG_LCDSEGALLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LCDSEG */ +#define GPIO_LCDSEG_LCDSEGALLOC_DEFAULT (_GPIO_LCDSEG_LCDSEGALLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LCDSEG */ /* Bit fields for GPIO LCDCOM */ -#define _GPIO_LCDCOM_RESETVALUE 0x00000000UL /**< Default value for GPIO_LCDCOM */ -#define _GPIO_LCDCOM_MASK 0x0000000FUL /**< Mask for GPIO_LCDCOM */ -#define _GPIO_LCDCOM_LCDCOMALLOC_SHIFT 0 /**< Shift value for GPIO_LCDCOMALLOC */ -#define _GPIO_LCDCOM_LCDCOMALLOC_MASK 0xFUL /**< Bit mask for GPIO_LCDCOMALLOC */ -#define _GPIO_LCDCOM_LCDCOMALLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LCDCOM */ -#define GPIO_LCDCOM_LCDCOMALLOC_DEFAULT (_GPIO_LCDCOM_LCDCOMALLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LCDCOM */ +#define _GPIO_LCDCOM_RESETVALUE 0x00000000UL /**< Default value for GPIO_LCDCOM */ +#define _GPIO_LCDCOM_MASK 0x0000000FUL /**< Mask for GPIO_LCDCOM */ +#define _GPIO_LCDCOM_LCDCOMALLOC_SHIFT 0 /**< Shift value for GPIO_LCDCOMALLOC */ +#define _GPIO_LCDCOM_LCDCOMALLOC_MASK 0xFUL /**< Bit mask for GPIO_LCDCOMALLOC */ +#define _GPIO_LCDCOM_LCDCOMALLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LCDCOM */ +#define GPIO_LCDCOM_LCDCOMALLOC_DEFAULT (_GPIO_LCDCOM_LCDCOMALLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LCDCOM */ /* Bit fields for GPIO_ACMP ROUTEEN */ -#define _GPIO_ACMP_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ROUTEEN */ -#define _GPIO_ACMP_ROUTEEN_MASK 0x00000001UL /**< Mask for GPIO_ACMP_ROUTEEN */ -#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN (0x1UL << 0) /**< ACMPOUT pin enable control bit */ -#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_SHIFT 0 /**< Shift value for GPIO_ACMPOUTPEN */ -#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_MASK 0x1UL /**< Bit mask for GPIO_ACMPOUTPEN */ -#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ROUTEEN */ -#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT (_GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ROUTEEN */ +#define _GPIO_ACMP_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ROUTEEN */ +#define _GPIO_ACMP_ROUTEEN_MASK 0x00000001UL /**< Mask for GPIO_ACMP_ROUTEEN */ +#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN (0x1UL << 0) /**< ACMPOUT pin enable control bit */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_SHIFT 0 /**< Shift value for GPIO_ACMPOUTPEN */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_MASK 0x1UL /**< Bit mask for GPIO_ACMPOUTPEN */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ROUTEEN */ +#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT (_GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ROUTEEN */ /* Bit fields for GPIO_ACMP ACMPOUTROUTE */ -#define _GPIO_ACMP_ACMPOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ACMPOUTROUTE */ -#define _GPIO_ACMP_ACMPOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_ACMP_ACMPOUTROUTE */ -#define _GPIO_ACMP_ACMPOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_ACMP_ACMPOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ -#define GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ -#define _GPIO_ACMP_ACMPOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_ACMP_ACMPOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ -#define GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ +#define _GPIO_ACMP_ACMPOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_ACMP_ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ +#define GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ +#define GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ /* Bit fields for GPIO_CMU ROUTEEN */ -#define _GPIO_CMU_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_ROUTEEN */ -#define _GPIO_CMU_ROUTEEN_MASK 0x0000000FUL /**< Mask for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 pin enable control bit */ -#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for GPIO_CLKOUT0PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_CLKOUT0PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 pin enable control bit */ -#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for GPIO_CLKOUT1PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_CLKOUT1PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 pin enable control bit */ -#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for GPIO_CLKOUT2PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_CLKOUT2PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_MASK 0x0000000FUL /**< Mask for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ /* Bit fields for GPIO_CMU CLKIN0ROUTE */ -#define _GPIO_CMU_CLKIN0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKIN0ROUTE */ -#define _GPIO_CMU_CLKIN0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKIN0ROUTE */ -#define _GPIO_CMU_CLKIN0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_CMU_CLKIN0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ -#define GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ -#define _GPIO_CMU_CLKIN0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_CMU_CLKIN0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ -#define GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ +#define _GPIO_CMU_CLKIN0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ /* Bit fields for GPIO_CMU CLKOUT0ROUTE */ -#define _GPIO_CMU_CLKOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT0ROUTE */ -#define _GPIO_CMU_CLKOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT0ROUTE */ -#define _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ -#define GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ -#define _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ -#define GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ +#define _GPIO_CMU_CLKOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ /* Bit fields for GPIO_CMU CLKOUT1ROUTE */ -#define _GPIO_CMU_CLKOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT1ROUTE */ -#define _GPIO_CMU_CLKOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT1ROUTE */ -#define _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ -#define GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ -#define _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ -#define GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ +#define _GPIO_CMU_CLKOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ /* Bit fields for GPIO_CMU CLKOUT2ROUTE */ -#define _GPIO_CMU_CLKOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT2ROUTE */ -#define _GPIO_CMU_CLKOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT2ROUTE */ -#define _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ -#define GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ -#define _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ -#define GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ +#define _GPIO_CMU_CLKOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ /* Bit fields for GPIO_EUSART ROUTEEN */ -#define _GPIO_EUSART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_ROUTEEN */ -#define _GPIO_EUSART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ -#define _GPIO_EUSART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ -#define _GPIO_EUSART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ -#define _GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ -#define GPIO_EUSART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ -#define _GPIO_EUSART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ -#define _GPIO_EUSART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ -#define _GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ -#define GPIO_EUSART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ -#define _GPIO_EUSART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ -#define _GPIO_EUSART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ -#define _GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ -#define GPIO_EUSART_ROUTEEN_SCLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ -#define _GPIO_EUSART_ROUTEEN_SCLKPEN_SHIFT 3 /**< Shift value for GPIO_SCLKPEN */ -#define _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK 0x8UL /**< Bit mask for GPIO_SCLKPEN */ -#define _GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ -#define GPIO_EUSART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ -#define _GPIO_EUSART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ -#define _GPIO_EUSART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ -#define _GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define _GPIO_EUSART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_ROUTEEN */ +#define _GPIO_EUSART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_SCLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_SHIFT 3 /**< Shift value for GPIO_SCLKPEN */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK 0x8UL /**< Bit mask for GPIO_SCLKPEN */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ /* Bit fields for GPIO_EUSART CSROUTE */ -#define _GPIO_EUSART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CSROUTE */ -#define _GPIO_EUSART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CSROUTE */ -#define _GPIO_EUSART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ -#define GPIO_EUSART_CSROUTE_PORT_DEFAULT (_GPIO_EUSART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ -#define _GPIO_EUSART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ -#define GPIO_EUSART_CSROUTE_PIN_DEFAULT (_GPIO_EUSART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ +#define _GPIO_EUSART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CSROUTE */ +#define _GPIO_EUSART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CSROUTE */ +#define _GPIO_EUSART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ +#define GPIO_EUSART_CSROUTE_PORT_DEFAULT (_GPIO_EUSART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ +#define _GPIO_EUSART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ +#define GPIO_EUSART_CSROUTE_PIN_DEFAULT (_GPIO_EUSART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ /* Bit fields for GPIO_EUSART CTSROUTE */ -#define _GPIO_EUSART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CTSROUTE */ -#define _GPIO_EUSART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CTSROUTE */ -#define _GPIO_EUSART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ -#define GPIO_EUSART_CTSROUTE_PORT_DEFAULT (_GPIO_EUSART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ -#define _GPIO_EUSART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ -#define GPIO_EUSART_CTSROUTE_PIN_DEFAULT (_GPIO_EUSART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ +#define _GPIO_EUSART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ +#define GPIO_EUSART_CTSROUTE_PORT_DEFAULT (_GPIO_EUSART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ +#define _GPIO_EUSART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ +#define GPIO_EUSART_CTSROUTE_PIN_DEFAULT (_GPIO_EUSART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ /* Bit fields for GPIO_EUSART RTSROUTE */ -#define _GPIO_EUSART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RTSROUTE */ -#define _GPIO_EUSART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RTSROUTE */ -#define _GPIO_EUSART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ -#define GPIO_EUSART_RTSROUTE_PORT_DEFAULT (_GPIO_EUSART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ -#define _GPIO_EUSART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ -#define GPIO_EUSART_RTSROUTE_PIN_DEFAULT (_GPIO_EUSART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ +#define _GPIO_EUSART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ +#define GPIO_EUSART_RTSROUTE_PORT_DEFAULT (_GPIO_EUSART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ +#define _GPIO_EUSART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ +#define GPIO_EUSART_RTSROUTE_PIN_DEFAULT (_GPIO_EUSART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ /* Bit fields for GPIO_EUSART RXROUTE */ -#define _GPIO_EUSART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RXROUTE */ -#define _GPIO_EUSART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RXROUTE */ -#define _GPIO_EUSART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ -#define GPIO_EUSART_RXROUTE_PORT_DEFAULT (_GPIO_EUSART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ -#define _GPIO_EUSART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ -#define GPIO_EUSART_RXROUTE_PIN_DEFAULT (_GPIO_EUSART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ +#define _GPIO_EUSART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RXROUTE */ +#define _GPIO_EUSART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RXROUTE */ +#define _GPIO_EUSART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ +#define GPIO_EUSART_RXROUTE_PORT_DEFAULT (_GPIO_EUSART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ +#define _GPIO_EUSART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ +#define GPIO_EUSART_RXROUTE_PIN_DEFAULT (_GPIO_EUSART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ /* Bit fields for GPIO_EUSART SCLKROUTE */ -#define _GPIO_EUSART_SCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_SCLKROUTE */ -#define _GPIO_EUSART_SCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_SCLKROUTE */ -#define _GPIO_EUSART_SCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_SCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_SCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ -#define GPIO_EUSART_SCLKROUTE_PORT_DEFAULT (_GPIO_EUSART_SCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ -#define _GPIO_EUSART_SCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_SCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_SCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ -#define GPIO_EUSART_SCLKROUTE_PIN_DEFAULT (_GPIO_EUSART_SCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ +#define _GPIO_EUSART_SCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_SCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_SCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ +#define GPIO_EUSART_SCLKROUTE_PORT_DEFAULT (_GPIO_EUSART_SCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ +#define _GPIO_EUSART_SCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_SCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_SCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ +#define GPIO_EUSART_SCLKROUTE_PIN_DEFAULT (_GPIO_EUSART_SCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ /* Bit fields for GPIO_EUSART TXROUTE */ -#define _GPIO_EUSART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_TXROUTE */ -#define _GPIO_EUSART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_TXROUTE */ -#define _GPIO_EUSART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ -#define GPIO_EUSART_TXROUTE_PORT_DEFAULT (_GPIO_EUSART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ -#define _GPIO_EUSART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ -#define GPIO_EUSART_TXROUTE_PIN_DEFAULT (_GPIO_EUSART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ +#define _GPIO_EUSART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_TXROUTE */ +#define _GPIO_EUSART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_TXROUTE */ +#define _GPIO_EUSART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ +#define GPIO_EUSART_TXROUTE_PORT_DEFAULT (_GPIO_EUSART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ +#define _GPIO_EUSART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ +#define GPIO_EUSART_TXROUTE_PIN_DEFAULT (_GPIO_EUSART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ /* Bit fields for GPIO_FRC ROUTEEN */ -#define _GPIO_FRC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_ROUTEEN */ -#define _GPIO_FRC_ROUTEEN_MASK 0x00000007UL /**< Mask for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DCLKPEN (0x1UL << 0) /**< DCLK pin enable control bit */ -#define _GPIO_FRC_ROUTEEN_DCLKPEN_SHIFT 0 /**< Shift value for GPIO_DCLKPEN */ -#define _GPIO_FRC_ROUTEEN_DCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_DCLKPEN */ -#define _GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DFRAMEPEN (0x1UL << 1) /**< DFRAME pin enable control bit */ -#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_SHIFT 1 /**< Shift value for GPIO_DFRAMEPEN */ -#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_MASK 0x2UL /**< Bit mask for GPIO_DFRAMEPEN */ -#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DOUTPEN (0x1UL << 2) /**< DOUT pin enable control bit */ -#define _GPIO_FRC_ROUTEEN_DOUTPEN_SHIFT 2 /**< Shift value for GPIO_DOUTPEN */ -#define _GPIO_FRC_ROUTEEN_DOUTPEN_MASK 0x4UL /**< Bit mask for GPIO_DOUTPEN */ -#define _GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_MASK 0x00000007UL /**< Mask for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN (0x1UL << 0) /**< DCLK pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_SHIFT 0 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN (0x1UL << 1) /**< DFRAME pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_SHIFT 1 /**< Shift value for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_MASK 0x2UL /**< Bit mask for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN (0x1UL << 2) /**< DOUT pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_SHIFT 2 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_MASK 0x4UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ /* Bit fields for GPIO_FRC DCLKROUTE */ -#define _GPIO_FRC_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DCLKROUTE */ -#define _GPIO_FRC_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DCLKROUTE */ -#define _GPIO_FRC_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_FRC_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_FRC_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ -#define GPIO_FRC_DCLKROUTE_PORT_DEFAULT (_GPIO_FRC_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ -#define _GPIO_FRC_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_FRC_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_FRC_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ -#define GPIO_FRC_DCLKROUTE_PIN_DEFAULT (_GPIO_FRC_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PORT_DEFAULT (_GPIO_FRC_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PIN_DEFAULT (_GPIO_FRC_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ /* Bit fields for GPIO_FRC DFRAMEROUTE */ -#define _GPIO_FRC_DFRAMEROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DFRAMEROUTE */ -#define _GPIO_FRC_DFRAMEROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DFRAMEROUTE */ -#define _GPIO_FRC_DFRAMEROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_FRC_DFRAMEROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ -#define GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ -#define _GPIO_FRC_DFRAMEROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_FRC_DFRAMEROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ -#define GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ +#define _GPIO_FRC_DFRAMEROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ +#define _GPIO_FRC_DFRAMEROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ /* Bit fields for GPIO_FRC DOUTROUTE */ -#define _GPIO_FRC_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DOUTROUTE */ -#define _GPIO_FRC_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DOUTROUTE */ -#define _GPIO_FRC_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_FRC_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_FRC_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ -#define GPIO_FRC_DOUTROUTE_PORT_DEFAULT (_GPIO_FRC_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ -#define _GPIO_FRC_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_FRC_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_FRC_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ -#define GPIO_FRC_DOUTROUTE_PIN_DEFAULT (_GPIO_FRC_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PORT_DEFAULT (_GPIO_FRC_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PIN_DEFAULT (_GPIO_FRC_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ /* Bit fields for GPIO_I2C ROUTEEN */ -#define _GPIO_I2C_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_ROUTEEN */ -#define _GPIO_I2C_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_I2C_ROUTEEN */ -#define GPIO_I2C_ROUTEEN_SCLPEN (0x1UL << 0) /**< SCL pin enable control bit */ -#define _GPIO_I2C_ROUTEEN_SCLPEN_SHIFT 0 /**< Shift value for GPIO_SCLPEN */ -#define _GPIO_I2C_ROUTEEN_SCLPEN_MASK 0x1UL /**< Bit mask for GPIO_SCLPEN */ -#define _GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ -#define GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ -#define GPIO_I2C_ROUTEEN_SDAPEN (0x1UL << 1) /**< SDA pin enable control bit */ -#define _GPIO_I2C_ROUTEEN_SDAPEN_SHIFT 1 /**< Shift value for GPIO_SDAPEN */ -#define _GPIO_I2C_ROUTEEN_SDAPEN_MASK 0x2UL /**< Bit mask for GPIO_SDAPEN */ -#define _GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ -#define GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN (0x1UL << 0) /**< SCL pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_SHIFT 0 /**< Shift value for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_MASK 0x1UL /**< Bit mask for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN (0x1UL << 1) /**< SDA pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_SHIFT 1 /**< Shift value for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_MASK 0x2UL /**< Bit mask for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ /* Bit fields for GPIO_I2C SCLROUTE */ -#define _GPIO_I2C_SCLROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SCLROUTE */ -#define _GPIO_I2C_SCLROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SCLROUTE */ -#define _GPIO_I2C_SCLROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_I2C_SCLROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_I2C_SCLROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ -#define GPIO_I2C_SCLROUTE_PORT_DEFAULT (_GPIO_I2C_SCLROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ -#define _GPIO_I2C_SCLROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_I2C_SCLROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_I2C_SCLROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ -#define GPIO_I2C_SCLROUTE_PIN_DEFAULT (_GPIO_I2C_SCLROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PORT_DEFAULT (_GPIO_I2C_SCLROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PIN_DEFAULT (_GPIO_I2C_SCLROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ /* Bit fields for GPIO_I2C SDAROUTE */ -#define _GPIO_I2C_SDAROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SDAROUTE */ -#define _GPIO_I2C_SDAROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SDAROUTE */ -#define _GPIO_I2C_SDAROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_I2C_SDAROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_I2C_SDAROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ -#define GPIO_I2C_SDAROUTE_PORT_DEFAULT (_GPIO_I2C_SDAROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ -#define _GPIO_I2C_SDAROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_I2C_SDAROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_I2C_SDAROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ -#define GPIO_I2C_SDAROUTE_PIN_DEFAULT (_GPIO_I2C_SDAROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PORT_DEFAULT (_GPIO_I2C_SDAROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PIN_DEFAULT (_GPIO_I2C_SDAROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ /* Bit fields for GPIO_KEYSCAN ROUTEEN */ -#define _GPIO_KEYSCAN_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROUTEEN */ -#define _GPIO_KEYSCAN_ROUTEEN_MASK 0x000000FFUL /**< Mask for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN (0x1UL << 0) /**< COLOUT0 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_SHIFT 0 /**< Shift value for GPIO_COLOUT0PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_COLOUT0PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN (0x1UL << 1) /**< COLOUT1 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_SHIFT 1 /**< Shift value for GPIO_COLOUT1PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_COLOUT1PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN (0x1UL << 2) /**< COLOUT2 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_SHIFT 2 /**< Shift value for GPIO_COLOUT2PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_COLOUT2PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN (0x1UL << 3) /**< COLOUT3 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_SHIFT 3 /**< Shift value for GPIO_COLOUT3PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_MASK 0x8UL /**< Bit mask for GPIO_COLOUT3PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN (0x1UL << 4) /**< COLOUT4 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_SHIFT 4 /**< Shift value for GPIO_COLOUT4PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_MASK 0x10UL /**< Bit mask for GPIO_COLOUT4PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN (0x1UL << 5) /**< COLOUT5 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_SHIFT 5 /**< Shift value for GPIO_COLOUT5PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_MASK 0x20UL /**< Bit mask for GPIO_COLOUT5PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN (0x1UL << 6) /**< COLOUT6 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_SHIFT 6 /**< Shift value for GPIO_COLOUT6PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_MASK 0x40UL /**< Bit mask for GPIO_COLOUT6PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN (0x1UL << 7) /**< COLOUT7 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_SHIFT 7 /**< Shift value for GPIO_COLOUT7PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_MASK 0x80UL /**< Bit mask for GPIO_COLOUT7PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define _GPIO_KEYSCAN_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROUTEEN */ +#define _GPIO_KEYSCAN_ROUTEEN_MASK 0x000000FFUL /**< Mask for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN (0x1UL << 0) /**< COLOUT0 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_SHIFT 0 /**< Shift value for GPIO_COLOUT0PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_COLOUT0PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN (0x1UL << 1) /**< COLOUT1 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_SHIFT 1 /**< Shift value for GPIO_COLOUT1PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_COLOUT1PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN (0x1UL << 2) /**< COLOUT2 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_SHIFT 2 /**< Shift value for GPIO_COLOUT2PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_COLOUT2PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN (0x1UL << 3) /**< COLOUT3 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_SHIFT 3 /**< Shift value for GPIO_COLOUT3PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_MASK 0x8UL /**< Bit mask for GPIO_COLOUT3PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN (0x1UL << 4) /**< COLOUT4 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_SHIFT 4 /**< Shift value for GPIO_COLOUT4PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_MASK 0x10UL /**< Bit mask for GPIO_COLOUT4PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN (0x1UL << 5) /**< COLOUT5 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_SHIFT 5 /**< Shift value for GPIO_COLOUT5PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_MASK 0x20UL /**< Bit mask for GPIO_COLOUT5PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN (0x1UL << 6) /**< COLOUT6 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_SHIFT 6 /**< Shift value for GPIO_COLOUT6PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_MASK 0x40UL /**< Bit mask for GPIO_COLOUT6PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN (0x1UL << 7) /**< COLOUT7 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_SHIFT 7 /**< Shift value for GPIO_COLOUT7PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_MASK 0x80UL /**< Bit mask for GPIO_COLOUT7PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ /* Bit fields for GPIO_KEYSCAN COLOUT0ROUTE */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT0ROUTE */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT0ROUTE */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ -#define GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ -#define GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ /* Bit fields for GPIO_KEYSCAN COLOUT1ROUTE */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT1ROUTE */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT1ROUTE */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ -#define GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ -#define GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ /* Bit fields for GPIO_KEYSCAN COLOUT2ROUTE */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT2ROUTE */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT2ROUTE */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ -#define GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ -#define GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ /* Bit fields for GPIO_KEYSCAN COLOUT3ROUTE */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT3ROUTE */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT3ROUTE */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ -#define GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ -#define GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ /* Bit fields for GPIO_KEYSCAN COLOUT4ROUTE */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT4ROUTE */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT4ROUTE */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ -#define GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ -#define GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ /* Bit fields for GPIO_KEYSCAN COLOUT5ROUTE */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT5ROUTE */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT5ROUTE */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ -#define GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ -#define GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ /* Bit fields for GPIO_KEYSCAN COLOUT6ROUTE */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT6ROUTE */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT6ROUTE */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ -#define GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ -#define GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ /* Bit fields for GPIO_KEYSCAN COLOUT7ROUTE */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT7ROUTE */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT7ROUTE */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ -#define GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ -#define GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ /* Bit fields for GPIO_KEYSCAN ROWSENSE0ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE0ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE0ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ /* Bit fields for GPIO_KEYSCAN ROWSENSE1ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE1ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE1ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ /* Bit fields for GPIO_KEYSCAN ROWSENSE2ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE2ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE2ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ /* Bit fields for GPIO_KEYSCAN ROWSENSE3ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE3ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE3ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ /* Bit fields for GPIO_KEYSCAN ROWSENSE4ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE4ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE4ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ /* Bit fields for GPIO_KEYSCAN ROWSENSE5ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE5ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE5ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ /* Bit fields for GPIO_LESENSE ROUTEEN */ -#define _GPIO_LESENSE_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_ROUTEEN */ -#define _GPIO_LESENSE_ROUTEEN_MASK 0x0000FFFFUL /**< Mask for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH0OUTPEN (0x1UL << 0) /**< CH0OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH0OUTPEN_SHIFT 0 /**< Shift value for GPIO_CH0OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH0OUTPEN_MASK 0x1UL /**< Bit mask for GPIO_CH0OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH0OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH0OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH0OUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH1OUTPEN (0x1UL << 1) /**< CH1OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH1OUTPEN_SHIFT 1 /**< Shift value for GPIO_CH1OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH1OUTPEN_MASK 0x2UL /**< Bit mask for GPIO_CH1OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH1OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH1OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH1OUTPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH2OUTPEN (0x1UL << 2) /**< CH2OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH2OUTPEN_SHIFT 2 /**< Shift value for GPIO_CH2OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH2OUTPEN_MASK 0x4UL /**< Bit mask for GPIO_CH2OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH2OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH2OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH2OUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH3OUTPEN (0x1UL << 3) /**< CH3OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH3OUTPEN_SHIFT 3 /**< Shift value for GPIO_CH3OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH3OUTPEN_MASK 0x8UL /**< Bit mask for GPIO_CH3OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH3OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH3OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH3OUTPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH4OUTPEN (0x1UL << 4) /**< CH4OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH4OUTPEN_SHIFT 4 /**< Shift value for GPIO_CH4OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH4OUTPEN_MASK 0x10UL /**< Bit mask for GPIO_CH4OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH4OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH4OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH4OUTPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH5OUTPEN (0x1UL << 5) /**< CH5OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH5OUTPEN_SHIFT 5 /**< Shift value for GPIO_CH5OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH5OUTPEN_MASK 0x20UL /**< Bit mask for GPIO_CH5OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH5OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH5OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH5OUTPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH6OUTPEN (0x1UL << 6) /**< CH6OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH6OUTPEN_SHIFT 6 /**< Shift value for GPIO_CH6OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH6OUTPEN_MASK 0x40UL /**< Bit mask for GPIO_CH6OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH6OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH6OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH6OUTPEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH7OUTPEN (0x1UL << 7) /**< CH7OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH7OUTPEN_SHIFT 7 /**< Shift value for GPIO_CH7OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH7OUTPEN_MASK 0x80UL /**< Bit mask for GPIO_CH7OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH7OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH7OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH7OUTPEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH8OUTPEN (0x1UL << 8) /**< CH8OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH8OUTPEN_SHIFT 8 /**< Shift value for GPIO_CH8OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH8OUTPEN_MASK 0x100UL /**< Bit mask for GPIO_CH8OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH8OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH8OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH8OUTPEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH9OUTPEN (0x1UL << 9) /**< CH9OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH9OUTPEN_SHIFT 9 /**< Shift value for GPIO_CH9OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH9OUTPEN_MASK 0x200UL /**< Bit mask for GPIO_CH9OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH9OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH9OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH9OUTPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH10OUTPEN (0x1UL << 10) /**< CH10OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH10OUTPEN_SHIFT 10 /**< Shift value for GPIO_CH10OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH10OUTPEN_MASK 0x400UL /**< Bit mask for GPIO_CH10OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH10OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH10OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH10OUTPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH11OUTPEN (0x1UL << 11) /**< CH11OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH11OUTPEN_SHIFT 11 /**< Shift value for GPIO_CH11OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH11OUTPEN_MASK 0x800UL /**< Bit mask for GPIO_CH11OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH11OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH11OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH11OUTPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH12OUTPEN (0x1UL << 12) /**< CH12OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH12OUTPEN_SHIFT 12 /**< Shift value for GPIO_CH12OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH12OUTPEN_MASK 0x1000UL /**< Bit mask for GPIO_CH12OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH12OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH12OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH12OUTPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH13OUTPEN (0x1UL << 13) /**< CH13OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH13OUTPEN_SHIFT 13 /**< Shift value for GPIO_CH13OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH13OUTPEN_MASK 0x2000UL /**< Bit mask for GPIO_CH13OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH13OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH13OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH13OUTPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH14OUTPEN (0x1UL << 14) /**< CH14OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH14OUTPEN_SHIFT 14 /**< Shift value for GPIO_CH14OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH14OUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_CH14OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH14OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH14OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH14OUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH15OUTPEN (0x1UL << 15) /**< CH15OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH15OUTPEN_SHIFT 15 /**< Shift value for GPIO_CH15OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH15OUTPEN_MASK 0x8000UL /**< Bit mask for GPIO_CH15OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH15OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH15OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH15OUTPEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define _GPIO_LESENSE_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_ROUTEEN */ +#define _GPIO_LESENSE_ROUTEEN_MASK 0x0000FFFFUL /**< Mask for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH0OUTPEN (0x1UL << 0) /**< CH0OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH0OUTPEN_SHIFT 0 /**< Shift value for GPIO_CH0OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH0OUTPEN_MASK 0x1UL /**< Bit mask for GPIO_CH0OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH0OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH0OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH0OUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH1OUTPEN (0x1UL << 1) /**< CH1OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH1OUTPEN_SHIFT 1 /**< Shift value for GPIO_CH1OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH1OUTPEN_MASK 0x2UL /**< Bit mask for GPIO_CH1OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH1OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH1OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH1OUTPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH2OUTPEN (0x1UL << 2) /**< CH2OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH2OUTPEN_SHIFT 2 /**< Shift value for GPIO_CH2OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH2OUTPEN_MASK 0x4UL /**< Bit mask for GPIO_CH2OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH2OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH2OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH2OUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH3OUTPEN (0x1UL << 3) /**< CH3OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH3OUTPEN_SHIFT 3 /**< Shift value for GPIO_CH3OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH3OUTPEN_MASK 0x8UL /**< Bit mask for GPIO_CH3OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH3OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH3OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH3OUTPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH4OUTPEN (0x1UL << 4) /**< CH4OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH4OUTPEN_SHIFT 4 /**< Shift value for GPIO_CH4OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH4OUTPEN_MASK 0x10UL /**< Bit mask for GPIO_CH4OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH4OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH4OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH4OUTPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH5OUTPEN (0x1UL << 5) /**< CH5OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH5OUTPEN_SHIFT 5 /**< Shift value for GPIO_CH5OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH5OUTPEN_MASK 0x20UL /**< Bit mask for GPIO_CH5OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH5OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH5OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH5OUTPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH6OUTPEN (0x1UL << 6) /**< CH6OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH6OUTPEN_SHIFT 6 /**< Shift value for GPIO_CH6OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH6OUTPEN_MASK 0x40UL /**< Bit mask for GPIO_CH6OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH6OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH6OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH6OUTPEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH7OUTPEN (0x1UL << 7) /**< CH7OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH7OUTPEN_SHIFT 7 /**< Shift value for GPIO_CH7OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH7OUTPEN_MASK 0x80UL /**< Bit mask for GPIO_CH7OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH7OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH7OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH7OUTPEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH8OUTPEN (0x1UL << 8) /**< CH8OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH8OUTPEN_SHIFT 8 /**< Shift value for GPIO_CH8OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH8OUTPEN_MASK 0x100UL /**< Bit mask for GPIO_CH8OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH8OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH8OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH8OUTPEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH9OUTPEN (0x1UL << 9) /**< CH9OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH9OUTPEN_SHIFT 9 /**< Shift value for GPIO_CH9OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH9OUTPEN_MASK 0x200UL /**< Bit mask for GPIO_CH9OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH9OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH9OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH9OUTPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH10OUTPEN (0x1UL << 10) /**< CH10OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH10OUTPEN_SHIFT 10 /**< Shift value for GPIO_CH10OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH10OUTPEN_MASK 0x400UL /**< Bit mask for GPIO_CH10OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH10OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH10OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH10OUTPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH11OUTPEN (0x1UL << 11) /**< CH11OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH11OUTPEN_SHIFT 11 /**< Shift value for GPIO_CH11OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH11OUTPEN_MASK 0x800UL /**< Bit mask for GPIO_CH11OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH11OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH11OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH11OUTPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH12OUTPEN (0x1UL << 12) /**< CH12OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH12OUTPEN_SHIFT 12 /**< Shift value for GPIO_CH12OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH12OUTPEN_MASK 0x1000UL /**< Bit mask for GPIO_CH12OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH12OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH12OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH12OUTPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH13OUTPEN (0x1UL << 13) /**< CH13OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH13OUTPEN_SHIFT 13 /**< Shift value for GPIO_CH13OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH13OUTPEN_MASK 0x2000UL /**< Bit mask for GPIO_CH13OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH13OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH13OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH13OUTPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH14OUTPEN (0x1UL << 14) /**< CH14OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH14OUTPEN_SHIFT 14 /**< Shift value for GPIO_CH14OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH14OUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_CH14OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH14OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH14OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH14OUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH15OUTPEN (0x1UL << 15) /**< CH15OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH15OUTPEN_SHIFT 15 /**< Shift value for GPIO_CH15OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH15OUTPEN_MASK 0x8000UL /**< Bit mask for GPIO_CH15OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH15OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH15OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH15OUTPEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ /* Bit fields for GPIO_LESENSE CH0OUTROUTE */ -#define _GPIO_LESENSE_CH0OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH0OUTROUTE */ -#define _GPIO_LESENSE_CH0OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH0OUTROUTE */ -#define _GPIO_LESENSE_CH0OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH0OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH0OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE */ -#define GPIO_LESENSE_CH0OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH0OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE*/ -#define _GPIO_LESENSE_CH0OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH0OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH0OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE */ -#define GPIO_LESENSE_CH0OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH0OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE*/ +#define _GPIO_LESENSE_CH0OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH0OUTROUTE */ +#define _GPIO_LESENSE_CH0OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH0OUTROUTE */ +#define _GPIO_LESENSE_CH0OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH0OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH0OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE */ +#define GPIO_LESENSE_CH0OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH0OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE*/ +#define _GPIO_LESENSE_CH0OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH0OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH0OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE */ +#define GPIO_LESENSE_CH0OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH0OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH1OUTROUTE */ -#define _GPIO_LESENSE_CH1OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH1OUTROUTE */ -#define _GPIO_LESENSE_CH1OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH1OUTROUTE */ -#define _GPIO_LESENSE_CH1OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH1OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH1OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE */ -#define GPIO_LESENSE_CH1OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH1OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE*/ -#define _GPIO_LESENSE_CH1OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH1OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH1OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE */ -#define GPIO_LESENSE_CH1OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH1OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE*/ +#define _GPIO_LESENSE_CH1OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH1OUTROUTE */ +#define _GPIO_LESENSE_CH1OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH1OUTROUTE */ +#define _GPIO_LESENSE_CH1OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH1OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH1OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE */ +#define GPIO_LESENSE_CH1OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH1OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE*/ +#define _GPIO_LESENSE_CH1OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH1OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH1OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE */ +#define GPIO_LESENSE_CH1OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH1OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH2OUTROUTE */ -#define _GPIO_LESENSE_CH2OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH2OUTROUTE */ -#define _GPIO_LESENSE_CH2OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH2OUTROUTE */ -#define _GPIO_LESENSE_CH2OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH2OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH2OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE */ -#define GPIO_LESENSE_CH2OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH2OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE*/ -#define _GPIO_LESENSE_CH2OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH2OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH2OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE */ -#define GPIO_LESENSE_CH2OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH2OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE*/ +#define _GPIO_LESENSE_CH2OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH2OUTROUTE */ +#define _GPIO_LESENSE_CH2OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH2OUTROUTE */ +#define _GPIO_LESENSE_CH2OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH2OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH2OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE */ +#define GPIO_LESENSE_CH2OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH2OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE*/ +#define _GPIO_LESENSE_CH2OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH2OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH2OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE */ +#define GPIO_LESENSE_CH2OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH2OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH3OUTROUTE */ -#define _GPIO_LESENSE_CH3OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH3OUTROUTE */ -#define _GPIO_LESENSE_CH3OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH3OUTROUTE */ -#define _GPIO_LESENSE_CH3OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH3OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH3OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE */ -#define GPIO_LESENSE_CH3OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH3OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE*/ -#define _GPIO_LESENSE_CH3OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH3OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH3OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE */ -#define GPIO_LESENSE_CH3OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH3OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE*/ +#define _GPIO_LESENSE_CH3OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH3OUTROUTE */ +#define _GPIO_LESENSE_CH3OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH3OUTROUTE */ +#define _GPIO_LESENSE_CH3OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH3OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH3OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE */ +#define GPIO_LESENSE_CH3OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH3OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE*/ +#define _GPIO_LESENSE_CH3OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH3OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH3OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE */ +#define GPIO_LESENSE_CH3OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH3OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH4OUTROUTE */ -#define _GPIO_LESENSE_CH4OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH4OUTROUTE */ -#define _GPIO_LESENSE_CH4OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH4OUTROUTE */ -#define _GPIO_LESENSE_CH4OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH4OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH4OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE */ -#define GPIO_LESENSE_CH4OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH4OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE*/ -#define _GPIO_LESENSE_CH4OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH4OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH4OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE */ -#define GPIO_LESENSE_CH4OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH4OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE*/ +#define _GPIO_LESENSE_CH4OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH4OUTROUTE */ +#define _GPIO_LESENSE_CH4OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH4OUTROUTE */ +#define _GPIO_LESENSE_CH4OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH4OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH4OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE */ +#define GPIO_LESENSE_CH4OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH4OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE*/ +#define _GPIO_LESENSE_CH4OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH4OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH4OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE */ +#define GPIO_LESENSE_CH4OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH4OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH5OUTROUTE */ -#define _GPIO_LESENSE_CH5OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH5OUTROUTE */ -#define _GPIO_LESENSE_CH5OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH5OUTROUTE */ -#define _GPIO_LESENSE_CH5OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH5OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH5OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE */ -#define GPIO_LESENSE_CH5OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH5OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE*/ -#define _GPIO_LESENSE_CH5OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH5OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH5OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE */ -#define GPIO_LESENSE_CH5OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH5OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE*/ +#define _GPIO_LESENSE_CH5OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH5OUTROUTE */ +#define _GPIO_LESENSE_CH5OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH5OUTROUTE */ +#define _GPIO_LESENSE_CH5OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH5OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH5OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE */ +#define GPIO_LESENSE_CH5OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH5OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE*/ +#define _GPIO_LESENSE_CH5OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH5OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH5OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE */ +#define GPIO_LESENSE_CH5OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH5OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH6OUTROUTE */ -#define _GPIO_LESENSE_CH6OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH6OUTROUTE */ -#define _GPIO_LESENSE_CH6OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH6OUTROUTE */ -#define _GPIO_LESENSE_CH6OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH6OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH6OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE */ -#define GPIO_LESENSE_CH6OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH6OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE*/ -#define _GPIO_LESENSE_CH6OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH6OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH6OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE */ -#define GPIO_LESENSE_CH6OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH6OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE*/ +#define _GPIO_LESENSE_CH6OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH6OUTROUTE */ +#define _GPIO_LESENSE_CH6OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH6OUTROUTE */ +#define _GPIO_LESENSE_CH6OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH6OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH6OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE */ +#define GPIO_LESENSE_CH6OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH6OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE*/ +#define _GPIO_LESENSE_CH6OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH6OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH6OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE */ +#define GPIO_LESENSE_CH6OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH6OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH7OUTROUTE */ -#define _GPIO_LESENSE_CH7OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH7OUTROUTE */ -#define _GPIO_LESENSE_CH7OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH7OUTROUTE */ -#define _GPIO_LESENSE_CH7OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH7OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH7OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE */ -#define GPIO_LESENSE_CH7OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH7OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE*/ -#define _GPIO_LESENSE_CH7OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH7OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH7OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE */ -#define GPIO_LESENSE_CH7OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH7OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE*/ +#define _GPIO_LESENSE_CH7OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH7OUTROUTE */ +#define _GPIO_LESENSE_CH7OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH7OUTROUTE */ +#define _GPIO_LESENSE_CH7OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH7OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH7OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE */ +#define GPIO_LESENSE_CH7OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH7OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE*/ +#define _GPIO_LESENSE_CH7OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH7OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH7OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE */ +#define GPIO_LESENSE_CH7OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH7OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH8OUTROUTE */ -#define _GPIO_LESENSE_CH8OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH8OUTROUTE */ -#define _GPIO_LESENSE_CH8OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH8OUTROUTE */ -#define _GPIO_LESENSE_CH8OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH8OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH8OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE */ -#define GPIO_LESENSE_CH8OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH8OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE*/ -#define _GPIO_LESENSE_CH8OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH8OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH8OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE */ -#define GPIO_LESENSE_CH8OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH8OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE*/ +#define _GPIO_LESENSE_CH8OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH8OUTROUTE */ +#define _GPIO_LESENSE_CH8OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH8OUTROUTE */ +#define _GPIO_LESENSE_CH8OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH8OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH8OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE */ +#define GPIO_LESENSE_CH8OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH8OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE*/ +#define _GPIO_LESENSE_CH8OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH8OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH8OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE */ +#define GPIO_LESENSE_CH8OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH8OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH9OUTROUTE */ -#define _GPIO_LESENSE_CH9OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH9OUTROUTE */ -#define _GPIO_LESENSE_CH9OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH9OUTROUTE */ -#define _GPIO_LESENSE_CH9OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH9OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH9OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE */ -#define GPIO_LESENSE_CH9OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH9OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE*/ -#define _GPIO_LESENSE_CH9OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH9OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH9OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE */ -#define GPIO_LESENSE_CH9OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH9OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE*/ +#define _GPIO_LESENSE_CH9OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH9OUTROUTE */ +#define _GPIO_LESENSE_CH9OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH9OUTROUTE */ +#define _GPIO_LESENSE_CH9OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH9OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH9OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE */ +#define GPIO_LESENSE_CH9OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH9OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE*/ +#define _GPIO_LESENSE_CH9OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH9OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH9OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE */ +#define GPIO_LESENSE_CH9OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH9OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH10OUTROUTE */ -#define _GPIO_LESENSE_CH10OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH10OUTROUTE */ -#define _GPIO_LESENSE_CH10OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH10OUTROUTE */ -#define _GPIO_LESENSE_CH10OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH10OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH10OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE */ -#define GPIO_LESENSE_CH10OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH10OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE*/ -#define _GPIO_LESENSE_CH10OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH10OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH10OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE */ -#define GPIO_LESENSE_CH10OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH10OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE*/ +#define _GPIO_LESENSE_CH10OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH10OUTROUTE */ +#define _GPIO_LESENSE_CH10OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH10OUTROUTE */ +#define _GPIO_LESENSE_CH10OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH10OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH10OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE */ +#define GPIO_LESENSE_CH10OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH10OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE*/ +#define _GPIO_LESENSE_CH10OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH10OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH10OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE */ +#define GPIO_LESENSE_CH10OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH10OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH11OUTROUTE */ -#define _GPIO_LESENSE_CH11OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH11OUTROUTE */ -#define _GPIO_LESENSE_CH11OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH11OUTROUTE */ -#define _GPIO_LESENSE_CH11OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH11OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH11OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE */ -#define GPIO_LESENSE_CH11OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH11OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE*/ -#define _GPIO_LESENSE_CH11OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH11OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH11OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE */ -#define GPIO_LESENSE_CH11OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH11OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE*/ +#define _GPIO_LESENSE_CH11OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH11OUTROUTE */ +#define _GPIO_LESENSE_CH11OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH11OUTROUTE */ +#define _GPIO_LESENSE_CH11OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH11OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH11OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE */ +#define GPIO_LESENSE_CH11OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH11OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE*/ +#define _GPIO_LESENSE_CH11OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH11OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH11OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE */ +#define GPIO_LESENSE_CH11OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH11OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH12OUTROUTE */ -#define _GPIO_LESENSE_CH12OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH12OUTROUTE */ -#define _GPIO_LESENSE_CH12OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH12OUTROUTE */ -#define _GPIO_LESENSE_CH12OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH12OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH12OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE */ -#define GPIO_LESENSE_CH12OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH12OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE*/ -#define _GPIO_LESENSE_CH12OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH12OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH12OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE */ -#define GPIO_LESENSE_CH12OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH12OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE*/ +#define _GPIO_LESENSE_CH12OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH12OUTROUTE */ +#define _GPIO_LESENSE_CH12OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH12OUTROUTE */ +#define _GPIO_LESENSE_CH12OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH12OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH12OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE */ +#define GPIO_LESENSE_CH12OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH12OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE*/ +#define _GPIO_LESENSE_CH12OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH12OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH12OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE */ +#define GPIO_LESENSE_CH12OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH12OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH13OUTROUTE */ -#define _GPIO_LESENSE_CH13OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH13OUTROUTE */ -#define _GPIO_LESENSE_CH13OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH13OUTROUTE */ -#define _GPIO_LESENSE_CH13OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH13OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH13OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE */ -#define GPIO_LESENSE_CH13OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH13OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE*/ -#define _GPIO_LESENSE_CH13OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH13OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH13OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE */ -#define GPIO_LESENSE_CH13OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH13OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE*/ +#define _GPIO_LESENSE_CH13OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH13OUTROUTE */ +#define _GPIO_LESENSE_CH13OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH13OUTROUTE */ +#define _GPIO_LESENSE_CH13OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH13OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH13OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE */ +#define GPIO_LESENSE_CH13OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH13OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE*/ +#define _GPIO_LESENSE_CH13OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH13OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH13OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE */ +#define GPIO_LESENSE_CH13OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH13OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH14OUTROUTE */ -#define _GPIO_LESENSE_CH14OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH14OUTROUTE */ -#define _GPIO_LESENSE_CH14OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH14OUTROUTE */ -#define _GPIO_LESENSE_CH14OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH14OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH14OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE */ -#define GPIO_LESENSE_CH14OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH14OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE*/ -#define _GPIO_LESENSE_CH14OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH14OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH14OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE */ -#define GPIO_LESENSE_CH14OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH14OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE*/ +#define _GPIO_LESENSE_CH14OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH14OUTROUTE */ +#define _GPIO_LESENSE_CH14OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH14OUTROUTE */ +#define _GPIO_LESENSE_CH14OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH14OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH14OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE */ +#define GPIO_LESENSE_CH14OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH14OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE*/ +#define _GPIO_LESENSE_CH14OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH14OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH14OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE */ +#define GPIO_LESENSE_CH14OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH14OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH15OUTROUTE */ -#define _GPIO_LESENSE_CH15OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH15OUTROUTE */ -#define _GPIO_LESENSE_CH15OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH15OUTROUTE */ -#define _GPIO_LESENSE_CH15OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH15OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH15OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE */ -#define GPIO_LESENSE_CH15OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH15OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE*/ -#define _GPIO_LESENSE_CH15OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH15OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH15OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE */ -#define GPIO_LESENSE_CH15OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH15OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE*/ +#define _GPIO_LESENSE_CH15OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH15OUTROUTE */ +#define _GPIO_LESENSE_CH15OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH15OUTROUTE */ +#define _GPIO_LESENSE_CH15OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH15OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH15OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE */ +#define GPIO_LESENSE_CH15OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH15OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE*/ +#define _GPIO_LESENSE_CH15OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH15OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH15OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE */ +#define GPIO_LESENSE_CH15OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH15OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE*/ /* Bit fields for GPIO_LETIMER ROUTEEN */ -#define _GPIO_LETIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_ROUTEEN */ -#define _GPIO_LETIMER_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_LETIMER_ROUTEEN */ -#define GPIO_LETIMER_ROUTEEN_OUT0PEN (0x1UL << 0) /**< OUT0 pin enable control bit */ -#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_SHIFT 0 /**< Shift value for GPIO_OUT0PEN */ -#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_OUT0PEN */ -#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ -#define GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ -#define GPIO_LETIMER_ROUTEEN_OUT1PEN (0x1UL << 1) /**< OUT1 pin enable control bit */ -#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_SHIFT 1 /**< Shift value for GPIO_OUT1PEN */ -#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_OUT1PEN */ -#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ -#define GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ +#define _GPIO_LETIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_ROUTEEN */ +#define _GPIO_LETIMER_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN (0x1UL << 0) /**< OUT0 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_SHIFT 0 /**< Shift value for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN (0x1UL << 1) /**< OUT1 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_SHIFT 1 /**< Shift value for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ /* Bit fields for GPIO_LETIMER OUT0ROUTE */ -#define _GPIO_LETIMER_OUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT0ROUTE */ -#define _GPIO_LETIMER_OUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT0ROUTE */ -#define _GPIO_LETIMER_OUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LETIMER_OUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ -#define GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ -#define _GPIO_LETIMER_OUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LETIMER_OUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ -#define GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ +#define _GPIO_LETIMER_OUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ /* Bit fields for GPIO_LETIMER OUT1ROUTE */ -#define _GPIO_LETIMER_OUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT1ROUTE */ -#define _GPIO_LETIMER_OUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT1ROUTE */ -#define _GPIO_LETIMER_OUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LETIMER_OUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ -#define GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ -#define _GPIO_LETIMER_OUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LETIMER_OUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ -#define GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ +#define _GPIO_LETIMER_OUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ /* Bit fields for GPIO_MODEM ROUTEEN */ -#define _GPIO_MODEM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ROUTEEN */ -#define _GPIO_MODEM_ROUTEEN_MASK 0x00007FFFUL /**< Mask for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANT0PEN (0x1UL << 0) /**< ANT0 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANT0PEN_SHIFT 0 /**< Shift value for GPIO_ANT0PEN */ -#define _GPIO_MODEM_ROUTEEN_ANT0PEN_MASK 0x1UL /**< Bit mask for GPIO_ANT0PEN */ -#define _GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANT1PEN (0x1UL << 1) /**< ANT1 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANT1PEN_SHIFT 1 /**< Shift value for GPIO_ANT1PEN */ -#define _GPIO_MODEM_ROUTEEN_ANT1PEN_MASK 0x2UL /**< Bit mask for GPIO_ANT1PEN */ -#define _GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN (0x1UL << 2) /**< ANTROLLOVER pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_SHIFT 2 /**< Shift value for GPIO_ANTROLLOVERPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_MASK 0x4UL /**< Bit mask for GPIO_ANTROLLOVERPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR0PEN (0x1UL << 3) /**< ANTRR0 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_SHIFT 3 /**< Shift value for GPIO_ANTRR0PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_MASK 0x8UL /**< Bit mask for GPIO_ANTRR0PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR1PEN (0x1UL << 4) /**< ANTRR1 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_SHIFT 4 /**< Shift value for GPIO_ANTRR1PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_MASK 0x10UL /**< Bit mask for GPIO_ANTRR1PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR2PEN (0x1UL << 5) /**< ANTRR2 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_SHIFT 5 /**< Shift value for GPIO_ANTRR2PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_MASK 0x20UL /**< Bit mask for GPIO_ANTRR2PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR3PEN (0x1UL << 6) /**< ANTRR3 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_SHIFT 6 /**< Shift value for GPIO_ANTRR3PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_MASK 0x40UL /**< Bit mask for GPIO_ANTRR3PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR4PEN (0x1UL << 7) /**< ANTRR4 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_SHIFT 7 /**< Shift value for GPIO_ANTRR4PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_MASK 0x80UL /**< Bit mask for GPIO_ANTRR4PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR5PEN (0x1UL << 8) /**< ANTRR5 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_SHIFT 8 /**< Shift value for GPIO_ANTRR5PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_MASK 0x100UL /**< Bit mask for GPIO_ANTRR5PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTSWENPEN (0x1UL << 9) /**< ANTSWEN pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_SHIFT 9 /**< Shift value for GPIO_ANTSWENPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_MASK 0x200UL /**< Bit mask for GPIO_ANTSWENPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN (0x1UL << 10) /**< ANTSWUS pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_SHIFT 10 /**< Shift value for GPIO_ANTSWUSPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_MASK 0x400UL /**< Bit mask for GPIO_ANTSWUSPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN (0x1UL << 11) /**< ANTTRIG pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_SHIFT 11 /**< Shift value for GPIO_ANTTRIGPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_MASK 0x800UL /**< Bit mask for GPIO_ANTTRIGPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN (0x1UL << 12) /**< ANTTRIGSTOP pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_SHIFT 12 /**< Shift value for GPIO_ANTTRIGSTOPPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_MASK 0x1000UL /**< Bit mask for GPIO_ANTTRIGSTOPPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_DCLKPEN (0x1UL << 13) /**< DCLK pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_DCLKPEN_SHIFT 13 /**< Shift value for GPIO_DCLKPEN */ -#define _GPIO_MODEM_ROUTEEN_DCLKPEN_MASK 0x2000UL /**< Bit mask for GPIO_DCLKPEN */ -#define _GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_DOUTPEN (0x1UL << 14) /**< DOUT pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_DOUTPEN_SHIFT 14 /**< Shift value for GPIO_DOUTPEN */ -#define _GPIO_MODEM_ROUTEEN_DOUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_DOUTPEN */ -#define _GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_MASK 0x00007FFFUL /**< Mask for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN (0x1UL << 0) /**< ANT0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_SHIFT 0 /**< Shift value for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_MASK 0x1UL /**< Bit mask for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN (0x1UL << 1) /**< ANT1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_SHIFT 1 /**< Shift value for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_MASK 0x2UL /**< Bit mask for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN (0x1UL << 2) /**< ANTROLLOVER pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_SHIFT 2 /**< Shift value for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_MASK 0x4UL /**< Bit mask for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN (0x1UL << 3) /**< ANTRR0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_SHIFT 3 /**< Shift value for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_MASK 0x8UL /**< Bit mask for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN (0x1UL << 4) /**< ANTRR1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_SHIFT 4 /**< Shift value for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_MASK 0x10UL /**< Bit mask for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN (0x1UL << 5) /**< ANTRR2 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_SHIFT 5 /**< Shift value for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_MASK 0x20UL /**< Bit mask for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN (0x1UL << 6) /**< ANTRR3 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_SHIFT 6 /**< Shift value for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_MASK 0x40UL /**< Bit mask for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN (0x1UL << 7) /**< ANTRR4 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_SHIFT 7 /**< Shift value for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_MASK 0x80UL /**< Bit mask for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN (0x1UL << 8) /**< ANTRR5 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_SHIFT 8 /**< Shift value for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_MASK 0x100UL /**< Bit mask for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN (0x1UL << 9) /**< ANTSWEN pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_SHIFT 9 /**< Shift value for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_MASK 0x200UL /**< Bit mask for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN (0x1UL << 10) /**< ANTSWUS pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_SHIFT 10 /**< Shift value for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_MASK 0x400UL /**< Bit mask for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN (0x1UL << 11) /**< ANTTRIG pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_SHIFT 11 /**< Shift value for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_MASK 0x800UL /**< Bit mask for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN (0x1UL << 12) /**< ANTTRIGSTOP pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_SHIFT 12 /**< Shift value for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_MASK 0x1000UL /**< Bit mask for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN (0x1UL << 13) /**< DCLK pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_SHIFT 13 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_MASK 0x2000UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN (0x1UL << 14) /**< DOUT pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_SHIFT 14 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ /* Bit fields for GPIO_MODEM ANT0ROUTE */ -#define _GPIO_MODEM_ANT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT0ROUTE */ -#define _GPIO_MODEM_ANT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT0ROUTE */ -#define _GPIO_MODEM_ANT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ -#define GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ -#define _GPIO_MODEM_ANT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ -#define GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ +#define _GPIO_MODEM_ANT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ +#define _GPIO_MODEM_ANT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ /* Bit fields for GPIO_MODEM ANT1ROUTE */ -#define _GPIO_MODEM_ANT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT1ROUTE */ -#define _GPIO_MODEM_ANT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT1ROUTE */ -#define _GPIO_MODEM_ANT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ -#define GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ -#define _GPIO_MODEM_ANT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ -#define GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ +#define _GPIO_MODEM_ANT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ +#define _GPIO_MODEM_ANT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ /* Bit fields for GPIO_MODEM ANTROLLOVERROUTE */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTROLLOVERROUTE*/ -#define _GPIO_MODEM_ANTROLLOVERROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTROLLOVERROUTE */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ -#define GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ -#define GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTROLLOVERROUTE */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ /* Bit fields for GPIO_MODEM ANTRR0ROUTE */ -#define _GPIO_MODEM_ANTRR0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR0ROUTE */ -#define _GPIO_MODEM_ANTRR0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR0ROUTE */ -#define _GPIO_MODEM_ANTRR0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ -#define GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ -#define _GPIO_MODEM_ANTRR0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ -#define GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ +#define _GPIO_MODEM_ANTRR0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ /* Bit fields for GPIO_MODEM ANTRR1ROUTE */ -#define _GPIO_MODEM_ANTRR1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR1ROUTE */ -#define _GPIO_MODEM_ANTRR1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR1ROUTE */ -#define _GPIO_MODEM_ANTRR1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ -#define GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ -#define _GPIO_MODEM_ANTRR1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ -#define GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ +#define _GPIO_MODEM_ANTRR1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ /* Bit fields for GPIO_MODEM ANTRR2ROUTE */ -#define _GPIO_MODEM_ANTRR2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR2ROUTE */ -#define _GPIO_MODEM_ANTRR2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR2ROUTE */ -#define _GPIO_MODEM_ANTRR2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ -#define GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ -#define _GPIO_MODEM_ANTRR2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ -#define GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ +#define _GPIO_MODEM_ANTRR2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ /* Bit fields for GPIO_MODEM ANTRR3ROUTE */ -#define _GPIO_MODEM_ANTRR3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR3ROUTE */ -#define _GPIO_MODEM_ANTRR3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR3ROUTE */ -#define _GPIO_MODEM_ANTRR3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ -#define GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ -#define _GPIO_MODEM_ANTRR3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ -#define GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ +#define _GPIO_MODEM_ANTRR3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ /* Bit fields for GPIO_MODEM ANTRR4ROUTE */ -#define _GPIO_MODEM_ANTRR4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR4ROUTE */ -#define _GPIO_MODEM_ANTRR4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR4ROUTE */ -#define _GPIO_MODEM_ANTRR4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ -#define GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ -#define _GPIO_MODEM_ANTRR4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ -#define GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ +#define _GPIO_MODEM_ANTRR4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ /* Bit fields for GPIO_MODEM ANTRR5ROUTE */ -#define _GPIO_MODEM_ANTRR5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR5ROUTE */ -#define _GPIO_MODEM_ANTRR5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR5ROUTE */ -#define _GPIO_MODEM_ANTRR5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ -#define GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ -#define _GPIO_MODEM_ANTRR5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ -#define GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ +#define _GPIO_MODEM_ANTRR5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ /* Bit fields for GPIO_MODEM ANTSWENROUTE */ -#define _GPIO_MODEM_ANTSWENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWENROUTE */ -#define _GPIO_MODEM_ANTSWENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWENROUTE */ -#define _GPIO_MODEM_ANTSWENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTSWENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ -#define GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ -#define _GPIO_MODEM_ANTSWENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTSWENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ -#define GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ +#define _GPIO_MODEM_ANTSWENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ /* Bit fields for GPIO_MODEM ANTSWUSROUTE */ -#define _GPIO_MODEM_ANTSWUSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWUSROUTE */ -#define _GPIO_MODEM_ANTSWUSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWUSROUTE */ -#define _GPIO_MODEM_ANTSWUSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTSWUSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ -#define GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ -#define _GPIO_MODEM_ANTSWUSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTSWUSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ -#define GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ +#define _GPIO_MODEM_ANTSWUSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ /* Bit fields for GPIO_MODEM ANTTRIGROUTE */ -#define _GPIO_MODEM_ANTTRIGROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGROUTE */ -#define _GPIO_MODEM_ANTTRIGROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGROUTE */ -#define _GPIO_MODEM_ANTTRIGROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTTRIGROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ -#define GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ -#define _GPIO_MODEM_ANTTRIGROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTTRIGROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ -#define GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ +#define _GPIO_MODEM_ANTTRIGROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ /* Bit fields for GPIO_MODEM ANTTRIGSTOPROUTE */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGSTOPROUTE*/ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGSTOPROUTE */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ -#define GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ -#define GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGSTOPROUTE */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ /* Bit fields for GPIO_MODEM DCLKROUTE */ -#define _GPIO_MODEM_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DCLKROUTE */ -#define _GPIO_MODEM_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DCLKROUTE */ -#define _GPIO_MODEM_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ -#define GPIO_MODEM_DCLKROUTE_PORT_DEFAULT (_GPIO_MODEM_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ -#define _GPIO_MODEM_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ -#define GPIO_MODEM_DCLKROUTE_PIN_DEFAULT (_GPIO_MODEM_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ +#define _GPIO_MODEM_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PORT_DEFAULT (_GPIO_MODEM_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ +#define _GPIO_MODEM_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PIN_DEFAULT (_GPIO_MODEM_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ /* Bit fields for GPIO_MODEM DINROUTE */ -#define _GPIO_MODEM_DINROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DINROUTE */ -#define _GPIO_MODEM_DINROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DINROUTE */ -#define _GPIO_MODEM_DINROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_DINROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_DINROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ -#define GPIO_MODEM_DINROUTE_PORT_DEFAULT (_GPIO_MODEM_DINROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ -#define _GPIO_MODEM_DINROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_DINROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_DINROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ -#define GPIO_MODEM_DINROUTE_PIN_DEFAULT (_GPIO_MODEM_DINROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ +#define _GPIO_MODEM_DINROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PORT_DEFAULT (_GPIO_MODEM_DINROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ +#define _GPIO_MODEM_DINROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PIN_DEFAULT (_GPIO_MODEM_DINROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ /* Bit fields for GPIO_MODEM DOUTROUTE */ -#define _GPIO_MODEM_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DOUTROUTE */ -#define _GPIO_MODEM_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DOUTROUTE */ -#define _GPIO_MODEM_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ -#define GPIO_MODEM_DOUTROUTE_PORT_DEFAULT (_GPIO_MODEM_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ -#define _GPIO_MODEM_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ -#define GPIO_MODEM_DOUTROUTE_PIN_DEFAULT (_GPIO_MODEM_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ +#define _GPIO_MODEM_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PORT_DEFAULT (_GPIO_MODEM_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ +#define _GPIO_MODEM_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PIN_DEFAULT (_GPIO_MODEM_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ /* Bit fields for GPIO_PCNT S0INROUTE */ -#define _GPIO_PCNT_S0INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S0INROUTE */ -#define _GPIO_PCNT_S0INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S0INROUTE */ -#define _GPIO_PCNT_S0INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PCNT_S0INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PCNT_S0INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ -#define GPIO_PCNT_S0INROUTE_PORT_DEFAULT (_GPIO_PCNT_S0INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ -#define _GPIO_PCNT_S0INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PCNT_S0INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PCNT_S0INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ -#define GPIO_PCNT_S0INROUTE_PIN_DEFAULT (_GPIO_PCNT_S0INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ +#define _GPIO_PCNT_S0INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S0INROUTE */ +#define _GPIO_PCNT_S0INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S0INROUTE */ +#define _GPIO_PCNT_S0INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PCNT_S0INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PCNT_S0INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ +#define GPIO_PCNT_S0INROUTE_PORT_DEFAULT (_GPIO_PCNT_S0INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ +#define _GPIO_PCNT_S0INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PCNT_S0INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PCNT_S0INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ +#define GPIO_PCNT_S0INROUTE_PIN_DEFAULT (_GPIO_PCNT_S0INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ /* Bit fields for GPIO_PCNT S1INROUTE */ -#define _GPIO_PCNT_S1INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S1INROUTE */ -#define _GPIO_PCNT_S1INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S1INROUTE */ -#define _GPIO_PCNT_S1INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PCNT_S1INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PCNT_S1INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ -#define GPIO_PCNT_S1INROUTE_PORT_DEFAULT (_GPIO_PCNT_S1INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ -#define _GPIO_PCNT_S1INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PCNT_S1INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PCNT_S1INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ -#define GPIO_PCNT_S1INROUTE_PIN_DEFAULT (_GPIO_PCNT_S1INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ +#define _GPIO_PCNT_S1INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S1INROUTE */ +#define _GPIO_PCNT_S1INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S1INROUTE */ +#define _GPIO_PCNT_S1INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PCNT_S1INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PCNT_S1INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ +#define GPIO_PCNT_S1INROUTE_PORT_DEFAULT (_GPIO_PCNT_S1INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ +#define _GPIO_PCNT_S1INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PCNT_S1INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PCNT_S1INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ +#define GPIO_PCNT_S1INROUTE_PIN_DEFAULT (_GPIO_PCNT_S1INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ /* Bit fields for GPIO_PRS ROUTEEN */ -#define _GPIO_PRS_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ROUTEEN */ -#define _GPIO_PRS_ROUTEEN_MASK 0x0000FFFFUL /**< Mask for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH0PEN (0x1UL << 0) /**< ASYNCH0 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT 0 /**< Shift value for GPIO_ASYNCH0PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_MASK 0x1UL /**< Bit mask for GPIO_ASYNCH0PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH1PEN (0x1UL << 1) /**< ASYNCH1 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_SHIFT 1 /**< Shift value for GPIO_ASYNCH1PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_MASK 0x2UL /**< Bit mask for GPIO_ASYNCH1PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH2PEN (0x1UL << 2) /**< ASYNCH2 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_SHIFT 2 /**< Shift value for GPIO_ASYNCH2PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_MASK 0x4UL /**< Bit mask for GPIO_ASYNCH2PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH3PEN (0x1UL << 3) /**< ASYNCH3 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_SHIFT 3 /**< Shift value for GPIO_ASYNCH3PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_MASK 0x8UL /**< Bit mask for GPIO_ASYNCH3PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH4PEN (0x1UL << 4) /**< ASYNCH4 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_SHIFT 4 /**< Shift value for GPIO_ASYNCH4PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_MASK 0x10UL /**< Bit mask for GPIO_ASYNCH4PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH5PEN (0x1UL << 5) /**< ASYNCH5 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_SHIFT 5 /**< Shift value for GPIO_ASYNCH5PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_MASK 0x20UL /**< Bit mask for GPIO_ASYNCH5PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH6PEN (0x1UL << 6) /**< ASYNCH6 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_SHIFT 6 /**< Shift value for GPIO_ASYNCH6PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_MASK 0x40UL /**< Bit mask for GPIO_ASYNCH6PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH7PEN (0x1UL << 7) /**< ASYNCH7 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_SHIFT 7 /**< Shift value for GPIO_ASYNCH7PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_MASK 0x80UL /**< Bit mask for GPIO_ASYNCH7PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH8PEN (0x1UL << 8) /**< ASYNCH8 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_SHIFT 8 /**< Shift value for GPIO_ASYNCH8PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_MASK 0x100UL /**< Bit mask for GPIO_ASYNCH8PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH9PEN (0x1UL << 9) /**< ASYNCH9 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_SHIFT 9 /**< Shift value for GPIO_ASYNCH9PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_MASK 0x200UL /**< Bit mask for GPIO_ASYNCH9PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH10PEN (0x1UL << 10) /**< ASYNCH10 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_SHIFT 10 /**< Shift value for GPIO_ASYNCH10PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_MASK 0x400UL /**< Bit mask for GPIO_ASYNCH10PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH11PEN (0x1UL << 11) /**< ASYNCH11 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_SHIFT 11 /**< Shift value for GPIO_ASYNCH11PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_MASK 0x800UL /**< Bit mask for GPIO_ASYNCH11PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH0PEN (0x1UL << 12) /**< SYNCH0 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT 12 /**< Shift value for GPIO_SYNCH0PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_MASK 0x1000UL /**< Bit mask for GPIO_SYNCH0PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH1PEN (0x1UL << 13) /**< SYNCH1 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_SHIFT 13 /**< Shift value for GPIO_SYNCH1PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_MASK 0x2000UL /**< Bit mask for GPIO_SYNCH1PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH2PEN (0x1UL << 14) /**< SYNCH2 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_SHIFT 14 /**< Shift value for GPIO_SYNCH2PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_MASK 0x4000UL /**< Bit mask for GPIO_SYNCH2PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH3PEN (0x1UL << 15) /**< SYNCH3 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_SHIFT 15 /**< Shift value for GPIO_SYNCH3PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_MASK 0x8000UL /**< Bit mask for GPIO_SYNCH3PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_MASK 0x0000FFFFUL /**< Mask for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN (0x1UL << 0) /**< ASYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT 0 /**< Shift value for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_MASK 0x1UL /**< Bit mask for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN (0x1UL << 1) /**< ASYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_SHIFT 1 /**< Shift value for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_MASK 0x2UL /**< Bit mask for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN (0x1UL << 2) /**< ASYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_SHIFT 2 /**< Shift value for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_MASK 0x4UL /**< Bit mask for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN (0x1UL << 3) /**< ASYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_SHIFT 3 /**< Shift value for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_MASK 0x8UL /**< Bit mask for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN (0x1UL << 4) /**< ASYNCH4 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_SHIFT 4 /**< Shift value for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_MASK 0x10UL /**< Bit mask for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN (0x1UL << 5) /**< ASYNCH5 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_SHIFT 5 /**< Shift value for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_MASK 0x20UL /**< Bit mask for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN (0x1UL << 6) /**< ASYNCH6 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_SHIFT 6 /**< Shift value for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_MASK 0x40UL /**< Bit mask for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN (0x1UL << 7) /**< ASYNCH7 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_SHIFT 7 /**< Shift value for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_MASK 0x80UL /**< Bit mask for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN (0x1UL << 8) /**< ASYNCH8 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_SHIFT 8 /**< Shift value for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_MASK 0x100UL /**< Bit mask for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN (0x1UL << 9) /**< ASYNCH9 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_SHIFT 9 /**< Shift value for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_MASK 0x200UL /**< Bit mask for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN (0x1UL << 10) /**< ASYNCH10 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_SHIFT 10 /**< Shift value for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_MASK 0x400UL /**< Bit mask for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN (0x1UL << 11) /**< ASYNCH11 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_SHIFT 11 /**< Shift value for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_MASK 0x800UL /**< Bit mask for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN (0x1UL << 12) /**< SYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT 12 /**< Shift value for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_MASK 0x1000UL /**< Bit mask for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN (0x1UL << 13) /**< SYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_SHIFT 13 /**< Shift value for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_MASK 0x2000UL /**< Bit mask for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN (0x1UL << 14) /**< SYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_SHIFT 14 /**< Shift value for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_MASK 0x4000UL /**< Bit mask for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN (0x1UL << 15) /**< SYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_SHIFT 15 /**< Shift value for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_MASK 0x8000UL /**< Bit mask for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ /* Bit fields for GPIO_PRS ASYNCH0ROUTE */ -#define _GPIO_PRS_ASYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH0ROUTE */ -#define _GPIO_PRS_ASYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH0ROUTE */ -#define _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ -#define GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ -#define _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ -#define GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ +#define _GPIO_PRS_ASYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH1ROUTE */ -#define _GPIO_PRS_ASYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH1ROUTE */ -#define _GPIO_PRS_ASYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH1ROUTE */ -#define _GPIO_PRS_ASYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ -#define GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ -#define _GPIO_PRS_ASYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ -#define GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ +#define _GPIO_PRS_ASYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH2ROUTE */ -#define _GPIO_PRS_ASYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH2ROUTE */ -#define _GPIO_PRS_ASYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH2ROUTE */ -#define _GPIO_PRS_ASYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ -#define GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ -#define _GPIO_PRS_ASYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ -#define GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ +#define _GPIO_PRS_ASYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH3ROUTE */ -#define _GPIO_PRS_ASYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH3ROUTE */ -#define _GPIO_PRS_ASYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH3ROUTE */ -#define _GPIO_PRS_ASYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ -#define GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ -#define _GPIO_PRS_ASYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ -#define GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ +#define _GPIO_PRS_ASYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH4ROUTE */ -#define _GPIO_PRS_ASYNCH4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH4ROUTE */ -#define _GPIO_PRS_ASYNCH4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH4ROUTE */ -#define _GPIO_PRS_ASYNCH4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ -#define GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ -#define _GPIO_PRS_ASYNCH4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ -#define GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ +#define _GPIO_PRS_ASYNCH4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH5ROUTE */ -#define _GPIO_PRS_ASYNCH5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH5ROUTE */ -#define _GPIO_PRS_ASYNCH5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH5ROUTE */ -#define _GPIO_PRS_ASYNCH5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ -#define GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ -#define _GPIO_PRS_ASYNCH5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ -#define GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ +#define _GPIO_PRS_ASYNCH5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH6ROUTE */ -#define _GPIO_PRS_ASYNCH6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH6ROUTE */ -#define _GPIO_PRS_ASYNCH6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH6ROUTE */ -#define _GPIO_PRS_ASYNCH6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ -#define GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ -#define _GPIO_PRS_ASYNCH6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ -#define GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ +#define _GPIO_PRS_ASYNCH6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH7ROUTE */ -#define _GPIO_PRS_ASYNCH7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH7ROUTE */ -#define _GPIO_PRS_ASYNCH7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH7ROUTE */ -#define _GPIO_PRS_ASYNCH7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ -#define GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ -#define _GPIO_PRS_ASYNCH7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ -#define GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ +#define _GPIO_PRS_ASYNCH7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH8ROUTE */ -#define _GPIO_PRS_ASYNCH8ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH8ROUTE */ -#define _GPIO_PRS_ASYNCH8ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH8ROUTE */ -#define _GPIO_PRS_ASYNCH8ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH8ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ -#define GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ -#define _GPIO_PRS_ASYNCH8ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH8ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ -#define GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ +#define _GPIO_PRS_ASYNCH8ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH9ROUTE */ -#define _GPIO_PRS_ASYNCH9ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH9ROUTE */ -#define _GPIO_PRS_ASYNCH9ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH9ROUTE */ -#define _GPIO_PRS_ASYNCH9ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH9ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ -#define GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ -#define _GPIO_PRS_ASYNCH9ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH9ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ -#define GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ +#define _GPIO_PRS_ASYNCH9ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH10ROUTE */ -#define _GPIO_PRS_ASYNCH10ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH10ROUTE */ -#define _GPIO_PRS_ASYNCH10ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH10ROUTE */ -#define _GPIO_PRS_ASYNCH10ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH10ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ -#define GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ -#define _GPIO_PRS_ASYNCH10ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH10ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ -#define GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ +#define _GPIO_PRS_ASYNCH10ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH11ROUTE */ -#define _GPIO_PRS_ASYNCH11ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH11ROUTE */ -#define _GPIO_PRS_ASYNCH11ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH11ROUTE */ -#define _GPIO_PRS_ASYNCH11ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH11ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ -#define GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ -#define _GPIO_PRS_ASYNCH11ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH11ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ -#define GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ +#define _GPIO_PRS_ASYNCH11ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ /* Bit fields for GPIO_PRS SYNCH0ROUTE */ -#define _GPIO_PRS_SYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH0ROUTE */ -#define _GPIO_PRS_SYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH0ROUTE */ -#define _GPIO_PRS_SYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_SYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ -#define GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ -#define _GPIO_PRS_SYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_SYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ -#define GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ +#define _GPIO_PRS_SYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ /* Bit fields for GPIO_PRS SYNCH1ROUTE */ -#define _GPIO_PRS_SYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH1ROUTE */ -#define _GPIO_PRS_SYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH1ROUTE */ -#define _GPIO_PRS_SYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_SYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ -#define GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ -#define _GPIO_PRS_SYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_SYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ -#define GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ +#define _GPIO_PRS_SYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ /* Bit fields for GPIO_PRS SYNCH2ROUTE */ -#define _GPIO_PRS_SYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH2ROUTE */ -#define _GPIO_PRS_SYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH2ROUTE */ -#define _GPIO_PRS_SYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_SYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ -#define GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ -#define _GPIO_PRS_SYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_SYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ -#define GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ +#define _GPIO_PRS_SYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ /* Bit fields for GPIO_PRS SYNCH3ROUTE */ -#define _GPIO_PRS_SYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH3ROUTE */ -#define _GPIO_PRS_SYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH3ROUTE */ -#define _GPIO_PRS_SYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_SYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ -#define GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ -#define _GPIO_PRS_SYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_SYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ -#define GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ +#define _GPIO_PRS_SYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ /* Bit fields for GPIO_SYXO BUFOUTREQINASYNCROUTE */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_MASK 0x000F0003UL /**< Mask for GPIO_SYXO_BUFOUTREQINASYNCROUTE */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ -#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ -#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_MASK 0x000F0003UL /**< Mask for GPIO_SYXO_BUFOUTREQINASYNCROUTE */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ /* Bit fields for GPIO_TIMER ROUTEEN */ -#define _GPIO_TIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_ROUTEEN */ -#define _GPIO_TIMER_ROUTEEN_MASK 0x0000003FUL /**< Mask for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC0PEN (0x1UL << 0) /**< CC0 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CC0PEN_SHIFT 0 /**< Shift value for GPIO_CC0PEN */ -#define _GPIO_TIMER_ROUTEEN_CC0PEN_MASK 0x1UL /**< Bit mask for GPIO_CC0PEN */ -#define _GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC1PEN (0x1UL << 1) /**< CC1 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CC1PEN_SHIFT 1 /**< Shift value for GPIO_CC1PEN */ -#define _GPIO_TIMER_ROUTEEN_CC1PEN_MASK 0x2UL /**< Bit mask for GPIO_CC1PEN */ -#define _GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC2PEN (0x1UL << 2) /**< CC2 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CC2PEN_SHIFT 2 /**< Shift value for GPIO_CC2PEN */ -#define _GPIO_TIMER_ROUTEEN_CC2PEN_MASK 0x4UL /**< Bit mask for GPIO_CC2PEN */ -#define _GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC0PEN (0x1UL << 3) /**< CDTI0 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CCC0PEN_SHIFT 3 /**< Shift value for GPIO_CCC0PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC0PEN_MASK 0x8UL /**< Bit mask for GPIO_CCC0PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC1PEN (0x1UL << 4) /**< CDTI1 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CCC1PEN_SHIFT 4 /**< Shift value for GPIO_CCC1PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC1PEN_MASK 0x10UL /**< Bit mask for GPIO_CCC1PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC2PEN (0x1UL << 5) /**< CDTI2 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CCC2PEN_SHIFT 5 /**< Shift value for GPIO_CCC2PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC2PEN_MASK 0x20UL /**< Bit mask for GPIO_CCC2PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_MASK 0x0000003FUL /**< Mask for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN (0x1UL << 0) /**< CC0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_SHIFT 0 /**< Shift value for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_MASK 0x1UL /**< Bit mask for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN (0x1UL << 1) /**< CC1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_SHIFT 1 /**< Shift value for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_MASK 0x2UL /**< Bit mask for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN (0x1UL << 2) /**< CC2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_SHIFT 2 /**< Shift value for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_MASK 0x4UL /**< Bit mask for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN (0x1UL << 3) /**< CDTI0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_SHIFT 3 /**< Shift value for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_MASK 0x8UL /**< Bit mask for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN (0x1UL << 4) /**< CDTI1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_SHIFT 4 /**< Shift value for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_MASK 0x10UL /**< Bit mask for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN (0x1UL << 5) /**< CDTI2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_SHIFT 5 /**< Shift value for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_MASK 0x20UL /**< Bit mask for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ /* Bit fields for GPIO_TIMER CC0ROUTE */ -#define _GPIO_TIMER_CC0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC0ROUTE */ -#define _GPIO_TIMER_CC0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC0ROUTE */ -#define _GPIO_TIMER_CC0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CC0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CC0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ -#define GPIO_TIMER_CC0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ -#define _GPIO_TIMER_CC0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CC0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CC0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ -#define GPIO_TIMER_CC0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ +#define _GPIO_TIMER_CC0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ +#define _GPIO_TIMER_CC0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ /* Bit fields for GPIO_TIMER CC1ROUTE */ -#define _GPIO_TIMER_CC1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC1ROUTE */ -#define _GPIO_TIMER_CC1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC1ROUTE */ -#define _GPIO_TIMER_CC1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CC1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CC1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ -#define GPIO_TIMER_CC1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ -#define _GPIO_TIMER_CC1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CC1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CC1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ -#define GPIO_TIMER_CC1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ +#define _GPIO_TIMER_CC1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ +#define _GPIO_TIMER_CC1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ /* Bit fields for GPIO_TIMER CC2ROUTE */ -#define _GPIO_TIMER_CC2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC2ROUTE */ -#define _GPIO_TIMER_CC2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC2ROUTE */ -#define _GPIO_TIMER_CC2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CC2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CC2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ -#define GPIO_TIMER_CC2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ -#define _GPIO_TIMER_CC2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CC2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CC2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ -#define GPIO_TIMER_CC2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ +#define _GPIO_TIMER_CC2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ +#define _GPIO_TIMER_CC2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ /* Bit fields for GPIO_TIMER CDTI0ROUTE */ -#define _GPIO_TIMER_CDTI0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI0ROUTE */ -#define _GPIO_TIMER_CDTI0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI0ROUTE */ -#define _GPIO_TIMER_CDTI0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CDTI0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ -#define GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ -#define _GPIO_TIMER_CDTI0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CDTI0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ -#define GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ +#define _GPIO_TIMER_CDTI0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ /* Bit fields for GPIO_TIMER CDTI1ROUTE */ -#define _GPIO_TIMER_CDTI1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI1ROUTE */ -#define _GPIO_TIMER_CDTI1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI1ROUTE */ -#define _GPIO_TIMER_CDTI1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CDTI1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ -#define GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ -#define _GPIO_TIMER_CDTI1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CDTI1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ -#define GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ +#define _GPIO_TIMER_CDTI1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ /* Bit fields for GPIO_TIMER CDTI2ROUTE */ -#define _GPIO_TIMER_CDTI2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI2ROUTE */ -#define _GPIO_TIMER_CDTI2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI2ROUTE */ -#define _GPIO_TIMER_CDTI2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CDTI2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ -#define GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ -#define _GPIO_TIMER_CDTI2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CDTI2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ -#define GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ +#define _GPIO_TIMER_CDTI2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ /* Bit fields for GPIO_USART ROUTEEN */ -#define _GPIO_USART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_ROUTEEN */ -#define _GPIO_USART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ -#define _GPIO_USART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ -#define _GPIO_USART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ -#define _GPIO_USART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_CSPEN_DEFAULT (_GPIO_USART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ -#define _GPIO_USART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ -#define _GPIO_USART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ -#define _GPIO_USART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_USART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ -#define _GPIO_USART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ -#define _GPIO_USART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ -#define _GPIO_USART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_RXPEN_DEFAULT (_GPIO_USART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_CLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ -#define _GPIO_USART_ROUTEEN_CLKPEN_SHIFT 3 /**< Shift value for GPIO_CLKPEN */ -#define _GPIO_USART_ROUTEEN_CLKPEN_MASK 0x8UL /**< Bit mask for GPIO_CLKPEN */ -#define _GPIO_USART_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_CLKPEN_DEFAULT (_GPIO_USART_ROUTEEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ -#define _GPIO_USART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ -#define _GPIO_USART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ -#define _GPIO_USART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_TXPEN_DEFAULT (_GPIO_USART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define _GPIO_USART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_ROUTEEN */ +#define _GPIO_USART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN_DEFAULT (_GPIO_USART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_USART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN_DEFAULT (_GPIO_USART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CLKPEN_SHIFT 3 /**< Shift value for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_MASK 0x8UL /**< Bit mask for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN_DEFAULT (_GPIO_USART_ROUTEEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN_DEFAULT (_GPIO_USART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ /* Bit fields for GPIO_USART CSROUTE */ -#define _GPIO_USART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CSROUTE */ -#define _GPIO_USART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CSROUTE */ -#define _GPIO_USART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ -#define GPIO_USART_CSROUTE_PORT_DEFAULT (_GPIO_USART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ -#define _GPIO_USART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ -#define GPIO_USART_CSROUTE_PIN_DEFAULT (_GPIO_USART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PORT_DEFAULT (_GPIO_USART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PIN_DEFAULT (_GPIO_USART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ /* Bit fields for GPIO_USART CTSROUTE */ -#define _GPIO_USART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CTSROUTE */ -#define _GPIO_USART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CTSROUTE */ -#define _GPIO_USART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ -#define GPIO_USART_CTSROUTE_PORT_DEFAULT (_GPIO_USART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ -#define _GPIO_USART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ -#define GPIO_USART_CTSROUTE_PIN_DEFAULT (_GPIO_USART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ +#define _GPIO_USART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PORT_DEFAULT (_GPIO_USART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ +#define _GPIO_USART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PIN_DEFAULT (_GPIO_USART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ /* Bit fields for GPIO_USART RTSROUTE */ -#define _GPIO_USART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RTSROUTE */ -#define _GPIO_USART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RTSROUTE */ -#define _GPIO_USART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ -#define GPIO_USART_RTSROUTE_PORT_DEFAULT (_GPIO_USART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ -#define _GPIO_USART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ -#define GPIO_USART_RTSROUTE_PIN_DEFAULT (_GPIO_USART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ +#define _GPIO_USART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PORT_DEFAULT (_GPIO_USART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ +#define _GPIO_USART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PIN_DEFAULT (_GPIO_USART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ /* Bit fields for GPIO_USART RXROUTE */ -#define _GPIO_USART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RXROUTE */ -#define _GPIO_USART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RXROUTE */ -#define _GPIO_USART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ -#define GPIO_USART_RXROUTE_PORT_DEFAULT (_GPIO_USART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ -#define _GPIO_USART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ -#define GPIO_USART_RXROUTE_PIN_DEFAULT (_GPIO_USART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PORT_DEFAULT (_GPIO_USART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PIN_DEFAULT (_GPIO_USART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ /* Bit fields for GPIO_USART CLKROUTE */ -#define _GPIO_USART_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CLKROUTE */ -#define _GPIO_USART_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CLKROUTE */ -#define _GPIO_USART_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ -#define GPIO_USART_CLKROUTE_PORT_DEFAULT (_GPIO_USART_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ -#define _GPIO_USART_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ -#define GPIO_USART_CLKROUTE_PIN_DEFAULT (_GPIO_USART_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ +#define _GPIO_USART_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PORT_DEFAULT (_GPIO_USART_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ +#define _GPIO_USART_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PIN_DEFAULT (_GPIO_USART_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ /* Bit fields for GPIO_USART TXROUTE */ -#define _GPIO_USART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_TXROUTE */ -#define _GPIO_USART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_TXROUTE */ -#define _GPIO_USART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ -#define GPIO_USART_TXROUTE_PORT_DEFAULT (_GPIO_USART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ -#define _GPIO_USART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ -#define GPIO_USART_TXROUTE_PIN_DEFAULT (_GPIO_USART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PORT_DEFAULT (_GPIO_USART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PIN_DEFAULT (_GPIO_USART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ /** @} End of group Parts */ #endif // EFR32SG23_GPIO_H diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpio_port.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpio_port.h index 558c207b1f..2c02a3a445 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_gpio_port.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -30,7 +30,6 @@ #ifndef GPIO_PORT_H #define GPIO_PORT_H - /**************************************************************************//** * @addtogroup Parts * @{ @@ -38,460 +37,457 @@ /**************************************************************************//** * @brief EFR32SG23 GPIO PORT *****************************************************************************/ -typedef struct -{ - __IOM uint32_t CTRL; /**< Port control */ - __IOM uint32_t MODEL; /**< mode low */ - uint32_t RESERVED0[1]; /**< Reserved for future use */ - __IOM uint32_t MODEH; /**< mode high */ - __IOM uint32_t DOUT; /**< data out */ - __IM uint32_t DIN; /**< data in */ - uint32_t RESERVED1[6]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t CTRL; /**< Port control */ + __IOM uint32_t MODEL; /**< mode low */ + uint32_t RESERVED0[1]; /**< Reserved for future use */ + __IOM uint32_t MODEH; /**< mode high */ + __IOM uint32_t DOUT; /**< data out */ + __IM uint32_t DIN; /**< data in */ + uint32_t RESERVED1[6]; /**< Reserved for future use */ } GPIO_PORT_TypeDef; - /* Bit fields for GPIO_P CTRL */ -#define _GPIO_P_CTRL_RESETVALUE 0x00400040UL /**< Default value for GPIO_P_CTRL */ -#define _GPIO_P_CTRL_MASK 0x10701070UL /**< Mask for GPIO_P_CTRL */ -#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ -#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ -#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */ -#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ -#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ -#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ -#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ -#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ -#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Data In Disable Alt */ -#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ -#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ -#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_RESETVALUE 0x00400040UL /**< Default value for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_MASK 0x10701070UL /**< Mask for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */ +#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Data In Disable Alt */ +#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ /* Bit fields for GPIO_P MODEL */ -#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ -#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ -#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ -#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ -#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ -#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ -#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ -#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ -#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ -#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ -#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ -#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ -#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ -#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ -#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ -#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ -#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ /* Bit fields for GPIO_P MODEH */ -#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MASK 0x00000FFFUL /**< Mask for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ -#define _GPIO_P_MODEH_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ -#define _GPIO_P_MODEH_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_DEFAULT (_GPIO_P_MODEH_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_DISABLED (_GPIO_P_MODEH_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_INPUT (_GPIO_P_MODEH_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_INPUTPULL (_GPIO_P_MODEH_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_INPUTPULLFILTER (_GPIO_P_MODEH_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_PUSHPULL (_GPIO_P_MODEH_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_PUSHPULLALT (_GPIO_P_MODEH_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_WIREDOR (_GPIO_P_MODEH_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDAND (_GPIO_P_MODEH_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_WIREDANDFILTER (_GPIO_P_MODEH_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDALT (_GPIO_P_MODEH_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define _GPIO_P_MODEH_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ -#define _GPIO_P_MODEH_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ -#define _GPIO_P_MODEH_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_DEFAULT (_GPIO_P_MODEH_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_DISABLED (_GPIO_P_MODEH_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_INPUT (_GPIO_P_MODEH_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_INPUTPULL (_GPIO_P_MODEH_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_INPUTPULLFILTER (_GPIO_P_MODEH_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_PUSHPULL (_GPIO_P_MODEH_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_PUSHPULLALT (_GPIO_P_MODEH_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_WIREDOR (_GPIO_P_MODEH_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDAND (_GPIO_P_MODEH_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_WIREDANDFILTER (_GPIO_P_MODEH_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDANDPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDANDALT (_GPIO_P_MODEH_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define _GPIO_P_MODEH_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ -#define _GPIO_P_MODEH_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ -#define _GPIO_P_MODEH_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE2_DEFAULT (_GPIO_P_MODEH_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_DISABLED (_GPIO_P_MODEH_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_INPUT (_GPIO_P_MODEH_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_INPUTPULL (_GPIO_P_MODEH_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_INPUTPULLFILTER (_GPIO_P_MODEH_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE2_PUSHPULL (_GPIO_P_MODEH_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_PUSHPULLALT (_GPIO_P_MODEH_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_WIREDOR (_GPIO_P_MODEH_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE2_WIREDAND (_GPIO_P_MODEH_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_WIREDANDFILTER (_GPIO_P_MODEH_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE2_WIREDANDPULLUP (_GPIO_P_MODEH_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE2_WIREDANDALT (_GPIO_P_MODEH_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MASK 0x00000FFFUL /**< Mask for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_DEFAULT (_GPIO_P_MODEH_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_DISABLED (_GPIO_P_MODEH_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUT (_GPIO_P_MODEH_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULL (_GPIO_P_MODEH_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULLFILTER (_GPIO_P_MODEH_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_PUSHPULL (_GPIO_P_MODEH_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_PUSHPULLALT (_GPIO_P_MODEH_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDOR (_GPIO_P_MODEH_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDAND (_GPIO_P_MODEH_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDFILTER (_GPIO_P_MODEH_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALT (_GPIO_P_MODEH_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEH_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEH_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_DEFAULT (_GPIO_P_MODEH_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_DISABLED (_GPIO_P_MODEH_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUT (_GPIO_P_MODEH_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUTPULL (_GPIO_P_MODEH_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUTPULLFILTER (_GPIO_P_MODEH_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_PUSHPULL (_GPIO_P_MODEH_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_PUSHPULLALT (_GPIO_P_MODEH_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDOR (_GPIO_P_MODEH_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDAND (_GPIO_P_MODEH_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDANDFILTER (_GPIO_P_MODEH_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALT (_GPIO_P_MODEH_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEH_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEH_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_DEFAULT (_GPIO_P_MODEH_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_DISABLED (_GPIO_P_MODEH_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_INPUT (_GPIO_P_MODEH_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_INPUTPULL (_GPIO_P_MODEH_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_INPUTPULLFILTER (_GPIO_P_MODEH_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_PUSHPULL (_GPIO_P_MODEH_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_PUSHPULLALT (_GPIO_P_MODEH_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_WIREDOR (_GPIO_P_MODEH_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDAND (_GPIO_P_MODEH_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_WIREDANDFILTER (_GPIO_P_MODEH_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDPULLUP (_GPIO_P_MODEH_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDALT (_GPIO_P_MODEH_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ /* Bit fields for GPIO_P DOUT */ -#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ -#define _GPIO_P_DOUT_MASK 0x000007FFUL /**< Mask for GPIO_P_DOUT */ -#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ -#define _GPIO_P_DOUT_DOUT_MASK 0x7FFUL /**< Bit mask for GPIO_DOUT */ -#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ -#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_MASK 0x000007FFUL /**< Mask for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_MASK 0x7FFUL /**< Bit mask for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ +#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ /* Bit fields for GPIO_P DIN */ -#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ -#define _GPIO_P_DIN_MASK 0x000007FFUL /**< Mask for GPIO_P_DIN */ -#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ -#define _GPIO_P_DIN_DIN_MASK 0x7FFUL /**< Bit mask for GPIO_DIN */ -#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ -#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ +#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ +#define _GPIO_P_DIN_MASK 0x000007FFUL /**< Mask for GPIO_P_DIN */ +#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_MASK 0x7FFUL /**< Bit mask for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ +#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ /** @} End of group Parts */ - #endif // GPIO_PORT_H diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_hfrco.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_hfrco.h index cb1e7bd016..f7af665155 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_hfrco.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_HFRCO_H #define EFR32SG23_HFRCO_H - #define HFRCO_HAS_SET_CLEAR /**************************************************************************//** @@ -43,43 +42,42 @@ *****************************************************************************/ /** HFRCO Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP Version ID */ - __IOM uint32_t CTRL; /**< Ctrl Register */ - __IOM uint32_t CAL; /**< Calibration Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Lock Register */ - uint32_t RESERVED1[1016U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version ID */ - __IOM uint32_t CTRL_SET; /**< Ctrl Register */ - __IOM uint32_t CAL_SET; /**< Calibration Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Lock Register */ - uint32_t RESERVED3[1016U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ - __IOM uint32_t CTRL_CLR; /**< Ctrl Register */ - __IOM uint32_t CAL_CLR; /**< Calibration Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Lock Register */ - uint32_t RESERVED5[1016U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ - __IOM uint32_t CTRL_TGL; /**< Ctrl Register */ - __IOM uint32_t CAL_TGL; /**< Calibration Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Lock Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t CTRL; /**< Ctrl Register */ + __IOM uint32_t CAL; /**< Calibration Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED1[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t CTRL_SET; /**< Ctrl Register */ + __IOM uint32_t CAL_SET; /**< Calibration Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED3[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t CTRL_CLR; /**< Ctrl Register */ + __IOM uint32_t CAL_CLR; /**< Calibration Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED5[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t CTRL_TGL; /**< Ctrl Register */ + __IOM uint32_t CAL_TGL; /**< Calibration Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ } HFRCO_TypeDef; /** @} End of group EFR32SG23_HFRCO */ @@ -91,135 +89,135 @@ typedef struct *****************************************************************************/ /* Bit fields for HFRCO IPVERSION */ -#define _HFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFRCO_IPVERSION */ -#define _HFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFRCO_IPVERSION */ -#define _HFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFRCO_IPVERSION */ -#define _HFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFRCO_IPVERSION */ -#define _HFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_IPVERSION */ -#define HFRCO_IPVERSION_IPVERSION_DEFAULT (_HFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_IPVERSION */ +#define HFRCO_IPVERSION_IPVERSION_DEFAULT (_HFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IPVERSION */ /* Bit fields for HFRCO CTRL */ -#define _HFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for HFRCO_CTRL */ -#define _HFRCO_CTRL_MASK 0x00000007UL /**< Mask for HFRCO_CTRL */ -#define HFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ -#define _HFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFRCO_FORCEEN */ -#define _HFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFRCO_FORCEEN */ -#define _HFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_FORCEEN_DEFAULT (_HFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand */ -#define _HFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFRCO_DISONDEMAND */ -#define _HFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFRCO_DISONDEMAND */ -#define _HFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_DISONDEMAND_DEFAULT (_HFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_EM23ONDEMAND (0x1UL << 2) /**< EM23 On-demand */ -#define _HFRCO_CTRL_EM23ONDEMAND_SHIFT 2 /**< Shift value for HFRCO_EM23ONDEMAND */ -#define _HFRCO_CTRL_EM23ONDEMAND_MASK 0x4UL /**< Bit mask for HFRCO_EM23ONDEMAND */ -#define _HFRCO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_EM23ONDEMAND_DEFAULT (_HFRCO_CTRL_EM23ONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define _HFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for HFRCO_CTRL */ +#define _HFRCO_CTRL_MASK 0x00000007UL /**< Mask for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _HFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN_DEFAULT (_HFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand */ +#define _HFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND_DEFAULT (_HFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_EM23ONDEMAND (0x1UL << 2) /**< EM23 On-demand */ +#define _HFRCO_CTRL_EM23ONDEMAND_SHIFT 2 /**< Shift value for HFRCO_EM23ONDEMAND */ +#define _HFRCO_CTRL_EM23ONDEMAND_MASK 0x4UL /**< Bit mask for HFRCO_EM23ONDEMAND */ +#define _HFRCO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_EM23ONDEMAND_DEFAULT (_HFRCO_CTRL_EM23ONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_CTRL */ /* Bit fields for HFRCO CAL */ -#define _HFRCO_CAL_RESETVALUE 0xA8689F7FUL /**< Default value for HFRCO_CAL */ -#define _HFRCO_CAL_MASK 0xFFFFBF7FUL /**< Mask for HFRCO_CAL */ -#define _HFRCO_CAL_TUNING_SHIFT 0 /**< Shift value for HFRCO_TUNING */ -#define _HFRCO_CAL_TUNING_MASK 0x7FUL /**< Bit mask for HFRCO_TUNING */ -#define _HFRCO_CAL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_TUNING_DEFAULT (_HFRCO_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_FINETUNING_SHIFT 8 /**< Shift value for HFRCO_FINETUNING */ -#define _HFRCO_CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for HFRCO_FINETUNING */ -#define _HFRCO_CAL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_FINETUNING_DEFAULT (_HFRCO_CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_LDOHP (0x1UL << 15) /**< LDO High Power Mode */ -#define _HFRCO_CAL_LDOHP_SHIFT 15 /**< Shift value for HFRCO_LDOHP */ -#define _HFRCO_CAL_LDOHP_MASK 0x8000UL /**< Bit mask for HFRCO_LDOHP */ -#define _HFRCO_CAL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_LDOHP_DEFAULT (_HFRCO_CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_FREQRANGE_SHIFT 16 /**< Shift value for HFRCO_FREQRANGE */ -#define _HFRCO_CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for HFRCO_FREQRANGE */ -#define _HFRCO_CAL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_FREQRANGE_DEFAULT (_HFRCO_CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_CMPBIAS_SHIFT 21 /**< Shift value for HFRCO_CMPBIAS */ -#define _HFRCO_CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for HFRCO_CMPBIAS */ -#define _HFRCO_CAL_CMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_CMPBIAS_DEFAULT (_HFRCO_CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_CLKDIV_SHIFT 24 /**< Shift value for HFRCO_CLKDIV */ -#define _HFRCO_CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for HFRCO_CLKDIV */ -#define _HFRCO_CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for HFRCO_CAL */ -#define _HFRCO_CAL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for HFRCO_CAL */ -#define _HFRCO_CAL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for HFRCO_CAL */ -#define HFRCO_CAL_CLKDIV_DEFAULT (_HFRCO_CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_CLKDIV_DIV1 (_HFRCO_CAL_CLKDIV_DIV1 << 24) /**< Shifted mode DIV1 for HFRCO_CAL */ -#define HFRCO_CAL_CLKDIV_DIV2 (_HFRCO_CAL_CLKDIV_DIV2 << 24) /**< Shifted mode DIV2 for HFRCO_CAL */ -#define HFRCO_CAL_CLKDIV_DIV4 (_HFRCO_CAL_CLKDIV_DIV4 << 24) /**< Shifted mode DIV4 for HFRCO_CAL */ -#define _HFRCO_CAL_CMPSEL_SHIFT 26 /**< Shift value for HFRCO_CMPSEL */ -#define _HFRCO_CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for HFRCO_CMPSEL */ -#define _HFRCO_CAL_CMPSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_CMPSEL_DEFAULT (_HFRCO_CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_IREFTC_SHIFT 28 /**< Shift value for HFRCO_IREFTC */ -#define _HFRCO_CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for HFRCO_IREFTC */ -#define _HFRCO_CAL_IREFTC_DEFAULT 0x0000000AUL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_IREFTC_DEFAULT (_HFRCO_CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_RESETVALUE 0xA8689F7FUL /**< Default value for HFRCO_CAL */ +#define _HFRCO_CAL_MASK 0xFFFFBF7FUL /**< Mask for HFRCO_CAL */ +#define _HFRCO_CAL_TUNING_SHIFT 0 /**< Shift value for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_MASK 0x7FUL /**< Bit mask for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_TUNING_DEFAULT (_HFRCO_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FINETUNING_SHIFT 8 /**< Shift value for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FINETUNING_DEFAULT (_HFRCO_CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP (0x1UL << 15) /**< LDO High Power Mode */ +#define _HFRCO_CAL_LDOHP_SHIFT 15 /**< Shift value for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_MASK 0x8000UL /**< Bit mask for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP_DEFAULT (_HFRCO_CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FREQRANGE_SHIFT 16 /**< Shift value for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FREQRANGE_DEFAULT (_HFRCO_CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CMPBIAS_SHIFT 21 /**< Shift value for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPBIAS_DEFAULT (_HFRCO_CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_SHIFT 24 /**< Shift value for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DEFAULT (_HFRCO_CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV1 (_HFRCO_CAL_CLKDIV_DIV1 << 24) /**< Shifted mode DIV1 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV2 (_HFRCO_CAL_CLKDIV_DIV2 << 24) /**< Shifted mode DIV2 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV4 (_HFRCO_CAL_CLKDIV_DIV4 << 24) /**< Shifted mode DIV4 for HFRCO_CAL */ +#define _HFRCO_CAL_CMPSEL_SHIFT 26 /**< Shift value for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPSEL_DEFAULT (_HFRCO_CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_IREFTC_SHIFT 28 /**< Shift value for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_DEFAULT 0x0000000AUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_IREFTC_DEFAULT (_HFRCO_CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for HFRCO_CAL */ /* Bit fields for HFRCO STATUS */ -#define _HFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFRCO_STATUS */ -#define _HFRCO_STATUS_MASK 0x80010007UL /**< Mask for HFRCO_STATUS */ -#define HFRCO_STATUS_RDY (0x1UL << 0) /**< Ready */ -#define _HFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ -#define _HFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ -#define _HFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_RDY_DEFAULT (_HFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_FREQBSY (0x1UL << 1) /**< Frequency Updating Busy */ -#define _HFRCO_STATUS_FREQBSY_SHIFT 1 /**< Shift value for HFRCO_FREQBSY */ -#define _HFRCO_STATUS_FREQBSY_MASK 0x2UL /**< Bit mask for HFRCO_FREQBSY */ -#define _HFRCO_STATUS_FREQBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_FREQBSY_DEFAULT (_HFRCO_STATUS_FREQBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_SYNCBUSY (0x1UL << 2) /**< Synchronization Busy */ -#define _HFRCO_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for HFRCO_SYNCBUSY */ -#define _HFRCO_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for HFRCO_SYNCBUSY */ -#define _HFRCO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_SYNCBUSY_DEFAULT (_HFRCO_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ -#define _HFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for HFRCO_ENS */ -#define _HFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFRCO_ENS */ -#define _HFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_ENS_DEFAULT (_HFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ -#define _HFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFRCO_LOCK */ -#define _HFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFRCO_LOCK */ -#define _HFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define _HFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFRCO_STATUS */ -#define _HFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFRCO_STATUS */ -#define HFRCO_STATUS_LOCK_DEFAULT (_HFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_LOCK_UNLOCKED (_HFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFRCO_STATUS */ -#define HFRCO_STATUS_LOCK_LOCKED (_HFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFRCO_STATUS */ +#define _HFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFRCO_STATUS */ +#define _HFRCO_STATUS_MASK 0x80010007UL /**< Mask for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY (0x1UL << 0) /**< Ready */ +#define _HFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY_DEFAULT (_HFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY (0x1UL << 1) /**< Frequency Updating Busy */ +#define _HFRCO_STATUS_FREQBSY_SHIFT 1 /**< Shift value for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_MASK 0x2UL /**< Bit mask for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY_DEFAULT (_HFRCO_STATUS_FREQBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY (0x1UL << 2) /**< Synchronization Busy */ +#define _HFRCO_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY_DEFAULT (_HFRCO_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _HFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS_DEFAULT (_HFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _HFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_DEFAULT (_HFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_UNLOCKED (_HFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_LOCKED (_HFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFRCO_STATUS */ /* Bit fields for HFRCO IF */ -#define _HFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IF */ -#define _HFRCO_IF_MASK 0x00000001UL /**< Mask for HFRCO_IF */ -#define HFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ -#define _HFRCO_IF_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ -#define _HFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ -#define _HFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IF */ -#define HFRCO_IF_RDY_DEFAULT (_HFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IF */ +#define _HFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IF */ +#define _HFRCO_IF_MASK 0x00000001UL /**< Mask for HFRCO_IF */ +#define HFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _HFRCO_IF_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IF */ +#define HFRCO_IF_RDY_DEFAULT (_HFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IF */ /* Bit fields for HFRCO IEN */ -#define _HFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IEN */ -#define _HFRCO_IEN_MASK 0x00000001UL /**< Mask for HFRCO_IEN */ -#define HFRCO_IEN_RDY (0x1UL << 0) /**< RDY Interrupt Enable */ -#define _HFRCO_IEN_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ -#define _HFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ -#define _HFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IEN */ -#define HFRCO_IEN_RDY_DEFAULT (_HFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IEN */ +#define _HFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IEN */ +#define _HFRCO_IEN_MASK 0x00000001UL /**< Mask for HFRCO_IEN */ +#define HFRCO_IEN_RDY (0x1UL << 0) /**< RDY Interrupt Enable */ +#define _HFRCO_IEN_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IEN */ +#define HFRCO_IEN_RDY_DEFAULT (_HFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IEN */ /* Bit fields for HFRCO LOCK */ -#define _HFRCO_LOCK_RESETVALUE 0x00008195UL /**< Default value for HFRCO_LOCK */ -#define _HFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFRCO_LOCK */ -#define _HFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFRCO_LOCKKEY */ -#define _HFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFRCO_LOCKKEY */ -#define _HFRCO_LOCK_LOCKKEY_DEFAULT 0x00008195UL /**< Mode DEFAULT for HFRCO_LOCK */ -#define _HFRCO_LOCK_LOCKKEY_UNLOCK 0x00008195UL /**< Mode UNLOCK for HFRCO_LOCK */ -#define HFRCO_LOCK_LOCKKEY_DEFAULT (_HFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_LOCK */ -#define HFRCO_LOCK_LOCKKEY_UNLOCK (_HFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFRCO_LOCK */ +#define _HFRCO_LOCK_RESETVALUE 0x00008195UL /**< Default value for HFRCO_LOCK */ +#define _HFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_DEFAULT 0x00008195UL /**< Mode DEFAULT for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_UNLOCK 0x00008195UL /**< Mode UNLOCK for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_DEFAULT (_HFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_UNLOCK (_HFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFRCO_LOCK */ /** @} End of group EFR32SG23_HFRCO_BitFields */ /** @} End of group EFR32SG23_HFRCO */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_hfxo.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_hfxo.h index 5b9d3a7af0..10eeb26068 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_hfxo.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_HFXO_H #define EFR32SG23_HFXO_H - #define HFXO_HAS_SET_CLEAR /**************************************************************************//** @@ -43,95 +42,94 @@ *****************************************************************************/ /** HFXO Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version ID */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - __IOM uint32_t XTALCFG; /**< Crystal Configuration Register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t XTALCTRL; /**< Crystal Control Register */ - __IOM uint32_t XTALCTRL1; /**< BUFOUT Crystal Control Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IOM uint32_t CTRL; /**< Control Register */ - uint32_t RESERVED3[5U]; /**< Reserved for future use */ - __IOM uint32_t BUFOUTTRIM; /**< BUFOUT Trim Configuration Register */ - __IOM uint32_t BUFOUTCTRL; /**< BUFOUT Control Register */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t CMD; /**< Command Register */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - uint32_t RESERVED6[5U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED7[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - uint32_t RESERVED8[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - uint32_t RESERVED9[3U]; /**< Reserved for future use */ - __IOM uint32_t XTALCFG_SET; /**< Crystal Configuration Register */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - __IOM uint32_t XTALCTRL_SET; /**< Crystal Control Register */ - __IOM uint32_t XTALCTRL1_SET; /**< BUFOUT Crystal Control Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - uint32_t RESERVED11[1U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - uint32_t RESERVED12[5U]; /**< Reserved for future use */ - __IOM uint32_t BUFOUTTRIM_SET; /**< BUFOUT Trim Configuration Register */ - __IOM uint32_t BUFOUTCTRL_SET; /**< BUFOUT Control Register */ - uint32_t RESERVED13[2U]; /**< Reserved for future use */ - __IOM uint32_t CMD_SET; /**< Command Register */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - uint32_t RESERVED15[5U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED16[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - uint32_t RESERVED17[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - uint32_t RESERVED18[3U]; /**< Reserved for future use */ - __IOM uint32_t XTALCFG_CLR; /**< Crystal Configuration Register */ - uint32_t RESERVED19[1U]; /**< Reserved for future use */ - __IOM uint32_t XTALCTRL_CLR; /**< Crystal Control Register */ - __IOM uint32_t XTALCTRL1_CLR; /**< BUFOUT Crystal Control Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - uint32_t RESERVED20[1U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - uint32_t RESERVED21[5U]; /**< Reserved for future use */ - __IOM uint32_t BUFOUTTRIM_CLR; /**< BUFOUT Trim Configuration Register */ - __IOM uint32_t BUFOUTCTRL_CLR; /**< BUFOUT Control Register */ - uint32_t RESERVED22[2U]; /**< Reserved for future use */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - uint32_t RESERVED23[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - uint32_t RESERVED24[5U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED25[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - uint32_t RESERVED26[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - uint32_t RESERVED27[3U]; /**< Reserved for future use */ - __IOM uint32_t XTALCFG_TGL; /**< Crystal Configuration Register */ - uint32_t RESERVED28[1U]; /**< Reserved for future use */ - __IOM uint32_t XTALCTRL_TGL; /**< Crystal Control Register */ - __IOM uint32_t XTALCTRL1_TGL; /**< BUFOUT Crystal Control Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - uint32_t RESERVED29[1U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - uint32_t RESERVED30[5U]; /**< Reserved for future use */ - __IOM uint32_t BUFOUTTRIM_TGL; /**< BUFOUT Trim Configuration Register */ - __IOM uint32_t BUFOUTCTRL_TGL; /**< BUFOUT Control Register */ - uint32_t RESERVED31[2U]; /**< Reserved for future use */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - uint32_t RESERVED32[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - uint32_t RESERVED33[5U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED34[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG; /**< Crystal Configuration Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Control Register */ + uint32_t RESERVED3[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL; /**< BUFOUT Control Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED6[5U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED8[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED9[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_SET; /**< Crystal Configuration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_SET; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_SET; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + uint32_t RESERVED12[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_SET; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_SET; /**< BUFOUT Control Register */ + uint32_t RESERVED13[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED15[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED17[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_CLR; /**< Crystal Configuration Register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_CLR; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_CLR; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + uint32_t RESERVED21[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_CLR; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_CLR; /**< BUFOUT Control Register */ + uint32_t RESERVED22[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED24[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED25[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED26[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_TGL; /**< Crystal Configuration Register */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_TGL; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_TGL; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + uint32_t RESERVED30[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_TGL; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_TGL; /**< BUFOUT Control Register */ + uint32_t RESERVED31[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED33[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED34[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ } HFXO_TypeDef; /** @} End of group EFR32SG23_HFXO */ @@ -143,658 +141,658 @@ typedef struct *****************************************************************************/ /* Bit fields for HFXO IPVERSION */ -#define _HFXO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for HFXO_IPVERSION */ -#define _HFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFXO_IPVERSION */ -#define _HFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFXO_IPVERSION */ -#define _HFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFXO_IPVERSION */ -#define _HFXO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_IPVERSION */ -#define HFXO_IPVERSION_IPVERSION_DEFAULT (_HFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_IPVERSION */ +#define HFXO_IPVERSION_IPVERSION_DEFAULT (_HFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IPVERSION */ /* Bit fields for HFXO XTALCFG */ -#define _HFXO_XTALCFG_RESETVALUE 0x0BB00820UL /**< Default value for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_MASK 0x0FFFFFFFUL /**< Mask for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT 0 /**< Shift value for HFXO_COREBIASSTARTUPI */ -#define _HFXO_XTALCFG_COREBIASSTARTUPI_MASK 0x3FUL /**< Bit mask for HFXO_COREBIASSTARTUPI */ -#define _HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT 6 /**< Shift value for HFXO_COREBIASSTARTUP */ -#define _HFXO_XTALCFG_COREBIASSTARTUP_MASK 0xFC0UL /**< Bit mask for HFXO_COREBIASSTARTUP */ -#define _HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT 12 /**< Shift value for HFXO_CTUNEXISTARTUP */ -#define _HFXO_XTALCFG_CTUNEXISTARTUP_MASK 0xF000UL /**< Bit mask for HFXO_CTUNEXISTARTUP */ -#define _HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT 16 /**< Shift value for HFXO_CTUNEXOSTARTUP */ -#define _HFXO_XTALCFG_CTUNEXOSTARTUP_MASK 0xF0000UL /**< Bit mask for HFXO_CTUNEXOSTARTUP */ -#define _HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTEADY */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTEADY */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4US 0x00000000UL /**< Mode T4US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T16US 0x00000001UL /**< Mode T16US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T83US 0x00000003UL /**< Mode T83US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T125US 0x00000004UL /**< Mode T125US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T166US 0x00000005UL /**< Mode T166US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T208US 0x00000006UL /**< Mode T208US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T250US 0x00000007UL /**< Mode T250US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T333US 0x00000008UL /**< Mode T333US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T416US 0x00000009UL /**< Mode T416US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T500US 0x0000000AUL /**< Mode T500US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T666US 0x0000000BUL /**< Mode T666US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US 0x0000000DUL /**< Mode T1666US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US 0x0000000EUL /**< Mode T2500US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US 0x0000000FUL /**< Mode T4166US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT (_HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T4US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4US << 20) /**< Shifted mode T4US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T16US (_HFXO_XTALCFG_TIMEOUTSTEADY_T16US << 20) /**< Shifted mode T16US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T41US (_HFXO_XTALCFG_TIMEOUTSTEADY_T41US << 20) /**< Shifted mode T41US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T83US (_HFXO_XTALCFG_TIMEOUTSTEADY_T83US << 20) /**< Shifted mode T83US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T125US (_HFXO_XTALCFG_TIMEOUTSTEADY_T125US << 20) /**< Shifted mode T125US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T166US << 20) /**< Shifted mode T166US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T208US (_HFXO_XTALCFG_TIMEOUTSTEADY_T208US << 20) /**< Shifted mode T208US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T250US (_HFXO_XTALCFG_TIMEOUTSTEADY_T250US << 20) /**< Shifted mode T250US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T333US (_HFXO_XTALCFG_TIMEOUTSTEADY_T333US << 20) /**< Shifted mode T333US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T416US (_HFXO_XTALCFG_TIMEOUTSTEADY_T416US << 20) /**< Shifted mode T416US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T500US << 20) /**< Shifted mode T500US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T666US << 20) /**< Shifted mode T666US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T833US (_HFXO_XTALCFG_TIMEOUTSTEADY_T833US << 20) /**< Shifted mode T833US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T1666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T1666US << 20) /**< Shifted mode T1666US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T2500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T2500US << 20) /**< Shifted mode T2500US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T4166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4166US << 20) /**< Shifted mode T4166US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT 24 /**< Shift value for HFXO_TIMEOUTCBLSB */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_MASK 0xF000000UL /**< Bit mask for HFXO_TIMEOUTCBLSB */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T8US 0x00000000UL /**< Mode T8US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T20US 0x00000001UL /**< Mode T20US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T62US 0x00000003UL /**< Mode T62US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T83US 0x00000004UL /**< Mode T83US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T104US 0x00000005UL /**< Mode T104US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T125US 0x00000006UL /**< Mode T125US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T166US 0x00000007UL /**< Mode T166US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T208US 0x00000008UL /**< Mode T208US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T250US 0x00000009UL /**< Mode T250US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T333US 0x0000000AUL /**< Mode T333US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T416US 0x0000000BUL /**< Mode T416US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US 0x0000000DUL /**< Mode T1250US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US 0x0000000EUL /**< Mode T2083US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US 0x0000000FUL /**< Mode T3750US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT (_HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T8US (_HFXO_XTALCFG_TIMEOUTCBLSB_T8US << 24) /**< Shifted mode T8US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T20US (_HFXO_XTALCFG_TIMEOUTCBLSB_T20US << 24) /**< Shifted mode T20US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T41US (_HFXO_XTALCFG_TIMEOUTCBLSB_T41US << 24) /**< Shifted mode T41US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T62US (_HFXO_XTALCFG_TIMEOUTCBLSB_T62US << 24) /**< Shifted mode T62US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T83US (_HFXO_XTALCFG_TIMEOUTCBLSB_T83US << 24) /**< Shifted mode T83US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T104US (_HFXO_XTALCFG_TIMEOUTCBLSB_T104US << 24) /**< Shifted mode T104US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T125US (_HFXO_XTALCFG_TIMEOUTCBLSB_T125US << 24) /**< Shifted mode T125US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T166US (_HFXO_XTALCFG_TIMEOUTCBLSB_T166US << 24) /**< Shifted mode T166US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T208US (_HFXO_XTALCFG_TIMEOUTCBLSB_T208US << 24) /**< Shifted mode T208US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T250US << 24) /**< Shifted mode T250US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T333US (_HFXO_XTALCFG_TIMEOUTCBLSB_T333US << 24) /**< Shifted mode T333US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T416US (_HFXO_XTALCFG_TIMEOUTCBLSB_T416US << 24) /**< Shifted mode T416US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T833US (_HFXO_XTALCFG_TIMEOUTCBLSB_T833US << 24) /**< Shifted mode T833US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T1250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T1250US << 24) /**< Shifted mode T1250US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T2083US (_HFXO_XTALCFG_TIMEOUTCBLSB_T2083US << 24) /**< Shifted mode T2083US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T3750US (_HFXO_XTALCFG_TIMEOUTCBLSB_T3750US << 24) /**< Shifted mode T3750US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_RESETVALUE 0x0BB00820UL /**< Default value for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_MASK 0x0FFFFFFFUL /**< Mask for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT 0 /**< Shift value for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_MASK 0x3FUL /**< Bit mask for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT 6 /**< Shift value for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_MASK 0xFC0UL /**< Bit mask for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT 12 /**< Shift value for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_MASK 0xF000UL /**< Bit mask for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT 16 /**< Shift value for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_MASK 0xF0000UL /**< Bit mask for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4US 0x00000000UL /**< Mode T4US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T16US 0x00000001UL /**< Mode T16US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T83US 0x00000003UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T125US 0x00000004UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T166US 0x00000005UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T208US 0x00000006UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T250US 0x00000007UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T333US 0x00000008UL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T416US 0x00000009UL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T500US 0x0000000AUL /**< Mode T500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T666US 0x0000000BUL /**< Mode T666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US 0x0000000DUL /**< Mode T1666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US 0x0000000EUL /**< Mode T2500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US 0x0000000FUL /**< Mode T4166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT (_HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T4US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4US << 20) /**< Shifted mode T4US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T16US (_HFXO_XTALCFG_TIMEOUTSTEADY_T16US << 20) /**< Shifted mode T16US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T41US (_HFXO_XTALCFG_TIMEOUTSTEADY_T41US << 20) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T83US (_HFXO_XTALCFG_TIMEOUTSTEADY_T83US << 20) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T125US (_HFXO_XTALCFG_TIMEOUTSTEADY_T125US << 20) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T166US << 20) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T208US (_HFXO_XTALCFG_TIMEOUTSTEADY_T208US << 20) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T250US (_HFXO_XTALCFG_TIMEOUTSTEADY_T250US << 20) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T333US (_HFXO_XTALCFG_TIMEOUTSTEADY_T333US << 20) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T416US (_HFXO_XTALCFG_TIMEOUTSTEADY_T416US << 20) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T500US << 20) /**< Shifted mode T500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T666US << 20) /**< Shifted mode T666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T833US (_HFXO_XTALCFG_TIMEOUTSTEADY_T833US << 20) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T1666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T1666US << 20) /**< Shifted mode T1666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T2500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T2500US << 20) /**< Shifted mode T2500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T4166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4166US << 20) /**< Shifted mode T4166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT 24 /**< Shift value for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_MASK 0xF000000UL /**< Bit mask for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T8US 0x00000000UL /**< Mode T8US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T20US 0x00000001UL /**< Mode T20US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T62US 0x00000003UL /**< Mode T62US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T83US 0x00000004UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T104US 0x00000005UL /**< Mode T104US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T125US 0x00000006UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T166US 0x00000007UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T208US 0x00000008UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T250US 0x00000009UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T333US 0x0000000AUL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T416US 0x0000000BUL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US 0x0000000DUL /**< Mode T1250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US 0x0000000EUL /**< Mode T2083US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US 0x0000000FUL /**< Mode T3750US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT (_HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T8US (_HFXO_XTALCFG_TIMEOUTCBLSB_T8US << 24) /**< Shifted mode T8US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T20US (_HFXO_XTALCFG_TIMEOUTCBLSB_T20US << 24) /**< Shifted mode T20US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T41US (_HFXO_XTALCFG_TIMEOUTCBLSB_T41US << 24) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T62US (_HFXO_XTALCFG_TIMEOUTCBLSB_T62US << 24) /**< Shifted mode T62US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T83US (_HFXO_XTALCFG_TIMEOUTCBLSB_T83US << 24) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T104US (_HFXO_XTALCFG_TIMEOUTCBLSB_T104US << 24) /**< Shifted mode T104US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T125US (_HFXO_XTALCFG_TIMEOUTCBLSB_T125US << 24) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T166US (_HFXO_XTALCFG_TIMEOUTCBLSB_T166US << 24) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T208US (_HFXO_XTALCFG_TIMEOUTCBLSB_T208US << 24) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T250US << 24) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T333US (_HFXO_XTALCFG_TIMEOUTCBLSB_T333US << 24) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T416US (_HFXO_XTALCFG_TIMEOUTCBLSB_T416US << 24) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T833US (_HFXO_XTALCFG_TIMEOUTCBLSB_T833US << 24) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T1250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T1250US << 24) /**< Shifted mode T1250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T2083US (_HFXO_XTALCFG_TIMEOUTCBLSB_T2083US << 24) /**< Shifted mode T2083US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T3750US (_HFXO_XTALCFG_TIMEOUTCBLSB_T3750US << 24) /**< Shifted mode T3750US for HFXO_XTALCFG */ /* Bit fields for HFXO XTALCTRL */ -#define _HFXO_XTALCTRL_RESETVALUE 0x033C3C3CUL /**< Default value for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_MASK 0x8FFFFFFFUL /**< Mask for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREBIASANA_SHIFT 0 /**< Shift value for HFXO_COREBIASANA */ -#define _HFXO_XTALCTRL_COREBIASANA_MASK 0xFFUL /**< Bit mask for HFXO_COREBIASANA */ -#define _HFXO_XTALCTRL_COREBIASANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREBIASANA_DEFAULT (_HFXO_XTALCTRL_COREBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEXIANA_SHIFT 8 /**< Shift value for HFXO_CTUNEXIANA */ -#define _HFXO_XTALCTRL_CTUNEXIANA_MASK 0xFF00UL /**< Bit mask for HFXO_CTUNEXIANA */ -#define _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEXIANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEXOANA_SHIFT 16 /**< Shift value for HFXO_CTUNEXOANA */ -#define _HFXO_XTALCTRL_CTUNEXOANA_MASK 0xFF0000UL /**< Bit mask for HFXO_CTUNEXOANA */ -#define _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEXOANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT 24 /**< Shift value for HFXO_CTUNEFIXANA */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_MASK 0x3000000UL /**< Bit mask for HFXO_CTUNEFIXANA */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_XI 0x00000001UL /**< Mode XI for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_XO 0x00000002UL /**< Mode XO for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_BOTH 0x00000003UL /**< Mode BOTH for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT (_HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_NONE (_HFXO_XTALCTRL_CTUNEFIXANA_NONE << 24) /**< Shifted mode NONE for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_XI (_HFXO_XTALCTRL_CTUNEFIXANA_XI << 24) /**< Shifted mode XI for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_XO (_HFXO_XTALCTRL_CTUNEFIXANA_XO << 24) /**< Shifted mode XO for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_BOTH (_HFXO_XTALCTRL_CTUNEFIXANA_BOTH << 24) /**< Shifted mode BOTH for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_SHIFT 26 /**< Shift value for HFXO_COREDGENANA */ -#define _HFXO_XTALCTRL_COREDGENANA_MASK 0xC000000UL /**< Bit mask for HFXO_COREDGENANA */ -#define _HFXO_XTALCTRL_COREDGENANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_DGEN33 0x00000001UL /**< Mode DGEN33 for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_DGEN50 0x00000002UL /**< Mode DGEN50 for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_DGEN100 0x00000003UL /**< Mode DGEN100 for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_DEFAULT (_HFXO_XTALCTRL_COREDGENANA_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_NONE (_HFXO_XTALCTRL_COREDGENANA_NONE << 26) /**< Shifted mode NONE for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_DGEN33 (_HFXO_XTALCTRL_COREDGENANA_DGEN33 << 26) /**< Shifted mode DGEN33 for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_DGEN50 (_HFXO_XTALCTRL_COREDGENANA_DGEN50 << 26) /**< Shifted mode DGEN50 for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_DGEN100 (_HFXO_XTALCTRL_COREDGENANA_DGEN100 << 26) /**< Shifted mode DGEN100 for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_SKIPCOREBIASOPT (0x1UL << 31) /**< Skip Core Bias Optimization */ -#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_SHIFT 31 /**< Shift value for HFXO_SKIPCOREBIASOPT */ -#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK 0x80000000UL /**< Bit mask for HFXO_SKIPCOREBIASOPT */ -#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT (_HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_RESETVALUE 0x033C3C3CUL /**< Default value for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_MASK 0x8FFFFFFFUL /**< Mask for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREBIASANA_SHIFT 0 /**< Shift value for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_MASK 0xFFUL /**< Bit mask for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREBIASANA_DEFAULT (_HFXO_XTALCTRL_COREBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXIANA_SHIFT 8 /**< Shift value for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_MASK 0xFF00UL /**< Bit mask for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXIANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXOANA_SHIFT 16 /**< Shift value for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_MASK 0xFF0000UL /**< Bit mask for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXOANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT 24 /**< Shift value for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_MASK 0x3000000UL /**< Bit mask for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XI 0x00000001UL /**< Mode XI for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XO 0x00000002UL /**< Mode XO for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_BOTH 0x00000003UL /**< Mode BOTH for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT (_HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_NONE (_HFXO_XTALCTRL_CTUNEFIXANA_NONE << 24) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XI (_HFXO_XTALCTRL_CTUNEFIXANA_XI << 24) /**< Shifted mode XI for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XO (_HFXO_XTALCTRL_CTUNEFIXANA_XO << 24) /**< Shifted mode XO for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_BOTH (_HFXO_XTALCTRL_CTUNEFIXANA_BOTH << 24) /**< Shifted mode BOTH for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_SHIFT 26 /**< Shift value for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_MASK 0xC000000UL /**< Bit mask for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN33 0x00000001UL /**< Mode DGEN33 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN50 0x00000002UL /**< Mode DGEN50 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN100 0x00000003UL /**< Mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DEFAULT (_HFXO_XTALCTRL_COREDGENANA_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_NONE (_HFXO_XTALCTRL_COREDGENANA_NONE << 26) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN33 (_HFXO_XTALCTRL_COREDGENANA_DGEN33 << 26) /**< Shifted mode DGEN33 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN50 (_HFXO_XTALCTRL_COREDGENANA_DGEN50 << 26) /**< Shifted mode DGEN50 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN100 (_HFXO_XTALCTRL_COREDGENANA_DGEN100 << 26) /**< Shifted mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT (0x1UL << 31) /**< Skip Core Bias Optimization */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_SHIFT 31 /**< Shift value for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK 0x80000000UL /**< Bit mask for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT (_HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ /* Bit fields for HFXO XTALCTRL1 */ -#define _HFXO_XTALCTRL1_RESETVALUE 0x0000003CUL /**< Default value for HFXO_XTALCTRL1 */ -#define _HFXO_XTALCTRL1_MASK 0x000000FFUL /**< Mask for HFXO_XTALCTRL1 */ -#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_SHIFT 0 /**< Shift value for HFXO_CTUNEXIBUFOUTANA */ -#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_MASK 0xFFUL /**< Bit mask for HFXO_CTUNEXIBUFOUTANA */ -#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL1 */ -#define HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT (_HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL1 */ +#define _HFXO_XTALCTRL1_RESETVALUE 0x0000003CUL /**< Default value for HFXO_XTALCTRL1 */ +#define _HFXO_XTALCTRL1_MASK 0x000000FFUL /**< Mask for HFXO_XTALCTRL1 */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_SHIFT 0 /**< Shift value for HFXO_CTUNEXIBUFOUTANA */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_MASK 0xFFUL /**< Bit mask for HFXO_CTUNEXIBUFOUTANA */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL1 */ +#define HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT (_HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL1 */ /* Bit fields for HFXO CFG */ -#define _HFXO_CFG_RESETVALUE 0x10000000UL /**< Default value for HFXO_CFG */ -#define _HFXO_CFG_MASK 0xB000000FUL /**< Mask for HFXO_CFG */ -#define _HFXO_CFG_MODE_SHIFT 0 /**< Shift value for HFXO_MODE */ -#define _HFXO_CFG_MODE_MASK 0x3UL /**< Bit mask for HFXO_MODE */ -#define _HFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ -#define _HFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for HFXO_CFG */ -#define _HFXO_CFG_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for HFXO_CFG */ -#define _HFXO_CFG_MODE_EXTCLKPKDET 0x00000002UL /**< Mode EXTCLKPKDET for HFXO_CFG */ -#define HFXO_CFG_MODE_DEFAULT (_HFXO_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_MODE_XTAL (_HFXO_CFG_MODE_XTAL << 0) /**< Shifted mode XTAL for HFXO_CFG */ -#define HFXO_CFG_MODE_EXTCLK (_HFXO_CFG_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for HFXO_CFG */ -#define HFXO_CFG_MODE_EXTCLKPKDET (_HFXO_CFG_MODE_EXTCLKPKDET << 0) /**< Shifted mode EXTCLKPKDET for HFXO_CFG */ -#define HFXO_CFG_ENXIDCBIASANA (0x1UL << 2) /**< Enable XI Internal DC Bias */ -#define _HFXO_CFG_ENXIDCBIASANA_SHIFT 2 /**< Shift value for HFXO_ENXIDCBIASANA */ -#define _HFXO_CFG_ENXIDCBIASANA_MASK 0x4UL /**< Bit mask for HFXO_ENXIDCBIASANA */ -#define _HFXO_CFG_ENXIDCBIASANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_ENXIDCBIASANA_DEFAULT (_HFXO_CFG_ENXIDCBIASANA_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_SQBUFSCHTRGANA (0x1UL << 3) /**< Squaring Buffer Schmitt Trigger */ -#define _HFXO_CFG_SQBUFSCHTRGANA_SHIFT 3 /**< Shift value for HFXO_SQBUFSCHTRGANA */ -#define _HFXO_CFG_SQBUFSCHTRGANA_MASK 0x8UL /**< Bit mask for HFXO_SQBUFSCHTRGANA */ -#define _HFXO_CFG_SQBUFSCHTRGANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ -#define _HFXO_CFG_SQBUFSCHTRGANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CFG */ -#define _HFXO_CFG_SQBUFSCHTRGANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CFG */ -#define HFXO_CFG_SQBUFSCHTRGANA_DEFAULT (_HFXO_CFG_SQBUFSCHTRGANA_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_SQBUFSCHTRGANA_DISABLE (_HFXO_CFG_SQBUFSCHTRGANA_DISABLE << 3) /**< Shifted mode DISABLE for HFXO_CFG */ -#define HFXO_CFG_SQBUFSCHTRGANA_ENABLE (_HFXO_CFG_SQBUFSCHTRGANA_ENABLE << 3) /**< Shifted mode ENABLE for HFXO_CFG */ -#define HFXO_CFG_FORCELFTIMEOUT (0x1UL << 28) /**< Force Low Frequency Timeout */ -#define _HFXO_CFG_FORCELFTIMEOUT_SHIFT 28 /**< Shift value for HFXO_FORCELFTIMEOUT */ -#define _HFXO_CFG_FORCELFTIMEOUT_MASK 0x10000000UL /**< Bit mask for HFXO_FORCELFTIMEOUT */ -#define _HFXO_CFG_FORCELFTIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_FORCELFTIMEOUT_DEFAULT (_HFXO_CFG_FORCELFTIMEOUT_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_RESETVALUE 0x10000000UL /**< Default value for HFXO_CFG */ +#define _HFXO_CFG_MASK 0xB000000FUL /**< Mask for HFXO_CFG */ +#define _HFXO_CFG_MODE_SHIFT 0 /**< Shift value for HFXO_MODE */ +#define _HFXO_CFG_MODE_MASK 0x3UL /**< Bit mask for HFXO_MODE */ +#define _HFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for HFXO_CFG */ +#define _HFXO_CFG_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for HFXO_CFG */ +#define _HFXO_CFG_MODE_EXTCLKPKDET 0x00000002UL /**< Mode EXTCLKPKDET for HFXO_CFG */ +#define HFXO_CFG_MODE_DEFAULT (_HFXO_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_MODE_XTAL (_HFXO_CFG_MODE_XTAL << 0) /**< Shifted mode XTAL for HFXO_CFG */ +#define HFXO_CFG_MODE_EXTCLK (_HFXO_CFG_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for HFXO_CFG */ +#define HFXO_CFG_MODE_EXTCLKPKDET (_HFXO_CFG_MODE_EXTCLKPKDET << 0) /**< Shifted mode EXTCLKPKDET for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA (0x1UL << 2) /**< Enable XI Internal DC Bias */ +#define _HFXO_CFG_ENXIDCBIASANA_SHIFT 2 /**< Shift value for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_MASK 0x4UL /**< Bit mask for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA_DEFAULT (_HFXO_CFG_ENXIDCBIASANA_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA (0x1UL << 3) /**< Squaring Buffer Schmitt Trigger */ +#define _HFXO_CFG_SQBUFSCHTRGANA_SHIFT 3 /**< Shift value for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_MASK 0x8UL /**< Bit mask for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DEFAULT (_HFXO_CFG_SQBUFSCHTRGANA_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DISABLE (_HFXO_CFG_SQBUFSCHTRGANA_DISABLE << 3) /**< Shifted mode DISABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_ENABLE (_HFXO_CFG_SQBUFSCHTRGANA_ENABLE << 3) /**< Shifted mode ENABLE for HFXO_CFG */ +#define HFXO_CFG_FORCELFTIMEOUT (0x1UL << 28) /**< Force Low Frequency Timeout */ +#define _HFXO_CFG_FORCELFTIMEOUT_SHIFT 28 /**< Shift value for HFXO_FORCELFTIMEOUT */ +#define _HFXO_CFG_FORCELFTIMEOUT_MASK 0x10000000UL /**< Bit mask for HFXO_FORCELFTIMEOUT */ +#define _HFXO_CFG_FORCELFTIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_FORCELFTIMEOUT_DEFAULT (_HFXO_CFG_FORCELFTIMEOUT_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_CFG */ /* Bit fields for HFXO CTRL */ -#define _HFXO_CTRL_RESETVALUE 0x07000040UL /**< Default value for HFXO_CTRL */ -#define _HFXO_CTRL_MASK 0x8707FF7DUL /**< Mask for HFXO_CTRL */ -#define HFXO_CTRL_BUFOUTFREEZE (0x1UL << 0) /**< Freeze BUFOUT Controls */ -#define _HFXO_CTRL_BUFOUTFREEZE_SHIFT 0 /**< Shift value for HFXO_BUFOUTFREEZE */ -#define _HFXO_CTRL_BUFOUTFREEZE_MASK 0x1UL /**< Bit mask for HFXO_BUFOUTFREEZE */ -#define _HFXO_CTRL_BUFOUTFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_BUFOUTFREEZE_DEFAULT (_HFXO_CTRL_BUFOUTFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_KEEPWARM (0x1UL << 2) /**< Keep Warm */ -#define _HFXO_CTRL_KEEPWARM_SHIFT 2 /**< Shift value for HFXO_KEEPWARM */ -#define _HFXO_CTRL_KEEPWARM_MASK 0x4UL /**< Bit mask for HFXO_KEEPWARM */ -#define _HFXO_CTRL_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_KEEPWARM_DEFAULT (_HFXO_CTRL_KEEPWARM_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_EM23ONDEMAND (0x1UL << 3) /**< On-demand During EM23 */ -#define _HFXO_CTRL_EM23ONDEMAND_SHIFT 3 /**< Shift value for HFXO_EM23ONDEMAND */ -#define _HFXO_CTRL_EM23ONDEMAND_MASK 0x8UL /**< Bit mask for HFXO_EM23ONDEMAND */ -#define _HFXO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_EM23ONDEMAND_DEFAULT (_HFXO_CTRL_EM23ONDEMAND_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXI2GNDANA (0x1UL << 4) /**< Force XI Pin to Ground */ -#define _HFXO_CTRL_FORCEXI2GNDANA_SHIFT 4 /**< Shift value for HFXO_FORCEXI2GNDANA */ -#define _HFXO_CTRL_FORCEXI2GNDANA_MASK 0x10UL /**< Bit mask for HFXO_FORCEXI2GNDANA */ -#define _HFXO_CTRL_FORCEXI2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define _HFXO_CTRL_FORCEXI2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ -#define _HFXO_CTRL_FORCEXI2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXI2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXI2GNDANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXI2GNDANA_DISABLE (_HFXO_CTRL_FORCEXI2GNDANA_DISABLE << 4) /**< Shifted mode DISABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXI2GNDANA_ENABLE (_HFXO_CTRL_FORCEXI2GNDANA_ENABLE << 4) /**< Shifted mode ENABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXO2GNDANA (0x1UL << 5) /**< Force XO Pin to Ground */ -#define _HFXO_CTRL_FORCEXO2GNDANA_SHIFT 5 /**< Shift value for HFXO_FORCEXO2GNDANA */ -#define _HFXO_CTRL_FORCEXO2GNDANA_MASK 0x20UL /**< Bit mask for HFXO_FORCEXO2GNDANA */ -#define _HFXO_CTRL_FORCEXO2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define _HFXO_CTRL_FORCEXO2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ -#define _HFXO_CTRL_FORCEXO2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXO2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXO2GNDANA_DEFAULT << 5) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXO2GNDANA_DISABLE (_HFXO_CTRL_FORCEXO2GNDANA_DISABLE << 5) /**< Shifted mode DISABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXO2GNDANA_ENABLE (_HFXO_CTRL_FORCEXO2GNDANA_ENABLE << 5) /**< Shifted mode ENABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCECTUNEMAX (0x1UL << 6) /**< Force Tuning Cap to Max Value */ -#define _HFXO_CTRL_FORCECTUNEMAX_SHIFT 6 /**< Shift value for HFXO_FORCECTUNEMAX */ -#define _HFXO_CTRL_FORCECTUNEMAX_MASK 0x40UL /**< Bit mask for HFXO_FORCECTUNEMAX */ -#define _HFXO_CTRL_FORCECTUNEMAX_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCECTUNEMAX_DEFAULT (_HFXO_CTRL_FORCECTUNEMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_SHIFT 8 /**< Shift value for HFXO_PRSSTATUSSEL0 */ -#define _HFXO_CTRL_PRSSTATUSSEL0_MASK 0xF00UL /**< Bit mask for HFXO_PRSSTATUSSEL0 */ -#define _HFXO_CTRL_PRSSTATUSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL0_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_DISABLED (_HFXO_CTRL_PRSSTATUSSEL0_DISABLED << 8) /**< Shifted mode DISABLED for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_ENS (_HFXO_CTRL_PRSSTATUSSEL0_ENS << 8) /**< Shifted mode ENS for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY << 8) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_RDY (_HFXO_CTRL_PRSSTATUSSEL0_RDY << 8) /**< Shifted mode RDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL0_PRSRDY << 8) /**< Shifted mode PRSRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY << 8) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_HWREQ (_HFXO_CTRL_PRSSTATUSSEL0_HWREQ << 8) /**< Shifted mode HWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ << 8) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ << 8) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_SHIFT 12 /**< Shift value for HFXO_PRSSTATUSSEL1 */ -#define _HFXO_CTRL_PRSSTATUSSEL1_MASK 0xF000UL /**< Bit mask for HFXO_PRSSTATUSSEL1 */ -#define _HFXO_CTRL_PRSSTATUSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL1_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_DISABLED (_HFXO_CTRL_PRSSTATUSSEL1_DISABLED << 12) /**< Shifted mode DISABLED for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_ENS (_HFXO_CTRL_PRSSTATUSSEL1_ENS << 12) /**< Shifted mode ENS for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY << 12) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_RDY (_HFXO_CTRL_PRSSTATUSSEL1_RDY << 12) /**< Shifted mode RDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL1_PRSRDY << 12) /**< Shifted mode PRSRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY << 12) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_HWREQ (_HFXO_CTRL_PRSSTATUSSEL1_HWREQ << 12) /**< Shifted mode HWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ << 12) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ << 12) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ -#define HFXO_CTRL_FORCEEN (0x1UL << 16) /**< Force Digital Clock Request */ -#define _HFXO_CTRL_FORCEEN_SHIFT 16 /**< Shift value for HFXO_FORCEEN */ -#define _HFXO_CTRL_FORCEEN_MASK 0x10000UL /**< Bit mask for HFXO_FORCEEN */ -#define _HFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEEN_DEFAULT (_HFXO_CTRL_FORCEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEENPRS (0x1UL << 17) /**< Force PRS Oscillator Request */ -#define _HFXO_CTRL_FORCEENPRS_SHIFT 17 /**< Shift value for HFXO_FORCEENPRS */ -#define _HFXO_CTRL_FORCEENPRS_MASK 0x20000UL /**< Bit mask for HFXO_FORCEENPRS */ -#define _HFXO_CTRL_FORCEENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEENPRS_DEFAULT (_HFXO_CTRL_FORCEENPRS_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEENBUFOUT (0x1UL << 18) /**< Force BUFOUT Request */ -#define _HFXO_CTRL_FORCEENBUFOUT_SHIFT 18 /**< Shift value for HFXO_FORCEENBUFOUT */ -#define _HFXO_CTRL_FORCEENBUFOUT_MASK 0x40000UL /**< Bit mask for HFXO_FORCEENBUFOUT */ -#define _HFXO_CTRL_FORCEENBUFOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEENBUFOUT_DEFAULT (_HFXO_CTRL_FORCEENBUFOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMAND (0x1UL << 24) /**< Disable On-demand For Digital Clock */ -#define _HFXO_CTRL_DISONDEMAND_SHIFT 24 /**< Shift value for HFXO_DISONDEMAND */ -#define _HFXO_CTRL_DISONDEMAND_MASK 0x1000000UL /**< Bit mask for HFXO_DISONDEMAND */ -#define _HFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMAND_DEFAULT (_HFXO_CTRL_DISONDEMAND_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMANDPRS (0x1UL << 25) /**< Disable On-demand For PRS */ -#define _HFXO_CTRL_DISONDEMANDPRS_SHIFT 25 /**< Shift value for HFXO_DISONDEMANDPRS */ -#define _HFXO_CTRL_DISONDEMANDPRS_MASK 0x2000000UL /**< Bit mask for HFXO_DISONDEMANDPRS */ -#define _HFXO_CTRL_DISONDEMANDPRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMANDPRS_DEFAULT (_HFXO_CTRL_DISONDEMANDPRS_DEFAULT << 25) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMANDBUFOUT (0x1UL << 26) /**< Disable On-demand For BUFOUT */ -#define _HFXO_CTRL_DISONDEMANDBUFOUT_SHIFT 26 /**< Shift value for HFXO_DISONDEMANDBUFOUT */ -#define _HFXO_CTRL_DISONDEMANDBUFOUT_MASK 0x4000000UL /**< Bit mask for HFXO_DISONDEMANDBUFOUT */ -#define _HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT (_HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_RESETVALUE 0x07000040UL /**< Default value for HFXO_CTRL */ +#define _HFXO_CTRL_MASK 0x8707FF7DUL /**< Mask for HFXO_CTRL */ +#define HFXO_CTRL_BUFOUTFREEZE (0x1UL << 0) /**< Freeze BUFOUT Controls */ +#define _HFXO_CTRL_BUFOUTFREEZE_SHIFT 0 /**< Shift value for HFXO_BUFOUTFREEZE */ +#define _HFXO_CTRL_BUFOUTFREEZE_MASK 0x1UL /**< Bit mask for HFXO_BUFOUTFREEZE */ +#define _HFXO_CTRL_BUFOUTFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_BUFOUTFREEZE_DEFAULT (_HFXO_CTRL_BUFOUTFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM (0x1UL << 2) /**< Keep Warm */ +#define _HFXO_CTRL_KEEPWARM_SHIFT 2 /**< Shift value for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_MASK 0x4UL /**< Bit mask for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM_DEFAULT (_HFXO_CTRL_KEEPWARM_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_EM23ONDEMAND (0x1UL << 3) /**< On-demand During EM23 */ +#define _HFXO_CTRL_EM23ONDEMAND_SHIFT 3 /**< Shift value for HFXO_EM23ONDEMAND */ +#define _HFXO_CTRL_EM23ONDEMAND_MASK 0x8UL /**< Bit mask for HFXO_EM23ONDEMAND */ +#define _HFXO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_EM23ONDEMAND_DEFAULT (_HFXO_CTRL_EM23ONDEMAND_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA (0x1UL << 4) /**< Force XI Pin to Ground */ +#define _HFXO_CTRL_FORCEXI2GNDANA_SHIFT 4 /**< Shift value for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_MASK 0x10UL /**< Bit mask for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXI2GNDANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DISABLE (_HFXO_CTRL_FORCEXI2GNDANA_DISABLE << 4) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_ENABLE (_HFXO_CTRL_FORCEXI2GNDANA_ENABLE << 4) /**< Shifted mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA (0x1UL << 5) /**< Force XO Pin to Ground */ +#define _HFXO_CTRL_FORCEXO2GNDANA_SHIFT 5 /**< Shift value for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_MASK 0x20UL /**< Bit mask for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXO2GNDANA_DEFAULT << 5) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DISABLE (_HFXO_CTRL_FORCEXO2GNDANA_DISABLE << 5) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_ENABLE (_HFXO_CTRL_FORCEXO2GNDANA_ENABLE << 5) /**< Shifted mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCECTUNEMAX (0x1UL << 6) /**< Force Tuning Cap to Max Value */ +#define _HFXO_CTRL_FORCECTUNEMAX_SHIFT 6 /**< Shift value for HFXO_FORCECTUNEMAX */ +#define _HFXO_CTRL_FORCECTUNEMAX_MASK 0x40UL /**< Bit mask for HFXO_FORCECTUNEMAX */ +#define _HFXO_CTRL_FORCECTUNEMAX_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCECTUNEMAX_DEFAULT (_HFXO_CTRL_FORCECTUNEMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_SHIFT 8 /**< Shift value for HFXO_PRSSTATUSSEL0 */ +#define _HFXO_CTRL_PRSSTATUSSEL0_MASK 0xF00UL /**< Bit mask for HFXO_PRSSTATUSSEL0 */ +#define _HFXO_CTRL_PRSSTATUSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL0_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_DISABLED (_HFXO_CTRL_PRSSTATUSSEL0_DISABLED << 8) /**< Shifted mode DISABLED for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_ENS (_HFXO_CTRL_PRSSTATUSSEL0_ENS << 8) /**< Shifted mode ENS for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY << 8) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_RDY (_HFXO_CTRL_PRSSTATUSSEL0_RDY << 8) /**< Shifted mode RDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL0_PRSRDY << 8) /**< Shifted mode PRSRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY << 8) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_HWREQ (_HFXO_CTRL_PRSSTATUSSEL0_HWREQ << 8) /**< Shifted mode HWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ << 8) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ << 8) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_SHIFT 12 /**< Shift value for HFXO_PRSSTATUSSEL1 */ +#define _HFXO_CTRL_PRSSTATUSSEL1_MASK 0xF000UL /**< Bit mask for HFXO_PRSSTATUSSEL1 */ +#define _HFXO_CTRL_PRSSTATUSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL1_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_DISABLED (_HFXO_CTRL_PRSSTATUSSEL1_DISABLED << 12) /**< Shifted mode DISABLED for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_ENS (_HFXO_CTRL_PRSSTATUSSEL1_ENS << 12) /**< Shifted mode ENS for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY << 12) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_RDY (_HFXO_CTRL_PRSSTATUSSEL1_RDY << 12) /**< Shifted mode RDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL1_PRSRDY << 12) /**< Shifted mode PRSRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY << 12) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_HWREQ (_HFXO_CTRL_PRSSTATUSSEL1_HWREQ << 12) /**< Shifted mode HWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ << 12) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ << 12) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN (0x1UL << 16) /**< Force Digital Clock Request */ +#define _HFXO_CTRL_FORCEEN_SHIFT 16 /**< Shift value for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_MASK 0x10000UL /**< Bit mask for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN_DEFAULT (_HFXO_CTRL_FORCEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENPRS (0x1UL << 17) /**< Force PRS Oscillator Request */ +#define _HFXO_CTRL_FORCEENPRS_SHIFT 17 /**< Shift value for HFXO_FORCEENPRS */ +#define _HFXO_CTRL_FORCEENPRS_MASK 0x20000UL /**< Bit mask for HFXO_FORCEENPRS */ +#define _HFXO_CTRL_FORCEENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENPRS_DEFAULT (_HFXO_CTRL_FORCEENPRS_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENBUFOUT (0x1UL << 18) /**< Force BUFOUT Request */ +#define _HFXO_CTRL_FORCEENBUFOUT_SHIFT 18 /**< Shift value for HFXO_FORCEENBUFOUT */ +#define _HFXO_CTRL_FORCEENBUFOUT_MASK 0x40000UL /**< Bit mask for HFXO_FORCEENBUFOUT */ +#define _HFXO_CTRL_FORCEENBUFOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENBUFOUT_DEFAULT (_HFXO_CTRL_FORCEENBUFOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND (0x1UL << 24) /**< Disable On-demand For Digital Clock */ +#define _HFXO_CTRL_DISONDEMAND_SHIFT 24 /**< Shift value for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_MASK 0x1000000UL /**< Bit mask for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND_DEFAULT (_HFXO_CTRL_DISONDEMAND_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDPRS (0x1UL << 25) /**< Disable On-demand For PRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_SHIFT 25 /**< Shift value for HFXO_DISONDEMANDPRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_MASK 0x2000000UL /**< Bit mask for HFXO_DISONDEMANDPRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDPRS_DEFAULT (_HFXO_CTRL_DISONDEMANDPRS_DEFAULT << 25) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDBUFOUT (0x1UL << 26) /**< Disable On-demand For BUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_SHIFT 26 /**< Shift value for HFXO_DISONDEMANDBUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_MASK 0x4000000UL /**< Bit mask for HFXO_DISONDEMANDBUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT (_HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_CTRL */ /* Bit fields for HFXO BUFOUTTRIM */ -#define _HFXO_BUFOUTTRIM_RESETVALUE 0x00000008UL /**< Default value for HFXO_BUFOUTTRIM */ -#define _HFXO_BUFOUTTRIM_MASK 0x0000000FUL /**< Mask for HFXO_BUFOUTTRIM */ -#define _HFXO_BUFOUTTRIM_VTRTRIMANA_SHIFT 0 /**< Shift value for HFXO_VTRTRIMANA */ -#define _HFXO_BUFOUTTRIM_VTRTRIMANA_MASK 0xFUL /**< Bit mask for HFXO_VTRTRIMANA */ -#define _HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFXO_BUFOUTTRIM */ -#define HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT (_HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_RESETVALUE 0x00000008UL /**< Default value for HFXO_BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_MASK 0x0000000FUL /**< Mask for HFXO_BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_SHIFT 0 /**< Shift value for HFXO_VTRTRIMANA */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_MASK 0xFUL /**< Bit mask for HFXO_VTRTRIMANA */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFXO_BUFOUTTRIM */ +#define HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT (_HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTTRIM */ /* Bit fields for HFXO BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_RESETVALUE 0x00643C15UL /**< Default value for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_MASK 0xC0FFFFFFUL /**< Mask for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_XOUTBIASANA_SHIFT 0 /**< Shift value for HFXO_XOUTBIASANA */ -#define _HFXO_BUFOUTCTRL_XOUTBIASANA_MASK 0xFUL /**< Bit mask for HFXO_XOUTBIASANA */ -#define _HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT 0x00000005UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_XOUTCFANA_SHIFT 4 /**< Shift value for HFXO_XOUTCFANA */ -#define _HFXO_BUFOUTCTRL_XOUTCFANA_MASK 0xF0UL /**< Bit mask for HFXO_XOUTCFANA */ -#define _HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_XOUTGMANA_SHIFT 8 /**< Shift value for HFXO_XOUTGMANA */ -#define _HFXO_BUFOUTCTRL_XOUTGMANA_MASK 0xF00UL /**< Bit mask for HFXO_XOUTGMANA */ -#define _HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT 0x0000000CUL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_SHIFT 12 /**< Shift value for HFXO_PEAKDETTHRESANA */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_MASK 0xF000UL /**< Bit mask for HFXO_PEAKDETTHRESANA */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV 0x00000000UL /**< Mode V105MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV 0x00000001UL /**< Mode V132MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV 0x00000002UL /**< Mode V157MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV 0x00000003UL /**< Mode V184MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV 0x00000004UL /**< Mode V210MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV 0x00000005UL /**< Mode V236MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV 0x00000006UL /**< Mode V262MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV 0x00000007UL /**< Mode V289MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV 0x00000008UL /**< Mode V315MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV 0x00000009UL /**< Mode V341MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV 0x0000000AUL /**< Mode V367MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV 0x0000000BUL /**< Mode V394MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV 0x0000000CUL /**< Mode V420MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV 0x0000000DUL /**< Mode V446MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV 0x0000000EUL /**< Mode V472MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV 0x0000000FUL /**< Mode V499MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV << 12) /**< Shifted mode V105MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV << 12) /**< Shifted mode V132MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV << 12) /**< Shifted mode V157MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV << 12) /**< Shifted mode V184MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV << 12) /**< Shifted mode V210MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV << 12) /**< Shifted mode V236MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV << 12) /**< Shifted mode V262MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV << 12) /**< Shifted mode V289MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV << 12) /**< Shifted mode V315MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV << 12) /**< Shifted mode V341MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV << 12) /**< Shifted mode V367MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV << 12) /**< Shifted mode V394MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV << 12) /**< Shifted mode V420MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV << 12) /**< Shifted mode V446MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV << 12) /**< Shifted mode V472MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV << 12) /**< Shifted mode V499MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_SHIFT 16 /**< Shift value for HFXO_TIMEOUTCTUNE */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_MASK 0xF0000UL /**< Bit mask for HFXO_TIMEOUTCTUNE */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US 0x00000000UL /**< Mode T2US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US 0x00000001UL /**< Mode T5US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US 0x00000002UL /**< Mode T10US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US 0x00000003UL /**< Mode T16US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US 0x00000004UL /**< Mode T21US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US 0x00000005UL /**< Mode T26US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US 0x00000006UL /**< Mode T31US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US 0x00000007UL /**< Mode T42US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US 0x00000008UL /**< Mode T52US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US 0x00000009UL /**< Mode T63US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US 0x0000000AUL /**< Mode T83US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US 0x0000000BUL /**< Mode T104US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US 0x0000000CUL /**< Mode T208US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US 0x0000000DUL /**< Mode T313US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US 0x0000000EUL /**< Mode T521US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US 0x0000000FUL /**< Mode T938US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US << 16) /**< Shifted mode T2US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US << 16) /**< Shifted mode T5US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US << 16) /**< Shifted mode T10US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US << 16) /**< Shifted mode T16US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US << 16) /**< Shifted mode T21US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US << 16) /**< Shifted mode T26US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US << 16) /**< Shifted mode T31US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US << 16) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US << 16) /**< Shifted mode T52US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US << 16) /**< Shifted mode T63US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US << 16) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US << 16) /**< Shifted mode T104US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US << 16) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US << 16) /**< Shifted mode T313US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US << 16) /**< Shifted mode T521US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US << 16) /**< Shifted mode T938US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTARTUP */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTARTUP */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT 0x00000006UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US 0x00000000UL /**< Mode T42US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US 0x00000001UL /**< Mode T83US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US 0x00000002UL /**< Mode T108US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US 0x00000003UL /**< Mode T133US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US 0x00000004UL /**< Mode T158US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US 0x00000005UL /**< Mode T183US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US 0x00000006UL /**< Mode T208US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US 0x00000007UL /**< Mode T233US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US 0x00000008UL /**< Mode T258US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US 0x00000009UL /**< Mode T283US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US 0x0000000AUL /**< Mode T333US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US 0x0000000BUL /**< Mode T375US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US 0x0000000CUL /**< Mode T417US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US 0x0000000DUL /**< Mode T458US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US 0x0000000EUL /**< Mode T500US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US 0x0000000FUL /**< Mode T667US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US << 20) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US << 20) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US << 20) /**< Shifted mode T108US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US << 20) /**< Shifted mode T133US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US << 20) /**< Shifted mode T158US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US << 20) /**< Shifted mode T183US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US << 20) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US << 20) /**< Shifted mode T233US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US << 20) /**< Shifted mode T258US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US << 20) /**< Shifted mode T283US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US << 20) /**< Shifted mode T333US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US << 20) /**< Shifted mode T375US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US << 20) /**< Shifted mode T417US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US << 20) /**< Shifted mode T458US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US << 20) /**< Shifted mode T500US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US << 20) /**< Shifted mode T667US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY (0x1UL << 31) /**< Minimum Startup Delay */ -#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_SHIFT 31 /**< Shift value for HFXO_MINIMUMSTARTUPDELAY */ -#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_MASK 0x80000000UL /**< Bit mask for HFXO_MINIMUMSTARTUPDELAY */ -#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT (_HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_RESETVALUE 0x00643C15UL /**< Default value for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_MASK 0xC0FFFFFFUL /**< Mask for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_SHIFT 0 /**< Shift value for HFXO_XOUTBIASANA */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_MASK 0xFUL /**< Bit mask for HFXO_XOUTBIASANA */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT 0x00000005UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_SHIFT 4 /**< Shift value for HFXO_XOUTCFANA */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_MASK 0xF0UL /**< Bit mask for HFXO_XOUTCFANA */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_SHIFT 8 /**< Shift value for HFXO_XOUTGMANA */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_MASK 0xF00UL /**< Bit mask for HFXO_XOUTGMANA */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT 0x0000000CUL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_SHIFT 12 /**< Shift value for HFXO_PEAKDETTHRESANA */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_MASK 0xF000UL /**< Bit mask for HFXO_PEAKDETTHRESANA */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV 0x00000000UL /**< Mode V105MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV 0x00000001UL /**< Mode V132MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV 0x00000002UL /**< Mode V157MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV 0x00000003UL /**< Mode V184MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV 0x00000004UL /**< Mode V210MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV 0x00000005UL /**< Mode V236MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV 0x00000006UL /**< Mode V262MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV 0x00000007UL /**< Mode V289MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV 0x00000008UL /**< Mode V315MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV 0x00000009UL /**< Mode V341MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV 0x0000000AUL /**< Mode V367MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV 0x0000000BUL /**< Mode V394MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV 0x0000000CUL /**< Mode V420MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV 0x0000000DUL /**< Mode V446MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV 0x0000000EUL /**< Mode V472MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV 0x0000000FUL /**< Mode V499MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV << 12) /**< Shifted mode V105MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV << 12) /**< Shifted mode V132MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV << 12) /**< Shifted mode V157MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV << 12) /**< Shifted mode V184MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV << 12) /**< Shifted mode V210MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV << 12) /**< Shifted mode V236MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV << 12) /**< Shifted mode V262MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV << 12) /**< Shifted mode V289MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV << 12) /**< Shifted mode V315MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV << 12) /**< Shifted mode V341MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV << 12) /**< Shifted mode V367MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV << 12) /**< Shifted mode V394MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV << 12) /**< Shifted mode V420MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV << 12) /**< Shifted mode V446MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV << 12) /**< Shifted mode V472MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV << 12) /**< Shifted mode V499MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_SHIFT 16 /**< Shift value for HFXO_TIMEOUTCTUNE */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_MASK 0xF0000UL /**< Bit mask for HFXO_TIMEOUTCTUNE */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US 0x00000000UL /**< Mode T2US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US 0x00000001UL /**< Mode T5US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US 0x00000002UL /**< Mode T10US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US 0x00000003UL /**< Mode T16US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US 0x00000004UL /**< Mode T21US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US 0x00000005UL /**< Mode T26US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US 0x00000006UL /**< Mode T31US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US 0x00000007UL /**< Mode T42US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US 0x00000008UL /**< Mode T52US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US 0x00000009UL /**< Mode T63US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US 0x0000000AUL /**< Mode T83US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US 0x0000000BUL /**< Mode T104US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US 0x0000000CUL /**< Mode T208US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US 0x0000000DUL /**< Mode T313US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US 0x0000000EUL /**< Mode T521US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US 0x0000000FUL /**< Mode T938US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US << 16) /**< Shifted mode T2US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US << 16) /**< Shifted mode T5US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US << 16) /**< Shifted mode T10US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US << 16) /**< Shifted mode T16US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US << 16) /**< Shifted mode T21US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US << 16) /**< Shifted mode T26US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US << 16) /**< Shifted mode T31US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US << 16) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US << 16) /**< Shifted mode T52US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US << 16) /**< Shifted mode T63US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US << 16) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US << 16) /**< Shifted mode T104US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US << 16) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US << 16) /**< Shifted mode T313US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US << 16) /**< Shifted mode T521US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US << 16) /**< Shifted mode T938US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTARTUP */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTARTUP */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT 0x00000006UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US 0x00000000UL /**< Mode T42US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US 0x00000001UL /**< Mode T83US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US 0x00000002UL /**< Mode T108US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US 0x00000003UL /**< Mode T133US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US 0x00000004UL /**< Mode T158US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US 0x00000005UL /**< Mode T183US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US 0x00000006UL /**< Mode T208US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US 0x00000007UL /**< Mode T233US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US 0x00000008UL /**< Mode T258US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US 0x00000009UL /**< Mode T283US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US 0x0000000AUL /**< Mode T333US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US 0x0000000BUL /**< Mode T375US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US 0x0000000CUL /**< Mode T417US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US 0x0000000DUL /**< Mode T458US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US 0x0000000EUL /**< Mode T500US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US 0x0000000FUL /**< Mode T667US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US << 20) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US << 20) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US << 20) /**< Shifted mode T108US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US << 20) /**< Shifted mode T133US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US << 20) /**< Shifted mode T158US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US << 20) /**< Shifted mode T183US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US << 20) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US << 20) /**< Shifted mode T233US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US << 20) /**< Shifted mode T258US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US << 20) /**< Shifted mode T283US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US << 20) /**< Shifted mode T333US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US << 20) /**< Shifted mode T375US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US << 20) /**< Shifted mode T417US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US << 20) /**< Shifted mode T458US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US << 20) /**< Shifted mode T500US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US << 20) /**< Shifted mode T667US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY (0x1UL << 31) /**< Minimum Startup Delay */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_SHIFT 31 /**< Shift value for HFXO_MINIMUMSTARTUPDELAY */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_MASK 0x80000000UL /**< Bit mask for HFXO_MINIMUMSTARTUPDELAY */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT (_HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ /* Bit fields for HFXO CMD */ -#define _HFXO_CMD_RESETVALUE 0x00000000UL /**< Default value for HFXO_CMD */ -#define _HFXO_CMD_MASK 0x00000001UL /**< Mask for HFXO_CMD */ -#define HFXO_CMD_COREBIASOPT (0x1UL << 0) /**< Core Bias Optimizaton */ -#define _HFXO_CMD_COREBIASOPT_SHIFT 0 /**< Shift value for HFXO_COREBIASOPT */ -#define _HFXO_CMD_COREBIASOPT_MASK 0x1UL /**< Bit mask for HFXO_COREBIASOPT */ -#define _HFXO_CMD_COREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ -#define HFXO_CMD_COREBIASOPT_DEFAULT (_HFXO_CMD_COREBIASOPT_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CMD */ +#define _HFXO_CMD_RESETVALUE 0x00000000UL /**< Default value for HFXO_CMD */ +#define _HFXO_CMD_MASK 0x00000001UL /**< Mask for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT (0x1UL << 0) /**< Core Bias Optimizaton */ +#define _HFXO_CMD_COREBIASOPT_SHIFT 0 /**< Shift value for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_MASK 0x1UL /**< Bit mask for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT_DEFAULT (_HFXO_CMD_COREBIASOPT_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CMD */ /* Bit fields for HFXO STATUS */ -#define _HFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFXO_STATUS */ -#define _HFXO_STATUS_MASK 0xC03F800FUL /**< Mask for HFXO_STATUS */ -#define HFXO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ -#define _HFXO_STATUS_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ -#define _HFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ -#define _HFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_RDY_DEFAULT (_HFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready */ -#define _HFXO_STATUS_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ -#define _HFXO_STATUS_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ -#define _HFXO_STATUS_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_COREBIASOPTRDY_DEFAULT (_HFXO_STATUS_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_PRSRDY (0x1UL << 2) /**< PRS Ready Status */ -#define _HFXO_STATUS_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ -#define _HFXO_STATUS_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ -#define _HFXO_STATUS_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_PRSRDY_DEFAULT (_HFXO_STATUS_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Status */ -#define _HFXO_STATUS_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ -#define _HFXO_STATUS_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ -#define _HFXO_STATUS_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTRDY_DEFAULT (_HFXO_STATUS_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT Frozen */ -#define _HFXO_STATUS_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ -#define _HFXO_STATUS_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ -#define _HFXO_STATUS_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTFROZEN_DEFAULT (_HFXO_STATUS_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ -#define _HFXO_STATUS_ENS_SHIFT 16 /**< Shift value for HFXO_ENS */ -#define _HFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFXO_ENS */ -#define _HFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_ENS_DEFAULT (_HFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_HWREQ (0x1UL << 17) /**< Oscillator Requested by Digital Clock */ -#define _HFXO_STATUS_HWREQ_SHIFT 17 /**< Shift value for HFXO_HWREQ */ -#define _HFXO_STATUS_HWREQ_MASK 0x20000UL /**< Bit mask for HFXO_HWREQ */ -#define _HFXO_STATUS_HWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_HWREQ_DEFAULT (_HFXO_STATUS_HWREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_ISWARM (0x1UL << 19) /**< Oscillator Is Kept Warm */ -#define _HFXO_STATUS_ISWARM_SHIFT 19 /**< Shift value for HFXO_ISWARM */ -#define _HFXO_STATUS_ISWARM_MASK 0x80000UL /**< Bit mask for HFXO_ISWARM */ -#define _HFXO_STATUS_ISWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_ISWARM_DEFAULT (_HFXO_STATUS_ISWARM_DEFAULT << 19) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_PRSHWREQ (0x1UL << 20) /**< Oscillator Requested by PRS Request */ -#define _HFXO_STATUS_PRSHWREQ_SHIFT 20 /**< Shift value for HFXO_PRSHWREQ */ -#define _HFXO_STATUS_PRSHWREQ_MASK 0x100000UL /**< Bit mask for HFXO_PRSHWREQ */ -#define _HFXO_STATUS_PRSHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_PRSHWREQ_DEFAULT (_HFXO_STATUS_PRSHWREQ_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTHWREQ (0x1UL << 21) /**< Oscillator Requested by BUFOUT Request */ -#define _HFXO_STATUS_BUFOUTHWREQ_SHIFT 21 /**< Shift value for HFXO_BUFOUTHWREQ */ -#define _HFXO_STATUS_BUFOUTHWREQ_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTHWREQ */ -#define _HFXO_STATUS_BUFOUTHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTHWREQ_DEFAULT (_HFXO_STATUS_BUFOUTHWREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_SYNCBUSY (0x1UL << 30) /**< Sync Busy */ -#define _HFXO_STATUS_SYNCBUSY_SHIFT 30 /**< Shift value for HFXO_SYNCBUSY */ -#define _HFXO_STATUS_SYNCBUSY_MASK 0x40000000UL /**< Bit mask for HFXO_SYNCBUSY */ -#define _HFXO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_SYNCBUSY_DEFAULT (_HFXO_STATUS_SYNCBUSY_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ -#define _HFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFXO_LOCK */ -#define _HFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFXO_LOCK */ -#define _HFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define _HFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ -#define _HFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ -#define HFXO_STATUS_LOCK_DEFAULT (_HFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_LOCK_UNLOCKED (_HFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFXO_STATUS */ -#define HFXO_STATUS_LOCK_LOCKED (_HFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFXO_STATUS */ +#define _HFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFXO_STATUS */ +#define _HFXO_STATUS_MASK 0xC03F800FUL /**< Mask for HFXO_STATUS */ +#define HFXO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _HFXO_STATUS_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_RDY_DEFAULT (_HFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready */ +#define _HFXO_STATUS_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY_DEFAULT (_HFXO_STATUS_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSRDY (0x1UL << 2) /**< PRS Ready Status */ +#define _HFXO_STATUS_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_STATUS_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_STATUS_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSRDY_DEFAULT (_HFXO_STATUS_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Status */ +#define _HFXO_STATUS_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_STATUS_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_STATUS_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTRDY_DEFAULT (_HFXO_STATUS_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT Frozen */ +#define _HFXO_STATUS_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_STATUS_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_STATUS_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTFROZEN_DEFAULT (_HFXO_STATUS_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _HFXO_STATUS_ENS_SHIFT 16 /**< Shift value for HFXO_ENS */ +#define _HFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFXO_ENS */ +#define _HFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS_DEFAULT (_HFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ (0x1UL << 17) /**< Oscillator Requested by Digital Clock */ +#define _HFXO_STATUS_HWREQ_SHIFT 17 /**< Shift value for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_MASK 0x20000UL /**< Bit mask for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ_DEFAULT (_HFXO_STATUS_HWREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM (0x1UL << 19) /**< Oscillator Is Kept Warm */ +#define _HFXO_STATUS_ISWARM_SHIFT 19 /**< Shift value for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_MASK 0x80000UL /**< Bit mask for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM_DEFAULT (_HFXO_STATUS_ISWARM_DEFAULT << 19) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSHWREQ (0x1UL << 20) /**< Oscillator Requested by PRS Request */ +#define _HFXO_STATUS_PRSHWREQ_SHIFT 20 /**< Shift value for HFXO_PRSHWREQ */ +#define _HFXO_STATUS_PRSHWREQ_MASK 0x100000UL /**< Bit mask for HFXO_PRSHWREQ */ +#define _HFXO_STATUS_PRSHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSHWREQ_DEFAULT (_HFXO_STATUS_PRSHWREQ_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTHWREQ (0x1UL << 21) /**< Oscillator Requested by BUFOUT Request */ +#define _HFXO_STATUS_BUFOUTHWREQ_SHIFT 21 /**< Shift value for HFXO_BUFOUTHWREQ */ +#define _HFXO_STATUS_BUFOUTHWREQ_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTHWREQ */ +#define _HFXO_STATUS_BUFOUTHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTHWREQ_DEFAULT (_HFXO_STATUS_BUFOUTHWREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_SYNCBUSY (0x1UL << 30) /**< Sync Busy */ +#define _HFXO_STATUS_SYNCBUSY_SHIFT 30 /**< Shift value for HFXO_SYNCBUSY */ +#define _HFXO_STATUS_SYNCBUSY_MASK 0x40000000UL /**< Bit mask for HFXO_SYNCBUSY */ +#define _HFXO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_SYNCBUSY_DEFAULT (_HFXO_STATUS_SYNCBUSY_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _HFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_DEFAULT (_HFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_UNLOCKED (_HFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_LOCKED (_HFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFXO_STATUS */ /* Bit fields for HFXO IF */ -#define _HFXO_IF_RESETVALUE 0x00000000UL /**< Default value for HFXO_IF */ -#define _HFXO_IF_MASK 0xF830800FUL /**< Mask for HFXO_IF */ -#define HFXO_IF_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ -#define _HFXO_IF_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ -#define _HFXO_IF_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ -#define _HFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_RDY_DEFAULT (_HFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ -#define _HFXO_IF_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ -#define _HFXO_IF_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ -#define _HFXO_IF_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_COREBIASOPTRDY_DEFAULT (_HFXO_IF_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ -#define _HFXO_IF_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ -#define _HFXO_IF_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ -#define _HFXO_IF_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_PRSRDY_DEFAULT (_HFXO_IF_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ -#define _HFXO_IF_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ -#define _HFXO_IF_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ -#define _HFXO_IF_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTRDY_DEFAULT (_HFXO_IF_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ -#define _HFXO_IF_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ -#define _HFXO_IF_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ -#define _HFXO_IF_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTFROZEN_DEFAULT (_HFXO_IF_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ -#define _HFXO_IF_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ -#define _HFXO_IF_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ -#define _HFXO_IF_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_PRSERR_DEFAULT (_HFXO_IF_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ -#define _HFXO_IF_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ -#define _HFXO_IF_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ -#define _HFXO_IF_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTERR_DEFAULT (_HFXO_IF_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ -#define _HFXO_IF_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ -#define _HFXO_IF_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ -#define _HFXO_IF_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTFREEZEERR_DEFAULT (_HFXO_IF_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ -#define _HFXO_IF_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ -#define _HFXO_IF_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ -#define _HFXO_IF_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTDNSERR_DEFAULT (_HFXO_IF_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ -#define _HFXO_IF_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ -#define _HFXO_IF_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ -#define _HFXO_IF_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_DNSERR_DEFAULT (_HFXO_IF_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ -#define _HFXO_IF_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ -#define _HFXO_IF_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ -#define _HFXO_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_LFTIMEOUTERR_DEFAULT (_HFXO_IF_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ -#define _HFXO_IF_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ -#define _HFXO_IF_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ -#define _HFXO_IF_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_COREBIASOPTERR_DEFAULT (_HFXO_IF_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IF */ +#define _HFXO_IF_RESETVALUE 0x00000000UL /**< Default value for HFXO_IF */ +#define _HFXO_IF_MASK 0xF830800FUL /**< Mask for HFXO_IF */ +#define HFXO_IF_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ +#define _HFXO_IF_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IF_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_RDY_DEFAULT (_HFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IF_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY_DEFAULT (_HFXO_IF_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ +#define _HFXO_IF_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_IF_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_IF_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSRDY_DEFAULT (_HFXO_IF_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ +#define _HFXO_IF_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_IF_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_IF_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTRDY_DEFAULT (_HFXO_IF_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ +#define _HFXO_IF_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_IF_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_IF_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFROZEN_DEFAULT (_HFXO_IF_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ +#define _HFXO_IF_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ +#define _HFXO_IF_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ +#define _HFXO_IF_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSERR_DEFAULT (_HFXO_IF_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ +#define _HFXO_IF_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ +#define _HFXO_IF_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ +#define _HFXO_IF_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTERR_DEFAULT (_HFXO_IF_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ +#define _HFXO_IF_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IF_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IF_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFREEZEERR_DEFAULT (_HFXO_IF_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ +#define _HFXO_IF_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ +#define _HFXO_IF_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ +#define _HFXO_IF_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTDNSERR_DEFAULT (_HFXO_IF_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IF_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR_DEFAULT (_HFXO_IF_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ +#define _HFXO_IF_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ +#define _HFXO_IF_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ +#define _HFXO_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_LFTIMEOUTERR_DEFAULT (_HFXO_IF_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IF_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR_DEFAULT (_HFXO_IF_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IF */ /* Bit fields for HFXO IEN */ -#define _HFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFXO_IEN */ -#define _HFXO_IEN_MASK 0xF830800FUL /**< Mask for HFXO_IEN */ -#define HFXO_IEN_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ -#define _HFXO_IEN_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ -#define _HFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ -#define _HFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_RDY_DEFAULT (_HFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ -#define _HFXO_IEN_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ -#define _HFXO_IEN_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ -#define _HFXO_IEN_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_COREBIASOPTRDY_DEFAULT (_HFXO_IEN_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ -#define _HFXO_IEN_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ -#define _HFXO_IEN_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ -#define _HFXO_IEN_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_PRSRDY_DEFAULT (_HFXO_IEN_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ -#define _HFXO_IEN_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ -#define _HFXO_IEN_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ -#define _HFXO_IEN_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTRDY_DEFAULT (_HFXO_IEN_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ -#define _HFXO_IEN_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ -#define _HFXO_IEN_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ -#define _HFXO_IEN_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTFROZEN_DEFAULT (_HFXO_IEN_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ -#define _HFXO_IEN_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ -#define _HFXO_IEN_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ -#define _HFXO_IEN_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_PRSERR_DEFAULT (_HFXO_IEN_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ -#define _HFXO_IEN_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ -#define _HFXO_IEN_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ -#define _HFXO_IEN_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTERR_DEFAULT (_HFXO_IEN_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ -#define _HFXO_IEN_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ -#define _HFXO_IEN_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ -#define _HFXO_IEN_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTFREEZEERR_DEFAULT (_HFXO_IEN_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ -#define _HFXO_IEN_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ -#define _HFXO_IEN_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ -#define _HFXO_IEN_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTDNSERR_DEFAULT (_HFXO_IEN_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ -#define _HFXO_IEN_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ -#define _HFXO_IEN_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ -#define _HFXO_IEN_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_DNSERR_DEFAULT (_HFXO_IEN_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ -#define _HFXO_IEN_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ -#define _HFXO_IEN_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ -#define _HFXO_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_LFTIMEOUTERR_DEFAULT (_HFXO_IEN_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ -#define _HFXO_IEN_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ -#define _HFXO_IEN_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ -#define _HFXO_IEN_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_COREBIASOPTERR_DEFAULT (_HFXO_IEN_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define _HFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFXO_IEN */ +#define _HFXO_IEN_MASK 0xF830800FUL /**< Mask for HFXO_IEN */ +#define HFXO_IEN_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ +#define _HFXO_IEN_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_RDY_DEFAULT (_HFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IEN_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY_DEFAULT (_HFXO_IEN_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ +#define _HFXO_IEN_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_IEN_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_IEN_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSRDY_DEFAULT (_HFXO_IEN_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ +#define _HFXO_IEN_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_IEN_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_IEN_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTRDY_DEFAULT (_HFXO_IEN_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ +#define _HFXO_IEN_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_IEN_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_IEN_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFROZEN_DEFAULT (_HFXO_IEN_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ +#define _HFXO_IEN_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ +#define _HFXO_IEN_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ +#define _HFXO_IEN_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSERR_DEFAULT (_HFXO_IEN_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ +#define _HFXO_IEN_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ +#define _HFXO_IEN_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ +#define _HFXO_IEN_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTERR_DEFAULT (_HFXO_IEN_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ +#define _HFXO_IEN_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IEN_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IEN_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFREEZEERR_DEFAULT (_HFXO_IEN_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ +#define _HFXO_IEN_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ +#define _HFXO_IEN_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ +#define _HFXO_IEN_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTDNSERR_DEFAULT (_HFXO_IEN_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IEN_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR_DEFAULT (_HFXO_IEN_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ +#define _HFXO_IEN_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ +#define _HFXO_IEN_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ +#define _HFXO_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_LFTIMEOUTERR_DEFAULT (_HFXO_IEN_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IEN_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR_DEFAULT (_HFXO_IEN_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IEN */ /* Bit fields for HFXO LOCK */ -#define _HFXO_LOCK_RESETVALUE 0x0000580EUL /**< Default value for HFXO_LOCK */ -#define _HFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFXO_LOCK */ -#define _HFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFXO_LOCKKEY */ -#define _HFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFXO_LOCKKEY */ -#define _HFXO_LOCK_LOCKKEY_DEFAULT 0x0000580EUL /**< Mode DEFAULT for HFXO_LOCK */ -#define _HFXO_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for HFXO_LOCK */ -#define HFXO_LOCK_LOCKKEY_DEFAULT (_HFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_LOCK */ -#define HFXO_LOCK_LOCKKEY_UNLOCK (_HFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFXO_LOCK */ +#define _HFXO_LOCK_RESETVALUE 0x0000580EUL /**< Default value for HFXO_LOCK */ +#define _HFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_DEFAULT 0x0000580EUL /**< Mode DEFAULT for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_DEFAULT (_HFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_UNLOCK (_HFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFXO_LOCK */ /** @} End of group EFR32SG23_HFXO_BitFields */ /** @} End of group EFR32SG23_HFXO */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_i2c.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_i2c.h index 71e6462556..c2185e018d 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_i2c.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_i2c.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_I2C_H #define EFR32SG23_I2C_H - #define I2C_HAS_SET_CLEAR /**************************************************************************//** @@ -43,79 +42,78 @@ *****************************************************************************/ /** I2C Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP VERSION Register */ - __IOM uint32_t EN; /**< Enable Register */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATE; /**< State Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t CLKDIV; /**< Clock Division Register */ - __IOM uint32_t SADDR; /**< Follower Address Register */ - __IOM uint32_t SADDRMASK; /**< Follower Address Mask Register */ - __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ - __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ - __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ - __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ - __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ - __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED0[1007U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP VERSION Register */ - __IOM uint32_t EN_SET; /**< Enable Register */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATE_SET; /**< State Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t CLKDIV_SET; /**< Clock Division Register */ - __IOM uint32_t SADDR_SET; /**< Follower Address Register */ - __IOM uint32_t SADDRMASK_SET; /**< Follower Address Mask Register */ - __IM uint32_t RXDATA_SET; /**< Receive Buffer Data Register */ - __IM uint32_t RXDOUBLE_SET; /**< Receive Buffer Double Data Register */ - __IM uint32_t RXDATAP_SET; /**< Receive Buffer Data Peek Register */ - __IM uint32_t RXDOUBLEP_SET; /**< Receive Buffer Double Data Peek Register */ - __IOM uint32_t TXDATA_SET; /**< Transmit Buffer Data Register */ - __IOM uint32_t TXDOUBLE_SET; /**< Transmit Buffer Double Data Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED1[1007U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP VERSION Register */ - __IOM uint32_t EN_CLR; /**< Enable Register */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATE_CLR; /**< State Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t CLKDIV_CLR; /**< Clock Division Register */ - __IOM uint32_t SADDR_CLR; /**< Follower Address Register */ - __IOM uint32_t SADDRMASK_CLR; /**< Follower Address Mask Register */ - __IM uint32_t RXDATA_CLR; /**< Receive Buffer Data Register */ - __IM uint32_t RXDOUBLE_CLR; /**< Receive Buffer Double Data Register */ - __IM uint32_t RXDATAP_CLR; /**< Receive Buffer Data Peek Register */ - __IM uint32_t RXDOUBLEP_CLR; /**< Receive Buffer Double Data Peek Register */ - __IOM uint32_t TXDATA_CLR; /**< Transmit Buffer Data Register */ - __IOM uint32_t TXDOUBLE_CLR; /**< Transmit Buffer Double Data Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED2[1007U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP VERSION Register */ - __IOM uint32_t EN_TGL; /**< Enable Register */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATE_TGL; /**< State Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t CLKDIV_TGL; /**< Clock Division Register */ - __IOM uint32_t SADDR_TGL; /**< Follower Address Register */ - __IOM uint32_t SADDRMASK_TGL; /**< Follower Address Mask Register */ - __IM uint32_t RXDATA_TGL; /**< Receive Buffer Data Register */ - __IM uint32_t RXDOUBLE_TGL; /**< Receive Buffer Double Data Register */ - __IM uint32_t RXDATAP_TGL; /**< Receive Buffer Data Peek Register */ - __IM uint32_t RXDOUBLEP_TGL; /**< Receive Buffer Double Data Peek Register */ - __IOM uint32_t TXDATA_TGL; /**< Transmit Buffer Data Register */ - __IOM uint32_t TXDOUBLE_TGL; /**< Transmit Buffer Double Data Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP VERSION Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATE; /**< State Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Division Register */ + __IOM uint32_t SADDR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATE_SET; /**< State Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Division Register */ + __IOM uint32_t SADDR_SET; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_SET; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_SET; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_SET; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_SET; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_SET; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_SET; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATE_CLR; /**< State Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Division Register */ + __IOM uint32_t SADDR_CLR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_CLR; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_CLR; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_CLR; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_CLR; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_CLR; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATE_TGL; /**< State Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Division Register */ + __IOM uint32_t SADDR_TGL; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_TGL; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_TGL; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_TGL; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_TGL; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_TGL; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ } I2C_TypeDef; /** @} End of group EFR32SG23_I2C */ @@ -127,617 +125,617 @@ typedef struct *****************************************************************************/ /* Bit fields for I2C IPVERSION */ -#define _I2C_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for I2C_IPVERSION */ -#define _I2C_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for I2C_IPVERSION */ -#define _I2C_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for I2C_IPVERSION */ -#define _I2C_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for I2C_IPVERSION */ -#define _I2C_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IPVERSION */ -#define I2C_IPVERSION_IPVERSION_DEFAULT (_I2C_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IPVERSION */ +#define _I2C_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for I2C_IPVERSION */ +#define _I2C_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IPVERSION */ +#define I2C_IPVERSION_IPVERSION_DEFAULT (_I2C_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IPVERSION */ /* Bit fields for I2C EN */ -#define _I2C_EN_RESETVALUE 0x00000000UL /**< Default value for I2C_EN */ -#define _I2C_EN_MASK 0x00000001UL /**< Mask for I2C_EN */ -#define I2C_EN_EN (0x1UL << 0) /**< module enable */ -#define _I2C_EN_EN_SHIFT 0 /**< Shift value for I2C_EN */ -#define _I2C_EN_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ -#define _I2C_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_EN */ -#define _I2C_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_EN */ -#define _I2C_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_EN */ -#define I2C_EN_EN_DEFAULT (_I2C_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_EN */ -#define I2C_EN_EN_DISABLE (_I2C_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for I2C_EN */ -#define I2C_EN_EN_ENABLE (_I2C_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for I2C_EN */ +#define _I2C_EN_RESETVALUE 0x00000000UL /**< Default value for I2C_EN */ +#define _I2C_EN_MASK 0x00000001UL /**< Mask for I2C_EN */ +#define I2C_EN_EN (0x1UL << 0) /**< module enable */ +#define _I2C_EN_EN_SHIFT 0 /**< Shift value for I2C_EN */ +#define _I2C_EN_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ +#define _I2C_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_EN */ +#define _I2C_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_EN */ +#define _I2C_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_EN */ +#define I2C_EN_EN_DEFAULT (_I2C_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_EN */ +#define I2C_EN_EN_DISABLE (_I2C_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for I2C_EN */ +#define I2C_EN_EN_ENABLE (_I2C_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for I2C_EN */ /* Bit fields for I2C CTRL */ -#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ -#define _I2C_CTRL_MASK 0x0037B3FFUL /**< Mask for I2C_CTRL */ -#define I2C_CTRL_CORERST (0x1UL << 0) /**< Soft Reset the internal state registers */ -#define _I2C_CTRL_CORERST_SHIFT 0 /**< Shift value for I2C_CORERST */ -#define _I2C_CTRL_CORERST_MASK 0x1UL /**< Bit mask for I2C_CORERST */ -#define _I2C_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_CORERST_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_CORERST_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_CORERST_DEFAULT (_I2C_CTRL_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_CORERST_DISABLE (_I2C_CTRL_CORERST_DISABLE << 0) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_CORERST_ENABLE (_I2C_CTRL_CORERST_ENABLE << 0) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Follower */ -#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ -#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ -#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_SLAVE_DISABLE (_I2C_CTRL_SLAVE_DISABLE << 1) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_SLAVE_ENABLE (_I2C_CTRL_SLAVE_ENABLE << 1) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ -#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ -#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ -#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_AUTOACK_DISABLE (_I2C_CTRL_AUTOACK_DISABLE << 2) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOACK_ENABLE (_I2C_CTRL_AUTOACK_ENABLE << 2) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ -#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ -#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ -#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_AUTOSE_DISABLE (_I2C_CTRL_AUTOSE_DISABLE << 3) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSE_ENABLE (_I2C_CTRL_AUTOSE_ENABLE << 3) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ -#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ -#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ -#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_AUTOSN_DISABLE (_I2C_CTRL_AUTOSN_DISABLE << 4) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSN_ENABLE (_I2C_CTRL_AUTOSN_ENABLE << 4) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ -#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ -#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ -#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_ARBDIS_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_ARBDIS_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_ARBDIS_DISABLE (_I2C_CTRL_ARBDIS_DISABLE << 5) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_ARBDIS_ENABLE (_I2C_CTRL_ARBDIS_ENABLE << 5) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ -#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ -#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ -#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_GCAMEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_GCAMEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_GCAMEN_DISABLE (_I2C_CTRL_GCAMEN_DISABLE << 6) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_GCAMEN_ENABLE (_I2C_CTRL_GCAMEN_ENABLE << 6) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ -#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ -#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ -#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ -#define _I2C_CTRL_TXBIL_HALF_FULL 0x00000001UL /**< Mode HALF_FULL for I2C_CTRL */ -#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ -#define I2C_CTRL_TXBIL_HALF_FULL (_I2C_CTRL_TXBIL_HALF_FULL << 7) /**< Shifted mode HALF_FULL for I2C_CTRL */ -#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ -#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ -#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ -#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ -#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ -#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ -#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ -#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ -#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ -#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ -#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ -#define _I2C_CTRL_BITO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ -#define _I2C_CTRL_BITO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ -#define _I2C_CTRL_BITO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ -#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ -#define I2C_CTRL_BITO_I2C40PCC (_I2C_CTRL_BITO_I2C40PCC << 12) /**< Shifted mode I2C40PCC for I2C_CTRL */ -#define I2C_CTRL_BITO_I2C80PCC (_I2C_CTRL_BITO_I2C80PCC << 12) /**< Shifted mode I2C80PCC for I2C_CTRL */ -#define I2C_CTRL_BITO_I2C160PCC (_I2C_CTRL_BITO_I2C160PCC << 12) /**< Shifted mode I2C160PCC for I2C_CTRL */ -#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ -#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ -#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ -#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_GIBITO_DISABLE (_I2C_CTRL_GIBITO_DISABLE << 15) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_GIBITO_ENABLE (_I2C_CTRL_GIBITO_ENABLE << 15) /**< Shifted mode ENABLE for I2C_CTRL */ -#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ -#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ -#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C320PCC 0x00000004UL /**< Mode I2C320PCC for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C1024PCC 0x00000005UL /**< Mode I2C1024PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C40PCC (_I2C_CTRL_CLTO_I2C40PCC << 16) /**< Shifted mode I2C40PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C80PCC (_I2C_CTRL_CLTO_I2C80PCC << 16) /**< Shifted mode I2C80PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C160PCC (_I2C_CTRL_CLTO_I2C160PCC << 16) /**< Shifted mode I2C160PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C320PCC (_I2C_CTRL_CLTO_I2C320PCC << 16) /**< Shifted mode I2C320PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C1024PCC (_I2C_CTRL_CLTO_I2C1024PCC << 16) /**< Shifted mode I2C1024PCC for I2C_CTRL */ -#define I2C_CTRL_SCLMONEN (0x1UL << 20) /**< SCL Monitor Enable */ -#define _I2C_CTRL_SCLMONEN_SHIFT 20 /**< Shift value for I2C_SCLMONEN */ -#define _I2C_CTRL_SCLMONEN_MASK 0x100000UL /**< Bit mask for I2C_SCLMONEN */ -#define _I2C_CTRL_SCLMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_SCLMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_SCLMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SCLMONEN_DEFAULT (_I2C_CTRL_SCLMONEN_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_SCLMONEN_DISABLE (_I2C_CTRL_SCLMONEN_DISABLE << 20) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_SCLMONEN_ENABLE (_I2C_CTRL_SCLMONEN_ENABLE << 20) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SDAMONEN (0x1UL << 21) /**< SDA Monitor Enable */ -#define _I2C_CTRL_SDAMONEN_SHIFT 21 /**< Shift value for I2C_SDAMONEN */ -#define _I2C_CTRL_SDAMONEN_MASK 0x200000UL /**< Bit mask for I2C_SDAMONEN */ -#define _I2C_CTRL_SDAMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_SDAMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_SDAMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SDAMONEN_DEFAULT (_I2C_CTRL_SDAMONEN_DEFAULT << 21) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_SDAMONEN_DISABLE (_I2C_CTRL_SDAMONEN_DISABLE << 21) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_SDAMONEN_ENABLE (_I2C_CTRL_SDAMONEN_ENABLE << 21) /**< Shifted mode ENABLE for I2C_CTRL */ +#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ +#define _I2C_CTRL_MASK 0x0037B3FFUL /**< Mask for I2C_CTRL */ +#define I2C_CTRL_CORERST (0x1UL << 0) /**< Soft Reset the internal state registers */ +#define _I2C_CTRL_CORERST_SHIFT 0 /**< Shift value for I2C_CORERST */ +#define _I2C_CTRL_CORERST_MASK 0x1UL /**< Bit mask for I2C_CORERST */ +#define _I2C_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CORERST_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_CORERST_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_DEFAULT (_I2C_CTRL_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CORERST_DISABLE (_I2C_CTRL_CORERST_DISABLE << 0) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_ENABLE (_I2C_CTRL_CORERST_ENABLE << 0) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Follower */ +#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DISABLE (_I2C_CTRL_SLAVE_DISABLE << 1) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_ENABLE (_I2C_CTRL_SLAVE_ENABLE << 1) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ +#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DISABLE (_I2C_CTRL_AUTOACK_DISABLE << 2) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_ENABLE (_I2C_CTRL_AUTOACK_ENABLE << 2) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ +#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DISABLE (_I2C_CTRL_AUTOSE_DISABLE << 3) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_ENABLE (_I2C_CTRL_AUTOSE_ENABLE << 3) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ +#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DISABLE (_I2C_CTRL_AUTOSN_DISABLE << 4) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_ENABLE (_I2C_CTRL_AUTOSN_ENABLE << 4) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ +#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DISABLE (_I2C_CTRL_ARBDIS_DISABLE << 5) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_ENABLE (_I2C_CTRL_ARBDIS_ENABLE << 5) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ +#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DISABLE (_I2C_CTRL_GCAMEN_DISABLE << 6) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_ENABLE (_I2C_CTRL_GCAMEN_ENABLE << 6) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ +#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_HALF_FULL 0x00000001UL /**< Mode HALF_FULL for I2C_CTRL */ +#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ +#define I2C_CTRL_TXBIL_HALF_FULL (_I2C_CTRL_TXBIL_HALF_FULL << 7) /**< Shifted mode HALF_FULL for I2C_CTRL */ +#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ +#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ +#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ +#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ +#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ +#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ +#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ +#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ +#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ +#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ +#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C40PCC (_I2C_CTRL_BITO_I2C40PCC << 12) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C80PCC (_I2C_CTRL_BITO_I2C80PCC << 12) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C160PCC (_I2C_CTRL_BITO_I2C160PCC << 12) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ +#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DISABLE (_I2C_CTRL_GIBITO_DISABLE << 15) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_ENABLE (_I2C_CTRL_GIBITO_ENABLE << 15) /**< Shifted mode ENABLE for I2C_CTRL */ +#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ +#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C320PCC 0x00000004UL /**< Mode I2C320PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C1024PCC 0x00000005UL /**< Mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C40PCC (_I2C_CTRL_CLTO_I2C40PCC << 16) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C80PCC (_I2C_CTRL_CLTO_I2C80PCC << 16) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C160PCC (_I2C_CTRL_CLTO_I2C160PCC << 16) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C320PCC (_I2C_CTRL_CLTO_I2C320PCC << 16) /**< Shifted mode I2C320PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C1024PCC (_I2C_CTRL_CLTO_I2C1024PCC << 16) /**< Shifted mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN (0x1UL << 20) /**< SCL Monitor Enable */ +#define _I2C_CTRL_SCLMONEN_SHIFT 20 /**< Shift value for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_MASK 0x100000UL /**< Bit mask for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DEFAULT (_I2C_CTRL_SCLMONEN_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DISABLE (_I2C_CTRL_SCLMONEN_DISABLE << 20) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_ENABLE (_I2C_CTRL_SCLMONEN_ENABLE << 20) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN (0x1UL << 21) /**< SDA Monitor Enable */ +#define _I2C_CTRL_SDAMONEN_SHIFT 21 /**< Shift value for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_MASK 0x200000UL /**< Bit mask for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DEFAULT (_I2C_CTRL_SDAMONEN_DEFAULT << 21) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DISABLE (_I2C_CTRL_SDAMONEN_DISABLE << 21) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_ENABLE (_I2C_CTRL_SDAMONEN_ENABLE << 21) /**< Shifted mode ENABLE for I2C_CTRL */ /* Bit fields for I2C CMD */ -#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ -#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ -#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ -#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ -#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ -#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ -#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ -#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ -#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ -#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ -#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ -#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ -#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ -#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ -#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ -#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ -#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ -#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ -#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ -#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ -#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ -#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ -#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ -#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ -#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ -#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ -#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ +#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ +#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ +#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ +#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ +#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ +#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ +#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ +#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ +#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ +#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ +#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ +#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ +#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ +#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ +#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ +#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ +#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ +#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ +#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ +#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ /* Bit fields for I2C STATE */ -#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ -#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ -#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ -#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ -#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ -#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_MASTER (0x1UL << 1) /**< Leader */ -#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ -#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ -#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ -#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ -#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ -#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ -#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ -#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ -#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ -#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ -#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ -#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ -#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ -#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ -#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ -#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ -#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ -#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ -#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ -#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ -#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ -#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ -#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ -#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ -#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ -#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ -#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ -#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ +#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ +#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ +#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ +#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ +#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ +#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER (0x1UL << 1) /**< Leader */ +#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ +#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ +#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ +#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ +#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ +#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ +#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ +#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ +#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ +#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ +#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ +#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ +#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ +#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ +#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ +#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ +#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ +#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ +#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ +#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ +#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ +#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ +#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ /* Bit fields for I2C STATUS */ -#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ -#define _I2C_STATUS_MASK 0x00000FFFUL /**< Mask for I2C_STATUS */ -#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ -#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ -#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ -#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ -#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ -#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ -#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ -#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ -#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ -#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ -#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ -#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ -#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ -#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ -#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ -#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ -#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ -#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ -#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ -#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ -#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ -#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ -#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ -#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ -#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ -#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ -#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ -#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ -#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ -#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ -#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define _I2C_STATUS_TXBUFCNT_SHIFT 10 /**< Shift value for I2C_TXBUFCNT */ -#define _I2C_STATUS_TXBUFCNT_MASK 0xC00UL /**< Bit mask for I2C_TXBUFCNT */ -#define _I2C_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXBUFCNT_DEFAULT (_I2C_STATUS_TXBUFCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ +#define _I2C_STATUS_MASK 0x00000FFFUL /**< Mask for I2C_STATUS */ +#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ +#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ +#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ +#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ +#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ +#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ +#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ +#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ +#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ +#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ +#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ +#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ +#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ +#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ +#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ +#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ +#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ +#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ +#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ +#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ +#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ +#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ +#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ +#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ +#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_TXBUFCNT_SHIFT 10 /**< Shift value for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_MASK 0xC00UL /**< Bit mask for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBUFCNT_DEFAULT (_I2C_STATUS_TXBUFCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_STATUS */ /* Bit fields for I2C CLKDIV */ -#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ -#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ -#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ -#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ -#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ -#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ +#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ +#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ +#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ +#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ +#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ +#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ /* Bit fields for I2C SADDR */ -#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ -#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ -#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ -#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ -#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ -#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ +#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ +#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ +#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ +#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ +#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ +#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ /* Bit fields for I2C SADDRMASK */ -#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ -#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ -#define _I2C_SADDRMASK_SADDRMASK_SHIFT 1 /**< Shift value for I2C_SADDRMASK */ -#define _I2C_SADDRMASK_SADDRMASK_MASK 0xFEUL /**< Bit mask for I2C_SADDRMASK */ -#define _I2C_SADDRMASK_SADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ -#define I2C_SADDRMASK_SADDRMASK_DEFAULT (_I2C_SADDRMASK_SADDRMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_SHIFT 1 /**< Shift value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_MASK 0xFEUL /**< Bit mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ +#define I2C_SADDRMASK_SADDRMASK_DEFAULT (_I2C_SADDRMASK_SADDRMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ /* Bit fields for I2C RXDATA */ -#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ -#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ -#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ -#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ -#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ -#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ +#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ +#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ +#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ /* Bit fields for I2C RXDOUBLE */ -#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ -#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ -#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ -#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ -#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ -#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ -#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ -#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ -#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ -#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ /* Bit fields for I2C RXDATAP */ -#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ -#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ -#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ -#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ -#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ -#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ +#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ +#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ +#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ /* Bit fields for I2C RXDOUBLEP */ -#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ -#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ -#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ -#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ -#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ -#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ -#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ -#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ -#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ -#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ /* Bit fields for I2C TXDATA */ -#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ -#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ -#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ -#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ -#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ -#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ +#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ +#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ +#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ /* Bit fields for I2C TXDOUBLE */ -#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ -#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ -#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ -#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ -#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ -#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ -#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ -#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ -#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ -#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ /* Bit fields for I2C IF */ -#define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */ -#define _I2C_IF_MASK 0x001FFFFFUL /**< Mask for I2C_IF */ -#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ -#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ -#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ -#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ -#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ -#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ -#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ -#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ -#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ -#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ -#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ -#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ -#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ -#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ -#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ -#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ -#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ -#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ -#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ -#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ -#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ -#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ -#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ -#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ -#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ -#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ -#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ -#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ -#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ -#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ -#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ -#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ -#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ -#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ -#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ -#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ -#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ -#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ -#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ -#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ -#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ -#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ -#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ -#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ -#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ -#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ -#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ -#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ -#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ -#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ -#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ -#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ -#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ -#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ -#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ -#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ -#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ -#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ -#define _I2C_IF_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ -#define _I2C_IF_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ -#define _I2C_IF_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_SCLERR_DEFAULT (_I2C_IF_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ -#define _I2C_IF_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ -#define _I2C_IF_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ -#define _I2C_IF_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_SDAERR_DEFAULT (_I2C_IF_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */ +#define _I2C_IF_MASK 0x001FFFFFUL /**< Mask for I2C_IF */ +#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IF_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IF_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IF_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR_DEFAULT (_I2C_IF_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IF_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IF_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IF_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR_DEFAULT (_I2C_IF_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IF */ /* Bit fields for I2C IEN */ -#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ -#define _I2C_IEN_MASK 0x001FFFFFUL /**< Mask for I2C_IEN */ -#define I2C_IEN_START (0x1UL << 0) /**< START condition Interrupt Flag */ -#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ -#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ -#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ -#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ -#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ -#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ -#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ -#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ -#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ -#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ -#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ -#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ -#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ -#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ -#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ -#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ -#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ -#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ -#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ -#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ -#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ -#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ -#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ -#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ -#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ -#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ -#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ -#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ -#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ -#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ -#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ -#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ -#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ -#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ -#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ -#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ -#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ -#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ -#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ -#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ -#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ -#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ -#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ -#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ -#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ -#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ -#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ -#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ -#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ -#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ -#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ -#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ -#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ -#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ -#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ -#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ -#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ -#define _I2C_IEN_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ -#define _I2C_IEN_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ -#define _I2C_IEN_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SCLERR_DEFAULT (_I2C_IEN_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ -#define _I2C_IEN_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ -#define _I2C_IEN_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ -#define _I2C_IEN_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SDAERR_DEFAULT (_I2C_IEN_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ +#define _I2C_IEN_MASK 0x001FFFFFUL /**< Mask for I2C_IEN */ +#define I2C_IEN_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IEN_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR_DEFAULT (_I2C_IEN_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IEN_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR_DEFAULT (_I2C_IEN_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IEN */ /** @} End of group EFR32SG23_I2C_BitFields */ /** @} End of group EFR32SG23_I2C */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_iadc.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_iadc.h index a6d09cc42e..f223b2d5d1 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_iadc.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_iadc.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_IADC_H #define EFR32SG23_IADC_H - #define IADC_HAS_SET_CLEAR /**************************************************************************//** @@ -43,152 +42,147 @@ *****************************************************************************/ /** IADC CFG Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t CFG; /**< Configuration */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t SCALE; /**< Scaling */ - __IOM uint32_t SCHED; /**< Scheduling */ +typedef struct { + __IOM uint32_t CFG; /**< Configuration */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t SCALE; /**< Scaling */ + __IOM uint32_t SCHED; /**< Scheduling */ } IADC_CFG_TypeDef; - /** IADC SCANTABLE Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t SCAN; /**< SCAN Entry */ +typedef struct { + __IOM uint32_t SCAN; /**< SCAN Entry */ } IADC_SCANTABLE_TypeDef; - /** IADC Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< Enable */ - __IOM uint32_t CTRL; /**< Control */ - __IOM uint32_t CMD; /**< Command */ - __IOM uint32_t TIMER; /**< Timer */ - __IM uint32_t STATUS; /**< Status */ - __IOM uint32_t MASKREQ; /**< Mask Request */ - __IM uint32_t STMASK; /**< Scan Table Mask */ - __IOM uint32_t CMPTHR; /**< Digital Window Comparator Threshold */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - __IOM uint32_t TRIGGER; /**< Trigger */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - uint32_t RESERVED1[5U]; /**< Reserved for future use */ - IADC_CFG_TypeDef CFG[2U]; /**< CFG */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IOM uint32_t SINGLEFIFOCFG; /**< Single FIFO Configuration */ - __IM uint32_t SINGLEFIFODATA; /**< Single FIFO DATA */ - __IM uint32_t SINGLEFIFOSTAT; /**< Single FIFO Status */ - __IM uint32_t SINGLEDATA; /**< Single Data */ - __IOM uint32_t SCANFIFOCFG; /**< Scan FIFO Configuration */ - __IM uint32_t SCANFIFODATA; /**< Scan FIFO Read Data */ - __IM uint32_t SCANFIFOSTAT; /**< Scan FIFO Status */ - __IM uint32_t SCANDATA; /**< Scan Data */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IOM uint32_t SINGLE; /**< Single Queue Port Selection */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - IADC_SCANTABLE_TypeDef SCANTABLE[16U]; /**< SCANTABLE */ - uint32_t RESERVED6[4U]; /**< Reserved for future use */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - uint32_t RESERVED8[963U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< Enable */ - __IOM uint32_t CTRL_SET; /**< Control */ - __IOM uint32_t CMD_SET; /**< Command */ - __IOM uint32_t TIMER_SET; /**< Timer */ - __IM uint32_t STATUS_SET; /**< Status */ - __IOM uint32_t MASKREQ_SET; /**< Mask Request */ - __IM uint32_t STMASK_SET; /**< Scan Table Mask */ - __IOM uint32_t CMPTHR_SET; /**< Digital Window Comparator Threshold */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - __IOM uint32_t TRIGGER_SET; /**< Trigger */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - uint32_t RESERVED10[5U]; /**< Reserved for future use */ - IADC_CFG_TypeDef CFG_SET[2U]; /**< CFG */ - uint32_t RESERVED11[2U]; /**< Reserved for future use */ - __IOM uint32_t SINGLEFIFOCFG_SET; /**< Single FIFO Configuration */ - __IM uint32_t SINGLEFIFODATA_SET; /**< Single FIFO DATA */ - __IM uint32_t SINGLEFIFOSTAT_SET; /**< Single FIFO Status */ - __IM uint32_t SINGLEDATA_SET; /**< Single Data */ - __IOM uint32_t SCANFIFOCFG_SET; /**< Scan FIFO Configuration */ - __IM uint32_t SCANFIFODATA_SET; /**< Scan FIFO Read Data */ - __IM uint32_t SCANFIFOSTAT_SET; /**< Scan FIFO Status */ - __IM uint32_t SCANDATA_SET; /**< Scan Data */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - uint32_t RESERVED13[1U]; /**< Reserved for future use */ - __IOM uint32_t SINGLE_SET; /**< Single Queue Port Selection */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - IADC_SCANTABLE_TypeDef SCANTABLE_SET[16U];/**< SCANTABLE */ - uint32_t RESERVED15[4U]; /**< Reserved for future use */ - uint32_t RESERVED16[1U]; /**< Reserved for future use */ - uint32_t RESERVED17[963U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< Enable */ - __IOM uint32_t CTRL_CLR; /**< Control */ - __IOM uint32_t CMD_CLR; /**< Command */ - __IOM uint32_t TIMER_CLR; /**< Timer */ - __IM uint32_t STATUS_CLR; /**< Status */ - __IOM uint32_t MASKREQ_CLR; /**< Mask Request */ - __IM uint32_t STMASK_CLR; /**< Scan Table Mask */ - __IOM uint32_t CMPTHR_CLR; /**< Digital Window Comparator Threshold */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - __IOM uint32_t TRIGGER_CLR; /**< Trigger */ - uint32_t RESERVED18[1U]; /**< Reserved for future use */ - uint32_t RESERVED19[5U]; /**< Reserved for future use */ - IADC_CFG_TypeDef CFG_CLR[2U]; /**< CFG */ - uint32_t RESERVED20[2U]; /**< Reserved for future use */ - __IOM uint32_t SINGLEFIFOCFG_CLR; /**< Single FIFO Configuration */ - __IM uint32_t SINGLEFIFODATA_CLR; /**< Single FIFO DATA */ - __IM uint32_t SINGLEFIFOSTAT_CLR; /**< Single FIFO Status */ - __IM uint32_t SINGLEDATA_CLR; /**< Single Data */ - __IOM uint32_t SCANFIFOCFG_CLR; /**< Scan FIFO Configuration */ - __IM uint32_t SCANFIFODATA_CLR; /**< Scan FIFO Read Data */ - __IM uint32_t SCANFIFOSTAT_CLR; /**< Scan FIFO Status */ - __IM uint32_t SCANDATA_CLR; /**< Scan Data */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - uint32_t RESERVED22[1U]; /**< Reserved for future use */ - __IOM uint32_t SINGLE_CLR; /**< Single Queue Port Selection */ - uint32_t RESERVED23[1U]; /**< Reserved for future use */ - IADC_SCANTABLE_TypeDef SCANTABLE_CLR[16U];/**< SCANTABLE */ - uint32_t RESERVED24[4U]; /**< Reserved for future use */ - uint32_t RESERVED25[1U]; /**< Reserved for future use */ - uint32_t RESERVED26[963U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< Enable */ - __IOM uint32_t CTRL_TGL; /**< Control */ - __IOM uint32_t CMD_TGL; /**< Command */ - __IOM uint32_t TIMER_TGL; /**< Timer */ - __IM uint32_t STATUS_TGL; /**< Status */ - __IOM uint32_t MASKREQ_TGL; /**< Mask Request */ - __IM uint32_t STMASK_TGL; /**< Scan Table Mask */ - __IOM uint32_t CMPTHR_TGL; /**< Digital Window Comparator Threshold */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - __IOM uint32_t TRIGGER_TGL; /**< Trigger */ - uint32_t RESERVED27[1U]; /**< Reserved for future use */ - uint32_t RESERVED28[5U]; /**< Reserved for future use */ - IADC_CFG_TypeDef CFG_TGL[2U]; /**< CFG */ - uint32_t RESERVED29[2U]; /**< Reserved for future use */ - __IOM uint32_t SINGLEFIFOCFG_TGL; /**< Single FIFO Configuration */ - __IM uint32_t SINGLEFIFODATA_TGL; /**< Single FIFO DATA */ - __IM uint32_t SINGLEFIFOSTAT_TGL; /**< Single FIFO Status */ - __IM uint32_t SINGLEDATA_TGL; /**< Single Data */ - __IOM uint32_t SCANFIFOCFG_TGL; /**< Scan FIFO Configuration */ - __IM uint32_t SCANFIFODATA_TGL; /**< Scan FIFO Read Data */ - __IM uint32_t SCANFIFOSTAT_TGL; /**< Scan FIFO Status */ - __IM uint32_t SCANDATA_TGL; /**< Scan Data */ - uint32_t RESERVED30[1U]; /**< Reserved for future use */ - uint32_t RESERVED31[1U]; /**< Reserved for future use */ - __IOM uint32_t SINGLE_TGL; /**< Single Queue Port Selection */ - uint32_t RESERVED32[1U]; /**< Reserved for future use */ - IADC_SCANTABLE_TypeDef SCANTABLE_TGL[16U];/**< SCANTABLE */ - uint32_t RESERVED33[4U]; /**< Reserved for future use */ - uint32_t RESERVED34[1U]; /**< Reserved for future use */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CTRL; /**< Control */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t TIMER; /**< Timer */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t MASKREQ; /**< Mask Request */ + __IM uint32_t STMASK; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER; /**< Trigger */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG[2U]; /**< CFG */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA; /**< Scan Data */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE; /**< Single Queue Port Selection */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE[16U]; /**< SCANTABLE */ + uint32_t RESERVED6[4U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CTRL_SET; /**< Control */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t TIMER_SET; /**< Timer */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t MASKREQ_SET; /**< Mask Request */ + __IM uint32_t STMASK_SET; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_SET; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_SET; /**< Trigger */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_SET[2U]; /**< CFG */ + uint32_t RESERVED11[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_SET; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_SET; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_SET; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_SET; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_SET; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_SET; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_SET; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_SET; /**< Scan Data */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_SET; /**< Single Queue Port Selection */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_SET[16U]; /**< SCANTABLE */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CTRL_CLR; /**< Control */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t TIMER_CLR; /**< Timer */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t MASKREQ_CLR; /**< Mask Request */ + __IM uint32_t STMASK_CLR; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_CLR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_CLR; /**< Trigger */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_CLR[2U]; /**< CFG */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_CLR; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_CLR; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_CLR; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_CLR; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_CLR; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_CLR; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_CLR; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_CLR; /**< Scan Data */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_CLR; /**< Single Queue Port Selection */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_CLR[16U]; /**< SCANTABLE */ + uint32_t RESERVED24[4U]; /**< Reserved for future use */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + uint32_t RESERVED26[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CTRL_TGL; /**< Control */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t TIMER_TGL; /**< Timer */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t MASKREQ_TGL; /**< Mask Request */ + __IM uint32_t STMASK_TGL; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_TGL; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_TGL; /**< Trigger */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_TGL[2U]; /**< CFG */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_TGL; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_TGL; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_TGL; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_TGL; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_TGL; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_TGL; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_TGL; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_TGL; /**< Scan Data */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + uint32_t RESERVED31[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_TGL; /**< Single Queue Port Selection */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_TGL[16U]; /**< SCANTABLE */ + uint32_t RESERVED33[4U]; /**< Reserved for future use */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ } IADC_TypeDef; /** @} End of group EFR32SG23_IADC */ @@ -200,840 +194,840 @@ typedef struct *****************************************************************************/ /* Bit fields for IADC IPVERSION */ -#define _IADC_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for IADC_IPVERSION */ -#define _IADC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for IADC_IPVERSION */ -#define _IADC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for IADC_IPVERSION */ -#define _IADC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_IPVERSION */ -#define _IADC_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_IPVERSION */ -#define IADC_IPVERSION_IPVERSION_DEFAULT (_IADC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IPVERSION */ +#define _IADC_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for IADC_IPVERSION */ +#define _IADC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_IPVERSION */ +#define IADC_IPVERSION_IPVERSION_DEFAULT (_IADC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IPVERSION */ /* Bit fields for IADC EN */ -#define _IADC_EN_RESETVALUE 0x00000000UL /**< Default value for IADC_EN */ -#define _IADC_EN_MASK 0x00000003UL /**< Mask for IADC_EN */ -#define IADC_EN_EN (0x1UL << 0) /**< Enable IADC Module */ -#define _IADC_EN_EN_SHIFT 0 /**< Shift value for IADC_EN */ -#define _IADC_EN_EN_MASK 0x1UL /**< Bit mask for IADC_EN */ -#define _IADC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ -#define _IADC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for IADC_EN */ -#define _IADC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for IADC_EN */ -#define IADC_EN_EN_DEFAULT (_IADC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_EN */ -#define IADC_EN_EN_DISABLE (_IADC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for IADC_EN */ -#define IADC_EN_EN_ENABLE (_IADC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for IADC_EN */ -#define IADC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _IADC_EN_DISABLING_SHIFT 1 /**< Shift value for IADC_DISABLING */ -#define _IADC_EN_DISABLING_MASK 0x2UL /**< Bit mask for IADC_DISABLING */ -#define _IADC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ -#define IADC_EN_DISABLING_DEFAULT (_IADC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_EN */ +#define _IADC_EN_RESETVALUE 0x00000000UL /**< Default value for IADC_EN */ +#define _IADC_EN_MASK 0x00000003UL /**< Mask for IADC_EN */ +#define IADC_EN_EN (0x1UL << 0) /**< Enable IADC Module */ +#define _IADC_EN_EN_SHIFT 0 /**< Shift value for IADC_EN */ +#define _IADC_EN_EN_MASK 0x1UL /**< Bit mask for IADC_EN */ +#define _IADC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ +#define _IADC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for IADC_EN */ +#define _IADC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for IADC_EN */ +#define IADC_EN_EN_DEFAULT (_IADC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_EN */ +#define IADC_EN_EN_DISABLE (_IADC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for IADC_EN */ +#define IADC_EN_EN_ENABLE (_IADC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for IADC_EN */ +#define IADC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _IADC_EN_DISABLING_SHIFT 1 /**< Shift value for IADC_DISABLING */ +#define _IADC_EN_DISABLING_MASK 0x2UL /**< Bit mask for IADC_DISABLING */ +#define _IADC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ +#define IADC_EN_DISABLING_DEFAULT (_IADC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_EN */ /* Bit fields for IADC CTRL */ -#define _IADC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IADC_CTRL */ -#define _IADC_CTRL_MASK 0x707F003FUL /**< Mask for IADC_CTRL */ -#define IADC_CTRL_EM23WUCONVERT (0x1UL << 0) /**< EM23 Wakeup on Conversion */ -#define _IADC_CTRL_EM23WUCONVERT_SHIFT 0 /**< Shift value for IADC_EM23WUCONVERT */ -#define _IADC_CTRL_EM23WUCONVERT_MASK 0x1UL /**< Bit mask for IADC_EM23WUCONVERT */ -#define _IADC_CTRL_EM23WUCONVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_EM23WUCONVERT_WUDVL 0x00000000UL /**< Mode WUDVL for IADC_CTRL */ -#define _IADC_CTRL_EM23WUCONVERT_WUCONVERT 0x00000001UL /**< Mode WUCONVERT for IADC_CTRL */ -#define IADC_CTRL_EM23WUCONVERT_DEFAULT (_IADC_CTRL_EM23WUCONVERT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_EM23WUCONVERT_WUDVL (_IADC_CTRL_EM23WUCONVERT_WUDVL << 0) /**< Shifted mode WUDVL for IADC_CTRL */ -#define IADC_CTRL_EM23WUCONVERT_WUCONVERT (_IADC_CTRL_EM23WUCONVERT_WUCONVERT << 0) /**< Shifted mode WUCONVERT for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND0 (0x1UL << 1) /**< ADC_CLK Suspend - PRS0 */ -#define _IADC_CTRL_ADCCLKSUSPEND0_SHIFT 1 /**< Shift value for IADC_ADCCLKSUSPEND0 */ -#define _IADC_CTRL_ADCCLKSUSPEND0_MASK 0x2UL /**< Bit mask for IADC_ADCCLKSUSPEND0 */ -#define _IADC_CTRL_ADCCLKSUSPEND0_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ -#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND0_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND0_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS << 1) /**< Shifted mode PRSWUDIS for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN << 1) /**< Shifted mode PRSWUEN for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND1 (0x1UL << 2) /**< ADC_CLK Suspend - PRS1 */ -#define _IADC_CTRL_ADCCLKSUSPEND1_SHIFT 2 /**< Shift value for IADC_ADCCLKSUSPEND1 */ -#define _IADC_CTRL_ADCCLKSUSPEND1_MASK 0x4UL /**< Bit mask for IADC_ADCCLKSUSPEND1 */ -#define _IADC_CTRL_ADCCLKSUSPEND1_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ -#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND1_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND1_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS << 2) /**< Shifted mode PRSWUDIS for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN << 2) /**< Shifted mode PRSWUEN for IADC_CTRL */ -#define IADC_CTRL_DBGHALT (0x1UL << 3) /**< Debug Halt */ -#define _IADC_CTRL_DBGHALT_SHIFT 3 /**< Shift value for IADC_DBGHALT */ -#define _IADC_CTRL_DBGHALT_MASK 0x8UL /**< Bit mask for IADC_DBGHALT */ -#define _IADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ -#define _IADC_CTRL_DBGHALT_HALT 0x00000001UL /**< Mode HALT for IADC_CTRL */ -#define IADC_CTRL_DBGHALT_DEFAULT (_IADC_CTRL_DBGHALT_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_DBGHALT_NORMAL (_IADC_CTRL_DBGHALT_NORMAL << 3) /**< Shifted mode NORMAL for IADC_CTRL */ -#define IADC_CTRL_DBGHALT_HALT (_IADC_CTRL_DBGHALT_HALT << 3) /**< Shifted mode HALT for IADC_CTRL */ -#define _IADC_CTRL_WARMUPMODE_SHIFT 4 /**< Shift value for IADC_WARMUPMODE */ -#define _IADC_CTRL_WARMUPMODE_MASK 0x30UL /**< Bit mask for IADC_WARMUPMODE */ -#define _IADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ -#define _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for IADC_CTRL */ -#define _IADC_CTRL_WARMUPMODE_KEEPWARM 0x00000002UL /**< Mode KEEPWARM for IADC_CTRL */ -#define IADC_CTRL_WARMUPMODE_DEFAULT (_IADC_CTRL_WARMUPMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_WARMUPMODE_NORMAL (_IADC_CTRL_WARMUPMODE_NORMAL << 4) /**< Shifted mode NORMAL for IADC_CTRL */ -#define IADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_IADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 4) /**< Shifted mode KEEPINSTANDBY for IADC_CTRL */ -#define IADC_CTRL_WARMUPMODE_KEEPWARM (_IADC_CTRL_WARMUPMODE_KEEPWARM << 4) /**< Shifted mode KEEPWARM for IADC_CTRL */ -#define _IADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for IADC_TIMEBASE */ -#define _IADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for IADC_TIMEBASE */ -#define _IADC_CTRL_TIMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_TIMEBASE_DEFAULT (_IADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_SHIFT 28 /**< Shift value for IADC_HSCLKRATE */ -#define _IADC_CTRL_HSCLKRATE_MASK 0x70000000UL /**< Bit mask for IADC_HSCLKRATE */ -#define _IADC_CTRL_HSCLKRATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_DIV1 0x00000000UL /**< Mode DIV1 for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_DIV2 0x00000001UL /**< Mode DIV2 for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_DIV3 0x00000002UL /**< Mode DIV3 for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_DIV4 0x00000003UL /**< Mode DIV4 for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DEFAULT (_IADC_CTRL_HSCLKRATE_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DIV1 (_IADC_CTRL_HSCLKRATE_DIV1 << 28) /**< Shifted mode DIV1 for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DIV2 (_IADC_CTRL_HSCLKRATE_DIV2 << 28) /**< Shifted mode DIV2 for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DIV3 (_IADC_CTRL_HSCLKRATE_DIV3 << 28) /**< Shifted mode DIV3 for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DIV4 (_IADC_CTRL_HSCLKRATE_DIV4 << 28) /**< Shifted mode DIV4 for IADC_CTRL */ +#define _IADC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IADC_CTRL */ +#define _IADC_CTRL_MASK 0x707F003FUL /**< Mask for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT (0x1UL << 0) /**< EM23 Wakeup on Conversion */ +#define _IADC_CTRL_EM23WUCONVERT_SHIFT 0 /**< Shift value for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_MASK 0x1UL /**< Bit mask for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUDVL 0x00000000UL /**< Mode WUDVL for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUCONVERT 0x00000001UL /**< Mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_DEFAULT (_IADC_CTRL_EM23WUCONVERT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUDVL (_IADC_CTRL_EM23WUCONVERT_WUDVL << 0) /**< Shifted mode WUDVL for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUCONVERT (_IADC_CTRL_EM23WUCONVERT_WUCONVERT << 0) /**< Shifted mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0 (0x1UL << 1) /**< ADC_CLK Suspend - PRS0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_SHIFT 1 /**< Shift value for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_MASK 0x2UL /**< Bit mask for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND0_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS << 1) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN << 1) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1 (0x1UL << 2) /**< ADC_CLK Suspend - PRS1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_SHIFT 2 /**< Shift value for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_MASK 0x4UL /**< Bit mask for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND1_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS << 2) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN << 2) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_DBGHALT (0x1UL << 3) /**< Debug Halt */ +#define _IADC_CTRL_DBGHALT_SHIFT 3 /**< Shift value for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_MASK 0x8UL /**< Bit mask for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_HALT 0x00000001UL /**< Mode HALT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_DEFAULT (_IADC_CTRL_DBGHALT_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_NORMAL (_IADC_CTRL_DBGHALT_NORMAL << 3) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_HALT (_IADC_CTRL_DBGHALT_HALT << 3) /**< Shifted mode HALT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_SHIFT 4 /**< Shift value for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_MASK 0x30UL /**< Bit mask for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPWARM 0x00000002UL /**< Mode KEEPWARM for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_DEFAULT (_IADC_CTRL_WARMUPMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_NORMAL (_IADC_CTRL_WARMUPMODE_NORMAL << 4) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_IADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 4) /**< Shifted mode KEEPINSTANDBY for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPWARM (_IADC_CTRL_WARMUPMODE_KEEPWARM << 4) /**< Shifted mode KEEPWARM for IADC_CTRL */ +#define _IADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_TIMEBASE_DEFAULT (_IADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_SHIFT 28 /**< Shift value for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_MASK 0x70000000UL /**< Bit mask for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV1 0x00000000UL /**< Mode DIV1 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV2 0x00000001UL /**< Mode DIV2 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV3 0x00000002UL /**< Mode DIV3 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV4 0x00000003UL /**< Mode DIV4 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DEFAULT (_IADC_CTRL_HSCLKRATE_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV1 (_IADC_CTRL_HSCLKRATE_DIV1 << 28) /**< Shifted mode DIV1 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV2 (_IADC_CTRL_HSCLKRATE_DIV2 << 28) /**< Shifted mode DIV2 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV3 (_IADC_CTRL_HSCLKRATE_DIV3 << 28) /**< Shifted mode DIV3 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV4 (_IADC_CTRL_HSCLKRATE_DIV4 << 28) /**< Shifted mode DIV4 for IADC_CTRL */ /* Bit fields for IADC CMD */ -#define _IADC_CMD_RESETVALUE 0x00000000UL /**< Default value for IADC_CMD */ -#define _IADC_CMD_MASK 0x0303001BUL /**< Mask for IADC_CMD */ -#define IADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Queue Start */ -#define _IADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for IADC_SINGLESTART */ -#define _IADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for IADC_SINGLESTART */ -#define _IADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLESTART_DEFAULT (_IADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Queue Stop */ -#define _IADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for IADC_SINGLESTOP */ -#define _IADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for IADC_SINGLESTOP */ -#define _IADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLESTOP_DEFAULT (_IADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANSTART (0x1UL << 3) /**< Scan Queue Start */ -#define _IADC_CMD_SCANSTART_SHIFT 3 /**< Shift value for IADC_SCANSTART */ -#define _IADC_CMD_SCANSTART_MASK 0x8UL /**< Bit mask for IADC_SCANSTART */ -#define _IADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANSTART_DEFAULT (_IADC_CMD_SCANSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANSTOP (0x1UL << 4) /**< Scan Queue Stop */ -#define _IADC_CMD_SCANSTOP_SHIFT 4 /**< Shift value for IADC_SCANSTOP */ -#define _IADC_CMD_SCANSTOP_MASK 0x10UL /**< Bit mask for IADC_SCANSTOP */ -#define _IADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANSTOP_DEFAULT (_IADC_CMD_SCANSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_TIMEREN (0x1UL << 16) /**< Timer Enable */ -#define _IADC_CMD_TIMEREN_SHIFT 16 /**< Shift value for IADC_TIMEREN */ -#define _IADC_CMD_TIMEREN_MASK 0x10000UL /**< Bit mask for IADC_TIMEREN */ -#define _IADC_CMD_TIMEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_TIMEREN_DEFAULT (_IADC_CMD_TIMEREN_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_TIMERDIS (0x1UL << 17) /**< Timer Disable */ -#define _IADC_CMD_TIMERDIS_SHIFT 17 /**< Shift value for IADC_TIMERDIS */ -#define _IADC_CMD_TIMERDIS_MASK 0x20000UL /**< Bit mask for IADC_TIMERDIS */ -#define _IADC_CMD_TIMERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_TIMERDIS_DEFAULT (_IADC_CMD_TIMERDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLEFIFOFLUSH (0x1UL << 24) /**< Flush the Single FIFO */ -#define _IADC_CMD_SINGLEFIFOFLUSH_SHIFT 24 /**< Shift value for IADC_SINGLEFIFOFLUSH */ -#define _IADC_CMD_SINGLEFIFOFLUSH_MASK 0x1000000UL /**< Bit mask for IADC_SINGLEFIFOFLUSH */ -#define _IADC_CMD_SINGLEFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLEFIFOFLUSH_DEFAULT (_IADC_CMD_SINGLEFIFOFLUSH_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANFIFOFLUSH (0x1UL << 25) /**< Flush the Scan FIFO */ -#define _IADC_CMD_SCANFIFOFLUSH_SHIFT 25 /**< Shift value for IADC_SCANFIFOFLUSH */ -#define _IADC_CMD_SCANFIFOFLUSH_MASK 0x2000000UL /**< Bit mask for IADC_SCANFIFOFLUSH */ -#define _IADC_CMD_SCANFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANFIFOFLUSH_DEFAULT (_IADC_CMD_SCANFIFOFLUSH_DEFAULT << 25) /**< Shifted mode DEFAULT for IADC_CMD */ +#define _IADC_CMD_RESETVALUE 0x00000000UL /**< Default value for IADC_CMD */ +#define _IADC_CMD_MASK 0x0303001BUL /**< Mask for IADC_CMD */ +#define IADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Queue Start */ +#define _IADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTART_DEFAULT (_IADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Queue Stop */ +#define _IADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP_DEFAULT (_IADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART (0x1UL << 3) /**< Scan Queue Start */ +#define _IADC_CMD_SCANSTART_SHIFT 3 /**< Shift value for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_MASK 0x8UL /**< Bit mask for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART_DEFAULT (_IADC_CMD_SCANSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP (0x1UL << 4) /**< Scan Queue Stop */ +#define _IADC_CMD_SCANSTOP_SHIFT 4 /**< Shift value for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_MASK 0x10UL /**< Bit mask for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP_DEFAULT (_IADC_CMD_SCANSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN (0x1UL << 16) /**< Timer Enable */ +#define _IADC_CMD_TIMEREN_SHIFT 16 /**< Shift value for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_MASK 0x10000UL /**< Bit mask for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN_DEFAULT (_IADC_CMD_TIMEREN_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS (0x1UL << 17) /**< Timer Disable */ +#define _IADC_CMD_TIMERDIS_SHIFT 17 /**< Shift value for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_MASK 0x20000UL /**< Bit mask for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS_DEFAULT (_IADC_CMD_TIMERDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH (0x1UL << 24) /**< Flush the Single FIFO */ +#define _IADC_CMD_SINGLEFIFOFLUSH_SHIFT 24 /**< Shift value for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_MASK 0x1000000UL /**< Bit mask for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH_DEFAULT (_IADC_CMD_SINGLEFIFOFLUSH_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH (0x1UL << 25) /**< Flush the Scan FIFO */ +#define _IADC_CMD_SCANFIFOFLUSH_SHIFT 25 /**< Shift value for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_MASK 0x2000000UL /**< Bit mask for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH_DEFAULT (_IADC_CMD_SCANFIFOFLUSH_DEFAULT << 25) /**< Shifted mode DEFAULT for IADC_CMD */ /* Bit fields for IADC TIMER */ -#define _IADC_TIMER_RESETVALUE 0x00000000UL /**< Default value for IADC_TIMER */ -#define _IADC_TIMER_MASK 0x0000FFFFUL /**< Mask for IADC_TIMER */ -#define _IADC_TIMER_TIMER_SHIFT 0 /**< Shift value for IADC_TIMER */ -#define _IADC_TIMER_TIMER_MASK 0xFFFFUL /**< Bit mask for IADC_TIMER */ -#define _IADC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TIMER */ -#define IADC_TIMER_TIMER_DEFAULT (_IADC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TIMER */ +#define _IADC_TIMER_RESETVALUE 0x00000000UL /**< Default value for IADC_TIMER */ +#define _IADC_TIMER_MASK 0x0000FFFFUL /**< Mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_SHIFT 0 /**< Shift value for IADC_TIMER */ +#define _IADC_TIMER_TIMER_MASK 0xFFFFUL /**< Bit mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TIMER */ +#define IADC_TIMER_TIMER_DEFAULT (_IADC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TIMER */ /* Bit fields for IADC STATUS */ -#define _IADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IADC_STATUS */ -#define _IADC_STATUS_MASK 0x4131CF5BUL /**< Mask for IADC_STATUS */ -#define IADC_STATUS_SINGLEQEN (0x1UL << 0) /**< Single Queue Enabled */ -#define _IADC_STATUS_SINGLEQEN_SHIFT 0 /**< Shift value for IADC_SINGLEQEN */ -#define _IADC_STATUS_SINGLEQEN_MASK 0x1UL /**< Bit mask for IADC_SINGLEQEN */ -#define _IADC_STATUS_SINGLEQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEQEN_DEFAULT (_IADC_STATUS_SINGLEQEN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEQUEUEPENDING (0x1UL << 1) /**< Single Queue Pending */ -#define _IADC_STATUS_SINGLEQUEUEPENDING_SHIFT 1 /**< Shift value for IADC_SINGLEQUEUEPENDING */ -#define _IADC_STATUS_SINGLEQUEUEPENDING_MASK 0x2UL /**< Bit mask for IADC_SINGLEQUEUEPENDING */ -#define _IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT (_IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANQEN (0x1UL << 3) /**< Scan Queued Enabled */ -#define _IADC_STATUS_SCANQEN_SHIFT 3 /**< Shift value for IADC_SCANQEN */ -#define _IADC_STATUS_SCANQEN_MASK 0x8UL /**< Bit mask for IADC_SCANQEN */ -#define _IADC_STATUS_SCANQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANQEN_DEFAULT (_IADC_STATUS_SCANQEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANQUEUEPENDING (0x1UL << 4) /**< Scan Queue Pending */ -#define _IADC_STATUS_SCANQUEUEPENDING_SHIFT 4 /**< Shift value for IADC_SCANQUEUEPENDING */ -#define _IADC_STATUS_SCANQUEUEPENDING_MASK 0x10UL /**< Bit mask for IADC_SCANQUEUEPENDING */ -#define _IADC_STATUS_SCANQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANQUEUEPENDING_DEFAULT (_IADC_STATUS_SCANQUEUEPENDING_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_CONVERTING (0x1UL << 6) /**< Converting */ -#define _IADC_STATUS_CONVERTING_SHIFT 6 /**< Shift value for IADC_CONVERTING */ -#define _IADC_STATUS_CONVERTING_MASK 0x40UL /**< Bit mask for IADC_CONVERTING */ -#define _IADC_STATUS_CONVERTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_CONVERTING_DEFAULT (_IADC_STATUS_CONVERTING_DEFAULT << 6) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEFIFODV (0x1UL << 8) /**< SINGLEFIFO Data Valid */ -#define _IADC_STATUS_SINGLEFIFODV_SHIFT 8 /**< Shift value for IADC_SINGLEFIFODV */ -#define _IADC_STATUS_SINGLEFIFODV_MASK 0x100UL /**< Bit mask for IADC_SINGLEFIFODV */ -#define _IADC_STATUS_SINGLEFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEFIFODV_DEFAULT (_IADC_STATUS_SINGLEFIFODV_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANFIFODV (0x1UL << 9) /**< SCANFIFO Data Valid */ -#define _IADC_STATUS_SCANFIFODV_SHIFT 9 /**< Shift value for IADC_SCANFIFODV */ -#define _IADC_STATUS_SCANFIFODV_MASK 0x200UL /**< Bit mask for IADC_SCANFIFODV */ -#define _IADC_STATUS_SCANFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANFIFODV_DEFAULT (_IADC_STATUS_SCANFIFODV_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEFIFOFLUSHING (0x1UL << 14) /**< The Single FIFO is flushing */ -#define _IADC_STATUS_SINGLEFIFOFLUSHING_SHIFT 14 /**< Shift value for IADC_SINGLEFIFOFLUSHING */ -#define _IADC_STATUS_SINGLEFIFOFLUSHING_MASK 0x4000UL /**< Bit mask for IADC_SINGLEFIFOFLUSHING */ -#define _IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT (_IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT << 14) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANFIFOFLUSHING (0x1UL << 15) /**< The Scan FIFO is flushing */ -#define _IADC_STATUS_SCANFIFOFLUSHING_SHIFT 15 /**< Shift value for IADC_SCANFIFOFLUSHING */ -#define _IADC_STATUS_SCANFIFOFLUSHING_MASK 0x8000UL /**< Bit mask for IADC_SCANFIFOFLUSHING */ -#define _IADC_STATUS_SCANFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANFIFOFLUSHING_DEFAULT (_IADC_STATUS_SCANFIFOFLUSHING_DEFAULT << 15) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_TIMERACTIVE (0x1UL << 16) /**< Timer Active */ -#define _IADC_STATUS_TIMERACTIVE_SHIFT 16 /**< Shift value for IADC_TIMERACTIVE */ -#define _IADC_STATUS_TIMERACTIVE_MASK 0x10000UL /**< Bit mask for IADC_TIMERACTIVE */ -#define _IADC_STATUS_TIMERACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_TIMERACTIVE_DEFAULT (_IADC_STATUS_TIMERACTIVE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEWRITEPENDING (0x1UL << 20) /**< SINGLE write pending */ -#define _IADC_STATUS_SINGLEWRITEPENDING_SHIFT 20 /**< Shift value for IADC_SINGLEWRITEPENDING */ -#define _IADC_STATUS_SINGLEWRITEPENDING_MASK 0x100000UL /**< Bit mask for IADC_SINGLEWRITEPENDING */ -#define _IADC_STATUS_SINGLEWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEWRITEPENDING_DEFAULT (_IADC_STATUS_SINGLEWRITEPENDING_DEFAULT << 20) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_MASKREQWRITEPENDING (0x1UL << 21) /**< MASKREQ write pending */ -#define _IADC_STATUS_MASKREQWRITEPENDING_SHIFT 21 /**< Shift value for IADC_MASKREQWRITEPENDING */ -#define _IADC_STATUS_MASKREQWRITEPENDING_MASK 0x200000UL /**< Bit mask for IADC_MASKREQWRITEPENDING */ -#define _IADC_STATUS_MASKREQWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_MASKREQWRITEPENDING_DEFAULT (_IADC_STATUS_MASKREQWRITEPENDING_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SYNCBUSY (0x1UL << 24) /**< SYNCBUSY */ -#define _IADC_STATUS_SYNCBUSY_SHIFT 24 /**< Shift value for IADC_SYNCBUSY */ -#define _IADC_STATUS_SYNCBUSY_MASK 0x1000000UL /**< Bit mask for IADC_SYNCBUSY */ -#define _IADC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SYNCBUSY_DEFAULT (_IADC_STATUS_SYNCBUSY_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_ADCWARM (0x1UL << 30) /**< ADCWARM */ -#define _IADC_STATUS_ADCWARM_SHIFT 30 /**< Shift value for IADC_ADCWARM */ -#define _IADC_STATUS_ADCWARM_MASK 0x40000000UL /**< Bit mask for IADC_ADCWARM */ -#define _IADC_STATUS_ADCWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_ADCWARM_DEFAULT (_IADC_STATUS_ADCWARM_DEFAULT << 30) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define _IADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IADC_STATUS */ +#define _IADC_STATUS_MASK 0x4131CF5BUL /**< Mask for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN (0x1UL << 0) /**< Single Queue Enabled */ +#define _IADC_STATUS_SINGLEQEN_SHIFT 0 /**< Shift value for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_MASK 0x1UL /**< Bit mask for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN_DEFAULT (_IADC_STATUS_SINGLEQEN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING (0x1UL << 1) /**< Single Queue Pending */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_SHIFT 1 /**< Shift value for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_MASK 0x2UL /**< Bit mask for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT (_IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN (0x1UL << 3) /**< Scan Queued Enabled */ +#define _IADC_STATUS_SCANQEN_SHIFT 3 /**< Shift value for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_MASK 0x8UL /**< Bit mask for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN_DEFAULT (_IADC_STATUS_SCANQEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING (0x1UL << 4) /**< Scan Queue Pending */ +#define _IADC_STATUS_SCANQUEUEPENDING_SHIFT 4 /**< Shift value for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_MASK 0x10UL /**< Bit mask for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING_DEFAULT (_IADC_STATUS_SCANQUEUEPENDING_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING (0x1UL << 6) /**< Converting */ +#define _IADC_STATUS_CONVERTING_SHIFT 6 /**< Shift value for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_MASK 0x40UL /**< Bit mask for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING_DEFAULT (_IADC_STATUS_CONVERTING_DEFAULT << 6) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV (0x1UL << 8) /**< SINGLEFIFO Data Valid */ +#define _IADC_STATUS_SINGLEFIFODV_SHIFT 8 /**< Shift value for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_MASK 0x100UL /**< Bit mask for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV_DEFAULT (_IADC_STATUS_SINGLEFIFODV_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV (0x1UL << 9) /**< SCANFIFO Data Valid */ +#define _IADC_STATUS_SCANFIFODV_SHIFT 9 /**< Shift value for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_MASK 0x200UL /**< Bit mask for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV_DEFAULT (_IADC_STATUS_SCANFIFODV_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING (0x1UL << 14) /**< The Single FIFO is flushing */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_SHIFT 14 /**< Shift value for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_MASK 0x4000UL /**< Bit mask for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT (_IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT << 14) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING (0x1UL << 15) /**< The Scan FIFO is flushing */ +#define _IADC_STATUS_SCANFIFOFLUSHING_SHIFT 15 /**< Shift value for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_MASK 0x8000UL /**< Bit mask for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING_DEFAULT (_IADC_STATUS_SCANFIFOFLUSHING_DEFAULT << 15) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE (0x1UL << 16) /**< Timer Active */ +#define _IADC_STATUS_TIMERACTIVE_SHIFT 16 /**< Shift value for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_MASK 0x10000UL /**< Bit mask for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE_DEFAULT (_IADC_STATUS_TIMERACTIVE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING (0x1UL << 20) /**< SINGLE write pending */ +#define _IADC_STATUS_SINGLEWRITEPENDING_SHIFT 20 /**< Shift value for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_MASK 0x100000UL /**< Bit mask for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING_DEFAULT (_IADC_STATUS_SINGLEWRITEPENDING_DEFAULT << 20) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING (0x1UL << 21) /**< MASKREQ write pending */ +#define _IADC_STATUS_MASKREQWRITEPENDING_SHIFT 21 /**< Shift value for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_MASK 0x200000UL /**< Bit mask for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING_DEFAULT (_IADC_STATUS_MASKREQWRITEPENDING_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY (0x1UL << 24) /**< SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_SHIFT 24 /**< Shift value for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_MASK 0x1000000UL /**< Bit mask for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY_DEFAULT (_IADC_STATUS_SYNCBUSY_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM (0x1UL << 30) /**< ADCWARM */ +#define _IADC_STATUS_ADCWARM_SHIFT 30 /**< Shift value for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_MASK 0x40000000UL /**< Bit mask for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM_DEFAULT (_IADC_STATUS_ADCWARM_DEFAULT << 30) /**< Shifted mode DEFAULT for IADC_STATUS */ /* Bit fields for IADC MASKREQ */ -#define _IADC_MASKREQ_RESETVALUE 0x00000000UL /**< Default value for IADC_MASKREQ */ -#define _IADC_MASKREQ_MASK 0x0000FFFFUL /**< Mask for IADC_MASKREQ */ -#define _IADC_MASKREQ_MASKREQ_SHIFT 0 /**< Shift value for IADC_MASKREQ */ -#define _IADC_MASKREQ_MASKREQ_MASK 0xFFFFUL /**< Bit mask for IADC_MASKREQ */ -#define _IADC_MASKREQ_MASKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_MASKREQ */ -#define IADC_MASKREQ_MASKREQ_DEFAULT (_IADC_MASKREQ_MASKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_MASKREQ */ +#define _IADC_MASKREQ_RESETVALUE 0x00000000UL /**< Default value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASK 0x0000FFFFUL /**< Mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_SHIFT 0 /**< Shift value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_MASK 0xFFFFUL /**< Bit mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_MASKREQ */ +#define IADC_MASKREQ_MASKREQ_DEFAULT (_IADC_MASKREQ_MASKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_MASKREQ */ /* Bit fields for IADC STMASK */ -#define _IADC_STMASK_RESETVALUE 0x00000000UL /**< Default value for IADC_STMASK */ -#define _IADC_STMASK_MASK 0x0000FFFFUL /**< Mask for IADC_STMASK */ -#define _IADC_STMASK_STMASK_SHIFT 0 /**< Shift value for IADC_STMASK */ -#define _IADC_STMASK_STMASK_MASK 0xFFFFUL /**< Bit mask for IADC_STMASK */ -#define _IADC_STMASK_STMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STMASK */ -#define IADC_STMASK_STMASK_DEFAULT (_IADC_STMASK_STMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STMASK */ +#define _IADC_STMASK_RESETVALUE 0x00000000UL /**< Default value for IADC_STMASK */ +#define _IADC_STMASK_MASK 0x0000FFFFUL /**< Mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_SHIFT 0 /**< Shift value for IADC_STMASK */ +#define _IADC_STMASK_STMASK_MASK 0xFFFFUL /**< Bit mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STMASK */ +#define IADC_STMASK_STMASK_DEFAULT (_IADC_STMASK_STMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STMASK */ /* Bit fields for IADC CMPTHR */ -#define _IADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for IADC_CMPTHR */ -#define _IADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for IADC_CMPTHR */ -#define _IADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for IADC_ADLT */ -#define _IADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for IADC_ADLT */ -#define _IADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ -#define IADC_CMPTHR_ADLT_DEFAULT (_IADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMPTHR */ -#define _IADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for IADC_ADGT */ -#define _IADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for IADC_ADGT */ -#define _IADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ -#define IADC_CMPTHR_ADGT_DEFAULT (_IADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMPTHR */ +#define _IADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for IADC_CMPTHR */ +#define _IADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADLT_DEFAULT (_IADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADGT_DEFAULT (_IADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMPTHR */ /* Bit fields for IADC IF */ -#define _IADC_IF_RESETVALUE 0x00000000UL /**< Default value for IADC_IF */ -#define _IADC_IF_MASK 0x800F338FUL /**< Mask for IADC_IF */ -#define IADC_IF_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level */ -#define _IADC_IF_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ -#define _IADC_IF_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ -#define _IADC_IF_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFODVL_DEFAULT (_IADC_IF_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level */ -#define _IADC_IF_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ -#define _IADC_IF_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ -#define _IADC_IF_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFODVL_DEFAULT (_IADC_IF_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare */ -#define _IADC_IF_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ -#define _IADC_IF_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ -#define _IADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLECMP_DEFAULT (_IADC_IF_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare */ -#define _IADC_IF_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ -#define _IADC_IF_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ -#define _IADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANCMP_DEFAULT (_IADC_IF_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done */ -#define _IADC_IF_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ -#define _IADC_IF_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ -#define _IADC_IF_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANENTRYDONE_DEFAULT (_IADC_IF_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done */ -#define _IADC_IF_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ -#define _IADC_IF_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ -#define _IADC_IF_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANTABLEDONE_DEFAULT (_IADC_IF_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done */ -#define _IADC_IF_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ -#define _IADC_IF_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ -#define _IADC_IF_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEDONE_DEFAULT (_IADC_IF_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_POLARITYERR (0x1UL << 12) /**< Polarity Error */ -#define _IADC_IF_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ -#define _IADC_IF_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ -#define _IADC_IF_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_POLARITYERR_DEFAULT (_IADC_IF_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error */ -#define _IADC_IF_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ -#define _IADC_IF_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ -#define _IADC_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_PORTALLOCERR_DEFAULT (_IADC_IF_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow */ -#define _IADC_IF_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ -#define _IADC_IF_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ -#define _IADC_IF_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFOOF_DEFAULT (_IADC_IF_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow */ -#define _IADC_IF_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ -#define _IADC_IF_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ -#define _IADC_IF_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFOOF_DEFAULT (_IADC_IF_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow */ -#define _IADC_IF_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ -#define _IADC_IF_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ -#define _IADC_IF_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFOUF_DEFAULT (_IADC_IF_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow */ -#define _IADC_IF_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ -#define _IADC_IF_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ -#define _IADC_IF_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFOUF_DEFAULT (_IADC_IF_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error */ -#define _IADC_IF_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ -#define _IADC_IF_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ -#define _IADC_IF_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_EM23ABORTERROR_DEFAULT (_IADC_IF_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IF */ +#define _IADC_IF_RESETVALUE 0x00000000UL /**< Default value for IADC_IF */ +#define _IADC_IF_MASK 0x800F338FUL /**< Mask for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level */ +#define _IADC_IF_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL_DEFAULT (_IADC_IF_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level */ +#define _IADC_IF_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL_DEFAULT (_IADC_IF_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare */ +#define _IADC_IF_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP_DEFAULT (_IADC_IF_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare */ +#define _IADC_IF_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP_DEFAULT (_IADC_IF_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done */ +#define _IADC_IF_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE_DEFAULT (_IADC_IF_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done */ +#define _IADC_IF_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE_DEFAULT (_IADC_IF_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done */ +#define _IADC_IF_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE_DEFAULT (_IADC_IF_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR (0x1UL << 12) /**< Polarity Error */ +#define _IADC_IF_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR_DEFAULT (_IADC_IF_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error */ +#define _IADC_IF_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR_DEFAULT (_IADC_IF_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow */ +#define _IADC_IF_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF_DEFAULT (_IADC_IF_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow */ +#define _IADC_IF_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF_DEFAULT (_IADC_IF_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow */ +#define _IADC_IF_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF_DEFAULT (_IADC_IF_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow */ +#define _IADC_IF_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF_DEFAULT (_IADC_IF_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error */ +#define _IADC_IF_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR_DEFAULT (_IADC_IF_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IF */ /* Bit fields for IADC IEN */ -#define _IADC_IEN_RESETVALUE 0x00000000UL /**< Default value for IADC_IEN */ -#define _IADC_IEN_MASK 0x800F338FUL /**< Mask for IADC_IEN */ -#define IADC_IEN_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level Enable */ -#define _IADC_IEN_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ -#define _IADC_IEN_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ -#define _IADC_IEN_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFODVL_DEFAULT (_IADC_IEN_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level Enable */ -#define _IADC_IEN_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ -#define _IADC_IEN_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ -#define _IADC_IEN_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFODVL_DEFAULT (_IADC_IEN_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare Enable */ -#define _IADC_IEN_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ -#define _IADC_IEN_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ -#define _IADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLECMP_DEFAULT (_IADC_IEN_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare Enable */ -#define _IADC_IEN_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ -#define _IADC_IEN_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ -#define _IADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANCMP_DEFAULT (_IADC_IEN_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done Enable */ -#define _IADC_IEN_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ -#define _IADC_IEN_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ -#define _IADC_IEN_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANENTRYDONE_DEFAULT (_IADC_IEN_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done Enable */ -#define _IADC_IEN_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ -#define _IADC_IEN_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ -#define _IADC_IEN_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANTABLEDONE_DEFAULT (_IADC_IEN_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done Enable */ -#define _IADC_IEN_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ -#define _IADC_IEN_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ -#define _IADC_IEN_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEDONE_DEFAULT (_IADC_IEN_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_POLARITYERR (0x1UL << 12) /**< Polarity Error Enable */ -#define _IADC_IEN_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ -#define _IADC_IEN_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ -#define _IADC_IEN_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_POLARITYERR_DEFAULT (_IADC_IEN_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error Enable */ -#define _IADC_IEN_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ -#define _IADC_IEN_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ -#define _IADC_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_PORTALLOCERR_DEFAULT (_IADC_IEN_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow Enable */ -#define _IADC_IEN_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ -#define _IADC_IEN_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ -#define _IADC_IEN_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFOOF_DEFAULT (_IADC_IEN_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow Enable */ -#define _IADC_IEN_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ -#define _IADC_IEN_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ -#define _IADC_IEN_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFOOF_DEFAULT (_IADC_IEN_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow Enable */ -#define _IADC_IEN_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ -#define _IADC_IEN_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ -#define _IADC_IEN_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFOUF_DEFAULT (_IADC_IEN_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow Enable */ -#define _IADC_IEN_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ -#define _IADC_IEN_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ -#define _IADC_IEN_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFOUF_DEFAULT (_IADC_IEN_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error Enable */ -#define _IADC_IEN_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ -#define _IADC_IEN_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ -#define _IADC_IEN_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_EM23ABORTERROR_DEFAULT (_IADC_IEN_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IEN */ +#define _IADC_IEN_RESETVALUE 0x00000000UL /**< Default value for IADC_IEN */ +#define _IADC_IEN_MASK 0x800F338FUL /**< Mask for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level Enable */ +#define _IADC_IEN_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL_DEFAULT (_IADC_IEN_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level Enable */ +#define _IADC_IEN_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL_DEFAULT (_IADC_IEN_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare Enable */ +#define _IADC_IEN_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP_DEFAULT (_IADC_IEN_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare Enable */ +#define _IADC_IEN_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP_DEFAULT (_IADC_IEN_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done Enable */ +#define _IADC_IEN_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE_DEFAULT (_IADC_IEN_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done Enable */ +#define _IADC_IEN_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE_DEFAULT (_IADC_IEN_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done Enable */ +#define _IADC_IEN_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE_DEFAULT (_IADC_IEN_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR (0x1UL << 12) /**< Polarity Error Enable */ +#define _IADC_IEN_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR_DEFAULT (_IADC_IEN_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error Enable */ +#define _IADC_IEN_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR_DEFAULT (_IADC_IEN_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow Enable */ +#define _IADC_IEN_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF_DEFAULT (_IADC_IEN_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow Enable */ +#define _IADC_IEN_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF_DEFAULT (_IADC_IEN_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow Enable */ +#define _IADC_IEN_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF_DEFAULT (_IADC_IEN_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow Enable */ +#define _IADC_IEN_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF_DEFAULT (_IADC_IEN_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error Enable */ +#define _IADC_IEN_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR_DEFAULT (_IADC_IEN_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IEN */ /* Bit fields for IADC TRIGGER */ -#define _IADC_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for IADC_TRIGGER */ -#define _IADC_TRIGGER_MASK 0x00011717UL /**< Mask for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_SHIFT 0 /**< Shift value for IADC_SCANTRIGSEL */ -#define _IADC_TRIGGER_SCANTRIGSEL_MASK 0x7UL /**< Bit mask for IADC_SCANTRIGSEL */ -#define _IADC_TRIGGER_SCANTRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_LESENSE 0x00000005UL /**< Mode LESENSE for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_DEFAULT (_IADC_TRIGGER_SCANTRIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE (_IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE << 0) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_TIMER (_IADC_TRIGGER_SCANTRIGSEL_TIMER << 0) /**< Shifted mode TIMER for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP << 0) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_PRSPOS (_IADC_TRIGGER_SCANTRIGSEL_PRSPOS << 0) /**< Shifted mode PRSPOS for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_PRSNEG (_IADC_TRIGGER_SCANTRIGSEL_PRSNEG << 0) /**< Shifted mode PRSNEG for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_LESENSE (_IADC_TRIGGER_SCANTRIGSEL_LESENSE << 0) /**< Shifted mode LESENSE for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGACTION (0x1UL << 4) /**< Scan Trigger Action */ -#define _IADC_TRIGGER_SCANTRIGACTION_SHIFT 4 /**< Shift value for IADC_SCANTRIGACTION */ -#define _IADC_TRIGGER_SCANTRIGACTION_MASK 0x10UL /**< Bit mask for IADC_SCANTRIGACTION */ -#define _IADC_TRIGGER_SCANTRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGACTION_DEFAULT (_IADC_TRIGGER_SCANTRIGACTION_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGACTION_ONCE (_IADC_TRIGGER_SCANTRIGACTION_ONCE << 4) /**< Shifted mode ONCE for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS (_IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS << 4) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_SHIFT 8 /**< Shift value for IADC_SINGLETRIGSEL */ -#define _IADC_TRIGGER_SINGLETRIGSEL_MASK 0x700UL /**< Bit mask for IADC_SINGLETRIGSEL */ -#define _IADC_TRIGGER_SINGLETRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_DEFAULT (_IADC_TRIGGER_SINGLETRIGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE (_IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE << 8) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_TIMER (_IADC_TRIGGER_SINGLETRIGSEL_TIMER << 8) /**< Shifted mode TIMER for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP << 8) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_PRSPOS (_IADC_TRIGGER_SINGLETRIGSEL_PRSPOS << 8) /**< Shifted mode PRSPOS for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_PRSNEG (_IADC_TRIGGER_SINGLETRIGSEL_PRSNEG << 8) /**< Shifted mode PRSNEG for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGACTION (0x1UL << 12) /**< Single Trigger Action */ -#define _IADC_TRIGGER_SINGLETRIGACTION_SHIFT 12 /**< Shift value for IADC_SINGLETRIGACTION */ -#define _IADC_TRIGGER_SINGLETRIGACTION_MASK 0x1000UL /**< Bit mask for IADC_SINGLETRIGACTION */ -#define _IADC_TRIGGER_SINGLETRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGACTION_DEFAULT (_IADC_TRIGGER_SINGLETRIGACTION_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGACTION_ONCE (_IADC_TRIGGER_SINGLETRIGACTION_ONCE << 12) /**< Shifted mode ONCE for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS (_IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS << 12) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETAILGATE (0x1UL << 16) /**< Single Tailgate Enable */ -#define _IADC_TRIGGER_SINGLETAILGATE_SHIFT 16 /**< Shift value for IADC_SINGLETAILGATE */ -#define _IADC_TRIGGER_SINGLETAILGATE_MASK 0x10000UL /**< Bit mask for IADC_SINGLETAILGATE */ -#define _IADC_TRIGGER_SINGLETAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF 0x00000000UL /**< Mode TAILGATEOFF for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEON 0x00000001UL /**< Mode TAILGATEON for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETAILGATE_DEFAULT (_IADC_TRIGGER_SINGLETAILGATE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF << 16) /**< Shifted mode TAILGATEOFF for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEON (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEON << 16) /**< Shifted mode TAILGATEON for IADC_TRIGGER */ +#define _IADC_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for IADC_TRIGGER */ +#define _IADC_TRIGGER_MASK 0x00011717UL /**< Mask for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_SHIFT 0 /**< Shift value for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_MASK 0x7UL /**< Bit mask for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_LESENSE 0x00000005UL /**< Mode LESENSE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_DEFAULT (_IADC_TRIGGER_SCANTRIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE (_IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE << 0) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_TIMER (_IADC_TRIGGER_SCANTRIGSEL_TIMER << 0) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP << 0) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSPOS (_IADC_TRIGGER_SCANTRIGSEL_PRSPOS << 0) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSNEG (_IADC_TRIGGER_SCANTRIGSEL_PRSNEG << 0) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_LESENSE (_IADC_TRIGGER_SCANTRIGSEL_LESENSE << 0) /**< Shifted mode LESENSE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION (0x1UL << 4) /**< Scan Trigger Action */ +#define _IADC_TRIGGER_SCANTRIGACTION_SHIFT 4 /**< Shift value for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_MASK 0x10UL /**< Bit mask for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_DEFAULT (_IADC_TRIGGER_SCANTRIGACTION_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_ONCE (_IADC_TRIGGER_SCANTRIGACTION_ONCE << 4) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS (_IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS << 4) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_SHIFT 8 /**< Shift value for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_MASK 0x700UL /**< Bit mask for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_DEFAULT (_IADC_TRIGGER_SINGLETRIGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE (_IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE << 8) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_TIMER (_IADC_TRIGGER_SINGLETRIGSEL_TIMER << 8) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP << 8) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSPOS (_IADC_TRIGGER_SINGLETRIGSEL_PRSPOS << 8) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSNEG (_IADC_TRIGGER_SINGLETRIGSEL_PRSNEG << 8) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION (0x1UL << 12) /**< Single Trigger Action */ +#define _IADC_TRIGGER_SINGLETRIGACTION_SHIFT 12 /**< Shift value for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_MASK 0x1000UL /**< Bit mask for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_DEFAULT (_IADC_TRIGGER_SINGLETRIGACTION_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_ONCE (_IADC_TRIGGER_SINGLETRIGACTION_ONCE << 12) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS (_IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS << 12) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE (0x1UL << 16) /**< Single Tailgate Enable */ +#define _IADC_TRIGGER_SINGLETAILGATE_SHIFT 16 /**< Shift value for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_MASK 0x10000UL /**< Bit mask for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF 0x00000000UL /**< Mode TAILGATEOFF for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEON 0x00000001UL /**< Mode TAILGATEON for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_DEFAULT (_IADC_TRIGGER_SINGLETAILGATE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF << 16) /**< Shifted mode TAILGATEOFF for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEON (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEON << 16) /**< Shifted mode TAILGATEON for IADC_TRIGGER */ /* Bit fields for IADC CFG */ -#define _IADC_CFG_RESETVALUE 0x00002060UL /**< Default value for IADC_CFG */ -#define _IADC_CFG_MASK 0x30E770FFUL /**< Mask for IADC_CFG */ -#define _IADC_CFG_ADCMODE_SHIFT 0 /**< Shift value for IADC_ADCMODE */ -#define _IADC_CFG_ADCMODE_MASK 0x3UL /**< Bit mask for IADC_ADCMODE */ -#define _IADC_CFG_ADCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_ADCMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CFG */ -#define IADC_CFG_ADCMODE_DEFAULT (_IADC_CFG_ADCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_ADCMODE_NORMAL (_IADC_CFG_ADCMODE_NORMAL << 0) /**< Shifted mode NORMAL for IADC_CFG */ -#define _IADC_CFG_OSRHS_SHIFT 2 /**< Shift value for IADC_OSRHS */ -#define _IADC_CFG_OSRHS_MASK 0x1CUL /**< Bit mask for IADC_OSRHS */ -#define _IADC_CFG_OSRHS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD2 0x00000000UL /**< Mode HISPD2 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD4 0x00000001UL /**< Mode HISPD4 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD8 0x00000002UL /**< Mode HISPD8 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD16 0x00000003UL /**< Mode HISPD16 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD32 0x00000004UL /**< Mode HISPD32 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD64 0x00000005UL /**< Mode HISPD64 for IADC_CFG */ -#define IADC_CFG_OSRHS_DEFAULT (_IADC_CFG_OSRHS_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD2 (_IADC_CFG_OSRHS_HISPD2 << 2) /**< Shifted mode HISPD2 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD4 (_IADC_CFG_OSRHS_HISPD4 << 2) /**< Shifted mode HISPD4 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD8 (_IADC_CFG_OSRHS_HISPD8 << 2) /**< Shifted mode HISPD8 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD16 (_IADC_CFG_OSRHS_HISPD16 << 2) /**< Shifted mode HISPD16 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD32 (_IADC_CFG_OSRHS_HISPD32 << 2) /**< Shifted mode HISPD32 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD64 (_IADC_CFG_OSRHS_HISPD64 << 2) /**< Shifted mode HISPD64 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_SHIFT 12 /**< Shift value for IADC_ANALOGGAIN */ -#define _IADC_CFG_ANALOGGAIN_MASK 0x7000UL /**< Bit mask for IADC_ANALOGGAIN */ -#define _IADC_CFG_ANALOGGAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN0P5 0x00000001UL /**< Mode ANAGAIN0P5 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN1 0x00000002UL /**< Mode ANAGAIN1 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN2 0x00000003UL /**< Mode ANAGAIN2 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN3 0x00000004UL /**< Mode ANAGAIN3 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN4 0x00000005UL /**< Mode ANAGAIN4 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_DEFAULT (_IADC_CFG_ANALOGGAIN_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN0P5 (_IADC_CFG_ANALOGGAIN_ANAGAIN0P5 << 12) /**< Shifted mode ANAGAIN0P5 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN1 (_IADC_CFG_ANALOGGAIN_ANAGAIN1 << 12) /**< Shifted mode ANAGAIN1 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN2 (_IADC_CFG_ANALOGGAIN_ANAGAIN2 << 12) /**< Shifted mode ANAGAIN2 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN3 (_IADC_CFG_ANALOGGAIN_ANAGAIN3 << 12) /**< Shifted mode ANAGAIN3 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN4 (_IADC_CFG_ANALOGGAIN_ANAGAIN4 << 12) /**< Shifted mode ANAGAIN4 for IADC_CFG */ -#define _IADC_CFG_REFSEL_SHIFT 16 /**< Shift value for IADC_REFSEL */ -#define _IADC_CFG_REFSEL_MASK 0x70000UL /**< Bit mask for IADC_REFSEL */ -#define _IADC_CFG_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_REFSEL_VBGR 0x00000000UL /**< Mode VBGR for IADC_CFG */ -#define _IADC_CFG_REFSEL_VREF 0x00000001UL /**< Mode VREF for IADC_CFG */ -#define _IADC_CFG_REFSEL_VDDX 0x00000003UL /**< Mode VDDX for IADC_CFG */ -#define _IADC_CFG_REFSEL_VDDX0P8BUF 0x00000004UL /**< Mode VDDX0P8BUF for IADC_CFG */ -#define IADC_CFG_REFSEL_DEFAULT (_IADC_CFG_REFSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_REFSEL_VBGR (_IADC_CFG_REFSEL_VBGR << 16) /**< Shifted mode VBGR for IADC_CFG */ -#define IADC_CFG_REFSEL_VREF (_IADC_CFG_REFSEL_VREF << 16) /**< Shifted mode VREF for IADC_CFG */ -#define IADC_CFG_REFSEL_VDDX (_IADC_CFG_REFSEL_VDDX << 16) /**< Shifted mode VDDX for IADC_CFG */ -#define IADC_CFG_REFSEL_VDDX0P8BUF (_IADC_CFG_REFSEL_VDDX0P8BUF << 16) /**< Shifted mode VDDX0P8BUF for IADC_CFG */ -#define _IADC_CFG_DIGAVG_SHIFT 21 /**< Shift value for IADC_DIGAVG */ -#define _IADC_CFG_DIGAVG_MASK 0xE00000UL /**< Bit mask for IADC_DIGAVG */ -#define _IADC_CFG_DIGAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG1 0x00000000UL /**< Mode AVG1 for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG2 0x00000001UL /**< Mode AVG2 for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG4 0x00000002UL /**< Mode AVG4 for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG8 0x00000003UL /**< Mode AVG8 for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG16 0x00000004UL /**< Mode AVG16 for IADC_CFG */ -#define IADC_CFG_DIGAVG_DEFAULT (_IADC_CFG_DIGAVG_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG1 (_IADC_CFG_DIGAVG_AVG1 << 21) /**< Shifted mode AVG1 for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG2 (_IADC_CFG_DIGAVG_AVG2 << 21) /**< Shifted mode AVG2 for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG4 (_IADC_CFG_DIGAVG_AVG4 << 21) /**< Shifted mode AVG4 for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG8 (_IADC_CFG_DIGAVG_AVG8 << 21) /**< Shifted mode AVG8 for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG16 (_IADC_CFG_DIGAVG_AVG16 << 21) /**< Shifted mode AVG16 for IADC_CFG */ -#define _IADC_CFG_TWOSCOMPL_SHIFT 28 /**< Shift value for IADC_TWOSCOMPL */ -#define _IADC_CFG_TWOSCOMPL_MASK 0x30000000UL /**< Bit mask for IADC_TWOSCOMPL */ -#define _IADC_CFG_TWOSCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_TWOSCOMPL_AUTO 0x00000000UL /**< Mode AUTO for IADC_CFG */ -#define _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR 0x00000001UL /**< Mode FORCEUNIPOLAR for IADC_CFG */ -#define _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR 0x00000002UL /**< Mode FORCEBIPOLAR for IADC_CFG */ -#define IADC_CFG_TWOSCOMPL_DEFAULT (_IADC_CFG_TWOSCOMPL_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_TWOSCOMPL_AUTO (_IADC_CFG_TWOSCOMPL_AUTO << 28) /**< Shifted mode AUTO for IADC_CFG */ -#define IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR << 28) /**< Shifted mode FORCEUNIPOLAR for IADC_CFG */ -#define IADC_CFG_TWOSCOMPL_FORCEBIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEBIPOLAR << 28) /**< Shifted mode FORCEBIPOLAR for IADC_CFG */ +#define _IADC_CFG_RESETVALUE 0x00002060UL /**< Default value for IADC_CFG */ +#define _IADC_CFG_MASK 0x30E770FFUL /**< Mask for IADC_CFG */ +#define _IADC_CFG_ADCMODE_SHIFT 0 /**< Shift value for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_MASK 0x3UL /**< Bit mask for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ADCMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CFG */ +#define IADC_CFG_ADCMODE_DEFAULT (_IADC_CFG_ADCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ADCMODE_NORMAL (_IADC_CFG_ADCMODE_NORMAL << 0) /**< Shifted mode NORMAL for IADC_CFG */ +#define _IADC_CFG_OSRHS_SHIFT 2 /**< Shift value for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_MASK 0x1CUL /**< Bit mask for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD2 0x00000000UL /**< Mode HISPD2 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD4 0x00000001UL /**< Mode HISPD4 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD8 0x00000002UL /**< Mode HISPD8 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD16 0x00000003UL /**< Mode HISPD16 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD32 0x00000004UL /**< Mode HISPD32 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD64 0x00000005UL /**< Mode HISPD64 for IADC_CFG */ +#define IADC_CFG_OSRHS_DEFAULT (_IADC_CFG_OSRHS_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD2 (_IADC_CFG_OSRHS_HISPD2 << 2) /**< Shifted mode HISPD2 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD4 (_IADC_CFG_OSRHS_HISPD4 << 2) /**< Shifted mode HISPD4 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD8 (_IADC_CFG_OSRHS_HISPD8 << 2) /**< Shifted mode HISPD8 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD16 (_IADC_CFG_OSRHS_HISPD16 << 2) /**< Shifted mode HISPD16 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD32 (_IADC_CFG_OSRHS_HISPD32 << 2) /**< Shifted mode HISPD32 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD64 (_IADC_CFG_OSRHS_HISPD64 << 2) /**< Shifted mode HISPD64 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_SHIFT 12 /**< Shift value for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_MASK 0x7000UL /**< Bit mask for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN0P5 0x00000001UL /**< Mode ANAGAIN0P5 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN1 0x00000002UL /**< Mode ANAGAIN1 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN2 0x00000003UL /**< Mode ANAGAIN2 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN3 0x00000004UL /**< Mode ANAGAIN3 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN4 0x00000005UL /**< Mode ANAGAIN4 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_DEFAULT (_IADC_CFG_ANALOGGAIN_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN0P5 (_IADC_CFG_ANALOGGAIN_ANAGAIN0P5 << 12) /**< Shifted mode ANAGAIN0P5 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN1 (_IADC_CFG_ANALOGGAIN_ANAGAIN1 << 12) /**< Shifted mode ANAGAIN1 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN2 (_IADC_CFG_ANALOGGAIN_ANAGAIN2 << 12) /**< Shifted mode ANAGAIN2 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN3 (_IADC_CFG_ANALOGGAIN_ANAGAIN3 << 12) /**< Shifted mode ANAGAIN3 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN4 (_IADC_CFG_ANALOGGAIN_ANAGAIN4 << 12) /**< Shifted mode ANAGAIN4 for IADC_CFG */ +#define _IADC_CFG_REFSEL_SHIFT 16 /**< Shift value for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_MASK 0x70000UL /**< Bit mask for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_REFSEL_VBGR 0x00000000UL /**< Mode VBGR for IADC_CFG */ +#define _IADC_CFG_REFSEL_VREF 0x00000001UL /**< Mode VREF for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX 0x00000003UL /**< Mode VDDX for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX0P8BUF 0x00000004UL /**< Mode VDDX0P8BUF for IADC_CFG */ +#define IADC_CFG_REFSEL_DEFAULT (_IADC_CFG_REFSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_REFSEL_VBGR (_IADC_CFG_REFSEL_VBGR << 16) /**< Shifted mode VBGR for IADC_CFG */ +#define IADC_CFG_REFSEL_VREF (_IADC_CFG_REFSEL_VREF << 16) /**< Shifted mode VREF for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX (_IADC_CFG_REFSEL_VDDX << 16) /**< Shifted mode VDDX for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX0P8BUF (_IADC_CFG_REFSEL_VDDX0P8BUF << 16) /**< Shifted mode VDDX0P8BUF for IADC_CFG */ +#define _IADC_CFG_DIGAVG_SHIFT 21 /**< Shift value for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_MASK 0xE00000UL /**< Bit mask for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG1 0x00000000UL /**< Mode AVG1 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG2 0x00000001UL /**< Mode AVG2 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG4 0x00000002UL /**< Mode AVG4 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG8 0x00000003UL /**< Mode AVG8 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG16 0x00000004UL /**< Mode AVG16 for IADC_CFG */ +#define IADC_CFG_DIGAVG_DEFAULT (_IADC_CFG_DIGAVG_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG1 (_IADC_CFG_DIGAVG_AVG1 << 21) /**< Shifted mode AVG1 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG2 (_IADC_CFG_DIGAVG_AVG2 << 21) /**< Shifted mode AVG2 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG4 (_IADC_CFG_DIGAVG_AVG4 << 21) /**< Shifted mode AVG4 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG8 (_IADC_CFG_DIGAVG_AVG8 << 21) /**< Shifted mode AVG8 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG16 (_IADC_CFG_DIGAVG_AVG16 << 21) /**< Shifted mode AVG16 for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_SHIFT 28 /**< Shift value for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_MASK 0x30000000UL /**< Bit mask for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_AUTO 0x00000000UL /**< Mode AUTO for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR 0x00000001UL /**< Mode FORCEUNIPOLAR for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR 0x00000002UL /**< Mode FORCEBIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_DEFAULT (_IADC_CFG_TWOSCOMPL_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_AUTO (_IADC_CFG_TWOSCOMPL_AUTO << 28) /**< Shifted mode AUTO for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR << 28) /**< Shifted mode FORCEUNIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEBIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEBIPOLAR << 28) /**< Shifted mode FORCEBIPOLAR for IADC_CFG */ /* Bit fields for IADC SCALE */ -#define _IADC_SCALE_RESETVALUE 0x8002C000UL /**< Default value for IADC_SCALE */ -#define _IADC_SCALE_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCALE */ -#define _IADC_SCALE_OFFSET_SHIFT 0 /**< Shift value for IADC_OFFSET */ -#define _IADC_SCALE_OFFSET_MASK 0x3FFFFUL /**< Bit mask for IADC_OFFSET */ -#define _IADC_SCALE_OFFSET_DEFAULT 0x0002C000UL /**< Mode DEFAULT for IADC_SCALE */ -#define IADC_SCALE_OFFSET_DEFAULT (_IADC_SCALE_OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCALE */ -#define _IADC_SCALE_GAIN13LSB_SHIFT 18 /**< Shift value for IADC_GAIN13LSB */ -#define _IADC_SCALE_GAIN13LSB_MASK 0x7FFC0000UL /**< Bit mask for IADC_GAIN13LSB */ -#define _IADC_SCALE_GAIN13LSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCALE */ -#define IADC_SCALE_GAIN13LSB_DEFAULT (_IADC_SCALE_GAIN13LSB_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_SCALE */ -#define IADC_SCALE_GAIN3MSB (0x1UL << 31) /**< Gain 3 MSBs */ -#define _IADC_SCALE_GAIN3MSB_SHIFT 31 /**< Shift value for IADC_GAIN3MSB */ -#define _IADC_SCALE_GAIN3MSB_MASK 0x80000000UL /**< Bit mask for IADC_GAIN3MSB */ -#define _IADC_SCALE_GAIN3MSB_DEFAULT 0x00000001UL /**< Mode DEFAULT for IADC_SCALE */ -#define _IADC_SCALE_GAIN3MSB_GAIN011 0x00000000UL /**< Mode GAIN011 for IADC_SCALE */ -#define _IADC_SCALE_GAIN3MSB_GAIN100 0x00000001UL /**< Mode GAIN100 for IADC_SCALE */ -#define IADC_SCALE_GAIN3MSB_DEFAULT (_IADC_SCALE_GAIN3MSB_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_SCALE */ -#define IADC_SCALE_GAIN3MSB_GAIN011 (_IADC_SCALE_GAIN3MSB_GAIN011 << 31) /**< Shifted mode GAIN011 for IADC_SCALE */ -#define IADC_SCALE_GAIN3MSB_GAIN100 (_IADC_SCALE_GAIN3MSB_GAIN100 << 31) /**< Shifted mode GAIN100 for IADC_SCALE */ +#define _IADC_SCALE_RESETVALUE 0x8002C000UL /**< Default value for IADC_SCALE */ +#define _IADC_SCALE_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCALE */ +#define _IADC_SCALE_OFFSET_SHIFT 0 /**< Shift value for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_MASK 0x3FFFFUL /**< Bit mask for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_DEFAULT 0x0002C000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_OFFSET_DEFAULT (_IADC_SCALE_OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN13LSB_SHIFT 18 /**< Shift value for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_MASK 0x7FFC0000UL /**< Bit mask for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN13LSB_DEFAULT (_IADC_SCALE_GAIN13LSB_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB (0x1UL << 31) /**< Gain 3 MSBs */ +#define _IADC_SCALE_GAIN3MSB_SHIFT 31 /**< Shift value for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_MASK 0x80000000UL /**< Bit mask for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_DEFAULT 0x00000001UL /**< Mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN011 0x00000000UL /**< Mode GAIN011 for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN100 0x00000001UL /**< Mode GAIN100 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_DEFAULT (_IADC_SCALE_GAIN3MSB_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN011 (_IADC_SCALE_GAIN3MSB_GAIN011 << 31) /**< Shifted mode GAIN011 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN100 (_IADC_SCALE_GAIN3MSB_GAIN100 << 31) /**< Shifted mode GAIN100 for IADC_SCALE */ /* Bit fields for IADC SCHED */ -#define _IADC_SCHED_RESETVALUE 0x00000000UL /**< Default value for IADC_SCHED */ -#define _IADC_SCHED_MASK 0x000003FFUL /**< Mask for IADC_SCHED */ -#define _IADC_SCHED_PRESCALE_SHIFT 0 /**< Shift value for IADC_PRESCALE */ -#define _IADC_SCHED_PRESCALE_MASK 0x3FFUL /**< Bit mask for IADC_PRESCALE */ -#define _IADC_SCHED_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCHED */ -#define IADC_SCHED_PRESCALE_DEFAULT (_IADC_SCHED_PRESCALE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCHED */ +#define _IADC_SCHED_RESETVALUE 0x00000000UL /**< Default value for IADC_SCHED */ +#define _IADC_SCHED_MASK 0x000003FFUL /**< Mask for IADC_SCHED */ +#define _IADC_SCHED_PRESCALE_SHIFT 0 /**< Shift value for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_MASK 0x3FFUL /**< Bit mask for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCHED */ +#define IADC_SCHED_PRESCALE_DEFAULT (_IADC_SCHED_PRESCALE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCHED */ /* Bit fields for IADC SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ -#define _IADC_SINGLEFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ -#define _IADC_SINGLEFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ -#define _IADC_SINGLEFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_SHOWID_DEFAULT (_IADC_SINGLEFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ -#define _IADC_SINGLEFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ -#define _IADC_SINGLEFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_DEFAULT (_IADC_SINGLEFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID1 (_IADC_SINGLEFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID2 (_IADC_SINGLEFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID3 (_IADC_SINGLEFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID4 (_IADC_SINGLEFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID5 (_IADC_SINGLEFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID6 (_IADC_SINGLEFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID7 (_IADC_SINGLEFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID8 (_IADC_SINGLEFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE (0x1UL << 8) /**< Single FIFO DMA wakeup. */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSINGLE */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSINGLE */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SINGLEFIFOCFG*/ -#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID_DEFAULT (_IADC_SINGLEFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_DEFAULT (_IADC_SINGLEFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID1 (_IADC_SINGLEFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID2 (_IADC_SINGLEFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID3 (_IADC_SINGLEFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID4 (_IADC_SINGLEFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID5 (_IADC_SINGLEFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID6 (_IADC_SINGLEFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID7 (_IADC_SINGLEFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID8 (_IADC_SINGLEFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE (0x1UL << 8) /**< Single FIFO DMA wakeup. */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SINGLEFIFOCFG*/ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SINGLEFIFOCFG */ /* Bit fields for IADC SINGLEFIFODATA */ -#define _IADC_SINGLEFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFODATA */ -#define _IADC_SINGLEFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEFIFODATA */ -#define _IADC_SINGLEFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ -#define _IADC_SINGLEFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ -#define _IADC_SINGLEFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFODATA */ -#define IADC_SINGLEFIFODATA_DATA_DEFAULT (_IADC_SINGLEFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFODATA*/ +#define _IADC_SINGLEFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFODATA */ +#define IADC_SINGLEFIFODATA_DATA_DEFAULT (_IADC_SINGLEFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFODATA*/ /* Bit fields for IADC SINGLEFIFOSTAT */ -#define _IADC_SINGLEFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFOSTAT */ -#define _IADC_SINGLEFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SINGLEFIFOSTAT */ -#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ -#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ -#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOSTAT */ -#define IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOSTAT*/ +#define _IADC_SINGLEFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOSTAT */ +#define IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOSTAT*/ /* Bit fields for IADC SINGLEDATA */ -#define _IADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEDATA */ -#define _IADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEDATA */ -#define _IADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ -#define _IADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ -#define _IADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEDATA */ -#define IADC_SINGLEDATA_DATA_DEFAULT (_IADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEDATA */ +#define IADC_SINGLEDATA_DATA_DEFAULT (_IADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEDATA */ /* Bit fields for IADC SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ -#define _IADC_SCANFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ -#define _IADC_SCANFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ -#define _IADC_SCANFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_SHOWID_DEFAULT (_IADC_SCANFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ -#define _IADC_SCANFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ -#define _IADC_SCANFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_DEFAULT (_IADC_SCANFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID1 (_IADC_SCANFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID2 (_IADC_SCANFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID3 (_IADC_SCANFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID4 (_IADC_SCANFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID5 (_IADC_SCANFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID6 (_IADC_SCANFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID7 (_IADC_SCANFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID8 (_IADC_SCANFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN (0x1UL << 8) /**< Scan FIFO DMA Wakeup */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSCAN */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSCAN */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SCANFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID_DEFAULT (_IADC_SCANFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_DEFAULT (_IADC_SCANFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID1 (_IADC_SCANFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID2 (_IADC_SCANFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID3 (_IADC_SCANFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID4 (_IADC_SCANFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID5 (_IADC_SCANFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID6 (_IADC_SCANFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID7 (_IADC_SCANFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID8 (_IADC_SCANFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN (0x1UL << 8) /**< Scan FIFO DMA Wakeup */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SCANFIFOCFG */ /* Bit fields for IADC SCANFIFODATA */ -#define _IADC_SCANFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFODATA */ -#define _IADC_SCANFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANFIFODATA */ -#define _IADC_SCANFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ -#define _IADC_SCANFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ -#define _IADC_SCANFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFODATA */ -#define IADC_SCANFIFODATA_DATA_DEFAULT (_IADC_SCANFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFODATA */ +#define IADC_SCANFIFODATA_DATA_DEFAULT (_IADC_SCANFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFODATA */ /* Bit fields for IADC SCANFIFOSTAT */ -#define _IADC_SCANFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFOSTAT */ -#define _IADC_SCANFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SCANFIFOSTAT */ -#define _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ -#define _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ -#define _IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOSTAT */ -#define IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOSTAT */ +#define IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOSTAT */ /* Bit fields for IADC SCANDATA */ -#define _IADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANDATA */ -#define _IADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANDATA */ -#define _IADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ -#define _IADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ -#define _IADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANDATA */ -#define IADC_SCANDATA_DATA_DEFAULT (_IADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANDATA */ +#define _IADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANDATA */ +#define _IADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANDATA */ +#define _IADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANDATA */ +#define IADC_SCANDATA_DATA_DEFAULT (_IADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANDATA */ /* Bit fields for IADC SINGLE */ -#define _IADC_SINGLE_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLE */ -#define _IADC_SINGLE_MASK 0x0003FFFFUL /**< Mask for IADC_SINGLE */ -#define _IADC_SINGLE_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ -#define _IADC_SINGLE_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ -#define _IADC_SINGLE_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_PINNEG_DEFAULT (_IADC_SINGLE_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ -#define _IADC_SINGLE_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ -#define _IADC_SINGLE_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_DEFAULT (_IADC_SINGLE_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_GND (_IADC_SINGLE_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_DAC1 (_IADC_SINGLE_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PORTA (_IADC_SINGLE_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PORTB (_IADC_SINGLE_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PORTC (_IADC_SINGLE_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PORTD (_IADC_SINGLE_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SINGLE */ -#define _IADC_SINGLE_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ -#define _IADC_SINGLE_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ -#define _IADC_SINGLE_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_PINPOS_DEFAULT (_IADC_SINGLE_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ -#define _IADC_SINGLE_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ -#define _IADC_SINGLE_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_DEFAULT (_IADC_SINGLE_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_GND (_IADC_SINGLE_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_SUPPLY (_IADC_SINGLE_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_DAC0 (_IADC_SINGLE_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PORTA (_IADC_SINGLE_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PORTB (_IADC_SINGLE_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PORTC (_IADC_SINGLE_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PORTD (_IADC_SINGLE_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SINGLE */ -#define IADC_SINGLE_CFG (0x1UL << 16) /**< Configuration Group Select */ -#define _IADC_SINGLE_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ -#define _IADC_SINGLE_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ -#define _IADC_SINGLE_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SINGLE */ -#define _IADC_SINGLE_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SINGLE */ -#define IADC_SINGLE_CFG_DEFAULT (_IADC_SINGLE_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_CFG_CONFIG0 (_IADC_SINGLE_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SINGLE */ -#define IADC_SINGLE_CFG_CONFIG1 (_IADC_SINGLE_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SINGLE */ -#define IADC_SINGLE_CMP (0x1UL << 17) /**< Comparison Enable */ -#define _IADC_SINGLE_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ -#define _IADC_SINGLE_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ -#define _IADC_SINGLE_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_CMP_DEFAULT (_IADC_SINGLE_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLE */ +#define _IADC_SINGLE_MASK 0x0003FFFFUL /**< Mask for IADC_SINGLE */ +#define _IADC_SINGLE_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINNEG_DEFAULT (_IADC_SINGLE_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_DEFAULT (_IADC_SINGLE_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_GND (_IADC_SINGLE_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_DAC1 (_IADC_SINGLE_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTA (_IADC_SINGLE_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTB (_IADC_SINGLE_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTC (_IADC_SINGLE_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTD (_IADC_SINGLE_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SINGLE */ +#define _IADC_SINGLE_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINPOS_DEFAULT (_IADC_SINGLE_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_DEFAULT (_IADC_SINGLE_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_GND (_IADC_SINGLE_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_SUPPLY (_IADC_SINGLE_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_DAC0 (_IADC_SINGLE_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTA (_IADC_SINGLE_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTB (_IADC_SINGLE_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTC (_IADC_SINGLE_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTD (_IADC_SINGLE_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SINGLE_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SINGLE_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SINGLE_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_DEFAULT (_IADC_SINGLE_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG0 (_IADC_SINGLE_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG1 (_IADC_SINGLE_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SINGLE_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SINGLE_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SINGLE_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CMP_DEFAULT (_IADC_SINGLE_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SINGLE */ /* Bit fields for IADC SCAN */ -#define _IADC_SCAN_RESETVALUE 0x00000000UL /**< Default value for IADC_SCAN */ -#define _IADC_SCAN_MASK 0x0003FFFFUL /**< Mask for IADC_SCAN */ -#define _IADC_SCAN_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ -#define _IADC_SCAN_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ -#define _IADC_SCAN_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_PINNEG_DEFAULT (_IADC_SCAN_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ -#define _IADC_SCAN_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ -#define _IADC_SCAN_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_DEFAULT (_IADC_SCAN_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_GND (_IADC_SCAN_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_DAC1 (_IADC_SCAN_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PORTA (_IADC_SCAN_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PORTB (_IADC_SCAN_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PORTC (_IADC_SCAN_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PORTD (_IADC_SCAN_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SCAN */ -#define _IADC_SCAN_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ -#define _IADC_SCAN_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ -#define _IADC_SCAN_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_PINPOS_DEFAULT (_IADC_SCAN_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ -#define _IADC_SCAN_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ -#define _IADC_SCAN_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_DEFAULT (_IADC_SCAN_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_GND (_IADC_SCAN_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_SUPPLY (_IADC_SCAN_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_DAC0 (_IADC_SCAN_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PORTA (_IADC_SCAN_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PORTB (_IADC_SCAN_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PORTC (_IADC_SCAN_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PORTD (_IADC_SCAN_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SCAN */ -#define IADC_SCAN_CFG (0x1UL << 16) /**< Configuration Group Select */ -#define _IADC_SCAN_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ -#define _IADC_SCAN_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ -#define _IADC_SCAN_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SCAN */ -#define _IADC_SCAN_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SCAN */ -#define IADC_SCAN_CFG_DEFAULT (_IADC_SCAN_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_CFG_CONFIG0 (_IADC_SCAN_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SCAN */ -#define IADC_SCAN_CFG_CONFIG1 (_IADC_SCAN_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SCAN */ -#define IADC_SCAN_CMP (0x1UL << 17) /**< Comparison Enable */ -#define _IADC_SCAN_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ -#define _IADC_SCAN_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ -#define _IADC_SCAN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_CMP_DEFAULT (_IADC_SCAN_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_RESETVALUE 0x00000000UL /**< Default value for IADC_SCAN */ +#define _IADC_SCAN_MASK 0x0003FFFFUL /**< Mask for IADC_SCAN */ +#define _IADC_SCAN_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINNEG_DEFAULT (_IADC_SCAN_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_DEFAULT (_IADC_SCAN_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_GND (_IADC_SCAN_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_DAC1 (_IADC_SCAN_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTA (_IADC_SCAN_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTB (_IADC_SCAN_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTC (_IADC_SCAN_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTD (_IADC_SCAN_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SCAN */ +#define _IADC_SCAN_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINPOS_DEFAULT (_IADC_SCAN_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_DEFAULT (_IADC_SCAN_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_GND (_IADC_SCAN_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_SUPPLY (_IADC_SCAN_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_DAC0 (_IADC_SCAN_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTA (_IADC_SCAN_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTB (_IADC_SCAN_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTC (_IADC_SCAN_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTD (_IADC_SCAN_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SCAN */ +#define IADC_SCAN_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SCAN_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SCAN_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SCAN_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CFG_DEFAULT (_IADC_SCAN_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG0 (_IADC_SCAN_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG1 (_IADC_SCAN_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SCAN_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SCAN_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SCAN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CMP_DEFAULT (_IADC_SCAN_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SCAN */ /** @} End of group EFR32SG23_IADC_BitFields */ /** @} End of group EFR32SG23_IADC */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_icache.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_icache.h index ba3022bf7c..bd08f1b99a 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_icache.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_icache.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_ICACHE_H #define EFR32SG23_ICACHE_H - #define ICACHE_HAS_SET_CLEAR /**************************************************************************//** @@ -43,51 +42,50 @@ *****************************************************************************/ /** ICACHE Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP Version */ - __IOM uint32_t CTRL; /**< Control Register */ - __IM uint32_t PCHITS; /**< Performance Counter Hits */ - __IM uint32_t PCMISSES; /**< Performance Counter Misses */ - __IM uint32_t PCAHITS; /**< Performance Counter Advanced Hits */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IOM uint32_t LPMODE; /**< Low Power Mode */ - __IOM uint32_t IF; /**< Interrupt Flag */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED0[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IM uint32_t PCHITS_SET; /**< Performance Counter Hits */ - __IM uint32_t PCMISSES_SET; /**< Performance Counter Misses */ - __IM uint32_t PCAHITS_SET; /**< Performance Counter Advanced Hits */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IOM uint32_t LPMODE_SET; /**< Low Power Mode */ - __IOM uint32_t IF_SET; /**< Interrupt Flag */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IM uint32_t PCHITS_CLR; /**< Performance Counter Hits */ - __IM uint32_t PCMISSES_CLR; /**< Performance Counter Misses */ - __IM uint32_t PCAHITS_CLR; /**< Performance Counter Advanced Hits */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IOM uint32_t LPMODE_CLR; /**< Low Power Mode */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - uint32_t RESERVED2[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IM uint32_t PCHITS_TGL; /**< Performance Counter Hits */ - __IM uint32_t PCMISSES_TGL; /**< Performance Counter Misses */ - __IM uint32_t PCAHITS_TGL; /**< Performance Counter Advanced Hits */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IOM uint32_t LPMODE_TGL; /**< Low Power Mode */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t PCHITS; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t LPMODE; /**< Low Power Mode */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED0[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IM uint32_t PCHITS_SET; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_SET; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_SET; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t LPMODE_SET; /**< Low Power Mode */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IM uint32_t PCHITS_CLR; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_CLR; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_CLR; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t LPMODE_CLR; /**< Low Power Mode */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED2[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IM uint32_t PCHITS_TGL; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_TGL; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_TGL; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t LPMODE_TGL; /**< Low Power Mode */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ } ICACHE_TypeDef; /** @} End of group EFR32SG23_ICACHE */ @@ -99,149 +97,149 @@ typedef struct *****************************************************************************/ /* Bit fields for ICACHE IPVERSION */ -#define _ICACHE_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IPVERSION */ -#define _ICACHE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_IPVERSION */ -#define _ICACHE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ICACHE_IPVERSION */ -#define _ICACHE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_IPVERSION */ -#define _ICACHE_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IPVERSION */ -#define ICACHE_IPVERSION_IPVERSION_DEFAULT (_ICACHE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IPVERSION */ +#define ICACHE_IPVERSION_IPVERSION_DEFAULT (_ICACHE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IPVERSION */ /* Bit fields for ICACHE CTRL */ -#define _ICACHE_CTRL_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CTRL */ -#define _ICACHE_CTRL_MASK 0x00000007UL /**< Mask for ICACHE_CTRL */ -#define ICACHE_CTRL_CACHEDIS (0x1UL << 0) /**< Cache Disable */ -#define _ICACHE_CTRL_CACHEDIS_SHIFT 0 /**< Shift value for ICACHE_CACHEDIS */ -#define _ICACHE_CTRL_CACHEDIS_MASK 0x1UL /**< Bit mask for ICACHE_CACHEDIS */ -#define _ICACHE_CTRL_CACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_CACHEDIS_DEFAULT (_ICACHE_CTRL_CACHEDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_USEMPU (0x1UL << 1) /**< Use MPU */ -#define _ICACHE_CTRL_USEMPU_SHIFT 1 /**< Shift value for ICACHE_USEMPU */ -#define _ICACHE_CTRL_USEMPU_MASK 0x2UL /**< Bit mask for ICACHE_USEMPU */ -#define _ICACHE_CTRL_USEMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_USEMPU_DEFAULT (_ICACHE_CTRL_USEMPU_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_AUTOFLUSHDIS (0x1UL << 2) /**< Automatic Flushing Disable */ -#define _ICACHE_CTRL_AUTOFLUSHDIS_SHIFT 2 /**< Shift value for ICACHE_AUTOFLUSHDIS */ -#define _ICACHE_CTRL_AUTOFLUSHDIS_MASK 0x4UL /**< Bit mask for ICACHE_AUTOFLUSHDIS */ -#define _ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT (_ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define _ICACHE_CTRL_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CTRL */ +#define _ICACHE_CTRL_MASK 0x00000007UL /**< Mask for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS (0x1UL << 0) /**< Cache Disable */ +#define _ICACHE_CTRL_CACHEDIS_SHIFT 0 /**< Shift value for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_MASK 0x1UL /**< Bit mask for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS_DEFAULT (_ICACHE_CTRL_CACHEDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU (0x1UL << 1) /**< Use MPU */ +#define _ICACHE_CTRL_USEMPU_SHIFT 1 /**< Shift value for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_MASK 0x2UL /**< Bit mask for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU_DEFAULT (_ICACHE_CTRL_USEMPU_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS (0x1UL << 2) /**< Automatic Flushing Disable */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_SHIFT 2 /**< Shift value for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_MASK 0x4UL /**< Bit mask for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT (_ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CTRL */ /* Bit fields for ICACHE PCHITS */ -#define _ICACHE_PCHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCHITS */ -#define _ICACHE_PCHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCHITS */ -#define _ICACHE_PCHITS_PCHITS_SHIFT 0 /**< Shift value for ICACHE_PCHITS */ -#define _ICACHE_PCHITS_PCHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCHITS */ -#define _ICACHE_PCHITS_PCHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCHITS */ -#define ICACHE_PCHITS_PCHITS_DEFAULT (_ICACHE_PCHITS_PCHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_SHIFT 0 /**< Shift value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCHITS */ +#define ICACHE_PCHITS_PCHITS_DEFAULT (_ICACHE_PCHITS_PCHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCHITS */ /* Bit fields for ICACHE PCMISSES */ -#define _ICACHE_PCMISSES_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCMISSES */ -#define _ICACHE_PCMISSES_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCMISSES */ -#define _ICACHE_PCMISSES_PCMISSES_SHIFT 0 /**< Shift value for ICACHE_PCMISSES */ -#define _ICACHE_PCMISSES_PCMISSES_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCMISSES */ -#define _ICACHE_PCMISSES_PCMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCMISSES */ -#define ICACHE_PCMISSES_PCMISSES_DEFAULT (_ICACHE_PCMISSES_PCMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_SHIFT 0 /**< Shift value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCMISSES */ +#define ICACHE_PCMISSES_PCMISSES_DEFAULT (_ICACHE_PCMISSES_PCMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCMISSES */ /* Bit fields for ICACHE PCAHITS */ -#define _ICACHE_PCAHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCAHITS */ -#define _ICACHE_PCAHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCAHITS */ -#define _ICACHE_PCAHITS_PCAHITS_SHIFT 0 /**< Shift value for ICACHE_PCAHITS */ -#define _ICACHE_PCAHITS_PCAHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCAHITS */ -#define _ICACHE_PCAHITS_PCAHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCAHITS */ -#define ICACHE_PCAHITS_PCAHITS_DEFAULT (_ICACHE_PCAHITS_PCAHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_SHIFT 0 /**< Shift value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCAHITS */ +#define ICACHE_PCAHITS_PCAHITS_DEFAULT (_ICACHE_PCAHITS_PCAHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCAHITS */ /* Bit fields for ICACHE STATUS */ -#define _ICACHE_STATUS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_STATUS */ -#define _ICACHE_STATUS_MASK 0x00000001UL /**< Mask for ICACHE_STATUS */ -#define ICACHE_STATUS_PCRUNNING (0x1UL << 0) /**< PC Running */ -#define _ICACHE_STATUS_PCRUNNING_SHIFT 0 /**< Shift value for ICACHE_PCRUNNING */ -#define _ICACHE_STATUS_PCRUNNING_MASK 0x1UL /**< Bit mask for ICACHE_PCRUNNING */ -#define _ICACHE_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_STATUS */ -#define ICACHE_STATUS_PCRUNNING_DEFAULT (_ICACHE_STATUS_PCRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_STATUS */ +#define _ICACHE_STATUS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_STATUS */ +#define _ICACHE_STATUS_MASK 0x00000001UL /**< Mask for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING (0x1UL << 0) /**< PC Running */ +#define _ICACHE_STATUS_PCRUNNING_SHIFT 0 /**< Shift value for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_MASK 0x1UL /**< Bit mask for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING_DEFAULT (_ICACHE_STATUS_PCRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_STATUS */ /* Bit fields for ICACHE CMD */ -#define _ICACHE_CMD_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CMD */ -#define _ICACHE_CMD_MASK 0x00000007UL /**< Mask for ICACHE_CMD */ -#define ICACHE_CMD_FLUSH (0x1UL << 0) /**< Flush */ -#define _ICACHE_CMD_FLUSH_SHIFT 0 /**< Shift value for ICACHE_FLUSH */ -#define _ICACHE_CMD_FLUSH_MASK 0x1UL /**< Bit mask for ICACHE_FLUSH */ -#define _ICACHE_CMD_FLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_FLUSH_DEFAULT (_ICACHE_CMD_FLUSH_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ -#define _ICACHE_CMD_STARTPC_SHIFT 1 /**< Shift value for ICACHE_STARTPC */ -#define _ICACHE_CMD_STARTPC_MASK 0x2UL /**< Bit mask for ICACHE_STARTPC */ -#define _ICACHE_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_STARTPC_DEFAULT (_ICACHE_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ -#define _ICACHE_CMD_STOPPC_SHIFT 2 /**< Shift value for ICACHE_STOPPC */ -#define _ICACHE_CMD_STOPPC_MASK 0x4UL /**< Bit mask for ICACHE_STOPPC */ -#define _ICACHE_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_STOPPC_DEFAULT (_ICACHE_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define _ICACHE_CMD_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CMD */ +#define _ICACHE_CMD_MASK 0x00000007UL /**< Mask for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH (0x1UL << 0) /**< Flush */ +#define _ICACHE_CMD_FLUSH_SHIFT 0 /**< Shift value for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_MASK 0x1UL /**< Bit mask for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH_DEFAULT (_ICACHE_CMD_FLUSH_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _ICACHE_CMD_STARTPC_SHIFT 1 /**< Shift value for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_MASK 0x2UL /**< Bit mask for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC_DEFAULT (_ICACHE_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _ICACHE_CMD_STOPPC_SHIFT 2 /**< Shift value for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_MASK 0x4UL /**< Bit mask for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC_DEFAULT (_ICACHE_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CMD */ /* Bit fields for ICACHE LPMODE */ -#define _ICACHE_LPMODE_RESETVALUE 0x00000023UL /**< Default value for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_MASK 0x000000F3UL /**< Mask for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_LPLEVEL_SHIFT 0 /**< Shift value for ICACHE_LPLEVEL */ -#define _ICACHE_LPMODE_LPLEVEL_MASK 0x3UL /**< Bit mask for ICACHE_LPLEVEL */ -#define _ICACHE_LPMODE_LPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_LPLEVEL_BASIC 0x00000000UL /**< Mode BASIC for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_LPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_LPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for ICACHE_LPMODE */ -#define ICACHE_LPMODE_LPLEVEL_DEFAULT (_ICACHE_LPMODE_LPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ -#define ICACHE_LPMODE_LPLEVEL_BASIC (_ICACHE_LPMODE_LPLEVEL_BASIC << 0) /**< Shifted mode BASIC for ICACHE_LPMODE */ -#define ICACHE_LPMODE_LPLEVEL_ADVANCED (_ICACHE_LPMODE_LPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for ICACHE_LPMODE */ -#define ICACHE_LPMODE_LPLEVEL_MINACTIVITY (_ICACHE_LPMODE_LPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_NESTFACTOR_SHIFT 4 /**< Shift value for ICACHE_NESTFACTOR */ -#define _ICACHE_LPMODE_NESTFACTOR_MASK 0xF0UL /**< Bit mask for ICACHE_NESTFACTOR */ -#define _ICACHE_LPMODE_NESTFACTOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for ICACHE_LPMODE */ -#define ICACHE_LPMODE_NESTFACTOR_DEFAULT (_ICACHE_LPMODE_NESTFACTOR_DEFAULT << 4) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_RESETVALUE 0x00000023UL /**< Default value for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_MASK 0x000000F3UL /**< Mask for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_SHIFT 0 /**< Shift value for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_MASK 0x3UL /**< Bit mask for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_BASIC 0x00000000UL /**< Mode BASIC for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_DEFAULT (_ICACHE_LPMODE_LPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_BASIC (_ICACHE_LPMODE_LPLEVEL_BASIC << 0) /**< Shifted mode BASIC for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_ADVANCED (_ICACHE_LPMODE_LPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_MINACTIVITY (_ICACHE_LPMODE_LPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_NESTFACTOR_SHIFT 4 /**< Shift value for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_MASK 0xF0UL /**< Bit mask for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_NESTFACTOR_DEFAULT (_ICACHE_LPMODE_NESTFACTOR_DEFAULT << 4) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ /* Bit fields for ICACHE IF */ -#define _ICACHE_IF_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IF */ -#define _ICACHE_IF_MASK 0x00000107UL /**< Mask for ICACHE_IF */ -#define ICACHE_IF_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Flag */ -#define _ICACHE_IF_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ -#define _ICACHE_IF_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ -#define _ICACHE_IF_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_HITOF_DEFAULT (_ICACHE_IF_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Flag */ -#define _ICACHE_IF_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ -#define _ICACHE_IF_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ -#define _ICACHE_IF_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_MISSOF_DEFAULT (_ICACHE_IF_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Flag */ -#define _ICACHE_IF_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ -#define _ICACHE_IF_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ -#define _ICACHE_IF_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_AHITOF_DEFAULT (_ICACHE_IF_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Flag */ -#define _ICACHE_IF_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ -#define _ICACHE_IF_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ -#define _ICACHE_IF_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_RAMERROR_DEFAULT (_ICACHE_IF_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define _ICACHE_IF_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IF */ +#define _ICACHE_IF_MASK 0x00000107UL /**< Mask for ICACHE_IF */ +#define ICACHE_IF_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_HITOF_DEFAULT (_ICACHE_IF_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Flag */ +#define _ICACHE_IF_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF_DEFAULT (_ICACHE_IF_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF_DEFAULT (_ICACHE_IF_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Flag */ +#define _ICACHE_IF_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR_DEFAULT (_ICACHE_IF_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IF */ /* Bit fields for ICACHE IEN */ -#define _ICACHE_IEN_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IEN */ -#define _ICACHE_IEN_MASK 0x00000107UL /**< Mask for ICACHE_IEN */ -#define ICACHE_IEN_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Enable */ -#define _ICACHE_IEN_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ -#define _ICACHE_IEN_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ -#define _ICACHE_IEN_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_HITOF_DEFAULT (_ICACHE_IEN_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Enable */ -#define _ICACHE_IEN_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ -#define _ICACHE_IEN_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ -#define _ICACHE_IEN_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_MISSOF_DEFAULT (_ICACHE_IEN_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Enable */ -#define _ICACHE_IEN_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ -#define _ICACHE_IEN_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ -#define _ICACHE_IEN_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_AHITOF_DEFAULT (_ICACHE_IEN_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Enable */ -#define _ICACHE_IEN_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ -#define _ICACHE_IEN_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ -#define _ICACHE_IEN_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_RAMERROR_DEFAULT (_ICACHE_IEN_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define _ICACHE_IEN_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IEN */ +#define _ICACHE_IEN_MASK 0x00000107UL /**< Mask for ICACHE_IEN */ +#define ICACHE_IEN_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_HITOF_DEFAULT (_ICACHE_IEN_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Enable */ +#define _ICACHE_IEN_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF_DEFAULT (_ICACHE_IEN_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF_DEFAULT (_ICACHE_IEN_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Enable */ +#define _ICACHE_IEN_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR_DEFAULT (_ICACHE_IEN_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IEN */ /** @} End of group EFR32SG23_ICACHE_BitFields */ /** @} End of group EFR32SG23_ICACHE */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_keyscan.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_keyscan.h index 01fa08508a..88c62b6b10 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_keyscan.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_KEYSCAN_H #define EFR32SG23_KEYSCAN_H - #define KEYSCAN_HAS_SET_CLEAR /**************************************************************************//** @@ -43,47 +42,46 @@ *****************************************************************************/ /** KEYSCAN Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< Enable */ - __IOM uint32_t SWRST; /**< Software Reset */ - __IOM uint32_t CFG; /**< Config */ - __IOM uint32_t CMD; /**< Command */ - __IOM uint32_t DELAY; /**< Delay */ - __IM uint32_t STATUS; /**< Status */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enables */ - uint32_t RESERVED0[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< Enable */ - __IOM uint32_t SWRST_SET; /**< Software Reset */ - __IOM uint32_t CFG_SET; /**< Config */ - __IOM uint32_t CMD_SET; /**< Command */ - __IOM uint32_t DELAY_SET; /**< Delay */ - __IM uint32_t STATUS_SET; /**< Status */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enables */ - uint32_t RESERVED1[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< Enable */ - __IOM uint32_t SWRST_CLR; /**< Software Reset */ - __IOM uint32_t CFG_CLR; /**< Config */ - __IOM uint32_t CMD_CLR; /**< Command */ - __IOM uint32_t DELAY_CLR; /**< Delay */ - __IM uint32_t STATUS_CLR; /**< Status */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ - uint32_t RESERVED2[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< Enable */ - __IOM uint32_t SWRST_TGL; /**< Software Reset */ - __IOM uint32_t CFG_TGL; /**< Config */ - __IOM uint32_t CMD_TGL; /**< Command */ - __IOM uint32_t DELAY_TGL; /**< Delay */ - __IM uint32_t STATUS_TGL; /**< Status */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t SWRST; /**< Software Reset */ + __IOM uint32_t CFG; /**< Config */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t DELAY; /**< Delay */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + uint32_t RESERVED0[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset */ + __IOM uint32_t CFG_SET; /**< Config */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t DELAY_SET; /**< Delay */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + uint32_t RESERVED1[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset */ + __IOM uint32_t CFG_CLR; /**< Config */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t DELAY_CLR; /**< Delay */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset */ + __IOM uint32_t CFG_TGL; /**< Config */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t DELAY_TGL; /**< Delay */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ } KEYSCAN_TypeDef; /** @} End of group EFR32SG23_KEYSCAN */ @@ -95,11 +93,11 @@ typedef struct *****************************************************************************/ /* Bit fields for KEYSCAN IPVERSION */ -#define _KEYSCAN_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for KEYSCAN_IPVERSION */ -#define _KEYSCAN_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for KEYSCAN_IPVERSION */ -#define _KEYSCAN_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for KEYSCAN_IPVERSION */ -#define _KEYSCAN_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for KEYSCAN_IPVERSION */ -#define _KEYSCAN_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_IPVERSION */ #define KEYSCAN_IPVERSION_IPVERSION_DEFAULT (_KEYSCAN_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IPVERSION */ /* Bit fields for KEYSCAN EN */ @@ -135,164 +133,164 @@ typedef struct #define KEYSCAN_SWRST_RESETTING_DEFAULT (_KEYSCAN_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_SWRST */ /* Bit fields for KEYSCAN CFG */ -#define _KEYSCAN_CFG_RESETVALUE 0x2501387FUL /**< Default value for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_MASK 0x7753FFFFUL /**< Mask for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_CLKDIV_SHIFT 0 /**< Shift value for KEYSCAN_CLKDIV */ -#define _KEYSCAN_CFG_CLKDIV_MASK 0x3FFFFUL /**< Bit mask for KEYSCAN_CLKDIV */ -#define _KEYSCAN_CFG_CLKDIV_DEFAULT 0x0001387FUL /**< Mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_CLKDIV_DEFAULT (_KEYSCAN_CFG_CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_SINGLEPRESS (0x1UL << 20) /**< Single Press */ -#define _KEYSCAN_CFG_SINGLEPRESS_SHIFT 20 /**< Shift value for KEYSCAN_SINGLEPRESS */ -#define _KEYSCAN_CFG_SINGLEPRESS_MASK 0x100000UL /**< Bit mask for KEYSCAN_SINGLEPRESS */ -#define _KEYSCAN_CFG_SINGLEPRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS 0x00000000UL /**< Mode MULTIPRESS for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS 0x00000001UL /**< Mode SINGLEPRESS for KEYSCAN_CFG */ -#define KEYSCAN_CFG_SINGLEPRESS_DEFAULT (_KEYSCAN_CFG_SINGLEPRESS_DEFAULT << 20) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS (_KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS << 20) /**< Shifted mode MULTIPRESS for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_RESETVALUE 0x2501387FUL /**< Default value for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_MASK 0x7753FFFFUL /**< Mask for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_CLKDIV_SHIFT 0 /**< Shift value for KEYSCAN_CLKDIV */ +#define _KEYSCAN_CFG_CLKDIV_MASK 0x3FFFFUL /**< Bit mask for KEYSCAN_CLKDIV */ +#define _KEYSCAN_CFG_CLKDIV_DEFAULT 0x0001387FUL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_CLKDIV_DEFAULT (_KEYSCAN_CFG_CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS (0x1UL << 20) /**< Single Press */ +#define _KEYSCAN_CFG_SINGLEPRESS_SHIFT 20 /**< Shift value for KEYSCAN_SINGLEPRESS */ +#define _KEYSCAN_CFG_SINGLEPRESS_MASK 0x100000UL /**< Bit mask for KEYSCAN_SINGLEPRESS */ +#define _KEYSCAN_CFG_SINGLEPRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS 0x00000000UL /**< Mode MULTIPRESS for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS 0x00000001UL /**< Mode SINGLEPRESS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS_DEFAULT (_KEYSCAN_CFG_SINGLEPRESS_DEFAULT << 20) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS (_KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS << 20) /**< Shifted mode MULTIPRESS for KEYSCAN_CFG */ #define KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS (_KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS << 20) /**< Shifted mode SINGLEPRESS for KEYSCAN_CFG */ -#define KEYSCAN_CFG_AUTOSTART (0x1UL << 22) /**< Automatically Start */ -#define _KEYSCAN_CFG_AUTOSTART_SHIFT 22 /**< Shift value for KEYSCAN_AUTOSTART */ -#define _KEYSCAN_CFG_AUTOSTART_MASK 0x400000UL /**< Bit mask for KEYSCAN_AUTOSTART */ -#define _KEYSCAN_CFG_AUTOSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS 0x00000000UL /**< Mode AUTOSTARTDIS for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN 0x00000001UL /**< Mode AUTOSTARTEN for KEYSCAN_CFG */ -#define KEYSCAN_CFG_AUTOSTART_DEFAULT (_KEYSCAN_CFG_AUTOSTART_DEFAULT << 22) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS << 22) /**< Shifted mode AUTOSTARTDIS for KEYSCAN_CFG */ -#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN << 22) /**< Shifted mode AUTOSTARTEN for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_SHIFT 24 /**< Shift value for KEYSCAN_NUMROWS */ -#define _KEYSCAN_CFG_NUMROWS_MASK 0x7000000UL /**< Bit mask for KEYSCAN_NUMROWS */ -#define _KEYSCAN_CFG_NUMROWS_DEFAULT 0x00000005UL /**< Mode DEFAULT for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_RSV1 0x00000000UL /**< Mode RSV1 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_RSV2 0x00000001UL /**< Mode RSV2 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_ROW3 0x00000002UL /**< Mode ROW3 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_ROW4 0x00000003UL /**< Mode ROW4 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_ROW5 0x00000004UL /**< Mode ROW5 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_ROW6 0x00000005UL /**< Mode ROW6 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_DEFAULT (_KEYSCAN_CFG_NUMROWS_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_RSV1 (_KEYSCAN_CFG_NUMROWS_RSV1 << 24) /**< Shifted mode RSV1 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_RSV2 (_KEYSCAN_CFG_NUMROWS_RSV2 << 24) /**< Shifted mode RSV2 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_ROW3 (_KEYSCAN_CFG_NUMROWS_ROW3 << 24) /**< Shifted mode ROW3 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_ROW4 (_KEYSCAN_CFG_NUMROWS_ROW4 << 24) /**< Shifted mode ROW4 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_ROW5 (_KEYSCAN_CFG_NUMROWS_ROW5 << 24) /**< Shifted mode ROW5 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_ROW6 (_KEYSCAN_CFG_NUMROWS_ROW6 << 24) /**< Shifted mode ROW6 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMCOLS_SHIFT 28 /**< Shift value for KEYSCAN_NUMCOLS */ -#define _KEYSCAN_CFG_NUMCOLS_MASK 0x70000000UL /**< Bit mask for KEYSCAN_NUMCOLS */ -#define _KEYSCAN_CFG_NUMCOLS_DEFAULT 0x00000002UL /**< Mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMCOLS_DEFAULT (_KEYSCAN_CFG_NUMCOLS_DEFAULT << 28) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART (0x1UL << 22) /**< Automatically Start */ +#define _KEYSCAN_CFG_AUTOSTART_SHIFT 22 /**< Shift value for KEYSCAN_AUTOSTART */ +#define _KEYSCAN_CFG_AUTOSTART_MASK 0x400000UL /**< Bit mask for KEYSCAN_AUTOSTART */ +#define _KEYSCAN_CFG_AUTOSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS 0x00000000UL /**< Mode AUTOSTARTDIS for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN 0x00000001UL /**< Mode AUTOSTARTEN for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_DEFAULT (_KEYSCAN_CFG_AUTOSTART_DEFAULT << 22) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS << 22) /**< Shifted mode AUTOSTARTDIS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN << 22) /**< Shifted mode AUTOSTARTEN for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_SHIFT 24 /**< Shift value for KEYSCAN_NUMROWS */ +#define _KEYSCAN_CFG_NUMROWS_MASK 0x7000000UL /**< Bit mask for KEYSCAN_NUMROWS */ +#define _KEYSCAN_CFG_NUMROWS_DEFAULT 0x00000005UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_RSV1 0x00000000UL /**< Mode RSV1 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_RSV2 0x00000001UL /**< Mode RSV2 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW3 0x00000002UL /**< Mode ROW3 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW4 0x00000003UL /**< Mode ROW4 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW5 0x00000004UL /**< Mode ROW5 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW6 0x00000005UL /**< Mode ROW6 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_DEFAULT (_KEYSCAN_CFG_NUMROWS_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_RSV1 (_KEYSCAN_CFG_NUMROWS_RSV1 << 24) /**< Shifted mode RSV1 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_RSV2 (_KEYSCAN_CFG_NUMROWS_RSV2 << 24) /**< Shifted mode RSV2 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW3 (_KEYSCAN_CFG_NUMROWS_ROW3 << 24) /**< Shifted mode ROW3 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW4 (_KEYSCAN_CFG_NUMROWS_ROW4 << 24) /**< Shifted mode ROW4 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW5 (_KEYSCAN_CFG_NUMROWS_ROW5 << 24) /**< Shifted mode ROW5 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW6 (_KEYSCAN_CFG_NUMROWS_ROW6 << 24) /**< Shifted mode ROW6 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMCOLS_SHIFT 28 /**< Shift value for KEYSCAN_NUMCOLS */ +#define _KEYSCAN_CFG_NUMCOLS_MASK 0x70000000UL /**< Bit mask for KEYSCAN_NUMCOLS */ +#define _KEYSCAN_CFG_NUMCOLS_DEFAULT 0x00000002UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMCOLS_DEFAULT (_KEYSCAN_CFG_NUMCOLS_DEFAULT << 28) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ /* Bit fields for KEYSCAN CMD */ -#define _KEYSCAN_CMD_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_CMD */ -#define _KEYSCAN_CMD_MASK 0x00000003UL /**< Mask for KEYSCAN_CMD */ -#define KEYSCAN_CMD_KEYSCANSTART (0x1UL << 0) /**< Keyscan Start */ -#define _KEYSCAN_CMD_KEYSCANSTART_SHIFT 0 /**< Shift value for KEYSCAN_KEYSCANSTART */ -#define _KEYSCAN_CMD_KEYSCANSTART_MASK 0x1UL /**< Bit mask for KEYSCAN_KEYSCANSTART */ -#define _KEYSCAN_CMD_KEYSCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ +#define _KEYSCAN_CMD_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_CMD */ +#define _KEYSCAN_CMD_MASK 0x00000003UL /**< Mask for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTART (0x1UL << 0) /**< Keyscan Start */ +#define _KEYSCAN_CMD_KEYSCANSTART_SHIFT 0 /**< Shift value for KEYSCAN_KEYSCANSTART */ +#define _KEYSCAN_CMD_KEYSCANSTART_MASK 0x1UL /**< Bit mask for KEYSCAN_KEYSCANSTART */ +#define _KEYSCAN_CMD_KEYSCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ #define KEYSCAN_CMD_KEYSCANSTART_DEFAULT (_KEYSCAN_CMD_KEYSCANSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CMD */ -#define KEYSCAN_CMD_KEYSCANSTOP (0x1UL << 1) /**< Keyscan Stop */ -#define _KEYSCAN_CMD_KEYSCANSTOP_SHIFT 1 /**< Shift value for KEYSCAN_KEYSCANSTOP */ -#define _KEYSCAN_CMD_KEYSCANSTOP_MASK 0x2UL /**< Bit mask for KEYSCAN_KEYSCANSTOP */ -#define _KEYSCAN_CMD_KEYSCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ -#define KEYSCAN_CMD_KEYSCANSTOP_DEFAULT (_KEYSCAN_CMD_KEYSCANSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTOP (0x1UL << 1) /**< Keyscan Stop */ +#define _KEYSCAN_CMD_KEYSCANSTOP_SHIFT 1 /**< Shift value for KEYSCAN_KEYSCANSTOP */ +#define _KEYSCAN_CMD_KEYSCANSTOP_MASK 0x2UL /**< Bit mask for KEYSCAN_KEYSCANSTOP */ +#define _KEYSCAN_CMD_KEYSCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTOP_DEFAULT (_KEYSCAN_CMD_KEYSCANSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_CMD */ /* Bit fields for KEYSCAN DELAY */ -#define _KEYSCAN_DELAY_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_MASK 0x0F0F0F00UL /**< Mask for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SHIFT 8 /**< Shift value for KEYSCAN_SCANDLY */ -#define _KEYSCAN_DELAY_SCANDLY_MASK 0xF00UL /**< Bit mask for KEYSCAN_SCANDLY */ -#define _KEYSCAN_DELAY_SCANDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY2 0x00000000UL /**< Mode SCANDLY2 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY4 0x00000001UL /**< Mode SCANDLY4 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY6 0x00000002UL /**< Mode SCANDLY6 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY8 0x00000003UL /**< Mode SCANDLY8 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY10 0x00000004UL /**< Mode SCANDLY10 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY12 0x00000005UL /**< Mode SCANDLY12 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY14 0x00000006UL /**< Mode SCANDLY14 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY16 0x00000007UL /**< Mode SCANDLY16 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY18 0x00000008UL /**< Mode SCANDLY18 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY20 0x00000009UL /**< Mode SCANDLY20 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY22 0x0000000AUL /**< Mode SCANDLY22 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY24 0x0000000BUL /**< Mode SCANDLY24 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY26 0x0000000CUL /**< Mode SCANDLY26 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY28 0x0000000DUL /**< Mode SCANDLY28 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY30 0x0000000EUL /**< Mode SCANDLY30 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY32 0x0000000FUL /**< Mode SCANDLY32 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_DEFAULT (_KEYSCAN_DELAY_SCANDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY2 (_KEYSCAN_DELAY_SCANDLY_SCANDLY2 << 8) /**< Shifted mode SCANDLY2 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY4 (_KEYSCAN_DELAY_SCANDLY_SCANDLY4 << 8) /**< Shifted mode SCANDLY4 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY6 (_KEYSCAN_DELAY_SCANDLY_SCANDLY6 << 8) /**< Shifted mode SCANDLY6 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY8 (_KEYSCAN_DELAY_SCANDLY_SCANDLY8 << 8) /**< Shifted mode SCANDLY8 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY10 (_KEYSCAN_DELAY_SCANDLY_SCANDLY10 << 8) /**< Shifted mode SCANDLY10 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY12 (_KEYSCAN_DELAY_SCANDLY_SCANDLY12 << 8) /**< Shifted mode SCANDLY12 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY14 (_KEYSCAN_DELAY_SCANDLY_SCANDLY14 << 8) /**< Shifted mode SCANDLY14 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY16 (_KEYSCAN_DELAY_SCANDLY_SCANDLY16 << 8) /**< Shifted mode SCANDLY16 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY18 (_KEYSCAN_DELAY_SCANDLY_SCANDLY18 << 8) /**< Shifted mode SCANDLY18 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY20 (_KEYSCAN_DELAY_SCANDLY_SCANDLY20 << 8) /**< Shifted mode SCANDLY20 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY22 (_KEYSCAN_DELAY_SCANDLY_SCANDLY22 << 8) /**< Shifted mode SCANDLY22 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY24 (_KEYSCAN_DELAY_SCANDLY_SCANDLY24 << 8) /**< Shifted mode SCANDLY24 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY26 (_KEYSCAN_DELAY_SCANDLY_SCANDLY26 << 8) /**< Shifted mode SCANDLY26 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY28 (_KEYSCAN_DELAY_SCANDLY_SCANDLY28 << 8) /**< Shifted mode SCANDLY28 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY30 (_KEYSCAN_DELAY_SCANDLY_SCANDLY30 << 8) /**< Shifted mode SCANDLY30 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY32 (_KEYSCAN_DELAY_SCANDLY_SCANDLY32 << 8) /**< Shifted mode SCANDLY32 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_SHIFT 16 /**< Shift value for KEYSCAN_DEBDLY */ -#define _KEYSCAN_DELAY_DEBDLY_MASK 0xF0000UL /**< Bit mask for KEYSCAN_DEBDLY */ -#define _KEYSCAN_DELAY_DEBDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY2 0x00000000UL /**< Mode DEBDLY2 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY4 0x00000001UL /**< Mode DEBDLY4 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY6 0x00000002UL /**< Mode DEBDLY6 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY8 0x00000003UL /**< Mode DEBDLY8 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY10 0x00000004UL /**< Mode DEBDLY10 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY12 0x00000005UL /**< Mode DEBDLY12 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY14 0x00000006UL /**< Mode DEBDLY14 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY16 0x00000007UL /**< Mode DEBDLY16 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY18 0x00000008UL /**< Mode DEBDLY18 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY20 0x00000009UL /**< Mode DEBDLY20 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY22 0x0000000AUL /**< Mode DEBDLY22 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY24 0x0000000BUL /**< Mode DEBDLY24 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY26 0x0000000CUL /**< Mode DEBDLY26 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY28 0x0000000DUL /**< Mode DEBDLY28 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY30 0x0000000EUL /**< Mode DEBDLY30 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY32 0x0000000FUL /**< Mode DEBDLY32 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEFAULT (_KEYSCAN_DELAY_DEBDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY2 (_KEYSCAN_DELAY_DEBDLY_DEBDLY2 << 16) /**< Shifted mode DEBDLY2 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY4 (_KEYSCAN_DELAY_DEBDLY_DEBDLY4 << 16) /**< Shifted mode DEBDLY4 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY6 (_KEYSCAN_DELAY_DEBDLY_DEBDLY6 << 16) /**< Shifted mode DEBDLY6 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY8 (_KEYSCAN_DELAY_DEBDLY_DEBDLY8 << 16) /**< Shifted mode DEBDLY8 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY10 (_KEYSCAN_DELAY_DEBDLY_DEBDLY10 << 16) /**< Shifted mode DEBDLY10 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY12 (_KEYSCAN_DELAY_DEBDLY_DEBDLY12 << 16) /**< Shifted mode DEBDLY12 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY14 (_KEYSCAN_DELAY_DEBDLY_DEBDLY14 << 16) /**< Shifted mode DEBDLY14 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY16 (_KEYSCAN_DELAY_DEBDLY_DEBDLY16 << 16) /**< Shifted mode DEBDLY16 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY18 (_KEYSCAN_DELAY_DEBDLY_DEBDLY18 << 16) /**< Shifted mode DEBDLY18 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY20 (_KEYSCAN_DELAY_DEBDLY_DEBDLY20 << 16) /**< Shifted mode DEBDLY20 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY22 (_KEYSCAN_DELAY_DEBDLY_DEBDLY22 << 16) /**< Shifted mode DEBDLY22 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY24 (_KEYSCAN_DELAY_DEBDLY_DEBDLY24 << 16) /**< Shifted mode DEBDLY24 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY26 (_KEYSCAN_DELAY_DEBDLY_DEBDLY26 << 16) /**< Shifted mode DEBDLY26 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY28 (_KEYSCAN_DELAY_DEBDLY_DEBDLY28 << 16) /**< Shifted mode DEBDLY28 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY30 (_KEYSCAN_DELAY_DEBDLY_DEBDLY30 << 16) /**< Shifted mode DEBDLY30 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY32 (_KEYSCAN_DELAY_DEBDLY_DEBDLY32 << 16) /**< Shifted mode DEBDLY32 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_SHIFT 24 /**< Shift value for KEYSCAN_STABDLY */ -#define _KEYSCAN_DELAY_STABDLY_MASK 0xF000000UL /**< Bit mask for KEYSCAN_STABDLY */ -#define _KEYSCAN_DELAY_STABDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY2 0x00000000UL /**< Mode STABDLY2 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY4 0x00000001UL /**< Mode STABDLY4 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY6 0x00000002UL /**< Mode STABDLY6 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY8 0x00000003UL /**< Mode STABDLY8 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY10 0x00000004UL /**< Mode STABDLY10 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY12 0x00000005UL /**< Mode STABDLY12 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY14 0x00000006UL /**< Mode STABDLY14 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY16 0x00000007UL /**< Mode STABDLY16 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY18 0x00000008UL /**< Mode STABDLY18 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY20 0x00000009UL /**< Mode STABDLY20 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY22 0x0000000AUL /**< Mode STABDLY22 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY24 0x0000000BUL /**< Mode STABDLY24 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY26 0x0000000CUL /**< Mode STABDLY26 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY28 0x0000000DUL /**< Mode STABDLY28 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY30 0x0000000EUL /**< Mode STABDLY30 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY32 0x0000000FUL /**< Mode STABDLY32 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_DEFAULT (_KEYSCAN_DELAY_STABDLY_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY2 (_KEYSCAN_DELAY_STABDLY_STABDLY2 << 24) /**< Shifted mode STABDLY2 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY4 (_KEYSCAN_DELAY_STABDLY_STABDLY4 << 24) /**< Shifted mode STABDLY4 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY6 (_KEYSCAN_DELAY_STABDLY_STABDLY6 << 24) /**< Shifted mode STABDLY6 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY8 (_KEYSCAN_DELAY_STABDLY_STABDLY8 << 24) /**< Shifted mode STABDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_MASK 0x0F0F0F00UL /**< Mask for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SHIFT 8 /**< Shift value for KEYSCAN_SCANDLY */ +#define _KEYSCAN_DELAY_SCANDLY_MASK 0xF00UL /**< Bit mask for KEYSCAN_SCANDLY */ +#define _KEYSCAN_DELAY_SCANDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY2 0x00000000UL /**< Mode SCANDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY4 0x00000001UL /**< Mode SCANDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY6 0x00000002UL /**< Mode SCANDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY8 0x00000003UL /**< Mode SCANDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY10 0x00000004UL /**< Mode SCANDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY12 0x00000005UL /**< Mode SCANDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY14 0x00000006UL /**< Mode SCANDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY16 0x00000007UL /**< Mode SCANDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY18 0x00000008UL /**< Mode SCANDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY20 0x00000009UL /**< Mode SCANDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY22 0x0000000AUL /**< Mode SCANDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY24 0x0000000BUL /**< Mode SCANDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY26 0x0000000CUL /**< Mode SCANDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY28 0x0000000DUL /**< Mode SCANDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY30 0x0000000EUL /**< Mode SCANDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY32 0x0000000FUL /**< Mode SCANDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_DEFAULT (_KEYSCAN_DELAY_SCANDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY2 (_KEYSCAN_DELAY_SCANDLY_SCANDLY2 << 8) /**< Shifted mode SCANDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY4 (_KEYSCAN_DELAY_SCANDLY_SCANDLY4 << 8) /**< Shifted mode SCANDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY6 (_KEYSCAN_DELAY_SCANDLY_SCANDLY6 << 8) /**< Shifted mode SCANDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY8 (_KEYSCAN_DELAY_SCANDLY_SCANDLY8 << 8) /**< Shifted mode SCANDLY8 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY10 (_KEYSCAN_DELAY_SCANDLY_SCANDLY10 << 8) /**< Shifted mode SCANDLY10 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY12 (_KEYSCAN_DELAY_SCANDLY_SCANDLY12 << 8) /**< Shifted mode SCANDLY12 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY14 (_KEYSCAN_DELAY_SCANDLY_SCANDLY14 << 8) /**< Shifted mode SCANDLY14 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY16 (_KEYSCAN_DELAY_SCANDLY_SCANDLY16 << 8) /**< Shifted mode SCANDLY16 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY18 (_KEYSCAN_DELAY_SCANDLY_SCANDLY18 << 8) /**< Shifted mode SCANDLY18 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY20 (_KEYSCAN_DELAY_SCANDLY_SCANDLY20 << 8) /**< Shifted mode SCANDLY20 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY22 (_KEYSCAN_DELAY_SCANDLY_SCANDLY22 << 8) /**< Shifted mode SCANDLY22 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY24 (_KEYSCAN_DELAY_SCANDLY_SCANDLY24 << 8) /**< Shifted mode SCANDLY24 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY26 (_KEYSCAN_DELAY_SCANDLY_SCANDLY26 << 8) /**< Shifted mode SCANDLY26 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY28 (_KEYSCAN_DELAY_SCANDLY_SCANDLY28 << 8) /**< Shifted mode SCANDLY28 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY30 (_KEYSCAN_DELAY_SCANDLY_SCANDLY30 << 8) /**< Shifted mode SCANDLY30 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY32 (_KEYSCAN_DELAY_SCANDLY_SCANDLY32 << 8) /**< Shifted mode SCANDLY32 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_SHIFT 16 /**< Shift value for KEYSCAN_DEBDLY */ +#define _KEYSCAN_DELAY_DEBDLY_MASK 0xF0000UL /**< Bit mask for KEYSCAN_DEBDLY */ +#define _KEYSCAN_DELAY_DEBDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY2 0x00000000UL /**< Mode DEBDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY4 0x00000001UL /**< Mode DEBDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY6 0x00000002UL /**< Mode DEBDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY8 0x00000003UL /**< Mode DEBDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY10 0x00000004UL /**< Mode DEBDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY12 0x00000005UL /**< Mode DEBDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY14 0x00000006UL /**< Mode DEBDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY16 0x00000007UL /**< Mode DEBDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY18 0x00000008UL /**< Mode DEBDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY20 0x00000009UL /**< Mode DEBDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY22 0x0000000AUL /**< Mode DEBDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY24 0x0000000BUL /**< Mode DEBDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY26 0x0000000CUL /**< Mode DEBDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY28 0x0000000DUL /**< Mode DEBDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY30 0x0000000EUL /**< Mode DEBDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY32 0x0000000FUL /**< Mode DEBDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEFAULT (_KEYSCAN_DELAY_DEBDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY2 (_KEYSCAN_DELAY_DEBDLY_DEBDLY2 << 16) /**< Shifted mode DEBDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY4 (_KEYSCAN_DELAY_DEBDLY_DEBDLY4 << 16) /**< Shifted mode DEBDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY6 (_KEYSCAN_DELAY_DEBDLY_DEBDLY6 << 16) /**< Shifted mode DEBDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY8 (_KEYSCAN_DELAY_DEBDLY_DEBDLY8 << 16) /**< Shifted mode DEBDLY8 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY10 (_KEYSCAN_DELAY_DEBDLY_DEBDLY10 << 16) /**< Shifted mode DEBDLY10 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY12 (_KEYSCAN_DELAY_DEBDLY_DEBDLY12 << 16) /**< Shifted mode DEBDLY12 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY14 (_KEYSCAN_DELAY_DEBDLY_DEBDLY14 << 16) /**< Shifted mode DEBDLY14 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY16 (_KEYSCAN_DELAY_DEBDLY_DEBDLY16 << 16) /**< Shifted mode DEBDLY16 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY18 (_KEYSCAN_DELAY_DEBDLY_DEBDLY18 << 16) /**< Shifted mode DEBDLY18 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY20 (_KEYSCAN_DELAY_DEBDLY_DEBDLY20 << 16) /**< Shifted mode DEBDLY20 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY22 (_KEYSCAN_DELAY_DEBDLY_DEBDLY22 << 16) /**< Shifted mode DEBDLY22 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY24 (_KEYSCAN_DELAY_DEBDLY_DEBDLY24 << 16) /**< Shifted mode DEBDLY24 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY26 (_KEYSCAN_DELAY_DEBDLY_DEBDLY26 << 16) /**< Shifted mode DEBDLY26 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY28 (_KEYSCAN_DELAY_DEBDLY_DEBDLY28 << 16) /**< Shifted mode DEBDLY28 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY30 (_KEYSCAN_DELAY_DEBDLY_DEBDLY30 << 16) /**< Shifted mode DEBDLY30 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY32 (_KEYSCAN_DELAY_DEBDLY_DEBDLY32 << 16) /**< Shifted mode DEBDLY32 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_SHIFT 24 /**< Shift value for KEYSCAN_STABDLY */ +#define _KEYSCAN_DELAY_STABDLY_MASK 0xF000000UL /**< Bit mask for KEYSCAN_STABDLY */ +#define _KEYSCAN_DELAY_STABDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY2 0x00000000UL /**< Mode STABDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY4 0x00000001UL /**< Mode STABDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY6 0x00000002UL /**< Mode STABDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY8 0x00000003UL /**< Mode STABDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY10 0x00000004UL /**< Mode STABDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY12 0x00000005UL /**< Mode STABDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY14 0x00000006UL /**< Mode STABDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY16 0x00000007UL /**< Mode STABDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY18 0x00000008UL /**< Mode STABDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY20 0x00000009UL /**< Mode STABDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY22 0x0000000AUL /**< Mode STABDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY24 0x0000000BUL /**< Mode STABDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY26 0x0000000CUL /**< Mode STABDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY28 0x0000000DUL /**< Mode STABDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY30 0x0000000EUL /**< Mode STABDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY32 0x0000000FUL /**< Mode STABDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_DEFAULT (_KEYSCAN_DELAY_STABDLY_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY2 (_KEYSCAN_DELAY_STABDLY_STABDLY2 << 24) /**< Shifted mode STABDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY4 (_KEYSCAN_DELAY_STABDLY_STABDLY4 << 24) /**< Shifted mode STABDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY6 (_KEYSCAN_DELAY_STABDLY_STABDLY6 << 24) /**< Shifted mode STABDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY8 (_KEYSCAN_DELAY_STABDLY_STABDLY8 << 24) /**< Shifted mode STABDLY8 for KEYSCAN_DELAY */ #define KEYSCAN_DELAY_STABDLY_STABDLY10 (_KEYSCAN_DELAY_STABDLY_STABDLY10 << 24) /**< Shifted mode STABDLY10 for KEYSCAN_DELAY */ #define KEYSCAN_DELAY_STABDLY_STABDLY12 (_KEYSCAN_DELAY_STABDLY_STABDLY12 << 24) /**< Shifted mode STABDLY12 for KEYSCAN_DELAY */ #define KEYSCAN_DELAY_STABDLY_STABDLY14 (_KEYSCAN_DELAY_STABDLY_STABDLY14 << 24) /**< Shifted mode STABDLY14 for KEYSCAN_DELAY */ @@ -307,30 +305,30 @@ typedef struct #define KEYSCAN_DELAY_STABDLY_STABDLY32 (_KEYSCAN_DELAY_STABDLY_STABDLY32 << 24) /**< Shifted mode STABDLY32 for KEYSCAN_DELAY */ /* Bit fields for KEYSCAN STATUS */ -#define _KEYSCAN_STATUS_RESETVALUE 0x40000000UL /**< Default value for KEYSCAN_STATUS */ -#define _KEYSCAN_STATUS_MASK 0xC701003FUL /**< Mask for KEYSCAN_STATUS */ -#define _KEYSCAN_STATUS_ROW_SHIFT 0 /**< Shift value for KEYSCAN_ROW */ -#define _KEYSCAN_STATUS_ROW_MASK 0x3FUL /**< Bit mask for KEYSCAN_ROW */ -#define _KEYSCAN_STATUS_ROW_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_ROW_DEFAULT (_KEYSCAN_STATUS_ROW_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_RUNNING (0x1UL << 16) /**< Running */ -#define _KEYSCAN_STATUS_RUNNING_SHIFT 16 /**< Shift value for KEYSCAN_RUNNING */ -#define _KEYSCAN_STATUS_RUNNING_MASK 0x10000UL /**< Bit mask for KEYSCAN_RUNNING */ -#define _KEYSCAN_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_RUNNING_DEFAULT (_KEYSCAN_STATUS_RUNNING_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ -#define _KEYSCAN_STATUS_COL_SHIFT 24 /**< Shift value for KEYSCAN_COL */ -#define _KEYSCAN_STATUS_COL_MASK 0x7000000UL /**< Bit mask for KEYSCAN_COL */ -#define _KEYSCAN_STATUS_COL_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_COL_DEFAULT (_KEYSCAN_STATUS_COL_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_NOKEY (0x1UL << 30) /**< No Key pressed status */ -#define _KEYSCAN_STATUS_NOKEY_SHIFT 30 /**< Shift value for KEYSCAN_NOKEY */ -#define _KEYSCAN_STATUS_NOKEY_MASK 0x40000000UL /**< Bit mask for KEYSCAN_NOKEY */ -#define _KEYSCAN_STATUS_NOKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_NOKEY_DEFAULT (_KEYSCAN_STATUS_NOKEY_DEFAULT << 30) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy */ -#define _KEYSCAN_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for KEYSCAN_SYNCBUSY */ -#define _KEYSCAN_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for KEYSCAN_SYNCBUSY */ -#define _KEYSCAN_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_RESETVALUE 0x40000000UL /**< Default value for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_MASK 0xC701003FUL /**< Mask for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_ROW_SHIFT 0 /**< Shift value for KEYSCAN_ROW */ +#define _KEYSCAN_STATUS_ROW_MASK 0x3FUL /**< Bit mask for KEYSCAN_ROW */ +#define _KEYSCAN_STATUS_ROW_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_ROW_DEFAULT (_KEYSCAN_STATUS_ROW_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_RUNNING (0x1UL << 16) /**< Running */ +#define _KEYSCAN_STATUS_RUNNING_SHIFT 16 /**< Shift value for KEYSCAN_RUNNING */ +#define _KEYSCAN_STATUS_RUNNING_MASK 0x10000UL /**< Bit mask for KEYSCAN_RUNNING */ +#define _KEYSCAN_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_RUNNING_DEFAULT (_KEYSCAN_STATUS_RUNNING_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_COL_SHIFT 24 /**< Shift value for KEYSCAN_COL */ +#define _KEYSCAN_STATUS_COL_MASK 0x7000000UL /**< Bit mask for KEYSCAN_COL */ +#define _KEYSCAN_STATUS_COL_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_COL_DEFAULT (_KEYSCAN_STATUS_COL_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_NOKEY (0x1UL << 30) /**< No Key pressed status */ +#define _KEYSCAN_STATUS_NOKEY_SHIFT 30 /**< Shift value for KEYSCAN_NOKEY */ +#define _KEYSCAN_STATUS_NOKEY_MASK 0x40000000UL /**< Bit mask for KEYSCAN_NOKEY */ +#define _KEYSCAN_STATUS_NOKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_NOKEY_DEFAULT (_KEYSCAN_STATUS_NOKEY_DEFAULT << 30) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy */ +#define _KEYSCAN_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for KEYSCAN_SYNCBUSY */ +#define _KEYSCAN_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for KEYSCAN_SYNCBUSY */ +#define _KEYSCAN_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ #define KEYSCAN_STATUS_SYNCBUSY_DEFAULT (_KEYSCAN_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ /* Bit fields for KEYSCAN IF */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lcd.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lcd.h index b1270230ac..3d7be41e3d 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lcd.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lcd.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lcdrf.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lcdrf.h index 49f35414e2..390540aeba 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lcdrf.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lcdrf.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldma.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldma.h index b8eeb55d65..a59ecc1610 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldma.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldma.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_LDMA_H #define EFR32SG23_LDMA_H - #define LDMA_HAS_SET_CLEAR /**************************************************************************//** @@ -43,117 +42,114 @@ *****************************************************************************/ /** LDMA CH Register Group Declaration. */ -typedef struct -{ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t CFG; /**< Channel Configuration Register */ - __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ - __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ - __IOM uint32_t SRC; /**< Channel Descriptor Source Address */ - __IOM uint32_t DST; /**< Channel Descriptor Destination Address */ - __IOM uint32_t LINK; /**< Channel Descriptor Link Address */ - uint32_t RESERVED1[5U]; /**< Reserved for future use */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG; /**< Channel Configuration Register */ + __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ + __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ + __IOM uint32_t SRC; /**< Channel Descriptor Source Address */ + __IOM uint32_t DST; /**< Channel Descriptor Destination Address */ + __IOM uint32_t LINK; /**< Channel Descriptor Link Address */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ } LDMA_CH_TypeDef; - /** LDMA Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< DMA Channel Request Clear Register */ - __IOM uint32_t EN; /**< DMA module enable disable Register */ - __IOM uint32_t CTRL; /**< DMA Control Register */ - __IM uint32_t STATUS; /**< DMA Status Register */ - __IOM uint32_t SYNCSWSET; /**< DMA Sync Trig Sw Set Register */ - __IOM uint32_t SYNCSWCLR; /**< DMA Sync Trig Sw Clear register */ - __IOM uint32_t SYNCHWEN; /**< DMA Sync HW trigger enable register */ - __IOM uint32_t SYNCHWSEL; /**< DMA Sync HW trigger selection register */ - __IM uint32_t SYNCSTATUS; /**< DMA Sync Trigger Status Register */ - __IOM uint32_t CHEN; /**< DMA Channel Enable Register */ - __IOM uint32_t CHDIS; /**< DMA Channel Disable Register */ - __IM uint32_t CHSTATUS; /**< DMA Channel Status Register */ - __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ - __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register */ - __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ - __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request */ - __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ - __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ - __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ - __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED0[906U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< DMA Channel Request Clear Register */ - __IOM uint32_t EN_SET; /**< DMA module enable disable Register */ - __IOM uint32_t CTRL_SET; /**< DMA Control Register */ - __IM uint32_t STATUS_SET; /**< DMA Status Register */ - __IOM uint32_t SYNCSWSET_SET; /**< DMA Sync Trig Sw Set Register */ - __IOM uint32_t SYNCSWCLR_SET; /**< DMA Sync Trig Sw Clear register */ - __IOM uint32_t SYNCHWEN_SET; /**< DMA Sync HW trigger enable register */ - __IOM uint32_t SYNCHWSEL_SET; /**< DMA Sync HW trigger selection register */ - __IM uint32_t SYNCSTATUS_SET; /**< DMA Sync Trigger Status Register */ - __IOM uint32_t CHEN_SET; /**< DMA Channel Enable Register */ - __IOM uint32_t CHDIS_SET; /**< DMA Channel Disable Register */ - __IM uint32_t CHSTATUS_SET; /**< DMA Channel Status Register */ - __IM uint32_t CHBUSY_SET; /**< DMA Channel Busy Register */ - __IOM uint32_t CHDONE_SET; /**< DMA Channel Linking Done Register */ - __IOM uint32_t DBGHALT_SET; /**< DMA Channel Debug Halt Register */ - __IOM uint32_t SWREQ_SET; /**< DMA Channel Software Transfer Request */ - __IOM uint32_t REQDIS_SET; /**< DMA Channel Request Disable Register */ - __IM uint32_t REQPEND_SET; /**< DMA Channel Requests Pending Register */ - __IOM uint32_t LINKLOAD_SET; /**< DMA Channel Link Load Register */ - __IOM uint32_t REQCLEAR_SET; /**< DMA Channel Request Clear Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - LDMA_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED1[906U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< DMA Channel Request Clear Register */ - __IOM uint32_t EN_CLR; /**< DMA module enable disable Register */ - __IOM uint32_t CTRL_CLR; /**< DMA Control Register */ - __IM uint32_t STATUS_CLR; /**< DMA Status Register */ - __IOM uint32_t SYNCSWSET_CLR; /**< DMA Sync Trig Sw Set Register */ - __IOM uint32_t SYNCSWCLR_CLR; /**< DMA Sync Trig Sw Clear register */ - __IOM uint32_t SYNCHWEN_CLR; /**< DMA Sync HW trigger enable register */ - __IOM uint32_t SYNCHWSEL_CLR; /**< DMA Sync HW trigger selection register */ - __IM uint32_t SYNCSTATUS_CLR; /**< DMA Sync Trigger Status Register */ - __IOM uint32_t CHEN_CLR; /**< DMA Channel Enable Register */ - __IOM uint32_t CHDIS_CLR; /**< DMA Channel Disable Register */ - __IM uint32_t CHSTATUS_CLR; /**< DMA Channel Status Register */ - __IM uint32_t CHBUSY_CLR; /**< DMA Channel Busy Register */ - __IOM uint32_t CHDONE_CLR; /**< DMA Channel Linking Done Register */ - __IOM uint32_t DBGHALT_CLR; /**< DMA Channel Debug Halt Register */ - __IOM uint32_t SWREQ_CLR; /**< DMA Channel Software Transfer Request */ - __IOM uint32_t REQDIS_CLR; /**< DMA Channel Request Disable Register */ - __IM uint32_t REQPEND_CLR; /**< DMA Channel Requests Pending Register */ - __IOM uint32_t LINKLOAD_CLR; /**< DMA Channel Link Load Register */ - __IOM uint32_t REQCLEAR_CLR; /**< DMA Channel Request Clear Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - LDMA_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED2[906U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< DMA Channel Request Clear Register */ - __IOM uint32_t EN_TGL; /**< DMA module enable disable Register */ - __IOM uint32_t CTRL_TGL; /**< DMA Control Register */ - __IM uint32_t STATUS_TGL; /**< DMA Status Register */ - __IOM uint32_t SYNCSWSET_TGL; /**< DMA Sync Trig Sw Set Register */ - __IOM uint32_t SYNCSWCLR_TGL; /**< DMA Sync Trig Sw Clear register */ - __IOM uint32_t SYNCHWEN_TGL; /**< DMA Sync HW trigger enable register */ - __IOM uint32_t SYNCHWSEL_TGL; /**< DMA Sync HW trigger selection register */ - __IM uint32_t SYNCSTATUS_TGL; /**< DMA Sync Trigger Status Register */ - __IOM uint32_t CHEN_TGL; /**< DMA Channel Enable Register */ - __IOM uint32_t CHDIS_TGL; /**< DMA Channel Disable Register */ - __IM uint32_t CHSTATUS_TGL; /**< DMA Channel Status Register */ - __IM uint32_t CHBUSY_TGL; /**< DMA Channel Busy Register */ - __IOM uint32_t CHDONE_TGL; /**< DMA Channel Linking Done Register */ - __IOM uint32_t DBGHALT_TGL; /**< DMA Channel Debug Halt Register */ - __IOM uint32_t SWREQ_TGL; /**< DMA Channel Software Transfer Request */ - __IOM uint32_t REQDIS_TGL; /**< DMA Channel Request Disable Register */ - __IM uint32_t REQPEND_TGL; /**< DMA Channel Requests Pending Register */ - __IOM uint32_t LINKLOAD_TGL; /**< DMA Channel Link Load Register */ - __IOM uint32_t REQCLEAR_TGL; /**< DMA Channel Request Clear Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - LDMA_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +typedef struct { + __IM uint32_t IPVERSION; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL; /**< DMA Control Register */ + __IM uint32_t STATUS; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN_SET; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_SET; /**< DMA Control Register */ + __IM uint32_t STATUS_SET; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_SET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_SET; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_SET; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_SET; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_SET; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_SET; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_SET; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_SET; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_SET; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_SET; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_SET; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_SET; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_SET; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_SET; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_SET; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_SET; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN_CLR; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_CLR; /**< DMA Control Register */ + __IM uint32_t STATUS_CLR; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_CLR; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_CLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_CLR; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_CLR; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_CLR; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_CLR; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_CLR; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_CLR; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_CLR; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_CLR; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_CLR; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_CLR; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_CLR; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_CLR; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_CLR; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_CLR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN_TGL; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_TGL; /**< DMA Control Register */ + __IM uint32_t STATUS_TGL; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_TGL; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_TGL; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_TGL; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_TGL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_TGL; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_TGL; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_TGL; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_TGL; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_TGL; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_TGL; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_TGL; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_TGL; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_TGL; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_TGL; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_TGL; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_TGL; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ } LDMA_TypeDef; /** @} End of group EFR32SG23_LDMA */ @@ -165,11 +161,11 @@ typedef struct *****************************************************************************/ /* Bit fields for LDMA IPVERSION */ -#define _LDMA_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LDMA_IPVERSION */ -#define _LDMA_IPVERSION_MASK 0x000000FFUL /**< Mask for LDMA_IPVERSION */ -#define _LDMA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMA_IPVERSION */ -#define _LDMA_IPVERSION_IPVERSION_MASK 0xFFUL /**< Bit mask for LDMA_IPVERSION */ -#define _LDMA_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_MASK 0x000000FFUL /**< Mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_MASK 0xFFUL /**< Bit mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IPVERSION */ #define LDMA_IPVERSION_IPVERSION_DEFAULT (_LDMA_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IPVERSION */ /* Bit fields for LDMA EN */ @@ -225,59 +221,59 @@ typedef struct #define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ /* Bit fields for LDMA SYNCSWSET */ -#define _LDMA_SYNCSWSET_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWSET */ -#define _LDMA_SYNCSWSET_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWSET */ -#define _LDMA_SYNCSWSET_SYNCSWSET_SHIFT 0 /**< Shift value for LDMA_SYNCSWSET */ -#define _LDMA_SYNCSWSET_SYNCSWSET_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWSET */ -#define _LDMA_SYNCSWSET_SYNCSWSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_SHIFT 0 /**< Shift value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWSET */ #define LDMA_SYNCSWSET_SYNCSWSET_DEFAULT (_LDMA_SYNCSWSET_SYNCSWSET_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWSET */ /* Bit fields for LDMA SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_SYNCSWCLR_SHIFT 0 /**< Shift value for LDMA_SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_SYNCSWCLR_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_SHIFT 0 /**< Shift value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWCLR */ #define LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT (_LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWCLR */ /* Bit fields for LDMA SYNCHWEN */ -#define _LDMA_SYNCHWEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWEN */ -#define _LDMA_SYNCHWEN_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWEN */ -#define _LDMA_SYNCHWEN_SYNCSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCSETEN */ -#define _LDMA_SYNCHWEN_SYNCSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEN */ -#define _LDMA_SYNCHWEN_SYNCSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ -#define LDMA_SYNCHWEN_SYNCSETEN_DEFAULT (_LDMA_SYNCHWEN_SYNCSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ -#define _LDMA_SYNCHWEN_SYNCCLREN_SHIFT 16 /**< Shift value for LDMA_SYNCCLREN */ -#define _LDMA_SYNCHWEN_SYNCCLREN_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREN */ -#define _LDMA_SYNCHWEN_SYNCCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define LDMA_SYNCHWEN_SYNCSETEN_DEFAULT (_LDMA_SYNCHWEN_SYNCSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_SHIFT 16 /**< Shift value for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ #define LDMA_SYNCHWEN_SYNCCLREN_DEFAULT (_LDMA_SYNCHWEN_SYNCCLREN_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ /* Bit fields for LDMA SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_SHIFT 0 /**< Shift value for LDMA_SYNCSETEDGE */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEDGE */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCSETEDGE_RISE (_LDMA_SYNCHWSEL_SYNCSETEDGE_RISE << 0) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCSETEDGE_FALL (_LDMA_SYNCHWSEL_SYNCSETEDGE_FALL << 0) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_SHIFT 16 /**< Shift value for LDMA_SYNCCLREDGE */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREDGE */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_SHIFT 0 /**< Shift value for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_RISE (_LDMA_SYNCHWSEL_SYNCSETEDGE_RISE << 0) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_FALL (_LDMA_SYNCHWSEL_SYNCSETEDGE_FALL << 0) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_SHIFT 16 /**< Shift value for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ #define LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCCLREDGE_RISE (_LDMA_SYNCHWSEL_SYNCCLREDGE_RISE << 16) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCCLREDGE_FALL (_LDMA_SYNCHWSEL_SYNCCLREDGE_FALL << 16) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_RISE (_LDMA_SYNCHWSEL_SYNCCLREDGE_RISE << 16) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_FALL (_LDMA_SYNCHWSEL_SYNCCLREDGE_FALL << 16) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ /* Bit fields for LDMA SYNCSTATUS */ -#define _LDMA_SYNCSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSTATUS */ -#define _LDMA_SYNCSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSTATUS */ -#define _LDMA_SYNCSTATUS_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ -#define _LDMA_SYNCSTATUS_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ -#define _LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSTATUS */ #define LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT (_LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSTATUS */ /* Bit fields for LDMA CHEN */ @@ -467,36 +463,36 @@ typedef struct #define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ /* Bit fields for LDMA CH_CFG */ -#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ -#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ -#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ -#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ -#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ -#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ -#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ +#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ #define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ #define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ -#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ -#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ -#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ +#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ #define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ #define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ @@ -509,140 +505,140 @@ typedef struct #define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ /* Bit fields for LDMA CH_CTRL */ -#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ -#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ -#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ -#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ -#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ -#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ -#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ -#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ -#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ -#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ -#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ -#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ -#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DONEIEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set En */ -#define _LDMA_CH_CTRL_DONEIEN_SHIFT 20 /**< Shift value for LDMA_DONEIEN */ -#define _LDMA_CH_CTRL_DONEIEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIEN */ -#define _LDMA_CH_CTRL_DONEIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DONEIEN_DEFAULT (_LDMA_CH_CTRL_DONEIEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ -#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ -#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ -#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ -#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ -#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ -#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ -#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ -#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ -#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ -#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ -#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ -#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ -#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ -#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ -#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ -#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ -#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ -#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ -#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ -#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ -#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ +#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ +#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set En */ +#define _LDMA_CH_CTRL_DONEIEN_SHIFT 20 /**< Shift value for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN_DEFAULT (_LDMA_CH_CTRL_DONEIEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ +#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ +#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ +#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ +#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ +#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ /* Bit fields for LDMA CH_SRC */ #define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldmaxbar.h index 8792be0be9..6043a16aa6 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldmaxbar.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_LDMAXBAR_H #define EFR32SG23_LDMAXBAR_H - #define LDMAXBAR_HAS_SET_CLEAR /**************************************************************************//** @@ -43,26 +42,23 @@ *****************************************************************************/ /** LDMAXBAR CH Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Reg... */ +typedef struct { + __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Reg... */ } LDMAXBAR_CH_TypeDef; - /** LDMAXBAR Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP veersion ID */ - LDMAXBAR_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED0[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP veersion ID */ - LDMAXBAR_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED1[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP veersion ID */ - LDMAXBAR_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED2[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP veersion ID */ - LDMAXBAR_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ } LDMAXBAR_TypeDef; /** @} End of group EFR32SG23_LDMAXBAR */ @@ -74,24 +70,24 @@ typedef struct *****************************************************************************/ /* Bit fields for LDMAXBAR IPVERSION */ -#define _LDMAXBAR_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for LDMAXBAR_IPVERSION */ -#define _LDMAXBAR_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LDMAXBAR_IPVERSION */ -#define _LDMAXBAR_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMAXBAR_IPVERSION */ -#define _LDMAXBAR_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LDMAXBAR_IPVERSION */ -#define _LDMAXBAR_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for LDMAXBAR_IPVERSION */ -#define LDMAXBAR_IPVERSION_IPVERSION_DEFAULT (_LDMAXBAR_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for LDMAXBAR_IPVERSION */ +#define LDMAXBAR_IPVERSION_IPVERSION_DEFAULT (_LDMAXBAR_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_IPVERSION */ /* Bit fields for LDMAXBAR CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMAXBAR_SIGSEL */ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMAXBAR_SIGSEL */ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMAXBAR_SOURCESEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMAXBAR_SOURCESEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ /** @} End of group EFR32SG23_LDMAXBAR_BitFields */ /** @} End of group EFR32SG23_LDMAXBAR */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldmaxbar_defines.h index 49092960c2..5a93f2934a 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lesense.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lesense.h index afdd57a4de..e756d29fd9 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lesense.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lesense.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_LESENSE_H #define EFR32SG23_LESENSE_H - #define LESENSE_HAS_SET_CLEAR /**************************************************************************//** @@ -43,136 +42,131 @@ *****************************************************************************/ /** LESENSE CH Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t TIMING; /**< Scan configuration */ - __IOM uint32_t INTERACT; /**< Scan configuration */ - __IOM uint32_t EVALCFG; /**< Scan configuration */ - __IOM uint32_t EVALTHRES; /**< Scan confguration */ +typedef struct { + __IOM uint32_t TIMING; /**< Scan configuration */ + __IOM uint32_t INTERACT; /**< Scan configuration */ + __IOM uint32_t EVALCFG; /**< Scan configuration */ + __IOM uint32_t EVALTHRES; /**< Scan confguration */ } LESENSE_CH_TypeDef; - /** LESENSE ST Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t ARC; /**< State transition Arc */ +typedef struct { + __IOM uint32_t ARC; /**< State transition Arc */ } LESENSE_ST_TypeDef; - /** LESENSE Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< Enable */ - __IOM uint32_t SWRST; /**< Software Reset Register */ - __IOM uint32_t CFG; /**< Configuration */ - __IOM uint32_t TIMCTRL; /**< Timing Control */ - __IOM uint32_t PERCTRL; /**< Peripheral Control */ - __IOM uint32_t DECCTRL; /**< Decoder control */ - __IOM uint32_t EVALCTRL; /**< LESENSE evaluation */ - __IOM uint32_t PRSCTRL; /**< PRS control */ - __IOM uint32_t CMD; /**< Command */ - __IOM uint32_t CHEN; /**< Channel enable */ - __IM uint32_t SCANRES; /**< Scan result */ - __IM uint32_t STATUS; /**< Status */ - __IM uint32_t RESCOUNT; /**< Result FIFO Count */ - __IM uint32_t RESFIFO; /**< Result Fifo */ - __IM uint32_t CURCH; /**< Current channel index */ - __IM uint32_t DECSTATE; /**< Current decoder state */ - __IM uint32_t SENSORSTATE; /**< Sensor State */ - __IOM uint32_t IDLECONF; /**< IDLE Configuration */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t SYNCBUSY; /**< Synchronization */ - uint32_t RESERVED1[3U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enables */ - uint32_t RESERVED2[38U]; /**< Reserved for future use */ - LESENSE_CH_TypeDef CH[16U]; /**< Channels */ - LESENSE_ST_TypeDef ST[64U]; /**< Decoding FSM Arcs */ - uint32_t RESERVED3[832U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< Enable */ - __IOM uint32_t SWRST_SET; /**< Software Reset Register */ - __IOM uint32_t CFG_SET; /**< Configuration */ - __IOM uint32_t TIMCTRL_SET; /**< Timing Control */ - __IOM uint32_t PERCTRL_SET; /**< Peripheral Control */ - __IOM uint32_t DECCTRL_SET; /**< Decoder control */ - __IOM uint32_t EVALCTRL_SET; /**< LESENSE evaluation */ - __IOM uint32_t PRSCTRL_SET; /**< PRS control */ - __IOM uint32_t CMD_SET; /**< Command */ - __IOM uint32_t CHEN_SET; /**< Channel enable */ - __IM uint32_t SCANRES_SET; /**< Scan result */ - __IM uint32_t STATUS_SET; /**< Status */ - __IM uint32_t RESCOUNT_SET; /**< Result FIFO Count */ - __IM uint32_t RESFIFO_SET; /**< Result Fifo */ - __IM uint32_t CURCH_SET; /**< Current channel index */ - __IM uint32_t DECSTATE_SET; /**< Current decoder state */ - __IM uint32_t SENSORSTATE_SET; /**< Sensor State */ - __IOM uint32_t IDLECONF_SET; /**< IDLE Configuration */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization */ - uint32_t RESERVED5[3U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enables */ - uint32_t RESERVED6[38U]; /**< Reserved for future use */ - LESENSE_CH_TypeDef CH_SET[16U]; /**< Channels */ - LESENSE_ST_TypeDef ST_SET[64U]; /**< Decoding FSM Arcs */ - uint32_t RESERVED7[832U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< Enable */ - __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ - __IOM uint32_t CFG_CLR; /**< Configuration */ - __IOM uint32_t TIMCTRL_CLR; /**< Timing Control */ - __IOM uint32_t PERCTRL_CLR; /**< Peripheral Control */ - __IOM uint32_t DECCTRL_CLR; /**< Decoder control */ - __IOM uint32_t EVALCTRL_CLR; /**< LESENSE evaluation */ - __IOM uint32_t PRSCTRL_CLR; /**< PRS control */ - __IOM uint32_t CMD_CLR; /**< Command */ - __IOM uint32_t CHEN_CLR; /**< Channel enable */ - __IM uint32_t SCANRES_CLR; /**< Scan result */ - __IM uint32_t STATUS_CLR; /**< Status */ - __IM uint32_t RESCOUNT_CLR; /**< Result FIFO Count */ - __IM uint32_t RESFIFO_CLR; /**< Result Fifo */ - __IM uint32_t CURCH_CLR; /**< Current channel index */ - __IM uint32_t DECSTATE_CLR; /**< Current decoder state */ - __IM uint32_t SENSORSTATE_CLR; /**< Sensor State */ - __IOM uint32_t IDLECONF_CLR; /**< IDLE Configuration */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization */ - uint32_t RESERVED9[3U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ - uint32_t RESERVED10[38U]; /**< Reserved for future use */ - LESENSE_CH_TypeDef CH_CLR[16U]; /**< Channels */ - LESENSE_ST_TypeDef ST_CLR[64U]; /**< Decoding FSM Arcs */ - uint32_t RESERVED11[832U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< Enable */ - __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ - __IOM uint32_t CFG_TGL; /**< Configuration */ - __IOM uint32_t TIMCTRL_TGL; /**< Timing Control */ - __IOM uint32_t PERCTRL_TGL; /**< Peripheral Control */ - __IOM uint32_t DECCTRL_TGL; /**< Decoder control */ - __IOM uint32_t EVALCTRL_TGL; /**< LESENSE evaluation */ - __IOM uint32_t PRSCTRL_TGL; /**< PRS control */ - __IOM uint32_t CMD_TGL; /**< Command */ - __IOM uint32_t CHEN_TGL; /**< Channel enable */ - __IM uint32_t SCANRES_TGL; /**< Scan result */ - __IM uint32_t STATUS_TGL; /**< Status */ - __IM uint32_t RESCOUNT_TGL; /**< Result FIFO Count */ - __IM uint32_t RESFIFO_TGL; /**< Result Fifo */ - __IM uint32_t CURCH_TGL; /**< Current channel index */ - __IM uint32_t DECSTATE_TGL; /**< Current decoder state */ - __IM uint32_t SENSORSTATE_TGL; /**< Sensor State */ - __IOM uint32_t IDLECONF_TGL; /**< IDLE Configuration */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization */ - uint32_t RESERVED13[3U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ - uint32_t RESERVED14[38U]; /**< Reserved for future use */ - LESENSE_CH_TypeDef CH_TGL[16U]; /**< Channels */ - LESENSE_ST_TypeDef ST_TGL[64U]; /**< Decoding FSM Arcs */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Configuration */ + __IOM uint32_t TIMCTRL; /**< Timing Control */ + __IOM uint32_t PERCTRL; /**< Peripheral Control */ + __IOM uint32_t DECCTRL; /**< Decoder control */ + __IOM uint32_t EVALCTRL; /**< LESENSE evaluation */ + __IOM uint32_t PRSCTRL; /**< PRS control */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t CHEN; /**< Channel enable */ + __IM uint32_t SCANRES; /**< Scan result */ + __IM uint32_t STATUS; /**< Status */ + __IM uint32_t RESCOUNT; /**< Result FIFO Count */ + __IM uint32_t RESFIFO; /**< Result Fifo */ + __IM uint32_t CURCH; /**< Current channel index */ + __IM uint32_t DECSTATE; /**< Current decoder state */ + __IM uint32_t SENSORSTATE; /**< Sensor State */ + __IOM uint32_t IDLECONF; /**< IDLE Configuration */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY; /**< Synchronization */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + uint32_t RESERVED2[38U]; /**< Reserved for future use */ + LESENSE_CH_TypeDef CH[16U]; /**< Channels */ + LESENSE_ST_TypeDef ST[64U]; /**< Decoding FSM Arcs */ + uint32_t RESERVED3[832U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Configuration */ + __IOM uint32_t TIMCTRL_SET; /**< Timing Control */ + __IOM uint32_t PERCTRL_SET; /**< Peripheral Control */ + __IOM uint32_t DECCTRL_SET; /**< Decoder control */ + __IOM uint32_t EVALCTRL_SET; /**< LESENSE evaluation */ + __IOM uint32_t PRSCTRL_SET; /**< PRS control */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t CHEN_SET; /**< Channel enable */ + __IM uint32_t SCANRES_SET; /**< Scan result */ + __IM uint32_t STATUS_SET; /**< Status */ + __IM uint32_t RESCOUNT_SET; /**< Result FIFO Count */ + __IM uint32_t RESFIFO_SET; /**< Result Fifo */ + __IM uint32_t CURCH_SET; /**< Current channel index */ + __IM uint32_t DECSTATE_SET; /**< Current decoder state */ + __IM uint32_t SENSORSTATE_SET; /**< Sensor State */ + __IOM uint32_t IDLECONF_SET; /**< IDLE Configuration */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization */ + uint32_t RESERVED5[3U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + uint32_t RESERVED6[38U]; /**< Reserved for future use */ + LESENSE_CH_TypeDef CH_SET[16U]; /**< Channels */ + LESENSE_ST_TypeDef ST_SET[64U]; /**< Decoding FSM Arcs */ + uint32_t RESERVED7[832U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Configuration */ + __IOM uint32_t TIMCTRL_CLR; /**< Timing Control */ + __IOM uint32_t PERCTRL_CLR; /**< Peripheral Control */ + __IOM uint32_t DECCTRL_CLR; /**< Decoder control */ + __IOM uint32_t EVALCTRL_CLR; /**< LESENSE evaluation */ + __IOM uint32_t PRSCTRL_CLR; /**< PRS control */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t CHEN_CLR; /**< Channel enable */ + __IM uint32_t SCANRES_CLR; /**< Scan result */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IM uint32_t RESCOUNT_CLR; /**< Result FIFO Count */ + __IM uint32_t RESFIFO_CLR; /**< Result Fifo */ + __IM uint32_t CURCH_CLR; /**< Current channel index */ + __IM uint32_t DECSTATE_CLR; /**< Current decoder state */ + __IM uint32_t SENSORSTATE_CLR; /**< Sensor State */ + __IOM uint32_t IDLECONF_CLR; /**< IDLE Configuration */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization */ + uint32_t RESERVED9[3U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + uint32_t RESERVED10[38U]; /**< Reserved for future use */ + LESENSE_CH_TypeDef CH_CLR[16U]; /**< Channels */ + LESENSE_ST_TypeDef ST_CLR[64U]; /**< Decoding FSM Arcs */ + uint32_t RESERVED11[832U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Configuration */ + __IOM uint32_t TIMCTRL_TGL; /**< Timing Control */ + __IOM uint32_t PERCTRL_TGL; /**< Peripheral Control */ + __IOM uint32_t DECCTRL_TGL; /**< Decoder control */ + __IOM uint32_t EVALCTRL_TGL; /**< LESENSE evaluation */ + __IOM uint32_t PRSCTRL_TGL; /**< PRS control */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t CHEN_TGL; /**< Channel enable */ + __IM uint32_t SCANRES_TGL; /**< Scan result */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IM uint32_t RESCOUNT_TGL; /**< Result FIFO Count */ + __IM uint32_t RESFIFO_TGL; /**< Result Fifo */ + __IM uint32_t CURCH_TGL; /**< Current channel index */ + __IM uint32_t DECSTATE_TGL; /**< Current decoder state */ + __IM uint32_t SENSORSTATE_TGL; /**< Sensor State */ + __IOM uint32_t IDLECONF_TGL; /**< IDLE Configuration */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization */ + uint32_t RESERVED13[3U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ + uint32_t RESERVED14[38U]; /**< Reserved for future use */ + LESENSE_CH_TypeDef CH_TGL[16U]; /**< Channels */ + LESENSE_ST_TypeDef ST_TGL[64U]; /**< Decoding FSM Arcs */ } LESENSE_TypeDef; /** @} End of group EFR32SG23_LESENSE */ @@ -184,1042 +178,1042 @@ typedef struct *****************************************************************************/ /* Bit fields for LESENSE IPVERSION */ -#define _LESENSE_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LESENSE_IPVERSION */ -#define _LESENSE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_IPVERSION */ -#define _LESENSE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LESENSE_IPVERSION */ -#define _LESENSE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LESENSE_IPVERSION */ -#define _LESENSE_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LESENSE_IPVERSION */ -#define LESENSE_IPVERSION_IPVERSION_DEFAULT (_LESENSE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IPVERSION */ +#define _LESENSE_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LESENSE_IPVERSION */ +#define _LESENSE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_IPVERSION */ +#define _LESENSE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LESENSE_IPVERSION */ +#define _LESENSE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LESENSE_IPVERSION */ +#define _LESENSE_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LESENSE_IPVERSION */ +#define LESENSE_IPVERSION_IPVERSION_DEFAULT (_LESENSE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IPVERSION */ /* Bit fields for LESENSE EN */ -#define _LESENSE_EN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_EN */ -#define _LESENSE_EN_MASK 0x00000003UL /**< Mask for LESENSE_EN */ -#define LESENSE_EN_EN (0x1UL << 0) /**< Enable */ -#define _LESENSE_EN_EN_SHIFT 0 /**< Shift value for LESENSE_EN */ -#define _LESENSE_EN_EN_MASK 0x1UL /**< Bit mask for LESENSE_EN */ -#define _LESENSE_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EN */ -#define _LESENSE_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_EN */ -#define _LESENSE_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for LESENSE_EN */ -#define LESENSE_EN_EN_DEFAULT (_LESENSE_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_EN */ -#define LESENSE_EN_EN_DISABLE (_LESENSE_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_EN */ -#define LESENSE_EN_EN_ENABLE (_LESENSE_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for LESENSE_EN */ -#define LESENSE_EN_DISABLING (0x1UL << 1) /**< Disabling */ -#define _LESENSE_EN_DISABLING_SHIFT 1 /**< Shift value for LESENSE_DISABLING */ -#define _LESENSE_EN_DISABLING_MASK 0x2UL /**< Bit mask for LESENSE_DISABLING */ -#define _LESENSE_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EN */ -#define LESENSE_EN_DISABLING_DEFAULT (_LESENSE_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_EN */ +#define _LESENSE_EN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_EN */ +#define _LESENSE_EN_MASK 0x00000003UL /**< Mask for LESENSE_EN */ +#define LESENSE_EN_EN (0x1UL << 0) /**< Enable */ +#define _LESENSE_EN_EN_SHIFT 0 /**< Shift value for LESENSE_EN */ +#define _LESENSE_EN_EN_MASK 0x1UL /**< Bit mask for LESENSE_EN */ +#define _LESENSE_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EN */ +#define _LESENSE_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_EN */ +#define _LESENSE_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for LESENSE_EN */ +#define LESENSE_EN_EN_DEFAULT (_LESENSE_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_EN */ +#define LESENSE_EN_EN_DISABLE (_LESENSE_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_EN */ +#define LESENSE_EN_EN_ENABLE (_LESENSE_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for LESENSE_EN */ +#define LESENSE_EN_DISABLING (0x1UL << 1) /**< Disabling */ +#define _LESENSE_EN_DISABLING_SHIFT 1 /**< Shift value for LESENSE_DISABLING */ +#define _LESENSE_EN_DISABLING_MASK 0x2UL /**< Bit mask for LESENSE_DISABLING */ +#define _LESENSE_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EN */ +#define LESENSE_EN_DISABLING_DEFAULT (_LESENSE_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_EN */ /* Bit fields for LESENSE SWRST */ -#define _LESENSE_SWRST_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SWRST */ -#define _LESENSE_SWRST_MASK 0x00000003UL /**< Mask for LESENSE_SWRST */ -#define LESENSE_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ -#define _LESENSE_SWRST_SWRST_SHIFT 0 /**< Shift value for LESENSE_SWRST */ -#define _LESENSE_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LESENSE_SWRST */ -#define _LESENSE_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SWRST */ -#define LESENSE_SWRST_SWRST_DEFAULT (_LESENSE_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SWRST */ -#define LESENSE_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ -#define _LESENSE_SWRST_RESETTING_SHIFT 1 /**< Shift value for LESENSE_RESETTING */ -#define _LESENSE_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LESENSE_RESETTING */ -#define _LESENSE_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SWRST */ -#define LESENSE_SWRST_RESETTING_DEFAULT (_LESENSE_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_SWRST */ +#define _LESENSE_SWRST_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SWRST */ +#define _LESENSE_SWRST_MASK 0x00000003UL /**< Mask for LESENSE_SWRST */ +#define LESENSE_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _LESENSE_SWRST_SWRST_SHIFT 0 /**< Shift value for LESENSE_SWRST */ +#define _LESENSE_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LESENSE_SWRST */ +#define _LESENSE_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SWRST */ +#define LESENSE_SWRST_SWRST_DEFAULT (_LESENSE_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SWRST */ +#define LESENSE_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _LESENSE_SWRST_RESETTING_SHIFT 1 /**< Shift value for LESENSE_RESETTING */ +#define _LESENSE_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LESENSE_RESETTING */ +#define _LESENSE_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SWRST */ +#define LESENSE_SWRST_RESETTING_DEFAULT (_LESENSE_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_SWRST */ /* Bit fields for LESENSE CFG */ -#define _LESENSE_CFG_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CFG */ -#define _LESENSE_CFG_MASK 0x00020FEFUL /**< Mask for LESENSE_CFG */ -#define _LESENSE_CFG_SCANMODE_SHIFT 0 /**< Shift value for LESENSE_SCANMODE */ -#define _LESENSE_CFG_SCANMODE_MASK 0x3UL /**< Bit mask for LESENSE_SCANMODE */ -#define _LESENSE_CFG_SCANMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ -#define _LESENSE_CFG_SCANMODE_PERIODIC 0x00000000UL /**< Mode PERIODIC for LESENSE_CFG */ -#define _LESENSE_CFG_SCANMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LESENSE_CFG */ -#define _LESENSE_CFG_SCANMODE_PRS 0x00000002UL /**< Mode PRS for LESENSE_CFG */ -#define LESENSE_CFG_SCANMODE_DEFAULT (_LESENSE_CFG_SCANMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_SCANMODE_PERIODIC (_LESENSE_CFG_SCANMODE_PERIODIC << 0) /**< Shifted mode PERIODIC for LESENSE_CFG */ -#define LESENSE_CFG_SCANMODE_ONESHOT (_LESENSE_CFG_SCANMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LESENSE_CFG */ -#define LESENSE_CFG_SCANMODE_PRS (_LESENSE_CFG_SCANMODE_PRS << 0) /**< Shifted mode PRS for LESENSE_CFG */ -#define _LESENSE_CFG_SCANCONF_SHIFT 2 /**< Shift value for LESENSE_SCANCONF */ -#define _LESENSE_CFG_SCANCONF_MASK 0xCUL /**< Bit mask for LESENSE_SCANCONF */ -#define _LESENSE_CFG_SCANCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ -#define _LESENSE_CFG_SCANCONF_DIRMAP 0x00000000UL /**< Mode DIRMAP for LESENSE_CFG */ -#define _LESENSE_CFG_SCANCONF_INVMAP 0x00000001UL /**< Mode INVMAP for LESENSE_CFG */ -#define _LESENSE_CFG_SCANCONF_TOGGLE 0x00000002UL /**< Mode TOGGLE for LESENSE_CFG */ -#define _LESENSE_CFG_SCANCONF_DECDEF 0x00000003UL /**< Mode DECDEF for LESENSE_CFG */ -#define LESENSE_CFG_SCANCONF_DEFAULT (_LESENSE_CFG_SCANCONF_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_SCANCONF_DIRMAP (_LESENSE_CFG_SCANCONF_DIRMAP << 2) /**< Shifted mode DIRMAP for LESENSE_CFG */ -#define LESENSE_CFG_SCANCONF_INVMAP (_LESENSE_CFG_SCANCONF_INVMAP << 2) /**< Shifted mode INVMAP for LESENSE_CFG */ -#define LESENSE_CFG_SCANCONF_TOGGLE (_LESENSE_CFG_SCANCONF_TOGGLE << 2) /**< Shifted mode TOGGLE for LESENSE_CFG */ -#define LESENSE_CFG_SCANCONF_DECDEF (_LESENSE_CFG_SCANCONF_DECDEF << 2) /**< Shifted mode DECDEF for LESENSE_CFG */ -#define LESENSE_CFG_DUALSAMPLE (0x1UL << 5) /**< Enable dual sample mode */ -#define _LESENSE_CFG_DUALSAMPLE_SHIFT 5 /**< Shift value for LESENSE_DUALSAMPLE */ -#define _LESENSE_CFG_DUALSAMPLE_MASK 0x20UL /**< Bit mask for LESENSE_DUALSAMPLE */ -#define _LESENSE_CFG_DUALSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_DUALSAMPLE_DEFAULT (_LESENSE_CFG_DUALSAMPLE_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_STRSCANRES (0x1UL << 6) /**< Enable storing of SCANRES */ -#define _LESENSE_CFG_STRSCANRES_SHIFT 6 /**< Shift value for LESENSE_STRSCANRES */ -#define _LESENSE_CFG_STRSCANRES_MASK 0x40UL /**< Bit mask for LESENSE_STRSCANRES */ -#define _LESENSE_CFG_STRSCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_STRSCANRES_DEFAULT (_LESENSE_CFG_STRSCANRES_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_DMAWU (0x1UL << 7) /**< DMA wake-up from EM2 */ -#define _LESENSE_CFG_DMAWU_SHIFT 7 /**< Shift value for LESENSE_DMAWU */ -#define _LESENSE_CFG_DMAWU_MASK 0x80UL /**< Bit mask for LESENSE_DMAWU */ -#define _LESENSE_CFG_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ -#define _LESENSE_CFG_DMAWU_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CFG */ -#define _LESENSE_CFG_DMAWU_ENABLE 0x00000001UL /**< Mode ENABLE for LESENSE_CFG */ -#define LESENSE_CFG_DMAWU_DEFAULT (_LESENSE_CFG_DMAWU_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_DMAWU_DISABLE (_LESENSE_CFG_DMAWU_DISABLE << 7) /**< Shifted mode DISABLE for LESENSE_CFG */ -#define LESENSE_CFG_DMAWU_ENABLE (_LESENSE_CFG_DMAWU_ENABLE << 7) /**< Shifted mode ENABLE for LESENSE_CFG */ -#define _LESENSE_CFG_RESFIDL_SHIFT 8 /**< Shift value for LESENSE_RESFIDL */ -#define _LESENSE_CFG_RESFIDL_MASK 0xF00UL /**< Bit mask for LESENSE_RESFIDL */ -#define _LESENSE_CFG_RESFIDL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_RESFIDL_DEFAULT (_LESENSE_CFG_RESFIDL_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_DEBUGRUN (0x1UL << 17) /**< Debug Mode Run Enable */ -#define _LESENSE_CFG_DEBUGRUN_SHIFT 17 /**< Shift value for LESENSE_DEBUGRUN */ -#define _LESENSE_CFG_DEBUGRUN_MASK 0x20000UL /**< Bit mask for LESENSE_DEBUGRUN */ -#define _LESENSE_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ -#define _LESENSE_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for LESENSE_CFG */ -#define _LESENSE_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for LESENSE_CFG */ -#define LESENSE_CFG_DEBUGRUN_DEFAULT (_LESENSE_CFG_DEBUGRUN_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_DEBUGRUN_X0 (_LESENSE_CFG_DEBUGRUN_X0 << 17) /**< Shifted mode X0 for LESENSE_CFG */ -#define LESENSE_CFG_DEBUGRUN_X1 (_LESENSE_CFG_DEBUGRUN_X1 << 17) /**< Shifted mode X1 for LESENSE_CFG */ +#define _LESENSE_CFG_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CFG */ +#define _LESENSE_CFG_MASK 0x00020FEFUL /**< Mask for LESENSE_CFG */ +#define _LESENSE_CFG_SCANMODE_SHIFT 0 /**< Shift value for LESENSE_SCANMODE */ +#define _LESENSE_CFG_SCANMODE_MASK 0x3UL /**< Bit mask for LESENSE_SCANMODE */ +#define _LESENSE_CFG_SCANMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define _LESENSE_CFG_SCANMODE_PERIODIC 0x00000000UL /**< Mode PERIODIC for LESENSE_CFG */ +#define _LESENSE_CFG_SCANMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LESENSE_CFG */ +#define _LESENSE_CFG_SCANMODE_PRS 0x00000002UL /**< Mode PRS for LESENSE_CFG */ +#define LESENSE_CFG_SCANMODE_DEFAULT (_LESENSE_CFG_SCANMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_SCANMODE_PERIODIC (_LESENSE_CFG_SCANMODE_PERIODIC << 0) /**< Shifted mode PERIODIC for LESENSE_CFG */ +#define LESENSE_CFG_SCANMODE_ONESHOT (_LESENSE_CFG_SCANMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LESENSE_CFG */ +#define LESENSE_CFG_SCANMODE_PRS (_LESENSE_CFG_SCANMODE_PRS << 0) /**< Shifted mode PRS for LESENSE_CFG */ +#define _LESENSE_CFG_SCANCONF_SHIFT 2 /**< Shift value for LESENSE_SCANCONF */ +#define _LESENSE_CFG_SCANCONF_MASK 0xCUL /**< Bit mask for LESENSE_SCANCONF */ +#define _LESENSE_CFG_SCANCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define _LESENSE_CFG_SCANCONF_DIRMAP 0x00000000UL /**< Mode DIRMAP for LESENSE_CFG */ +#define _LESENSE_CFG_SCANCONF_INVMAP 0x00000001UL /**< Mode INVMAP for LESENSE_CFG */ +#define _LESENSE_CFG_SCANCONF_TOGGLE 0x00000002UL /**< Mode TOGGLE for LESENSE_CFG */ +#define _LESENSE_CFG_SCANCONF_DECDEF 0x00000003UL /**< Mode DECDEF for LESENSE_CFG */ +#define LESENSE_CFG_SCANCONF_DEFAULT (_LESENSE_CFG_SCANCONF_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_SCANCONF_DIRMAP (_LESENSE_CFG_SCANCONF_DIRMAP << 2) /**< Shifted mode DIRMAP for LESENSE_CFG */ +#define LESENSE_CFG_SCANCONF_INVMAP (_LESENSE_CFG_SCANCONF_INVMAP << 2) /**< Shifted mode INVMAP for LESENSE_CFG */ +#define LESENSE_CFG_SCANCONF_TOGGLE (_LESENSE_CFG_SCANCONF_TOGGLE << 2) /**< Shifted mode TOGGLE for LESENSE_CFG */ +#define LESENSE_CFG_SCANCONF_DECDEF (_LESENSE_CFG_SCANCONF_DECDEF << 2) /**< Shifted mode DECDEF for LESENSE_CFG */ +#define LESENSE_CFG_DUALSAMPLE (0x1UL << 5) /**< Enable dual sample mode */ +#define _LESENSE_CFG_DUALSAMPLE_SHIFT 5 /**< Shift value for LESENSE_DUALSAMPLE */ +#define _LESENSE_CFG_DUALSAMPLE_MASK 0x20UL /**< Bit mask for LESENSE_DUALSAMPLE */ +#define _LESENSE_CFG_DUALSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_DUALSAMPLE_DEFAULT (_LESENSE_CFG_DUALSAMPLE_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_STRSCANRES (0x1UL << 6) /**< Enable storing of SCANRES */ +#define _LESENSE_CFG_STRSCANRES_SHIFT 6 /**< Shift value for LESENSE_STRSCANRES */ +#define _LESENSE_CFG_STRSCANRES_MASK 0x40UL /**< Bit mask for LESENSE_STRSCANRES */ +#define _LESENSE_CFG_STRSCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_STRSCANRES_DEFAULT (_LESENSE_CFG_STRSCANRES_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_DMAWU (0x1UL << 7) /**< DMA wake-up from EM2 */ +#define _LESENSE_CFG_DMAWU_SHIFT 7 /**< Shift value for LESENSE_DMAWU */ +#define _LESENSE_CFG_DMAWU_MASK 0x80UL /**< Bit mask for LESENSE_DMAWU */ +#define _LESENSE_CFG_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define _LESENSE_CFG_DMAWU_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CFG */ +#define _LESENSE_CFG_DMAWU_ENABLE 0x00000001UL /**< Mode ENABLE for LESENSE_CFG */ +#define LESENSE_CFG_DMAWU_DEFAULT (_LESENSE_CFG_DMAWU_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_DMAWU_DISABLE (_LESENSE_CFG_DMAWU_DISABLE << 7) /**< Shifted mode DISABLE for LESENSE_CFG */ +#define LESENSE_CFG_DMAWU_ENABLE (_LESENSE_CFG_DMAWU_ENABLE << 7) /**< Shifted mode ENABLE for LESENSE_CFG */ +#define _LESENSE_CFG_RESFIDL_SHIFT 8 /**< Shift value for LESENSE_RESFIDL */ +#define _LESENSE_CFG_RESFIDL_MASK 0xF00UL /**< Bit mask for LESENSE_RESFIDL */ +#define _LESENSE_CFG_RESFIDL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_RESFIDL_DEFAULT (_LESENSE_CFG_RESFIDL_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_DEBUGRUN (0x1UL << 17) /**< Debug Mode Run Enable */ +#define _LESENSE_CFG_DEBUGRUN_SHIFT 17 /**< Shift value for LESENSE_DEBUGRUN */ +#define _LESENSE_CFG_DEBUGRUN_MASK 0x20000UL /**< Bit mask for LESENSE_DEBUGRUN */ +#define _LESENSE_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define _LESENSE_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for LESENSE_CFG */ +#define _LESENSE_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for LESENSE_CFG */ +#define LESENSE_CFG_DEBUGRUN_DEFAULT (_LESENSE_CFG_DEBUGRUN_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_DEBUGRUN_X0 (_LESENSE_CFG_DEBUGRUN_X0 << 17) /**< Shifted mode X0 for LESENSE_CFG */ +#define LESENSE_CFG_DEBUGRUN_X1 (_LESENSE_CFG_DEBUGRUN_X1 << 17) /**< Shifted mode X1 for LESENSE_CFG */ /* Bit fields for LESENSE TIMCTRL */ -#define _LESENSE_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_MASK 0x10CFF773UL /**< Mask for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_AUXPRESC_SHIFT 0 /**< Shift value for LESENSE_AUXPRESC */ -#define _LESENSE_TIMCTRL_AUXPRESC_MASK 0x3UL /**< Bit mask for LESENSE_AUXPRESC */ -#define _LESENSE_TIMCTRL_AUXPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_AUXPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_AUXPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_AUXPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_AUXPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXPRESC_DEFAULT (_LESENSE_TIMCTRL_AUXPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXPRESC_DIV1 (_LESENSE_TIMCTRL_AUXPRESC_DIV1 << 0) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXPRESC_DIV2 (_LESENSE_TIMCTRL_AUXPRESC_DIV2 << 0) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXPRESC_DIV4 (_LESENSE_TIMCTRL_AUXPRESC_DIV4 << 0) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXPRESC_DIV8 (_LESENSE_TIMCTRL_AUXPRESC_DIV8 << 0) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_SHIFT 4 /**< Shift value for LESENSE_LFPRESC */ -#define _LESENSE_TIMCTRL_LFPRESC_MASK 0x70UL /**< Bit mask for LESENSE_LFPRESC */ -#define _LESENSE_TIMCTRL_LFPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DEFAULT (_LESENSE_TIMCTRL_LFPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DIV1 (_LESENSE_TIMCTRL_LFPRESC_DIV1 << 4) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DIV2 (_LESENSE_TIMCTRL_LFPRESC_DIV2 << 4) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DIV4 (_LESENSE_TIMCTRL_LFPRESC_DIV4 << 4) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DIV8 (_LESENSE_TIMCTRL_LFPRESC_DIV8 << 4) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DIV16 (_LESENSE_TIMCTRL_LFPRESC_DIV16 << 4) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DIV32 (_LESENSE_TIMCTRL_LFPRESC_DIV32 << 4) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DIV64 (_LESENSE_TIMCTRL_LFPRESC_DIV64 << 4) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DIV128 (_LESENSE_TIMCTRL_LFPRESC_DIV128 << 4) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_SHIFT 8 /**< Shift value for LESENSE_PCPRESC */ -#define _LESENSE_TIMCTRL_PCPRESC_MASK 0x700UL /**< Bit mask for LESENSE_PCPRESC */ -#define _LESENSE_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DEFAULT (_LESENSE_TIMCTRL_PCPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DIV1 (_LESENSE_TIMCTRL_PCPRESC_DIV1 << 8) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DIV2 (_LESENSE_TIMCTRL_PCPRESC_DIV2 << 8) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DIV4 (_LESENSE_TIMCTRL_PCPRESC_DIV4 << 8) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DIV8 (_LESENSE_TIMCTRL_PCPRESC_DIV8 << 8) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DIV16 (_LESENSE_TIMCTRL_PCPRESC_DIV16 << 8) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DIV32 (_LESENSE_TIMCTRL_PCPRESC_DIV32 << 8) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DIV64 (_LESENSE_TIMCTRL_PCPRESC_DIV64 << 8) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DIV128 (_LESENSE_TIMCTRL_PCPRESC_DIV128 << 8) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCTOP_SHIFT 12 /**< Shift value for LESENSE_PCTOP */ -#define _LESENSE_TIMCTRL_PCTOP_MASK 0xFF000UL /**< Bit mask for LESENSE_PCTOP */ -#define _LESENSE_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCTOP_DEFAULT (_LESENSE_TIMCTRL_PCTOP_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_STARTDLY_SHIFT 22 /**< Shift value for LESENSE_STARTDLY */ -#define _LESENSE_TIMCTRL_STARTDLY_MASK 0xC00000UL /**< Bit mask for LESENSE_STARTDLY */ -#define _LESENSE_TIMCTRL_STARTDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_STARTDLY_DEFAULT (_LESENSE_TIMCTRL_STARTDLY_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXSTARTUP (0x1UL << 28) /**< AUX startup config */ -#define _LESENSE_TIMCTRL_AUXSTARTUP_SHIFT 28 /**< Shift value for LESENSE_AUXSTARTUP */ -#define _LESENSE_TIMCTRL_AUXSTARTUP_MASK 0x10000000UL /**< Bit mask for LESENSE_AUXSTARTUP */ -#define _LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND 0x00000000UL /**< Mode PREDEMAND for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND 0x00000001UL /**< Mode ONDEMAND for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT (_LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND << 28) /**< Shifted mode PREDEMAND for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND << 28) /**< Shifted mode ONDEMAND for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_MASK 0x10CFF773UL /**< Mask for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_SHIFT 0 /**< Shift value for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_MASK 0x3UL /**< Bit mask for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DEFAULT (_LESENSE_TIMCTRL_AUXPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV1 (_LESENSE_TIMCTRL_AUXPRESC_DIV1 << 0) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV2 (_LESENSE_TIMCTRL_AUXPRESC_DIV2 << 0) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV4 (_LESENSE_TIMCTRL_AUXPRESC_DIV4 << 0) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV8 (_LESENSE_TIMCTRL_AUXPRESC_DIV8 << 0) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_SHIFT 4 /**< Shift value for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_MASK 0x70UL /**< Bit mask for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DEFAULT (_LESENSE_TIMCTRL_LFPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV1 (_LESENSE_TIMCTRL_LFPRESC_DIV1 << 4) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV2 (_LESENSE_TIMCTRL_LFPRESC_DIV2 << 4) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV4 (_LESENSE_TIMCTRL_LFPRESC_DIV4 << 4) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV8 (_LESENSE_TIMCTRL_LFPRESC_DIV8 << 4) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV16 (_LESENSE_TIMCTRL_LFPRESC_DIV16 << 4) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV32 (_LESENSE_TIMCTRL_LFPRESC_DIV32 << 4) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV64 (_LESENSE_TIMCTRL_LFPRESC_DIV64 << 4) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV128 (_LESENSE_TIMCTRL_LFPRESC_DIV128 << 4) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_SHIFT 8 /**< Shift value for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_MASK 0x700UL /**< Bit mask for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DEFAULT (_LESENSE_TIMCTRL_PCPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV1 (_LESENSE_TIMCTRL_PCPRESC_DIV1 << 8) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV2 (_LESENSE_TIMCTRL_PCPRESC_DIV2 << 8) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV4 (_LESENSE_TIMCTRL_PCPRESC_DIV4 << 8) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV8 (_LESENSE_TIMCTRL_PCPRESC_DIV8 << 8) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV16 (_LESENSE_TIMCTRL_PCPRESC_DIV16 << 8) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV32 (_LESENSE_TIMCTRL_PCPRESC_DIV32 << 8) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV64 (_LESENSE_TIMCTRL_PCPRESC_DIV64 << 8) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV128 (_LESENSE_TIMCTRL_PCPRESC_DIV128 << 8) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCTOP_SHIFT 12 /**< Shift value for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_MASK 0xFF000UL /**< Bit mask for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCTOP_DEFAULT (_LESENSE_TIMCTRL_PCTOP_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_STARTDLY_SHIFT 22 /**< Shift value for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_MASK 0xC00000UL /**< Bit mask for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_STARTDLY_DEFAULT (_LESENSE_TIMCTRL_STARTDLY_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP (0x1UL << 28) /**< AUX startup config */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_SHIFT 28 /**< Shift value for LESENSE_AUXSTARTUP */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_MASK 0x10000000UL /**< Bit mask for LESENSE_AUXSTARTUP */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND 0x00000000UL /**< Mode PREDEMAND for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND 0x00000001UL /**< Mode ONDEMAND for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT (_LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND << 28) /**< Shifted mode PREDEMAND for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND << 28) /**< Shifted mode ONDEMAND for LESENSE_TIMCTRL */ /* Bit fields for LESENSE PERCTRL */ -#define _LESENSE_PERCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_MASK 0x03500144UL /**< Mask for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACCH0DATA (0x1UL << 2) /**< DAC CH0 data selection. */ -#define _LESENSE_PERCTRL_DACCH0DATA_SHIFT 2 /**< Shift value for LESENSE_DACCH0DATA */ -#define _LESENSE_PERCTRL_DACCH0DATA_MASK 0x4UL /**< Bit mask for LESENSE_DACCH0DATA */ -#define _LESENSE_PERCTRL_DACCH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_DACCH0DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_DACCH0DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACCH0DATA_DEFAULT (_LESENSE_PERCTRL_DACCH0DATA_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACCH0DATA_DACDATA (_LESENSE_PERCTRL_DACCH0DATA_DACDATA << 2) /**< Shifted mode DACDATA for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACCH0DATA_THRES (_LESENSE_PERCTRL_DACCH0DATA_THRES << 2) /**< Shifted mode THRES for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACSTARTUP (0x1UL << 6) /**< DAC startup configuration */ -#define _LESENSE_PERCTRL_DACSTARTUP_SHIFT 6 /**< Shift value for LESENSE_DACSTARTUP */ -#define _LESENSE_PERCTRL_DACSTARTUP_MASK 0x40UL /**< Bit mask for LESENSE_DACSTARTUP */ -#define _LESENSE_PERCTRL_DACSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE 0x00000000UL /**< Mode FULLCYCLE for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE 0x00000001UL /**< Mode HALFCYCLE for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACSTARTUP_DEFAULT (_LESENSE_PERCTRL_DACSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE (_LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE << 6) /**< Shifted mode FULLCYCLE for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE (_LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE << 6) /**< Shifted mode HALFCYCLE for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACCONVTRIG (0x1UL << 8) /**< DAC conversion trigger configuration */ -#define _LESENSE_PERCTRL_DACCONVTRIG_SHIFT 8 /**< Shift value for LESENSE_DACCONVTRIG */ -#define _LESENSE_PERCTRL_DACCONVTRIG_MASK 0x100UL /**< Bit mask for LESENSE_DACCONVTRIG */ -#define _LESENSE_PERCTRL_DACCONVTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART 0x00000000UL /**< Mode CHANNELSTART for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_DACCONVTRIG_SCANSTART 0x00000001UL /**< Mode SCANSTART for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACCONVTRIG_DEFAULT (_LESENSE_PERCTRL_DACCONVTRIG_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART (_LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART << 8) /**< Shifted mode CHANNELSTART for LESENSE_PERCTRL*/ -#define LESENSE_PERCTRL_DACCONVTRIG_SCANSTART (_LESENSE_PERCTRL_DACCONVTRIG_SCANSTART << 8) /**< Shifted mode SCANSTART for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP0MODE (0x1UL << 20) /**< ACMP0 mode */ -#define _LESENSE_PERCTRL_ACMP0MODE_SHIFT 20 /**< Shift value for LESENSE_ACMP0MODE */ -#define _LESENSE_PERCTRL_ACMP0MODE_MASK 0x100000UL /**< Bit mask for LESENSE_ACMP0MODE */ -#define _LESENSE_PERCTRL_ACMP0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_ACMP0MODE_MUX 0x00000000UL /**< Mode MUX for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_ACMP0MODE_MUXTHRES 0x00000001UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP0MODE_DEFAULT (_LESENSE_PERCTRL_ACMP0MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP0MODE_MUX (_LESENSE_PERCTRL_ACMP0MODE_MUX << 20) /**< Shifted mode MUX for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP0MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP0MODE_MUXTHRES << 20) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP1MODE (0x1UL << 22) /**< ACMP1 mode */ -#define _LESENSE_PERCTRL_ACMP1MODE_SHIFT 22 /**< Shift value for LESENSE_ACMP1MODE */ -#define _LESENSE_PERCTRL_ACMP1MODE_MASK 0x400000UL /**< Bit mask for LESENSE_ACMP1MODE */ -#define _LESENSE_PERCTRL_ACMP1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_ACMP1MODE_MUX 0x00000000UL /**< Mode MUX for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_ACMP1MODE_MUXTHRES 0x00000001UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP1MODE_DEFAULT (_LESENSE_PERCTRL_ACMP1MODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP1MODE_MUX (_LESENSE_PERCTRL_ACMP1MODE_MUX << 22) /**< Shifted mode MUX for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP1MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP1MODE_MUXTHRES << 22) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP0INV (0x1UL << 24) /**< Invert analog comparator 0 output */ -#define _LESENSE_PERCTRL_ACMP0INV_SHIFT 24 /**< Shift value for LESENSE_ACMP0INV */ -#define _LESENSE_PERCTRL_ACMP0INV_MASK 0x1000000UL /**< Bit mask for LESENSE_ACMP0INV */ -#define _LESENSE_PERCTRL_ACMP0INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP0INV_DEFAULT (_LESENSE_PERCTRL_ACMP0INV_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP1INV (0x1UL << 25) /**< Invert analog comparator 1 output */ -#define _LESENSE_PERCTRL_ACMP1INV_SHIFT 25 /**< Shift value for LESENSE_ACMP1INV */ -#define _LESENSE_PERCTRL_ACMP1INV_MASK 0x2000000UL /**< Bit mask for LESENSE_ACMP1INV */ -#define _LESENSE_PERCTRL_ACMP1INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP1INV_DEFAULT (_LESENSE_PERCTRL_ACMP1INV_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_MASK 0x03500144UL /**< Mask for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA (0x1UL << 2) /**< DAC CH0 data selection. */ +#define _LESENSE_PERCTRL_DACCH0DATA_SHIFT 2 /**< Shift value for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_MASK 0x4UL /**< Bit mask for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DEFAULT (_LESENSE_PERCTRL_DACCH0DATA_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DACDATA (_LESENSE_PERCTRL_DACCH0DATA_DACDATA << 2) /**< Shifted mode DACDATA for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_THRES (_LESENSE_PERCTRL_DACCH0DATA_THRES << 2) /**< Shifted mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP (0x1UL << 6) /**< DAC startup configuration */ +#define _LESENSE_PERCTRL_DACSTARTUP_SHIFT 6 /**< Shift value for LESENSE_DACSTARTUP */ +#define _LESENSE_PERCTRL_DACSTARTUP_MASK 0x40UL /**< Bit mask for LESENSE_DACSTARTUP */ +#define _LESENSE_PERCTRL_DACSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE 0x00000000UL /**< Mode FULLCYCLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE 0x00000001UL /**< Mode HALFCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_DEFAULT (_LESENSE_PERCTRL_DACSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE (_LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE << 6) /**< Shifted mode FULLCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE (_LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE << 6) /**< Shifted mode HALFCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG (0x1UL << 8) /**< DAC conversion trigger configuration */ +#define _LESENSE_PERCTRL_DACCONVTRIG_SHIFT 8 /**< Shift value for LESENSE_DACCONVTRIG */ +#define _LESENSE_PERCTRL_DACCONVTRIG_MASK 0x100UL /**< Bit mask for LESENSE_DACCONVTRIG */ +#define _LESENSE_PERCTRL_DACCONVTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART 0x00000000UL /**< Mode CHANNELSTART for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCONVTRIG_SCANSTART 0x00000001UL /**< Mode SCANSTART for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_DEFAULT (_LESENSE_PERCTRL_DACCONVTRIG_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART (_LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART << 8) /**< Shifted mode CHANNELSTART for LESENSE_PERCTRL*/ +#define LESENSE_PERCTRL_DACCONVTRIG_SCANSTART (_LESENSE_PERCTRL_DACCONVTRIG_SCANSTART << 8) /**< Shifted mode SCANSTART for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE (0x1UL << 20) /**< ACMP0 mode */ +#define _LESENSE_PERCTRL_ACMP0MODE_SHIFT 20 /**< Shift value for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_MASK 0x100000UL /**< Bit mask for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUX 0x00000000UL /**< Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUXTHRES 0x00000001UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_DEFAULT (_LESENSE_PERCTRL_ACMP0MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUX (_LESENSE_PERCTRL_ACMP0MODE_MUX << 20) /**< Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP0MODE_MUXTHRES << 20) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE (0x1UL << 22) /**< ACMP1 mode */ +#define _LESENSE_PERCTRL_ACMP1MODE_SHIFT 22 /**< Shift value for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_MASK 0x400000UL /**< Bit mask for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUX 0x00000000UL /**< Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUXTHRES 0x00000001UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_DEFAULT (_LESENSE_PERCTRL_ACMP1MODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUX (_LESENSE_PERCTRL_ACMP1MODE_MUX << 22) /**< Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP1MODE_MUXTHRES << 22) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0INV (0x1UL << 24) /**< Invert analog comparator 0 output */ +#define _LESENSE_PERCTRL_ACMP0INV_SHIFT 24 /**< Shift value for LESENSE_ACMP0INV */ +#define _LESENSE_PERCTRL_ACMP0INV_MASK 0x1000000UL /**< Bit mask for LESENSE_ACMP0INV */ +#define _LESENSE_PERCTRL_ACMP0INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0INV_DEFAULT (_LESENSE_PERCTRL_ACMP0INV_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1INV (0x1UL << 25) /**< Invert analog comparator 1 output */ +#define _LESENSE_PERCTRL_ACMP1INV_SHIFT 25 /**< Shift value for LESENSE_ACMP1INV */ +#define _LESENSE_PERCTRL_ACMP1INV_MASK 0x2000000UL /**< Bit mask for LESENSE_ACMP1INV */ +#define _LESENSE_PERCTRL_ACMP1INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1INV_DEFAULT (_LESENSE_PERCTRL_ACMP1INV_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ /* Bit fields for LESENSE DECCTRL */ -#define _LESENSE_DECCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECCTRL */ -#define _LESENSE_DECCTRL_MASK 0x000000FDUL /**< Mask for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_DECDIS (0x1UL << 0) /**< Disable the decoder */ -#define _LESENSE_DECCTRL_DECDIS_SHIFT 0 /**< Shift value for LESENSE_DECDIS */ -#define _LESENSE_DECCTRL_DECDIS_MASK 0x1UL /**< Bit mask for LESENSE_DECDIS */ -#define _LESENSE_DECCTRL_DECDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_DECDIS_DEFAULT (_LESENSE_DECCTRL_DECDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_INTMAP (0x1UL << 2) /**< Enable decoder to channel interrupt map */ -#define _LESENSE_DECCTRL_INTMAP_SHIFT 2 /**< Shift value for LESENSE_INTMAP */ -#define _LESENSE_DECCTRL_INTMAP_MASK 0x4UL /**< Bit mask for LESENSE_INTMAP */ -#define _LESENSE_DECCTRL_INTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_INTMAP_DEFAULT (_LESENSE_DECCTRL_INTMAP_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_HYSTPRS0 (0x1UL << 3) /**< Enable decoder hysteresis on PRS0 output */ -#define _LESENSE_DECCTRL_HYSTPRS0_SHIFT 3 /**< Shift value for LESENSE_HYSTPRS0 */ -#define _LESENSE_DECCTRL_HYSTPRS0_MASK 0x8UL /**< Bit mask for LESENSE_HYSTPRS0 */ -#define _LESENSE_DECCTRL_HYSTPRS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_HYSTPRS0_DEFAULT (_LESENSE_DECCTRL_HYSTPRS0_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_HYSTPRS1 (0x1UL << 4) /**< Enable decoder hysteresis on PRS1 output */ -#define _LESENSE_DECCTRL_HYSTPRS1_SHIFT 4 /**< Shift value for LESENSE_HYSTPRS1 */ -#define _LESENSE_DECCTRL_HYSTPRS1_MASK 0x10UL /**< Bit mask for LESENSE_HYSTPRS1 */ -#define _LESENSE_DECCTRL_HYSTPRS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_HYSTPRS1_DEFAULT (_LESENSE_DECCTRL_HYSTPRS1_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_HYSTPRS2 (0x1UL << 5) /**< Enable decoder hysteresis on PRS2 output */ -#define _LESENSE_DECCTRL_HYSTPRS2_SHIFT 5 /**< Shift value for LESENSE_HYSTPRS2 */ -#define _LESENSE_DECCTRL_HYSTPRS2_MASK 0x20UL /**< Bit mask for LESENSE_HYSTPRS2 */ -#define _LESENSE_DECCTRL_HYSTPRS2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_HYSTPRS2_DEFAULT (_LESENSE_DECCTRL_HYSTPRS2_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_HYSTIRQ (0x1UL << 6) /**< Enable decoder hysteresis on interrupt r */ -#define _LESENSE_DECCTRL_HYSTIRQ_SHIFT 6 /**< Shift value for LESENSE_HYSTIRQ */ -#define _LESENSE_DECCTRL_HYSTIRQ_MASK 0x40UL /**< Bit mask for LESENSE_HYSTIRQ */ -#define _LESENSE_DECCTRL_HYSTIRQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_HYSTIRQ_DEFAULT (_LESENSE_DECCTRL_HYSTIRQ_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_PRSCNT (0x1UL << 7) /**< Enable count mode on decoder PRS channel */ -#define _LESENSE_DECCTRL_PRSCNT_SHIFT 7 /**< Shift value for LESENSE_PRSCNT */ -#define _LESENSE_DECCTRL_PRSCNT_MASK 0x80UL /**< Bit mask for LESENSE_PRSCNT */ -#define _LESENSE_DECCTRL_PRSCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_PRSCNT_DEFAULT (_LESENSE_DECCTRL_PRSCNT_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_MASK 0x000000FDUL /**< Mask for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_DECDIS (0x1UL << 0) /**< Disable the decoder */ +#define _LESENSE_DECCTRL_DECDIS_SHIFT 0 /**< Shift value for LESENSE_DECDIS */ +#define _LESENSE_DECCTRL_DECDIS_MASK 0x1UL /**< Bit mask for LESENSE_DECDIS */ +#define _LESENSE_DECCTRL_DECDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_DECDIS_DEFAULT (_LESENSE_DECCTRL_DECDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP (0x1UL << 2) /**< Enable decoder to channel interrupt map */ +#define _LESENSE_DECCTRL_INTMAP_SHIFT 2 /**< Shift value for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_MASK 0x4UL /**< Bit mask for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP_DEFAULT (_LESENSE_DECCTRL_INTMAP_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0 (0x1UL << 3) /**< Enable decoder hysteresis on PRS0 output */ +#define _LESENSE_DECCTRL_HYSTPRS0_SHIFT 3 /**< Shift value for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_MASK 0x8UL /**< Bit mask for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0_DEFAULT (_LESENSE_DECCTRL_HYSTPRS0_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1 (0x1UL << 4) /**< Enable decoder hysteresis on PRS1 output */ +#define _LESENSE_DECCTRL_HYSTPRS1_SHIFT 4 /**< Shift value for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_MASK 0x10UL /**< Bit mask for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1_DEFAULT (_LESENSE_DECCTRL_HYSTPRS1_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2 (0x1UL << 5) /**< Enable decoder hysteresis on PRS2 output */ +#define _LESENSE_DECCTRL_HYSTPRS2_SHIFT 5 /**< Shift value for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_MASK 0x20UL /**< Bit mask for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2_DEFAULT (_LESENSE_DECCTRL_HYSTPRS2_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ (0x1UL << 6) /**< Enable decoder hysteresis on interrupt r */ +#define _LESENSE_DECCTRL_HYSTIRQ_SHIFT 6 /**< Shift value for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_MASK 0x40UL /**< Bit mask for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ_DEFAULT (_LESENSE_DECCTRL_HYSTIRQ_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT (0x1UL << 7) /**< Enable count mode on decoder PRS channel */ +#define _LESENSE_DECCTRL_PRSCNT_SHIFT 7 /**< Shift value for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_MASK 0x80UL /**< Bit mask for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT_DEFAULT (_LESENSE_DECCTRL_PRSCNT_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ /* Bit fields for LESENSE EVALCTRL */ -#define _LESENSE_EVALCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_EVALCTRL */ -#define _LESENSE_EVALCTRL_MASK 0x0000FFFFUL /**< Mask for LESENSE_EVALCTRL */ -#define _LESENSE_EVALCTRL_WINSIZE_SHIFT 0 /**< Shift value for LESENSE_WINSIZE */ -#define _LESENSE_EVALCTRL_WINSIZE_MASK 0xFFFFUL /**< Bit mask for LESENSE_WINSIZE */ -#define _LESENSE_EVALCTRL_WINSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EVALCTRL */ -#define LESENSE_EVALCTRL_WINSIZE_DEFAULT (_LESENSE_EVALCTRL_WINSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_MASK 0x0000FFFFUL /**< Mask for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_WINSIZE_SHIFT 0 /**< Shift value for LESENSE_WINSIZE */ +#define _LESENSE_EVALCTRL_WINSIZE_MASK 0xFFFFUL /**< Bit mask for LESENSE_WINSIZE */ +#define _LESENSE_EVALCTRL_WINSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EVALCTRL */ +#define LESENSE_EVALCTRL_WINSIZE_DEFAULT (_LESENSE_EVALCTRL_WINSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_EVALCTRL */ /* Bit fields for LESENSE PRSCTRL */ -#define _LESENSE_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PRSCTRL */ -#define _LESENSE_PRSCTRL_MASK 0x00011F1FUL /**< Mask for LESENSE_PRSCTRL */ -#define _LESENSE_PRSCTRL_DECCMPVAL_SHIFT 0 /**< Shift value for LESENSE_DECCMPVAL */ -#define _LESENSE_PRSCTRL_DECCMPVAL_MASK 0x1FUL /**< Bit mask for LESENSE_DECCMPVAL */ -#define _LESENSE_PRSCTRL_DECCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ -#define LESENSE_PRSCTRL_DECCMPVAL_DEFAULT (_LESENSE_PRSCTRL_DECCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ -#define _LESENSE_PRSCTRL_DECCMPMASK_SHIFT 8 /**< Shift value for LESENSE_DECCMPMASK */ -#define _LESENSE_PRSCTRL_DECCMPMASK_MASK 0x1F00UL /**< Bit mask for LESENSE_DECCMPMASK */ -#define _LESENSE_PRSCTRL_DECCMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ -#define LESENSE_PRSCTRL_DECCMPMASK_DEFAULT (_LESENSE_PRSCTRL_DECCMPMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ -#define LESENSE_PRSCTRL_DECCMPEN (0x1UL << 16) /**< Enable PRS output DECCMP */ -#define _LESENSE_PRSCTRL_DECCMPEN_SHIFT 16 /**< Shift value for LESENSE_DECCMPEN */ -#define _LESENSE_PRSCTRL_DECCMPEN_MASK 0x10000UL /**< Bit mask for LESENSE_DECCMPEN */ -#define _LESENSE_PRSCTRL_DECCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ -#define LESENSE_PRSCTRL_DECCMPEN_DEFAULT (_LESENSE_PRSCTRL_DECCMPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_MASK 0x00011F1FUL /**< Mask for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_SHIFT 0 /**< Shift value for LESENSE_DECCMPVAL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_MASK 0x1FUL /**< Bit mask for LESENSE_DECCMPVAL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPVAL_DEFAULT (_LESENSE_PRSCTRL_DECCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_DECCMPMASK_SHIFT 8 /**< Shift value for LESENSE_DECCMPMASK */ +#define _LESENSE_PRSCTRL_DECCMPMASK_MASK 0x1F00UL /**< Bit mask for LESENSE_DECCMPMASK */ +#define _LESENSE_PRSCTRL_DECCMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPMASK_DEFAULT (_LESENSE_PRSCTRL_DECCMPMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPEN (0x1UL << 16) /**< Enable PRS output DECCMP */ +#define _LESENSE_PRSCTRL_DECCMPEN_SHIFT 16 /**< Shift value for LESENSE_DECCMPEN */ +#define _LESENSE_PRSCTRL_DECCMPEN_MASK 0x10000UL /**< Bit mask for LESENSE_DECCMPEN */ +#define _LESENSE_PRSCTRL_DECCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPEN_DEFAULT (_LESENSE_PRSCTRL_DECCMPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ /* Bit fields for LESENSE CMD */ -#define _LESENSE_CMD_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CMD */ -#define _LESENSE_CMD_MASK 0x0000000FUL /**< Mask for LESENSE_CMD */ -#define LESENSE_CMD_START (0x1UL << 0) /**< Start scanning of sensors. */ -#define _LESENSE_CMD_START_SHIFT 0 /**< Shift value for LESENSE_START */ -#define _LESENSE_CMD_START_MASK 0x1UL /**< Bit mask for LESENSE_START */ -#define _LESENSE_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ -#define LESENSE_CMD_START_DEFAULT (_LESENSE_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CMD */ -#define LESENSE_CMD_STOP (0x1UL << 1) /**< Stop scanning of sensors */ -#define _LESENSE_CMD_STOP_SHIFT 1 /**< Shift value for LESENSE_STOP */ -#define _LESENSE_CMD_STOP_MASK 0x2UL /**< Bit mask for LESENSE_STOP */ -#define _LESENSE_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ -#define LESENSE_CMD_STOP_DEFAULT (_LESENSE_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_CMD */ -#define LESENSE_CMD_DECODE (0x1UL << 2) /**< Start decoder */ -#define _LESENSE_CMD_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */ -#define _LESENSE_CMD_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */ -#define _LESENSE_CMD_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ -#define LESENSE_CMD_DECODE_DEFAULT (_LESENSE_CMD_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CMD */ -#define LESENSE_CMD_CLEARBUF (0x1UL << 3) /**< Clear result buffer */ -#define _LESENSE_CMD_CLEARBUF_SHIFT 3 /**< Shift value for LESENSE_CLEARBUF */ -#define _LESENSE_CMD_CLEARBUF_MASK 0x8UL /**< Bit mask for LESENSE_CLEARBUF */ -#define _LESENSE_CMD_CLEARBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ -#define LESENSE_CMD_CLEARBUF_DEFAULT (_LESENSE_CMD_CLEARBUF_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define _LESENSE_CMD_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CMD */ +#define _LESENSE_CMD_MASK 0x0000000FUL /**< Mask for LESENSE_CMD */ +#define LESENSE_CMD_START (0x1UL << 0) /**< Start scanning of sensors. */ +#define _LESENSE_CMD_START_SHIFT 0 /**< Shift value for LESENSE_START */ +#define _LESENSE_CMD_START_MASK 0x1UL /**< Bit mask for LESENSE_START */ +#define _LESENSE_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_START_DEFAULT (_LESENSE_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP (0x1UL << 1) /**< Stop scanning of sensors */ +#define _LESENSE_CMD_STOP_SHIFT 1 /**< Shift value for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_MASK 0x2UL /**< Bit mask for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP_DEFAULT (_LESENSE_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE (0x1UL << 2) /**< Start decoder */ +#define _LESENSE_CMD_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE_DEFAULT (_LESENSE_CMD_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF (0x1UL << 3) /**< Clear result buffer */ +#define _LESENSE_CMD_CLEARBUF_SHIFT 3 /**< Shift value for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_MASK 0x8UL /**< Bit mask for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF_DEFAULT (_LESENSE_CMD_CLEARBUF_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_CMD */ /* Bit fields for LESENSE CHEN */ -#define _LESENSE_CHEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CHEN */ -#define _LESENSE_CHEN_MASK 0x0000FFFFUL /**< Mask for LESENSE_CHEN */ -#define _LESENSE_CHEN_CHEN_SHIFT 0 /**< Shift value for LESENSE_CHEN */ -#define _LESENSE_CHEN_CHEN_MASK 0xFFFFUL /**< Bit mask for LESENSE_CHEN */ -#define _LESENSE_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CHEN */ -#define LESENSE_CHEN_CHEN_DEFAULT (_LESENSE_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CHEN */ +#define _LESENSE_CHEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CHEN */ +#define _LESENSE_CHEN_MASK 0x0000FFFFUL /**< Mask for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_SHIFT 0 /**< Shift value for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_MASK 0xFFFFUL /**< Bit mask for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CHEN */ +#define LESENSE_CHEN_CHEN_DEFAULT (_LESENSE_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CHEN */ /* Bit fields for LESENSE SCANRES */ -#define _LESENSE_SCANRES_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SCANRES */ -#define _LESENSE_SCANRES_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_SCANRES */ -#define _LESENSE_SCANRES_SCANRES_SHIFT 0 /**< Shift value for LESENSE_SCANRES */ -#define _LESENSE_SCANRES_SCANRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_SCANRES */ -#define _LESENSE_SCANRES_SCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ -#define LESENSE_SCANRES_SCANRES_DEFAULT (_LESENSE_SCANRES_SCANRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ -#define _LESENSE_SCANRES_STEPDIR_SHIFT 16 /**< Shift value for LESENSE_STEPDIR */ -#define _LESENSE_SCANRES_STEPDIR_MASK 0xFFFF0000UL /**< Bit mask for LESENSE_STEPDIR */ -#define _LESENSE_SCANRES_STEPDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ -#define LESENSE_SCANRES_STEPDIR_DEFAULT (_LESENSE_SCANRES_STEPDIR_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_SHIFT 0 /**< Shift value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ +#define LESENSE_SCANRES_SCANRES_DEFAULT (_LESENSE_SCANRES_SCANRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_STEPDIR_SHIFT 16 /**< Shift value for LESENSE_STEPDIR */ +#define _LESENSE_SCANRES_STEPDIR_MASK 0xFFFF0000UL /**< Bit mask for LESENSE_STEPDIR */ +#define _LESENSE_SCANRES_STEPDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ +#define LESENSE_SCANRES_STEPDIR_DEFAULT (_LESENSE_SCANRES_STEPDIR_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ /* Bit fields for LESENSE STATUS */ -#define _LESENSE_STATUS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_STATUS */ -#define _LESENSE_STATUS_MASK 0x0000007BUL /**< Mask for LESENSE_STATUS */ -#define LESENSE_STATUS_RESFIFOV (0x1UL << 0) /**< Result fifo valid */ -#define _LESENSE_STATUS_RESFIFOV_SHIFT 0 /**< Shift value for LESENSE_RESFIFOV */ -#define _LESENSE_STATUS_RESFIFOV_MASK 0x1UL /**< Bit mask for LESENSE_RESFIFOV */ -#define _LESENSE_STATUS_RESFIFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_RESFIFOV_DEFAULT (_LESENSE_STATUS_RESFIFOV_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_RESFIFOFULL (0x1UL << 1) /**< Result fifo full */ -#define _LESENSE_STATUS_RESFIFOFULL_SHIFT 1 /**< Shift value for LESENSE_RESFIFOFULL */ -#define _LESENSE_STATUS_RESFIFOFULL_MASK 0x2UL /**< Bit mask for LESENSE_RESFIFOFULL */ -#define _LESENSE_STATUS_RESFIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_RESFIFOFULL_DEFAULT (_LESENSE_STATUS_RESFIFOFULL_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_SCANACTIVE (0x1UL << 3) /**< LESENSE scan active */ -#define _LESENSE_STATUS_SCANACTIVE_SHIFT 3 /**< Shift value for LESENSE_SCANACTIVE */ -#define _LESENSE_STATUS_SCANACTIVE_MASK 0x8UL /**< Bit mask for LESENSE_SCANACTIVE */ -#define _LESENSE_STATUS_SCANACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_SCANACTIVE_DEFAULT (_LESENSE_STATUS_SCANACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_RUNNING (0x1UL << 4) /**< LESENSE periodic counter running */ -#define _LESENSE_STATUS_RUNNING_SHIFT 4 /**< Shift value for LESENSE_RUNNING */ -#define _LESENSE_STATUS_RUNNING_MASK 0x10UL /**< Bit mask for LESENSE_RUNNING */ -#define _LESENSE_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_RUNNING_DEFAULT (_LESENSE_STATUS_RUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_READBUSY (0x1UL << 5) /**< FIFO Read Busy */ -#define _LESENSE_STATUS_READBUSY_SHIFT 5 /**< Shift value for LESENSE_READBUSY */ -#define _LESENSE_STATUS_READBUSY_MASK 0x20UL /**< Bit mask for LESENSE_READBUSY */ -#define _LESENSE_STATUS_READBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_READBUSY_DEFAULT (_LESENSE_STATUS_READBUSY_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_FLUSHING (0x1UL << 6) /**< FIFO Flushing */ -#define _LESENSE_STATUS_FLUSHING_SHIFT 6 /**< Shift value for LESENSE_FLUSHING */ -#define _LESENSE_STATUS_FLUSHING_MASK 0x40UL /**< Bit mask for LESENSE_FLUSHING */ -#define _LESENSE_STATUS_FLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_FLUSHING_DEFAULT (_LESENSE_STATUS_FLUSHING_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define _LESENSE_STATUS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_STATUS */ +#define _LESENSE_STATUS_MASK 0x0000007BUL /**< Mask for LESENSE_STATUS */ +#define LESENSE_STATUS_RESFIFOV (0x1UL << 0) /**< Result fifo valid */ +#define _LESENSE_STATUS_RESFIFOV_SHIFT 0 /**< Shift value for LESENSE_RESFIFOV */ +#define _LESENSE_STATUS_RESFIFOV_MASK 0x1UL /**< Bit mask for LESENSE_RESFIFOV */ +#define _LESENSE_STATUS_RESFIFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RESFIFOV_DEFAULT (_LESENSE_STATUS_RESFIFOV_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RESFIFOFULL (0x1UL << 1) /**< Result fifo full */ +#define _LESENSE_STATUS_RESFIFOFULL_SHIFT 1 /**< Shift value for LESENSE_RESFIFOFULL */ +#define _LESENSE_STATUS_RESFIFOFULL_MASK 0x2UL /**< Bit mask for LESENSE_RESFIFOFULL */ +#define _LESENSE_STATUS_RESFIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RESFIFOFULL_DEFAULT (_LESENSE_STATUS_RESFIFOFULL_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE (0x1UL << 3) /**< LESENSE scan active */ +#define _LESENSE_STATUS_SCANACTIVE_SHIFT 3 /**< Shift value for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_MASK 0x8UL /**< Bit mask for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE_DEFAULT (_LESENSE_STATUS_SCANACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING (0x1UL << 4) /**< LESENSE periodic counter running */ +#define _LESENSE_STATUS_RUNNING_SHIFT 4 /**< Shift value for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_MASK 0x10UL /**< Bit mask for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING_DEFAULT (_LESENSE_STATUS_RUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_READBUSY (0x1UL << 5) /**< FIFO Read Busy */ +#define _LESENSE_STATUS_READBUSY_SHIFT 5 /**< Shift value for LESENSE_READBUSY */ +#define _LESENSE_STATUS_READBUSY_MASK 0x20UL /**< Bit mask for LESENSE_READBUSY */ +#define _LESENSE_STATUS_READBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_READBUSY_DEFAULT (_LESENSE_STATUS_READBUSY_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_FLUSHING (0x1UL << 6) /**< FIFO Flushing */ +#define _LESENSE_STATUS_FLUSHING_SHIFT 6 /**< Shift value for LESENSE_FLUSHING */ +#define _LESENSE_STATUS_FLUSHING_MASK 0x40UL /**< Bit mask for LESENSE_FLUSHING */ +#define _LESENSE_STATUS_FLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_FLUSHING_DEFAULT (_LESENSE_STATUS_FLUSHING_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_STATUS */ /* Bit fields for LESENSE RESCOUNT */ -#define _LESENSE_RESCOUNT_RESETVALUE 0x00000000UL /**< Default value for LESENSE_RESCOUNT */ -#define _LESENSE_RESCOUNT_MASK 0x0000001FUL /**< Mask for LESENSE_RESCOUNT */ -#define _LESENSE_RESCOUNT_COUNT_SHIFT 0 /**< Shift value for LESENSE_COUNT */ -#define _LESENSE_RESCOUNT_COUNT_MASK 0x1FUL /**< Bit mask for LESENSE_COUNT */ -#define _LESENSE_RESCOUNT_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_RESCOUNT */ -#define LESENSE_RESCOUNT_COUNT_DEFAULT (_LESENSE_RESCOUNT_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_RESCOUNT */ +#define _LESENSE_RESCOUNT_RESETVALUE 0x00000000UL /**< Default value for LESENSE_RESCOUNT */ +#define _LESENSE_RESCOUNT_MASK 0x0000001FUL /**< Mask for LESENSE_RESCOUNT */ +#define _LESENSE_RESCOUNT_COUNT_SHIFT 0 /**< Shift value for LESENSE_COUNT */ +#define _LESENSE_RESCOUNT_COUNT_MASK 0x1FUL /**< Bit mask for LESENSE_COUNT */ +#define _LESENSE_RESCOUNT_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_RESCOUNT */ +#define LESENSE_RESCOUNT_COUNT_DEFAULT (_LESENSE_RESCOUNT_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_RESCOUNT */ /* Bit fields for LESENSE RESFIFO */ -#define _LESENSE_RESFIFO_RESETVALUE 0x00000000UL /**< Default value for LESENSE_RESFIFO */ -#define _LESENSE_RESFIFO_MASK 0x000FFFFFUL /**< Mask for LESENSE_RESFIFO */ -#define _LESENSE_RESFIFO_BUFDATASRC_SHIFT 0 /**< Shift value for LESENSE_BUFDATASRC */ -#define _LESENSE_RESFIFO_BUFDATASRC_MASK 0xFFFFFUL /**< Bit mask for LESENSE_BUFDATASRC */ -#define _LESENSE_RESFIFO_BUFDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_RESFIFO */ -#define LESENSE_RESFIFO_BUFDATASRC_DEFAULT (_LESENSE_RESFIFO_BUFDATASRC_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_RESFIFO */ +#define _LESENSE_RESFIFO_RESETVALUE 0x00000000UL /**< Default value for LESENSE_RESFIFO */ +#define _LESENSE_RESFIFO_MASK 0x000FFFFFUL /**< Mask for LESENSE_RESFIFO */ +#define _LESENSE_RESFIFO_BUFDATASRC_SHIFT 0 /**< Shift value for LESENSE_BUFDATASRC */ +#define _LESENSE_RESFIFO_BUFDATASRC_MASK 0xFFFFFUL /**< Bit mask for LESENSE_BUFDATASRC */ +#define _LESENSE_RESFIFO_BUFDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_RESFIFO */ +#define LESENSE_RESFIFO_BUFDATASRC_DEFAULT (_LESENSE_RESFIFO_BUFDATASRC_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_RESFIFO */ /* Bit fields for LESENSE CURCH */ -#define _LESENSE_CURCH_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CURCH */ -#define _LESENSE_CURCH_MASK 0x0000000FUL /**< Mask for LESENSE_CURCH */ -#define _LESENSE_CURCH_CURCH_SHIFT 0 /**< Shift value for LESENSE_CURCH */ -#define _LESENSE_CURCH_CURCH_MASK 0xFUL /**< Bit mask for LESENSE_CURCH */ -#define _LESENSE_CURCH_CURCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CURCH */ -#define LESENSE_CURCH_CURCH_DEFAULT (_LESENSE_CURCH_CURCH_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CURCH */ +#define _LESENSE_CURCH_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CURCH */ +#define _LESENSE_CURCH_MASK 0x0000000FUL /**< Mask for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_SHIFT 0 /**< Shift value for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_MASK 0xFUL /**< Bit mask for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CURCH */ +#define LESENSE_CURCH_CURCH_DEFAULT (_LESENSE_CURCH_CURCH_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CURCH */ /* Bit fields for LESENSE DECSTATE */ -#define _LESENSE_DECSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECSTATE */ -#define _LESENSE_DECSTATE_MASK 0x0000001FUL /**< Mask for LESENSE_DECSTATE */ -#define _LESENSE_DECSTATE_DECSTATE_SHIFT 0 /**< Shift value for LESENSE_DECSTATE */ -#define _LESENSE_DECSTATE_DECSTATE_MASK 0x1FUL /**< Bit mask for LESENSE_DECSTATE */ -#define _LESENSE_DECSTATE_DECSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECSTATE */ -#define LESENSE_DECSTATE_DECSTATE_DEFAULT (_LESENSE_DECSTATE_DECSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_MASK 0x0000001FUL /**< Mask for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_SHIFT 0 /**< Shift value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_MASK 0x1FUL /**< Bit mask for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECSTATE */ +#define LESENSE_DECSTATE_DECSTATE_DEFAULT (_LESENSE_DECSTATE_DECSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECSTATE */ /* Bit fields for LESENSE SENSORSTATE */ -#define _LESENSE_SENSORSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SENSORSTATE */ -#define _LESENSE_SENSORSTATE_MASK 0x0000000FUL /**< Mask for LESENSE_SENSORSTATE */ -#define _LESENSE_SENSORSTATE_SENSORSTATE_SHIFT 0 /**< Shift value for LESENSE_SENSORSTATE */ -#define _LESENSE_SENSORSTATE_SENSORSTATE_MASK 0xFUL /**< Bit mask for LESENSE_SENSORSTATE */ -#define _LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SENSORSTATE */ -#define LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT (_LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SENSORSTATE*/ +#define _LESENSE_SENSORSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_MASK 0x0000000FUL /**< Mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_SHIFT 0 /**< Shift value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_MASK 0xFUL /**< Bit mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SENSORSTATE */ +#define LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT (_LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SENSORSTATE*/ /* Bit fields for LESENSE IDLECONF */ -#define _LESENSE_IDLECONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE0_SHIFT 0 /**< Shift value for LESENSE_CHIDLE0 */ -#define _LESENSE_IDLECONF_CHIDLE0_MASK 0x3UL /**< Bit mask for LESENSE_CHIDLE0 */ -#define _LESENSE_IDLECONF_CHIDLE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE0_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE0_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE0_DEFAULT (_LESENSE_IDLECONF_CHIDLE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE0_DISABLE (_LESENSE_IDLECONF_CHIDLE0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE0_HIGH (_LESENSE_IDLECONF_CHIDLE0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE0_LOW (_LESENSE_IDLECONF_CHIDLE0_LOW << 0) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE0_DAC (_LESENSE_IDLECONF_CHIDLE0_DAC << 0) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE1_SHIFT 2 /**< Shift value for LESENSE_CHIDLE1 */ -#define _LESENSE_IDLECONF_CHIDLE1_MASK 0xCUL /**< Bit mask for LESENSE_CHIDLE1 */ -#define _LESENSE_IDLECONF_CHIDLE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE1_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE1_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE1_DEFAULT (_LESENSE_IDLECONF_CHIDLE1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE1_DISABLE (_LESENSE_IDLECONF_CHIDLE1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE1_HIGH (_LESENSE_IDLECONF_CHIDLE1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE1_LOW (_LESENSE_IDLECONF_CHIDLE1_LOW << 2) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE1_DAC (_LESENSE_IDLECONF_CHIDLE1_DAC << 2) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE2_SHIFT 4 /**< Shift value for LESENSE_CHIDLE2 */ -#define _LESENSE_IDLECONF_CHIDLE2_MASK 0x30UL /**< Bit mask for LESENSE_CHIDLE2 */ -#define _LESENSE_IDLECONF_CHIDLE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE2_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE2_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE2_DEFAULT (_LESENSE_IDLECONF_CHIDLE2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE2_DISABLE (_LESENSE_IDLECONF_CHIDLE2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE2_HIGH (_LESENSE_IDLECONF_CHIDLE2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE2_LOW (_LESENSE_IDLECONF_CHIDLE2_LOW << 4) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE2_DAC (_LESENSE_IDLECONF_CHIDLE2_DAC << 4) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE3_SHIFT 6 /**< Shift value for LESENSE_CHIDLE3 */ -#define _LESENSE_IDLECONF_CHIDLE3_MASK 0xC0UL /**< Bit mask for LESENSE_CHIDLE3 */ -#define _LESENSE_IDLECONF_CHIDLE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE3_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE3_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE3_DEFAULT (_LESENSE_IDLECONF_CHIDLE3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE3_DISABLE (_LESENSE_IDLECONF_CHIDLE3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE3_HIGH (_LESENSE_IDLECONF_CHIDLE3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE3_LOW (_LESENSE_IDLECONF_CHIDLE3_LOW << 6) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE3_DAC (_LESENSE_IDLECONF_CHIDLE3_DAC << 6) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE4_SHIFT 8 /**< Shift value for LESENSE_CHIDLE4 */ -#define _LESENSE_IDLECONF_CHIDLE4_MASK 0x300UL /**< Bit mask for LESENSE_CHIDLE4 */ -#define _LESENSE_IDLECONF_CHIDLE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE4_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE4_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE4_DEFAULT (_LESENSE_IDLECONF_CHIDLE4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE4_DISABLE (_LESENSE_IDLECONF_CHIDLE4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE4_HIGH (_LESENSE_IDLECONF_CHIDLE4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE4_LOW (_LESENSE_IDLECONF_CHIDLE4_LOW << 8) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE4_DAC (_LESENSE_IDLECONF_CHIDLE4_DAC << 8) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE5_SHIFT 10 /**< Shift value for LESENSE_CHIDLE5 */ -#define _LESENSE_IDLECONF_CHIDLE5_MASK 0xC00UL /**< Bit mask for LESENSE_CHIDLE5 */ -#define _LESENSE_IDLECONF_CHIDLE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE5_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE5_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE5_DEFAULT (_LESENSE_IDLECONF_CHIDLE5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE5_DISABLE (_LESENSE_IDLECONF_CHIDLE5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE5_HIGH (_LESENSE_IDLECONF_CHIDLE5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE5_LOW (_LESENSE_IDLECONF_CHIDLE5_LOW << 10) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE5_DAC (_LESENSE_IDLECONF_CHIDLE5_DAC << 10) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE6_SHIFT 12 /**< Shift value for LESENSE_CHIDLE6 */ -#define _LESENSE_IDLECONF_CHIDLE6_MASK 0x3000UL /**< Bit mask for LESENSE_CHIDLE6 */ -#define _LESENSE_IDLECONF_CHIDLE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE6_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE6_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE6_DEFAULT (_LESENSE_IDLECONF_CHIDLE6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE6_DISABLE (_LESENSE_IDLECONF_CHIDLE6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE6_HIGH (_LESENSE_IDLECONF_CHIDLE6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE6_LOW (_LESENSE_IDLECONF_CHIDLE6_LOW << 12) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE6_DAC (_LESENSE_IDLECONF_CHIDLE6_DAC << 12) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE7_SHIFT 14 /**< Shift value for LESENSE_CHIDLE7 */ -#define _LESENSE_IDLECONF_CHIDLE7_MASK 0xC000UL /**< Bit mask for LESENSE_CHIDLE7 */ -#define _LESENSE_IDLECONF_CHIDLE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE7_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE7_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE7_DEFAULT (_LESENSE_IDLECONF_CHIDLE7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE7_DISABLE (_LESENSE_IDLECONF_CHIDLE7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE7_HIGH (_LESENSE_IDLECONF_CHIDLE7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE7_LOW (_LESENSE_IDLECONF_CHIDLE7_LOW << 14) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE7_DAC (_LESENSE_IDLECONF_CHIDLE7_DAC << 14) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE8_SHIFT 16 /**< Shift value for LESENSE_CHIDLE8 */ -#define _LESENSE_IDLECONF_CHIDLE8_MASK 0x30000UL /**< Bit mask for LESENSE_CHIDLE8 */ -#define _LESENSE_IDLECONF_CHIDLE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE8_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE8_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE8_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE8_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE8_DEFAULT (_LESENSE_IDLECONF_CHIDLE8_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE8_DISABLE (_LESENSE_IDLECONF_CHIDLE8_DISABLE << 16) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE8_HIGH (_LESENSE_IDLECONF_CHIDLE8_HIGH << 16) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE8_LOW (_LESENSE_IDLECONF_CHIDLE8_LOW << 16) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE8_DAC (_LESENSE_IDLECONF_CHIDLE8_DAC << 16) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE9_SHIFT 18 /**< Shift value for LESENSE_CHIDLE9 */ -#define _LESENSE_IDLECONF_CHIDLE9_MASK 0xC0000UL /**< Bit mask for LESENSE_CHIDLE9 */ -#define _LESENSE_IDLECONF_CHIDLE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE9_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE9_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE9_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE9_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE9_DEFAULT (_LESENSE_IDLECONF_CHIDLE9_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE9_DISABLE (_LESENSE_IDLECONF_CHIDLE9_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE9_HIGH (_LESENSE_IDLECONF_CHIDLE9_HIGH << 18) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE9_LOW (_LESENSE_IDLECONF_CHIDLE9_LOW << 18) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE9_DAC (_LESENSE_IDLECONF_CHIDLE9_DAC << 18) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE10_SHIFT 20 /**< Shift value for LESENSE_CHIDLE10 */ -#define _LESENSE_IDLECONF_CHIDLE10_MASK 0x300000UL /**< Bit mask for LESENSE_CHIDLE10 */ -#define _LESENSE_IDLECONF_CHIDLE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE10_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE10_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE10_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE10_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE10_DEFAULT (_LESENSE_IDLECONF_CHIDLE10_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE10_DISABLE (_LESENSE_IDLECONF_CHIDLE10_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE10_HIGH (_LESENSE_IDLECONF_CHIDLE10_HIGH << 20) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE10_LOW (_LESENSE_IDLECONF_CHIDLE10_LOW << 20) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE10_DAC (_LESENSE_IDLECONF_CHIDLE10_DAC << 20) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE11_SHIFT 22 /**< Shift value for LESENSE_CHIDLE11 */ -#define _LESENSE_IDLECONF_CHIDLE11_MASK 0xC00000UL /**< Bit mask for LESENSE_CHIDLE11 */ -#define _LESENSE_IDLECONF_CHIDLE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE11_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE11_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE11_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE11_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE11_DEFAULT (_LESENSE_IDLECONF_CHIDLE11_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE11_DISABLE (_LESENSE_IDLECONF_CHIDLE11_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE11_HIGH (_LESENSE_IDLECONF_CHIDLE11_HIGH << 22) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE11_LOW (_LESENSE_IDLECONF_CHIDLE11_LOW << 22) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE11_DAC (_LESENSE_IDLECONF_CHIDLE11_DAC << 22) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE12_SHIFT 24 /**< Shift value for LESENSE_CHIDLE12 */ -#define _LESENSE_IDLECONF_CHIDLE12_MASK 0x3000000UL /**< Bit mask for LESENSE_CHIDLE12 */ -#define _LESENSE_IDLECONF_CHIDLE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE12_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE12_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE12_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE12_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE12_DEFAULT (_LESENSE_IDLECONF_CHIDLE12_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE12_DISABLE (_LESENSE_IDLECONF_CHIDLE12_DISABLE << 24) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE12_HIGH (_LESENSE_IDLECONF_CHIDLE12_HIGH << 24) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE12_LOW (_LESENSE_IDLECONF_CHIDLE12_LOW << 24) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE12_DAC (_LESENSE_IDLECONF_CHIDLE12_DAC << 24) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE13_SHIFT 26 /**< Shift value for LESENSE_CHIDLE13 */ -#define _LESENSE_IDLECONF_CHIDLE13_MASK 0xC000000UL /**< Bit mask for LESENSE_CHIDLE13 */ -#define _LESENSE_IDLECONF_CHIDLE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE13_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE13_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE13_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE13_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE13_DEFAULT (_LESENSE_IDLECONF_CHIDLE13_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE13_DISABLE (_LESENSE_IDLECONF_CHIDLE13_DISABLE << 26) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE13_HIGH (_LESENSE_IDLECONF_CHIDLE13_HIGH << 26) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE13_LOW (_LESENSE_IDLECONF_CHIDLE13_LOW << 26) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE13_DAC (_LESENSE_IDLECONF_CHIDLE13_DAC << 26) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE14_SHIFT 28 /**< Shift value for LESENSE_CHIDLE14 */ -#define _LESENSE_IDLECONF_CHIDLE14_MASK 0x30000000UL /**< Bit mask for LESENSE_CHIDLE14 */ -#define _LESENSE_IDLECONF_CHIDLE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE14_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE14_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE14_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE14_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE14_DEFAULT (_LESENSE_IDLECONF_CHIDLE14_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE14_DISABLE (_LESENSE_IDLECONF_CHIDLE14_DISABLE << 28) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE14_HIGH (_LESENSE_IDLECONF_CHIDLE14_HIGH << 28) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE14_LOW (_LESENSE_IDLECONF_CHIDLE14_LOW << 28) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE14_DAC (_LESENSE_IDLECONF_CHIDLE14_DAC << 28) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE15_SHIFT 30 /**< Shift value for LESENSE_CHIDLE15 */ -#define _LESENSE_IDLECONF_CHIDLE15_MASK 0xC0000000UL /**< Bit mask for LESENSE_CHIDLE15 */ -#define _LESENSE_IDLECONF_CHIDLE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE15_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE15_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE15_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE15_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE15_DEFAULT (_LESENSE_IDLECONF_CHIDLE15_DEFAULT << 30) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE15_DISABLE (_LESENSE_IDLECONF_CHIDLE15_DISABLE << 30) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE15_HIGH (_LESENSE_IDLECONF_CHIDLE15_HIGH << 30) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE15_LOW (_LESENSE_IDLECONF_CHIDLE15_LOW << 30) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE15_DAC (_LESENSE_IDLECONF_CHIDLE15_DAC << 30) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE0_SHIFT 0 /**< Shift value for LESENSE_CHIDLE0 */ +#define _LESENSE_IDLECONF_CHIDLE0_MASK 0x3UL /**< Bit mask for LESENSE_CHIDLE0 */ +#define _LESENSE_IDLECONF_CHIDLE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE0_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE0_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE0_DEFAULT (_LESENSE_IDLECONF_CHIDLE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE0_DISABLE (_LESENSE_IDLECONF_CHIDLE0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE0_HIGH (_LESENSE_IDLECONF_CHIDLE0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE0_LOW (_LESENSE_IDLECONF_CHIDLE0_LOW << 0) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE0_DAC (_LESENSE_IDLECONF_CHIDLE0_DAC << 0) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE1_SHIFT 2 /**< Shift value for LESENSE_CHIDLE1 */ +#define _LESENSE_IDLECONF_CHIDLE1_MASK 0xCUL /**< Bit mask for LESENSE_CHIDLE1 */ +#define _LESENSE_IDLECONF_CHIDLE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE1_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE1_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE1_DEFAULT (_LESENSE_IDLECONF_CHIDLE1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE1_DISABLE (_LESENSE_IDLECONF_CHIDLE1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE1_HIGH (_LESENSE_IDLECONF_CHIDLE1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE1_LOW (_LESENSE_IDLECONF_CHIDLE1_LOW << 2) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE1_DAC (_LESENSE_IDLECONF_CHIDLE1_DAC << 2) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE2_SHIFT 4 /**< Shift value for LESENSE_CHIDLE2 */ +#define _LESENSE_IDLECONF_CHIDLE2_MASK 0x30UL /**< Bit mask for LESENSE_CHIDLE2 */ +#define _LESENSE_IDLECONF_CHIDLE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE2_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE2_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE2_DEFAULT (_LESENSE_IDLECONF_CHIDLE2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE2_DISABLE (_LESENSE_IDLECONF_CHIDLE2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE2_HIGH (_LESENSE_IDLECONF_CHIDLE2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE2_LOW (_LESENSE_IDLECONF_CHIDLE2_LOW << 4) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE2_DAC (_LESENSE_IDLECONF_CHIDLE2_DAC << 4) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE3_SHIFT 6 /**< Shift value for LESENSE_CHIDLE3 */ +#define _LESENSE_IDLECONF_CHIDLE3_MASK 0xC0UL /**< Bit mask for LESENSE_CHIDLE3 */ +#define _LESENSE_IDLECONF_CHIDLE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE3_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE3_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE3_DEFAULT (_LESENSE_IDLECONF_CHIDLE3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE3_DISABLE (_LESENSE_IDLECONF_CHIDLE3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE3_HIGH (_LESENSE_IDLECONF_CHIDLE3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE3_LOW (_LESENSE_IDLECONF_CHIDLE3_LOW << 6) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE3_DAC (_LESENSE_IDLECONF_CHIDLE3_DAC << 6) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE4_SHIFT 8 /**< Shift value for LESENSE_CHIDLE4 */ +#define _LESENSE_IDLECONF_CHIDLE4_MASK 0x300UL /**< Bit mask for LESENSE_CHIDLE4 */ +#define _LESENSE_IDLECONF_CHIDLE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE4_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE4_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE4_DEFAULT (_LESENSE_IDLECONF_CHIDLE4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE4_DISABLE (_LESENSE_IDLECONF_CHIDLE4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE4_HIGH (_LESENSE_IDLECONF_CHIDLE4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE4_LOW (_LESENSE_IDLECONF_CHIDLE4_LOW << 8) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE4_DAC (_LESENSE_IDLECONF_CHIDLE4_DAC << 8) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE5_SHIFT 10 /**< Shift value for LESENSE_CHIDLE5 */ +#define _LESENSE_IDLECONF_CHIDLE5_MASK 0xC00UL /**< Bit mask for LESENSE_CHIDLE5 */ +#define _LESENSE_IDLECONF_CHIDLE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE5_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE5_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE5_DEFAULT (_LESENSE_IDLECONF_CHIDLE5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE5_DISABLE (_LESENSE_IDLECONF_CHIDLE5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE5_HIGH (_LESENSE_IDLECONF_CHIDLE5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE5_LOW (_LESENSE_IDLECONF_CHIDLE5_LOW << 10) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE5_DAC (_LESENSE_IDLECONF_CHIDLE5_DAC << 10) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE6_SHIFT 12 /**< Shift value for LESENSE_CHIDLE6 */ +#define _LESENSE_IDLECONF_CHIDLE6_MASK 0x3000UL /**< Bit mask for LESENSE_CHIDLE6 */ +#define _LESENSE_IDLECONF_CHIDLE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE6_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE6_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE6_DEFAULT (_LESENSE_IDLECONF_CHIDLE6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE6_DISABLE (_LESENSE_IDLECONF_CHIDLE6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE6_HIGH (_LESENSE_IDLECONF_CHIDLE6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE6_LOW (_LESENSE_IDLECONF_CHIDLE6_LOW << 12) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE6_DAC (_LESENSE_IDLECONF_CHIDLE6_DAC << 12) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE7_SHIFT 14 /**< Shift value for LESENSE_CHIDLE7 */ +#define _LESENSE_IDLECONF_CHIDLE7_MASK 0xC000UL /**< Bit mask for LESENSE_CHIDLE7 */ +#define _LESENSE_IDLECONF_CHIDLE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE7_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE7_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE7_DEFAULT (_LESENSE_IDLECONF_CHIDLE7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE7_DISABLE (_LESENSE_IDLECONF_CHIDLE7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE7_HIGH (_LESENSE_IDLECONF_CHIDLE7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE7_LOW (_LESENSE_IDLECONF_CHIDLE7_LOW << 14) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE7_DAC (_LESENSE_IDLECONF_CHIDLE7_DAC << 14) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE8_SHIFT 16 /**< Shift value for LESENSE_CHIDLE8 */ +#define _LESENSE_IDLECONF_CHIDLE8_MASK 0x30000UL /**< Bit mask for LESENSE_CHIDLE8 */ +#define _LESENSE_IDLECONF_CHIDLE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE8_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE8_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE8_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE8_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE8_DEFAULT (_LESENSE_IDLECONF_CHIDLE8_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE8_DISABLE (_LESENSE_IDLECONF_CHIDLE8_DISABLE << 16) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE8_HIGH (_LESENSE_IDLECONF_CHIDLE8_HIGH << 16) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE8_LOW (_LESENSE_IDLECONF_CHIDLE8_LOW << 16) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE8_DAC (_LESENSE_IDLECONF_CHIDLE8_DAC << 16) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE9_SHIFT 18 /**< Shift value for LESENSE_CHIDLE9 */ +#define _LESENSE_IDLECONF_CHIDLE9_MASK 0xC0000UL /**< Bit mask for LESENSE_CHIDLE9 */ +#define _LESENSE_IDLECONF_CHIDLE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE9_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE9_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE9_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE9_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE9_DEFAULT (_LESENSE_IDLECONF_CHIDLE9_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE9_DISABLE (_LESENSE_IDLECONF_CHIDLE9_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE9_HIGH (_LESENSE_IDLECONF_CHIDLE9_HIGH << 18) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE9_LOW (_LESENSE_IDLECONF_CHIDLE9_LOW << 18) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE9_DAC (_LESENSE_IDLECONF_CHIDLE9_DAC << 18) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE10_SHIFT 20 /**< Shift value for LESENSE_CHIDLE10 */ +#define _LESENSE_IDLECONF_CHIDLE10_MASK 0x300000UL /**< Bit mask for LESENSE_CHIDLE10 */ +#define _LESENSE_IDLECONF_CHIDLE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE10_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE10_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE10_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE10_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE10_DEFAULT (_LESENSE_IDLECONF_CHIDLE10_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE10_DISABLE (_LESENSE_IDLECONF_CHIDLE10_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE10_HIGH (_LESENSE_IDLECONF_CHIDLE10_HIGH << 20) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE10_LOW (_LESENSE_IDLECONF_CHIDLE10_LOW << 20) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE10_DAC (_LESENSE_IDLECONF_CHIDLE10_DAC << 20) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE11_SHIFT 22 /**< Shift value for LESENSE_CHIDLE11 */ +#define _LESENSE_IDLECONF_CHIDLE11_MASK 0xC00000UL /**< Bit mask for LESENSE_CHIDLE11 */ +#define _LESENSE_IDLECONF_CHIDLE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE11_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE11_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE11_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE11_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE11_DEFAULT (_LESENSE_IDLECONF_CHIDLE11_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE11_DISABLE (_LESENSE_IDLECONF_CHIDLE11_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE11_HIGH (_LESENSE_IDLECONF_CHIDLE11_HIGH << 22) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE11_LOW (_LESENSE_IDLECONF_CHIDLE11_LOW << 22) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE11_DAC (_LESENSE_IDLECONF_CHIDLE11_DAC << 22) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE12_SHIFT 24 /**< Shift value for LESENSE_CHIDLE12 */ +#define _LESENSE_IDLECONF_CHIDLE12_MASK 0x3000000UL /**< Bit mask for LESENSE_CHIDLE12 */ +#define _LESENSE_IDLECONF_CHIDLE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE12_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE12_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE12_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE12_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE12_DEFAULT (_LESENSE_IDLECONF_CHIDLE12_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE12_DISABLE (_LESENSE_IDLECONF_CHIDLE12_DISABLE << 24) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE12_HIGH (_LESENSE_IDLECONF_CHIDLE12_HIGH << 24) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE12_LOW (_LESENSE_IDLECONF_CHIDLE12_LOW << 24) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE12_DAC (_LESENSE_IDLECONF_CHIDLE12_DAC << 24) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE13_SHIFT 26 /**< Shift value for LESENSE_CHIDLE13 */ +#define _LESENSE_IDLECONF_CHIDLE13_MASK 0xC000000UL /**< Bit mask for LESENSE_CHIDLE13 */ +#define _LESENSE_IDLECONF_CHIDLE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE13_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE13_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE13_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE13_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE13_DEFAULT (_LESENSE_IDLECONF_CHIDLE13_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE13_DISABLE (_LESENSE_IDLECONF_CHIDLE13_DISABLE << 26) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE13_HIGH (_LESENSE_IDLECONF_CHIDLE13_HIGH << 26) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE13_LOW (_LESENSE_IDLECONF_CHIDLE13_LOW << 26) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE13_DAC (_LESENSE_IDLECONF_CHIDLE13_DAC << 26) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE14_SHIFT 28 /**< Shift value for LESENSE_CHIDLE14 */ +#define _LESENSE_IDLECONF_CHIDLE14_MASK 0x30000000UL /**< Bit mask for LESENSE_CHIDLE14 */ +#define _LESENSE_IDLECONF_CHIDLE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE14_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE14_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE14_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE14_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE14_DEFAULT (_LESENSE_IDLECONF_CHIDLE14_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE14_DISABLE (_LESENSE_IDLECONF_CHIDLE14_DISABLE << 28) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE14_HIGH (_LESENSE_IDLECONF_CHIDLE14_HIGH << 28) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE14_LOW (_LESENSE_IDLECONF_CHIDLE14_LOW << 28) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE14_DAC (_LESENSE_IDLECONF_CHIDLE14_DAC << 28) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE15_SHIFT 30 /**< Shift value for LESENSE_CHIDLE15 */ +#define _LESENSE_IDLECONF_CHIDLE15_MASK 0xC0000000UL /**< Bit mask for LESENSE_CHIDLE15 */ +#define _LESENSE_IDLECONF_CHIDLE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE15_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE15_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE15_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE15_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE15_DEFAULT (_LESENSE_IDLECONF_CHIDLE15_DEFAULT << 30) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE15_DISABLE (_LESENSE_IDLECONF_CHIDLE15_DISABLE << 30) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE15_HIGH (_LESENSE_IDLECONF_CHIDLE15_HIGH << 30) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE15_LOW (_LESENSE_IDLECONF_CHIDLE15_LOW << 30) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE15_DAC (_LESENSE_IDLECONF_CHIDLE15_DAC << 30) /**< Shifted mode DAC for LESENSE_IDLECONF */ /* Bit fields for LESENSE SYNCBUSY */ -#define _LESENSE_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SYNCBUSY */ -#define _LESENSE_SYNCBUSY_MASK 0x00000001UL /**< Mask for LESENSE_SYNCBUSY */ -#define LESENSE_SYNCBUSY_CMD (0x1UL << 0) /**< Command */ -#define _LESENSE_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for LESENSE_CMD */ -#define _LESENSE_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for LESENSE_CMD */ -#define _LESENSE_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SYNCBUSY */ -#define LESENSE_SYNCBUSY_CMD_DEFAULT (_LESENSE_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define _LESENSE_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SYNCBUSY */ +#define _LESENSE_SYNCBUSY_MASK 0x00000001UL /**< Mask for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD (0x1UL << 0) /**< Command */ +#define _LESENSE_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD_DEFAULT (_LESENSE_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SYNCBUSY */ /* Bit fields for LESENSE IF */ -#define _LESENSE_IF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IF */ -#define _LESENSE_IF_MASK 0x003FFFFFUL /**< Mask for LESENSE_IF */ -#define LESENSE_IF_CH0 (0x1UL << 0) /**< Channel */ -#define _LESENSE_IF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ -#define _LESENSE_IF_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ -#define _LESENSE_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH0_DEFAULT (_LESENSE_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH1 (0x1UL << 1) /**< Channel */ -#define _LESENSE_IF_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ -#define _LESENSE_IF_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ -#define _LESENSE_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH1_DEFAULT (_LESENSE_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH2 (0x1UL << 2) /**< Channel */ -#define _LESENSE_IF_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ -#define _LESENSE_IF_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ -#define _LESENSE_IF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH2_DEFAULT (_LESENSE_IF_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH3 (0x1UL << 3) /**< Channel */ -#define _LESENSE_IF_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ -#define _LESENSE_IF_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ -#define _LESENSE_IF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH3_DEFAULT (_LESENSE_IF_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH4 (0x1UL << 4) /**< Channel */ -#define _LESENSE_IF_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ -#define _LESENSE_IF_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ -#define _LESENSE_IF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH4_DEFAULT (_LESENSE_IF_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH5 (0x1UL << 5) /**< Channel */ -#define _LESENSE_IF_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ -#define _LESENSE_IF_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ -#define _LESENSE_IF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH5_DEFAULT (_LESENSE_IF_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH6 (0x1UL << 6) /**< Channel */ -#define _LESENSE_IF_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ -#define _LESENSE_IF_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ -#define _LESENSE_IF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH6_DEFAULT (_LESENSE_IF_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH7 (0x1UL << 7) /**< Channel */ -#define _LESENSE_IF_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ -#define _LESENSE_IF_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ -#define _LESENSE_IF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH7_DEFAULT (_LESENSE_IF_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH8 (0x1UL << 8) /**< Channel */ -#define _LESENSE_IF_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ -#define _LESENSE_IF_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ -#define _LESENSE_IF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH8_DEFAULT (_LESENSE_IF_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH9 (0x1UL << 9) /**< Channel */ -#define _LESENSE_IF_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ -#define _LESENSE_IF_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ -#define _LESENSE_IF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH9_DEFAULT (_LESENSE_IF_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH10 (0x1UL << 10) /**< Channel */ -#define _LESENSE_IF_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ -#define _LESENSE_IF_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ -#define _LESENSE_IF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH10_DEFAULT (_LESENSE_IF_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH11 (0x1UL << 11) /**< Channel */ -#define _LESENSE_IF_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ -#define _LESENSE_IF_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ -#define _LESENSE_IF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH11_DEFAULT (_LESENSE_IF_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH12 (0x1UL << 12) /**< Channel */ -#define _LESENSE_IF_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ -#define _LESENSE_IF_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ -#define _LESENSE_IF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH12_DEFAULT (_LESENSE_IF_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH13 (0x1UL << 13) /**< Channel */ -#define _LESENSE_IF_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ -#define _LESENSE_IF_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ -#define _LESENSE_IF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH13_DEFAULT (_LESENSE_IF_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH14 (0x1UL << 14) /**< Channel */ -#define _LESENSE_IF_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ -#define _LESENSE_IF_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ -#define _LESENSE_IF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH14_DEFAULT (_LESENSE_IF_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH15 (0x1UL << 15) /**< Channel */ -#define _LESENSE_IF_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ -#define _LESENSE_IF_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ -#define _LESENSE_IF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH15_DEFAULT (_LESENSE_IF_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_SCANDONE (0x1UL << 16) /**< Scan Done */ -#define _LESENSE_IF_SCANDONE_SHIFT 16 /**< Shift value for LESENSE_SCANDONE */ -#define _LESENSE_IF_SCANDONE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANDONE */ -#define _LESENSE_IF_SCANDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_SCANDONE_DEFAULT (_LESENSE_IF_SCANDONE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_DEC (0x1UL << 17) /**< Decoder */ -#define _LESENSE_IF_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ -#define _LESENSE_IF_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ -#define _LESENSE_IF_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_DEC_DEFAULT (_LESENSE_IF_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_RESWL (0x1UL << 18) /**< Result Watermark Level */ -#define _LESENSE_IF_RESWL_SHIFT 18 /**< Shift value for LESENSE_RESWL */ -#define _LESENSE_IF_RESWL_MASK 0x40000UL /**< Bit mask for LESENSE_RESWL */ -#define _LESENSE_IF_RESWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_RESWL_DEFAULT (_LESENSE_IF_RESWL_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_RESOF (0x1UL << 19) /**< Result Overflow */ -#define _LESENSE_IF_RESOF_SHIFT 19 /**< Shift value for LESENSE_RESOF */ -#define _LESENSE_IF_RESOF_MASK 0x80000UL /**< Bit mask for LESENSE_RESOF */ -#define _LESENSE_IF_RESOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_RESOF_DEFAULT (_LESENSE_IF_RESOF_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CNTOF (0x1UL << 20) /**< Counter Overflow */ -#define _LESENSE_IF_CNTOF_SHIFT 20 /**< Shift value for LESENSE_CNTOF */ -#define _LESENSE_IF_CNTOF_MASK 0x100000UL /**< Bit mask for LESENSE_CNTOF */ -#define _LESENSE_IF_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CNTOF_DEFAULT (_LESENSE_IF_CNTOF_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_RESUF (0x1UL << 21) /**< Result Underflow */ -#define _LESENSE_IF_RESUF_SHIFT 21 /**< Shift value for LESENSE_RESUF */ -#define _LESENSE_IF_RESUF_MASK 0x200000UL /**< Bit mask for LESENSE_RESUF */ -#define _LESENSE_IF_RESUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_RESUF_DEFAULT (_LESENSE_IF_RESUF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define _LESENSE_IF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IF */ +#define _LESENSE_IF_MASK 0x003FFFFFUL /**< Mask for LESENSE_IF */ +#define LESENSE_IF_CH0 (0x1UL << 0) /**< Channel */ +#define _LESENSE_IF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH0_DEFAULT (_LESENSE_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1 (0x1UL << 1) /**< Channel */ +#define _LESENSE_IF_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1_DEFAULT (_LESENSE_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2 (0x1UL << 2) /**< Channel */ +#define _LESENSE_IF_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2_DEFAULT (_LESENSE_IF_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3 (0x1UL << 3) /**< Channel */ +#define _LESENSE_IF_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3_DEFAULT (_LESENSE_IF_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4 (0x1UL << 4) /**< Channel */ +#define _LESENSE_IF_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4_DEFAULT (_LESENSE_IF_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5 (0x1UL << 5) /**< Channel */ +#define _LESENSE_IF_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5_DEFAULT (_LESENSE_IF_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6 (0x1UL << 6) /**< Channel */ +#define _LESENSE_IF_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6_DEFAULT (_LESENSE_IF_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7 (0x1UL << 7) /**< Channel */ +#define _LESENSE_IF_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7_DEFAULT (_LESENSE_IF_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8 (0x1UL << 8) /**< Channel */ +#define _LESENSE_IF_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8_DEFAULT (_LESENSE_IF_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9 (0x1UL << 9) /**< Channel */ +#define _LESENSE_IF_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9_DEFAULT (_LESENSE_IF_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10 (0x1UL << 10) /**< Channel */ +#define _LESENSE_IF_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10_DEFAULT (_LESENSE_IF_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11 (0x1UL << 11) /**< Channel */ +#define _LESENSE_IF_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11_DEFAULT (_LESENSE_IF_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12 (0x1UL << 12) /**< Channel */ +#define _LESENSE_IF_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12_DEFAULT (_LESENSE_IF_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13 (0x1UL << 13) /**< Channel */ +#define _LESENSE_IF_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13_DEFAULT (_LESENSE_IF_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14 (0x1UL << 14) /**< Channel */ +#define _LESENSE_IF_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14_DEFAULT (_LESENSE_IF_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15 (0x1UL << 15) /**< Channel */ +#define _LESENSE_IF_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15_DEFAULT (_LESENSE_IF_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANDONE (0x1UL << 16) /**< Scan Done */ +#define _LESENSE_IF_SCANDONE_SHIFT 16 /**< Shift value for LESENSE_SCANDONE */ +#define _LESENSE_IF_SCANDONE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANDONE */ +#define _LESENSE_IF_SCANDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANDONE_DEFAULT (_LESENSE_IF_SCANDONE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC (0x1UL << 17) /**< Decoder */ +#define _LESENSE_IF_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IF_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IF_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC_DEFAULT (_LESENSE_IF_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESWL (0x1UL << 18) /**< Result Watermark Level */ +#define _LESENSE_IF_RESWL_SHIFT 18 /**< Shift value for LESENSE_RESWL */ +#define _LESENSE_IF_RESWL_MASK 0x40000UL /**< Bit mask for LESENSE_RESWL */ +#define _LESENSE_IF_RESWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESWL_DEFAULT (_LESENSE_IF_RESWL_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESOF (0x1UL << 19) /**< Result Overflow */ +#define _LESENSE_IF_RESOF_SHIFT 19 /**< Shift value for LESENSE_RESOF */ +#define _LESENSE_IF_RESOF_MASK 0x80000UL /**< Bit mask for LESENSE_RESOF */ +#define _LESENSE_IF_RESOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESOF_DEFAULT (_LESENSE_IF_RESOF_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF (0x1UL << 20) /**< Counter Overflow */ +#define _LESENSE_IF_CNTOF_SHIFT 20 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_MASK 0x100000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF_DEFAULT (_LESENSE_IF_CNTOF_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESUF (0x1UL << 21) /**< Result Underflow */ +#define _LESENSE_IF_RESUF_SHIFT 21 /**< Shift value for LESENSE_RESUF */ +#define _LESENSE_IF_RESUF_MASK 0x200000UL /**< Bit mask for LESENSE_RESUF */ +#define _LESENSE_IF_RESUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESUF_DEFAULT (_LESENSE_IF_RESUF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IF */ /* Bit fields for LESENSE IEN */ -#define _LESENSE_IEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IEN */ -#define _LESENSE_IEN_MASK 0x003FFFFFUL /**< Mask for LESENSE_IEN */ -#define LESENSE_IEN_CH0 (0x1UL << 0) /**< Channel */ -#define _LESENSE_IEN_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ -#define _LESENSE_IEN_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ -#define _LESENSE_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH0_DEFAULT (_LESENSE_IEN_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH1 (0x1UL << 1) /**< Channel */ -#define _LESENSE_IEN_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ -#define _LESENSE_IEN_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ -#define _LESENSE_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH1_DEFAULT (_LESENSE_IEN_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH2 (0x1UL << 2) /**< Channel */ -#define _LESENSE_IEN_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ -#define _LESENSE_IEN_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ -#define _LESENSE_IEN_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH2_DEFAULT (_LESENSE_IEN_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH3 (0x1UL << 3) /**< Channel */ -#define _LESENSE_IEN_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ -#define _LESENSE_IEN_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ -#define _LESENSE_IEN_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH3_DEFAULT (_LESENSE_IEN_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH4 (0x1UL << 4) /**< Channel */ -#define _LESENSE_IEN_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ -#define _LESENSE_IEN_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ -#define _LESENSE_IEN_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH4_DEFAULT (_LESENSE_IEN_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH5 (0x1UL << 5) /**< Channel */ -#define _LESENSE_IEN_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ -#define _LESENSE_IEN_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ -#define _LESENSE_IEN_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH5_DEFAULT (_LESENSE_IEN_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH6 (0x1UL << 6) /**< Channel */ -#define _LESENSE_IEN_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ -#define _LESENSE_IEN_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ -#define _LESENSE_IEN_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH6_DEFAULT (_LESENSE_IEN_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH7 (0x1UL << 7) /**< Channel */ -#define _LESENSE_IEN_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ -#define _LESENSE_IEN_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ -#define _LESENSE_IEN_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH7_DEFAULT (_LESENSE_IEN_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH8 (0x1UL << 8) /**< Channel */ -#define _LESENSE_IEN_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ -#define _LESENSE_IEN_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ -#define _LESENSE_IEN_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH8_DEFAULT (_LESENSE_IEN_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH9 (0x1UL << 9) /**< Channel */ -#define _LESENSE_IEN_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ -#define _LESENSE_IEN_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ -#define _LESENSE_IEN_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH9_DEFAULT (_LESENSE_IEN_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH10 (0x1UL << 10) /**< Channel */ -#define _LESENSE_IEN_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ -#define _LESENSE_IEN_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ -#define _LESENSE_IEN_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH10_DEFAULT (_LESENSE_IEN_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH11 (0x1UL << 11) /**< Channel */ -#define _LESENSE_IEN_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ -#define _LESENSE_IEN_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ -#define _LESENSE_IEN_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH11_DEFAULT (_LESENSE_IEN_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH12 (0x1UL << 12) /**< Channel */ -#define _LESENSE_IEN_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ -#define _LESENSE_IEN_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ -#define _LESENSE_IEN_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH12_DEFAULT (_LESENSE_IEN_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH13 (0x1UL << 13) /**< Channel */ -#define _LESENSE_IEN_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ -#define _LESENSE_IEN_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ -#define _LESENSE_IEN_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH13_DEFAULT (_LESENSE_IEN_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH14 (0x1UL << 14) /**< Channel */ -#define _LESENSE_IEN_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ -#define _LESENSE_IEN_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ -#define _LESENSE_IEN_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH14_DEFAULT (_LESENSE_IEN_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH15 (0x1UL << 15) /**< Channel */ -#define _LESENSE_IEN_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ -#define _LESENSE_IEN_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ -#define _LESENSE_IEN_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH15_DEFAULT (_LESENSE_IEN_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_SCANDONE (0x1UL << 16) /**< Scan Complete */ -#define _LESENSE_IEN_SCANDONE_SHIFT 16 /**< Shift value for LESENSE_SCANDONE */ -#define _LESENSE_IEN_SCANDONE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANDONE */ -#define _LESENSE_IEN_SCANDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_SCANDONE_DEFAULT (_LESENSE_IEN_SCANDONE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_DEC (0x1UL << 17) /**< Decoder */ -#define _LESENSE_IEN_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ -#define _LESENSE_IEN_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ -#define _LESENSE_IEN_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_DEC_DEFAULT (_LESENSE_IEN_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_RESWL (0x1UL << 18) /**< Result Watermark Level */ -#define _LESENSE_IEN_RESWL_SHIFT 18 /**< Shift value for LESENSE_RESWL */ -#define _LESENSE_IEN_RESWL_MASK 0x40000UL /**< Bit mask for LESENSE_RESWL */ -#define _LESENSE_IEN_RESWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_RESWL_DEFAULT (_LESENSE_IEN_RESWL_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_RESOF (0x1UL << 19) /**< Result Overflow */ -#define _LESENSE_IEN_RESOF_SHIFT 19 /**< Shift value for LESENSE_RESOF */ -#define _LESENSE_IEN_RESOF_MASK 0x80000UL /**< Bit mask for LESENSE_RESOF */ -#define _LESENSE_IEN_RESOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_RESOF_DEFAULT (_LESENSE_IEN_RESOF_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CNTOF (0x1UL << 20) /**< Counter Overflow */ -#define _LESENSE_IEN_CNTOF_SHIFT 20 /**< Shift value for LESENSE_CNTOF */ -#define _LESENSE_IEN_CNTOF_MASK 0x100000UL /**< Bit mask for LESENSE_CNTOF */ -#define _LESENSE_IEN_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CNTOF_DEFAULT (_LESENSE_IEN_CNTOF_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_RESUF (0x1UL << 21) /**< Result Underflow */ -#define _LESENSE_IEN_RESUF_SHIFT 21 /**< Shift value for LESENSE_RESUF */ -#define _LESENSE_IEN_RESUF_MASK 0x200000UL /**< Bit mask for LESENSE_RESUF */ -#define _LESENSE_IEN_RESUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_RESUF_DEFAULT (_LESENSE_IEN_RESUF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define _LESENSE_IEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IEN */ +#define _LESENSE_IEN_MASK 0x003FFFFFUL /**< Mask for LESENSE_IEN */ +#define LESENSE_IEN_CH0 (0x1UL << 0) /**< Channel */ +#define _LESENSE_IEN_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH0_DEFAULT (_LESENSE_IEN_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1 (0x1UL << 1) /**< Channel */ +#define _LESENSE_IEN_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1_DEFAULT (_LESENSE_IEN_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2 (0x1UL << 2) /**< Channel */ +#define _LESENSE_IEN_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2_DEFAULT (_LESENSE_IEN_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3 (0x1UL << 3) /**< Channel */ +#define _LESENSE_IEN_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3_DEFAULT (_LESENSE_IEN_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4 (0x1UL << 4) /**< Channel */ +#define _LESENSE_IEN_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4_DEFAULT (_LESENSE_IEN_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5 (0x1UL << 5) /**< Channel */ +#define _LESENSE_IEN_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5_DEFAULT (_LESENSE_IEN_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6 (0x1UL << 6) /**< Channel */ +#define _LESENSE_IEN_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6_DEFAULT (_LESENSE_IEN_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7 (0x1UL << 7) /**< Channel */ +#define _LESENSE_IEN_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7_DEFAULT (_LESENSE_IEN_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8 (0x1UL << 8) /**< Channel */ +#define _LESENSE_IEN_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8_DEFAULT (_LESENSE_IEN_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9 (0x1UL << 9) /**< Channel */ +#define _LESENSE_IEN_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9_DEFAULT (_LESENSE_IEN_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10 (0x1UL << 10) /**< Channel */ +#define _LESENSE_IEN_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10_DEFAULT (_LESENSE_IEN_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11 (0x1UL << 11) /**< Channel */ +#define _LESENSE_IEN_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11_DEFAULT (_LESENSE_IEN_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12 (0x1UL << 12) /**< Channel */ +#define _LESENSE_IEN_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12_DEFAULT (_LESENSE_IEN_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13 (0x1UL << 13) /**< Channel */ +#define _LESENSE_IEN_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13_DEFAULT (_LESENSE_IEN_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14 (0x1UL << 14) /**< Channel */ +#define _LESENSE_IEN_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14_DEFAULT (_LESENSE_IEN_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15 (0x1UL << 15) /**< Channel */ +#define _LESENSE_IEN_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15_DEFAULT (_LESENSE_IEN_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANDONE (0x1UL << 16) /**< Scan Complete */ +#define _LESENSE_IEN_SCANDONE_SHIFT 16 /**< Shift value for LESENSE_SCANDONE */ +#define _LESENSE_IEN_SCANDONE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANDONE */ +#define _LESENSE_IEN_SCANDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANDONE_DEFAULT (_LESENSE_IEN_SCANDONE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC (0x1UL << 17) /**< Decoder */ +#define _LESENSE_IEN_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC_DEFAULT (_LESENSE_IEN_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESWL (0x1UL << 18) /**< Result Watermark Level */ +#define _LESENSE_IEN_RESWL_SHIFT 18 /**< Shift value for LESENSE_RESWL */ +#define _LESENSE_IEN_RESWL_MASK 0x40000UL /**< Bit mask for LESENSE_RESWL */ +#define _LESENSE_IEN_RESWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESWL_DEFAULT (_LESENSE_IEN_RESWL_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESOF (0x1UL << 19) /**< Result Overflow */ +#define _LESENSE_IEN_RESOF_SHIFT 19 /**< Shift value for LESENSE_RESOF */ +#define _LESENSE_IEN_RESOF_MASK 0x80000UL /**< Bit mask for LESENSE_RESOF */ +#define _LESENSE_IEN_RESOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESOF_DEFAULT (_LESENSE_IEN_RESOF_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF (0x1UL << 20) /**< Counter Overflow */ +#define _LESENSE_IEN_CNTOF_SHIFT 20 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_MASK 0x100000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF_DEFAULT (_LESENSE_IEN_CNTOF_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESUF (0x1UL << 21) /**< Result Underflow */ +#define _LESENSE_IEN_RESUF_SHIFT 21 /**< Shift value for LESENSE_RESUF */ +#define _LESENSE_IEN_RESUF_MASK 0x200000UL /**< Bit mask for LESENSE_RESUF */ +#define _LESENSE_IEN_RESUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESUF_DEFAULT (_LESENSE_IEN_RESUF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IEN */ /* Bit fields for LESENSE CH_TIMING */ -#define _LESENSE_CH_TIMING_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_TIMING */ -#define _LESENSE_CH_TIMING_MASK 0x00FFFFFFUL /**< Mask for LESENSE_CH_TIMING */ -#define _LESENSE_CH_TIMING_EXTIME_SHIFT 0 /**< Shift value for LESENSE_EXTIME */ -#define _LESENSE_CH_TIMING_EXTIME_MASK 0x3FUL /**< Bit mask for LESENSE_EXTIME */ -#define _LESENSE_CH_TIMING_EXTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ -#define LESENSE_CH_TIMING_EXTIME_DEFAULT (_LESENSE_CH_TIMING_EXTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ -#define _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT 6 /**< Shift value for LESENSE_SAMPLEDLY */ -#define _LESENSE_CH_TIMING_SAMPLEDLY_MASK 0x3FC0UL /**< Bit mask for LESENSE_SAMPLEDLY */ -#define _LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ -#define LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT (_LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ -#define _LESENSE_CH_TIMING_MEASUREDLY_SHIFT 14 /**< Shift value for LESENSE_MEASUREDLY */ -#define _LESENSE_CH_TIMING_MEASUREDLY_MASK 0xFFC000UL /**< Bit mask for LESENSE_MEASUREDLY */ -#define _LESENSE_CH_TIMING_MEASUREDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ -#define LESENSE_CH_TIMING_MEASUREDLY_DEFAULT (_LESENSE_CH_TIMING_MEASUREDLY_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MASK 0x00FFFFFFUL /**< Mask for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_EXTIME_SHIFT 0 /**< Shift value for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_MASK 0x3FUL /**< Bit mask for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_EXTIME_DEFAULT (_LESENSE_CH_TIMING_EXTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT 6 /**< Shift value for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_MASK 0x3FC0UL /**< Bit mask for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT (_LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MEASUREDLY_SHIFT 14 /**< Shift value for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_MASK 0xFFC000UL /**< Bit mask for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_MEASUREDLY_DEFAULT (_LESENSE_CH_TIMING_MEASUREDLY_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ /* Bit fields for LESENSE CH_INTERACT */ -#define _LESENSE_CH_INTERACT_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_MASK 0x3FFF0FFFUL /**< Mask for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_THRES_SHIFT 0 /**< Shift value for LESENSE_THRES */ -#define _LESENSE_CH_INTERACT_THRES_MASK 0xFFFUL /**< Bit mask for LESENSE_THRES */ -#define _LESENSE_CH_INTERACT_THRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_THRES_DEFAULT (_LESENSE_CH_INTERACT_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ -#define _LESENSE_CH_INTERACT_EXMODE_SHIFT 16 /**< Shift value for LESENSE_EXMODE */ -#define _LESENSE_CH_INTERACT_EXMODE_MASK 0x30000UL /**< Bit mask for LESENSE_EXMODE */ -#define _LESENSE_CH_INTERACT_EXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_EXMODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_EXMODE_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_EXMODE_LOW 0x00000002UL /**< Mode LOW for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_EXMODE_DACOUT 0x00000003UL /**< Mode DACOUT for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_EXMODE_DEFAULT (_LESENSE_CH_INTERACT_EXMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_EXMODE_DISABLE (_LESENSE_CH_INTERACT_EXMODE_DISABLE << 16) /**< Shifted mode DISABLE for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_EXMODE_HIGH (_LESENSE_CH_INTERACT_EXMODE_HIGH << 16) /**< Shifted mode HIGH for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_EXMODE_LOW (_LESENSE_CH_INTERACT_EXMODE_LOW << 16) /**< Shifted mode LOW for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_EXMODE_DACOUT (_LESENSE_CH_INTERACT_EXMODE_DACOUT << 16) /**< Shifted mode DACOUT for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_ALTEX (0x1UL << 18) /**< Use alternative excite pin */ -#define _LESENSE_CH_INTERACT_ALTEX_SHIFT 18 /**< Shift value for LESENSE_ALTEX */ -#define _LESENSE_CH_INTERACT_ALTEX_MASK 0x40000UL /**< Bit mask for LESENSE_ALTEX */ -#define _LESENSE_CH_INTERACT_ALTEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_ALTEX_DEFAULT (_LESENSE_CH_INTERACT_ALTEX_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_SAMPLECLK (0x1UL << 19) /**< Select clock used for timing of sample d */ -#define _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT 19 /**< Shift value for LESENSE_SAMPLECLK */ -#define _LESENSE_CH_INTERACT_SAMPLECLK_MASK 0x80000UL /**< Bit mask for LESENSE_SAMPLECLK */ -#define _LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SAMPLECLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT (_LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_SAMPLECLK_LFACLK (_LESENSE_CH_INTERACT_SAMPLECLK_LFACLK << 19) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO (_LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO << 19) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_EXCLK (0x1UL << 20) /**< Select clock used for excitation timing */ -#define _LESENSE_CH_INTERACT_EXCLK_SHIFT 20 /**< Shift value for LESENSE_EXCLK */ -#define _LESENSE_CH_INTERACT_EXCLK_MASK 0x100000UL /**< Bit mask for LESENSE_EXCLK */ -#define _LESENSE_CH_INTERACT_EXCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_EXCLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_EXCLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_EXCLK_DEFAULT (_LESENSE_CH_INTERACT_EXCLK_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_EXCLK_LFACLK (_LESENSE_CH_INTERACT_EXCLK_LFACLK << 20) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_EXCLK_AUXHFRCO (_LESENSE_CH_INTERACT_EXCLK_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT*/ -#define _LESENSE_CH_INTERACT_SETIF_SHIFT 21 /**< Shift value for LESENSE_SETIF */ -#define _LESENSE_CH_INTERACT_SETIF_MASK 0xE00000UL /**< Bit mask for LESENSE_SETIF */ -#define _LESENSE_CH_INTERACT_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SETIF_NONE 0x00000000UL /**< Mode NONE for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SETIF_LEVEL 0x00000001UL /**< Mode LEVEL for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SETIF_POSEDGE 0x00000002UL /**< Mode POSEDGE for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SETIF_NEGEDGE 0x00000003UL /**< Mode NEGEDGE for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SETIF_BOTHEDGES 0x00000004UL /**< Mode BOTHEDGES for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_SETIF_DEFAULT (_LESENSE_CH_INTERACT_SETIF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_SETIF_NONE (_LESENSE_CH_INTERACT_SETIF_NONE << 21) /**< Shifted mode NONE for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_SETIF_LEVEL (_LESENSE_CH_INTERACT_SETIF_LEVEL << 21) /**< Shifted mode LEVEL for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_SETIF_POSEDGE (_LESENSE_CH_INTERACT_SETIF_POSEDGE << 21) /**< Shifted mode POSEDGE for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_SETIF_NEGEDGE (_LESENSE_CH_INTERACT_SETIF_NEGEDGE << 21) /**< Shifted mode NEGEDGE for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_SETIF_BOTHEDGES (_LESENSE_CH_INTERACT_SETIF_BOTHEDGES << 21) /**< Shifted mode BOTHEDGES for LESENSE_CH_INTERACT*/ -#define _LESENSE_CH_INTERACT_OFFSET_SHIFT 24 /**< Shift value for LESENSE_OFFSET */ -#define _LESENSE_CH_INTERACT_OFFSET_MASK 0xF000000UL /**< Bit mask for LESENSE_OFFSET */ -#define _LESENSE_CH_INTERACT_OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_OFFSET_DEFAULT (_LESENSE_CH_INTERACT_OFFSET_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ -#define _LESENSE_CH_INTERACT_SAMPLE_SHIFT 28 /**< Shift value for LESENSE_SAMPLE */ -#define _LESENSE_CH_INTERACT_SAMPLE_MASK 0x30000000UL /**< Bit mask for LESENSE_SAMPLE */ -#define _LESENSE_CH_INTERACT_SAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT 0x00000000UL /**< Mode ACMPCOUNT for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SAMPLE_ACMP 0x00000001UL /**< Mode ACMP for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SAMPLE_ADC 0x00000002UL /**< Mode ADC for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SAMPLE_ADCDIFF 0x00000003UL /**< Mode ADCDIFF for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_SAMPLE_DEFAULT (_LESENSE_CH_INTERACT_SAMPLE_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT (_LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT << 28) /**< Shifted mode ACMPCOUNT for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_SAMPLE_ACMP (_LESENSE_CH_INTERACT_SAMPLE_ACMP << 28) /**< Shifted mode ACMP for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_SAMPLE_ADC (_LESENSE_CH_INTERACT_SAMPLE_ADC << 28) /**< Shifted mode ADC for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_SAMPLE_ADCDIFF (_LESENSE_CH_INTERACT_SAMPLE_ADCDIFF << 28) /**< Shifted mode ADCDIFF for LESENSE_CH_INTERACT*/ +#define _LESENSE_CH_INTERACT_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_MASK 0x3FFF0FFFUL /**< Mask for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_THRES_SHIFT 0 /**< Shift value for LESENSE_THRES */ +#define _LESENSE_CH_INTERACT_THRES_MASK 0xFFFUL /**< Bit mask for LESENSE_THRES */ +#define _LESENSE_CH_INTERACT_THRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_THRES_DEFAULT (_LESENSE_CH_INTERACT_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define _LESENSE_CH_INTERACT_EXMODE_SHIFT 16 /**< Shift value for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_MASK 0x30000UL /**< Bit mask for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_LOW 0x00000002UL /**< Mode LOW for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DACOUT 0x00000003UL /**< Mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DEFAULT (_LESENSE_CH_INTERACT_EXMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_EXMODE_DISABLE (_LESENSE_CH_INTERACT_EXMODE_DISABLE << 16) /**< Shifted mode DISABLE for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_EXMODE_HIGH (_LESENSE_CH_INTERACT_EXMODE_HIGH << 16) /**< Shifted mode HIGH for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_LOW (_LESENSE_CH_INTERACT_EXMODE_LOW << 16) /**< Shifted mode LOW for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DACOUT (_LESENSE_CH_INTERACT_EXMODE_DACOUT << 16) /**< Shifted mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX (0x1UL << 18) /**< Use alternative excite pin */ +#define _LESENSE_CH_INTERACT_ALTEX_SHIFT 18 /**< Shift value for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_MASK 0x40000UL /**< Bit mask for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX_DEFAULT (_LESENSE_CH_INTERACT_ALTEX_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SAMPLECLK (0x1UL << 19) /**< Select clock used for timing of sample d */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT 19 /**< Shift value for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_MASK 0x80000UL /**< Bit mask for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT (_LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SAMPLECLK_LFACLK (_LESENSE_CH_INTERACT_SAMPLECLK_LFACLK << 19) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO (_LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO << 19) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_EXCLK (0x1UL << 20) /**< Select clock used for excitation timing */ +#define _LESENSE_CH_INTERACT_EXCLK_SHIFT 20 /**< Shift value for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_MASK 0x100000UL /**< Bit mask for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_DEFAULT (_LESENSE_CH_INTERACT_EXCLK_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_EXCLK_LFACLK (_LESENSE_CH_INTERACT_EXCLK_LFACLK << 20) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_AUXHFRCO (_LESENSE_CH_INTERACT_EXCLK_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT*/ +#define _LESENSE_CH_INTERACT_SETIF_SHIFT 21 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_MASK 0xE00000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NONE 0x00000000UL /**< Mode NONE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_LEVEL 0x00000001UL /**< Mode LEVEL for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_POSEDGE 0x00000002UL /**< Mode POSEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NEGEDGE 0x00000003UL /**< Mode NEGEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_BOTHEDGES 0x00000004UL /**< Mode BOTHEDGES for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_DEFAULT (_LESENSE_CH_INTERACT_SETIF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SETIF_NONE (_LESENSE_CH_INTERACT_SETIF_NONE << 21) /**< Shifted mode NONE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_LEVEL (_LESENSE_CH_INTERACT_SETIF_LEVEL << 21) /**< Shifted mode LEVEL for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_POSEDGE (_LESENSE_CH_INTERACT_SETIF_POSEDGE << 21) /**< Shifted mode POSEDGE for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SETIF_NEGEDGE (_LESENSE_CH_INTERACT_SETIF_NEGEDGE << 21) /**< Shifted mode NEGEDGE for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SETIF_BOTHEDGES (_LESENSE_CH_INTERACT_SETIF_BOTHEDGES << 21) /**< Shifted mode BOTHEDGES for LESENSE_CH_INTERACT*/ +#define _LESENSE_CH_INTERACT_OFFSET_SHIFT 24 /**< Shift value for LESENSE_OFFSET */ +#define _LESENSE_CH_INTERACT_OFFSET_MASK 0xF000000UL /**< Bit mask for LESENSE_OFFSET */ +#define _LESENSE_CH_INTERACT_OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_OFFSET_DEFAULT (_LESENSE_CH_INTERACT_OFFSET_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define _LESENSE_CH_INTERACT_SAMPLE_SHIFT 28 /**< Shift value for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_MASK 0x30000000UL /**< Bit mask for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT 0x00000000UL /**< Mode ACMPCOUNT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ACMP 0x00000001UL /**< Mode ACMP for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ADC 0x00000002UL /**< Mode ADC for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ADCDIFF 0x00000003UL /**< Mode ADCDIFF for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_DEFAULT (_LESENSE_CH_INTERACT_SAMPLE_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT (_LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT << 28) /**< Shifted mode ACMPCOUNT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SAMPLE_ACMP (_LESENSE_CH_INTERACT_SAMPLE_ACMP << 28) /**< Shifted mode ACMP for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ADC (_LESENSE_CH_INTERACT_SAMPLE_ADC << 28) /**< Shifted mode ADC for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ADCDIFF (_LESENSE_CH_INTERACT_SAMPLE_ADCDIFF << 28) /**< Shifted mode ADCDIFF for LESENSE_CH_INTERACT*/ /* Bit fields for LESENSE CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_MASK 0x0000037CUL /**< Mask for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_DECODE (0x1UL << 2) /**< Send result to decoder */ -#define _LESENSE_CH_EVALCFG_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */ -#define _LESENSE_CH_EVALCFG_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */ -#define _LESENSE_CH_EVALCFG_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_DECODE_DEFAULT (_LESENSE_CH_EVALCFG_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_COMP (0x1UL << 3) /**< Select mode for threshold comparison */ -#define _LESENSE_CH_EVALCFG_COMP_SHIFT 3 /**< Shift value for LESENSE_COMP */ -#define _LESENSE_CH_EVALCFG_COMP_MASK 0x8UL /**< Bit mask for LESENSE_COMP */ -#define _LESENSE_CH_EVALCFG_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_COMP_LESS 0x00000000UL /**< Mode LESS for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_COMP_GE 0x00000001UL /**< Mode GE for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_COMP_DEFAULT (_LESENSE_CH_EVALCFG_COMP_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_COMP_LESS (_LESENSE_CH_EVALCFG_COMP_LESS << 3) /**< Shifted mode LESS for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_COMP_GE (_LESENSE_CH_EVALCFG_COMP_GE << 3) /**< Shifted mode GE for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_STRSAMPLE_SHIFT 4 /**< Shift value for LESENSE_STRSAMPLE */ -#define _LESENSE_CH_EVALCFG_STRSAMPLE_MASK 0x30UL /**< Bit mask for LESENSE_STRSAMPLE */ -#define _LESENSE_CH_EVALCFG_STRSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_STRSAMPLE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_STRSAMPLE_DATA 0x00000001UL /**< Mode DATA for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_STRSAMPLE_DATASRC 0x00000002UL /**< Mode DATASRC for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_STRSAMPLE_DEFAULT (_LESENSE_CH_EVALCFG_STRSAMPLE_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_STRSAMPLE_DISABLE (_LESENSE_CH_EVALCFG_STRSAMPLE_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_STRSAMPLE_DATA (_LESENSE_CH_EVALCFG_STRSAMPLE_DATA << 4) /**< Shifted mode DATA for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_STRSAMPLE_DATASRC (_LESENSE_CH_EVALCFG_STRSAMPLE_DATASRC << 4) /**< Shifted mode DATASRC for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_SCANRESINV (0x1UL << 6) /**< Enable inversion of result */ -#define _LESENSE_CH_EVALCFG_SCANRESINV_SHIFT 6 /**< Shift value for LESENSE_SCANRESINV */ -#define _LESENSE_CH_EVALCFG_SCANRESINV_MASK 0x40UL /**< Bit mask for LESENSE_SCANRESINV */ -#define _LESENSE_CH_EVALCFG_SCANRESINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_SCANRESINV_DEFAULT (_LESENSE_CH_EVALCFG_SCANRESINV_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_MODE_SHIFT 8 /**< Shift value for LESENSE_MODE */ -#define _LESENSE_CH_EVALCFG_MODE_MASK 0x300UL /**< Bit mask for LESENSE_MODE */ -#define _LESENSE_CH_EVALCFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_MODE_THRES 0x00000000UL /**< Mode THRES for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_MODE_SLIDINGWIN 0x00000001UL /**< Mode SLIDINGWIN for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_MODE_STEPDET 0x00000002UL /**< Mode STEPDET for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_MODE_DEFAULT (_LESENSE_CH_EVALCFG_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_MODE_THRES (_LESENSE_CH_EVALCFG_MODE_THRES << 8) /**< Shifted mode THRES for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_MODE_SLIDINGWIN (_LESENSE_CH_EVALCFG_MODE_SLIDINGWIN << 8) /**< Shifted mode SLIDINGWIN for LESENSE_CH_EVALCFG*/ -#define LESENSE_CH_EVALCFG_MODE_STEPDET (_LESENSE_CH_EVALCFG_MODE_STEPDET << 8) /**< Shifted mode STEPDET for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_MASK 0x0000037CUL /**< Mask for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_DECODE (0x1UL << 2) /**< Send result to decoder */ +#define _LESENSE_CH_EVALCFG_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */ +#define _LESENSE_CH_EVALCFG_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */ +#define _LESENSE_CH_EVALCFG_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_DECODE_DEFAULT (_LESENSE_CH_EVALCFG_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_COMP (0x1UL << 3) /**< Select mode for threshold comparison */ +#define _LESENSE_CH_EVALCFG_COMP_SHIFT 3 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_CH_EVALCFG_COMP_MASK 0x8UL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_CH_EVALCFG_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_COMP_LESS 0x00000000UL /**< Mode LESS for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_COMP_GE 0x00000001UL /**< Mode GE for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_COMP_DEFAULT (_LESENSE_CH_EVALCFG_COMP_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_COMP_LESS (_LESENSE_CH_EVALCFG_COMP_LESS << 3) /**< Shifted mode LESS for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_COMP_GE (_LESENSE_CH_EVALCFG_COMP_GE << 3) /**< Shifted mode GE for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_SHIFT 4 /**< Shift value for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_MASK 0x30UL /**< Bit mask for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_DATA 0x00000001UL /**< Mode DATA for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_DATASRC 0x00000002UL /**< Mode DATASRC for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_STRSAMPLE_DEFAULT (_LESENSE_CH_EVALCFG_STRSAMPLE_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_STRSAMPLE_DISABLE (_LESENSE_CH_EVALCFG_STRSAMPLE_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_STRSAMPLE_DATA (_LESENSE_CH_EVALCFG_STRSAMPLE_DATA << 4) /**< Shifted mode DATA for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_STRSAMPLE_DATASRC (_LESENSE_CH_EVALCFG_STRSAMPLE_DATASRC << 4) /**< Shifted mode DATASRC for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_SCANRESINV (0x1UL << 6) /**< Enable inversion of result */ +#define _LESENSE_CH_EVALCFG_SCANRESINV_SHIFT 6 /**< Shift value for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVALCFG_SCANRESINV_MASK 0x40UL /**< Bit mask for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVALCFG_SCANRESINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_SCANRESINV_DEFAULT (_LESENSE_CH_EVALCFG_SCANRESINV_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_MODE_SHIFT 8 /**< Shift value for LESENSE_MODE */ +#define _LESENSE_CH_EVALCFG_MODE_MASK 0x300UL /**< Bit mask for LESENSE_MODE */ +#define _LESENSE_CH_EVALCFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_MODE_THRES 0x00000000UL /**< Mode THRES for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_MODE_SLIDINGWIN 0x00000001UL /**< Mode SLIDINGWIN for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_MODE_STEPDET 0x00000002UL /**< Mode STEPDET for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_MODE_DEFAULT (_LESENSE_CH_EVALCFG_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_MODE_THRES (_LESENSE_CH_EVALCFG_MODE_THRES << 8) /**< Shifted mode THRES for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_MODE_SLIDINGWIN (_LESENSE_CH_EVALCFG_MODE_SLIDINGWIN << 8) /**< Shifted mode SLIDINGWIN for LESENSE_CH_EVALCFG*/ +#define LESENSE_CH_EVALCFG_MODE_STEPDET (_LESENSE_CH_EVALCFG_MODE_STEPDET << 8) /**< Shifted mode STEPDET for LESENSE_CH_EVALCFG */ /* Bit fields for LESENSE CH_EVALTHRES */ -#define _LESENSE_CH_EVALTHRES_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_EVALTHRES */ -#define _LESENSE_CH_EVALTHRES_MASK 0x0000FFFFUL /**< Mask for LESENSE_CH_EVALTHRES */ -#define _LESENSE_CH_EVALTHRES_EVALTHRES_SHIFT 0 /**< Shift value for LESENSE_EVALTHRES */ -#define _LESENSE_CH_EVALTHRES_EVALTHRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_EVALTHRES */ -#define _LESENSE_CH_EVALTHRES_EVALTHRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALTHRES */ -#define LESENSE_CH_EVALTHRES_EVALTHRES_DEFAULT (_LESENSE_CH_EVALTHRES_EVALTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_EVALTHRES*/ +#define _LESENSE_CH_EVALTHRES_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_EVALTHRES */ +#define _LESENSE_CH_EVALTHRES_MASK 0x0000FFFFUL /**< Mask for LESENSE_CH_EVALTHRES */ +#define _LESENSE_CH_EVALTHRES_EVALTHRES_SHIFT 0 /**< Shift value for LESENSE_EVALTHRES */ +#define _LESENSE_CH_EVALTHRES_EVALTHRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_EVALTHRES */ +#define _LESENSE_CH_EVALTHRES_EVALTHRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALTHRES */ +#define LESENSE_CH_EVALTHRES_EVALTHRES_DEFAULT (_LESENSE_CH_EVALTHRES_EVALTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_EVALTHRES*/ /* Bit fields for LESENSE ST_ARC */ -#define _LESENSE_ST_ARC_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_MASK 0x003FFFFFUL /**< Mask for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_SCOMP_SHIFT 0 /**< Shift value for LESENSE_SCOMP */ -#define _LESENSE_ST_ARC_SCOMP_MASK 0xFUL /**< Bit mask for LESENSE_SCOMP */ -#define _LESENSE_ST_ARC_SCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_SCOMP_DEFAULT (_LESENSE_ST_ARC_SCOMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_SMASK_SHIFT 4 /**< Shift value for LESENSE_SMASK */ -#define _LESENSE_ST_ARC_SMASK_MASK 0xF0UL /**< Bit mask for LESENSE_SMASK */ -#define _LESENSE_ST_ARC_SMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_SMASK_DEFAULT (_LESENSE_ST_ARC_SMASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_CURSTATE_SHIFT 8 /**< Shift value for LESENSE_CURSTATE */ -#define _LESENSE_ST_ARC_CURSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_CURSTATE */ -#define _LESENSE_ST_ARC_CURSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_CURSTATE_DEFAULT (_LESENSE_ST_ARC_CURSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_SHIFT 13 /**< Shift value for LESENSE_PRSACT */ -#define _LESENSE_ST_ARC_PRSACT_MASK 0xE000UL /**< Bit mask for LESENSE_PRSACT */ -#define _LESENSE_ST_ARC_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_DEFAULT (_LESENSE_ST_ARC_PRSACT_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_NONE (_LESENSE_ST_ARC_PRSACT_NONE << 13) /**< Shifted mode NONE for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_PRS0 (_LESENSE_ST_ARC_PRSACT_PRS0 << 13) /**< Shifted mode PRS0 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_UP (_LESENSE_ST_ARC_PRSACT_UP << 13) /**< Shifted mode UP for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_PRS1 (_LESENSE_ST_ARC_PRSACT_PRS1 << 13) /**< Shifted mode PRS1 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_DOWN (_LESENSE_ST_ARC_PRSACT_DOWN << 13) /**< Shifted mode DOWN for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_PRS01 (_LESENSE_ST_ARC_PRSACT_PRS01 << 13) /**< Shifted mode PRS01 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_PRS2 (_LESENSE_ST_ARC_PRSACT_PRS2 << 13) /**< Shifted mode PRS2 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_PRS02 (_LESENSE_ST_ARC_PRSACT_PRS02 << 13) /**< Shifted mode PRS02 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_UPANDPRS2 (_LESENSE_ST_ARC_PRSACT_UPANDPRS2 << 13) /**< Shifted mode UPANDPRS2 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_PRS12 (_LESENSE_ST_ARC_PRSACT_PRS12 << 13) /**< Shifted mode PRS12 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_DOWNANDPRS2 (_LESENSE_ST_ARC_PRSACT_DOWNANDPRS2 << 13) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_PRS012 (_LESENSE_ST_ARC_PRSACT_PRS012 << 13) /**< Shifted mode PRS012 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_NEXTSTATE_SHIFT 16 /**< Shift value for LESENSE_NEXTSTATE */ -#define _LESENSE_ST_ARC_NEXTSTATE_MASK 0x1F0000UL /**< Bit mask for LESENSE_NEXTSTATE */ -#define _LESENSE_ST_ARC_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_NEXTSTATE_DEFAULT (_LESENSE_ST_ARC_NEXTSTATE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_SETIF (0x1UL << 21) /**< Set interrupt flag */ -#define _LESENSE_ST_ARC_SETIF_SHIFT 21 /**< Shift value for LESENSE_SETIF */ -#define _LESENSE_ST_ARC_SETIF_MASK 0x200000UL /**< Bit mask for LESENSE_SETIF */ -#define _LESENSE_ST_ARC_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_SETIF_DEFAULT (_LESENSE_ST_ARC_SETIF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_MASK 0x003FFFFFUL /**< Mask for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_SCOMP_SHIFT 0 /**< Shift value for LESENSE_SCOMP */ +#define _LESENSE_ST_ARC_SCOMP_MASK 0xFUL /**< Bit mask for LESENSE_SCOMP */ +#define _LESENSE_ST_ARC_SCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_SCOMP_DEFAULT (_LESENSE_ST_ARC_SCOMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_SMASK_SHIFT 4 /**< Shift value for LESENSE_SMASK */ +#define _LESENSE_ST_ARC_SMASK_MASK 0xF0UL /**< Bit mask for LESENSE_SMASK */ +#define _LESENSE_ST_ARC_SMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_SMASK_DEFAULT (_LESENSE_ST_ARC_SMASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_CURSTATE_SHIFT 8 /**< Shift value for LESENSE_CURSTATE */ +#define _LESENSE_ST_ARC_CURSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_CURSTATE */ +#define _LESENSE_ST_ARC_CURSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_CURSTATE_DEFAULT (_LESENSE_ST_ARC_CURSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_SHIFT 13 /**< Shift value for LESENSE_PRSACT */ +#define _LESENSE_ST_ARC_PRSACT_MASK 0xE000UL /**< Bit mask for LESENSE_PRSACT */ +#define _LESENSE_ST_ARC_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_DEFAULT (_LESENSE_ST_ARC_PRSACT_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_NONE (_LESENSE_ST_ARC_PRSACT_NONE << 13) /**< Shifted mode NONE for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS0 (_LESENSE_ST_ARC_PRSACT_PRS0 << 13) /**< Shifted mode PRS0 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_UP (_LESENSE_ST_ARC_PRSACT_UP << 13) /**< Shifted mode UP for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS1 (_LESENSE_ST_ARC_PRSACT_PRS1 << 13) /**< Shifted mode PRS1 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_DOWN (_LESENSE_ST_ARC_PRSACT_DOWN << 13) /**< Shifted mode DOWN for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS01 (_LESENSE_ST_ARC_PRSACT_PRS01 << 13) /**< Shifted mode PRS01 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS2 (_LESENSE_ST_ARC_PRSACT_PRS2 << 13) /**< Shifted mode PRS2 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS02 (_LESENSE_ST_ARC_PRSACT_PRS02 << 13) /**< Shifted mode PRS02 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_UPANDPRS2 (_LESENSE_ST_ARC_PRSACT_UPANDPRS2 << 13) /**< Shifted mode UPANDPRS2 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS12 (_LESENSE_ST_ARC_PRSACT_PRS12 << 13) /**< Shifted mode PRS12 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_DOWNANDPRS2 (_LESENSE_ST_ARC_PRSACT_DOWNANDPRS2 << 13) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS012 (_LESENSE_ST_ARC_PRSACT_PRS012 << 13) /**< Shifted mode PRS012 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_NEXTSTATE_SHIFT 16 /**< Shift value for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_ARC_NEXTSTATE_MASK 0x1F0000UL /**< Bit mask for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_ARC_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_NEXTSTATE_DEFAULT (_LESENSE_ST_ARC_NEXTSTATE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_SETIF (0x1UL << 21) /**< Set interrupt flag */ +#define _LESENSE_ST_ARC_SETIF_SHIFT 21 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_ST_ARC_SETIF_MASK 0x200000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_ST_ARC_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_SETIF_DEFAULT (_LESENSE_ST_ARC_SETIF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ /** @} End of group EFR32SG23_LESENSE_BitFields */ /** @} End of group EFR32SG23_LESENSE */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_letimer.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_letimer.h index 4170ca5115..a4fe53651c 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_letimer.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_letimer.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_LETIMER_H #define EFR32SG23_LETIMER_H - #define LETIMER_HAS_SET_CLEAR /**************************************************************************//** @@ -43,87 +42,86 @@ *****************************************************************************/ /** LETIMER Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version */ - __IOM uint32_t EN; /**< module en */ - __IOM uint32_t SWRST; /**< Software Reset Register */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t CNT; /**< Counter Value Register */ - __IOM uint32_t COMP0; /**< Compare Value Register 0 */ - __IOM uint32_t COMP1; /**< Compare Value Register 1 */ - __IOM uint32_t TOP; /**< Counter TOP Value Register */ - __IOM uint32_t TOPBUFF; /**< Buffered Counter TOP Value */ - __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ - __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - __IOM uint32_t PRSMODE; /**< PRS Input mode select Register */ - uint32_t RESERVED1[1003U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version */ - __IOM uint32_t EN_SET; /**< module en */ - __IOM uint32_t SWRST_SET; /**< Software Reset Register */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t CNT_SET; /**< Counter Value Register */ - __IOM uint32_t COMP0_SET; /**< Compare Value Register 0 */ - __IOM uint32_t COMP1_SET; /**< Compare Value Register 1 */ - __IOM uint32_t TOP_SET; /**< Counter TOP Value Register */ - __IOM uint32_t TOPBUFF_SET; /**< Buffered Counter TOP Value */ - __IOM uint32_t REP0_SET; /**< Repeat Counter Register 0 */ - __IOM uint32_t REP1_SET; /**< Repeat Counter Register 1 */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - uint32_t RESERVED2[3U]; /**< Reserved for future use */ - __IOM uint32_t PRSMODE_SET; /**< PRS Input mode select Register */ - uint32_t RESERVED3[1003U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version */ - __IOM uint32_t EN_CLR; /**< module en */ - __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t CNT_CLR; /**< Counter Value Register */ - __IOM uint32_t COMP0_CLR; /**< Compare Value Register 0 */ - __IOM uint32_t COMP1_CLR; /**< Compare Value Register 1 */ - __IOM uint32_t TOP_CLR; /**< Counter TOP Value Register */ - __IOM uint32_t TOPBUFF_CLR; /**< Buffered Counter TOP Value */ - __IOM uint32_t REP0_CLR; /**< Repeat Counter Register 0 */ - __IOM uint32_t REP1_CLR; /**< Repeat Counter Register 1 */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - uint32_t RESERVED4[3U]; /**< Reserved for future use */ - __IOM uint32_t PRSMODE_CLR; /**< PRS Input mode select Register */ - uint32_t RESERVED5[1003U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version */ - __IOM uint32_t EN_TGL; /**< module en */ - __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t CNT_TGL; /**< Counter Value Register */ - __IOM uint32_t COMP0_TGL; /**< Compare Value Register 0 */ - __IOM uint32_t COMP1_TGL; /**< Compare Value Register 1 */ - __IOM uint32_t TOP_TGL; /**< Counter TOP Value Register */ - __IOM uint32_t TOPBUFF_TGL; /**< Buffered Counter TOP Value */ - __IOM uint32_t REP0_TGL; /**< Repeat Counter Register 0 */ - __IOM uint32_t REP1_TGL; /**< Repeat Counter Register 1 */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - uint32_t RESERVED6[3U]; /**< Reserved for future use */ - __IOM uint32_t PRSMODE_TGL; /**< PRS Input mode select Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t EN; /**< module en */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t COMP0; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1; /**< Compare Value Register 1 */ + __IOM uint32_t TOP; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE; /**< PRS Input mode select Register */ + uint32_t RESERVED1[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t EN_SET; /**< module en */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t COMP0_SET; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_SET; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_SET; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_SET; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_SET; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_SET; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_SET; /**< PRS Input mode select Register */ + uint32_t RESERVED3[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t EN_CLR; /**< module en */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t COMP0_CLR; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_CLR; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_CLR; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_CLR; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_CLR; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_CLR; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_CLR; /**< PRS Input mode select Register */ + uint32_t RESERVED5[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t EN_TGL; /**< module en */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t COMP0_TGL; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_TGL; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_TGL; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_TGL; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_TGL; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_TGL; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_TGL; /**< PRS Input mode select Register */ } LETIMER_TypeDef; /** @} End of group EFR32SG23_LETIMER */ @@ -135,399 +133,399 @@ typedef struct *****************************************************************************/ /* Bit fields for LETIMER IPVERSION */ -#define _LETIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LETIMER_IPVERSION */ -#define _LETIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LETIMER_IPVERSION */ -#define _LETIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LETIMER_IPVERSION */ -#define _LETIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LETIMER_IPVERSION */ -#define _LETIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LETIMER_IPVERSION */ -#define LETIMER_IPVERSION_IPVERSION_DEFAULT (_LETIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LETIMER_IPVERSION */ +#define LETIMER_IPVERSION_IPVERSION_DEFAULT (_LETIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IPVERSION */ /* Bit fields for LETIMER EN */ -#define _LETIMER_EN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_EN */ -#define _LETIMER_EN_MASK 0x00000003UL /**< Mask for LETIMER_EN */ -#define LETIMER_EN_EN (0x1UL << 0) /**< module en */ -#define _LETIMER_EN_EN_SHIFT 0 /**< Shift value for LETIMER_EN */ -#define _LETIMER_EN_EN_MASK 0x1UL /**< Bit mask for LETIMER_EN */ -#define _LETIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ -#define LETIMER_EN_EN_DEFAULT (_LETIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_EN */ -#define LETIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _LETIMER_EN_DISABLING_SHIFT 1 /**< Shift value for LETIMER_DISABLING */ -#define _LETIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for LETIMER_DISABLING */ -#define _LETIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ -#define LETIMER_EN_DISABLING_DEFAULT (_LETIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_EN */ +#define _LETIMER_EN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_EN */ +#define _LETIMER_EN_MASK 0x00000003UL /**< Mask for LETIMER_EN */ +#define LETIMER_EN_EN (0x1UL << 0) /**< module en */ +#define _LETIMER_EN_EN_SHIFT 0 /**< Shift value for LETIMER_EN */ +#define _LETIMER_EN_EN_MASK 0x1UL /**< Bit mask for LETIMER_EN */ +#define _LETIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_EN_DEFAULT (_LETIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _LETIMER_EN_DISABLING_SHIFT 1 /**< Shift value for LETIMER_DISABLING */ +#define _LETIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for LETIMER_DISABLING */ +#define _LETIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_DISABLING_DEFAULT (_LETIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_EN */ /* Bit fields for LETIMER SWRST */ -#define _LETIMER_SWRST_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SWRST */ -#define _LETIMER_SWRST_MASK 0x00000003UL /**< Mask for LETIMER_SWRST */ -#define LETIMER_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ -#define _LETIMER_SWRST_SWRST_SHIFT 0 /**< Shift value for LETIMER_SWRST */ -#define _LETIMER_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LETIMER_SWRST */ -#define _LETIMER_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ -#define LETIMER_SWRST_SWRST_DEFAULT (_LETIMER_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SWRST */ -#define LETIMER_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ -#define _LETIMER_SWRST_RESETTING_SHIFT 1 /**< Shift value for LETIMER_RESETTING */ -#define _LETIMER_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LETIMER_RESETTING */ -#define _LETIMER_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ -#define LETIMER_SWRST_RESETTING_DEFAULT (_LETIMER_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SWRST */ +#define _LETIMER_SWRST_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SWRST */ +#define _LETIMER_SWRST_MASK 0x00000003UL /**< Mask for LETIMER_SWRST */ +#define LETIMER_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _LETIMER_SWRST_SWRST_SHIFT 0 /**< Shift value for LETIMER_SWRST */ +#define _LETIMER_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LETIMER_SWRST */ +#define _LETIMER_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_SWRST_DEFAULT (_LETIMER_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _LETIMER_SWRST_RESETTING_SHIFT 1 /**< Shift value for LETIMER_RESETTING */ +#define _LETIMER_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LETIMER_RESETTING */ +#define _LETIMER_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_RESETTING_DEFAULT (_LETIMER_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SWRST */ /* Bit fields for LETIMER CTRL */ -#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ -#define _LETIMER_CTRL_MASK 0x000F13FFUL /**< Mask for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ -#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ -#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ -#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ -#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ -#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ -#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ -#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ -#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ -#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ -#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ -#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ -#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ -#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ -#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ -#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ -#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_BUFTOP_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_BUFTOP_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_BUFTOP_DISABLE (_LETIMER_CTRL_BUFTOP_DISABLE << 8) /**< Shifted mode DISABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_BUFTOP_ENABLE (_LETIMER_CTRL_BUFTOP_ENABLE << 8) /**< Shifted mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTTOPEN (0x1UL << 9) /**< Compare Value 0 Is Top Value */ -#define _LETIMER_CTRL_CNTTOPEN_SHIFT 9 /**< Shift value for LETIMER_CNTTOPEN */ -#define _LETIMER_CTRL_CNTTOPEN_MASK 0x200UL /**< Bit mask for LETIMER_CNTTOPEN */ -#define _LETIMER_CTRL_CNTTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTTOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTTOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTTOPEN_DEFAULT (_LETIMER_CTRL_CNTTOPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTTOPEN_DISABLE (_LETIMER_CTRL_CNTTOPEN_DISABLE << 9) /**< Shifted mode DISABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTTOPEN_ENABLE (_LETIMER_CTRL_CNTTOPEN_ENABLE << 9) /**< Shifted mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ -#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ -#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ -#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUGRUN_DISABLE (_LETIMER_CTRL_DEBUGRUN_DISABLE << 12) /**< Shifted mode DISABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUGRUN_ENABLE (_LETIMER_CTRL_DEBUGRUN_ENABLE << 12) /**< Shifted mode ENABLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_SHIFT 16 /**< Shift value for LETIMER_CNTPRESC */ -#define _LETIMER_CTRL_CNTPRESC_MASK 0xF0000UL /**< Bit mask for LETIMER_CNTPRESC */ -#define _LETIMER_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DEFAULT (_LETIMER_CTRL_CNTPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV1 (_LETIMER_CTRL_CNTPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV2 (_LETIMER_CTRL_CNTPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV4 (_LETIMER_CTRL_CNTPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV8 (_LETIMER_CTRL_CNTPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV16 (_LETIMER_CTRL_CNTPRESC_DIV16 << 16) /**< Shifted mode DIV16 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV32 (_LETIMER_CTRL_CNTPRESC_DIV32 << 16) /**< Shifted mode DIV32 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV64 (_LETIMER_CTRL_CNTPRESC_DIV64 << 16) /**< Shifted mode DIV64 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV128 (_LETIMER_CTRL_CNTPRESC_DIV128 << 16) /**< Shifted mode DIV128 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV256 (_LETIMER_CTRL_CNTPRESC_DIV256 << 16) /**< Shifted mode DIV256 for LETIMER_CTRL */ +#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ +#define _LETIMER_CTRL_MASK 0x000F13FFUL /**< Mask for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ +#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ +#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ +#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DISABLE (_LETIMER_CTRL_BUFTOP_DISABLE << 8) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_ENABLE (_LETIMER_CTRL_BUFTOP_ENABLE << 8) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN (0x1UL << 9) /**< Compare Value 0 Is Top Value */ +#define _LETIMER_CTRL_CNTTOPEN_SHIFT 9 /**< Shift value for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_MASK 0x200UL /**< Bit mask for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DEFAULT (_LETIMER_CTRL_CNTTOPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DISABLE (_LETIMER_CTRL_CNTTOPEN_DISABLE << 9) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_ENABLE (_LETIMER_CTRL_CNTTOPEN_ENABLE << 9) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ +#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DISABLE (_LETIMER_CTRL_DEBUGRUN_DISABLE << 12) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_ENABLE (_LETIMER_CTRL_DEBUGRUN_ENABLE << 12) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_SHIFT 16 /**< Shift value for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_MASK 0xF0000UL /**< Bit mask for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DEFAULT (_LETIMER_CTRL_CNTPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV1 (_LETIMER_CTRL_CNTPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV2 (_LETIMER_CTRL_CNTPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV4 (_LETIMER_CTRL_CNTPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV8 (_LETIMER_CTRL_CNTPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV16 (_LETIMER_CTRL_CNTPRESC_DIV16 << 16) /**< Shifted mode DIV16 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV32 (_LETIMER_CTRL_CNTPRESC_DIV32 << 16) /**< Shifted mode DIV32 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV64 (_LETIMER_CTRL_CNTPRESC_DIV64 << 16) /**< Shifted mode DIV64 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV128 (_LETIMER_CTRL_CNTPRESC_DIV128 << 16) /**< Shifted mode DIV128 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV256 (_LETIMER_CTRL_CNTPRESC_DIV256 << 16) /**< Shifted mode DIV256 for LETIMER_CTRL */ /* Bit fields for LETIMER CMD */ -#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ -#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ -#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ -#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ -#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ -#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ -#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ -#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ -#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ -#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ -#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ -#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ -#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ -#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ -#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ -#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ -#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ -#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ +#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ +#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ +#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ +#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ +#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ +#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ +#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ +#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ /* Bit fields for LETIMER STATUS */ -#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ -#define _LETIMER_STATUS_MASK 0x00000003UL /**< Mask for LETIMER_STATUS */ -#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ -#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ -#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ -#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ -#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ -#define LETIMER_STATUS_LETIMERLOCKSTATUS (0x1UL << 1) /**< LETIMER Lock Status */ -#define _LETIMER_STATUS_LETIMERLOCKSTATUS_SHIFT 1 /**< Shift value for LETIMER_LETIMERLOCKSTATUS */ -#define _LETIMER_STATUS_LETIMERLOCKSTATUS_MASK 0x2UL /**< Bit mask for LETIMER_LETIMERLOCKSTATUS */ -#define _LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ -#define _LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LETIMER_STATUS */ -#define _LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for LETIMER_STATUS */ -#define LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT (_LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_STATUS */ -#define LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for LETIMER_STATUS */ -#define LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for LETIMER_STATUS */ +#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ +#define _LETIMER_STATUS_MASK 0x00000003UL /**< Mask for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ +#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS (0x1UL << 1) /**< LETIMER Lock Status */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_SHIFT 1 /**< Shift value for LETIMER_LETIMERLOCKSTATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_MASK 0x2UL /**< Bit mask for LETIMER_LETIMERLOCKSTATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LETIMER_STATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT (_LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for LETIMER_STATUS */ /* Bit fields for LETIMER CNT */ -#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ -#define _LETIMER_CNT_MASK 0x00FFFFFFUL /**< Mask for LETIMER_CNT */ -#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ -#define _LETIMER_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_CNT */ -#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ -#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ +#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ +#define _LETIMER_CNT_MASK 0x00FFFFFFUL /**< Mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ +#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ /* Bit fields for LETIMER COMP0 */ -#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ -#define _LETIMER_COMP0_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP0 */ -#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ -#define _LETIMER_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP0 */ -#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ -#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ +#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ +#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ /* Bit fields for LETIMER COMP1 */ -#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ -#define _LETIMER_COMP1_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP1 */ -#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ -#define _LETIMER_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP1 */ -#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ -#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ +#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ +#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ /* Bit fields for LETIMER TOP */ -#define _LETIMER_TOP_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOP */ -#define _LETIMER_TOP_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOP */ -#define _LETIMER_TOP_TOP_SHIFT 0 /**< Shift value for LETIMER_TOP */ -#define _LETIMER_TOP_TOP_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOP */ -#define _LETIMER_TOP_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOP */ -#define LETIMER_TOP_TOP_DEFAULT (_LETIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOP */ +#define _LETIMER_TOP_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOP */ +#define _LETIMER_TOP_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_SHIFT 0 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOP */ +#define LETIMER_TOP_TOP_DEFAULT (_LETIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOP */ /* Bit fields for LETIMER TOPBUFF */ -#define _LETIMER_TOPBUFF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOPBUFF */ -#define _LETIMER_TOPBUFF_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOPBUFF */ -#define _LETIMER_TOPBUFF_TOPBUFF_SHIFT 0 /**< Shift value for LETIMER_TOPBUFF */ -#define _LETIMER_TOPBUFF_TOPBUFF_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOPBUFF */ -#define _LETIMER_TOPBUFF_TOPBUFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOPBUFF */ -#define LETIMER_TOPBUFF_TOPBUFF_DEFAULT (_LETIMER_TOPBUFF_TOPBUFF_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_SHIFT 0 /**< Shift value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOPBUFF */ +#define LETIMER_TOPBUFF_TOPBUFF_DEFAULT (_LETIMER_TOPBUFF_TOPBUFF_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOPBUFF */ /* Bit fields for LETIMER REP0 */ -#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ -#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ -#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ -#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ -#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ -#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ +#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ +#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ +#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ /* Bit fields for LETIMER REP1 */ -#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ -#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ -#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ -#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ -#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ -#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ +#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ +#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ +#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ /* Bit fields for LETIMER IF */ -#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ -#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ -#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ -#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ -#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ -#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ -#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ -#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ -#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ -#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ -#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ -#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ -#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ -#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ -#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ -#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ -#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ -#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ +#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ +#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ +#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ +#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ +#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ /* Bit fields for LETIMER IEN */ -#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ -#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ -#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Enable */ -#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ -#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ -#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Enable */ -#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ -#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ -#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_UF (0x1UL << 2) /**< Underflow Interrupt Enable */ -#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ -#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ -#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Enable */ -#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ -#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ -#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Enable */ -#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ -#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ -#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ +#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ +#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Enable */ +#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Enable */ +#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF (0x1UL << 2) /**< Underflow Interrupt Enable */ +#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Enable */ +#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Enable */ +#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ /* Bit fields for LETIMER LOCK */ -#define _LETIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for LETIMER_LOCK */ -#define _LETIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for LETIMER_LOCK */ -#define _LETIMER_LOCK_LETIMERLOCKKEY_SHIFT 0 /**< Shift value for LETIMER_LETIMERLOCKKEY */ -#define _LETIMER_LOCK_LETIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for LETIMER_LETIMERLOCKKEY */ -#define _LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_LOCK */ -#define _LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK 0x0000CCFCUL /**< Mode UNLOCK for LETIMER_LOCK */ -#define LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT (_LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_LOCK */ -#define LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK (_LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LETIMER_LOCK */ +#define _LETIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for LETIMER_LOCK */ +#define _LETIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for LETIMER_LOCK */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_SHIFT 0 /**< Shift value for LETIMER_LETIMERLOCKKEY */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for LETIMER_LETIMERLOCKKEY */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_LOCK */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK 0x0000CCFCUL /**< Mode UNLOCK for LETIMER_LOCK */ +#define LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT (_LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_LOCK */ +#define LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK (_LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LETIMER_LOCK */ /* Bit fields for LETIMER SYNCBUSY */ -#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ -#define _LETIMER_SYNCBUSY_MASK 0x000003FDUL /**< Mask for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CNT (0x1UL << 0) /**< Sync busy for CNT */ -#define _LETIMER_SYNCBUSY_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ -#define _LETIMER_SYNCBUSY_CNT_MASK 0x1UL /**< Bit mask for LETIMER_CNT */ -#define _LETIMER_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CNT_DEFAULT (_LETIMER_SYNCBUSY_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_TOP (0x1UL << 2) /**< Sync busy for TOP */ -#define _LETIMER_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for LETIMER_TOP */ -#define _LETIMER_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for LETIMER_TOP */ -#define _LETIMER_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_TOP_DEFAULT (_LETIMER_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP0 (0x1UL << 3) /**< Sync busy for REP0 */ -#define _LETIMER_SYNCBUSY_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ -#define _LETIMER_SYNCBUSY_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ -#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP1 (0x1UL << 4) /**< Sync busy for REP1 */ -#define _LETIMER_SYNCBUSY_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ -#define _LETIMER_SYNCBUSY_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ -#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_START (0x1UL << 5) /**< Sync busy for START */ -#define _LETIMER_SYNCBUSY_START_SHIFT 5 /**< Shift value for LETIMER_START */ -#define _LETIMER_SYNCBUSY_START_MASK 0x20UL /**< Bit mask for LETIMER_START */ -#define _LETIMER_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_START_DEFAULT (_LETIMER_SYNCBUSY_START_DEFAULT << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_STOP (0x1UL << 6) /**< Sync busy for STOP */ -#define _LETIMER_SYNCBUSY_STOP_SHIFT 6 /**< Shift value for LETIMER_STOP */ -#define _LETIMER_SYNCBUSY_STOP_MASK 0x40UL /**< Bit mask for LETIMER_STOP */ -#define _LETIMER_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_STOP_DEFAULT (_LETIMER_SYNCBUSY_STOP_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CLEAR (0x1UL << 7) /**< Sync busy for CLEAR */ -#define _LETIMER_SYNCBUSY_CLEAR_SHIFT 7 /**< Shift value for LETIMER_CLEAR */ -#define _LETIMER_SYNCBUSY_CLEAR_MASK 0x80UL /**< Bit mask for LETIMER_CLEAR */ -#define _LETIMER_SYNCBUSY_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CLEAR_DEFAULT (_LETIMER_SYNCBUSY_CLEAR_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CTO0 (0x1UL << 8) /**< Sync busy for CTO0 */ -#define _LETIMER_SYNCBUSY_CTO0_SHIFT 8 /**< Shift value for LETIMER_CTO0 */ -#define _LETIMER_SYNCBUSY_CTO0_MASK 0x100UL /**< Bit mask for LETIMER_CTO0 */ -#define _LETIMER_SYNCBUSY_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CTO0_DEFAULT (_LETIMER_SYNCBUSY_CTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CTO1 (0x1UL << 9) /**< Sync busy for CTO1 */ -#define _LETIMER_SYNCBUSY_CTO1_SHIFT 9 /**< Shift value for LETIMER_CTO1 */ -#define _LETIMER_SYNCBUSY_CTO1_MASK 0x200UL /**< Bit mask for LETIMER_CTO1 */ -#define _LETIMER_SYNCBUSY_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CTO1_DEFAULT (_LETIMER_SYNCBUSY_CTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_MASK 0x000003FDUL /**< Mask for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT (0x1UL << 0) /**< Sync busy for CNT */ +#define _LETIMER_SYNCBUSY_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_MASK 0x1UL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT_DEFAULT (_LETIMER_SYNCBUSY_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP (0x1UL << 2) /**< Sync busy for TOP */ +#define _LETIMER_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP_DEFAULT (_LETIMER_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0 (0x1UL << 3) /**< Sync busy for REP0 */ +#define _LETIMER_SYNCBUSY_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1 (0x1UL << 4) /**< Sync busy for REP1 */ +#define _LETIMER_SYNCBUSY_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START (0x1UL << 5) /**< Sync busy for START */ +#define _LETIMER_SYNCBUSY_START_SHIFT 5 /**< Shift value for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_MASK 0x20UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START_DEFAULT (_LETIMER_SYNCBUSY_START_DEFAULT << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP (0x1UL << 6) /**< Sync busy for STOP */ +#define _LETIMER_SYNCBUSY_STOP_SHIFT 6 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_MASK 0x40UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP_DEFAULT (_LETIMER_SYNCBUSY_STOP_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR (0x1UL << 7) /**< Sync busy for CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_SHIFT 7 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_MASK 0x80UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR_DEFAULT (_LETIMER_SYNCBUSY_CLEAR_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0 (0x1UL << 8) /**< Sync busy for CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_SHIFT 8 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_MASK 0x100UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0_DEFAULT (_LETIMER_SYNCBUSY_CTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1 (0x1UL << 9) /**< Sync busy for CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_SHIFT 9 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_MASK 0x200UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1_DEFAULT (_LETIMER_SYNCBUSY_CTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ /* Bit fields for LETIMER PRSMODE */ -#define _LETIMER_PRSMODE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_MASK 0x0CCC0000UL /**< Mask for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_NONE (_LETIMER_PRSMODE_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_RISING (_LETIMER_PRSMODE_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_FALLING (_LETIMER_PRSMODE_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_BOTH (_LETIMER_PRSMODE_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_NONE (_LETIMER_PRSMODE_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_RISING (_LETIMER_PRSMODE_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_FALLING (_LETIMER_PRSMODE_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_BOTH (_LETIMER_PRSMODE_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT (_LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_NONE (_LETIMER_PRSMODE_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_RISING (_LETIMER_PRSMODE_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_FALLING (_LETIMER_PRSMODE_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_BOTH (_LETIMER_PRSMODE_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_MASK 0x0CCC0000UL /**< Mask for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_NONE (_LETIMER_PRSMODE_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_RISING (_LETIMER_PRSMODE_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_FALLING (_LETIMER_PRSMODE_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_BOTH (_LETIMER_PRSMODE_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_NONE (_LETIMER_PRSMODE_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_RISING (_LETIMER_PRSMODE_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_FALLING (_LETIMER_PRSMODE_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_BOTH (_LETIMER_PRSMODE_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT (_LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_NONE (_LETIMER_PRSMODE_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_RISING (_LETIMER_PRSMODE_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_FALLING (_LETIMER_PRSMODE_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_BOTH (_LETIMER_PRSMODE_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSMODE */ /** @} End of group EFR32SG23_LETIMER_BitFields */ /** @} End of group EFR32SG23_LETIMER */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lfrco.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lfrco.h index b1ef889bd5..0216ce9279 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lfrco.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_LFRCO_H #define EFR32SG23_LFRCO_H - #define LFRCO_HAS_SET_CLEAR /**************************************************************************//** @@ -43,47 +42,46 @@ *****************************************************************************/ /** LFRCO Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t CAL; /**< Calibration Register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - uint32_t RESERVED2[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t CAL_SET; /**< Calibration Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - uint32_t RESERVED5[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t CAL_CLR; /**< Calibration Register */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - uint32_t RESERVED8[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t CAL_TGL; /**< Calibration Register */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CAL; /**< Calibration Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CAL_SET; /**< Calibration Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED5[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CAL_CLR; /**< Calibration Register */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED8[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CAL_TGL; /**< Calibration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ } LFRCO_TypeDef; /** @} End of group EFR32SG23_LFRCO */ @@ -95,102 +93,102 @@ typedef struct *****************************************************************************/ /* Bit fields for LFRCO IPVERSION */ -#define _LFRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IPVERSION */ -#define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */ -#define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */ -#define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */ -#define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IPVERSION */ -#define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IPVERSION */ +#define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */ /* Bit fields for LFRCO STATUS */ -#define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */ -#define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */ -#define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ -#define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ -#define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ -#define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ -#define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */ -#define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */ -#define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ -#define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */ -#define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */ -#define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ -#define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */ -#define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */ -#define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */ -#define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */ +#define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */ +#define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */ /* Bit fields for LFRCO CAL */ -#define _LFRCO_CAL_RESETVALUE 0x000000A5UL /**< Default value for LFRCO_CAL */ -#define _LFRCO_CAL_MASK 0x000000FFUL /**< Mask for LFRCO_CAL */ -#define _LFRCO_CAL_FREQTRIM_SHIFT 0 /**< Shift value for LFRCO_FREQTRIM */ -#define _LFRCO_CAL_FREQTRIM_MASK 0xFFUL /**< Bit mask for LFRCO_FREQTRIM */ -#define _LFRCO_CAL_FREQTRIM_DEFAULT 0x000000A5UL /**< Mode DEFAULT for LFRCO_CAL */ -#define LFRCO_CAL_FREQTRIM_DEFAULT (_LFRCO_CAL_FREQTRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CAL */ +#define _LFRCO_CAL_RESETVALUE 0x000000A5UL /**< Default value for LFRCO_CAL */ +#define _LFRCO_CAL_MASK 0x000000FFUL /**< Mask for LFRCO_CAL */ +#define _LFRCO_CAL_FREQTRIM_SHIFT 0 /**< Shift value for LFRCO_FREQTRIM */ +#define _LFRCO_CAL_FREQTRIM_MASK 0xFFUL /**< Bit mask for LFRCO_FREQTRIM */ +#define _LFRCO_CAL_FREQTRIM_DEFAULT 0x000000A5UL /**< Mode DEFAULT for LFRCO_CAL */ +#define LFRCO_CAL_FREQTRIM_DEFAULT (_LFRCO_CAL_FREQTRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CAL */ /* Bit fields for LFRCO IF */ -#define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */ -#define _LFRCO_IF_MASK 0x00000007UL /**< Mask for LFRCO_IF */ -#define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ -#define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ -#define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ -#define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ -#define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ -#define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ -#define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ -#define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ -#define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ -#define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */ +#define _LFRCO_IF_MASK 0x00000007UL /**< Mask for LFRCO_IF */ +#define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ +#define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ +#define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */ /* Bit fields for LFRCO IEN */ -#define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */ -#define _LFRCO_IEN_MASK 0x00000007UL /**< Mask for LFRCO_IEN */ -#define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Interrupt Enable */ -#define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ -#define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ -#define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ -#define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ -#define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ -#define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ -#define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ -#define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ -#define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */ +#define _LFRCO_IEN_MASK 0x00000007UL /**< Mask for LFRCO_IEN */ +#define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Interrupt Enable */ +#define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ +#define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ +#define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */ /* Bit fields for LFRCO SYNCBUSY */ -#define _LFRCO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFRCO_SYNCBUSY */ -#define _LFRCO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFRCO_SYNCBUSY */ -#define LFRCO_SYNCBUSY_CAL (0x1UL << 0) /**< CAL Busy */ -#define _LFRCO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFRCO_CAL */ -#define _LFRCO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFRCO_CAL */ -#define _LFRCO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_SYNCBUSY */ -#define LFRCO_SYNCBUSY_CAL_DEFAULT (_LFRCO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_SYNCBUSY */ +#define _LFRCO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFRCO_SYNCBUSY */ +#define _LFRCO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFRCO_SYNCBUSY */ +#define LFRCO_SYNCBUSY_CAL (0x1UL << 0) /**< CAL Busy */ +#define _LFRCO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFRCO_CAL */ +#define _LFRCO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFRCO_CAL */ +#define _LFRCO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_SYNCBUSY */ +#define LFRCO_SYNCBUSY_CAL_DEFAULT (_LFRCO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_SYNCBUSY */ /* Bit fields for LFRCO LOCK */ -#define _LFRCO_LOCK_RESETVALUE 0x00002603UL /**< Default value for LFRCO_LOCK */ -#define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */ -#define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */ -#define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */ -#define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00002603UL /**< Mode DEFAULT for LFRCO_LOCK */ -#define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */ -#define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00002603UL /**< Mode UNLOCK for LFRCO_LOCK */ -#define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */ -#define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */ -#define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */ +#define _LFRCO_LOCK_RESETVALUE 0x00002603UL /**< Default value for LFRCO_LOCK */ +#define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00002603UL /**< Mode DEFAULT for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00002603UL /**< Mode UNLOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */ /** @} End of group EFR32SG23_LFRCO_BitFields */ /** @} End of group EFR32SG23_LFRCO */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lfxo.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lfxo.h index fd40716a19..f6d29cdea7 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_lfxo.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_LFXO_H #define EFR32SG23_LFXO_H - #define LFXO_HAS_SET_CLEAR /**************************************************************************//** @@ -43,51 +42,50 @@ *****************************************************************************/ /** LFXO Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< LFXO IP version */ - __IOM uint32_t CTRL; /**< LFXO Control Register */ - __IOM uint32_t CFG; /**< LFXO Configuration Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< LFXO Status Register */ - __IOM uint32_t CAL; /**< LFXO Calibration Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY; /**< LFXO Sync Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< LFXO IP version */ - __IOM uint32_t CTRL_SET; /**< LFXO Control Register */ - __IOM uint32_t CFG_SET; /**< LFXO Configuration Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< LFXO Status Register */ - __IOM uint32_t CAL_SET; /**< LFXO Calibration Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_SET; /**< LFXO Sync Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - uint32_t RESERVED3[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< LFXO IP version */ - __IOM uint32_t CTRL_CLR; /**< LFXO Control Register */ - __IOM uint32_t CFG_CLR; /**< LFXO Configuration Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< LFXO Status Register */ - __IOM uint32_t CAL_CLR; /**< LFXO Calibration Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_CLR; /**< LFXO Sync Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - uint32_t RESERVED5[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< LFXO IP version */ - __IOM uint32_t CTRL_TGL; /**< LFXO Control Register */ - __IOM uint32_t CFG_TGL; /**< LFXO Configuration Register */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< LFXO Status Register */ - __IOM uint32_t CAL_TGL; /**< LFXO Calibration Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_TGL; /**< LFXO Sync Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< LFXO IP version */ + __IOM uint32_t CTRL; /**< LFXO Control Register */ + __IOM uint32_t CFG; /**< LFXO Configuration Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< LFXO Status Register */ + __IOM uint32_t CAL; /**< LFXO Calibration Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< LFXO IP version */ + __IOM uint32_t CTRL_SET; /**< LFXO Control Register */ + __IOM uint32_t CFG_SET; /**< LFXO Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< LFXO Status Register */ + __IOM uint32_t CAL_SET; /**< LFXO Calibration Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< LFXO IP version */ + __IOM uint32_t CTRL_CLR; /**< LFXO Control Register */ + __IOM uint32_t CFG_CLR; /**< LFXO Configuration Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< LFXO Status Register */ + __IOM uint32_t CAL_CLR; /**< LFXO Calibration Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< LFXO IP version */ + __IOM uint32_t CTRL_TGL; /**< LFXO Control Register */ + __IOM uint32_t CFG_TGL; /**< LFXO Configuration Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< LFXO Status Register */ + __IOM uint32_t CAL_TGL; /**< LFXO Calibration Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ } LFXO_TypeDef; /** @} End of group EFR32SG23_LFXO */ @@ -99,182 +97,182 @@ typedef struct *****************************************************************************/ /* Bit fields for LFXO IPVERSION */ -#define _LFXO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LFXO_IPVERSION */ -#define _LFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFXO_IPVERSION */ -#define _LFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFXO_IPVERSION */ -#define _LFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFXO_IPVERSION */ -#define _LFXO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IPVERSION */ -#define LFXO_IPVERSION_IPVERSION_DEFAULT (_LFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IPVERSION */ +#define LFXO_IPVERSION_IPVERSION_DEFAULT (_LFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IPVERSION */ /* Bit fields for LFXO CTRL */ -#define _LFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for LFXO_CTRL */ -#define _LFXO_CTRL_MASK 0x00000033UL /**< Mask for LFXO_CTRL */ -#define LFXO_CTRL_FORCEEN (0x1UL << 0) /**< LFXO Force Enable */ -#define _LFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFXO_FORCEEN */ -#define _LFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFXO_FORCEEN */ -#define _LFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FORCEEN_DEFAULT (_LFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< LFXO Disable On-demand requests */ -#define _LFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFXO_DISONDEMAND */ -#define _LFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFXO_DISONDEMAND */ -#define _LFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_DISONDEMAND_DEFAULT (_LFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FAILDETEN (0x1UL << 4) /**< LFXO Failure Detection Enable */ -#define _LFXO_CTRL_FAILDETEN_SHIFT 4 /**< Shift value for LFXO_FAILDETEN */ -#define _LFXO_CTRL_FAILDETEN_MASK 0x10UL /**< Bit mask for LFXO_FAILDETEN */ -#define _LFXO_CTRL_FAILDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FAILDETEN_DEFAULT (_LFXO_CTRL_FAILDETEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FAILDETEM4WUEN (0x1UL << 5) /**< LFXO Failure Detection EM4WU Enable */ -#define _LFXO_CTRL_FAILDETEM4WUEN_SHIFT 5 /**< Shift value for LFXO_FAILDETEM4WUEN */ -#define _LFXO_CTRL_FAILDETEM4WUEN_MASK 0x20UL /**< Bit mask for LFXO_FAILDETEM4WUEN */ -#define _LFXO_CTRL_FAILDETEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FAILDETEM4WUEN_DEFAULT (_LFXO_CTRL_FAILDETEM4WUEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define _LFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for LFXO_CTRL */ +#define _LFXO_CTRL_MASK 0x00000033UL /**< Mask for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN (0x1UL << 0) /**< LFXO Force Enable */ +#define _LFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN_DEFAULT (_LFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< LFXO Disable On-demand requests */ +#define _LFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND_DEFAULT (_LFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN (0x1UL << 4) /**< LFXO Failure Detection Enable */ +#define _LFXO_CTRL_FAILDETEN_SHIFT 4 /**< Shift value for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_MASK 0x10UL /**< Bit mask for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN_DEFAULT (_LFXO_CTRL_FAILDETEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN (0x1UL << 5) /**< LFXO Failure Detection EM4WU Enable */ +#define _LFXO_CTRL_FAILDETEM4WUEN_SHIFT 5 /**< Shift value for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_MASK 0x20UL /**< Bit mask for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN_DEFAULT (_LFXO_CTRL_FAILDETEM4WUEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LFXO_CTRL */ /* Bit fields for LFXO CFG */ -#define _LFXO_CFG_RESETVALUE 0x00000701UL /**< Default value for LFXO_CFG */ -#define _LFXO_CFG_MASK 0x00000733UL /**< Mask for LFXO_CFG */ -#define LFXO_CFG_AGC (0x1UL << 0) /**< LFXO AGC Enable */ -#define _LFXO_CFG_AGC_SHIFT 0 /**< Shift value for LFXO_AGC */ -#define _LFXO_CFG_AGC_MASK 0x1UL /**< Bit mask for LFXO_AGC */ -#define _LFXO_CFG_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_AGC_DEFAULT (_LFXO_CFG_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_HIGHAMPL (0x1UL << 1) /**< LFXO High Amplitude Enable */ -#define _LFXO_CFG_HIGHAMPL_SHIFT 1 /**< Shift value for LFXO_HIGHAMPL */ -#define _LFXO_CFG_HIGHAMPL_MASK 0x2UL /**< Bit mask for LFXO_HIGHAMPL */ -#define _LFXO_CFG_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_HIGHAMPL_DEFAULT (_LFXO_CFG_HIGHAMPL_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CFG */ -#define _LFXO_CFG_MODE_SHIFT 4 /**< Shift value for LFXO_MODE */ -#define _LFXO_CFG_MODE_MASK 0x30UL /**< Bit mask for LFXO_MODE */ -#define _LFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ -#define _LFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for LFXO_CFG */ -#define _LFXO_CFG_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for LFXO_CFG */ -#define _LFXO_CFG_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for LFXO_CFG */ -#define LFXO_CFG_MODE_DEFAULT (_LFXO_CFG_MODE_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_MODE_XTAL (_LFXO_CFG_MODE_XTAL << 4) /**< Shifted mode XTAL for LFXO_CFG */ -#define LFXO_CFG_MODE_BUFEXTCLK (_LFXO_CFG_MODE_BUFEXTCLK << 4) /**< Shifted mode BUFEXTCLK for LFXO_CFG */ -#define LFXO_CFG_MODE_DIGEXTCLK (_LFXO_CFG_MODE_DIGEXTCLK << 4) /**< Shifted mode DIGEXTCLK for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_SHIFT 8 /**< Shift value for LFXO_TIMEOUT */ -#define _LFXO_CFG_TIMEOUT_MASK 0x700UL /**< Bit mask for LFXO_TIMEOUT */ -#define _LFXO_CFG_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES2 0x00000000UL /**< Mode CYCLES2 for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES256 0x00000001UL /**< Mode CYCLES256 for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES1K 0x00000002UL /**< Mode CYCLES1K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES2K 0x00000003UL /**< Mode CYCLES2K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES4K 0x00000004UL /**< Mode CYCLES4K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES8K 0x00000005UL /**< Mode CYCLES8K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES16K 0x00000006UL /**< Mode CYCLES16K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES32K 0x00000007UL /**< Mode CYCLES32K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_DEFAULT (_LFXO_CFG_TIMEOUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES2 (_LFXO_CFG_TIMEOUT_CYCLES2 << 8) /**< Shifted mode CYCLES2 for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES256 (_LFXO_CFG_TIMEOUT_CYCLES256 << 8) /**< Shifted mode CYCLES256 for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES1K (_LFXO_CFG_TIMEOUT_CYCLES1K << 8) /**< Shifted mode CYCLES1K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES2K (_LFXO_CFG_TIMEOUT_CYCLES2K << 8) /**< Shifted mode CYCLES2K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES4K (_LFXO_CFG_TIMEOUT_CYCLES4K << 8) /**< Shifted mode CYCLES4K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES8K (_LFXO_CFG_TIMEOUT_CYCLES8K << 8) /**< Shifted mode CYCLES8K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES16K (_LFXO_CFG_TIMEOUT_CYCLES16K << 8) /**< Shifted mode CYCLES16K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES32K (_LFXO_CFG_TIMEOUT_CYCLES32K << 8) /**< Shifted mode CYCLES32K for LFXO_CFG */ +#define _LFXO_CFG_RESETVALUE 0x00000701UL /**< Default value for LFXO_CFG */ +#define _LFXO_CFG_MASK 0x00000733UL /**< Mask for LFXO_CFG */ +#define LFXO_CFG_AGC (0x1UL << 0) /**< LFXO AGC Enable */ +#define _LFXO_CFG_AGC_SHIFT 0 /**< Shift value for LFXO_AGC */ +#define _LFXO_CFG_AGC_MASK 0x1UL /**< Bit mask for LFXO_AGC */ +#define _LFXO_CFG_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_AGC_DEFAULT (_LFXO_CFG_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL (0x1UL << 1) /**< LFXO High Amplitude Enable */ +#define _LFXO_CFG_HIGHAMPL_SHIFT 1 /**< Shift value for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_MASK 0x2UL /**< Bit mask for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL_DEFAULT (_LFXO_CFG_HIGHAMPL_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_SHIFT 4 /**< Shift value for LFXO_MODE */ +#define _LFXO_CFG_MODE_MASK 0x30UL /**< Bit mask for LFXO_MODE */ +#define _LFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for LFXO_CFG */ +#define _LFXO_CFG_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DEFAULT (_LFXO_CFG_MODE_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_MODE_XTAL (_LFXO_CFG_MODE_XTAL << 4) /**< Shifted mode XTAL for LFXO_CFG */ +#define LFXO_CFG_MODE_BUFEXTCLK (_LFXO_CFG_MODE_BUFEXTCLK << 4) /**< Shifted mode BUFEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DIGEXTCLK (_LFXO_CFG_MODE_DIGEXTCLK << 4) /**< Shifted mode DIGEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_SHIFT 8 /**< Shift value for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_MASK 0x700UL /**< Bit mask for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2 0x00000000UL /**< Mode CYCLES2 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES256 0x00000001UL /**< Mode CYCLES256 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES1K 0x00000002UL /**< Mode CYCLES1K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2K 0x00000003UL /**< Mode CYCLES2K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES4K 0x00000004UL /**< Mode CYCLES4K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES8K 0x00000005UL /**< Mode CYCLES8K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES16K 0x00000006UL /**< Mode CYCLES16K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES32K 0x00000007UL /**< Mode CYCLES32K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_DEFAULT (_LFXO_CFG_TIMEOUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2 (_LFXO_CFG_TIMEOUT_CYCLES2 << 8) /**< Shifted mode CYCLES2 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES256 (_LFXO_CFG_TIMEOUT_CYCLES256 << 8) /**< Shifted mode CYCLES256 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES1K (_LFXO_CFG_TIMEOUT_CYCLES1K << 8) /**< Shifted mode CYCLES1K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2K (_LFXO_CFG_TIMEOUT_CYCLES2K << 8) /**< Shifted mode CYCLES2K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES4K (_LFXO_CFG_TIMEOUT_CYCLES4K << 8) /**< Shifted mode CYCLES4K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES8K (_LFXO_CFG_TIMEOUT_CYCLES8K << 8) /**< Shifted mode CYCLES8K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES16K (_LFXO_CFG_TIMEOUT_CYCLES16K << 8) /**< Shifted mode CYCLES16K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES32K (_LFXO_CFG_TIMEOUT_CYCLES32K << 8) /**< Shifted mode CYCLES32K for LFXO_CFG */ /* Bit fields for LFXO STATUS */ -#define _LFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFXO_STATUS */ -#define _LFXO_STATUS_MASK 0x80010001UL /**< Mask for LFXO_STATUS */ -#define LFXO_STATUS_RDY (0x1UL << 0) /**< LFXO Ready Status */ -#define _LFXO_STATUS_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ -#define _LFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ -#define _LFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_RDY_DEFAULT (_LFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_ENS (0x1UL << 16) /**< LFXO Enable Status */ -#define _LFXO_STATUS_ENS_SHIFT 16 /**< Shift value for LFXO_ENS */ -#define _LFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFXO_ENS */ -#define _LFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_ENS_DEFAULT (_LFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_LOCK (0x1UL << 31) /**< LFXO Locked Status */ -#define _LFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFXO_LOCK */ -#define _LFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFXO_LOCK */ -#define _LFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ -#define _LFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFXO_STATUS */ -#define _LFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFXO_STATUS */ -#define LFXO_STATUS_LOCK_DEFAULT (_LFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_LOCK_UNLOCKED (_LFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFXO_STATUS */ -#define LFXO_STATUS_LOCK_LOCKED (_LFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFXO_STATUS */ +#define _LFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFXO_STATUS */ +#define _LFXO_STATUS_MASK 0x80010001UL /**< Mask for LFXO_STATUS */ +#define LFXO_STATUS_RDY (0x1UL << 0) /**< LFXO Ready Status */ +#define _LFXO_STATUS_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_RDY_DEFAULT (_LFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS (0x1UL << 16) /**< LFXO Enable Status */ +#define _LFXO_STATUS_ENS_SHIFT 16 /**< Shift value for LFXO_ENS */ +#define _LFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFXO_ENS */ +#define _LFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS_DEFAULT (_LFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK (0x1UL << 31) /**< LFXO Locked Status */ +#define _LFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_DEFAULT (_LFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_UNLOCKED (_LFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_LOCKED (_LFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFXO_STATUS */ /* Bit fields for LFXO CAL */ -#define _LFXO_CAL_RESETVALUE 0x00000200UL /**< Default value for LFXO_CAL */ -#define _LFXO_CAL_MASK 0x0000037FUL /**< Mask for LFXO_CAL */ -#define _LFXO_CAL_CAPTUNE_SHIFT 0 /**< Shift value for LFXO_CAPTUNE */ -#define _LFXO_CAL_CAPTUNE_MASK 0x7FUL /**< Bit mask for LFXO_CAPTUNE */ -#define _LFXO_CAL_CAPTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CAL */ -#define LFXO_CAL_CAPTUNE_DEFAULT (_LFXO_CAL_CAPTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CAL */ -#define _LFXO_CAL_GAIN_SHIFT 8 /**< Shift value for LFXO_GAIN */ -#define _LFXO_CAL_GAIN_MASK 0x300UL /**< Bit mask for LFXO_GAIN */ -#define _LFXO_CAL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for LFXO_CAL */ -#define LFXO_CAL_GAIN_DEFAULT (_LFXO_CAL_GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CAL */ +#define _LFXO_CAL_RESETVALUE 0x00000200UL /**< Default value for LFXO_CAL */ +#define _LFXO_CAL_MASK 0x0000037FUL /**< Mask for LFXO_CAL */ +#define _LFXO_CAL_CAPTUNE_SHIFT 0 /**< Shift value for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_MASK 0x7FUL /**< Bit mask for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_CAPTUNE_DEFAULT (_LFXO_CAL_CAPTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CAL */ +#define _LFXO_CAL_GAIN_SHIFT 8 /**< Shift value for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_MASK 0x300UL /**< Bit mask for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_GAIN_DEFAULT (_LFXO_CAL_GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CAL */ /* Bit fields for LFXO IF */ -#define _LFXO_IF_RESETVALUE 0x00000000UL /**< Default value for LFXO_IF */ -#define _LFXO_IF_MASK 0x0000000FUL /**< Mask for LFXO_IF */ -#define LFXO_IF_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Flag */ -#define _LFXO_IF_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ -#define _LFXO_IF_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ -#define _LFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ -#define LFXO_IF_RDY_DEFAULT (_LFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IF */ -#define LFXO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ -#define _LFXO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ -#define _LFXO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ -#define _LFXO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ -#define LFXO_IF_POSEDGE_DEFAULT (_LFXO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IF */ -#define LFXO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ -#define _LFXO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ -#define _LFXO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ -#define _LFXO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ -#define LFXO_IF_NEGEDGE_DEFAULT (_LFXO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IF */ -#define LFXO_IF_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Flag */ -#define _LFXO_IF_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ -#define _LFXO_IF_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ -#define _LFXO_IF_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ -#define LFXO_IF_FAIL_DEFAULT (_LFXO_IF_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IF */ +#define _LFXO_IF_RESETVALUE 0x00000000UL /**< Default value for LFXO_IF */ +#define _LFXO_IF_MASK 0x0000000FUL /**< Mask for LFXO_IF */ +#define LFXO_IF_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Flag */ +#define _LFXO_IF_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IF_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_RDY_DEFAULT (_LFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ +#define _LFXO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE_DEFAULT (_LFXO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ +#define _LFXO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE_DEFAULT (_LFXO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Flag */ +#define _LFXO_IF_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IF_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IF_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL_DEFAULT (_LFXO_IF_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IF */ /* Bit fields for LFXO IEN */ -#define _LFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFXO_IEN */ -#define _LFXO_IEN_MASK 0x0000000FUL /**< Mask for LFXO_IEN */ -#define LFXO_IEN_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Enable */ -#define _LFXO_IEN_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ -#define _LFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ -#define _LFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_RDY_DEFAULT (_LFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ -#define _LFXO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ -#define _LFXO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ -#define _LFXO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_POSEDGE_DEFAULT (_LFXO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ -#define _LFXO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ -#define _LFXO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ -#define _LFXO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_NEGEDGE_DEFAULT (_LFXO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Enable */ -#define _LFXO_IEN_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ -#define _LFXO_IEN_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ -#define _LFXO_IEN_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_FAIL_DEFAULT (_LFXO_IEN_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define _LFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFXO_IEN */ +#define _LFXO_IEN_MASK 0x0000000FUL /**< Mask for LFXO_IEN */ +#define LFXO_IEN_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Enable */ +#define _LFXO_IEN_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_RDY_DEFAULT (_LFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ +#define _LFXO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE_DEFAULT (_LFXO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ +#define _LFXO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE_DEFAULT (_LFXO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Enable */ +#define _LFXO_IEN_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL_DEFAULT (_LFXO_IEN_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IEN */ /* Bit fields for LFXO SYNCBUSY */ -#define _LFXO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFXO_SYNCBUSY */ -#define _LFXO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFXO_SYNCBUSY */ -#define LFXO_SYNCBUSY_CAL (0x1UL << 0) /**< LFXO Synchronization status */ -#define _LFXO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFXO_CAL */ -#define _LFXO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFXO_CAL */ -#define _LFXO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_SYNCBUSY */ -#define LFXO_SYNCBUSY_CAL_DEFAULT (_LFXO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_SYNCBUSY */ +#define _LFXO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFXO_SYNCBUSY */ +#define _LFXO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL (0x1UL << 0) /**< LFXO Synchronization status */ +#define _LFXO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL_DEFAULT (_LFXO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_SYNCBUSY */ /* Bit fields for LFXO LOCK */ -#define _LFXO_LOCK_RESETVALUE 0x00001A20UL /**< Default value for LFXO_LOCK */ -#define _LFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFXO_LOCK */ -#define _LFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFXO_LOCKKEY */ -#define _LFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFXO_LOCKKEY */ -#define _LFXO_LOCK_LOCKKEY_DEFAULT 0x00001A20UL /**< Mode DEFAULT for LFXO_LOCK */ -#define _LFXO_LOCK_LOCKKEY_UNLOCK 0x00001A20UL /**< Mode UNLOCK for LFXO_LOCK */ -#define LFXO_LOCK_LOCKKEY_DEFAULT (_LFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_LOCK */ -#define LFXO_LOCK_LOCKKEY_UNLOCK (_LFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFXO_LOCK */ +#define _LFXO_LOCK_RESETVALUE 0x00001A20UL /**< Default value for LFXO_LOCK */ +#define _LFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_DEFAULT 0x00001A20UL /**< Mode DEFAULT for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_UNLOCK 0x00001A20UL /**< Mode UNLOCK for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_DEFAULT (_LFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_UNLOCK (_LFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFXO_LOCK */ /** @} End of group EFR32SG23_LFXO_BitFields */ /** @} End of group EFR32SG23_LFXO */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_mailbox.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_mailbox.h index add72239d4..193d4f47c5 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_mailbox.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_MAILBOX_H #define EFR32SG23_MAILBOX_H - #define MAILBOX_HAS_SET_CLEAR /**************************************************************************//** @@ -43,34 +42,31 @@ *****************************************************************************/ /** MAILBOX MSGPTRS Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t MSGPTR; /**< Message Pointer */ +typedef struct { + __IOM uint32_t MSGPTR; /**< Message Pointer */ } MAILBOX_MSGPTRS_TypeDef; - /** MAILBOX Register Declaration. */ -typedef struct -{ - MAILBOX_MSGPTRS_TypeDef MSGPTRS[4U]; /**< Message Pointers */ - uint32_t RESERVED0[12U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag register */ - __IOM uint32_t IEN; /**< Interrupt Enable register */ - uint32_t RESERVED1[1006U]; /**< Reserved for future use */ - MAILBOX_MSGPTRS_TypeDef MSGPTRS_SET[4U]; /**< Message Pointers */ - uint32_t RESERVED2[12U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable register */ - uint32_t RESERVED3[1006U]; /**< Reserved for future use */ - MAILBOX_MSGPTRS_TypeDef MSGPTRS_CLR[4U]; /**< Message Pointers */ - uint32_t RESERVED4[12U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable register */ - uint32_t RESERVED5[1006U]; /**< Reserved for future use */ - MAILBOX_MSGPTRS_TypeDef MSGPTRS_TGL[4U]; /**< Message Pointers */ - uint32_t RESERVED6[12U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable register */ +typedef struct { + MAILBOX_MSGPTRS_TypeDef MSGPTRS[4U]; /**< Message Pointers */ + uint32_t RESERVED0[12U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag register */ + __IOM uint32_t IEN; /**< Interrupt Enable register */ + uint32_t RESERVED1[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_SET[4U]; /**< Message Pointers */ + uint32_t RESERVED2[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable register */ + uint32_t RESERVED3[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_CLR[4U]; /**< Message Pointers */ + uint32_t RESERVED4[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable register */ + uint32_t RESERVED5[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_TGL[4U]; /**< Message Pointers */ + uint32_t RESERVED6[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable register */ } MAILBOX_TypeDef; /** @} End of group EFR32SG23_MAILBOX */ @@ -82,60 +78,60 @@ typedef struct *****************************************************************************/ /* Bit fields for MAILBOX MSGPTR */ -#define _MAILBOX_MSGPTR_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_MSGPTR */ -#define _MAILBOX_MSGPTR_MASK 0xFFFFFFFFUL /**< Mask for MAILBOX_MSGPTR */ -#define _MAILBOX_MSGPTR_PTR_SHIFT 0 /**< Shift value for MAILBOX_PTR */ -#define _MAILBOX_MSGPTR_PTR_MASK 0xFFFFFFFFUL /**< Bit mask for MAILBOX_PTR */ -#define _MAILBOX_MSGPTR_PTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_MSGPTR */ -#define MAILBOX_MSGPTR_PTR_DEFAULT (_MAILBOX_MSGPTR_PTR_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_MSGPTR */ +#define _MAILBOX_MSGPTR_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_MSGPTR */ +#define _MAILBOX_MSGPTR_MASK 0xFFFFFFFFUL /**< Mask for MAILBOX_MSGPTR */ +#define _MAILBOX_MSGPTR_PTR_SHIFT 0 /**< Shift value for MAILBOX_PTR */ +#define _MAILBOX_MSGPTR_PTR_MASK 0xFFFFFFFFUL /**< Bit mask for MAILBOX_PTR */ +#define _MAILBOX_MSGPTR_PTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_MSGPTR */ +#define MAILBOX_MSGPTR_PTR_DEFAULT (_MAILBOX_MSGPTR_PTR_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_MSGPTR */ /* Bit fields for MAILBOX IF */ -#define _MAILBOX_IF_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IF */ -#define _MAILBOX_IF_MASK 0x0000000FUL /**< Mask for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF0 (0x1UL << 0) /**< Mailbox Interupt Flag */ -#define _MAILBOX_IF_MBOXIF0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIF0 */ -#define _MAILBOX_IF_MBOXIF0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIF0 */ -#define _MAILBOX_IF_MBOXIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF0_DEFAULT (_MAILBOX_IF_MBOXIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF1 (0x1UL << 1) /**< Mailbox Interupt Flag */ -#define _MAILBOX_IF_MBOXIF1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIF1 */ -#define _MAILBOX_IF_MBOXIF1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIF1 */ -#define _MAILBOX_IF_MBOXIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF1_DEFAULT (_MAILBOX_IF_MBOXIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF2 (0x1UL << 2) /**< Mailbox Interupt Flag */ -#define _MAILBOX_IF_MBOXIF2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIF2 */ -#define _MAILBOX_IF_MBOXIF2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIF2 */ -#define _MAILBOX_IF_MBOXIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF2_DEFAULT (_MAILBOX_IF_MBOXIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF3 (0x1UL << 3) /**< Mailbox Interupt Flag */ -#define _MAILBOX_IF_MBOXIF3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIF3 */ -#define _MAILBOX_IF_MBOXIF3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIF3 */ -#define _MAILBOX_IF_MBOXIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF3_DEFAULT (_MAILBOX_IF_MBOXIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define _MAILBOX_IF_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IF */ +#define _MAILBOX_IF_MASK 0x0000000FUL /**< Mask for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF0 (0x1UL << 0) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIF0 */ +#define _MAILBOX_IF_MBOXIF0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIF0 */ +#define _MAILBOX_IF_MBOXIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF0_DEFAULT (_MAILBOX_IF_MBOXIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF1 (0x1UL << 1) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIF1 */ +#define _MAILBOX_IF_MBOXIF1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIF1 */ +#define _MAILBOX_IF_MBOXIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF1_DEFAULT (_MAILBOX_IF_MBOXIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF2 (0x1UL << 2) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIF2 */ +#define _MAILBOX_IF_MBOXIF2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIF2 */ +#define _MAILBOX_IF_MBOXIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF2_DEFAULT (_MAILBOX_IF_MBOXIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF3 (0x1UL << 3) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIF3 */ +#define _MAILBOX_IF_MBOXIF3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIF3 */ +#define _MAILBOX_IF_MBOXIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF3_DEFAULT (_MAILBOX_IF_MBOXIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IF */ /* Bit fields for MAILBOX IEN */ -#define _MAILBOX_IEN_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IEN */ -#define _MAILBOX_IEN_MASK 0x0000000FUL /**< Mask for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN0 (0x1UL << 0) /**< Mailbox Interrupt Enable */ -#define _MAILBOX_IEN_MBOXIEN0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIEN0 */ -#define _MAILBOX_IEN_MBOXIEN0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIEN0 */ -#define _MAILBOX_IEN_MBOXIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN0_DEFAULT (_MAILBOX_IEN_MBOXIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN1 (0x1UL << 1) /**< Mailbox Interrupt Enable */ -#define _MAILBOX_IEN_MBOXIEN1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIEN1 */ -#define _MAILBOX_IEN_MBOXIEN1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIEN1 */ -#define _MAILBOX_IEN_MBOXIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN1_DEFAULT (_MAILBOX_IEN_MBOXIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN2 (0x1UL << 2) /**< Mailbox Interrupt Enable */ -#define _MAILBOX_IEN_MBOXIEN2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIEN2 */ -#define _MAILBOX_IEN_MBOXIEN2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIEN2 */ -#define _MAILBOX_IEN_MBOXIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN2_DEFAULT (_MAILBOX_IEN_MBOXIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN3 (0x1UL << 3) /**< Mailbox Interrupt Enable */ -#define _MAILBOX_IEN_MBOXIEN3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIEN3 */ -#define _MAILBOX_IEN_MBOXIEN3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIEN3 */ -#define _MAILBOX_IEN_MBOXIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN3_DEFAULT (_MAILBOX_IEN_MBOXIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define _MAILBOX_IEN_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IEN */ +#define _MAILBOX_IEN_MASK 0x0000000FUL /**< Mask for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN0 (0x1UL << 0) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIEN0 */ +#define _MAILBOX_IEN_MBOXIEN0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIEN0 */ +#define _MAILBOX_IEN_MBOXIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN0_DEFAULT (_MAILBOX_IEN_MBOXIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN1 (0x1UL << 1) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIEN1 */ +#define _MAILBOX_IEN_MBOXIEN1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIEN1 */ +#define _MAILBOX_IEN_MBOXIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN1_DEFAULT (_MAILBOX_IEN_MBOXIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN2 (0x1UL << 2) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIEN2 */ +#define _MAILBOX_IEN_MBOXIEN2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIEN2 */ +#define _MAILBOX_IEN_MBOXIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN2_DEFAULT (_MAILBOX_IEN_MBOXIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN3 (0x1UL << 3) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIEN3 */ +#define _MAILBOX_IEN_MBOXIEN3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIEN3 */ +#define _MAILBOX_IEN_MBOXIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN3_DEFAULT (_MAILBOX_IEN_MBOXIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IEN */ /** @} End of group EFR32SG23_MAILBOX_BitFields */ /** @} End of group EFR32SG23_MAILBOX */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_mpahbram.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_mpahbram.h index db032a1319..10c481d400 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_mpahbram.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_MPAHBRAM_H #define EFR32SG23_MPAHBRAM_H - #define MPAHBRAM_HAS_SET_CLEAR /**************************************************************************//** @@ -43,55 +42,54 @@ *****************************************************************************/ /** MPAHBRAM Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t CMD; /**< Command register */ - __IOM uint32_t CTRL; /**< Control register */ - __IM uint32_t ECCERRADDR0; /**< ECC Error Address 0 */ - __IM uint32_t ECCERRADDR1; /**< ECC Error Address 1 */ - uint32_t RESERVED0[2U]; /**< Reserved for future use */ - __IM uint32_t ECCMERRIND; /**< Multiple ECC error indication */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED1[7U]; /**< Reserved for future use */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - uint32_t RESERVED3[1006U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t CMD_SET; /**< Command register */ - __IOM uint32_t CTRL_SET; /**< Control register */ - __IM uint32_t ECCERRADDR0_SET; /**< ECC Error Address 0 */ - __IM uint32_t ECCERRADDR1_SET; /**< ECC Error Address 1 */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IM uint32_t ECCMERRIND_SET; /**< Multiple ECC error indication */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - uint32_t RESERVED5[7U]; /**< Reserved for future use */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - uint32_t RESERVED7[1006U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t CMD_CLR; /**< Command register */ - __IOM uint32_t CTRL_CLR; /**< Control register */ - __IM uint32_t ECCERRADDR0_CLR; /**< ECC Error Address 0 */ - __IM uint32_t ECCERRADDR1_CLR; /**< ECC Error Address 1 */ - uint32_t RESERVED8[2U]; /**< Reserved for future use */ - __IM uint32_t ECCMERRIND_CLR; /**< Multiple ECC error indication */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - uint32_t RESERVED9[7U]; /**< Reserved for future use */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - uint32_t RESERVED11[1006U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t CMD_TGL; /**< Command register */ - __IOM uint32_t CTRL_TGL; /**< Control register */ - __IM uint32_t ECCERRADDR0_TGL; /**< ECC Error Address 0 */ - __IM uint32_t ECCERRADDR1_TGL; /**< ECC Error Address 1 */ - uint32_t RESERVED12[2U]; /**< Reserved for future use */ - __IM uint32_t ECCMERRIND_TGL; /**< Multiple ECC error indication */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - uint32_t RESERVED13[7U]; /**< Reserved for future use */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t CMD; /**< Command register */ + __IOM uint32_t CTRL; /**< Control register */ + __IM uint32_t ECCERRADDR0; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1; /**< ECC Error Address 1 */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IM uint32_t ECCMERRIND; /**< Multiple ECC error indication */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED1[7U]; /**< Reserved for future use */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + uint32_t RESERVED3[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t CMD_SET; /**< Command register */ + __IOM uint32_t CTRL_SET; /**< Control register */ + __IM uint32_t ECCERRADDR0_SET; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_SET; /**< ECC Error Address 1 */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IM uint32_t ECCMERRIND_SET; /**< Multiple ECC error indication */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t CMD_CLR; /**< Command register */ + __IOM uint32_t CTRL_CLR; /**< Control register */ + __IM uint32_t ECCERRADDR0_CLR; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_CLR; /**< ECC Error Address 1 */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IM uint32_t ECCMERRIND_CLR; /**< Multiple ECC error indication */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t CMD_TGL; /**< Command register */ + __IOM uint32_t CTRL_TGL; /**< Control register */ + __IM uint32_t ECCERRADDR0_TGL; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_TGL; /**< ECC Error Address 1 */ + uint32_t RESERVED12[2U]; /**< Reserved for future use */ + __IM uint32_t ECCMERRIND_TGL; /**< Multiple ECC error indication */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ } MPAHBRAM_TypeDef; /** @} End of group EFR32SG23_MPAHBRAM */ @@ -103,139 +101,139 @@ typedef struct *****************************************************************************/ /* Bit fields for MPAHBRAM IPVERSION */ -#define _MPAHBRAM_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for MPAHBRAM_IPVERSION */ -#define _MPAHBRAM_IPVERSION_MASK 0x00000001UL /**< Mask for MPAHBRAM_IPVERSION */ -#define MPAHBRAM_IPVERSION_IPVERSION (0x1UL << 0) /**< New BitField */ -#define _MPAHBRAM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MPAHBRAM_IPVERSION */ -#define _MPAHBRAM_IPVERSION_IPVERSION_MASK 0x1UL /**< Bit mask for MPAHBRAM_IPVERSION */ -#define _MPAHBRAM_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_IPVERSION */ -#define MPAHBRAM_IPVERSION_IPVERSION_DEFAULT (_MPAHBRAM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_MASK 0x00000001UL /**< Mask for MPAHBRAM_IPVERSION */ +#define MPAHBRAM_IPVERSION_IPVERSION (0x1UL << 0) /**< New BitField */ +#define _MPAHBRAM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_MASK 0x1UL /**< Bit mask for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_IPVERSION */ +#define MPAHBRAM_IPVERSION_IPVERSION_DEFAULT (_MPAHBRAM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IPVERSION */ /* Bit fields for MPAHBRAM CMD */ -#define _MPAHBRAM_CMD_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CMD */ -#define _MPAHBRAM_CMD_MASK 0x00000003UL /**< Mask for MPAHBRAM_CMD */ -#define MPAHBRAM_CMD_CLEARECCADDR0 (0x1UL << 0) /**< Clear ECCERRADDR0 */ -#define _MPAHBRAM_CMD_CLEARECCADDR0_SHIFT 0 /**< Shift value for MPAHBRAM_CLEARECCADDR0 */ -#define _MPAHBRAM_CMD_CLEARECCADDR0_MASK 0x1UL /**< Bit mask for MPAHBRAM_CLEARECCADDR0 */ -#define _MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ -#define MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ -#define MPAHBRAM_CMD_CLEARECCADDR1 (0x1UL << 1) /**< Clear ECCERRADDR1 */ -#define _MPAHBRAM_CMD_CLEARECCADDR1_SHIFT 1 /**< Shift value for MPAHBRAM_CLEARECCADDR1 */ -#define _MPAHBRAM_CMD_CLEARECCADDR1_MASK 0x2UL /**< Bit mask for MPAHBRAM_CLEARECCADDR1 */ -#define _MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ -#define MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ +#define _MPAHBRAM_CMD_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CMD */ +#define _MPAHBRAM_CMD_MASK 0x00000003UL /**< Mask for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR0 (0x1UL << 0) /**< Clear ECCERRADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_SHIFT 0 /**< Shift value for MPAHBRAM_CLEARECCADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_MASK 0x1UL /**< Bit mask for MPAHBRAM_CLEARECCADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR1 (0x1UL << 1) /**< Clear ECCERRADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_SHIFT 1 /**< Shift value for MPAHBRAM_CLEARECCADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_MASK 0x2UL /**< Bit mask for MPAHBRAM_CLEARECCADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ /* Bit fields for MPAHBRAM CTRL */ -#define _MPAHBRAM_CTRL_RESETVALUE 0x00000040UL /**< Default value for MPAHBRAM_CTRL */ -#define _MPAHBRAM_CTRL_MASK 0x0000007FUL /**< Mask for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_ECCEN (0x1UL << 0) /**< Enable ECC functionality */ -#define _MPAHBRAM_CTRL_ECCEN_SHIFT 0 /**< Shift value for MPAHBRAM_ECCEN */ -#define _MPAHBRAM_CTRL_ECCEN_MASK 0x1UL /**< Bit mask for MPAHBRAM_ECCEN */ -#define _MPAHBRAM_CTRL_ECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_ECCEN_DEFAULT (_MPAHBRAM_CTRL_ECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_ECCWEN (0x1UL << 1) /**< Enable ECC syndrome writes */ -#define _MPAHBRAM_CTRL_ECCWEN_SHIFT 1 /**< Shift value for MPAHBRAM_ECCWEN */ -#define _MPAHBRAM_CTRL_ECCWEN_MASK 0x2UL /**< Bit mask for MPAHBRAM_ECCWEN */ -#define _MPAHBRAM_CTRL_ECCWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_ECCWEN_DEFAULT (_MPAHBRAM_CTRL_ECCWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_ECCERRFAULTEN (0x1UL << 2) /**< ECC Error bus fault enable */ -#define _MPAHBRAM_CTRL_ECCERRFAULTEN_SHIFT 2 /**< Shift value for MPAHBRAM_ECCERRFAULTEN */ -#define _MPAHBRAM_CTRL_ECCERRFAULTEN_MASK 0x4UL /**< Bit mask for MPAHBRAM_ECCERRFAULTEN */ -#define _MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ -#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT 3 /**< Shift value for MPAHBRAM_AHBPORTPRIORITY */ -#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK 0x38UL /**< Bit mask for MPAHBRAM_AHBPORTPRIORITY */ -#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ -#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE 0x00000000UL /**< Mode NONE for MPAHBRAM_CTRL */ -#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 0x00000001UL /**< Mode PORT0 for MPAHBRAM_CTRL */ -#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 0x00000002UL /**< Mode PORT1 for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT (_MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE (_MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE << 3) /**< Shifted mode NONE for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 << 3) /**< Shifted mode PORT0 for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 << 3) /**< Shifted mode PORT1 for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_ADDRFAULTEN (0x1UL << 6) /**< Address fault bus fault enable */ -#define _MPAHBRAM_CTRL_ADDRFAULTEN_SHIFT 6 /**< Shift value for MPAHBRAM_ADDRFAULTEN */ -#define _MPAHBRAM_CTRL_ADDRFAULTEN_MASK 0x40UL /**< Bit mask for MPAHBRAM_ADDRFAULTEN */ -#define _MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_RESETVALUE 0x00000040UL /**< Default value for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_MASK 0x0000007FUL /**< Mask for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCEN (0x1UL << 0) /**< Enable ECC functionality */ +#define _MPAHBRAM_CTRL_ECCEN_SHIFT 0 /**< Shift value for MPAHBRAM_ECCEN */ +#define _MPAHBRAM_CTRL_ECCEN_MASK 0x1UL /**< Bit mask for MPAHBRAM_ECCEN */ +#define _MPAHBRAM_CTRL_ECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCEN_DEFAULT (_MPAHBRAM_CTRL_ECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCWEN (0x1UL << 1) /**< Enable ECC syndrome writes */ +#define _MPAHBRAM_CTRL_ECCWEN_SHIFT 1 /**< Shift value for MPAHBRAM_ECCWEN */ +#define _MPAHBRAM_CTRL_ECCWEN_MASK 0x2UL /**< Bit mask for MPAHBRAM_ECCWEN */ +#define _MPAHBRAM_CTRL_ECCWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCWEN_DEFAULT (_MPAHBRAM_CTRL_ECCWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCERRFAULTEN (0x1UL << 2) /**< ECC Error bus fault enable */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_SHIFT 2 /**< Shift value for MPAHBRAM_ECCERRFAULTEN */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_MASK 0x4UL /**< Bit mask for MPAHBRAM_ECCERRFAULTEN */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT 3 /**< Shift value for MPAHBRAM_AHBPORTPRIORITY */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK 0x38UL /**< Bit mask for MPAHBRAM_AHBPORTPRIORITY */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE 0x00000000UL /**< Mode NONE for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 0x00000001UL /**< Mode PORT0 for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 0x00000002UL /**< Mode PORT1 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT (_MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE (_MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE << 3) /**< Shifted mode NONE for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 << 3) /**< Shifted mode PORT0 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 << 3) /**< Shifted mode PORT1 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ADDRFAULTEN (0x1UL << 6) /**< Address fault bus fault enable */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_SHIFT 6 /**< Shift value for MPAHBRAM_ADDRFAULTEN */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_MASK 0x40UL /**< Bit mask for MPAHBRAM_ADDRFAULTEN */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ /* Bit fields for MPAHBRAM ECCERRADDR0 */ -#define _MPAHBRAM_ECCERRADDR0_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR0 */ -#define _MPAHBRAM_ECCERRADDR0_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR0 */ -#define _MPAHBRAM_ECCERRADDR0_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ -#define _MPAHBRAM_ECCERRADDR0_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ -#define _MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR0 */ -#define MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR0*/ +#define _MPAHBRAM_ECCERRADDR0_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR0 */ +#define MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR0*/ /* Bit fields for MPAHBRAM ECCERRADDR1 */ -#define _MPAHBRAM_ECCERRADDR1_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR1 */ -#define _MPAHBRAM_ECCERRADDR1_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR1 */ -#define _MPAHBRAM_ECCERRADDR1_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ -#define _MPAHBRAM_ECCERRADDR1_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ -#define _MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR1 */ -#define MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR1*/ +#define _MPAHBRAM_ECCERRADDR1_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR1 */ +#define MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR1*/ /* Bit fields for MPAHBRAM ECCMERRIND */ -#define _MPAHBRAM_ECCMERRIND_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCMERRIND */ -#define _MPAHBRAM_ECCMERRIND_MASK 0x00000003UL /**< Mask for MPAHBRAM_ECCMERRIND */ -#define MPAHBRAM_ECCMERRIND_P0 (0x1UL << 0) /**< Multiple ECC errors on AHB port 0 */ -#define _MPAHBRAM_ECCMERRIND_P0_SHIFT 0 /**< Shift value for MPAHBRAM_P0 */ -#define _MPAHBRAM_ECCMERRIND_P0_MASK 0x1UL /**< Bit mask for MPAHBRAM_P0 */ -#define _MPAHBRAM_ECCMERRIND_P0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ -#define MPAHBRAM_ECCMERRIND_P0_DEFAULT (_MPAHBRAM_ECCMERRIND_P0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ -#define MPAHBRAM_ECCMERRIND_P1 (0x1UL << 1) /**< Multiple ECC errors on AHB port 1 */ -#define _MPAHBRAM_ECCMERRIND_P1_SHIFT 1 /**< Shift value for MPAHBRAM_P1 */ -#define _MPAHBRAM_ECCMERRIND_P1_MASK 0x2UL /**< Bit mask for MPAHBRAM_P1 */ -#define _MPAHBRAM_ECCMERRIND_P1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ -#define MPAHBRAM_ECCMERRIND_P1_DEFAULT (_MPAHBRAM_ECCMERRIND_P1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ +#define _MPAHBRAM_ECCMERRIND_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCMERRIND */ +#define _MPAHBRAM_ECCMERRIND_MASK 0x00000003UL /**< Mask for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P0 (0x1UL << 0) /**< Multiple ECC errors on AHB port 0 */ +#define _MPAHBRAM_ECCMERRIND_P0_SHIFT 0 /**< Shift value for MPAHBRAM_P0 */ +#define _MPAHBRAM_ECCMERRIND_P0_MASK 0x1UL /**< Bit mask for MPAHBRAM_P0 */ +#define _MPAHBRAM_ECCMERRIND_P0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P0_DEFAULT (_MPAHBRAM_ECCMERRIND_P0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ +#define MPAHBRAM_ECCMERRIND_P1 (0x1UL << 1) /**< Multiple ECC errors on AHB port 1 */ +#define _MPAHBRAM_ECCMERRIND_P1_SHIFT 1 /**< Shift value for MPAHBRAM_P1 */ +#define _MPAHBRAM_ECCMERRIND_P1_MASK 0x2UL /**< Bit mask for MPAHBRAM_P1 */ +#define _MPAHBRAM_ECCMERRIND_P1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P1_DEFAULT (_MPAHBRAM_ECCMERRIND_P1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ /* Bit fields for MPAHBRAM IF */ -#define _MPAHBRAM_IF_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IF */ -#define _MPAHBRAM_IF_MASK 0x00000033UL /**< Mask for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Flag */ -#define _MPAHBRAM_IF_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ -#define _MPAHBRAM_IF_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ -#define _MPAHBRAM_IF_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB0ERR1B_DEFAULT (_MPAHBRAM_IF_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Flag */ -#define _MPAHBRAM_IF_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ -#define _MPAHBRAM_IF_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ -#define _MPAHBRAM_IF_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB1ERR1B_DEFAULT (_MPAHBRAM_IF_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Flag */ -#define _MPAHBRAM_IF_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ -#define _MPAHBRAM_IF_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ -#define _MPAHBRAM_IF_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB0ERR2B_DEFAULT (_MPAHBRAM_IF_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Flag */ -#define _MPAHBRAM_IF_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ -#define _MPAHBRAM_IF_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ -#define _MPAHBRAM_IF_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB1ERR2B_DEFAULT (_MPAHBRAM_IF_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define _MPAHBRAM_IF_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IF */ +#define _MPAHBRAM_IF_MASK 0x00000033UL /**< Mask for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IF_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IF_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR1B_DEFAULT (_MPAHBRAM_IF_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IF_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IF_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR1B_DEFAULT (_MPAHBRAM_IF_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IF_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IF_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR2B_DEFAULT (_MPAHBRAM_IF_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IF_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IF_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR2B_DEFAULT (_MPAHBRAM_IF_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ /* Bit fields for MPAHBRAM IEN */ -#define _MPAHBRAM_IEN_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IEN */ -#define _MPAHBRAM_IEN_MASK 0x00000033UL /**< Mask for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Enable */ -#define _MPAHBRAM_IEN_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ -#define _MPAHBRAM_IEN_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ -#define _MPAHBRAM_IEN_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB0ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Enable */ -#define _MPAHBRAM_IEN_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ -#define _MPAHBRAM_IEN_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ -#define _MPAHBRAM_IEN_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB1ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Enable */ -#define _MPAHBRAM_IEN_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ -#define _MPAHBRAM_IEN_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ -#define _MPAHBRAM_IEN_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB0ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Enable */ -#define _MPAHBRAM_IEN_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ -#define _MPAHBRAM_IEN_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ -#define _MPAHBRAM_IEN_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB1ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define _MPAHBRAM_IEN_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IEN */ +#define _MPAHBRAM_IEN_MASK 0x00000033UL /**< Mask for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IEN_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IEN_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IEN_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IEN_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IEN_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IEN_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IEN_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IEN_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ /** @} End of group EFR32SG23_MPAHBRAM_BitFields */ /** @} End of group EFR32SG23_MPAHBRAM */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_msc.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_msc.h index 827b74508a..af32b00182 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_msc.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_msc.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_pcnt.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_pcnt.h index dbbcc61043..a8513a96e8 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_pcnt.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_PCNT_H #define EFR32SG23_PCNT_H - #define PCNT_HAS_SET_CLEAR /**************************************************************************//** @@ -43,75 +42,74 @@ *****************************************************************************/ /** PCNT Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t EN; /**< Module Enable Register */ - __IOM uint32_t SWRST; /**< Software Reset Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IM uint32_t CNT; /**< Counter Value Register */ - __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */ - __IOM uint32_t TOP; /**< Top Value Register */ - __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ - __IOM uint32_t OVSCTRL; /**< Oversampling Control Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - uint32_t RESERVED0[1008U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t EN_SET; /**< Module Enable Register */ - __IOM uint32_t SWRST_SET; /**< Software Reset Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IM uint32_t CNT_SET; /**< Counter Value Register */ - __IM uint32_t AUXCNT_SET; /**< Auxiliary Counter Value Register */ - __IOM uint32_t TOP_SET; /**< Top Value Register */ - __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ - __IOM uint32_t OVSCTRL_SET; /**< Oversampling Control Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - uint32_t RESERVED1[1008U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t EN_CLR; /**< Module Enable Register */ - __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IM uint32_t CNT_CLR; /**< Counter Value Register */ - __IM uint32_t AUXCNT_CLR; /**< Auxiliary Counter Value Register */ - __IOM uint32_t TOP_CLR; /**< Top Value Register */ - __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ - __IOM uint32_t OVSCTRL_CLR; /**< Oversampling Control Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - uint32_t RESERVED2[1008U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t EN_TGL; /**< Module Enable Register */ - __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IM uint32_t CNT_TGL; /**< Counter Value Register */ - __IM uint32_t AUXCNT_TGL; /**< Auxiliary Counter Value Register */ - __IOM uint32_t TOP_TGL; /**< Top Value Register */ - __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ - __IOM uint32_t OVSCTRL_TGL; /**< Oversampling Control Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP; /**< Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED0[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t CNT_SET; /**< Counter Value Register */ + __IM uint32_t AUXCNT_SET; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_SET; /**< Top Value Register */ + __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_SET; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED1[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t CNT_CLR; /**< Counter Value Register */ + __IM uint32_t AUXCNT_CLR; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_CLR; /**< Top Value Register */ + __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_CLR; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED2[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t CNT_TGL; /**< Counter Value Register */ + __IM uint32_t AUXCNT_TGL; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_TGL; /**< Top Value Register */ + __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_TGL; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ } PCNT_TypeDef; /** @} End of group EFR32SG23_PCNT */ @@ -123,11 +121,11 @@ typedef struct *****************************************************************************/ /* Bit fields for PCNT IPVERSION */ -#define _PCNT_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for PCNT_IPVERSION */ -#define _PCNT_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PCNT_IPVERSION */ -#define _PCNT_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PCNT_IPVERSION */ -#define _PCNT_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PCNT_IPVERSION */ -#define _PCNT_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for PCNT_IPVERSION */ #define PCNT_IPVERSION_IPVERSION_DEFAULT (_PCNT_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IPVERSION */ /* Bit fields for PCNT EN */ @@ -299,41 +297,41 @@ typedef struct #define PCNT_CMD_STOPAUXCNT_DEFAULT (_PCNT_CMD_STOPAUXCNT_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_CMD */ /* Bit fields for PCNT STATUS */ -#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ -#define _PCNT_STATUS_MASK 0x0000001FUL /**< Mask for PCNT_STATUS */ -#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */ -#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ -#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ -#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ -#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ -#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ -#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */ -#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */ -#define PCNT_STATUS_TOPBV (0x1UL << 1) /**< TOP Buffer Valid */ -#define _PCNT_STATUS_TOPBV_SHIFT 1 /**< Shift value for PCNT_TOPBV */ -#define _PCNT_STATUS_TOPBV_MASK 0x2UL /**< Bit mask for PCNT_TOPBV */ -#define _PCNT_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_TOPBV_DEFAULT (_PCNT_STATUS_TOPBV_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_PCNTLOCKSTATUS (0x1UL << 2) /**< Lock Status */ -#define _PCNT_STATUS_PCNTLOCKSTATUS_SHIFT 2 /**< Shift value for PCNT_PCNTLOCKSTATUS */ -#define _PCNT_STATUS_PCNTLOCKSTATUS_MASK 0x4UL /**< Bit mask for PCNT_PCNTLOCKSTATUS */ -#define _PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ -#define _PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for PCNT_STATUS */ -#define _PCNT_STATUS_PCNTLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for PCNT_STATUS */ -#define PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT (_PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ +#define _PCNT_STATUS_MASK 0x0000001FUL /**< Mask for PCNT_STATUS */ +#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */ +#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ +#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ +#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_TOPBV (0x1UL << 1) /**< TOP Buffer Valid */ +#define _PCNT_STATUS_TOPBV_SHIFT 1 /**< Shift value for PCNT_TOPBV */ +#define _PCNT_STATUS_TOPBV_MASK 0x2UL /**< Bit mask for PCNT_TOPBV */ +#define _PCNT_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_TOPBV_DEFAULT (_PCNT_STATUS_TOPBV_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS (0x1UL << 2) /**< Lock Status */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_SHIFT 2 /**< Shift value for PCNT_PCNTLOCKSTATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_MASK 0x4UL /**< Bit mask for PCNT_PCNTLOCKSTATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for PCNT_STATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT (_PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_STATUS */ #define PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED << 2) /**< Shifted mode UNLOCKED for PCNT_STATUS */ -#define PCNT_STATUS_PCNTLOCKSTATUS_LOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_LOCKED << 2) /**< Shifted mode LOCKED for PCNT_STATUS */ -#define PCNT_STATUS_CNTRUNNING (0x1UL << 3) /**< Main Counter running status */ -#define _PCNT_STATUS_CNTRUNNING_SHIFT 3 /**< Shift value for PCNT_CNTRUNNING */ -#define _PCNT_STATUS_CNTRUNNING_MASK 0x8UL /**< Bit mask for PCNT_CNTRUNNING */ -#define _PCNT_STATUS_CNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_CNTRUNNING_DEFAULT (_PCNT_STATUS_CNTRUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_AUXCNTRUNNING (0x1UL << 4) /**< Aux Counter running status */ -#define _PCNT_STATUS_AUXCNTRUNNING_SHIFT 4 /**< Shift value for PCNT_AUXCNTRUNNING */ -#define _PCNT_STATUS_AUXCNTRUNNING_MASK 0x10UL /**< Bit mask for PCNT_AUXCNTRUNNING */ -#define _PCNT_STATUS_AUXCNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_AUXCNTRUNNING_DEFAULT (_PCNT_STATUS_AUXCNTRUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS_LOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_LOCKED << 2) /**< Shifted mode LOCKED for PCNT_STATUS */ +#define PCNT_STATUS_CNTRUNNING (0x1UL << 3) /**< Main Counter running status */ +#define _PCNT_STATUS_CNTRUNNING_SHIFT 3 /**< Shift value for PCNT_CNTRUNNING */ +#define _PCNT_STATUS_CNTRUNNING_MASK 0x8UL /**< Bit mask for PCNT_CNTRUNNING */ +#define _PCNT_STATUS_CNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_CNTRUNNING_DEFAULT (_PCNT_STATUS_CNTRUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_AUXCNTRUNNING (0x1UL << 4) /**< Aux Counter running status */ +#define _PCNT_STATUS_AUXCNTRUNNING_SHIFT 4 /**< Shift value for PCNT_AUXCNTRUNNING */ +#define _PCNT_STATUS_AUXCNTRUNNING_MASK 0x10UL /**< Bit mask for PCNT_AUXCNTRUNNING */ +#define _PCNT_STATUS_AUXCNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_AUXCNTRUNNING_DEFAULT (_PCNT_STATUS_AUXCNTRUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_STATUS */ /* Bit fields for PCNT IF */ #define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_pfmxpprf.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_pfmxpprf.h index a4fdcb2cb6..893b499709 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_pfmxpprf.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_pfmxpprf.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_PFMXPPRF_H #define EFR32SG23_PFMXPPRF_H - #define PFMXPPRF_HAS_SET_CLEAR /**************************************************************************//** @@ -43,31 +42,30 @@ *****************************************************************************/ /** PFMXPPRF Register Declaration. */ -typedef struct -{ - __IOM uint32_t RFIMDCDCCTRL0; /**< New Register */ - __IOM uint32_t RFIMDCDCCTRL1; /**< New Register */ - __IOM uint32_t RFIMDCDCCTRL2; /**< New Register */ - __IM uint32_t RFIMDCDCSTATUS; /**< New Register */ - __IOM uint32_t RPURATD0; /**< Root Access Type Descriptor Register */ - uint32_t RESERVED0[1019U]; /**< Reserved for future use */ - __IOM uint32_t RFIMDCDCCTRL0_SET; /**< New Register */ - __IOM uint32_t RFIMDCDCCTRL1_SET; /**< New Register */ - __IOM uint32_t RFIMDCDCCTRL2_SET; /**< New Register */ - __IM uint32_t RFIMDCDCSTATUS_SET; /**< New Register */ - __IOM uint32_t RPURATD0_SET; /**< Root Access Type Descriptor Register */ - uint32_t RESERVED1[1019U]; /**< Reserved for future use */ - __IOM uint32_t RFIMDCDCCTRL0_CLR; /**< New Register */ - __IOM uint32_t RFIMDCDCCTRL1_CLR; /**< New Register */ - __IOM uint32_t RFIMDCDCCTRL2_CLR; /**< New Register */ - __IM uint32_t RFIMDCDCSTATUS_CLR; /**< New Register */ - __IOM uint32_t RPURATD0_CLR; /**< Root Access Type Descriptor Register */ - uint32_t RESERVED2[1019U]; /**< Reserved for future use */ - __IOM uint32_t RFIMDCDCCTRL0_TGL; /**< New Register */ - __IOM uint32_t RFIMDCDCCTRL1_TGL; /**< New Register */ - __IOM uint32_t RFIMDCDCCTRL2_TGL; /**< New Register */ - __IM uint32_t RFIMDCDCSTATUS_TGL; /**< New Register */ - __IOM uint32_t RPURATD0_TGL; /**< Root Access Type Descriptor Register */ +typedef struct { + __IOM uint32_t RFIMDCDCCTRL0; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL1; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL2; /**< New Register */ + __IM uint32_t RFIMDCDCSTATUS; /**< New Register */ + __IOM uint32_t RPURATD0; /**< Root Access Type Descriptor Register */ + uint32_t RESERVED0[1019U]; /**< Reserved for future use */ + __IOM uint32_t RFIMDCDCCTRL0_SET; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL1_SET; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL2_SET; /**< New Register */ + __IM uint32_t RFIMDCDCSTATUS_SET; /**< New Register */ + __IOM uint32_t RPURATD0_SET; /**< Root Access Type Descriptor Register */ + uint32_t RESERVED1[1019U]; /**< Reserved for future use */ + __IOM uint32_t RFIMDCDCCTRL0_CLR; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL1_CLR; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL2_CLR; /**< New Register */ + __IM uint32_t RFIMDCDCSTATUS_CLR; /**< New Register */ + __IOM uint32_t RPURATD0_CLR; /**< Root Access Type Descriptor Register */ + uint32_t RESERVED2[1019U]; /**< Reserved for future use */ + __IOM uint32_t RFIMDCDCCTRL0_TGL; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL1_TGL; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL2_TGL; /**< New Register */ + __IM uint32_t RFIMDCDCSTATUS_TGL; /**< New Register */ + __IOM uint32_t RPURATD0_TGL; /**< Root Access Type Descriptor Register */ } PFMXPPRF_TypeDef; /** @} End of group EFR32SG23_PFMXPPRF */ @@ -79,136 +77,136 @@ typedef struct *****************************************************************************/ /* Bit fields for PFMXPPRF RFIMDCDCCTRL0 */ -#define _PFMXPPRF_RFIMDCDCCTRL0_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL0 */ -#define _PFMXPPRF_RFIMDCDCCTRL0_MASK 0x80000003UL /**< Mask for PFMXPPRF_RFIMDCDCCTRL0 */ -#define PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ (0x1UL << 0) /**< TX Max Req */ -#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_SHIFT 0 /**< Shift value for PFMXPPRF_TXMAXREQ */ -#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_MASK 0x1UL /**< Bit mask for PFMXPPRF_TXMAXREQ */ -#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0 */ -#define PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0*/ -#define PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ (0x1UL << 1) /**< RX PP Req */ -#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_SHIFT 1 /**< Shift value for PFMXPPRF_RXPPREQ */ -#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_MASK 0x2UL /**< Bit mask for PFMXPPRF_RXPPREQ */ -#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0 */ -#define PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0*/ +#define _PFMXPPRF_RFIMDCDCCTRL0_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL0 */ +#define _PFMXPPRF_RFIMDCDCCTRL0_MASK 0x80000003UL /**< Mask for PFMXPPRF_RFIMDCDCCTRL0 */ +#define PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ (0x1UL << 0) /**< TX Max Req */ +#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_SHIFT 0 /**< Shift value for PFMXPPRF_TXMAXREQ */ +#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_MASK 0x1UL /**< Bit mask for PFMXPPRF_TXMAXREQ */ +#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0 */ +#define PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0*/ +#define PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ (0x1UL << 1) /**< RX PP Req */ +#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_SHIFT 1 /**< Shift value for PFMXPPRF_RXPPREQ */ +#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_MASK 0x2UL /**< Bit mask for PFMXPPRF_RXPPREQ */ +#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0 */ +#define PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0*/ /* Bit fields for PFMXPPRF RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_RESETVALUE 0x00000014UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_MASK 0x0000003FUL /**< Mask for PFMXPPRF_RFIMDCDCCTRL1 */ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN (0x1UL << 0) /**< DCDC DIV Enable */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_SHIFT 0 /**< Shift value for PFMXPPRF_DCDCDIVEN */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_MASK 0x1UL /**< Bit mask for PFMXPPRF_DCDCDIVEN */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN (0x1UL << 1) /**< DCDC DIV Inverter Enable */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_SHIFT 1 /**< Shift value for PFMXPPRF_DCDCDIVINVEN */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_MASK 0x2UL /**< Bit mask for PFMXPPRF_DCDCDIVINVEN */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_SHIFT 2 /**< Shift value for PFMXPPRF_DCDCDIVRATIO */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_MASK 0x3CUL /**< Bit mask for PFMXPPRF_DCDCDIVRATIO */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT 0x00000005UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 0x00000000UL /**< Mode DIVRATIO8 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 0x00000001UL /**< Mode DIVRATIO9 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 0x00000002UL /**< Mode DIVRATIO10 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 0x00000003UL /**< Mode DIVRATIO11 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 0x00000004UL /**< Mode DIVRATIO12 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 0x00000005UL /**< Mode DIVRATIO13 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 0x00000006UL /**< Mode DIVRATIO14 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 0x00000007UL /**< Mode DIVRATIO15 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 0x00000008UL /**< Mode DIVRATIO16 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 0x00000009UL /**< Mode DIVRATIO17 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 0x0000000AUL /**< Mode DIVRATIO18 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 0x0000000BUL /**< Mode DIVRATIO19 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 0x0000000CUL /**< Mode DIVRATIO20 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 0x0000000DUL /**< Mode DIVRATIO21 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 0x0000000EUL /**< Mode DIVRATIO22 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 0x0000000FUL /**< Mode DIVRATIO23 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 << 2) /**< Shifted mode DIVRATIO8 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 << 2) /**< Shifted mode DIVRATIO9 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 << 2) /**< Shifted mode DIVRATIO10 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 << 2) /**< Shifted mode DIVRATIO11 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 << 2) /**< Shifted mode DIVRATIO12 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 << 2) /**< Shifted mode DIVRATIO13 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 << 2) /**< Shifted mode DIVRATIO14 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 << 2) /**< Shifted mode DIVRATIO15 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 << 2) /**< Shifted mode DIVRATIO16 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 << 2) /**< Shifted mode DIVRATIO17 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 << 2) /**< Shifted mode DIVRATIO18 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 << 2) /**< Shifted mode DIVRATIO19 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 << 2) /**< Shifted mode DIVRATIO20 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 << 2) /**< Shifted mode DIVRATIO21 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 << 2) /**< Shifted mode DIVRATIO22 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 << 2) /**< Shifted mode DIVRATIO23 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define _PFMXPPRF_RFIMDCDCCTRL1_RESETVALUE 0x00000014UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_MASK 0x0000003FUL /**< Mask for PFMXPPRF_RFIMDCDCCTRL1 */ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN (0x1UL << 0) /**< DCDC DIV Enable */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_SHIFT 0 /**< Shift value for PFMXPPRF_DCDCDIVEN */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_MASK 0x1UL /**< Bit mask for PFMXPPRF_DCDCDIVEN */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN (0x1UL << 1) /**< DCDC DIV Inverter Enable */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_SHIFT 1 /**< Shift value for PFMXPPRF_DCDCDIVINVEN */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_MASK 0x2UL /**< Bit mask for PFMXPPRF_DCDCDIVINVEN */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_SHIFT 2 /**< Shift value for PFMXPPRF_DCDCDIVRATIO */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_MASK 0x3CUL /**< Bit mask for PFMXPPRF_DCDCDIVRATIO */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT 0x00000005UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 0x00000000UL /**< Mode DIVRATIO8 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 0x00000001UL /**< Mode DIVRATIO9 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 0x00000002UL /**< Mode DIVRATIO10 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 0x00000003UL /**< Mode DIVRATIO11 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 0x00000004UL /**< Mode DIVRATIO12 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 0x00000005UL /**< Mode DIVRATIO13 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 0x00000006UL /**< Mode DIVRATIO14 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 0x00000007UL /**< Mode DIVRATIO15 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 0x00000008UL /**< Mode DIVRATIO16 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 0x00000009UL /**< Mode DIVRATIO17 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 0x0000000AUL /**< Mode DIVRATIO18 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 0x0000000BUL /**< Mode DIVRATIO19 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 0x0000000CUL /**< Mode DIVRATIO20 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 0x0000000DUL /**< Mode DIVRATIO21 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 0x0000000EUL /**< Mode DIVRATIO22 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 0x0000000FUL /**< Mode DIVRATIO23 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 << 2) /**< Shifted mode DIVRATIO8 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 << 2) /**< Shifted mode DIVRATIO9 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 << 2) /**< Shifted mode DIVRATIO10 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 << 2) /**< Shifted mode DIVRATIO11 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 << 2) /**< Shifted mode DIVRATIO12 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 << 2) /**< Shifted mode DIVRATIO13 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 << 2) /**< Shifted mode DIVRATIO14 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 << 2) /**< Shifted mode DIVRATIO15 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 << 2) /**< Shifted mode DIVRATIO16 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 << 2) /**< Shifted mode DIVRATIO17 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 << 2) /**< Shifted mode DIVRATIO18 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 << 2) /**< Shifted mode DIVRATIO19 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 << 2) /**< Shifted mode DIVRATIO20 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 << 2) /**< Shifted mode DIVRATIO21 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 << 2) /**< Shifted mode DIVRATIO22 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 << 2) /**< Shifted mode DIVRATIO23 for PFMXPPRF_RFIMDCDCCTRL1*/ /* Bit fields for PFMXPPRF RFIMDCDCCTRL2 */ -#define _PFMXPPRF_RFIMDCDCCTRL2_RESETVALUE 0x0AD0B4A0UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL2 */ -#define _PFMXPPRF_RFIMDCDCCTRL2_MASK 0x9FFFFFFFUL /**< Mask for PFMXPPRF_RFIMDCDCCTRL2 */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_SHIFT 0 /**< Shift value for PFMXPPRF_PPTMAX */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_MASK 0x1FFUL /**< Bit mask for PFMXPPRF_PPTMAX */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT 0x000000A0UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ -#define PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_SHIFT 9 /**< Shift value for PFMXPPRF_PPTMIN */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_MASK 0x3FE00UL /**< Bit mask for PFMXPPRF_PPTMIN */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT 0x0000005AUL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ -#define PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT << 9) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_SHIFT 18 /**< Shift value for PFMXPPRF_PPND */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_MASK 0x7FC0000UL /**< Bit mask for PFMXPPRF_PPND */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT 0x000000B4UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ -#define PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT << 18) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ -#define PFMXPPRF_RFIMDCDCCTRL2_PPCALEN (0x1UL << 27) /**< Pulse Pairing Calibration Loop Enable */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_SHIFT 27 /**< Shift value for PFMXPPRF_PPCALEN */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_MASK 0x8000000UL /**< Bit mask for PFMXPPRF_PPCALEN */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ -#define PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT << 27) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ -#define PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY (0x1UL << 28) /**< Pulse Pairing Sync Only */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_SHIFT 28 /**< Shift value for PFMXPPRF_PPSYNCONLY */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_MASK 0x10000000UL /**< Bit mask for PFMXPPRF_PPSYNCONLY */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ -#define PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT << 28) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ +#define _PFMXPPRF_RFIMDCDCCTRL2_RESETVALUE 0x0AD0B4A0UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL2 */ +#define _PFMXPPRF_RFIMDCDCCTRL2_MASK 0x9FFFFFFFUL /**< Mask for PFMXPPRF_RFIMDCDCCTRL2 */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_SHIFT 0 /**< Shift value for PFMXPPRF_PPTMAX */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_MASK 0x1FFUL /**< Bit mask for PFMXPPRF_PPTMAX */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT 0x000000A0UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ +#define PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_SHIFT 9 /**< Shift value for PFMXPPRF_PPTMIN */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_MASK 0x3FE00UL /**< Bit mask for PFMXPPRF_PPTMIN */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT 0x0000005AUL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ +#define PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT << 9) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_SHIFT 18 /**< Shift value for PFMXPPRF_PPND */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_MASK 0x7FC0000UL /**< Bit mask for PFMXPPRF_PPND */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT 0x000000B4UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ +#define PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT << 18) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ +#define PFMXPPRF_RFIMDCDCCTRL2_PPCALEN (0x1UL << 27) /**< Pulse Pairing Calibration Loop Enable */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_SHIFT 27 /**< Shift value for PFMXPPRF_PPCALEN */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_MASK 0x8000000UL /**< Bit mask for PFMXPPRF_PPCALEN */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ +#define PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT << 27) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ +#define PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY (0x1UL << 28) /**< Pulse Pairing Sync Only */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_SHIFT 28 /**< Shift value for PFMXPPRF_PPSYNCONLY */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_MASK 0x10000000UL /**< Bit mask for PFMXPPRF_PPSYNCONLY */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ +#define PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT << 28) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ /* Bit fields for PFMXPPRF RFIMDCDCSTATUS */ -#define _PFMXPPRF_RFIMDCDCSTATUS_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RFIMDCDCSTATUS */ -#define _PFMXPPRF_RFIMDCDCSTATUS_MASK 0x0001FF07UL /**< Mask for PFMXPPRF_RFIMDCDCSTATUS */ -#define PFMXPPRF_RFIMDCDCSTATUS_DCDCEN (0x1UL << 0) /**< DCDC Enable Status */ -#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_SHIFT 0 /**< Shift value for PFMXPPRF_DCDCEN */ -#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_MASK 0x1UL /**< Bit mask for PFMXPPRF_DCDCEN */ -#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ -#define PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ -#define PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS (0x1UL << 1) /**< TX MAX Status */ -#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_SHIFT 1 /**< Shift value for PFMXPPRF_TXMAXSTATUS */ -#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_MASK 0x2UL /**< Bit mask for PFMXPPRF_TXMAXSTATUS */ -#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ -#define PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ -#define PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS (0x1UL << 2) /**< RX PP Status */ -#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_SHIFT 2 /**< Shift value for PFMXPPRF_RXPPSTATUS */ -#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_MASK 0x4UL /**< Bit mask for PFMXPPRF_RXPPSTATUS */ -#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ -#define PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ -#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_SHIFT 8 /**< Shift value for PFMXPPRF_WNO1 */ -#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_MASK 0x1FF00UL /**< Bit mask for PFMXPPRF_WNO1 */ -#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ -#define PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT << 8) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ +#define _PFMXPPRF_RFIMDCDCSTATUS_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RFIMDCDCSTATUS */ +#define _PFMXPPRF_RFIMDCDCSTATUS_MASK 0x0001FF07UL /**< Mask for PFMXPPRF_RFIMDCDCSTATUS */ +#define PFMXPPRF_RFIMDCDCSTATUS_DCDCEN (0x1UL << 0) /**< DCDC Enable Status */ +#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_SHIFT 0 /**< Shift value for PFMXPPRF_DCDCEN */ +#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_MASK 0x1UL /**< Bit mask for PFMXPPRF_DCDCEN */ +#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ +#define PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ +#define PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS (0x1UL << 1) /**< TX MAX Status */ +#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_SHIFT 1 /**< Shift value for PFMXPPRF_TXMAXSTATUS */ +#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_MASK 0x2UL /**< Bit mask for PFMXPPRF_TXMAXSTATUS */ +#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ +#define PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ +#define PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS (0x1UL << 2) /**< RX PP Status */ +#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_SHIFT 2 /**< Shift value for PFMXPPRF_RXPPSTATUS */ +#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_MASK 0x4UL /**< Bit mask for PFMXPPRF_RXPPSTATUS */ +#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ +#define PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ +#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_SHIFT 8 /**< Shift value for PFMXPPRF_WNO1 */ +#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_MASK 0x1FF00UL /**< Bit mask for PFMXPPRF_WNO1 */ +#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ +#define PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT << 8) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ /* Bit fields for PFMXPPRF RPURATD0 */ -#define _PFMXPPRF_RPURATD0_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RPURATD0 */ -#define _PFMXPPRF_RPURATD0_MASK 0x00000007UL /**< Mask for PFMXPPRF_RPURATD0 */ -#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0 (0x1UL << 0) /**< RFIMDCDCCTRL0 Protection Bit */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_SHIFT 0 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL0 */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_MASK 0x1UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL0 */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ -#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ -#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1 (0x1UL << 1) /**< RFIMDCDCCTRL1 Protection Bit */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_SHIFT 1 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL1 */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_MASK 0x2UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL1 */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ -#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ -#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2 (0x1UL << 2) /**< RFIMDCDCCTRL2 Protection Bit */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_SHIFT 2 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL2 */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_MASK 0x4UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL2 */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ -#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ +#define _PFMXPPRF_RPURATD0_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RPURATD0 */ +#define _PFMXPPRF_RPURATD0_MASK 0x00000007UL /**< Mask for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0 (0x1UL << 0) /**< RFIMDCDCCTRL0 Protection Bit */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_SHIFT 0 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL0 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_MASK 0x1UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL0 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1 (0x1UL << 1) /**< RFIMDCDCCTRL1 Protection Bit */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_SHIFT 1 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL1 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_MASK 0x2UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL1 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2 (0x1UL << 2) /**< RFIMDCDCCTRL2 Protection Bit */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_SHIFT 2 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL2 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_MASK 0x4UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL2 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ /** @} End of group EFR32SG23_PFMXPPRF_BitFields */ /** @} End of group EFR32SG23_PFMXPPRF */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_prs.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_prs.h index 1d7d8ae2eb..b62040ad7e 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_prs.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_prs.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_PRS_H #define EFR32SG23_PRS_H - #define PRS_HAS_SET_CLEAR /**************************************************************************//** @@ -43,433 +42,428 @@ *****************************************************************************/ /** PRS ASYNC_CH Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t CTRL; /**< Async Channel Control Register */ +typedef struct { + __IOM uint32_t CTRL; /**< Async Channel Control Register */ } PRS_ASYNC_CH_TypeDef; - /** PRS SYNC_CH Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t CTRL; /**< Sync Channel Control Register */ +typedef struct { + __IOM uint32_t CTRL; /**< Sync Channel Control Register */ } PRS_SYNC_CH_TypeDef; - /** PRS Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< PRS IPVERSION */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t ASYNC_SWPULSE; /**< Software Pulse Register */ - __IOM uint32_t ASYNC_SWLEVEL; /**< Software Level Register */ - __IM uint32_t ASYNC_PEEK; /**< Async Channel Values */ - __IM uint32_t SYNC_PEEK; /**< Sync Channel Values */ - PRS_ASYNC_CH_TypeDef ASYNC_CH[12U]; /**< Async Channel registers */ - PRS_SYNC_CH_TypeDef SYNC_CH[4U]; /**< Sync Channel registers */ - __IOM uint32_t CONSUMER_CMU_CALDN; /**< CALDN consumer register */ - __IOM uint32_t CONSUMER_CMU_CALUP; /**< CALUP Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_CLK; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART0_RX; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_TRIGGER;/**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_CLK; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART1_RX; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_TRIGGER;/**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART2_CLK; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART2_RX; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART2_TRIGGER;/**< TRIGGER Consumer register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER;/**< SCAN consumer register */ - __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER;/**< SINGLE Consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0;/**< DMAREQ0 consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1;/**< DMAREQ1 Consumer register */ - uint32_t RESERVED2[4U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_LESENSE_START; /**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_CLEAR;/**< CLEAR consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_START;/**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_STOP; /**< STOP Consumer register */ - __IOM uint32_t CONSUMER_MODEM_DIN; /**< MODEM DIN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S0IN; /**< S0IN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S1IN; /**< S1IN Consumer register */ - uint32_t RESERVED3[11U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_RAC_CLR; /**< CLR consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN0; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN1; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN2; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN3; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_FORCETX; /**< FORCETX Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXDIS; /**< RXDIS Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXEN; /**< RXEN Consumer register */ - __IOM uint32_t CONSUMER_RAC_TXEN; /**< TXEN Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25;/**< TAMPERSRC25 consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26;/**< TAMPERSRC26 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27;/**< TAMPERSRC27 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28;/**< TAMPERSRC28 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29;/**< TAMPERSRC29 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30;/**< TAMPERSRC30 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31;/**< TAMPERSRC31 Consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN0; /**< IN0 consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN1; /**< IN1 Consumer register */ - __IOM uint32_t CONSUMER_HFXO0_OSCREQ; /**< OSCREQ consumer register */ - __IOM uint32_t CONSUMER_HFXO0_TIMEOUT; /**< TIMEOUT Consumer register */ - __IOM uint32_t CONSUMER_CORE_CTIIN0; /**< CTI0 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN1; /**< CTI1 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN2; /**< CTI2 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN3; /**< CTI3 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_M33RXEV; /**< M33 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC0; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC1; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC2; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTI; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS1; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS2; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC0; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC1; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC2; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTI; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS1; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS2; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC0; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC1; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC2; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTI; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS1; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS2; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC0; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC1; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC2; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTI; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS1; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS2; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC0; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC1; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC2; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTI; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS1; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS2; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_USART0_CLK; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_USART0_IR; /**< IR Consumer register */ - __IOM uint32_t CONSUMER_USART0_RX; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_USART0_TRIGGER;/**< TRIGGER Consumer register */ - uint32_t RESERVED4[3U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0;/**< ASYNCTRIG consumer register */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1;/**< ASYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0;/**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1;/**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC0; /**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC1; /**< SRC1 Consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC0; /**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC1; /**< SRC1 Consumer register */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - uint32_t RESERVED6[893U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< PRS IPVERSION */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - __IOM uint32_t ASYNC_SWPULSE_SET; /**< Software Pulse Register */ - __IOM uint32_t ASYNC_SWLEVEL_SET; /**< Software Level Register */ - __IM uint32_t ASYNC_PEEK_SET; /**< Async Channel Values */ - __IM uint32_t SYNC_PEEK_SET; /**< Sync Channel Values */ - PRS_ASYNC_CH_TypeDef ASYNC_CH_SET[12U]; /**< Async Channel registers */ - PRS_SYNC_CH_TypeDef SYNC_CH_SET[4U]; /**< Sync Channel registers */ - __IOM uint32_t CONSUMER_CMU_CALDN_SET; /**< CALDN consumer register */ - __IOM uint32_t CONSUMER_CMU_CALUP_SET; /**< CALUP Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_CLK_SET;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART0_RX_SET;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_TRIGGER_SET;/**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_CLK_SET;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART1_RX_SET;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_TRIGGER_SET;/**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART2_CLK_SET;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART2_RX_SET;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART2_TRIGGER_SET;/**< TRIGGER Consumer register */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_SET;/**< SCAN consumer register */ - __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_SET;/**< SINGLE Consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_SET;/**< DMAREQ0 consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_SET;/**< DMAREQ1 Consumer register */ - uint32_t RESERVED9[4U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_LESENSE_START_SET;/**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_CLEAR_SET;/**< CLEAR consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_START_SET;/**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_STOP_SET;/**< STOP Consumer register */ - __IOM uint32_t CONSUMER_MODEM_DIN_SET; /**< MODEM DIN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S0IN_SET;/**< S0IN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S1IN_SET;/**< S1IN Consumer register */ - uint32_t RESERVED10[11U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_RAC_CLR_SET; /**< CLR consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN0_SET;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN1_SET;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN2_SET;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN3_SET;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_FORCETX_SET;/**< FORCETX Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXDIS_SET; /**< RXDIS Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXEN_SET; /**< RXEN Consumer register */ - __IOM uint32_t CONSUMER_RAC_TXEN_SET; /**< TXEN Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_SET;/**< TAMPERSRC25 consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_SET;/**< TAMPERSRC26 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_SET;/**< TAMPERSRC27 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_SET;/**< TAMPERSRC28 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_SET;/**< TAMPERSRC29 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_SET;/**< TAMPERSRC30 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_SET;/**< TAMPERSRC31 Consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN0_SET;/**< IN0 consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN1_SET;/**< IN1 Consumer register */ - __IOM uint32_t CONSUMER_HFXO0_OSCREQ_SET;/**< OSCREQ consumer register */ - __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_SET;/**< TIMEOUT Consumer register */ - __IOM uint32_t CONSUMER_CORE_CTIIN0_SET;/**< CTI0 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN1_SET;/**< CTI1 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN2_SET;/**< CTI2 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN3_SET;/**< CTI3 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_M33RXEV_SET;/**< M33 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC0_SET;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC1_SET;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC2_SET;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTI_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS1_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS2_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC0_SET;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC1_SET;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC2_SET;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTI_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS1_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS2_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC0_SET;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC1_SET;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC2_SET;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTI_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS1_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS2_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC0_SET;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC1_SET;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC2_SET;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTI_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS1_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS2_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC0_SET;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC1_SET;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC2_SET;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTI_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS1_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS2_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_USART0_CLK_SET;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_USART0_IR_SET; /**< IR Consumer register */ - __IOM uint32_t CONSUMER_USART0_RX_SET; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_USART0_TRIGGER_SET;/**< TRIGGER Consumer register */ - uint32_t RESERVED11[3U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_SET;/**< ASYNCTRIG consumer register */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_SET;/**< ASYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_SET;/**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_SET;/**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC0_SET;/**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC1_SET;/**< SRC1 Consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC0_SET;/**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC1_SET;/**< SRC1 Consumer register */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - uint32_t RESERVED13[893U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< PRS IPVERSION */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - __IOM uint32_t ASYNC_SWPULSE_CLR; /**< Software Pulse Register */ - __IOM uint32_t ASYNC_SWLEVEL_CLR; /**< Software Level Register */ - __IM uint32_t ASYNC_PEEK_CLR; /**< Async Channel Values */ - __IM uint32_t SYNC_PEEK_CLR; /**< Sync Channel Values */ - PRS_ASYNC_CH_TypeDef ASYNC_CH_CLR[12U]; /**< Async Channel registers */ - PRS_SYNC_CH_TypeDef SYNC_CH_CLR[4U]; /**< Sync Channel registers */ - __IOM uint32_t CONSUMER_CMU_CALDN_CLR; /**< CALDN consumer register */ - __IOM uint32_t CONSUMER_CMU_CALUP_CLR; /**< CALUP Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_CLK_CLR;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART0_RX_CLR;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_TRIGGER_CLR;/**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_CLK_CLR;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART1_RX_CLR;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_TRIGGER_CLR;/**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART2_CLK_CLR;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART2_RX_CLR;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART2_TRIGGER_CLR;/**< TRIGGER Consumer register */ - uint32_t RESERVED15[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_CLR;/**< SCAN consumer register */ - __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_CLR;/**< SINGLE Consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_CLR;/**< DMAREQ0 consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_CLR;/**< DMAREQ1 Consumer register */ - uint32_t RESERVED16[4U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_LESENSE_START_CLR;/**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_CLEAR_CLR;/**< CLEAR consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_START_CLR;/**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_STOP_CLR;/**< STOP Consumer register */ - __IOM uint32_t CONSUMER_MODEM_DIN_CLR; /**< MODEM DIN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S0IN_CLR;/**< S0IN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S1IN_CLR;/**< S1IN Consumer register */ - uint32_t RESERVED17[11U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_RAC_CLR_CLR; /**< CLR consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN0_CLR;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN1_CLR;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN2_CLR;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN3_CLR;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_FORCETX_CLR;/**< FORCETX Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXDIS_CLR; /**< RXDIS Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXEN_CLR; /**< RXEN Consumer register */ - __IOM uint32_t CONSUMER_RAC_TXEN_CLR; /**< TXEN Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_CLR;/**< TAMPERSRC25 consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_CLR;/**< TAMPERSRC26 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_CLR;/**< TAMPERSRC27 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_CLR;/**< TAMPERSRC28 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_CLR;/**< TAMPERSRC29 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_CLR;/**< TAMPERSRC30 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_CLR;/**< TAMPERSRC31 Consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN0_CLR;/**< IN0 consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN1_CLR;/**< IN1 Consumer register */ - __IOM uint32_t CONSUMER_HFXO0_OSCREQ_CLR;/**< OSCREQ consumer register */ - __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_CLR;/**< TIMEOUT Consumer register */ - __IOM uint32_t CONSUMER_CORE_CTIIN0_CLR;/**< CTI0 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN1_CLR;/**< CTI1 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN2_CLR;/**< CTI2 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN3_CLR;/**< CTI3 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_M33RXEV_CLR;/**< M33 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC0_CLR;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC1_CLR;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC2_CLR;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTI_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS1_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS2_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC0_CLR;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC1_CLR;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC2_CLR;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTI_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS1_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS2_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC0_CLR;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC1_CLR;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC2_CLR;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTI_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS1_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS2_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC0_CLR;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC1_CLR;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC2_CLR;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTI_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS1_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS2_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC0_CLR;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC1_CLR;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC2_CLR;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTI_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS1_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS2_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_USART0_CLK_CLR;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_USART0_IR_CLR; /**< IR Consumer register */ - __IOM uint32_t CONSUMER_USART0_RX_CLR; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_USART0_TRIGGER_CLR;/**< TRIGGER Consumer register */ - uint32_t RESERVED18[3U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_CLR;/**< ASYNCTRIG consumer register */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_CLR;/**< ASYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_CLR;/**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_CLR;/**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC0_CLR;/**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC1_CLR;/**< SRC1 Consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC0_CLR;/**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC1_CLR;/**< SRC1 Consumer register */ - uint32_t RESERVED19[1U]; /**< Reserved for future use */ - uint32_t RESERVED20[893U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< PRS IPVERSION */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - __IOM uint32_t ASYNC_SWPULSE_TGL; /**< Software Pulse Register */ - __IOM uint32_t ASYNC_SWLEVEL_TGL; /**< Software Level Register */ - __IM uint32_t ASYNC_PEEK_TGL; /**< Async Channel Values */ - __IM uint32_t SYNC_PEEK_TGL; /**< Sync Channel Values */ - PRS_ASYNC_CH_TypeDef ASYNC_CH_TGL[12U]; /**< Async Channel registers */ - PRS_SYNC_CH_TypeDef SYNC_CH_TGL[4U]; /**< Sync Channel registers */ - __IOM uint32_t CONSUMER_CMU_CALDN_TGL; /**< CALDN consumer register */ - __IOM uint32_t CONSUMER_CMU_CALUP_TGL; /**< CALUP Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_CLK_TGL;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART0_RX_TGL;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_TRIGGER_TGL;/**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_CLK_TGL;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART1_RX_TGL;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_TRIGGER_TGL;/**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART2_CLK_TGL;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART2_RX_TGL;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART2_TRIGGER_TGL;/**< TRIGGER Consumer register */ - uint32_t RESERVED22[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_TGL;/**< SCAN consumer register */ - __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_TGL;/**< SINGLE Consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_TGL;/**< DMAREQ0 consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_TGL;/**< DMAREQ1 Consumer register */ - uint32_t RESERVED23[4U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_LESENSE_START_TGL;/**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_CLEAR_TGL;/**< CLEAR consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_START_TGL;/**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_STOP_TGL;/**< STOP Consumer register */ - __IOM uint32_t CONSUMER_MODEM_DIN_TGL; /**< MODEM DIN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S0IN_TGL;/**< S0IN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S1IN_TGL;/**< S1IN Consumer register */ - uint32_t RESERVED24[11U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_RAC_CLR_TGL; /**< CLR consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN0_TGL;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN1_TGL;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN2_TGL;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN3_TGL;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_FORCETX_TGL;/**< FORCETX Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXDIS_TGL; /**< RXDIS Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXEN_TGL; /**< RXEN Consumer register */ - __IOM uint32_t CONSUMER_RAC_TXEN_TGL; /**< TXEN Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_TGL;/**< TAMPERSRC25 consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_TGL;/**< TAMPERSRC26 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_TGL;/**< TAMPERSRC27 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_TGL;/**< TAMPERSRC28 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_TGL;/**< TAMPERSRC29 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_TGL;/**< TAMPERSRC30 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_TGL;/**< TAMPERSRC31 Consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN0_TGL;/**< IN0 consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN1_TGL;/**< IN1 Consumer register */ - __IOM uint32_t CONSUMER_HFXO0_OSCREQ_TGL;/**< OSCREQ consumer register */ - __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_TGL;/**< TIMEOUT Consumer register */ - __IOM uint32_t CONSUMER_CORE_CTIIN0_TGL;/**< CTI0 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN1_TGL;/**< CTI1 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN2_TGL;/**< CTI2 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN3_TGL;/**< CTI3 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_M33RXEV_TGL;/**< M33 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC0_TGL;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC1_TGL;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC2_TGL;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTI_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS1_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS2_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC0_TGL;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC1_TGL;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC2_TGL;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTI_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS1_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS2_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC0_TGL;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC1_TGL;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC2_TGL;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTI_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS1_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS2_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC0_TGL;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC1_TGL;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC2_TGL;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTI_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS1_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS2_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC0_TGL;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC1_TGL;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC2_TGL;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTI_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS1_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS2_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_USART0_CLK_TGL;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_USART0_IR_TGL; /**< IR Consumer register */ - __IOM uint32_t CONSUMER_USART0_RX_TGL; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_USART0_TRIGGER_TGL;/**< TRIGGER Consumer register */ - uint32_t RESERVED25[3U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_TGL;/**< ASYNCTRIG consumer register */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_TGL;/**< ASYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_TGL;/**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_TGL;/**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC0_TGL;/**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC1_TGL;/**< SRC1 Consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC0_TGL;/**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC1_TGL;/**< SRC1 Consumer register */ - uint32_t RESERVED26[1U]; /**< Reserved for future use */ +typedef struct { + __IM uint32_t IPVERSION; /**< PRS IPVERSION */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART2_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1; /**< DMAREQ1 Consumer register */ + uint32_t RESERVED2[4U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_LESENSE_START; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN; /**< MODEM DIN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN; /**< S1IN Consumer register */ + uint32_t RESERVED3[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1; /**< SRC1 Consumer register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + uint32_t RESERVED6[893U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< PRS IPVERSION */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_SET; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_SET; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_SET; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_SET; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_SET[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_SET[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_SET; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_SET; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_SET; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_SET; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART2_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_SET; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_SET; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_SET; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_SET; /**< DMAREQ1 Consumer register */ + uint32_t RESERVED9[4U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_LESENSE_START_SET; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_SET; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_SET; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_SET; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_SET; /**< MODEM DIN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_SET; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_SET; /**< S1IN Consumer register */ + uint32_t RESERVED10[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_SET; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_SET; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_SET; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_SET; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_SET; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_SET; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_SET; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_SET; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_SET; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_SET; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_SET; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_SET; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_SET; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_SET; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_SET; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_SET; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_SET; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_SET; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_SET; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_SET; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_SET; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_SET; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_SET; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_SET; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_SET; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_SET; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_SET; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_SET; /**< SRC1 Consumer register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[893U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< PRS IPVERSION */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_CLR; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_CLR; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_CLR; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_CLR; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_CLR[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_CLR[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_CLR; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_CLR; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_CLR; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART2_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_CLR; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_CLR; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_CLR; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_CLR; /**< DMAREQ1 Consumer register */ + uint32_t RESERVED16[4U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_LESENSE_START_CLR; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_CLR; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_CLR; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_CLR; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_CLR; /**< MODEM DIN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_CLR; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_CLR; /**< S1IN Consumer register */ + uint32_t RESERVED17[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_CLR; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_CLR; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_CLR; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_CLR; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_CLR; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_CLR; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_CLR; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_CLR; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_CLR; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_CLR; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_CLR; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_CLR; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_CLR; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_CLR; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_CLR; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_CLR; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_CLR; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_CLR; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_CLR; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_CLR; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_CLR; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_CLR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_CLR; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_CLR; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_CLR; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_CLR; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_CLR; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_CLR; /**< SRC1 Consumer register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + uint32_t RESERVED20[893U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< PRS IPVERSION */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_TGL; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_TGL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_TGL; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_TGL; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_TGL[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_TGL[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_TGL; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_TGL; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_TGL; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART2_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_TGL; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_TGL; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_TGL; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_TGL; /**< DMAREQ1 Consumer register */ + uint32_t RESERVED23[4U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_LESENSE_START_TGL; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_TGL; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_TGL; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_TGL; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_TGL; /**< MODEM DIN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_TGL; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_TGL; /**< S1IN Consumer register */ + uint32_t RESERVED24[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_TGL; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_TGL; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_TGL; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_TGL; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_TGL; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_TGL; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_TGL; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_TGL; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_TGL; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_TGL; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_TGL; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_TGL; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_TGL; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_TGL; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_TGL; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_TGL; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_TGL; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_TGL; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_TGL; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_TGL; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_TGL; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_TGL; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_TGL; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_TGL; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_TGL; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_TGL; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_TGL; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_TGL; /**< SRC1 Consumer register */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ } PRS_TypeDef; /** @} End of group EFR32SG23_PRS */ @@ -481,1076 +475,1076 @@ typedef struct *****************************************************************************/ /* Bit fields for PRS IPVERSION */ -#define _PRS_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for PRS_IPVERSION */ -#define _PRS_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PRS_IPVERSION */ -#define _PRS_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PRS_IPVERSION */ -#define _PRS_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PRS_IPVERSION */ -#define _PRS_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for PRS_IPVERSION */ -#define PRS_IPVERSION_IPVERSION_DEFAULT (_PRS_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_IPVERSION */ +#define _PRS_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for PRS_IPVERSION */ +#define _PRS_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for PRS_IPVERSION */ +#define PRS_IPVERSION_IPVERSION_DEFAULT (_PRS_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_IPVERSION */ /* Bit fields for PRS ASYNC_SWPULSE */ -#define _PRS_ASYNC_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWPULSE */ -#define _PRS_ASYNC_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ -#define _PRS_ASYNC_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ -#define _PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ -#define _PRS_ASYNC_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ -#define _PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ -#define _PRS_ASYNC_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ -#define _PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ -#define _PRS_ASYNC_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ -#define _PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ -#define _PRS_ASYNC_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ -#define _PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ -#define _PRS_ASYNC_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ -#define _PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ -#define _PRS_ASYNC_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ -#define _PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ -#define _PRS_ASYNC_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ -#define _PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ -#define _PRS_ASYNC_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ -#define _PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ -#define _PRS_ASYNC_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ -#define _PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ -#define _PRS_ASYNC_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ -#define _PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ -#define _PRS_ASYNC_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ -#define _PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ /* Bit fields for PRS ASYNC_SWLEVEL */ -#define _PRS_ASYNC_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWLEVEL */ -#define _PRS_ASYNC_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ /* Bit fields for PRS ASYNC_PEEK */ -#define _PRS_ASYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_PEEK */ -#define _PRS_ASYNC_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ -#define _PRS_ASYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ -#define _PRS_ASYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ -#define _PRS_ASYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH0VAL_DEFAULT (_PRS_ASYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ -#define _PRS_ASYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ -#define _PRS_ASYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ -#define _PRS_ASYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH1VAL_DEFAULT (_PRS_ASYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ -#define _PRS_ASYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ -#define _PRS_ASYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ -#define _PRS_ASYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH2VAL_DEFAULT (_PRS_ASYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ -#define _PRS_ASYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ -#define _PRS_ASYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ -#define _PRS_ASYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH3VAL_DEFAULT (_PRS_ASYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ -#define _PRS_ASYNC_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ -#define _PRS_ASYNC_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ -#define _PRS_ASYNC_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH4VAL_DEFAULT (_PRS_ASYNC_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ -#define _PRS_ASYNC_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ -#define _PRS_ASYNC_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ -#define _PRS_ASYNC_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH5VAL_DEFAULT (_PRS_ASYNC_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ -#define _PRS_ASYNC_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ -#define _PRS_ASYNC_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ -#define _PRS_ASYNC_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH6VAL_DEFAULT (_PRS_ASYNC_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ -#define _PRS_ASYNC_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ -#define _PRS_ASYNC_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ -#define _PRS_ASYNC_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH7VAL_DEFAULT (_PRS_ASYNC_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ -#define _PRS_ASYNC_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ -#define _PRS_ASYNC_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ -#define _PRS_ASYNC_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH8VAL_DEFAULT (_PRS_ASYNC_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ -#define _PRS_ASYNC_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ -#define _PRS_ASYNC_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ -#define _PRS_ASYNC_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH9VAL_DEFAULT (_PRS_ASYNC_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ -#define _PRS_ASYNC_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ -#define _PRS_ASYNC_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ -#define _PRS_ASYNC_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH10VAL_DEFAULT (_PRS_ASYNC_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ -#define _PRS_ASYNC_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ -#define _PRS_ASYNC_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ -#define _PRS_ASYNC_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH11VAL_DEFAULT (_PRS_ASYNC_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_ASYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL_DEFAULT (_PRS_ASYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_ASYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL_DEFAULT (_PRS_ASYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_ASYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL_DEFAULT (_PRS_ASYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_ASYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL_DEFAULT (_PRS_ASYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_ASYNC_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL_DEFAULT (_PRS_ASYNC_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_ASYNC_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL_DEFAULT (_PRS_ASYNC_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_ASYNC_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL_DEFAULT (_PRS_ASYNC_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_ASYNC_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL_DEFAULT (_PRS_ASYNC_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_ASYNC_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL_DEFAULT (_PRS_ASYNC_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_ASYNC_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL_DEFAULT (_PRS_ASYNC_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_ASYNC_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL_DEFAULT (_PRS_ASYNC_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_ASYNC_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL_DEFAULT (_PRS_ASYNC_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ /* Bit fields for PRS SYNC_PEEK */ -#define _PRS_SYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_PEEK */ -#define _PRS_SYNC_PEEK_MASK 0x0000000FUL /**< Mask for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel Value */ -#define _PRS_SYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ -#define _PRS_SYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ -#define _PRS_SYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH0VAL_DEFAULT (_PRS_SYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel Value */ -#define _PRS_SYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ -#define _PRS_SYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ -#define _PRS_SYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH1VAL_DEFAULT (_PRS_SYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel Value */ -#define _PRS_SYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ -#define _PRS_SYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ -#define _PRS_SYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH2VAL_DEFAULT (_PRS_SYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel Value */ -#define _PRS_SYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ -#define _PRS_SYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ -#define _PRS_SYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH3VAL_DEFAULT (_PRS_SYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define _PRS_SYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_PEEK */ +#define _PRS_SYNC_PEEK_MASK 0x0000000FUL /**< Mask for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL_DEFAULT (_PRS_SYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL_DEFAULT (_PRS_SYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL_DEFAULT (_PRS_SYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL_DEFAULT (_PRS_SYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ /* Bit fields for PRS ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_RESETVALUE 0x000C0000UL /**< Default value for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_MASK 0x0F0F7F07UL /**< Mask for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_SIGSEL_NONE (_PRS_ASYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT 16 /**< Shift value for PRS_FNSEL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_MASK 0xF0000UL /**< Bit mask for PRS_FNSEL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO 0x00000000UL /**< Mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B 0x00000001UL /**< Mode A_NOR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B 0x00000002UL /**< Mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A 0x00000003UL /**< Mode NOT_A for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B 0x00000004UL /**< Mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B 0x00000005UL /**< Mode NOT_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B 0x00000006UL /**< Mode A_XOR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B 0x00000007UL /**< Mode A_NAND_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B 0x00000008UL /**< Mode A_AND_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B 0x00000009UL /**< Mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_B 0x0000000AUL /**< Mode B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B 0x0000000BUL /**< Mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A 0x0000000CUL /**< Mode A for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B 0x0000000DUL /**< Mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B 0x0000000EUL /**< Mode A_OR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE 0x0000000FUL /**< Mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO << 16) /**< Shifted mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B << 16) /**< Shifted mode A_NOR_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B << 16) /**< Shifted mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A << 16) /**< Shifted mode NOT_A for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B << 16) /**< Shifted mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_B << 16) /**< Shifted mode NOT_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B << 16) /**< Shifted mode A_XOR_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B << 16) /**< Shifted mode A_NAND_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B << 16) /**< Shifted mode A_AND_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B << 16) /**< Shifted mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_B (_PRS_ASYNC_CH_CTRL_FNSEL_B << 16) /**< Shifted mode B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B << 16) /**< Shifted mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_A (_PRS_ASYNC_CH_CTRL_FNSEL_A << 16) /**< Shifted mode A for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B << 16) /**< Shifted mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B << 16) /**< Shifted mode A_OR_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE << 16) /**< Shifted mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL*/ -#define _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT 24 /**< Shift value for PRS_AUXSEL */ -#define _PRS_ASYNC_CH_CTRL_AUXSEL_MASK 0xF000000UL /**< Bit mask for PRS_AUXSEL */ -#define _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_RESETVALUE 0x000C0000UL /**< Default value for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_MASK 0x0F0F7F07UL /**< Mask for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_NONE (_PRS_ASYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT 16 /**< Shift value for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_MASK 0xF0000UL /**< Bit mask for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO 0x00000000UL /**< Mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B 0x00000001UL /**< Mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B 0x00000002UL /**< Mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A 0x00000003UL /**< Mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B 0x00000004UL /**< Mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B 0x00000005UL /**< Mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B 0x00000006UL /**< Mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B 0x00000007UL /**< Mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B 0x00000008UL /**< Mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B 0x00000009UL /**< Mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_B 0x0000000AUL /**< Mode B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B 0x0000000BUL /**< Mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A 0x0000000CUL /**< Mode A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B 0x0000000DUL /**< Mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B 0x0000000EUL /**< Mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE 0x0000000FUL /**< Mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO << 16) /**< Shifted mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B << 16) /**< Shifted mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B << 16) /**< Shifted mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A << 16) /**< Shifted mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B << 16) /**< Shifted mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_B << 16) /**< Shifted mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B << 16) /**< Shifted mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B << 16) /**< Shifted mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B << 16) /**< Shifted mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B << 16) /**< Shifted mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_B (_PRS_ASYNC_CH_CTRL_FNSEL_B << 16) /**< Shifted mode B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B << 16) /**< Shifted mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A (_PRS_ASYNC_CH_CTRL_FNSEL_A << 16) /**< Shifted mode A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B << 16) /**< Shifted mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B << 16) /**< Shifted mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE << 16) /**< Shifted mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL*/ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT 24 /**< Shift value for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_MASK 0xF000000UL /**< Bit mask for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ /* Bit fields for PRS SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_MASK 0x00007F07UL /**< Mask for PRS_SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ -#define _PRS_SYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ -#define _PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_SYNC_CH_CTRL */ -#define PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ -#define PRS_SYNC_CH_CTRL_SIGSEL_NONE (_PRS_SYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ -#define _PRS_SYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ -#define _PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ -#define PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_MASK 0x00007F07UL /**< Mask for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SIGSEL_NONE (_PRS_SYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ /* Bit fields for PRS CONSUMER_CMU_CALDN */ -#define _PRS_CONSUMER_CMU_CALDN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALDN */ -#define _PRS_CONSUMER_CMU_CALDN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALDN */ -#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALDN */ -#define PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALDN*/ +#define _PRS_CONSUMER_CMU_CALDN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALDN */ +#define PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALDN*/ /* Bit fields for PRS CONSUMER_CMU_CALUP */ -#define _PRS_CONSUMER_CMU_CALUP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALUP */ -#define _PRS_CONSUMER_CMU_CALUP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALUP */ -#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALUP */ -#define PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALUP*/ +#define _PRS_CONSUMER_CMU_CALUP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALUP */ +#define PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALUP*/ /* Bit fields for PRS CONSUMER_EUSART0_CLK */ -#define _PRS_CONSUMER_EUSART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_CLK */ -#define _PRS_CONSUMER_EUSART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_CLK */ -#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_CLK */ -#define PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_CLK*/ +#define _PRS_CONSUMER_EUSART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_CLK */ +#define PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_CLK*/ /* Bit fields for PRS CONSUMER_EUSART0_RX */ -#define _PRS_CONSUMER_EUSART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_RX */ -#define _PRS_CONSUMER_EUSART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_RX */ -#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_RX */ -#define PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_RX*/ +#define _PRS_CONSUMER_EUSART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_RX */ +#define PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_RX*/ /* Bit fields for PRS CONSUMER_EUSART0_TRIGGER */ -#define _PRS_CONSUMER_EUSART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_TRIGGER*/ -#define _PRS_CONSUMER_EUSART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_TRIGGER */ -#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ -#define PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define _PRS_CONSUMER_EUSART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define _PRS_CONSUMER_EUSART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_TRIGGER */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ /* Bit fields for PRS CONSUMER_EUSART1_CLK */ -#define _PRS_CONSUMER_EUSART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_CLK */ -#define _PRS_CONSUMER_EUSART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_CLK */ -#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_CLK */ -#define PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_CLK*/ +#define _PRS_CONSUMER_EUSART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_CLK */ +#define PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_CLK*/ /* Bit fields for PRS CONSUMER_EUSART1_RX */ -#define _PRS_CONSUMER_EUSART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_RX */ -#define _PRS_CONSUMER_EUSART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_RX */ -#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_RX */ -#define PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_RX*/ +#define _PRS_CONSUMER_EUSART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_RX */ +#define PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_RX*/ /* Bit fields for PRS CONSUMER_EUSART1_TRIGGER */ -#define _PRS_CONSUMER_EUSART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_TRIGGER*/ -#define _PRS_CONSUMER_EUSART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_TRIGGER */ -#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ -#define PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define _PRS_CONSUMER_EUSART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define _PRS_CONSUMER_EUSART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_TRIGGER */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ /* Bit fields for PRS CONSUMER_EUSART2_CLK */ -#define _PRS_CONSUMER_EUSART2_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_CLK */ -#define _PRS_CONSUMER_EUSART2_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_CLK */ -#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_CLK */ -#define PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_CLK*/ +#define _PRS_CONSUMER_EUSART2_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_CLK */ +#define _PRS_CONSUMER_EUSART2_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_CLK */ +#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_CLK */ +#define PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_CLK*/ /* Bit fields for PRS CONSUMER_EUSART2_RX */ -#define _PRS_CONSUMER_EUSART2_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_RX */ -#define _PRS_CONSUMER_EUSART2_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_RX */ -#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_RX */ -#define PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_RX*/ +#define _PRS_CONSUMER_EUSART2_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_RX */ +#define _PRS_CONSUMER_EUSART2_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_RX */ +#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_RX */ +#define PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_RX*/ /* Bit fields for PRS CONSUMER_EUSART2_TRIGGER */ -#define _PRS_CONSUMER_EUSART2_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_TRIGGER*/ -#define _PRS_CONSUMER_EUSART2_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_TRIGGER */ -#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_TRIGGER*/ -#define PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_TRIGGER*/ +#define _PRS_CONSUMER_EUSART2_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_TRIGGER*/ +#define _PRS_CONSUMER_EUSART2_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_TRIGGER */ +#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_TRIGGER*/ +#define PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_TRIGGER*/ /* Bit fields for PRS CONSUMER_IADC0_SCANTRIGGER */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SCANTRIGGER*/ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SCANTRIGGER */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ -#define PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ -#define PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SCANTRIGGER */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ /* Bit fields for PRS CONSUMER_IADC0_SINGLETRIGGER */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SINGLETRIGGER */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ -#define PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ -#define PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SINGLETRIGGER */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ /* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ0 */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ0 */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ -#define PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ0 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ /* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ1 */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ1 */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ -#define PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ1 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ /* Bit fields for PRS CONSUMER_LESENSE_START */ -#define _PRS_CONSUMER_LESENSE_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LESENSE_START*/ -#define _PRS_CONSUMER_LESENSE_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LESENSE_START */ -#define _PRS_CONSUMER_LESENSE_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LESENSE_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LESENSE_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LESENSE_START */ -#define PRS_CONSUMER_LESENSE_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LESENSE_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LESENSE_START*/ +#define _PRS_CONSUMER_LESENSE_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LESENSE_START*/ +#define _PRS_CONSUMER_LESENSE_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LESENSE_START */ +#define _PRS_CONSUMER_LESENSE_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LESENSE_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LESENSE_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LESENSE_START */ +#define PRS_CONSUMER_LESENSE_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LESENSE_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LESENSE_START*/ /* Bit fields for PRS CONSUMER_LETIMER0_CLEAR */ -#define _PRS_CONSUMER_LETIMER0_CLEAR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_CLEAR*/ -#define _PRS_CONSUMER_LETIMER0_CLEAR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_CLEAR */ -#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ -#define PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define _PRS_CONSUMER_LETIMER0_CLEAR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define _PRS_CONSUMER_LETIMER0_CLEAR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_CLEAR */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ /* Bit fields for PRS CONSUMER_LETIMER0_START */ -#define _PRS_CONSUMER_LETIMER0_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_START*/ -#define _PRS_CONSUMER_LETIMER0_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_START */ -#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ -#define PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ +#define _PRS_CONSUMER_LETIMER0_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_START*/ +#define _PRS_CONSUMER_LETIMER0_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_START */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ +#define PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ /* Bit fields for PRS CONSUMER_LETIMER0_STOP */ -#define _PRS_CONSUMER_LETIMER0_STOP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_STOP*/ -#define _PRS_CONSUMER_LETIMER0_STOP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_STOP */ -#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP */ -#define PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP*/ +#define _PRS_CONSUMER_LETIMER0_STOP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_STOP*/ +#define _PRS_CONSUMER_LETIMER0_STOP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_STOP */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP */ +#define PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP*/ /* Bit fields for PRS CONSUMER_MODEM_DIN */ -#define _PRS_CONSUMER_MODEM_DIN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_DIN */ -#define _PRS_CONSUMER_MODEM_DIN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_DIN */ -#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_DIN */ -#define PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_DIN*/ +#define _PRS_CONSUMER_MODEM_DIN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_DIN */ +#define PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_DIN*/ /* Bit fields for PRS CONSUMER_PCNT0_S0IN */ -#define _PRS_CONSUMER_PCNT0_S0IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S0IN */ -#define _PRS_CONSUMER_PCNT0_S0IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S0IN */ -#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN */ -#define PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN*/ +#define _PRS_CONSUMER_PCNT0_S0IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S0IN */ +#define _PRS_CONSUMER_PCNT0_S0IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S0IN */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN */ +#define PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN*/ /* Bit fields for PRS CONSUMER_PCNT0_S1IN */ -#define _PRS_CONSUMER_PCNT0_S1IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S1IN */ -#define _PRS_CONSUMER_PCNT0_S1IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S1IN */ -#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN */ -#define PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN*/ +#define _PRS_CONSUMER_PCNT0_S1IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S1IN */ +#define _PRS_CONSUMER_PCNT0_S1IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S1IN */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN */ +#define PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN*/ /* Bit fields for PRS CONSUMER_RAC_CLR */ -#define _PRS_CONSUMER_RAC_CLR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CLR */ -#define _PRS_CONSUMER_RAC_CLR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CLR */ -#define _PRS_CONSUMER_RAC_CLR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CLR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CLR */ -#define PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CLR*/ +#define _PRS_CONSUMER_RAC_CLR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CLR */ +#define PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CLR*/ /* Bit fields for PRS CONSUMER_RAC_CTIIN0 */ -#define _PRS_CONSUMER_RAC_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN0 */ -#define _PRS_CONSUMER_RAC_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN0 */ -#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0 */ -#define PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0*/ +#define _PRS_CONSUMER_RAC_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0 */ +#define PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0*/ /* Bit fields for PRS CONSUMER_RAC_CTIIN1 */ -#define _PRS_CONSUMER_RAC_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN1 */ -#define _PRS_CONSUMER_RAC_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN1 */ -#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1 */ -#define PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1*/ +#define _PRS_CONSUMER_RAC_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1 */ +#define PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1*/ /* Bit fields for PRS CONSUMER_RAC_CTIIN2 */ -#define _PRS_CONSUMER_RAC_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN2 */ -#define _PRS_CONSUMER_RAC_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN2 */ -#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2 */ -#define PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2*/ +#define _PRS_CONSUMER_RAC_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2 */ +#define PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2*/ /* Bit fields for PRS CONSUMER_RAC_CTIIN3 */ -#define _PRS_CONSUMER_RAC_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN3 */ -#define _PRS_CONSUMER_RAC_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN3 */ -#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3 */ -#define PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3*/ +#define _PRS_CONSUMER_RAC_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3 */ +#define PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3*/ /* Bit fields for PRS CONSUMER_RAC_FORCETX */ -#define _PRS_CONSUMER_RAC_FORCETX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_FORCETX */ -#define _PRS_CONSUMER_RAC_FORCETX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_FORCETX */ -#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_FORCETX */ -#define PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_FORCETX*/ +#define _PRS_CONSUMER_RAC_FORCETX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_FORCETX */ +#define PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_FORCETX*/ /* Bit fields for PRS CONSUMER_RAC_RXDIS */ -#define _PRS_CONSUMER_RAC_RXDIS_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXDIS */ -#define _PRS_CONSUMER_RAC_RXDIS_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXDIS */ -#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXDIS */ -#define PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXDIS*/ +#define _PRS_CONSUMER_RAC_RXDIS_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXDIS */ +#define PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXDIS*/ /* Bit fields for PRS CONSUMER_RAC_RXEN */ -#define _PRS_CONSUMER_RAC_RXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXEN */ -#define _PRS_CONSUMER_RAC_RXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXEN */ -#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXEN */ -#define PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXEN*/ +#define _PRS_CONSUMER_RAC_RXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXEN */ +#define PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXEN*/ /* Bit fields for PRS CONSUMER_RAC_TXEN */ -#define _PRS_CONSUMER_RAC_TXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_TXEN */ -#define _PRS_CONSUMER_RAC_TXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_TXEN */ -#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_TXEN */ -#define PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_TXEN*/ +#define _PRS_CONSUMER_RAC_TXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_TXEN */ +#define PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_TXEN*/ /* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC25 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC25 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC25 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ /* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC26 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC26 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC26 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ /* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC27 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC27 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC27 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ /* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC28 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC28 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC28 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ /* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC29 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC29 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC29 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ /* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC30 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC30 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC30 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ /* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC31 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC31 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC31 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ /* Bit fields for PRS CONSUMER_SYSRTC0_IN0 */ -#define _PRS_CONSUMER_SYSRTC0_IN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN0 */ -#define _PRS_CONSUMER_SYSRTC0_IN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN0 */ -#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0 */ -#define PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0*/ +#define _PRS_CONSUMER_SYSRTC0_IN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN0 */ +#define _PRS_CONSUMER_SYSRTC0_IN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN0 */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0 */ +#define PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0*/ /* Bit fields for PRS CONSUMER_SYSRTC0_IN1 */ -#define _PRS_CONSUMER_SYSRTC0_IN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN1 */ -#define _PRS_CONSUMER_SYSRTC0_IN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN1 */ -#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1 */ -#define PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1*/ +#define _PRS_CONSUMER_SYSRTC0_IN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN1 */ +#define _PRS_CONSUMER_SYSRTC0_IN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN1 */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1 */ +#define PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1*/ /* Bit fields for PRS CONSUMER_HFXO0_OSCREQ */ -#define _PRS_CONSUMER_HFXO0_OSCREQ_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_OSCREQ */ -#define _PRS_CONSUMER_HFXO0_OSCREQ_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_OSCREQ */ -#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ */ -#define PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ*/ +#define _PRS_CONSUMER_HFXO0_OSCREQ_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_OSCREQ */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_OSCREQ */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ */ +#define PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ*/ /* Bit fields for PRS CONSUMER_HFXO0_TIMEOUT */ -#define _PRS_CONSUMER_HFXO0_TIMEOUT_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_TIMEOUT*/ -#define _PRS_CONSUMER_HFXO0_TIMEOUT_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_TIMEOUT */ -#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT */ -#define PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT*/ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_TIMEOUT*/ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_TIMEOUT */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT */ +#define PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT*/ /* Bit fields for PRS CONSUMER_CORE_CTIIN0 */ -#define _PRS_CONSUMER_CORE_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN0 */ -#define _PRS_CONSUMER_CORE_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN0 */ -#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0 */ -#define PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0*/ +#define _PRS_CONSUMER_CORE_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0 */ +#define PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0*/ /* Bit fields for PRS CONSUMER_CORE_CTIIN1 */ -#define _PRS_CONSUMER_CORE_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN1 */ -#define _PRS_CONSUMER_CORE_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN1 */ -#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1 */ -#define PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1*/ +#define _PRS_CONSUMER_CORE_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1 */ +#define PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1*/ /* Bit fields for PRS CONSUMER_CORE_CTIIN2 */ -#define _PRS_CONSUMER_CORE_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN2 */ -#define _PRS_CONSUMER_CORE_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN2 */ -#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2 */ -#define PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2*/ +#define _PRS_CONSUMER_CORE_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2 */ +#define PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2*/ /* Bit fields for PRS CONSUMER_CORE_CTIIN3 */ -#define _PRS_CONSUMER_CORE_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN3 */ -#define _PRS_CONSUMER_CORE_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN3 */ -#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3 */ -#define PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3*/ +#define _PRS_CONSUMER_CORE_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3 */ +#define PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3*/ /* Bit fields for PRS CONSUMER_CORE_M33RXEV */ -#define _PRS_CONSUMER_CORE_M33RXEV_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_M33RXEV */ -#define _PRS_CONSUMER_CORE_M33RXEV_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_M33RXEV */ -#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV */ -#define PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV*/ +#define _PRS_CONSUMER_CORE_M33RXEV_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV */ +#define PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV*/ /* Bit fields for PRS CONSUMER_TIMER0_CC0 */ -#define _PRS_CONSUMER_TIMER0_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC0 */ -#define _PRS_CONSUMER_TIMER0_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC0 */ -#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ -#define PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ -#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ -#define PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ +#define _PRS_CONSUMER_TIMER0_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ /* Bit fields for PRS CONSUMER_TIMER0_CC1 */ -#define _PRS_CONSUMER_TIMER0_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC1 */ -#define _PRS_CONSUMER_TIMER0_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC1 */ -#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ -#define PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ -#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ -#define PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ +#define _PRS_CONSUMER_TIMER0_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ /* Bit fields for PRS CONSUMER_TIMER0_CC2 */ -#define _PRS_CONSUMER_TIMER0_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC2 */ -#define _PRS_CONSUMER_TIMER0_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC2 */ -#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ -#define PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ -#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ -#define PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ +#define _PRS_CONSUMER_TIMER0_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ /* Bit fields for PRS CONSUMER_TIMER0_DTI */ -#define _PRS_CONSUMER_TIMER0_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTI */ -#define _PRS_CONSUMER_TIMER0_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTI */ -#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTI */ -#define PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTI*/ +#define _PRS_CONSUMER_TIMER0_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTI */ +#define PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTI*/ /* Bit fields for PRS CONSUMER_TIMER0_DTIFS1 */ -#define _PRS_CONSUMER_TIMER0_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS1*/ -#define _PRS_CONSUMER_TIMER0_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS1 */ -#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1 */ -#define PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1*/ +#define _PRS_CONSUMER_TIMER0_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS1*/ +#define _PRS_CONSUMER_TIMER0_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1*/ /* Bit fields for PRS CONSUMER_TIMER0_DTIFS2 */ -#define _PRS_CONSUMER_TIMER0_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS2*/ -#define _PRS_CONSUMER_TIMER0_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS2 */ -#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2 */ -#define PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2*/ +#define _PRS_CONSUMER_TIMER0_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS2*/ +#define _PRS_CONSUMER_TIMER0_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2*/ /* Bit fields for PRS CONSUMER_TIMER1_CC0 */ -#define _PRS_CONSUMER_TIMER1_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC0 */ -#define _PRS_CONSUMER_TIMER1_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC0 */ -#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ -#define PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ -#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ -#define PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ +#define _PRS_CONSUMER_TIMER1_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ /* Bit fields for PRS CONSUMER_TIMER1_CC1 */ -#define _PRS_CONSUMER_TIMER1_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC1 */ -#define _PRS_CONSUMER_TIMER1_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC1 */ -#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ -#define PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ -#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ -#define PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ +#define _PRS_CONSUMER_TIMER1_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ /* Bit fields for PRS CONSUMER_TIMER1_CC2 */ -#define _PRS_CONSUMER_TIMER1_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC2 */ -#define _PRS_CONSUMER_TIMER1_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC2 */ -#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ -#define PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ -#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ -#define PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ +#define _PRS_CONSUMER_TIMER1_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ /* Bit fields for PRS CONSUMER_TIMER1_DTI */ -#define _PRS_CONSUMER_TIMER1_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTI */ -#define _PRS_CONSUMER_TIMER1_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTI */ -#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTI */ -#define PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTI*/ +#define _PRS_CONSUMER_TIMER1_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTI */ +#define PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTI*/ /* Bit fields for PRS CONSUMER_TIMER1_DTIFS1 */ -#define _PRS_CONSUMER_TIMER1_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS1*/ -#define _PRS_CONSUMER_TIMER1_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS1 */ -#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1 */ -#define PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1*/ +#define _PRS_CONSUMER_TIMER1_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS1*/ +#define _PRS_CONSUMER_TIMER1_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1*/ /* Bit fields for PRS CONSUMER_TIMER1_DTIFS2 */ -#define _PRS_CONSUMER_TIMER1_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS2*/ -#define _PRS_CONSUMER_TIMER1_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS2 */ -#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2 */ -#define PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2*/ +#define _PRS_CONSUMER_TIMER1_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS2*/ +#define _PRS_CONSUMER_TIMER1_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2*/ /* Bit fields for PRS CONSUMER_TIMER2_CC0 */ -#define _PRS_CONSUMER_TIMER2_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC0 */ -#define _PRS_CONSUMER_TIMER2_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC0 */ -#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ -#define PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ -#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ -#define PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ +#define _PRS_CONSUMER_TIMER2_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ /* Bit fields for PRS CONSUMER_TIMER2_CC1 */ -#define _PRS_CONSUMER_TIMER2_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC1 */ -#define _PRS_CONSUMER_TIMER2_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC1 */ -#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ -#define PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ -#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ -#define PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ +#define _PRS_CONSUMER_TIMER2_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ /* Bit fields for PRS CONSUMER_TIMER2_CC2 */ -#define _PRS_CONSUMER_TIMER2_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC2 */ -#define _PRS_CONSUMER_TIMER2_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC2 */ -#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ -#define PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ -#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ -#define PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ +#define _PRS_CONSUMER_TIMER2_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ /* Bit fields for PRS CONSUMER_TIMER2_DTI */ -#define _PRS_CONSUMER_TIMER2_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTI */ -#define _PRS_CONSUMER_TIMER2_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTI */ -#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTI */ -#define PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTI*/ +#define _PRS_CONSUMER_TIMER2_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTI */ +#define PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTI*/ /* Bit fields for PRS CONSUMER_TIMER2_DTIFS1 */ -#define _PRS_CONSUMER_TIMER2_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS1*/ -#define _PRS_CONSUMER_TIMER2_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS1 */ -#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1 */ -#define PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1*/ +#define _PRS_CONSUMER_TIMER2_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS1*/ +#define _PRS_CONSUMER_TIMER2_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1*/ /* Bit fields for PRS CONSUMER_TIMER2_DTIFS2 */ -#define _PRS_CONSUMER_TIMER2_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS2*/ -#define _PRS_CONSUMER_TIMER2_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS2 */ -#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2 */ -#define PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2*/ +#define _PRS_CONSUMER_TIMER2_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS2*/ +#define _PRS_CONSUMER_TIMER2_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2*/ /* Bit fields for PRS CONSUMER_TIMER3_CC0 */ -#define _PRS_CONSUMER_TIMER3_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC0 */ -#define _PRS_CONSUMER_TIMER3_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC0 */ -#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ -#define PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ -#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ -#define PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ +#define _PRS_CONSUMER_TIMER3_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ /* Bit fields for PRS CONSUMER_TIMER3_CC1 */ -#define _PRS_CONSUMER_TIMER3_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC1 */ -#define _PRS_CONSUMER_TIMER3_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC1 */ -#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ -#define PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ -#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ -#define PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ +#define _PRS_CONSUMER_TIMER3_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ /* Bit fields for PRS CONSUMER_TIMER3_CC2 */ -#define _PRS_CONSUMER_TIMER3_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC2 */ -#define _PRS_CONSUMER_TIMER3_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC2 */ -#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ -#define PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ -#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ -#define PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ +#define _PRS_CONSUMER_TIMER3_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ /* Bit fields for PRS CONSUMER_TIMER3_DTI */ -#define _PRS_CONSUMER_TIMER3_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTI */ -#define _PRS_CONSUMER_TIMER3_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTI */ -#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTI */ -#define PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTI*/ +#define _PRS_CONSUMER_TIMER3_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTI */ +#define PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTI*/ /* Bit fields for PRS CONSUMER_TIMER3_DTIFS1 */ -#define _PRS_CONSUMER_TIMER3_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS1*/ -#define _PRS_CONSUMER_TIMER3_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS1 */ -#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1 */ -#define PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1*/ +#define _PRS_CONSUMER_TIMER3_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS1*/ +#define _PRS_CONSUMER_TIMER3_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1*/ /* Bit fields for PRS CONSUMER_TIMER3_DTIFS2 */ -#define _PRS_CONSUMER_TIMER3_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS2*/ -#define _PRS_CONSUMER_TIMER3_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS2 */ -#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2 */ -#define PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2*/ +#define _PRS_CONSUMER_TIMER3_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS2*/ +#define _PRS_CONSUMER_TIMER3_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2*/ /* Bit fields for PRS CONSUMER_TIMER4_CC0 */ -#define _PRS_CONSUMER_TIMER4_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC0 */ -#define _PRS_CONSUMER_TIMER4_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC0 */ -#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ -#define PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ -#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ -#define PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ +#define _PRS_CONSUMER_TIMER4_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ /* Bit fields for PRS CONSUMER_TIMER4_CC1 */ -#define _PRS_CONSUMER_TIMER4_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC1 */ -#define _PRS_CONSUMER_TIMER4_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC1 */ -#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ -#define PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ -#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ -#define PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ +#define _PRS_CONSUMER_TIMER4_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ /* Bit fields for PRS CONSUMER_TIMER4_CC2 */ -#define _PRS_CONSUMER_TIMER4_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC2 */ -#define _PRS_CONSUMER_TIMER4_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC2 */ -#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ -#define PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ -#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ -#define PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ +#define _PRS_CONSUMER_TIMER4_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ /* Bit fields for PRS CONSUMER_TIMER4_DTI */ -#define _PRS_CONSUMER_TIMER4_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTI */ -#define _PRS_CONSUMER_TIMER4_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTI */ -#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTI */ -#define PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTI*/ +#define _PRS_CONSUMER_TIMER4_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTI */ +#define PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTI*/ /* Bit fields for PRS CONSUMER_TIMER4_DTIFS1 */ -#define _PRS_CONSUMER_TIMER4_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS1*/ -#define _PRS_CONSUMER_TIMER4_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS1 */ -#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1 */ -#define PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1*/ +#define _PRS_CONSUMER_TIMER4_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS1*/ +#define _PRS_CONSUMER_TIMER4_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1*/ /* Bit fields for PRS CONSUMER_TIMER4_DTIFS2 */ -#define _PRS_CONSUMER_TIMER4_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS2*/ -#define _PRS_CONSUMER_TIMER4_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS2 */ -#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2 */ -#define PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2*/ +#define _PRS_CONSUMER_TIMER4_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS2*/ +#define _PRS_CONSUMER_TIMER4_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2*/ /* Bit fields for PRS CONSUMER_USART0_CLK */ -#define _PRS_CONSUMER_USART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_CLK */ -#define _PRS_CONSUMER_USART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_CLK */ -#define _PRS_CONSUMER_USART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_CLK */ -#define PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_CLK*/ +#define _PRS_CONSUMER_USART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_CLK */ +#define PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_CLK*/ /* Bit fields for PRS CONSUMER_USART0_IR */ -#define _PRS_CONSUMER_USART0_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_IR */ -#define _PRS_CONSUMER_USART0_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_IR */ -#define _PRS_CONSUMER_USART0_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_IR */ -#define PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_IR*/ +#define _PRS_CONSUMER_USART0_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_IR */ +#define PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_IR*/ /* Bit fields for PRS CONSUMER_USART0_RX */ -#define _PRS_CONSUMER_USART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_RX */ -#define _PRS_CONSUMER_USART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_RX */ -#define _PRS_CONSUMER_USART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_RX */ -#define PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_RX*/ +#define _PRS_CONSUMER_USART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_RX */ +#define PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_RX*/ /* Bit fields for PRS CONSUMER_USART0_TRIGGER */ -#define _PRS_CONSUMER_USART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_TRIGGER*/ -#define _PRS_CONSUMER_USART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_TRIGGER */ -#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ -#define PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ +#define _PRS_CONSUMER_USART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_TRIGGER*/ +#define _PRS_CONSUMER_USART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_TRIGGER */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ +#define PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ /* Bit fields for PRS CONSUMER_VDAC0_ASYNCTRIGCH0 */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0 */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ -#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ /* Bit fields for PRS CONSUMER_VDAC0_ASYNCTRIGCH1 */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1 */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ -#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ /* Bit fields for PRS CONSUMER_VDAC0_SYNCTRIGCH0 */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH0 */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ -#define PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ /* Bit fields for PRS CONSUMER_VDAC0_SYNCTRIGCH1 */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH1 */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ -#define PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ /* Bit fields for PRS CONSUMER_WDOG0_SRC0 */ -#define _PRS_CONSUMER_WDOG0_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC0 */ -#define _PRS_CONSUMER_WDOG0_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC0 */ -#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0 */ -#define PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0*/ +#define _PRS_CONSUMER_WDOG0_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0 */ +#define PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0*/ /* Bit fields for PRS CONSUMER_WDOG0_SRC1 */ -#define _PRS_CONSUMER_WDOG0_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC1 */ -#define _PRS_CONSUMER_WDOG0_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC1 */ -#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1 */ -#define PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1*/ +#define _PRS_CONSUMER_WDOG0_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1 */ +#define PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1*/ /* Bit fields for PRS CONSUMER_WDOG1_SRC0 */ -#define _PRS_CONSUMER_WDOG1_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC0 */ -#define _PRS_CONSUMER_WDOG1_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC0 */ -#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0 */ -#define PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0*/ +#define _PRS_CONSUMER_WDOG1_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC0 */ +#define _PRS_CONSUMER_WDOG1_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC0 */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0 */ +#define PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0*/ /* Bit fields for PRS CONSUMER_WDOG1_SRC1 */ -#define _PRS_CONSUMER_WDOG1_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC1 */ -#define _PRS_CONSUMER_WDOG1_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC1 */ -#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1 */ -#define PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1*/ +#define _PRS_CONSUMER_WDOG1_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC1 */ +#define _PRS_CONSUMER_WDOG1_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC1 */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1 */ +#define PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1*/ /** @} End of group EFR32SG23_PRS_BitFields */ /** @} End of group EFR32SG23_PRS */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_prs_signals.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_prs_signals.h index 9ece492027..175c521eb0 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_scratchpad.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_scratchpad.h index 40d723c325..bb801e5275 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_scratchpad.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_SCRATCHPAD_H #define EFR32SG23_SCRATCHPAD_H - #define SCRATCHPAD_HAS_SET_CLEAR /**************************************************************************//** @@ -43,19 +42,18 @@ *****************************************************************************/ /** SCRATCHPAD Register Declaration. */ -typedef struct -{ - __IOM uint32_t SREG0; /**< Scratchpad Register 0 */ - __IOM uint32_t SREG1; /**< Scratchpad Register 1 */ - uint32_t RESERVED0[1022U]; /**< Reserved for future use */ - __IOM uint32_t SREG0_SET; /**< Scratchpad Register 0 */ - __IOM uint32_t SREG1_SET; /**< Scratchpad Register 1 */ - uint32_t RESERVED1[1022U]; /**< Reserved for future use */ - __IOM uint32_t SREG0_CLR; /**< Scratchpad Register 0 */ - __IOM uint32_t SREG1_CLR; /**< Scratchpad Register 1 */ - uint32_t RESERVED2[1022U]; /**< Reserved for future use */ - __IOM uint32_t SREG0_TGL; /**< Scratchpad Register 0 */ - __IOM uint32_t SREG1_TGL; /**< Scratchpad Register 1 */ +typedef struct { + __IOM uint32_t SREG0; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1; /**< Scratchpad Register 1 */ + uint32_t RESERVED0[1022U]; /**< Reserved for future use */ + __IOM uint32_t SREG0_SET; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1_SET; /**< Scratchpad Register 1 */ + uint32_t RESERVED1[1022U]; /**< Reserved for future use */ + __IOM uint32_t SREG0_CLR; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1_CLR; /**< Scratchpad Register 1 */ + uint32_t RESERVED2[1022U]; /**< Reserved for future use */ + __IOM uint32_t SREG0_TGL; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1_TGL; /**< Scratchpad Register 1 */ } SCRATCHPAD_TypeDef; /** @} End of group EFR32SG23_SCRATCHPAD */ @@ -67,20 +65,20 @@ typedef struct *****************************************************************************/ /* Bit fields for SCRATCHPAD SREG0 */ -#define _SCRATCHPAD_SREG0_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG0 */ -#define _SCRATCHPAD_SREG0_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG0 */ -#define _SCRATCHPAD_SREG0_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */ -#define _SCRATCHPAD_SREG0_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */ -#define _SCRATCHPAD_SREG0_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG0 */ -#define SCRATCHPAD_SREG0_SCRATCH_DEFAULT (_SCRATCHPAD_SREG0_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG0 */ +#define _SCRATCHPAD_SREG0_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG0 */ +#define _SCRATCHPAD_SREG0_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG0 */ +#define _SCRATCHPAD_SREG0_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG0_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG0_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG0 */ +#define SCRATCHPAD_SREG0_SCRATCH_DEFAULT (_SCRATCHPAD_SREG0_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG0 */ /* Bit fields for SCRATCHPAD SREG1 */ -#define _SCRATCHPAD_SREG1_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG1 */ -#define _SCRATCHPAD_SREG1_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG1 */ -#define _SCRATCHPAD_SREG1_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */ -#define _SCRATCHPAD_SREG1_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */ -#define _SCRATCHPAD_SREG1_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG1 */ -#define SCRATCHPAD_SREG1_SCRATCH_DEFAULT (_SCRATCHPAD_SREG1_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG1 */ +#define _SCRATCHPAD_SREG1_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG1 */ +#define _SCRATCHPAD_SREG1_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG1 */ +#define _SCRATCHPAD_SREG1_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG1_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG1_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG1 */ +#define SCRATCHPAD_SREG1_SCRATCH_DEFAULT (_SCRATCHPAD_SREG1_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG1 */ /** @} End of group EFR32SG23_SCRATCHPAD_BitFields */ /** @} End of group EFR32SG23_SCRATCHPAD */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_semailbox.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_semailbox.h index d3702b2344..def923067c 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_semailbox.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -41,17 +41,16 @@ *****************************************************************************/ /** SEMAILBOX_HOST Register Declaration. */ -typedef struct -{ - __IOM uint32_t FIFO; /**< ESECURE_MAILBOX_FIFO */ - uint32_t RESERVED0[15U]; /**< Reserved for future use */ - __IM uint32_t TX_STATUS; /**< ESECURE_MAILBOX_TXSTAT */ - __IM uint32_t RX_STATUS; /**< ESECURE_MAILBOX_RXSTAT */ - __IM uint32_t TX_PROT; /**< ESECURE_MAILBOX_TXPROTECT */ - __IM uint32_t RX_PROT; /**< ESECURE_MAILBOX_RXPROTECT */ - __IOM uint32_t TX_HEADER; /**< ESECURE_MAILBOX_TXHEADER */ - __IM uint32_t RX_HEADER; /**< ESECURE_MAILBOX_RXHEADER */ - __IOM uint32_t CONFIGURATION; /**< ESECURE_MAILBOX_CONFIG */ +typedef struct { + __IOM uint32_t FIFO; /**< ESECURE_MAILBOX_FIFO */ + uint32_t RESERVED0[15U]; /**< Reserved for future use */ + __IM uint32_t TX_STATUS; /**< ESECURE_MAILBOX_TXSTAT */ + __IM uint32_t RX_STATUS; /**< ESECURE_MAILBOX_RXSTAT */ + __IM uint32_t TX_PROT; /**< ESECURE_MAILBOX_TXPROTECT */ + __IM uint32_t RX_PROT; /**< ESECURE_MAILBOX_RXPROTECT */ + __IOM uint32_t TX_HEADER; /**< ESECURE_MAILBOX_TXHEADER */ + __IM uint32_t RX_HEADER; /**< ESECURE_MAILBOX_RXHEADER */ + __IOM uint32_t CONFIGURATION; /**< ESECURE_MAILBOX_CONFIG */ } SEMAILBOX_HOST_TypeDef; /** @} End of group EFR32SG23_SEMAILBOX_HOST */ @@ -63,147 +62,147 @@ typedef struct *****************************************************************************/ /* Bit fields for SEMAILBOX FIFO */ -#define _SEMAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_FIFO */ -#define _SEMAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_FIFO */ -#define _SEMAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ -#define _SEMAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ -#define _SEMAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_FIFO */ -#define SEMAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_FIFO */ +#define SEMAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_FIFO */ /* Bit fields for SEMAILBOX TX_STATUS */ -#define _SEMAILBOX_TX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_STATUS */ -#define _SEMAILBOX_TX_STATUS_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_TX_STATUS */ -#define _SEMAILBOX_TX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_TX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ -#define SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ -#define _SEMAILBOX_TX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_TX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ -#define SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ -#define SEMAILBOX_TX_STATUS_TXINT (0x1UL << 20) /**< TXINT */ -#define _SEMAILBOX_TX_STATUS_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ -#define _SEMAILBOX_TX_STATUS_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ -#define _SEMAILBOX_TX_STATUS_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ -#define SEMAILBOX_TX_STATUS_TXINT_DEFAULT (_SEMAILBOX_TX_STATUS_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ -#define SEMAILBOX_TX_STATUS_TXFULL (0x1UL << 21) /**< TXFULL */ -#define _SEMAILBOX_TX_STATUS_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ -#define _SEMAILBOX_TX_STATUS_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ -#define _SEMAILBOX_TX_STATUS_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ -#define SEMAILBOX_TX_STATUS_TXFULL_DEFAULT (_SEMAILBOX_TX_STATUS_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ -#define SEMAILBOX_TX_STATUS_TXERROR (0x1UL << 23) /**< TXERROR */ -#define _SEMAILBOX_TX_STATUS_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ -#define _SEMAILBOX_TX_STATUS_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ -#define _SEMAILBOX_TX_STATUS_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ -#define SEMAILBOX_TX_STATUS_TXERROR_DEFAULT (_SEMAILBOX_TX_STATUS_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define _SEMAILBOX_TX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define _SEMAILBOX_TX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_TX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXINT (0x1UL << 20) /**< TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXINT_DEFAULT (_SEMAILBOX_TX_STATUS_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXFULL (0x1UL << 21) /**< TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXFULL_DEFAULT (_SEMAILBOX_TX_STATUS_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXERROR (0x1UL << 23) /**< TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXERROR_DEFAULT (_SEMAILBOX_TX_STATUS_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ /* Bit fields for SEMAILBOX RX_STATUS */ -#define _SEMAILBOX_RX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_STATUS */ -#define _SEMAILBOX_RX_STATUS_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_RX_STATUS */ -#define _SEMAILBOX_RX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_RX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ -#define _SEMAILBOX_RX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_RX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ -#define SEMAILBOX_RX_STATUS_RXINT (0x1UL << 20) /**< RXINT */ -#define _SEMAILBOX_RX_STATUS_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ -#define _SEMAILBOX_RX_STATUS_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ -#define _SEMAILBOX_RX_STATUS_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_RXINT_DEFAULT (_SEMAILBOX_RX_STATUS_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ -#define SEMAILBOX_RX_STATUS_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ -#define _SEMAILBOX_RX_STATUS_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ -#define _SEMAILBOX_RX_STATUS_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ -#define _SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT (_SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ -#define SEMAILBOX_RX_STATUS_RXHDR (0x1UL << 22) /**< RXHDR */ -#define _SEMAILBOX_RX_STATUS_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ -#define _SEMAILBOX_RX_STATUS_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ -#define _SEMAILBOX_RX_STATUS_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_RXHDR_DEFAULT (_SEMAILBOX_RX_STATUS_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ -#define SEMAILBOX_RX_STATUS_RXERROR (0x1UL << 23) /**< RXERROR */ -#define _SEMAILBOX_RX_STATUS_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ -#define _SEMAILBOX_RX_STATUS_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ -#define _SEMAILBOX_RX_STATUS_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_RXERROR_DEFAULT (_SEMAILBOX_RX_STATUS_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define _SEMAILBOX_RX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define _SEMAILBOX_RX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_RX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXINT (0x1UL << 20) /**< RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXINT_DEFAULT (_SEMAILBOX_RX_STATUS_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT (_SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXHDR (0x1UL << 22) /**< RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXHDR_DEFAULT (_SEMAILBOX_RX_STATUS_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXERROR (0x1UL << 23) /**< RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXERROR_DEFAULT (_SEMAILBOX_RX_STATUS_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ /* Bit fields for SEMAILBOX TX_PROT */ -#define _SEMAILBOX_TX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_PROT */ -#define _SEMAILBOX_TX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ -#define _SEMAILBOX_TX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_TX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ -#define _SEMAILBOX_TX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_TX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ -#define _SEMAILBOX_TX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_TX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_TX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_TX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ -#define _SEMAILBOX_TX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ -#define _SEMAILBOX_TX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ -#define _SEMAILBOX_TX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_USER_DEFAULT (_SEMAILBOX_TX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_TX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_TX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_TX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_USER_DEFAULT (_SEMAILBOX_TX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ /* Bit fields for SEMAILBOX RX_PROT */ -#define _SEMAILBOX_RX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_PROT */ -#define _SEMAILBOX_RX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ -#define _SEMAILBOX_RX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_RX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ -#define _SEMAILBOX_RX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_RX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ -#define _SEMAILBOX_RX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_RX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_RX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_RX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ -#define _SEMAILBOX_RX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ -#define _SEMAILBOX_RX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ -#define _SEMAILBOX_RX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_USER_DEFAULT (_SEMAILBOX_RX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_RX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_RX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_RX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_USER_DEFAULT (_SEMAILBOX_RX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ /* Bit fields for SEMAILBOX TX_HEADER */ -#define _SEMAILBOX_TX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_HEADER */ -#define _SEMAILBOX_TX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_TX_HEADER */ -#define _SEMAILBOX_TX_HEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ -#define _SEMAILBOX_TX_HEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ -#define _SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_HEADER */ -#define SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT (_SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_HEADER*/ +#define _SEMAILBOX_TX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_HEADER */ +#define SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT (_SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_HEADER*/ /* Bit fields for SEMAILBOX RX_HEADER */ -#define _SEMAILBOX_RX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_HEADER */ -#define _SEMAILBOX_RX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_RX_HEADER */ -#define _SEMAILBOX_RX_HEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ -#define _SEMAILBOX_RX_HEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ -#define _SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_HEADER */ -#define SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT (_SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_HEADER*/ +#define _SEMAILBOX_RX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_HEADER */ +#define SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT (_SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_HEADER*/ /* Bit fields for SEMAILBOX CONFIGURATION */ -#define _SEMAILBOX_CONFIGURATION_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_CONFIGURATION */ -#define _SEMAILBOX_CONFIGURATION_MASK 0x00000003UL /**< Mask for SEMAILBOX_CONFIGURATION */ -#define SEMAILBOX_CONFIGURATION_TXINTEN (0x1UL << 0) /**< TXINTEN */ -#define _SEMAILBOX_CONFIGURATION_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ -#define _SEMAILBOX_CONFIGURATION_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ -#define _SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ -#define SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ -#define SEMAILBOX_CONFIGURATION_RXINTEN (0x1UL << 1) /**< RXINTEN */ -#define _SEMAILBOX_CONFIGURATION_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ -#define _SEMAILBOX_CONFIGURATION_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ -#define _SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ -#define SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ +#define _SEMAILBOX_CONFIGURATION_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_CONFIGURATION */ +#define _SEMAILBOX_CONFIGURATION_MASK 0x00000003UL /**< Mask for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_TXINTEN (0x1UL << 0) /**< TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ +#define SEMAILBOX_CONFIGURATION_RXINTEN (0x1UL << 1) /**< RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ /** @} End of group EFR32SG23_SEMAILBOX_HOST_BitFields */ /** @} End of group EFR32SG23_SEMAILBOX_HOST */ @@ -214,17 +213,16 @@ typedef struct *****************************************************************************/ /** SEMAILBOX_APBSE Register Declaration. */ -typedef struct -{ - __IOM uint32_t SE_ESECURE_MAILBOX_FIFO;/**< ESECURE_MAILBOX_FIFO */ - uint32_t RESERVED0[15U]; /**< Reserved for future use */ - __IM uint32_t SE_ESECURE_MAILBOX_TXSTAT;/**< ESECURE_MAILBOX_TXSTAT */ - __IM uint32_t SE_ESECURE_MAILBOX_RXSTAT;/**< ESECURE_MAILBOX_RXSTAT */ - __IM uint32_t SE_ESECURE_MAILBOX_TXPROTECT;/**< ESECURE_MAILBOX_TXPROTECT */ - __IM uint32_t SE_ESECURE_MAILBOX_RXPROTECT;/**< ESECURE_MAILBOX_RXPROTECT */ - __IOM uint32_t SE_ESECURE_MAILBOX_TXHEADER;/**< ESECURE_MAILBOX_TXHEADER */ - __IM uint32_t SE_ESECURE_MAILBOX_RXHEADER;/**< ESECURE_MAILBOX_RXHEADER */ - __IOM uint32_t SE_ESECURE_MAILBOX_CONFIG;/**< ESECURE_MAILBOX_CONFIG */ +typedef struct { + __IOM uint32_t SE_ESECURE_MAILBOX_FIFO; /**< ESECURE_MAILBOX_FIFO */ + uint32_t RESERVED0[15U]; /**< Reserved for future use */ + __IM uint32_t SE_ESECURE_MAILBOX_TXSTAT; /**< ESECURE_MAILBOX_TXSTAT */ + __IM uint32_t SE_ESECURE_MAILBOX_RXSTAT; /**< ESECURE_MAILBOX_RXSTAT */ + __IM uint32_t SE_ESECURE_MAILBOX_TXPROTECT; /**< ESECURE_MAILBOX_TXPROTECT */ + __IM uint32_t SE_ESECURE_MAILBOX_RXPROTECT; /**< ESECURE_MAILBOX_RXPROTECT */ + __IOM uint32_t SE_ESECURE_MAILBOX_TXHEADER; /**< ESECURE_MAILBOX_TXHEADER */ + __IM uint32_t SE_ESECURE_MAILBOX_RXHEADER; /**< ESECURE_MAILBOX_RXHEADER */ + __IOM uint32_t SE_ESECURE_MAILBOX_CONFIG; /**< ESECURE_MAILBOX_CONFIG */ } SEMAILBOX_APBSE_TypeDef; /** @} End of group EFR32SG23_SEMAILBOX_APBSE */ @@ -236,147 +234,147 @@ typedef struct *****************************************************************************/ /* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_FIFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ /* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXSTAT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT (0x1UL << 20) /**< TXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL (0x1UL << 21) /**< TXFULL */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR (0x1UL << 23) /**< TXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT (0x1UL << 20) /**< TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL (0x1UL << 21) /**< TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR (0x1UL << 23) /**< TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ /* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXSTAT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT (0x1UL << 20) /**< RXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR (0x1UL << 22) /**< RXHDR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR (0x1UL << 23) /**< RXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT (0x1UL << 20) /**< RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR (0x1UL << 22) /**< RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR (0x1UL << 23) /**< RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ /* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXPROTECT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ /* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXPROTECT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ /* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ /* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ /* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_CONFIG */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_MASK 0x00000003UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN (0x1UL << 0) /**< TXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN (0x1UL << 1) /**< RXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_MASK 0x00000003UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN (0x1UL << 0) /**< TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN (0x1UL << 1) /**< RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ /** @} End of group EFR32SG23_SEMAILBOX_APBSE_BitFields */ /** @} End of group EFR32SG23_SEMAILBOX_APBSE */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_smu.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_smu.h index 54361c08aa..ee1192c0cb 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_smu.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_smu.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_SMU_H #define EFR32SG23_SMU_H - #define SMU_HAS_SET_CLEAR /**************************************************************************//** @@ -43,135 +42,134 @@ *****************************************************************************/ /** SMU Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP Version */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t LOCK; /**< Lock Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - __IOM uint32_t M33CTRL; /**< M33 Control Settings */ - uint32_t RESERVED1[7U]; /**< Reserved for future use */ - __IOM uint32_t PPUPATD0; /**< Privileged Access */ - __IOM uint32_t PPUPATD1; /**< Privileged Access */ - uint32_t RESERVED2[6U]; /**< Reserved for future use */ - __IOM uint32_t PPUSATD0; /**< Secure Access */ - __IOM uint32_t PPUSATD1; /**< Secure Access */ - uint32_t RESERVED3[54U]; /**< Reserved for future use */ - __IM uint32_t PPUFS; /**< Fault Status */ - uint32_t RESERVED4[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUPATD0; /**< Privileged Attribute */ - uint32_t RESERVED5[7U]; /**< Reserved for future use */ - __IOM uint32_t BMPUSATD0; /**< Secure Attribute */ - uint32_t RESERVED6[55U]; /**< Reserved for future use */ - __IM uint32_t BMPUFS; /**< Fault Status */ - __IM uint32_t BMPUFSADDR; /**< Fault Status Address */ - uint32_t RESERVED7[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAURTYPES0; /**< Region Types 0 */ - __IOM uint32_t ESAURTYPES1; /**< Region Types 1 */ - uint32_t RESERVED8[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB01; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB12; /**< Movable Region Boundary */ - uint32_t RESERVED9[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB45; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB56; /**< Movable Region Boundary */ - uint32_t RESERVED10[862U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t LOCK_SET; /**< Lock Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED11[3U]; /**< Reserved for future use */ - __IOM uint32_t M33CTRL_SET; /**< M33 Control Settings */ - uint32_t RESERVED12[7U]; /**< Reserved for future use */ - __IOM uint32_t PPUPATD0_SET; /**< Privileged Access */ - __IOM uint32_t PPUPATD1_SET; /**< Privileged Access */ - uint32_t RESERVED13[6U]; /**< Reserved for future use */ - __IOM uint32_t PPUSATD0_SET; /**< Secure Access */ - __IOM uint32_t PPUSATD1_SET; /**< Secure Access */ - uint32_t RESERVED14[54U]; /**< Reserved for future use */ - __IM uint32_t PPUFS_SET; /**< Fault Status */ - uint32_t RESERVED15[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUPATD0_SET; /**< Privileged Attribute */ - uint32_t RESERVED16[7U]; /**< Reserved for future use */ - __IOM uint32_t BMPUSATD0_SET; /**< Secure Attribute */ - uint32_t RESERVED17[55U]; /**< Reserved for future use */ - __IM uint32_t BMPUFS_SET; /**< Fault Status */ - __IM uint32_t BMPUFSADDR_SET; /**< Fault Status Address */ - uint32_t RESERVED18[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAURTYPES0_SET; /**< Region Types 0 */ - __IOM uint32_t ESAURTYPES1_SET; /**< Region Types 1 */ - uint32_t RESERVED19[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB01_SET; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB12_SET; /**< Movable Region Boundary */ - uint32_t RESERVED20[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB45_SET; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB56_SET; /**< Movable Region Boundary */ - uint32_t RESERVED21[862U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t LOCK_CLR; /**< Lock Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED22[3U]; /**< Reserved for future use */ - __IOM uint32_t M33CTRL_CLR; /**< M33 Control Settings */ - uint32_t RESERVED23[7U]; /**< Reserved for future use */ - __IOM uint32_t PPUPATD0_CLR; /**< Privileged Access */ - __IOM uint32_t PPUPATD1_CLR; /**< Privileged Access */ - uint32_t RESERVED24[6U]; /**< Reserved for future use */ - __IOM uint32_t PPUSATD0_CLR; /**< Secure Access */ - __IOM uint32_t PPUSATD1_CLR; /**< Secure Access */ - uint32_t RESERVED25[54U]; /**< Reserved for future use */ - __IM uint32_t PPUFS_CLR; /**< Fault Status */ - uint32_t RESERVED26[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUPATD0_CLR; /**< Privileged Attribute */ - uint32_t RESERVED27[7U]; /**< Reserved for future use */ - __IOM uint32_t BMPUSATD0_CLR; /**< Secure Attribute */ - uint32_t RESERVED28[55U]; /**< Reserved for future use */ - __IM uint32_t BMPUFS_CLR; /**< Fault Status */ - __IM uint32_t BMPUFSADDR_CLR; /**< Fault Status Address */ - uint32_t RESERVED29[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAURTYPES0_CLR; /**< Region Types 0 */ - __IOM uint32_t ESAURTYPES1_CLR; /**< Region Types 1 */ - uint32_t RESERVED30[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB01_CLR; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB12_CLR; /**< Movable Region Boundary */ - uint32_t RESERVED31[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB45_CLR; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB56_CLR; /**< Movable Region Boundary */ - uint32_t RESERVED32[862U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t LOCK_TGL; /**< Lock Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED33[3U]; /**< Reserved for future use */ - __IOM uint32_t M33CTRL_TGL; /**< M33 Control Settings */ - uint32_t RESERVED34[7U]; /**< Reserved for future use */ - __IOM uint32_t PPUPATD0_TGL; /**< Privileged Access */ - __IOM uint32_t PPUPATD1_TGL; /**< Privileged Access */ - uint32_t RESERVED35[6U]; /**< Reserved for future use */ - __IOM uint32_t PPUSATD0_TGL; /**< Secure Access */ - __IOM uint32_t PPUSATD1_TGL; /**< Secure Access */ - uint32_t RESERVED36[54U]; /**< Reserved for future use */ - __IM uint32_t PPUFS_TGL; /**< Fault Status */ - uint32_t RESERVED37[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUPATD0_TGL; /**< Privileged Attribute */ - uint32_t RESERVED38[7U]; /**< Reserved for future use */ - __IOM uint32_t BMPUSATD0_TGL; /**< Secure Attribute */ - uint32_t RESERVED39[55U]; /**< Reserved for future use */ - __IM uint32_t BMPUFS_TGL; /**< Fault Status */ - __IM uint32_t BMPUFSADDR_TGL; /**< Fault Status Address */ - uint32_t RESERVED40[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAURTYPES0_TGL; /**< Region Types 0 */ - __IOM uint32_t ESAURTYPES1_TGL; /**< Region Types 1 */ - uint32_t RESERVED41[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB01_TGL; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB12_TGL; /**< Movable Region Boundary */ - uint32_t RESERVED42[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB45_TGL; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB56_TGL; /**< Movable Region Boundary */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL; /**< M33 Control Settings */ + uint32_t RESERVED1[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0; /**< Privileged Access */ + __IOM uint32_t PPUPATD1; /**< Privileged Access */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0; /**< Secure Access */ + __IOM uint32_t PPUSATD1; /**< Secure Access */ + uint32_t RESERVED3[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS; /**< Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0; /**< Privileged Attribute */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0; /**< Secure Attribute */ + uint32_t RESERVED6[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS; /**< Fault Status */ + __IM uint32_t BMPUFSADDR; /**< Fault Status Address */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1; /**< Region Types 1 */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12; /**< Movable Region Boundary */ + uint32_t RESERVED9[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56; /**< Movable Region Boundary */ + uint32_t RESERVED10[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_SET; /**< M33 Control Settings */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_SET; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_SET; /**< Privileged Access */ + uint32_t RESERVED13[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_SET; /**< Secure Access */ + __IOM uint32_t PPUSATD1_SET; /**< Secure Access */ + uint32_t RESERVED14[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_SET; /**< Fault Status */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_SET; /**< Privileged Attribute */ + uint32_t RESERVED16[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_SET; /**< Secure Attribute */ + uint32_t RESERVED17[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_SET; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_SET; /**< Fault Status Address */ + uint32_t RESERVED18[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_SET; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_SET; /**< Region Types 1 */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_SET; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_SET; /**< Movable Region Boundary */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_SET; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_SET; /**< Movable Region Boundary */ + uint32_t RESERVED21[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_CLR; /**< M33 Control Settings */ + uint32_t RESERVED23[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_CLR; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_CLR; /**< Privileged Access */ + uint32_t RESERVED24[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_CLR; /**< Secure Access */ + __IOM uint32_t PPUSATD1_CLR; /**< Secure Access */ + uint32_t RESERVED25[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_CLR; /**< Fault Status */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_CLR; /**< Privileged Attribute */ + uint32_t RESERVED27[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_CLR; /**< Secure Attribute */ + uint32_t RESERVED28[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_CLR; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_CLR; /**< Fault Status Address */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_CLR; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_CLR; /**< Region Types 1 */ + uint32_t RESERVED30[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_CLR; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_CLR; /**< Movable Region Boundary */ + uint32_t RESERVED31[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_CLR; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_CLR; /**< Movable Region Boundary */ + uint32_t RESERVED32[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_TGL; /**< M33 Control Settings */ + uint32_t RESERVED34[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_TGL; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_TGL; /**< Privileged Access */ + uint32_t RESERVED35[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_TGL; /**< Secure Access */ + __IOM uint32_t PPUSATD1_TGL; /**< Secure Access */ + uint32_t RESERVED36[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_TGL; /**< Fault Status */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_TGL; /**< Privileged Attribute */ + uint32_t RESERVED38[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_TGL; /**< Secure Attribute */ + uint32_t RESERVED39[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_TGL; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_TGL; /**< Fault Status Address */ + uint32_t RESERVED40[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_TGL; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_TGL; /**< Region Types 1 */ + uint32_t RESERVED41[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_TGL; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_TGL; /**< Movable Region Boundary */ + uint32_t RESERVED42[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_TGL; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_TGL; /**< Movable Region Boundary */ } SMU_TypeDef; /** @} End of group EFR32SG23_SMU */ @@ -183,835 +181,835 @@ typedef struct *****************************************************************************/ /* Bit fields for SMU IPVERSION */ -#define _SMU_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for SMU_IPVERSION */ -#define _SMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SMU_IPVERSION */ -#define _SMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SMU_IPVERSION */ -#define _SMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_IPVERSION */ -#define _SMU_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for SMU_IPVERSION */ -#define SMU_IPVERSION_IPVERSION_DEFAULT (_SMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IPVERSION */ +#define _SMU_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for SMU_IPVERSION */ +#define _SMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for SMU_IPVERSION */ +#define SMU_IPVERSION_IPVERSION_DEFAULT (_SMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IPVERSION */ /* Bit fields for SMU STATUS */ -#define _SMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_STATUS */ -#define _SMU_STATUS_MASK 0x00000003UL /**< Mask for SMU_STATUS */ -#define SMU_STATUS_SMULOCK (0x1UL << 0) /**< SMU Lock */ -#define _SMU_STATUS_SMULOCK_SHIFT 0 /**< Shift value for SMU_SMULOCK */ -#define _SMU_STATUS_SMULOCK_MASK 0x1UL /**< Bit mask for SMU_SMULOCK */ -#define _SMU_STATUS_SMULOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ -#define _SMU_STATUS_SMULOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_STATUS */ -#define _SMU_STATUS_SMULOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_STATUS */ -#define SMU_STATUS_SMULOCK_DEFAULT (_SMU_STATUS_SMULOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_STATUS */ -#define SMU_STATUS_SMULOCK_UNLOCKED (_SMU_STATUS_SMULOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_STATUS */ -#define SMU_STATUS_SMULOCK_LOCKED (_SMU_STATUS_SMULOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_STATUS */ -#define SMU_STATUS_SMUPRGERR (0x1UL << 1) /**< SMU Programming Error */ -#define _SMU_STATUS_SMUPRGERR_SHIFT 1 /**< Shift value for SMU_SMUPRGERR */ -#define _SMU_STATUS_SMUPRGERR_MASK 0x2UL /**< Bit mask for SMU_SMUPRGERR */ -#define _SMU_STATUS_SMUPRGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ -#define SMU_STATUS_SMUPRGERR_DEFAULT (_SMU_STATUS_SMUPRGERR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_STATUS */ +#define _SMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_STATUS */ +#define _SMU_STATUS_MASK 0x00000003UL /**< Mask for SMU_STATUS */ +#define SMU_STATUS_SMULOCK (0x1UL << 0) /**< SMU Lock */ +#define _SMU_STATUS_SMULOCK_SHIFT 0 /**< Shift value for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_MASK 0x1UL /**< Bit mask for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_DEFAULT (_SMU_STATUS_SMULOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_UNLOCKED (_SMU_STATUS_SMULOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_LOCKED (_SMU_STATUS_SMULOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR (0x1UL << 1) /**< SMU Programming Error */ +#define _SMU_STATUS_SMUPRGERR_SHIFT 1 /**< Shift value for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_MASK 0x2UL /**< Bit mask for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR_DEFAULT (_SMU_STATUS_SMUPRGERR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_STATUS */ /* Bit fields for SMU LOCK */ -#define _SMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_LOCK */ -#define _SMU_LOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_LOCK */ -#define _SMU_LOCK_SMULOCKKEY_SHIFT 0 /**< Shift value for SMU_SMULOCKKEY */ -#define _SMU_LOCK_SMULOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMULOCKKEY */ -#define _SMU_LOCK_SMULOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_LOCK */ -#define _SMU_LOCK_SMULOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_LOCK */ -#define SMU_LOCK_SMULOCKKEY_DEFAULT (_SMU_LOCK_SMULOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_LOCK */ -#define SMU_LOCK_SMULOCKKEY_UNLOCK (_SMU_LOCK_SMULOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_LOCK */ +#define _SMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_LOCK */ +#define _SMU_LOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_SHIFT 0 /**< Shift value for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_DEFAULT (_SMU_LOCK_SMULOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_UNLOCK (_SMU_LOCK_SMULOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_LOCK */ /* Bit fields for SMU IF */ -#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ -#define _SMU_IF_MASK 0x00030005UL /**< Mask for SMU_IF */ -#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ -#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ -#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ -#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Flag */ -#define _SMU_IF_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ -#define _SMU_IF_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ -#define _SMU_IF_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUINST_DEFAULT (_SMU_IF_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Flag */ -#define _SMU_IF_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ -#define _SMU_IF_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ -#define _SMU_IF_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUSEC_DEFAULT (_SMU_IF_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IF */ -#define SMU_IF_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Flag */ -#define _SMU_IF_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ -#define _SMU_IF_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ -#define _SMU_IF_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ -#define SMU_IF_BMPUSEC_DEFAULT (_SMU_IF_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00030005UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Flag */ +#define _SMU_IF_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IF_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IF_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST_DEFAULT (_SMU_IF_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Flag */ +#define _SMU_IF_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC_DEFAULT (_SMU_IF_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Flag */ +#define _SMU_IF_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC_DEFAULT (_SMU_IF_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IF */ /* Bit fields for SMU IEN */ -#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ -#define _SMU_IEN_MASK 0x00030005UL /**< Mask for SMU_IEN */ -#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Enable */ -#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ -#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ -#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Enable */ -#define _SMU_IEN_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ -#define _SMU_IEN_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ -#define _SMU_IEN_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUINST_DEFAULT (_SMU_IEN_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Enable */ -#define _SMU_IEN_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ -#define _SMU_IEN_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ -#define _SMU_IEN_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUSEC_DEFAULT (_SMU_IEN_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IEN */ -#define SMU_IEN_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Enable */ -#define _SMU_IEN_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ -#define _SMU_IEN_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ -#define _SMU_IEN_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ -#define SMU_IEN_BMPUSEC_DEFAULT (_SMU_IEN_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00030005UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Enable */ +#define _SMU_IEN_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST_DEFAULT (_SMU_IEN_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Enable */ +#define _SMU_IEN_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC_DEFAULT (_SMU_IEN_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Enable */ +#define _SMU_IEN_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC_DEFAULT (_SMU_IEN_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IEN */ /* Bit fields for SMU M33CTRL */ -#define _SMU_M33CTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_M33CTRL */ -#define _SMU_M33CTRL_MASK 0x0000001FUL /**< Mask for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSVTAIRCR (0x1UL << 0) /**< New BitField */ -#define _SMU_M33CTRL_LOCKSVTAIRCR_SHIFT 0 /**< Shift value for SMU_LOCKSVTAIRCR */ -#define _SMU_M33CTRL_LOCKSVTAIRCR_MASK 0x1UL /**< Bit mask for SMU_LOCKSVTAIRCR */ -#define _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT (_SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKNSVTOR (0x1UL << 1) /**< New BitField */ -#define _SMU_M33CTRL_LOCKNSVTOR_SHIFT 1 /**< Shift value for SMU_LOCKNSVTOR */ -#define _SMU_M33CTRL_LOCKNSVTOR_MASK 0x2UL /**< Bit mask for SMU_LOCKNSVTOR */ -#define _SMU_M33CTRL_LOCKNSVTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKNSVTOR_DEFAULT (_SMU_M33CTRL_LOCKNSVTOR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSMPU (0x1UL << 2) /**< New BitField */ -#define _SMU_M33CTRL_LOCKSMPU_SHIFT 2 /**< Shift value for SMU_LOCKSMPU */ -#define _SMU_M33CTRL_LOCKSMPU_MASK 0x4UL /**< Bit mask for SMU_LOCKSMPU */ -#define _SMU_M33CTRL_LOCKSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSMPU_DEFAULT (_SMU_M33CTRL_LOCKSMPU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKNSMPU (0x1UL << 3) /**< New BitField */ -#define _SMU_M33CTRL_LOCKNSMPU_SHIFT 3 /**< Shift value for SMU_LOCKNSMPU */ -#define _SMU_M33CTRL_LOCKNSMPU_MASK 0x8UL /**< Bit mask for SMU_LOCKNSMPU */ -#define _SMU_M33CTRL_LOCKNSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKNSMPU_DEFAULT (_SMU_M33CTRL_LOCKNSMPU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSAU (0x1UL << 4) /**< New BitField */ -#define _SMU_M33CTRL_LOCKSAU_SHIFT 4 /**< Shift value for SMU_LOCKSAU */ -#define _SMU_M33CTRL_LOCKSAU_MASK 0x10UL /**< Bit mask for SMU_LOCKSAU */ -#define _SMU_M33CTRL_LOCKSAU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSAU_DEFAULT (_SMU_M33CTRL_LOCKSAU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define _SMU_M33CTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_M33CTRL */ +#define _SMU_M33CTRL_MASK 0x0000001FUL /**< Mask for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR (0x1UL << 0) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_SHIFT 0 /**< Shift value for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_MASK 0x1UL /**< Bit mask for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT (_SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR (0x1UL << 1) /**< New BitField */ +#define _SMU_M33CTRL_LOCKNSVTOR_SHIFT 1 /**< Shift value for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_MASK 0x2UL /**< Bit mask for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR_DEFAULT (_SMU_M33CTRL_LOCKNSVTOR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU (0x1UL << 2) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSMPU_SHIFT 2 /**< Shift value for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_MASK 0x4UL /**< Bit mask for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU_DEFAULT (_SMU_M33CTRL_LOCKSMPU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU (0x1UL << 3) /**< New BitField */ +#define _SMU_M33CTRL_LOCKNSMPU_SHIFT 3 /**< Shift value for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_MASK 0x8UL /**< Bit mask for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU_DEFAULT (_SMU_M33CTRL_LOCKNSMPU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU (0x1UL << 4) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSAU_SHIFT 4 /**< Shift value for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_MASK 0x10UL /**< Bit mask for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU_DEFAULT (_SMU_M33CTRL_LOCKSAU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_M33CTRL */ /* Bit fields for SMU PPUPATD0 */ -#define _SMU_PPUPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUPATD0 */ -#define _SMU_PPUPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ -#define _SMU_PPUPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ -#define _SMU_PPUPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ -#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ -#define _SMU_PPUPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ -#define _SMU_PPUPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ -#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */ -#define _SMU_PPUPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ -#define _SMU_PPUPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ -#define _SMU_PPUPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_HFRCO0_DEFAULT (_SMU_PPUPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */ -#define _SMU_PPUPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ -#define _SMU_PPUPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ -#define _SMU_PPUPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_FSRCO_DEFAULT (_SMU_PPUPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */ -#define _SMU_PPUPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ -#define _SMU_PPUPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ -#define _SMU_PPUPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_DPLL0_DEFAULT (_SMU_PPUPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */ -#define _SMU_PPUPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ -#define _SMU_PPUPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ -#define _SMU_PPUPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LFXO_DEFAULT (_SMU_PPUPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */ -#define _SMU_PPUPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ -#define _SMU_PPUPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ -#define _SMU_PPUPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LFRCO_DEFAULT (_SMU_PPUPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */ -#define _SMU_PPUPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ -#define _SMU_PPUPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ -#define _SMU_PPUPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_ULFRCO_DEFAULT (_SMU_PPUPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */ -#define _SMU_PPUPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ -#define _SMU_PPUPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ -#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */ -#define _SMU_PPUPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ -#define _SMU_PPUPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ -#define _SMU_PPUPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_ICACHE0_DEFAULT (_SMU_PPUPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */ -#define _SMU_PPUPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ -#define _SMU_PPUPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ -#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */ -#define _SMU_PPUPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ -#define _SMU_PPUPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ -#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */ -#define _SMU_PPUPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ -#define _SMU_PPUPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ -#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */ -#define _SMU_PPUPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ -#define _SMU_PPUPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ -#define _SMU_PPUPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LDMAXBAR_DEFAULT (_SMU_PPUPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */ -#define _SMU_PPUPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ -#define _SMU_PPUPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ -#define _SMU_PPUPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER0_DEFAULT (_SMU_PPUPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */ -#define _SMU_PPUPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ -#define _SMU_PPUPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ -#define _SMU_PPUPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER1_DEFAULT (_SMU_PPUPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */ -#define _SMU_PPUPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ -#define _SMU_PPUPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ -#define _SMU_PPUPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER2_DEFAULT (_SMU_PPUPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */ -#define _SMU_PPUPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ -#define _SMU_PPUPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ -#define _SMU_PPUPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER3_DEFAULT (_SMU_PPUPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */ -#define _SMU_PPUPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ -#define _SMU_PPUPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ -#define _SMU_PPUPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER4_DEFAULT (_SMU_PPUPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */ -#define _SMU_PPUPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ -#define _SMU_PPUPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ -#define _SMU_PPUPATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_USART0_DEFAULT (_SMU_PPUPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */ -#define _SMU_PPUPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ -#define _SMU_PPUPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ -#define _SMU_PPUPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_BURTC_DEFAULT (_SMU_PPUPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */ -#define _SMU_PPUPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ -#define _SMU_PPUPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ -#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Privileged Access */ -#define _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ -#define _SMU_PPUPATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ -#define _SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */ -#define _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ -#define _SMU_PPUPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ -#define _SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */ -#define _SMU_PPUPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ -#define _SMU_PPUPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ -#define _SMU_PPUPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSCFG_DEFAULT (_SMU_PPUPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */ -#define _SMU_PPUPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ -#define _SMU_PPUPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ -#define _SMU_PPUPATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_BURAM_DEFAULT (_SMU_PPUPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */ -#define _SMU_PPUPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ -#define _SMU_PPUPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ -#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */ -#define _SMU_PPUPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ -#define _SMU_PPUPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ -#define _SMU_PPUPATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_DCDC_DEFAULT (_SMU_PPUPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */ -#define _SMU_PPUPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ -#define _SMU_PPUPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ -#define _SMU_PPUPATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */ -#define _SMU_PPUPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ -#define _SMU_PPUPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ -#define _SMU_PPUPATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EUSART1_DEFAULT (_SMU_PPUPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EUSART2 (0x1UL << 31) /**< EUSART2 Privileged Access */ -#define _SMU_PPUPATD0_EUSART2_SHIFT 31 /**< Shift value for SMU_EUSART2 */ -#define _SMU_PPUPATD0_EUSART2_MASK 0x80000000UL /**< Bit mask for SMU_EUSART2 */ -#define _SMU_PPUPATD0_EUSART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EUSART2_DEFAULT (_SMU_PPUPATD0_EUSART2_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0_DEFAULT (_SMU_PPUPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */ +#define _SMU_PPUPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO_DEFAULT (_SMU_PPUPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */ +#define _SMU_PPUPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0_DEFAULT (_SMU_PPUPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */ +#define _SMU_PPUPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO_DEFAULT (_SMU_PPUPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */ +#define _SMU_PPUPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO_DEFAULT (_SMU_PPUPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */ +#define _SMU_PPUPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO_DEFAULT (_SMU_PPUPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */ +#define _SMU_PPUPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0_DEFAULT (_SMU_PPUPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */ +#define _SMU_PPUPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */ +#define _SMU_PPUPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */ +#define _SMU_PPUPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR_DEFAULT (_SMU_PPUPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */ +#define _SMU_PPUPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0_DEFAULT (_SMU_PPUPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */ +#define _SMU_PPUPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1_DEFAULT (_SMU_PPUPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */ +#define _SMU_PPUPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2_DEFAULT (_SMU_PPUPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */ +#define _SMU_PPUPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3_DEFAULT (_SMU_PPUPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */ +#define _SMU_PPUPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4_DEFAULT (_SMU_PPUPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */ +#define _SMU_PPUPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART0_DEFAULT (_SMU_PPUPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */ +#define _SMU_PPUPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC_DEFAULT (_SMU_PPUPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */ +#define _SMU_PPUPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Privileged Access */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */ +#define _SMU_PPUPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG_DEFAULT (_SMU_PPUPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */ +#define _SMU_PPUPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUPATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURAM_DEFAULT (_SMU_PPUPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */ +#define _SMU_PPUPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUPATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DCDC_DEFAULT (_SMU_PPUPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */ +#define _SMU_PPUPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUPATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */ +#define _SMU_PPUPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUPATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EUSART1_DEFAULT (_SMU_PPUPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EUSART2 (0x1UL << 31) /**< EUSART2 Privileged Access */ +#define _SMU_PPUPATD0_EUSART2_SHIFT 31 /**< Shift value for SMU_EUSART2 */ +#define _SMU_PPUPATD0_EUSART2_MASK 0x80000000UL /**< Bit mask for SMU_EUSART2 */ +#define _SMU_PPUPATD0_EUSART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EUSART2_DEFAULT (_SMU_PPUPATD0_EUSART2_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ /* Bit fields for SMU PPUPATD1 */ -#define _SMU_PPUPATD1_RESETVALUE 0x01FFFFFFUL /**< Default value for SMU_PPUPATD1 */ -#define _SMU_PPUPATD1_MASK 0x01FFFFFFUL /**< Mask for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SYSRTC (0x1UL << 0) /**< SYSRTC Privileged Access */ -#define _SMU_PPUPATD1_SYSRTC_SHIFT 0 /**< Shift value for SMU_SYSRTC */ -#define _SMU_PPUPATD1_SYSRTC_MASK 0x1UL /**< Bit mask for SMU_SYSRTC */ -#define _SMU_PPUPATD1_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SYSRTC_DEFAULT (_SMU_PPUPATD1_SYSRTC_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LCD (0x1UL << 1) /**< LCD Privileged Access */ -#define _SMU_PPUPATD1_LCD_SHIFT 1 /**< Shift value for SMU_LCD */ -#define _SMU_PPUPATD1_LCD_MASK 0x2UL /**< Bit mask for SMU_LCD */ -#define _SMU_PPUPATD1_LCD_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LCD_DEFAULT (_SMU_PPUPATD1_LCD_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_KEYSCAN (0x1UL << 2) /**< KEYSCAN Privileged Access */ -#define _SMU_PPUPATD1_KEYSCAN_SHIFT 2 /**< Shift value for SMU_KEYSCAN */ -#define _SMU_PPUPATD1_KEYSCAN_MASK 0x4UL /**< Bit mask for SMU_KEYSCAN */ -#define _SMU_PPUPATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_KEYSCAN_DEFAULT (_SMU_PPUPATD1_KEYSCAN_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_DMEM (0x1UL << 3) /**< DMEM Privileged Access */ -#define _SMU_PPUPATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ -#define _SMU_PPUPATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ -#define _SMU_PPUPATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_DMEM_DEFAULT (_SMU_PPUPATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LCDRF (0x1UL << 4) /**< LCDRF Privileged Access */ -#define _SMU_PPUPATD1_LCDRF_SHIFT 4 /**< Shift value for SMU_LCDRF */ -#define _SMU_PPUPATD1_LCDRF_MASK 0x10UL /**< Bit mask for SMU_LCDRF */ -#define _SMU_PPUPATD1_LCDRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LCDRF_DEFAULT (_SMU_PPUPATD1_LCDRF_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_PFMXPPRF (0x1UL << 5) /**< PFMXPPRF Privileged Access */ -#define _SMU_PPUPATD1_PFMXPPRF_SHIFT 5 /**< Shift value for SMU_PFMXPPRF */ -#define _SMU_PPUPATD1_PFMXPPRF_MASK 0x20UL /**< Bit mask for SMU_PFMXPPRF */ -#define _SMU_PPUPATD1_PFMXPPRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_PFMXPPRF_DEFAULT (_SMU_PPUPATD1_PFMXPPRF_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_RADIOAES (0x1UL << 6) /**< RADIOAES Privileged Access */ -#define _SMU_PPUPATD1_RADIOAES_SHIFT 6 /**< Shift value for SMU_RADIOAES */ -#define _SMU_PPUPATD1_RADIOAES_MASK 0x40UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_PPUPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_RADIOAES_DEFAULT (_SMU_PPUPATD1_RADIOAES_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SMU (0x1UL << 7) /**< SMU Privileged Access */ -#define _SMU_PPUPATD1_SMU_SHIFT 7 /**< Shift value for SMU_SMU */ -#define _SMU_PPUPATD1_SMU_MASK 0x80UL /**< Bit mask for SMU_SMU */ -#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SMUCFGNS (0x1UL << 8) /**< SMUCFGNS Privileged Access */ -#define _SMU_PPUPATD1_SMUCFGNS_SHIFT 8 /**< Shift value for SMU_SMUCFGNS */ -#define _SMU_PPUPATD1_SMUCFGNS_MASK 0x100UL /**< Bit mask for SMU_SMUCFGNS */ -#define _SMU_PPUPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SMUCFGNS_DEFAULT (_SMU_PPUPATD1_SMUCFGNS_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LETIMER0 (0x1UL << 9) /**< LETIMER0 Privileged Access */ -#define _SMU_PPUPATD1_LETIMER0_SHIFT 9 /**< Shift value for SMU_LETIMER0 */ -#define _SMU_PPUPATD1_LETIMER0_MASK 0x200UL /**< Bit mask for SMU_LETIMER0 */ -#define _SMU_PPUPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LETIMER0_DEFAULT (_SMU_PPUPATD1_LETIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_IADC0 (0x1UL << 10) /**< IADC0 Privileged Access */ -#define _SMU_PPUPATD1_IADC0_SHIFT 10 /**< Shift value for SMU_IADC0 */ -#define _SMU_PPUPATD1_IADC0_MASK 0x400UL /**< Bit mask for SMU_IADC0 */ -#define _SMU_PPUPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_IADC0_DEFAULT (_SMU_PPUPATD1_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_ACMP0 (0x1UL << 11) /**< ACMP0 Privileged Access */ -#define _SMU_PPUPATD1_ACMP0_SHIFT 11 /**< Shift value for SMU_ACMP0 */ -#define _SMU_PPUPATD1_ACMP0_MASK 0x800UL /**< Bit mask for SMU_ACMP0 */ -#define _SMU_PPUPATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_ACMP0_DEFAULT (_SMU_PPUPATD1_ACMP0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_ACMP1 (0x1UL << 12) /**< ACMP1 Privileged Access */ -#define _SMU_PPUPATD1_ACMP1_SHIFT 12 /**< Shift value for SMU_ACMP1 */ -#define _SMU_PPUPATD1_ACMP1_MASK 0x1000UL /**< Bit mask for SMU_ACMP1 */ -#define _SMU_PPUPATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_ACMP1_DEFAULT (_SMU_PPUPATD1_ACMP1_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_AMUXCP0 (0x1UL << 13) /**< AMUXCP0 Privileged Access */ -#define _SMU_PPUPATD1_AMUXCP0_SHIFT 13 /**< Shift value for SMU_AMUXCP0 */ -#define _SMU_PPUPATD1_AMUXCP0_MASK 0x2000UL /**< Bit mask for SMU_AMUXCP0 */ -#define _SMU_PPUPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_AMUXCP0_DEFAULT (_SMU_PPUPATD1_AMUXCP0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_VDAC0 (0x1UL << 14) /**< VDAC0 Privileged Access */ -#define _SMU_PPUPATD1_VDAC0_SHIFT 14 /**< Shift value for SMU_VDAC0 */ -#define _SMU_PPUPATD1_VDAC0_MASK 0x4000UL /**< Bit mask for SMU_VDAC0 */ -#define _SMU_PPUPATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_VDAC0_DEFAULT (_SMU_PPUPATD1_VDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_PCNT (0x1UL << 15) /**< PCNT Privileged Access */ -#define _SMU_PPUPATD1_PCNT_SHIFT 15 /**< Shift value for SMU_PCNT */ -#define _SMU_PPUPATD1_PCNT_MASK 0x8000UL /**< Bit mask for SMU_PCNT */ -#define _SMU_PPUPATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_PCNT_DEFAULT (_SMU_PPUPATD1_PCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LESENSE (0x1UL << 16) /**< LESENSE Privileged Access */ -#define _SMU_PPUPATD1_LESENSE_SHIFT 16 /**< Shift value for SMU_LESENSE */ -#define _SMU_PPUPATD1_LESENSE_MASK 0x10000UL /**< Bit mask for SMU_LESENSE */ -#define _SMU_PPUPATD1_LESENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LESENSE_DEFAULT (_SMU_PPUPATD1_LESENSE_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_HFRCO1 (0x1UL << 17) /**< HFRCO1 Privileged Access */ -#define _SMU_PPUPATD1_HFRCO1_SHIFT 17 /**< Shift value for SMU_HFRCO1 */ -#define _SMU_PPUPATD1_HFRCO1_MASK 0x20000UL /**< Bit mask for SMU_HFRCO1 */ -#define _SMU_PPUPATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_HFRCO1_DEFAULT (_SMU_PPUPATD1_HFRCO1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_HFXO0 (0x1UL << 18) /**< HFXO0 Privileged Access */ -#define _SMU_PPUPATD1_HFXO0_SHIFT 18 /**< Shift value for SMU_HFXO0 */ -#define _SMU_PPUPATD1_HFXO0_MASK 0x40000UL /**< Bit mask for SMU_HFXO0 */ -#define _SMU_PPUPATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_HFXO0_DEFAULT (_SMU_PPUPATD1_HFXO0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_I2C0 (0x1UL << 19) /**< I2C0 Privileged Access */ -#define _SMU_PPUPATD1_I2C0_SHIFT 19 /**< Shift value for SMU_I2C0 */ -#define _SMU_PPUPATD1_I2C0_MASK 0x80000UL /**< Bit mask for SMU_I2C0 */ -#define _SMU_PPUPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_I2C0_DEFAULT (_SMU_PPUPATD1_I2C0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_WDOG0 (0x1UL << 20) /**< WDOG0 Privileged Access */ -#define _SMU_PPUPATD1_WDOG0_SHIFT 20 /**< Shift value for SMU_WDOG0 */ -#define _SMU_PPUPATD1_WDOG0_MASK 0x100000UL /**< Bit mask for SMU_WDOG0 */ -#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_WDOG1 (0x1UL << 21) /**< WDOG1 Privileged Access */ -#define _SMU_PPUPATD1_WDOG1_SHIFT 21 /**< Shift value for SMU_WDOG1 */ -#define _SMU_PPUPATD1_WDOG1_MASK 0x200000UL /**< Bit mask for SMU_WDOG1 */ -#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_EUSART0 (0x1UL << 22) /**< EUSART0 Privileged Access */ -#define _SMU_PPUPATD1_EUSART0_SHIFT 22 /**< Shift value for SMU_EUSART0 */ -#define _SMU_PPUPATD1_EUSART0_MASK 0x400000UL /**< Bit mask for SMU_EUSART0 */ -#define _SMU_PPUPATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_EUSART0_DEFAULT (_SMU_PPUPATD1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SEMAILBOX (0x1UL << 23) /**< SEMAILBOX Privileged Access */ -#define _SMU_PPUPATD1_SEMAILBOX_SHIFT 23 /**< Shift value for SMU_SEMAILBOX */ -#define _SMU_PPUPATD1_SEMAILBOX_MASK 0x800000UL /**< Bit mask for SMU_SEMAILBOX */ -#define _SMU_PPUPATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SEMAILBOX_DEFAULT (_SMU_PPUPATD1_SEMAILBOX_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_AHBRADIO (0x1UL << 24) /**< AHBRADIO Privileged Access */ -#define _SMU_PPUPATD1_AHBRADIO_SHIFT 24 /**< Shift value for SMU_AHBRADIO */ -#define _SMU_PPUPATD1_AHBRADIO_MASK 0x1000000UL /**< Bit mask for SMU_AHBRADIO */ -#define _SMU_PPUPATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_AHBRADIO_DEFAULT (_SMU_PPUPATD1_AHBRADIO_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x01FFFFFFUL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0x01FFFFFFUL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SYSRTC (0x1UL << 0) /**< SYSRTC Privileged Access */ +#define _SMU_PPUPATD1_SYSRTC_SHIFT 0 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUPATD1_SYSRTC_MASK 0x1UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUPATD1_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SYSRTC_DEFAULT (_SMU_PPUPATD1_SYSRTC_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LCD (0x1UL << 1) /**< LCD Privileged Access */ +#define _SMU_PPUPATD1_LCD_SHIFT 1 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD1_LCD_MASK 0x2UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD1_LCD_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LCD_DEFAULT (_SMU_PPUPATD1_LCD_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_KEYSCAN (0x1UL << 2) /**< KEYSCAN Privileged Access */ +#define _SMU_PPUPATD1_KEYSCAN_SHIFT 2 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUPATD1_KEYSCAN_MASK 0x4UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUPATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_KEYSCAN_DEFAULT (_SMU_PPUPATD1_KEYSCAN_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DMEM (0x1UL << 3) /**< DMEM Privileged Access */ +#define _SMU_PPUPATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUPATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUPATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DMEM_DEFAULT (_SMU_PPUPATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LCDRF (0x1UL << 4) /**< LCDRF Privileged Access */ +#define _SMU_PPUPATD1_LCDRF_SHIFT 4 /**< Shift value for SMU_LCDRF */ +#define _SMU_PPUPATD1_LCDRF_MASK 0x10UL /**< Bit mask for SMU_LCDRF */ +#define _SMU_PPUPATD1_LCDRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LCDRF_DEFAULT (_SMU_PPUPATD1_LCDRF_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PFMXPPRF (0x1UL << 5) /**< PFMXPPRF Privileged Access */ +#define _SMU_PPUPATD1_PFMXPPRF_SHIFT 5 /**< Shift value for SMU_PFMXPPRF */ +#define _SMU_PPUPATD1_PFMXPPRF_MASK 0x20UL /**< Bit mask for SMU_PFMXPPRF */ +#define _SMU_PPUPATD1_PFMXPPRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PFMXPPRF_DEFAULT (_SMU_PPUPATD1_PFMXPPRF_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES (0x1UL << 6) /**< RADIOAES Privileged Access */ +#define _SMU_PPUPATD1_RADIOAES_SHIFT 6 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_MASK 0x40UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES_DEFAULT (_SMU_PPUPATD1_RADIOAES_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 7) /**< SMU Privileged Access */ +#define _SMU_PPUPATD1_SMU_SHIFT 7 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x80UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS (0x1UL << 8) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUPATD1_SMUCFGNS_SHIFT 8 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_MASK 0x100UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS_DEFAULT (_SMU_PPUPATD1_SMUCFGNS_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0 (0x1UL << 9) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUPATD1_LETIMER0_SHIFT 9 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_MASK 0x200UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0_DEFAULT (_SMU_PPUPATD1_LETIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0 (0x1UL << 10) /**< IADC0 Privileged Access */ +#define _SMU_PPUPATD1_IADC0_SHIFT 10 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_MASK 0x400UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0_DEFAULT (_SMU_PPUPATD1_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP0 (0x1UL << 11) /**< ACMP0 Privileged Access */ +#define _SMU_PPUPATD1_ACMP0_SHIFT 11 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD1_ACMP0_MASK 0x800UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP0_DEFAULT (_SMU_PPUPATD1_ACMP0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP1 (0x1UL << 12) /**< ACMP1 Privileged Access */ +#define _SMU_PPUPATD1_ACMP1_SHIFT 12 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD1_ACMP1_MASK 0x1000UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP1_DEFAULT (_SMU_PPUPATD1_ACMP1_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0 (0x1UL << 13) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUPATD1_AMUXCP0_SHIFT 13 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_MASK 0x2000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0_DEFAULT (_SMU_PPUPATD1_AMUXCP0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC0 (0x1UL << 14) /**< VDAC0 Privileged Access */ +#define _SMU_PPUPATD1_VDAC0_SHIFT 14 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD1_VDAC0_MASK 0x4000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC0_DEFAULT (_SMU_PPUPATD1_VDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT (0x1UL << 15) /**< PCNT Privileged Access */ +#define _SMU_PPUPATD1_PCNT_SHIFT 15 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUPATD1_PCNT_MASK 0x8000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUPATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT_DEFAULT (_SMU_PPUPATD1_PCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LESENSE (0x1UL << 16) /**< LESENSE Privileged Access */ +#define _SMU_PPUPATD1_LESENSE_SHIFT 16 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD1_LESENSE_MASK 0x10000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD1_LESENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LESENSE_DEFAULT (_SMU_PPUPATD1_LESENSE_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFRCO1 (0x1UL << 17) /**< HFRCO1 Privileged Access */ +#define _SMU_PPUPATD1_HFRCO1_SHIFT 17 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUPATD1_HFRCO1_MASK 0x20000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUPATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFRCO1_DEFAULT (_SMU_PPUPATD1_HFRCO1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFXO0 (0x1UL << 18) /**< HFXO0 Privileged Access */ +#define _SMU_PPUPATD1_HFXO0_SHIFT 18 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUPATD1_HFXO0_MASK 0x40000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUPATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFXO0_DEFAULT (_SMU_PPUPATD1_HFXO0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0 (0x1UL << 19) /**< I2C0 Privileged Access */ +#define _SMU_PPUPATD1_I2C0_SHIFT 19 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_MASK 0x80000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0_DEFAULT (_SMU_PPUPATD1_I2C0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 20) /**< WDOG0 Privileged Access */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 20 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x100000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 21) /**< WDOG1 Privileged Access */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 21 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x200000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART0 (0x1UL << 22) /**< EUSART0 Privileged Access */ +#define _SMU_PPUPATD1_EUSART0_SHIFT 22 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUPATD1_EUSART0_MASK 0x400000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUPATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART0_DEFAULT (_SMU_PPUPATD1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SEMAILBOX (0x1UL << 23) /**< SEMAILBOX Privileged Access */ +#define _SMU_PPUPATD1_SEMAILBOX_SHIFT 23 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUPATD1_SEMAILBOX_MASK 0x800000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUPATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SEMAILBOX_DEFAULT (_SMU_PPUPATD1_SEMAILBOX_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AHBRADIO (0x1UL << 24) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUPATD1_AHBRADIO_SHIFT 24 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUPATD1_AHBRADIO_MASK 0x1000000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUPATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AHBRADIO_DEFAULT (_SMU_PPUPATD1_AHBRADIO_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ /* Bit fields for SMU PPUSATD0 */ -#define _SMU_PPUSATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUSATD0 */ -#define _SMU_PPUSATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EMU (0x1UL << 1) /**< EMU Secure Access */ -#define _SMU_PPUSATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ -#define _SMU_PPUSATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ -#define _SMU_PPUSATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EMU_DEFAULT (_SMU_PPUSATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_CMU (0x1UL << 2) /**< CMU Secure Access */ -#define _SMU_PPUSATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ -#define _SMU_PPUSATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ -#define _SMU_PPUSATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_CMU_DEFAULT (_SMU_PPUSATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Secure Access */ -#define _SMU_PPUSATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ -#define _SMU_PPUSATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ -#define _SMU_PPUSATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_HFRCO0_DEFAULT (_SMU_PPUSATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_FSRCO (0x1UL << 4) /**< FSRCO Secure Access */ -#define _SMU_PPUSATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ -#define _SMU_PPUSATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ -#define _SMU_PPUSATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_FSRCO_DEFAULT (_SMU_PPUSATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Secure Access */ -#define _SMU_PPUSATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ -#define _SMU_PPUSATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ -#define _SMU_PPUSATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_DPLL0_DEFAULT (_SMU_PPUSATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LFXO (0x1UL << 6) /**< LFXO Secure Access */ -#define _SMU_PPUSATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ -#define _SMU_PPUSATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ -#define _SMU_PPUSATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LFXO_DEFAULT (_SMU_PPUSATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LFRCO (0x1UL << 7) /**< LFRCO Secure Access */ -#define _SMU_PPUSATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ -#define _SMU_PPUSATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ -#define _SMU_PPUSATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LFRCO_DEFAULT (_SMU_PPUSATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Secure Access */ -#define _SMU_PPUSATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ -#define _SMU_PPUSATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ -#define _SMU_PPUSATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_ULFRCO_DEFAULT (_SMU_PPUSATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_MSC (0x1UL << 9) /**< MSC Secure Access */ -#define _SMU_PPUSATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ -#define _SMU_PPUSATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ -#define _SMU_PPUSATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_MSC_DEFAULT (_SMU_PPUSATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Secure Access */ -#define _SMU_PPUSATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ -#define _SMU_PPUSATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ -#define _SMU_PPUSATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_ICACHE0_DEFAULT (_SMU_PPUSATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_PRS (0x1UL << 11) /**< PRS Secure Access */ -#define _SMU_PPUSATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ -#define _SMU_PPUSATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ -#define _SMU_PPUSATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_PRS_DEFAULT (_SMU_PPUSATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_GPIO (0x1UL << 12) /**< GPIO Secure Access */ -#define _SMU_PPUSATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ -#define _SMU_PPUSATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ -#define _SMU_PPUSATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_GPIO_DEFAULT (_SMU_PPUSATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LDMA (0x1UL << 13) /**< LDMA Secure Access */ -#define _SMU_PPUSATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ -#define _SMU_PPUSATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ -#define _SMU_PPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LDMA_DEFAULT (_SMU_PPUSATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Secure Access */ -#define _SMU_PPUSATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ -#define _SMU_PPUSATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ -#define _SMU_PPUSATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LDMAXBAR_DEFAULT (_SMU_PPUSATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Secure Access */ -#define _SMU_PPUSATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ -#define _SMU_PPUSATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ -#define _SMU_PPUSATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER0_DEFAULT (_SMU_PPUSATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Secure Access */ -#define _SMU_PPUSATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ -#define _SMU_PPUSATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ -#define _SMU_PPUSATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER1_DEFAULT (_SMU_PPUSATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Secure Access */ -#define _SMU_PPUSATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ -#define _SMU_PPUSATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ -#define _SMU_PPUSATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER2_DEFAULT (_SMU_PPUSATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Secure Access */ -#define _SMU_PPUSATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ -#define _SMU_PPUSATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ -#define _SMU_PPUSATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER3_DEFAULT (_SMU_PPUSATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Secure Access */ -#define _SMU_PPUSATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ -#define _SMU_PPUSATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ -#define _SMU_PPUSATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER4_DEFAULT (_SMU_PPUSATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_USART0 (0x1UL << 20) /**< USART0 Secure Access */ -#define _SMU_PPUSATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ -#define _SMU_PPUSATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ -#define _SMU_PPUSATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_USART0_DEFAULT (_SMU_PPUSATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_BURTC (0x1UL << 21) /**< BURTC Secure Access */ -#define _SMU_PPUSATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ -#define _SMU_PPUSATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ -#define _SMU_PPUSATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_BURTC_DEFAULT (_SMU_PPUSATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_I2C1 (0x1UL << 22) /**< I2C1 Secure Access */ -#define _SMU_PPUSATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ -#define _SMU_PPUSATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ -#define _SMU_PPUSATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_I2C1_DEFAULT (_SMU_PPUSATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Secure Access */ -#define _SMU_PPUSATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ -#define _SMU_PPUSATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ -#define _SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Secure Access */ -#define _SMU_PPUSATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ -#define _SMU_PPUSATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ -#define _SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Secure Access */ -#define _SMU_PPUSATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ -#define _SMU_PPUSATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ -#define _SMU_PPUSATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSCFG_DEFAULT (_SMU_PPUSATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_BURAM (0x1UL << 26) /**< BURAM Secure Access */ -#define _SMU_PPUSATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ -#define _SMU_PPUSATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ -#define _SMU_PPUSATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_BURAM_DEFAULT (_SMU_PPUSATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_GPCRC (0x1UL << 27) /**< GPCRC Secure Access */ -#define _SMU_PPUSATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ -#define _SMU_PPUSATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ -#define _SMU_PPUSATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_GPCRC_DEFAULT (_SMU_PPUSATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_DCDC (0x1UL << 28) /**< DCDC Secure Access */ -#define _SMU_PPUSATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ -#define _SMU_PPUSATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ -#define _SMU_PPUSATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_DCDC_DEFAULT (_SMU_PPUSATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Secure Access */ -#define _SMU_PPUSATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ -#define _SMU_PPUSATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ -#define _SMU_PPUSATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUSATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Secure Access */ -#define _SMU_PPUSATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ -#define _SMU_PPUSATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ -#define _SMU_PPUSATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EUSART1_DEFAULT (_SMU_PPUSATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EUSART2 (0x1UL << 31) /**< EUSART2 Secure Access */ -#define _SMU_PPUSATD0_EUSART2_SHIFT 31 /**< Shift value for SMU_EUSART2 */ -#define _SMU_PPUSATD0_EUSART2_MASK 0x80000000UL /**< Bit mask for SMU_EUSART2 */ -#define _SMU_PPUSATD0_EUSART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EUSART2_DEFAULT (_SMU_PPUSATD0_EUSART2_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define _SMU_PPUSATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUSATD0 */ +#define _SMU_PPUSATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU (0x1UL << 1) /**< EMU Secure Access */ +#define _SMU_PPUSATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU_DEFAULT (_SMU_PPUSATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU (0x1UL << 2) /**< CMU Secure Access */ +#define _SMU_PPUSATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU_DEFAULT (_SMU_PPUSATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Secure Access */ +#define _SMU_PPUSATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0_DEFAULT (_SMU_PPUSATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO (0x1UL << 4) /**< FSRCO Secure Access */ +#define _SMU_PPUSATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO_DEFAULT (_SMU_PPUSATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Secure Access */ +#define _SMU_PPUSATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0_DEFAULT (_SMU_PPUSATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO (0x1UL << 6) /**< LFXO Secure Access */ +#define _SMU_PPUSATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO_DEFAULT (_SMU_PPUSATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO (0x1UL << 7) /**< LFRCO Secure Access */ +#define _SMU_PPUSATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO_DEFAULT (_SMU_PPUSATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Secure Access */ +#define _SMU_PPUSATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO_DEFAULT (_SMU_PPUSATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC (0x1UL << 9) /**< MSC Secure Access */ +#define _SMU_PPUSATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC_DEFAULT (_SMU_PPUSATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Secure Access */ +#define _SMU_PPUSATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0_DEFAULT (_SMU_PPUSATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS (0x1UL << 11) /**< PRS Secure Access */ +#define _SMU_PPUSATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS_DEFAULT (_SMU_PPUSATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO (0x1UL << 12) /**< GPIO Secure Access */ +#define _SMU_PPUSATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO_DEFAULT (_SMU_PPUSATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA (0x1UL << 13) /**< LDMA Secure Access */ +#define _SMU_PPUSATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA_DEFAULT (_SMU_PPUSATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Secure Access */ +#define _SMU_PPUSATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR_DEFAULT (_SMU_PPUSATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Secure Access */ +#define _SMU_PPUSATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0_DEFAULT (_SMU_PPUSATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Secure Access */ +#define _SMU_PPUSATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1_DEFAULT (_SMU_PPUSATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Secure Access */ +#define _SMU_PPUSATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2_DEFAULT (_SMU_PPUSATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Secure Access */ +#define _SMU_PPUSATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3_DEFAULT (_SMU_PPUSATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Secure Access */ +#define _SMU_PPUSATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4_DEFAULT (_SMU_PPUSATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART0 (0x1UL << 20) /**< USART0 Secure Access */ +#define _SMU_PPUSATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUSATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUSATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART0_DEFAULT (_SMU_PPUSATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC (0x1UL << 21) /**< BURTC Secure Access */ +#define _SMU_PPUSATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC_DEFAULT (_SMU_PPUSATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_I2C1 (0x1UL << 22) /**< I2C1 Secure Access */ +#define _SMU_PPUSATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUSATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUSATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_I2C1_DEFAULT (_SMU_PPUSATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Secure Access */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Secure Access */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Secure Access */ +#define _SMU_PPUSATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG_DEFAULT (_SMU_PPUSATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURAM (0x1UL << 26) /**< BURAM Secure Access */ +#define _SMU_PPUSATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUSATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUSATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURAM_DEFAULT (_SMU_PPUSATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPCRC (0x1UL << 27) /**< GPCRC Secure Access */ +#define _SMU_PPUSATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUSATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUSATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPCRC_DEFAULT (_SMU_PPUSATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DCDC (0x1UL << 28) /**< DCDC Secure Access */ +#define _SMU_PPUSATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUSATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUSATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DCDC_DEFAULT (_SMU_PPUSATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Secure Access */ +#define _SMU_PPUSATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUSATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUSATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUSATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Secure Access */ +#define _SMU_PPUSATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUSATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUSATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EUSART1_DEFAULT (_SMU_PPUSATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EUSART2 (0x1UL << 31) /**< EUSART2 Secure Access */ +#define _SMU_PPUSATD0_EUSART2_SHIFT 31 /**< Shift value for SMU_EUSART2 */ +#define _SMU_PPUSATD0_EUSART2_MASK 0x80000000UL /**< Bit mask for SMU_EUSART2 */ +#define _SMU_PPUSATD0_EUSART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EUSART2_DEFAULT (_SMU_PPUSATD0_EUSART2_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ /* Bit fields for SMU PPUSATD1 */ -#define _SMU_PPUSATD1_RESETVALUE 0x01FFFFFFUL /**< Default value for SMU_PPUSATD1 */ -#define _SMU_PPUSATD1_MASK 0x01FFFFFFUL /**< Mask for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SYSRTC (0x1UL << 0) /**< SYSRTC Secure Access */ -#define _SMU_PPUSATD1_SYSRTC_SHIFT 0 /**< Shift value for SMU_SYSRTC */ -#define _SMU_PPUSATD1_SYSRTC_MASK 0x1UL /**< Bit mask for SMU_SYSRTC */ -#define _SMU_PPUSATD1_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SYSRTC_DEFAULT (_SMU_PPUSATD1_SYSRTC_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LCD (0x1UL << 1) /**< LCD Secure Access */ -#define _SMU_PPUSATD1_LCD_SHIFT 1 /**< Shift value for SMU_LCD */ -#define _SMU_PPUSATD1_LCD_MASK 0x2UL /**< Bit mask for SMU_LCD */ -#define _SMU_PPUSATD1_LCD_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LCD_DEFAULT (_SMU_PPUSATD1_LCD_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_KEYSCAN (0x1UL << 2) /**< KEYSCAN Secure Access */ -#define _SMU_PPUSATD1_KEYSCAN_SHIFT 2 /**< Shift value for SMU_KEYSCAN */ -#define _SMU_PPUSATD1_KEYSCAN_MASK 0x4UL /**< Bit mask for SMU_KEYSCAN */ -#define _SMU_PPUSATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_KEYSCAN_DEFAULT (_SMU_PPUSATD1_KEYSCAN_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_DMEM (0x1UL << 3) /**< DMEM Secure Access */ -#define _SMU_PPUSATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ -#define _SMU_PPUSATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ -#define _SMU_PPUSATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_DMEM_DEFAULT (_SMU_PPUSATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LCDRF (0x1UL << 4) /**< LCDRF Secure Access */ -#define _SMU_PPUSATD1_LCDRF_SHIFT 4 /**< Shift value for SMU_LCDRF */ -#define _SMU_PPUSATD1_LCDRF_MASK 0x10UL /**< Bit mask for SMU_LCDRF */ -#define _SMU_PPUSATD1_LCDRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LCDRF_DEFAULT (_SMU_PPUSATD1_LCDRF_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_PFMXPPRF (0x1UL << 5) /**< PFMXPPRF Secure Access */ -#define _SMU_PPUSATD1_PFMXPPRF_SHIFT 5 /**< Shift value for SMU_PFMXPPRF */ -#define _SMU_PPUSATD1_PFMXPPRF_MASK 0x20UL /**< Bit mask for SMU_PFMXPPRF */ -#define _SMU_PPUSATD1_PFMXPPRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_PFMXPPRF_DEFAULT (_SMU_PPUSATD1_PFMXPPRF_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_RADIOAES (0x1UL << 6) /**< RADIOAES Secure Access */ -#define _SMU_PPUSATD1_RADIOAES_SHIFT 6 /**< Shift value for SMU_RADIOAES */ -#define _SMU_PPUSATD1_RADIOAES_MASK 0x40UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_PPUSATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_RADIOAES_DEFAULT (_SMU_PPUSATD1_RADIOAES_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SMU (0x1UL << 7) /**< SMU Secure Access */ -#define _SMU_PPUSATD1_SMU_SHIFT 7 /**< Shift value for SMU_SMU */ -#define _SMU_PPUSATD1_SMU_MASK 0x80UL /**< Bit mask for SMU_SMU */ -#define _SMU_PPUSATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SMU_DEFAULT (_SMU_PPUSATD1_SMU_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SMUCFGNS (0x1UL << 8) /**< SMUCFGNS Secure Access */ -#define _SMU_PPUSATD1_SMUCFGNS_SHIFT 8 /**< Shift value for SMU_SMUCFGNS */ -#define _SMU_PPUSATD1_SMUCFGNS_MASK 0x100UL /**< Bit mask for SMU_SMUCFGNS */ -#define _SMU_PPUSATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SMUCFGNS_DEFAULT (_SMU_PPUSATD1_SMUCFGNS_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LETIMER0 (0x1UL << 9) /**< LETIMER0 Secure Access */ -#define _SMU_PPUSATD1_LETIMER0_SHIFT 9 /**< Shift value for SMU_LETIMER0 */ -#define _SMU_PPUSATD1_LETIMER0_MASK 0x200UL /**< Bit mask for SMU_LETIMER0 */ -#define _SMU_PPUSATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LETIMER0_DEFAULT (_SMU_PPUSATD1_LETIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_IADC0 (0x1UL << 10) /**< IADC0 Secure Access */ -#define _SMU_PPUSATD1_IADC0_SHIFT 10 /**< Shift value for SMU_IADC0 */ -#define _SMU_PPUSATD1_IADC0_MASK 0x400UL /**< Bit mask for SMU_IADC0 */ -#define _SMU_PPUSATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_IADC0_DEFAULT (_SMU_PPUSATD1_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_ACMP0 (0x1UL << 11) /**< ACMP0 Secure Access */ -#define _SMU_PPUSATD1_ACMP0_SHIFT 11 /**< Shift value for SMU_ACMP0 */ -#define _SMU_PPUSATD1_ACMP0_MASK 0x800UL /**< Bit mask for SMU_ACMP0 */ -#define _SMU_PPUSATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_ACMP0_DEFAULT (_SMU_PPUSATD1_ACMP0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_ACMP1 (0x1UL << 12) /**< ACMP1 Secure Access */ -#define _SMU_PPUSATD1_ACMP1_SHIFT 12 /**< Shift value for SMU_ACMP1 */ -#define _SMU_PPUSATD1_ACMP1_MASK 0x1000UL /**< Bit mask for SMU_ACMP1 */ -#define _SMU_PPUSATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_ACMP1_DEFAULT (_SMU_PPUSATD1_ACMP1_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_AMUXCP0 (0x1UL << 13) /**< AMUXCP0 Secure Access */ -#define _SMU_PPUSATD1_AMUXCP0_SHIFT 13 /**< Shift value for SMU_AMUXCP0 */ -#define _SMU_PPUSATD1_AMUXCP0_MASK 0x2000UL /**< Bit mask for SMU_AMUXCP0 */ -#define _SMU_PPUSATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_AMUXCP0_DEFAULT (_SMU_PPUSATD1_AMUXCP0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_VDAC0 (0x1UL << 14) /**< VDAC0 Secure Access */ -#define _SMU_PPUSATD1_VDAC0_SHIFT 14 /**< Shift value for SMU_VDAC0 */ -#define _SMU_PPUSATD1_VDAC0_MASK 0x4000UL /**< Bit mask for SMU_VDAC0 */ -#define _SMU_PPUSATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_VDAC0_DEFAULT (_SMU_PPUSATD1_VDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_PCNT (0x1UL << 15) /**< PCNT Secure Access */ -#define _SMU_PPUSATD1_PCNT_SHIFT 15 /**< Shift value for SMU_PCNT */ -#define _SMU_PPUSATD1_PCNT_MASK 0x8000UL /**< Bit mask for SMU_PCNT */ -#define _SMU_PPUSATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_PCNT_DEFAULT (_SMU_PPUSATD1_PCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LESENSE (0x1UL << 16) /**< LESENSE Secure Access */ -#define _SMU_PPUSATD1_LESENSE_SHIFT 16 /**< Shift value for SMU_LESENSE */ -#define _SMU_PPUSATD1_LESENSE_MASK 0x10000UL /**< Bit mask for SMU_LESENSE */ -#define _SMU_PPUSATD1_LESENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LESENSE_DEFAULT (_SMU_PPUSATD1_LESENSE_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_HFRCO1 (0x1UL << 17) /**< HFRCO1 Secure Access */ -#define _SMU_PPUSATD1_HFRCO1_SHIFT 17 /**< Shift value for SMU_HFRCO1 */ -#define _SMU_PPUSATD1_HFRCO1_MASK 0x20000UL /**< Bit mask for SMU_HFRCO1 */ -#define _SMU_PPUSATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_HFRCO1_DEFAULT (_SMU_PPUSATD1_HFRCO1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_HFXO0 (0x1UL << 18) /**< HFXO0 Secure Access */ -#define _SMU_PPUSATD1_HFXO0_SHIFT 18 /**< Shift value for SMU_HFXO0 */ -#define _SMU_PPUSATD1_HFXO0_MASK 0x40000UL /**< Bit mask for SMU_HFXO0 */ -#define _SMU_PPUSATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_HFXO0_DEFAULT (_SMU_PPUSATD1_HFXO0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_I2C0 (0x1UL << 19) /**< I2C0 Secure Access */ -#define _SMU_PPUSATD1_I2C0_SHIFT 19 /**< Shift value for SMU_I2C0 */ -#define _SMU_PPUSATD1_I2C0_MASK 0x80000UL /**< Bit mask for SMU_I2C0 */ -#define _SMU_PPUSATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_I2C0_DEFAULT (_SMU_PPUSATD1_I2C0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_WDOG0 (0x1UL << 20) /**< WDOG0 Secure Access */ -#define _SMU_PPUSATD1_WDOG0_SHIFT 20 /**< Shift value for SMU_WDOG0 */ -#define _SMU_PPUSATD1_WDOG0_MASK 0x100000UL /**< Bit mask for SMU_WDOG0 */ -#define _SMU_PPUSATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_WDOG0_DEFAULT (_SMU_PPUSATD1_WDOG0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_WDOG1 (0x1UL << 21) /**< WDOG1 Secure Access */ -#define _SMU_PPUSATD1_WDOG1_SHIFT 21 /**< Shift value for SMU_WDOG1 */ -#define _SMU_PPUSATD1_WDOG1_MASK 0x200000UL /**< Bit mask for SMU_WDOG1 */ -#define _SMU_PPUSATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_WDOG1_DEFAULT (_SMU_PPUSATD1_WDOG1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_EUSART0 (0x1UL << 22) /**< EUSART0 Secure Access */ -#define _SMU_PPUSATD1_EUSART0_SHIFT 22 /**< Shift value for SMU_EUSART0 */ -#define _SMU_PPUSATD1_EUSART0_MASK 0x400000UL /**< Bit mask for SMU_EUSART0 */ -#define _SMU_PPUSATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_EUSART0_DEFAULT (_SMU_PPUSATD1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SEMAILBOX (0x1UL << 23) /**< SEMAILBOX Secure Access */ -#define _SMU_PPUSATD1_SEMAILBOX_SHIFT 23 /**< Shift value for SMU_SEMAILBOX */ -#define _SMU_PPUSATD1_SEMAILBOX_MASK 0x800000UL /**< Bit mask for SMU_SEMAILBOX */ -#define _SMU_PPUSATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SEMAILBOX_DEFAULT (_SMU_PPUSATD1_SEMAILBOX_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_AHBRADIO (0x1UL << 24) /**< AHBRADIO Secure Access */ -#define _SMU_PPUSATD1_AHBRADIO_SHIFT 24 /**< Shift value for SMU_AHBRADIO */ -#define _SMU_PPUSATD1_AHBRADIO_MASK 0x1000000UL /**< Bit mask for SMU_AHBRADIO */ -#define _SMU_PPUSATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_AHBRADIO_DEFAULT (_SMU_PPUSATD1_AHBRADIO_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define _SMU_PPUSATD1_RESETVALUE 0x01FFFFFFUL /**< Default value for SMU_PPUSATD1 */ +#define _SMU_PPUSATD1_MASK 0x01FFFFFFUL /**< Mask for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SYSRTC (0x1UL << 0) /**< SYSRTC Secure Access */ +#define _SMU_PPUSATD1_SYSRTC_SHIFT 0 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUSATD1_SYSRTC_MASK 0x1UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUSATD1_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SYSRTC_DEFAULT (_SMU_PPUSATD1_SYSRTC_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LCD (0x1UL << 1) /**< LCD Secure Access */ +#define _SMU_PPUSATD1_LCD_SHIFT 1 /**< Shift value for SMU_LCD */ +#define _SMU_PPUSATD1_LCD_MASK 0x2UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUSATD1_LCD_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LCD_DEFAULT (_SMU_PPUSATD1_LCD_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_KEYSCAN (0x1UL << 2) /**< KEYSCAN Secure Access */ +#define _SMU_PPUSATD1_KEYSCAN_SHIFT 2 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUSATD1_KEYSCAN_MASK 0x4UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUSATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_KEYSCAN_DEFAULT (_SMU_PPUSATD1_KEYSCAN_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DMEM (0x1UL << 3) /**< DMEM Secure Access */ +#define _SMU_PPUSATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUSATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUSATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DMEM_DEFAULT (_SMU_PPUSATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LCDRF (0x1UL << 4) /**< LCDRF Secure Access */ +#define _SMU_PPUSATD1_LCDRF_SHIFT 4 /**< Shift value for SMU_LCDRF */ +#define _SMU_PPUSATD1_LCDRF_MASK 0x10UL /**< Bit mask for SMU_LCDRF */ +#define _SMU_PPUSATD1_LCDRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LCDRF_DEFAULT (_SMU_PPUSATD1_LCDRF_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PFMXPPRF (0x1UL << 5) /**< PFMXPPRF Secure Access */ +#define _SMU_PPUSATD1_PFMXPPRF_SHIFT 5 /**< Shift value for SMU_PFMXPPRF */ +#define _SMU_PPUSATD1_PFMXPPRF_MASK 0x20UL /**< Bit mask for SMU_PFMXPPRF */ +#define _SMU_PPUSATD1_PFMXPPRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PFMXPPRF_DEFAULT (_SMU_PPUSATD1_PFMXPPRF_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES (0x1UL << 6) /**< RADIOAES Secure Access */ +#define _SMU_PPUSATD1_RADIOAES_SHIFT 6 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_MASK 0x40UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES_DEFAULT (_SMU_PPUSATD1_RADIOAES_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU (0x1UL << 7) /**< SMU Secure Access */ +#define _SMU_PPUSATD1_SMU_SHIFT 7 /**< Shift value for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_MASK 0x80UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU_DEFAULT (_SMU_PPUSATD1_SMU_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS (0x1UL << 8) /**< SMUCFGNS Secure Access */ +#define _SMU_PPUSATD1_SMUCFGNS_SHIFT 8 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_MASK 0x100UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS_DEFAULT (_SMU_PPUSATD1_SMUCFGNS_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0 (0x1UL << 9) /**< LETIMER0 Secure Access */ +#define _SMU_PPUSATD1_LETIMER0_SHIFT 9 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_MASK 0x200UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0_DEFAULT (_SMU_PPUSATD1_LETIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0 (0x1UL << 10) /**< IADC0 Secure Access */ +#define _SMU_PPUSATD1_IADC0_SHIFT 10 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_MASK 0x400UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0_DEFAULT (_SMU_PPUSATD1_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP0 (0x1UL << 11) /**< ACMP0 Secure Access */ +#define _SMU_PPUSATD1_ACMP0_SHIFT 11 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUSATD1_ACMP0_MASK 0x800UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUSATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP0_DEFAULT (_SMU_PPUSATD1_ACMP0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP1 (0x1UL << 12) /**< ACMP1 Secure Access */ +#define _SMU_PPUSATD1_ACMP1_SHIFT 12 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUSATD1_ACMP1_MASK 0x1000UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUSATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP1_DEFAULT (_SMU_PPUSATD1_ACMP1_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0 (0x1UL << 13) /**< AMUXCP0 Secure Access */ +#define _SMU_PPUSATD1_AMUXCP0_SHIFT 13 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_MASK 0x2000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0_DEFAULT (_SMU_PPUSATD1_AMUXCP0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC0 (0x1UL << 14) /**< VDAC0 Secure Access */ +#define _SMU_PPUSATD1_VDAC0_SHIFT 14 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUSATD1_VDAC0_MASK 0x4000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUSATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC0_DEFAULT (_SMU_PPUSATD1_VDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PCNT (0x1UL << 15) /**< PCNT Secure Access */ +#define _SMU_PPUSATD1_PCNT_SHIFT 15 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUSATD1_PCNT_MASK 0x8000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUSATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PCNT_DEFAULT (_SMU_PPUSATD1_PCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LESENSE (0x1UL << 16) /**< LESENSE Secure Access */ +#define _SMU_PPUSATD1_LESENSE_SHIFT 16 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUSATD1_LESENSE_MASK 0x10000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUSATD1_LESENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LESENSE_DEFAULT (_SMU_PPUSATD1_LESENSE_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFRCO1 (0x1UL << 17) /**< HFRCO1 Secure Access */ +#define _SMU_PPUSATD1_HFRCO1_SHIFT 17 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUSATD1_HFRCO1_MASK 0x20000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUSATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFRCO1_DEFAULT (_SMU_PPUSATD1_HFRCO1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFXO0 (0x1UL << 18) /**< HFXO0 Secure Access */ +#define _SMU_PPUSATD1_HFXO0_SHIFT 18 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUSATD1_HFXO0_MASK 0x40000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUSATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFXO0_DEFAULT (_SMU_PPUSATD1_HFXO0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0 (0x1UL << 19) /**< I2C0 Secure Access */ +#define _SMU_PPUSATD1_I2C0_SHIFT 19 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_MASK 0x80000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0_DEFAULT (_SMU_PPUSATD1_I2C0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0 (0x1UL << 20) /**< WDOG0 Secure Access */ +#define _SMU_PPUSATD1_WDOG0_SHIFT 20 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_MASK 0x100000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0_DEFAULT (_SMU_PPUSATD1_WDOG0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG1 (0x1UL << 21) /**< WDOG1 Secure Access */ +#define _SMU_PPUSATD1_WDOG1_SHIFT 21 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUSATD1_WDOG1_MASK 0x200000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUSATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG1_DEFAULT (_SMU_PPUSATD1_WDOG1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART0 (0x1UL << 22) /**< EUSART0 Secure Access */ +#define _SMU_PPUSATD1_EUSART0_SHIFT 22 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUSATD1_EUSART0_MASK 0x400000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUSATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART0_DEFAULT (_SMU_PPUSATD1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SEMAILBOX (0x1UL << 23) /**< SEMAILBOX Secure Access */ +#define _SMU_PPUSATD1_SEMAILBOX_SHIFT 23 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUSATD1_SEMAILBOX_MASK 0x800000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUSATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SEMAILBOX_DEFAULT (_SMU_PPUSATD1_SEMAILBOX_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AHBRADIO (0x1UL << 24) /**< AHBRADIO Secure Access */ +#define _SMU_PPUSATD1_AHBRADIO_SHIFT 24 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUSATD1_AHBRADIO_MASK 0x1000000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUSATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AHBRADIO_DEFAULT (_SMU_PPUSATD1_AHBRADIO_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ /* Bit fields for SMU PPUFS */ -#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ -#define _SMU_PPUFS_MASK 0x000000FFUL /**< Mask for SMU_PPUFS */ -#define _SMU_PPUFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ -#define _SMU_PPUFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ -#define _SMU_PPUFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ -#define SMU_PPUFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x000000FFUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ /* Bit fields for SMU BMPUPATD0 */ -#define _SMU_BMPUPATD0_RESETVALUE 0x0000003FUL /**< Default value for SMU_BMPUPATD0 */ -#define _SMU_BMPUPATD0_MASK 0x0000003FUL /**< Mask for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ -#define _SMU_BMPUPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ -#define _SMU_BMPUPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_BMPUPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOAES_DEFAULT (_SMU_BMPUPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */ -#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */ -#define _SMU_BMPUPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ -#define _SMU_BMPUPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ -#define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_LDMA_DEFAULT (_SMU_BMPUPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RFECA0 (0x1UL << 3) /**< RFECA0 privileged mode */ -#define _SMU_BMPUPATD0_RFECA0_SHIFT 3 /**< Shift value for SMU_RFECA0 */ -#define _SMU_BMPUPATD0_RFECA0_MASK 0x8UL /**< Bit mask for SMU_RFECA0 */ -#define _SMU_BMPUPATD0_RFECA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RFECA0_DEFAULT (_SMU_BMPUPATD0_RFECA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RFECA1 (0x1UL << 4) /**< RFECA1 privileged mode */ -#define _SMU_BMPUPATD0_RFECA1_SHIFT 4 /**< Shift value for SMU_RFECA1 */ -#define _SMU_BMPUPATD0_RFECA1_MASK 0x10UL /**< Bit mask for SMU_RFECA1 */ -#define _SMU_BMPUPATD0_RFECA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RFECA1_DEFAULT (_SMU_BMPUPATD0_RFECA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_SEEXTDMA (0x1UL << 5) /**< SEEXTDMA privileged mode */ -#define _SMU_BMPUPATD0_SEEXTDMA_SHIFT 5 /**< Shift value for SMU_SEEXTDMA */ -#define _SMU_BMPUPATD0_SEEXTDMA_MASK 0x20UL /**< Bit mask for SMU_SEEXTDMA */ -#define _SMU_BMPUPATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUPATD0_SEEXTDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define _SMU_BMPUPATD0_RESETVALUE 0x0000003FUL /**< Default value for SMU_BMPUPATD0 */ +#define _SMU_BMPUPATD0_MASK 0x0000003FUL /**< Mask for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ +#define _SMU_BMPUPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES_DEFAULT (_SMU_BMPUPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */ +#define _SMU_BMPUPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA_DEFAULT (_SMU_BMPUPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA0 (0x1UL << 3) /**< RFECA0 privileged mode */ +#define _SMU_BMPUPATD0_RFECA0_SHIFT 3 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUPATD0_RFECA0_MASK 0x8UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUPATD0_RFECA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA0_DEFAULT (_SMU_BMPUPATD0_RFECA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA1 (0x1UL << 4) /**< RFECA1 privileged mode */ +#define _SMU_BMPUPATD0_RFECA1_SHIFT 4 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUPATD0_RFECA1_MASK 0x10UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUPATD0_RFECA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA1_DEFAULT (_SMU_BMPUPATD0_RFECA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_SEEXTDMA (0x1UL << 5) /**< SEEXTDMA privileged mode */ +#define _SMU_BMPUPATD0_SEEXTDMA_SHIFT 5 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUPATD0_SEEXTDMA_MASK 0x20UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUPATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUPATD0_SEEXTDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ /* Bit fields for SMU BMPUSATD0 */ -#define _SMU_BMPUSATD0_RESETVALUE 0x0000003FUL /**< Default value for SMU_BMPUSATD0 */ -#define _SMU_BMPUSATD0_MASK 0x0000003FUL /**< Mask for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOAES (0x1UL << 0) /**< RADIOAES DMA secure mode */ -#define _SMU_BMPUSATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ -#define _SMU_BMPUSATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_BMPUSATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOAES_DEFAULT (_SMU_BMPUSATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager secure mode */ -#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_LDMA (0x1UL << 2) /**< MCU LDMA secure mode */ -#define _SMU_BMPUSATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ -#define _SMU_BMPUSATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ -#define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_LDMA_DEFAULT (_SMU_BMPUSATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RFECA0 (0x1UL << 3) /**< RFECA0 secure mode */ -#define _SMU_BMPUSATD0_RFECA0_SHIFT 3 /**< Shift value for SMU_RFECA0 */ -#define _SMU_BMPUSATD0_RFECA0_MASK 0x8UL /**< Bit mask for SMU_RFECA0 */ -#define _SMU_BMPUSATD0_RFECA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RFECA0_DEFAULT (_SMU_BMPUSATD0_RFECA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RFECA1 (0x1UL << 4) /**< RFECA1 secure mode */ -#define _SMU_BMPUSATD0_RFECA1_SHIFT 4 /**< Shift value for SMU_RFECA1 */ -#define _SMU_BMPUSATD0_RFECA1_MASK 0x10UL /**< Bit mask for SMU_RFECA1 */ -#define _SMU_BMPUSATD0_RFECA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RFECA1_DEFAULT (_SMU_BMPUSATD0_RFECA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_SEEXTDMA (0x1UL << 5) /**< SEEXTDMA secure mode */ -#define _SMU_BMPUSATD0_SEEXTDMA_SHIFT 5 /**< Shift value for SMU_SEEXTDMA */ -#define _SMU_BMPUSATD0_SEEXTDMA_MASK 0x20UL /**< Bit mask for SMU_SEEXTDMA */ -#define _SMU_BMPUSATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_SEEXTDMA_DEFAULT (_SMU_BMPUSATD0_SEEXTDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define _SMU_BMPUSATD0_RESETVALUE 0x0000003FUL /**< Default value for SMU_BMPUSATD0 */ +#define _SMU_BMPUSATD0_MASK 0x0000003FUL /**< Mask for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES (0x1UL << 0) /**< RADIOAES DMA secure mode */ +#define _SMU_BMPUSATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES_DEFAULT (_SMU_BMPUSATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager secure mode */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA (0x1UL << 2) /**< MCU LDMA secure mode */ +#define _SMU_BMPUSATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA_DEFAULT (_SMU_BMPUSATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA0 (0x1UL << 3) /**< RFECA0 secure mode */ +#define _SMU_BMPUSATD0_RFECA0_SHIFT 3 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUSATD0_RFECA0_MASK 0x8UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUSATD0_RFECA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA0_DEFAULT (_SMU_BMPUSATD0_RFECA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA1 (0x1UL << 4) /**< RFECA1 secure mode */ +#define _SMU_BMPUSATD0_RFECA1_SHIFT 4 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUSATD0_RFECA1_MASK 0x10UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUSATD0_RFECA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA1_DEFAULT (_SMU_BMPUSATD0_RFECA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_SEEXTDMA (0x1UL << 5) /**< SEEXTDMA secure mode */ +#define _SMU_BMPUSATD0_SEEXTDMA_SHIFT 5 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUSATD0_SEEXTDMA_MASK 0x20UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUSATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_SEEXTDMA_DEFAULT (_SMU_BMPUSATD0_SEEXTDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ /* Bit fields for SMU BMPUFS */ -#define _SMU_BMPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFS */ -#define _SMU_BMPUFS_MASK 0x000000FFUL /**< Mask for SMU_BMPUFS */ -#define _SMU_BMPUFS_BMPUFSMASTERID_SHIFT 0 /**< Shift value for SMU_BMPUFSMASTERID */ -#define _SMU_BMPUFS_BMPUFSMASTERID_MASK 0xFFUL /**< Bit mask for SMU_BMPUFSMASTERID */ -#define _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFS */ -#define SMU_BMPUFS_BMPUFSMASTERID_DEFAULT (_SMU_BMPUFS_BMPUFSMASTERID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFS */ +#define _SMU_BMPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFS */ +#define _SMU_BMPUFS_MASK 0x000000FFUL /**< Mask for SMU_BMPUFS */ +#define _SMU_BMPUFS_BMPUFSMASTERID_SHIFT 0 /**< Shift value for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_MASK 0xFFUL /**< Bit mask for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFS */ +#define SMU_BMPUFS_BMPUFSMASTERID_DEFAULT (_SMU_BMPUFS_BMPUFSMASTERID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFS */ /* Bit fields for SMU BMPUFSADDR */ -#define _SMU_BMPUFSADDR_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFSADDR */ -#define _SMU_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Mask for SMU_BMPUFSADDR */ -#define _SMU_BMPUFSADDR_BMPUFSADDR_SHIFT 0 /**< Shift value for SMU_BMPUFSADDR */ -#define _SMU_BMPUFSADDR_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_BMPUFSADDR */ -#define _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFSADDR */ -#define SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT (_SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_SHIFT 0 /**< Shift value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFSADDR */ +#define SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT (_SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFSADDR */ /* Bit fields for SMU ESAURTYPES0 */ -#define _SMU_ESAURTYPES0_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES0 */ -#define _SMU_ESAURTYPES0_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES0 */ -#define SMU_ESAURTYPES0_ESAUR3NS (0x1UL << 12) /**< Region 3 Non-Secure */ -#define _SMU_ESAURTYPES0_ESAUR3NS_SHIFT 12 /**< Shift value for SMU_ESAUR3NS */ -#define _SMU_ESAURTYPES0_ESAUR3NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR3NS */ -#define _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES0 */ -#define SMU_ESAURTYPES0_ESAUR3NS_DEFAULT (_SMU_ESAURTYPES0_ESAUR3NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS (0x1UL << 12) /**< Region 3 Non-Secure */ +#define _SMU_ESAURTYPES0_ESAUR3NS_SHIFT 12 /**< Shift value for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS_DEFAULT (_SMU_ESAURTYPES0_ESAUR3NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES0 */ /* Bit fields for SMU ESAURTYPES1 */ -#define _SMU_ESAURTYPES1_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES1 */ -#define _SMU_ESAURTYPES1_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES1 */ -#define SMU_ESAURTYPES1_ESAUR11NS (0x1UL << 12) /**< Region 11 Non-Secure */ -#define _SMU_ESAURTYPES1_ESAUR11NS_SHIFT 12 /**< Shift value for SMU_ESAUR11NS */ -#define _SMU_ESAURTYPES1_ESAUR11NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR11NS */ -#define _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES1 */ -#define SMU_ESAURTYPES1_ESAUR11NS_DEFAULT (_SMU_ESAURTYPES1_ESAUR11NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS (0x1UL << 12) /**< Region 11 Non-Secure */ +#define _SMU_ESAURTYPES1_ESAUR11NS_SHIFT 12 /**< Shift value for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS_DEFAULT (_SMU_ESAURTYPES1_ESAUR11NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES1 */ /* Bit fields for SMU ESAUMRB01 */ -#define _SMU_ESAUMRB01_RESETVALUE 0x0A000000UL /**< Default value for SMU_ESAUMRB01 */ -#define _SMU_ESAUMRB01_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB01 */ -#define _SMU_ESAUMRB01_ESAUMRB01_SHIFT 12 /**< Shift value for SMU_ESAUMRB01 */ -#define _SMU_ESAUMRB01_ESAUMRB01_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB01 */ -#define _SMU_ESAUMRB01_ESAUMRB01_DEFAULT 0x0000A000UL /**< Mode DEFAULT for SMU_ESAUMRB01 */ -#define SMU_ESAUMRB01_ESAUMRB01_DEFAULT (_SMU_ESAUMRB01_ESAUMRB01_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_RESETVALUE 0x0A000000UL /**< Default value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_SHIFT 12 /**< Shift value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_DEFAULT 0x0000A000UL /**< Mode DEFAULT for SMU_ESAUMRB01 */ +#define SMU_ESAUMRB01_ESAUMRB01_DEFAULT (_SMU_ESAUMRB01_ESAUMRB01_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB01 */ /* Bit fields for SMU ESAUMRB12 */ -#define _SMU_ESAUMRB12_RESETVALUE 0x0C000000UL /**< Default value for SMU_ESAUMRB12 */ -#define _SMU_ESAUMRB12_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB12 */ -#define _SMU_ESAUMRB12_ESAUMRB12_SHIFT 12 /**< Shift value for SMU_ESAUMRB12 */ -#define _SMU_ESAUMRB12_ESAUMRB12_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB12 */ -#define _SMU_ESAUMRB12_ESAUMRB12_DEFAULT 0x0000C000UL /**< Mode DEFAULT for SMU_ESAUMRB12 */ -#define SMU_ESAUMRB12_ESAUMRB12_DEFAULT (_SMU_ESAUMRB12_ESAUMRB12_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_RESETVALUE 0x0C000000UL /**< Default value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_SHIFT 12 /**< Shift value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_DEFAULT 0x0000C000UL /**< Mode DEFAULT for SMU_ESAUMRB12 */ +#define SMU_ESAUMRB12_ESAUMRB12_DEFAULT (_SMU_ESAUMRB12_ESAUMRB12_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB12 */ /* Bit fields for SMU ESAUMRB45 */ -#define _SMU_ESAUMRB45_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB45 */ -#define _SMU_ESAUMRB45_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB45 */ -#define _SMU_ESAUMRB45_ESAUMRB45_SHIFT 12 /**< Shift value for SMU_ESAUMRB45 */ -#define _SMU_ESAUMRB45_ESAUMRB45_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB45 */ -#define _SMU_ESAUMRB45_ESAUMRB45_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB45 */ -#define SMU_ESAUMRB45_ESAUMRB45_DEFAULT (_SMU_ESAUMRB45_ESAUMRB45_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_SHIFT 12 /**< Shift value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB45 */ +#define SMU_ESAUMRB45_ESAUMRB45_DEFAULT (_SMU_ESAUMRB45_ESAUMRB45_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB45 */ /* Bit fields for SMU ESAUMRB56 */ -#define _SMU_ESAUMRB56_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB56 */ -#define _SMU_ESAUMRB56_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB56 */ -#define _SMU_ESAUMRB56_ESAUMRB56_SHIFT 12 /**< Shift value for SMU_ESAUMRB56 */ -#define _SMU_ESAUMRB56_ESAUMRB56_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB56 */ -#define _SMU_ESAUMRB56_ESAUMRB56_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB56 */ -#define SMU_ESAUMRB56_ESAUMRB56_DEFAULT (_SMU_ESAUMRB56_ESAUMRB56_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_SHIFT 12 /**< Shift value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB56 */ +#define SMU_ESAUMRB56_ESAUMRB56_DEFAULT (_SMU_ESAUMRB56_ESAUMRB56_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB56 */ /** @} End of group EFR32SG23_SMU_BitFields */ /** @} End of group EFR32SG23_SMU */ @@ -1022,67 +1020,66 @@ typedef struct *****************************************************************************/ /** SMU_CFGNS Register Declaration. */ -typedef struct -{ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t NSSTATUS; /**< Status Register */ - __IOM uint32_t NSLOCK; /**< Lock Register */ - __IOM uint32_t NSIF; /**< Interrupt Flag Register */ - __IOM uint32_t NSIEN; /**< Interrupt Enable Register */ - uint32_t RESERVED1[3U]; /**< Reserved for future use */ - uint32_t RESERVED2[8U]; /**< Reserved for future use */ - __IOM uint32_t PPUNSPATD0; /**< Privileged Access */ - __IOM uint32_t PPUNSPATD1; /**< Privileged Access */ - uint32_t RESERVED3[62U]; /**< Reserved for future use */ - __IM uint32_t PPUNSFS; /**< Fault Status */ - uint32_t RESERVED4[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUNSPATD0; /**< Privileged Attribute */ - uint32_t RESERVED5[63U]; /**< Reserved for future use */ - uint32_t RESERVED6[876U]; /**< Reserved for future use */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - __IM uint32_t NSSTATUS_SET; /**< Status Register */ - __IOM uint32_t NSLOCK_SET; /**< Lock Register */ - __IOM uint32_t NSIF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t NSIEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED8[3U]; /**< Reserved for future use */ - uint32_t RESERVED9[8U]; /**< Reserved for future use */ - __IOM uint32_t PPUNSPATD0_SET; /**< Privileged Access */ - __IOM uint32_t PPUNSPATD1_SET; /**< Privileged Access */ - uint32_t RESERVED10[62U]; /**< Reserved for future use */ - __IM uint32_t PPUNSFS_SET; /**< Fault Status */ - uint32_t RESERVED11[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUNSPATD0_SET; /**< Privileged Attribute */ - uint32_t RESERVED12[63U]; /**< Reserved for future use */ - uint32_t RESERVED13[876U]; /**< Reserved for future use */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - __IM uint32_t NSSTATUS_CLR; /**< Status Register */ - __IOM uint32_t NSLOCK_CLR; /**< Lock Register */ - __IOM uint32_t NSIF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t NSIEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED15[3U]; /**< Reserved for future use */ - uint32_t RESERVED16[8U]; /**< Reserved for future use */ - __IOM uint32_t PPUNSPATD0_CLR; /**< Privileged Access */ - __IOM uint32_t PPUNSPATD1_CLR; /**< Privileged Access */ - uint32_t RESERVED17[62U]; /**< Reserved for future use */ - __IM uint32_t PPUNSFS_CLR; /**< Fault Status */ - uint32_t RESERVED18[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUNSPATD0_CLR; /**< Privileged Attribute */ - uint32_t RESERVED19[63U]; /**< Reserved for future use */ - uint32_t RESERVED20[876U]; /**< Reserved for future use */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - __IM uint32_t NSSTATUS_TGL; /**< Status Register */ - __IOM uint32_t NSLOCK_TGL; /**< Lock Register */ - __IOM uint32_t NSIF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t NSIEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED22[3U]; /**< Reserved for future use */ - uint32_t RESERVED23[8U]; /**< Reserved for future use */ - __IOM uint32_t PPUNSPATD0_TGL; /**< Privileged Access */ - __IOM uint32_t PPUNSPATD1_TGL; /**< Privileged Access */ - uint32_t RESERVED24[62U]; /**< Reserved for future use */ - __IM uint32_t PPUNSFS_TGL; /**< Fault Status */ - uint32_t RESERVED25[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUNSPATD0_TGL; /**< Privileged Attribute */ - uint32_t RESERVED26[63U]; /**< Reserved for future use */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS; /**< Status Register */ + __IOM uint32_t NSLOCK; /**< Lock Register */ + __IOM uint32_t NSIF; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN; /**< Interrupt Enable Register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1; /**< Privileged Access */ + uint32_t RESERVED3[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS; /**< Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0; /**< Privileged Attribute */ + uint32_t RESERVED5[63U]; /**< Reserved for future use */ + uint32_t RESERVED6[876U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_SET; /**< Status Register */ + __IOM uint32_t NSLOCK_SET; /**< Lock Register */ + __IOM uint32_t NSIF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED8[3U]; /**< Reserved for future use */ + uint32_t RESERVED9[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_SET; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_SET; /**< Privileged Access */ + uint32_t RESERVED10[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_SET; /**< Fault Status */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_SET; /**< Privileged Attribute */ + uint32_t RESERVED12[63U]; /**< Reserved for future use */ + uint32_t RESERVED13[876U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_CLR; /**< Status Register */ + __IOM uint32_t NSLOCK_CLR; /**< Lock Register */ + __IOM uint32_t NSIF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + uint32_t RESERVED16[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_CLR; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_CLR; /**< Privileged Access */ + uint32_t RESERVED17[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_CLR; /**< Fault Status */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_CLR; /**< Privileged Attribute */ + uint32_t RESERVED19[63U]; /**< Reserved for future use */ + uint32_t RESERVED20[876U]; /**< Reserved for future use */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_TGL; /**< Status Register */ + __IOM uint32_t NSLOCK_TGL; /**< Lock Register */ + __IOM uint32_t NSIF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + uint32_t RESERVED23[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_TGL; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_TGL; /**< Privileged Access */ + uint32_t RESERVED24[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_TGL; /**< Fault Status */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_TGL; /**< Privileged Attribute */ + uint32_t RESERVED26[63U]; /**< Reserved for future use */ } SMU_CFGNS_TypeDef; /** @} End of group EFR32SG23_SMU_CFGNS */ @@ -1094,390 +1091,390 @@ typedef struct *****************************************************************************/ /* Bit fields for SMU NSSTATUS */ -#define _SMU_NSSTATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_NSSTATUS */ -#define _SMU_NSSTATUS_MASK 0x00000001UL /**< Mask for SMU_NSSTATUS */ -#define SMU_NSSTATUS_SMUNSLOCK (0x1UL << 0) /**< SMUNS Lock */ -#define _SMU_NSSTATUS_SMUNSLOCK_SHIFT 0 /**< Shift value for SMU_SMUNSLOCK */ -#define _SMU_NSSTATUS_SMUNSLOCK_MASK 0x1UL /**< Bit mask for SMU_SMUNSLOCK */ -#define _SMU_NSSTATUS_SMUNSLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSSTATUS */ -#define _SMU_NSSTATUS_SMUNSLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_NSSTATUS */ -#define _SMU_NSSTATUS_SMUNSLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_NSSTATUS */ -#define SMU_NSSTATUS_SMUNSLOCK_DEFAULT (_SMU_NSSTATUS_SMUNSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSSTATUS */ -#define SMU_NSSTATUS_SMUNSLOCK_UNLOCKED (_SMU_NSSTATUS_SMUNSLOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_NSSTATUS */ -#define SMU_NSSTATUS_SMUNSLOCK_LOCKED (_SMU_NSSTATUS_SMUNSLOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_MASK 0x00000001UL /**< Mask for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK (0x1UL << 0) /**< SMUNS Lock */ +#define _SMU_NSSTATUS_SMUNSLOCK_SHIFT 0 /**< Shift value for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_MASK 0x1UL /**< Bit mask for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_DEFAULT (_SMU_NSSTATUS_SMUNSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_UNLOCKED (_SMU_NSSTATUS_SMUNSLOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_LOCKED (_SMU_NSSTATUS_SMUNSLOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_NSSTATUS */ /* Bit fields for SMU NSLOCK */ -#define _SMU_NSLOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_NSLOCK */ -#define _SMU_NSLOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_NSLOCK */ -#define _SMU_NSLOCK_SMUNSLOCKKEY_SHIFT 0 /**< Shift value for SMU_SMUNSLOCKKEY */ -#define _SMU_NSLOCK_SMUNSLOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMUNSLOCKKEY */ -#define _SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSLOCK */ -#define _SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_NSLOCK */ -#define SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT (_SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSLOCK */ -#define SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK (_SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_NSLOCK */ +#define _SMU_NSLOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_NSLOCK */ +#define _SMU_NSLOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_SHIFT 0 /**< Shift value for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT (_SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK (_SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_NSLOCK */ /* Bit fields for SMU NSIF */ -#define _SMU_NSIF_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIF */ -#define _SMU_NSIF_MASK 0x00000005UL /**< Mask for SMU_NSIF */ -#define SMU_NSIF_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Flag */ -#define _SMU_NSIF_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ -#define _SMU_NSIF_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ -#define _SMU_NSIF_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ -#define SMU_NSIF_PPUNSPRIV_DEFAULT (_SMU_NSIF_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIF */ -#define SMU_NSIF_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Flag */ -#define _SMU_NSIF_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ -#define _SMU_NSIF_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ -#define _SMU_NSIF_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ -#define SMU_NSIF_PPUNSINST_DEFAULT (_SMU_NSIF_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIF */ +#define _SMU_NSIF_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIF */ +#define _SMU_NSIF_MASK 0x00000005UL /**< Mask for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Flag */ +#define _SMU_NSIF_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV_DEFAULT (_SMU_NSIF_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Flag */ +#define _SMU_NSIF_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST_DEFAULT (_SMU_NSIF_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIF */ /* Bit fields for SMU NSIEN */ -#define _SMU_NSIEN_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIEN */ -#define _SMU_NSIEN_MASK 0x00000005UL /**< Mask for SMU_NSIEN */ -#define SMU_NSIEN_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Enable */ -#define _SMU_NSIEN_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ -#define _SMU_NSIEN_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ -#define _SMU_NSIEN_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ -#define SMU_NSIEN_PPUNSPRIV_DEFAULT (_SMU_NSIEN_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIEN */ -#define SMU_NSIEN_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Enable */ -#define _SMU_NSIEN_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ -#define _SMU_NSIEN_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ -#define _SMU_NSIEN_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ -#define SMU_NSIEN_PPUNSINST_DEFAULT (_SMU_NSIEN_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIEN */ +#define _SMU_NSIEN_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIEN */ +#define _SMU_NSIEN_MASK 0x00000005UL /**< Mask for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Enable */ +#define _SMU_NSIEN_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV_DEFAULT (_SMU_NSIEN_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Enable */ +#define _SMU_NSIEN_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST_DEFAULT (_SMU_NSIEN_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIEN */ /* Bit fields for SMU PPUNSPATD0 */ -#define _SMU_PPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD0 */ -#define _SMU_PPUNSPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SCRATCHPAD (0x1UL << 0) /**< SCRATCHPAD Privileged Access */ -#define _SMU_PPUNSPATD0_SCRATCHPAD_SHIFT 0 /**< Shift value for SMU_SCRATCHPAD */ -#define _SMU_PPUNSPATD0_SCRATCHPAD_MASK 0x1UL /**< Bit mask for SMU_SCRATCHPAD */ -#define _SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT (_SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ -#define _SMU_PPUNSPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ -#define _SMU_PPUNSPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ -#define _SMU_PPUNSPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EMU_DEFAULT (_SMU_PPUNSPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ -#define _SMU_PPUNSPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ -#define _SMU_PPUNSPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ -#define _SMU_PPUNSPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_CMU_DEFAULT (_SMU_PPUNSPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */ -#define _SMU_PPUNSPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ -#define _SMU_PPUNSPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ -#define _SMU_PPUNSPATD0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_HFRCO0_DEFAULT (_SMU_PPUNSPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */ -#define _SMU_PPUNSPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ -#define _SMU_PPUNSPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ -#define _SMU_PPUNSPATD0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_FSRCO_DEFAULT (_SMU_PPUNSPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */ -#define _SMU_PPUNSPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ -#define _SMU_PPUNSPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ -#define _SMU_PPUNSPATD0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_DPLL0_DEFAULT (_SMU_PPUNSPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */ -#define _SMU_PPUNSPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ -#define _SMU_PPUNSPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ -#define _SMU_PPUNSPATD0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LFXO_DEFAULT (_SMU_PPUNSPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */ -#define _SMU_PPUNSPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ -#define _SMU_PPUNSPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ -#define _SMU_PPUNSPATD0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LFRCO_DEFAULT (_SMU_PPUNSPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */ -#define _SMU_PPUNSPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ -#define _SMU_PPUNSPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ -#define _SMU_PPUNSPATD0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_ULFRCO_DEFAULT (_SMU_PPUNSPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */ -#define _SMU_PPUNSPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ -#define _SMU_PPUNSPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ -#define _SMU_PPUNSPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_MSC_DEFAULT (_SMU_PPUNSPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */ -#define _SMU_PPUNSPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ -#define _SMU_PPUNSPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ -#define _SMU_PPUNSPATD0_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_ICACHE0_DEFAULT (_SMU_PPUNSPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */ -#define _SMU_PPUNSPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ -#define _SMU_PPUNSPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ -#define _SMU_PPUNSPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_PRS_DEFAULT (_SMU_PPUNSPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */ -#define _SMU_PPUNSPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ -#define _SMU_PPUNSPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ -#define _SMU_PPUNSPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_GPIO_DEFAULT (_SMU_PPUNSPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */ -#define _SMU_PPUNSPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ -#define _SMU_PPUNSPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ -#define _SMU_PPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LDMA_DEFAULT (_SMU_PPUNSPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */ -#define _SMU_PPUNSPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ -#define _SMU_PPUNSPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ -#define _SMU_PPUNSPATD0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LDMAXBAR_DEFAULT (_SMU_PPUNSPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ -#define _SMU_PPUNSPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ -#define _SMU_PPUNSPATD0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER0_DEFAULT (_SMU_PPUNSPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ -#define _SMU_PPUNSPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ -#define _SMU_PPUNSPATD0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER1_DEFAULT (_SMU_PPUNSPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ -#define _SMU_PPUNSPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ -#define _SMU_PPUNSPATD0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER2_DEFAULT (_SMU_PPUNSPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ -#define _SMU_PPUNSPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ -#define _SMU_PPUNSPATD0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER3_DEFAULT (_SMU_PPUNSPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ -#define _SMU_PPUNSPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ -#define _SMU_PPUNSPATD0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER4_DEFAULT (_SMU_PPUNSPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */ -#define _SMU_PPUNSPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ -#define _SMU_PPUNSPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ -#define _SMU_PPUNSPATD0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_USART0_DEFAULT (_SMU_PPUNSPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */ -#define _SMU_PPUNSPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ -#define _SMU_PPUNSPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ -#define _SMU_PPUNSPATD0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_BURTC_DEFAULT (_SMU_PPUNSPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */ -#define _SMU_PPUNSPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ -#define _SMU_PPUNSPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ -#define _SMU_PPUNSPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_I2C1_DEFAULT (_SMU_PPUNSPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Privileged Access */ -#define _SMU_PPUNSPATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ -#define _SMU_PPUNSPATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ -#define _SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */ -#define _SMU_PPUNSPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ -#define _SMU_PPUNSPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ -#define _SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */ -#define _SMU_PPUNSPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ -#define _SMU_PPUNSPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ -#define _SMU_PPUNSPATD0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSCFG_DEFAULT (_SMU_PPUNSPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */ -#define _SMU_PPUNSPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ -#define _SMU_PPUNSPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ -#define _SMU_PPUNSPATD0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_BURAM_DEFAULT (_SMU_PPUNSPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */ -#define _SMU_PPUNSPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ -#define _SMU_PPUNSPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ -#define _SMU_PPUNSPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_GPCRC_DEFAULT (_SMU_PPUNSPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */ -#define _SMU_PPUNSPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ -#define _SMU_PPUNSPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ -#define _SMU_PPUNSPATD0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_DCDC_DEFAULT (_SMU_PPUNSPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */ -#define _SMU_PPUNSPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ -#define _SMU_PPUNSPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ -#define _SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */ -#define _SMU_PPUNSPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ -#define _SMU_PPUNSPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ -#define _SMU_PPUNSPATD0_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EUSART1_DEFAULT (_SMU_PPUNSPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EUSART2 (0x1UL << 31) /**< EUSART2 Privileged Access */ -#define _SMU_PPUNSPATD0_EUSART2_SHIFT 31 /**< Shift value for SMU_EUSART2 */ -#define _SMU_PPUNSPATD0_EUSART2_MASK 0x80000000UL /**< Bit mask for SMU_EUSART2 */ -#define _SMU_PPUNSPATD0_EUSART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EUSART2_DEFAULT (_SMU_PPUNSPATD0_EUSART2_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SCRATCHPAD (0x1UL << 0) /**< SCRATCHPAD Privileged Access */ +#define _SMU_PPUNSPATD0_SCRATCHPAD_SHIFT 0 /**< Shift value for SMU_SCRATCHPAD */ +#define _SMU_PPUNSPATD0_SCRATCHPAD_MASK 0x1UL /**< Bit mask for SMU_SCRATCHPAD */ +#define _SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT (_SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUNSPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU_DEFAULT (_SMU_PPUNSPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUNSPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU_DEFAULT (_SMU_PPUNSPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUNSPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0_DEFAULT (_SMU_PPUNSPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */ +#define _SMU_PPUNSPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO_DEFAULT (_SMU_PPUNSPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */ +#define _SMU_PPUNSPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0_DEFAULT (_SMU_PPUNSPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */ +#define _SMU_PPUNSPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO_DEFAULT (_SMU_PPUNSPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO_DEFAULT (_SMU_PPUNSPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO_DEFAULT (_SMU_PPUNSPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */ +#define _SMU_PPUNSPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC_DEFAULT (_SMU_PPUNSPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUNSPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0_DEFAULT (_SMU_PPUNSPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */ +#define _SMU_PPUNSPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS_DEFAULT (_SMU_PPUNSPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */ +#define _SMU_PPUNSPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO_DEFAULT (_SMU_PPUNSPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */ +#define _SMU_PPUNSPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA_DEFAULT (_SMU_PPUNSPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUNSPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR_DEFAULT (_SMU_PPUNSPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0_DEFAULT (_SMU_PPUNSPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1_DEFAULT (_SMU_PPUNSPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2_DEFAULT (_SMU_PPUNSPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3_DEFAULT (_SMU_PPUNSPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4_DEFAULT (_SMU_PPUNSPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */ +#define _SMU_PPUNSPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUNSPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUNSPATD0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART0_DEFAULT (_SMU_PPUNSPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */ +#define _SMU_PPUNSPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC_DEFAULT (_SMU_PPUNSPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */ +#define _SMU_PPUNSPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUNSPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUNSPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_I2C1_DEFAULT (_SMU_PPUNSPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Privileged Access */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG_DEFAULT (_SMU_PPUNSPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */ +#define _SMU_PPUNSPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUNSPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUNSPATD0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURAM_DEFAULT (_SMU_PPUNSPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */ +#define _SMU_PPUNSPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUNSPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUNSPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPCRC_DEFAULT (_SMU_PPUNSPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */ +#define _SMU_PPUNSPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUNSPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUNSPATD0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DCDC_DEFAULT (_SMU_PPUNSPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */ +#define _SMU_PPUNSPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUNSPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */ +#define _SMU_PPUNSPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUNSPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUNSPATD0_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EUSART1_DEFAULT (_SMU_PPUNSPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EUSART2 (0x1UL << 31) /**< EUSART2 Privileged Access */ +#define _SMU_PPUNSPATD0_EUSART2_SHIFT 31 /**< Shift value for SMU_EUSART2 */ +#define _SMU_PPUNSPATD0_EUSART2_MASK 0x80000000UL /**< Bit mask for SMU_EUSART2 */ +#define _SMU_PPUNSPATD0_EUSART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EUSART2_DEFAULT (_SMU_PPUNSPATD0_EUSART2_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ /* Bit fields for SMU PPUNSPATD1 */ -#define _SMU_PPUNSPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD1 */ -#define _SMU_PPUNSPATD1_MASK 0x01FFFFFFUL /**< Mask for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SYSRTC (0x1UL << 0) /**< SYSRTC Privileged Access */ -#define _SMU_PPUNSPATD1_SYSRTC_SHIFT 0 /**< Shift value for SMU_SYSRTC */ -#define _SMU_PPUNSPATD1_SYSRTC_MASK 0x1UL /**< Bit mask for SMU_SYSRTC */ -#define _SMU_PPUNSPATD1_SYSRTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SYSRTC_DEFAULT (_SMU_PPUNSPATD1_SYSRTC_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LCD (0x1UL << 1) /**< LCD Privileged Access */ -#define _SMU_PPUNSPATD1_LCD_SHIFT 1 /**< Shift value for SMU_LCD */ -#define _SMU_PPUNSPATD1_LCD_MASK 0x2UL /**< Bit mask for SMU_LCD */ -#define _SMU_PPUNSPATD1_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LCD_DEFAULT (_SMU_PPUNSPATD1_LCD_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_KEYSCAN (0x1UL << 2) /**< KEYSCAN Privileged Access */ -#define _SMU_PPUNSPATD1_KEYSCAN_SHIFT 2 /**< Shift value for SMU_KEYSCAN */ -#define _SMU_PPUNSPATD1_KEYSCAN_MASK 0x4UL /**< Bit mask for SMU_KEYSCAN */ -#define _SMU_PPUNSPATD1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_KEYSCAN_DEFAULT (_SMU_PPUNSPATD1_KEYSCAN_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_DMEM (0x1UL << 3) /**< DMEM Privileged Access */ -#define _SMU_PPUNSPATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ -#define _SMU_PPUNSPATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ -#define _SMU_PPUNSPATD1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_DMEM_DEFAULT (_SMU_PPUNSPATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LCDRF (0x1UL << 4) /**< LCDRF Privileged Access */ -#define _SMU_PPUNSPATD1_LCDRF_SHIFT 4 /**< Shift value for SMU_LCDRF */ -#define _SMU_PPUNSPATD1_LCDRF_MASK 0x10UL /**< Bit mask for SMU_LCDRF */ -#define _SMU_PPUNSPATD1_LCDRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LCDRF_DEFAULT (_SMU_PPUNSPATD1_LCDRF_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_PFMXPPRF (0x1UL << 5) /**< PFMXPPRF Privileged Access */ -#define _SMU_PPUNSPATD1_PFMXPPRF_SHIFT 5 /**< Shift value for SMU_PFMXPPRF */ -#define _SMU_PPUNSPATD1_PFMXPPRF_MASK 0x20UL /**< Bit mask for SMU_PFMXPPRF */ -#define _SMU_PPUNSPATD1_PFMXPPRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_PFMXPPRF_DEFAULT (_SMU_PPUNSPATD1_PFMXPPRF_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_RADIOAES (0x1UL << 6) /**< RADIOAES Privileged Access */ -#define _SMU_PPUNSPATD1_RADIOAES_SHIFT 6 /**< Shift value for SMU_RADIOAES */ -#define _SMU_PPUNSPATD1_RADIOAES_MASK 0x40UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_PPUNSPATD1_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_RADIOAES_DEFAULT (_SMU_PPUNSPATD1_RADIOAES_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SMU (0x1UL << 7) /**< SMU Privileged Access */ -#define _SMU_PPUNSPATD1_SMU_SHIFT 7 /**< Shift value for SMU_SMU */ -#define _SMU_PPUNSPATD1_SMU_MASK 0x80UL /**< Bit mask for SMU_SMU */ -#define _SMU_PPUNSPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SMU_DEFAULT (_SMU_PPUNSPATD1_SMU_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SMUCFGNS (0x1UL << 8) /**< SMUCFGNS Privileged Access */ -#define _SMU_PPUNSPATD1_SMUCFGNS_SHIFT 8 /**< Shift value for SMU_SMUCFGNS */ -#define _SMU_PPUNSPATD1_SMUCFGNS_MASK 0x100UL /**< Bit mask for SMU_SMUCFGNS */ -#define _SMU_PPUNSPATD1_SMUCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SMUCFGNS_DEFAULT (_SMU_PPUNSPATD1_SMUCFGNS_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LETIMER0 (0x1UL << 9) /**< LETIMER0 Privileged Access */ -#define _SMU_PPUNSPATD1_LETIMER0_SHIFT 9 /**< Shift value for SMU_LETIMER0 */ -#define _SMU_PPUNSPATD1_LETIMER0_MASK 0x200UL /**< Bit mask for SMU_LETIMER0 */ -#define _SMU_PPUNSPATD1_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LETIMER0_DEFAULT (_SMU_PPUNSPATD1_LETIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_IADC0 (0x1UL << 10) /**< IADC0 Privileged Access */ -#define _SMU_PPUNSPATD1_IADC0_SHIFT 10 /**< Shift value for SMU_IADC0 */ -#define _SMU_PPUNSPATD1_IADC0_MASK 0x400UL /**< Bit mask for SMU_IADC0 */ -#define _SMU_PPUNSPATD1_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_IADC0_DEFAULT (_SMU_PPUNSPATD1_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_ACMP0 (0x1UL << 11) /**< ACMP0 Privileged Access */ -#define _SMU_PPUNSPATD1_ACMP0_SHIFT 11 /**< Shift value for SMU_ACMP0 */ -#define _SMU_PPUNSPATD1_ACMP0_MASK 0x800UL /**< Bit mask for SMU_ACMP0 */ -#define _SMU_PPUNSPATD1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_ACMP0_DEFAULT (_SMU_PPUNSPATD1_ACMP0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_ACMP1 (0x1UL << 12) /**< ACMP1 Privileged Access */ -#define _SMU_PPUNSPATD1_ACMP1_SHIFT 12 /**< Shift value for SMU_ACMP1 */ -#define _SMU_PPUNSPATD1_ACMP1_MASK 0x1000UL /**< Bit mask for SMU_ACMP1 */ -#define _SMU_PPUNSPATD1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_ACMP1_DEFAULT (_SMU_PPUNSPATD1_ACMP1_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_AMUXCP0 (0x1UL << 13) /**< AMUXCP0 Privileged Access */ -#define _SMU_PPUNSPATD1_AMUXCP0_SHIFT 13 /**< Shift value for SMU_AMUXCP0 */ -#define _SMU_PPUNSPATD1_AMUXCP0_MASK 0x2000UL /**< Bit mask for SMU_AMUXCP0 */ -#define _SMU_PPUNSPATD1_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_AMUXCP0_DEFAULT (_SMU_PPUNSPATD1_AMUXCP0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_VDAC0 (0x1UL << 14) /**< VDAC0 Privileged Access */ -#define _SMU_PPUNSPATD1_VDAC0_SHIFT 14 /**< Shift value for SMU_VDAC0 */ -#define _SMU_PPUNSPATD1_VDAC0_MASK 0x4000UL /**< Bit mask for SMU_VDAC0 */ -#define _SMU_PPUNSPATD1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_VDAC0_DEFAULT (_SMU_PPUNSPATD1_VDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_PCNT (0x1UL << 15) /**< PCNT Privileged Access */ -#define _SMU_PPUNSPATD1_PCNT_SHIFT 15 /**< Shift value for SMU_PCNT */ -#define _SMU_PPUNSPATD1_PCNT_MASK 0x8000UL /**< Bit mask for SMU_PCNT */ -#define _SMU_PPUNSPATD1_PCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_PCNT_DEFAULT (_SMU_PPUNSPATD1_PCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LESENSE (0x1UL << 16) /**< LESENSE Privileged Access */ -#define _SMU_PPUNSPATD1_LESENSE_SHIFT 16 /**< Shift value for SMU_LESENSE */ -#define _SMU_PPUNSPATD1_LESENSE_MASK 0x10000UL /**< Bit mask for SMU_LESENSE */ -#define _SMU_PPUNSPATD1_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LESENSE_DEFAULT (_SMU_PPUNSPATD1_LESENSE_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_HFRCO1 (0x1UL << 17) /**< HFRCO1 Privileged Access */ -#define _SMU_PPUNSPATD1_HFRCO1_SHIFT 17 /**< Shift value for SMU_HFRCO1 */ -#define _SMU_PPUNSPATD1_HFRCO1_MASK 0x20000UL /**< Bit mask for SMU_HFRCO1 */ -#define _SMU_PPUNSPATD1_HFRCO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_HFRCO1_DEFAULT (_SMU_PPUNSPATD1_HFRCO1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_HFXO0 (0x1UL << 18) /**< HFXO0 Privileged Access */ -#define _SMU_PPUNSPATD1_HFXO0_SHIFT 18 /**< Shift value for SMU_HFXO0 */ -#define _SMU_PPUNSPATD1_HFXO0_MASK 0x40000UL /**< Bit mask for SMU_HFXO0 */ -#define _SMU_PPUNSPATD1_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_HFXO0_DEFAULT (_SMU_PPUNSPATD1_HFXO0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_I2C0 (0x1UL << 19) /**< I2C0 Privileged Access */ -#define _SMU_PPUNSPATD1_I2C0_SHIFT 19 /**< Shift value for SMU_I2C0 */ -#define _SMU_PPUNSPATD1_I2C0_MASK 0x80000UL /**< Bit mask for SMU_I2C0 */ -#define _SMU_PPUNSPATD1_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_I2C0_DEFAULT (_SMU_PPUNSPATD1_I2C0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_WDOG0 (0x1UL << 20) /**< WDOG0 Privileged Access */ -#define _SMU_PPUNSPATD1_WDOG0_SHIFT 20 /**< Shift value for SMU_WDOG0 */ -#define _SMU_PPUNSPATD1_WDOG0_MASK 0x100000UL /**< Bit mask for SMU_WDOG0 */ -#define _SMU_PPUNSPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_WDOG0_DEFAULT (_SMU_PPUNSPATD1_WDOG0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_WDOG1 (0x1UL << 21) /**< WDOG1 Privileged Access */ -#define _SMU_PPUNSPATD1_WDOG1_SHIFT 21 /**< Shift value for SMU_WDOG1 */ -#define _SMU_PPUNSPATD1_WDOG1_MASK 0x200000UL /**< Bit mask for SMU_WDOG1 */ -#define _SMU_PPUNSPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_WDOG1_DEFAULT (_SMU_PPUNSPATD1_WDOG1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_EUSART0 (0x1UL << 22) /**< EUSART0 Privileged Access */ -#define _SMU_PPUNSPATD1_EUSART0_SHIFT 22 /**< Shift value for SMU_EUSART0 */ -#define _SMU_PPUNSPATD1_EUSART0_MASK 0x400000UL /**< Bit mask for SMU_EUSART0 */ -#define _SMU_PPUNSPATD1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_EUSART0_DEFAULT (_SMU_PPUNSPATD1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SEMAILBOX (0x1UL << 23) /**< SEMAILBOX Privileged Access */ -#define _SMU_PPUNSPATD1_SEMAILBOX_SHIFT 23 /**< Shift value for SMU_SEMAILBOX */ -#define _SMU_PPUNSPATD1_SEMAILBOX_MASK 0x800000UL /**< Bit mask for SMU_SEMAILBOX */ -#define _SMU_PPUNSPATD1_SEMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SEMAILBOX_DEFAULT (_SMU_PPUNSPATD1_SEMAILBOX_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_AHBRADIO (0x1UL << 24) /**< AHBRADIO Privileged Access */ -#define _SMU_PPUNSPATD1_AHBRADIO_SHIFT 24 /**< Shift value for SMU_AHBRADIO */ -#define _SMU_PPUNSPATD1_AHBRADIO_MASK 0x1000000UL /**< Bit mask for SMU_AHBRADIO */ -#define _SMU_PPUNSPATD1_AHBRADIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_AHBRADIO_DEFAULT (_SMU_PPUNSPATD1_AHBRADIO_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_MASK 0x01FFFFFFUL /**< Mask for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SYSRTC (0x1UL << 0) /**< SYSRTC Privileged Access */ +#define _SMU_PPUNSPATD1_SYSRTC_SHIFT 0 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUNSPATD1_SYSRTC_MASK 0x1UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUNSPATD1_SYSRTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SYSRTC_DEFAULT (_SMU_PPUNSPATD1_SYSRTC_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LCD (0x1UL << 1) /**< LCD Privileged Access */ +#define _SMU_PPUNSPATD1_LCD_SHIFT 1 /**< Shift value for SMU_LCD */ +#define _SMU_PPUNSPATD1_LCD_MASK 0x2UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUNSPATD1_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LCD_DEFAULT (_SMU_PPUNSPATD1_LCD_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_KEYSCAN (0x1UL << 2) /**< KEYSCAN Privileged Access */ +#define _SMU_PPUNSPATD1_KEYSCAN_SHIFT 2 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUNSPATD1_KEYSCAN_MASK 0x4UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUNSPATD1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_KEYSCAN_DEFAULT (_SMU_PPUNSPATD1_KEYSCAN_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DMEM (0x1UL << 3) /**< DMEM Privileged Access */ +#define _SMU_PPUNSPATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUNSPATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUNSPATD1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DMEM_DEFAULT (_SMU_PPUNSPATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LCDRF (0x1UL << 4) /**< LCDRF Privileged Access */ +#define _SMU_PPUNSPATD1_LCDRF_SHIFT 4 /**< Shift value for SMU_LCDRF */ +#define _SMU_PPUNSPATD1_LCDRF_MASK 0x10UL /**< Bit mask for SMU_LCDRF */ +#define _SMU_PPUNSPATD1_LCDRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LCDRF_DEFAULT (_SMU_PPUNSPATD1_LCDRF_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PFMXPPRF (0x1UL << 5) /**< PFMXPPRF Privileged Access */ +#define _SMU_PPUNSPATD1_PFMXPPRF_SHIFT 5 /**< Shift value for SMU_PFMXPPRF */ +#define _SMU_PPUNSPATD1_PFMXPPRF_MASK 0x20UL /**< Bit mask for SMU_PFMXPPRF */ +#define _SMU_PPUNSPATD1_PFMXPPRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PFMXPPRF_DEFAULT (_SMU_PPUNSPATD1_PFMXPPRF_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES (0x1UL << 6) /**< RADIOAES Privileged Access */ +#define _SMU_PPUNSPATD1_RADIOAES_SHIFT 6 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_MASK 0x40UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES_DEFAULT (_SMU_PPUNSPATD1_RADIOAES_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU (0x1UL << 7) /**< SMU Privileged Access */ +#define _SMU_PPUNSPATD1_SMU_SHIFT 7 /**< Shift value for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_MASK 0x80UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU_DEFAULT (_SMU_PPUNSPATD1_SMU_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS (0x1UL << 8) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUNSPATD1_SMUCFGNS_SHIFT 8 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_MASK 0x100UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS_DEFAULT (_SMU_PPUNSPATD1_SMUCFGNS_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0 (0x1UL << 9) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUNSPATD1_LETIMER0_SHIFT 9 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_MASK 0x200UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0_DEFAULT (_SMU_PPUNSPATD1_LETIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0 (0x1UL << 10) /**< IADC0 Privileged Access */ +#define _SMU_PPUNSPATD1_IADC0_SHIFT 10 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_MASK 0x400UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0_DEFAULT (_SMU_PPUNSPATD1_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP0 (0x1UL << 11) /**< ACMP0 Privileged Access */ +#define _SMU_PPUNSPATD1_ACMP0_SHIFT 11 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUNSPATD1_ACMP0_MASK 0x800UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUNSPATD1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP0_DEFAULT (_SMU_PPUNSPATD1_ACMP0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP1 (0x1UL << 12) /**< ACMP1 Privileged Access */ +#define _SMU_PPUNSPATD1_ACMP1_SHIFT 12 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUNSPATD1_ACMP1_MASK 0x1000UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUNSPATD1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP1_DEFAULT (_SMU_PPUNSPATD1_ACMP1_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0 (0x1UL << 13) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUNSPATD1_AMUXCP0_SHIFT 13 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_MASK 0x2000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0_DEFAULT (_SMU_PPUNSPATD1_AMUXCP0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC0 (0x1UL << 14) /**< VDAC0 Privileged Access */ +#define _SMU_PPUNSPATD1_VDAC0_SHIFT 14 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUNSPATD1_VDAC0_MASK 0x4000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUNSPATD1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC0_DEFAULT (_SMU_PPUNSPATD1_VDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PCNT (0x1UL << 15) /**< PCNT Privileged Access */ +#define _SMU_PPUNSPATD1_PCNT_SHIFT 15 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUNSPATD1_PCNT_MASK 0x8000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUNSPATD1_PCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PCNT_DEFAULT (_SMU_PPUNSPATD1_PCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LESENSE (0x1UL << 16) /**< LESENSE Privileged Access */ +#define _SMU_PPUNSPATD1_LESENSE_SHIFT 16 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUNSPATD1_LESENSE_MASK 0x10000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUNSPATD1_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LESENSE_DEFAULT (_SMU_PPUNSPATD1_LESENSE_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFRCO1 (0x1UL << 17) /**< HFRCO1 Privileged Access */ +#define _SMU_PPUNSPATD1_HFRCO1_SHIFT 17 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUNSPATD1_HFRCO1_MASK 0x20000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUNSPATD1_HFRCO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFRCO1_DEFAULT (_SMU_PPUNSPATD1_HFRCO1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFXO0 (0x1UL << 18) /**< HFXO0 Privileged Access */ +#define _SMU_PPUNSPATD1_HFXO0_SHIFT 18 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUNSPATD1_HFXO0_MASK 0x40000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUNSPATD1_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFXO0_DEFAULT (_SMU_PPUNSPATD1_HFXO0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0 (0x1UL << 19) /**< I2C0 Privileged Access */ +#define _SMU_PPUNSPATD1_I2C0_SHIFT 19 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_MASK 0x80000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0_DEFAULT (_SMU_PPUNSPATD1_I2C0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0 (0x1UL << 20) /**< WDOG0 Privileged Access */ +#define _SMU_PPUNSPATD1_WDOG0_SHIFT 20 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_MASK 0x100000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0_DEFAULT (_SMU_PPUNSPATD1_WDOG0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG1 (0x1UL << 21) /**< WDOG1 Privileged Access */ +#define _SMU_PPUNSPATD1_WDOG1_SHIFT 21 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUNSPATD1_WDOG1_MASK 0x200000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUNSPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG1_DEFAULT (_SMU_PPUNSPATD1_WDOG1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART0 (0x1UL << 22) /**< EUSART0 Privileged Access */ +#define _SMU_PPUNSPATD1_EUSART0_SHIFT 22 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUNSPATD1_EUSART0_MASK 0x400000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUNSPATD1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART0_DEFAULT (_SMU_PPUNSPATD1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SEMAILBOX (0x1UL << 23) /**< SEMAILBOX Privileged Access */ +#define _SMU_PPUNSPATD1_SEMAILBOX_SHIFT 23 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUNSPATD1_SEMAILBOX_MASK 0x800000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUNSPATD1_SEMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SEMAILBOX_DEFAULT (_SMU_PPUNSPATD1_SEMAILBOX_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AHBRADIO (0x1UL << 24) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUNSPATD1_AHBRADIO_SHIFT 24 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD1_AHBRADIO_MASK 0x1000000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD1_AHBRADIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AHBRADIO_DEFAULT (_SMU_PPUNSPATD1_AHBRADIO_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ /* Bit fields for SMU PPUNSFS */ -#define _SMU_PPUNSFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSFS */ -#define _SMU_PPUNSFS_MASK 0x000000FFUL /**< Mask for SMU_PPUNSFS */ -#define _SMU_PPUNSFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ -#define _SMU_PPUNSFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ -#define _SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSFS */ -#define SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_MASK 0x000000FFUL /**< Mask for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSFS */ +#define SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSFS */ /* Bit fields for SMU BMPUNSPATD0 */ -#define _SMU_BMPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUNSPATD0 */ -#define _SMU_BMPUNSPATD0_MASK 0x0000003FUL /**< Mask for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ -#define _SMU_BMPUNSPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ -#define _SMU_BMPUNSPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_BMPUNSPATD0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOAES_DEFAULT (_SMU_BMPUNSPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */ -#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */ -#define _SMU_BMPUNSPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ -#define _SMU_BMPUNSPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ -#define _SMU_BMPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_LDMA_DEFAULT (_SMU_BMPUNSPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RFECA0 (0x1UL << 3) /**< RFECA0 privileged mode */ -#define _SMU_BMPUNSPATD0_RFECA0_SHIFT 3 /**< Shift value for SMU_RFECA0 */ -#define _SMU_BMPUNSPATD0_RFECA0_MASK 0x8UL /**< Bit mask for SMU_RFECA0 */ -#define _SMU_BMPUNSPATD0_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RFECA0_DEFAULT (_SMU_BMPUNSPATD0_RFECA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RFECA1 (0x1UL << 4) /**< RFECA1 privileged mode */ -#define _SMU_BMPUNSPATD0_RFECA1_SHIFT 4 /**< Shift value for SMU_RFECA1 */ -#define _SMU_BMPUNSPATD0_RFECA1_MASK 0x10UL /**< Bit mask for SMU_RFECA1 */ -#define _SMU_BMPUNSPATD0_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RFECA1_DEFAULT (_SMU_BMPUNSPATD0_RFECA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_SEEXTDMA (0x1UL << 5) /**< SEEXTDMA privileged mode */ -#define _SMU_BMPUNSPATD0_SEEXTDMA_SHIFT 5 /**< Shift value for SMU_SEEXTDMA */ -#define _SMU_BMPUNSPATD0_SEEXTDMA_MASK 0x20UL /**< Bit mask for SMU_SEEXTDMA */ -#define _SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_MASK 0x0000003FUL /**< Mask for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ +#define _SMU_BMPUNSPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES_DEFAULT (_SMU_BMPUNSPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */ +#define _SMU_BMPUNSPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA_DEFAULT (_SMU_BMPUNSPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA0 (0x1UL << 3) /**< RFECA0 privileged mode */ +#define _SMU_BMPUNSPATD0_RFECA0_SHIFT 3 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUNSPATD0_RFECA0_MASK 0x8UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUNSPATD0_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA0_DEFAULT (_SMU_BMPUNSPATD0_RFECA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA1 (0x1UL << 4) /**< RFECA1 privileged mode */ +#define _SMU_BMPUNSPATD0_RFECA1_SHIFT 4 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUNSPATD0_RFECA1_MASK 0x10UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUNSPATD0_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA1_DEFAULT (_SMU_BMPUNSPATD0_RFECA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_SEEXTDMA (0x1UL << 5) /**< SEEXTDMA privileged mode */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_SHIFT 5 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_MASK 0x20UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ /** @} End of group EFR32SG23_SMU_CFGNS_BitFields */ /** @} End of group EFR32SG23_SMU_CFGNS */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_syscfg.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_syscfg.h index 06ae6e0bb8..90f0647a46 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32SG23 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_sysrtc.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_sysrtc.h index 3abf8a8a64..9ff304e6b9 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_sysrtc.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_SYSRTC_H #define EFR32SG23_SYSRTC_H - #define SYSRTC_HAS_SET_CLEAR /**************************************************************************//** @@ -43,103 +42,102 @@ *****************************************************************************/ /** SYSRTC Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP VERSION */ - __IOM uint32_t EN; /**< Module Enable Register */ - __IOM uint32_t SWRST; /**< Software Reset Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status register */ - __IOM uint32_t CNT; /**< Counter Value Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - uint32_t RESERVED2[3U]; /**< Reserved for future use */ - __IOM uint32_t GRP0_IF; /**< Group Interrupt Flags */ - __IOM uint32_t GRP0_IEN; /**< Group Interrupt Enables */ - __IOM uint32_t GRP0_CTRL; /**< Group Control Register */ - __IOM uint32_t GRP0_CMP0VALUE; /**< Compare 0 Value Register */ - __IOM uint32_t GRP0_CMP1VALUE; /**< Compare 1 Value Register */ - __IM uint32_t GRP0_CAP0VALUE; /**< Capture 0 Value Register */ - __IM uint32_t GRP0_SYNCBUSY; /**< Synchronization busy Register */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - uint32_t RESERVED5[7U]; /**< Reserved for future use */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - uint32_t RESERVED7[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP VERSION */ - __IOM uint32_t EN_SET; /**< Module Enable Register */ - __IOM uint32_t SWRST_SET; /**< Software Reset Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status register */ - __IOM uint32_t CNT_SET; /**< Counter Value Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - uint32_t RESERVED8[3U]; /**< Reserved for future use */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - uint32_t RESERVED10[3U]; /**< Reserved for future use */ - __IOM uint32_t GRP0_IF_SET; /**< Group Interrupt Flags */ - __IOM uint32_t GRP0_IEN_SET; /**< Group Interrupt Enables */ - __IOM uint32_t GRP0_CTRL_SET; /**< Group Control Register */ - __IOM uint32_t GRP0_CMP0VALUE_SET; /**< Compare 0 Value Register */ - __IOM uint32_t GRP0_CMP1VALUE_SET; /**< Compare 1 Value Register */ - __IM uint32_t GRP0_CAP0VALUE_SET; /**< Capture 0 Value Register */ - __IM uint32_t GRP0_SYNCBUSY_SET; /**< Synchronization busy Register */ - uint32_t RESERVED11[1U]; /**< Reserved for future use */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - uint32_t RESERVED13[7U]; /**< Reserved for future use */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - uint32_t RESERVED15[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP VERSION */ - __IOM uint32_t EN_CLR; /**< Module Enable Register */ - __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status register */ - __IOM uint32_t CNT_CLR; /**< Counter Value Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - uint32_t RESERVED16[3U]; /**< Reserved for future use */ - uint32_t RESERVED17[1U]; /**< Reserved for future use */ - uint32_t RESERVED18[3U]; /**< Reserved for future use */ - __IOM uint32_t GRP0_IF_CLR; /**< Group Interrupt Flags */ - __IOM uint32_t GRP0_IEN_CLR; /**< Group Interrupt Enables */ - __IOM uint32_t GRP0_CTRL_CLR; /**< Group Control Register */ - __IOM uint32_t GRP0_CMP0VALUE_CLR; /**< Compare 0 Value Register */ - __IOM uint32_t GRP0_CMP1VALUE_CLR; /**< Compare 1 Value Register */ - __IM uint32_t GRP0_CAP0VALUE_CLR; /**< Capture 0 Value Register */ - __IM uint32_t GRP0_SYNCBUSY_CLR; /**< Synchronization busy Register */ - uint32_t RESERVED19[1U]; /**< Reserved for future use */ - uint32_t RESERVED20[1U]; /**< Reserved for future use */ - uint32_t RESERVED21[7U]; /**< Reserved for future use */ - uint32_t RESERVED22[1U]; /**< Reserved for future use */ - uint32_t RESERVED23[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP VERSION */ - __IOM uint32_t EN_TGL; /**< Module Enable Register */ - __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status register */ - __IOM uint32_t CNT_TGL; /**< Counter Value Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - uint32_t RESERVED24[3U]; /**< Reserved for future use */ - uint32_t RESERVED25[1U]; /**< Reserved for future use */ - uint32_t RESERVED26[3U]; /**< Reserved for future use */ - __IOM uint32_t GRP0_IF_TGL; /**< Group Interrupt Flags */ - __IOM uint32_t GRP0_IEN_TGL; /**< Group Interrupt Enables */ - __IOM uint32_t GRP0_CTRL_TGL; /**< Group Control Register */ - __IOM uint32_t GRP0_CMP0VALUE_TGL; /**< Compare 0 Value Register */ - __IOM uint32_t GRP0_CMP1VALUE_TGL; /**< Compare 1 Value Register */ - __IM uint32_t GRP0_CAP0VALUE_TGL; /**< Capture 0 Value Register */ - __IM uint32_t GRP0_SYNCBUSY_TGL; /**< Synchronization busy Register */ - uint32_t RESERVED27[1U]; /**< Reserved for future use */ - uint32_t RESERVED28[1U]; /**< Reserved for future use */ - uint32_t RESERVED29[7U]; /**< Reserved for future use */ - uint32_t RESERVED30[1U]; /**< Reserved for future use */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP VERSION */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY; /**< Synchronization busy Register */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED8[3U]; /**< Reserved for future use */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_SET; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_SET; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_SET; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_SET; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_SET; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_SET; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_SET; /**< Synchronization busy Register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + uint32_t RESERVED15[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED16[3U]; /**< Reserved for future use */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_CLR; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_CLR; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_CLR; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_CLR; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_CLR; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_CLR; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_CLR; /**< Synchronization busy Register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[7U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + uint32_t RESERVED24[3U]; /**< Reserved for future use */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_TGL; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_TGL; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_TGL; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_TGL; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_TGL; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_TGL; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_TGL; /**< Synchronization busy Register */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + uint32_t RESERVED29[7U]; /**< Reserved for future use */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ } SYSRTC_TypeDef; /** @} End of group EFR32SG23_SYSRTC */ @@ -151,270 +149,270 @@ typedef struct *****************************************************************************/ /* Bit fields for SYSRTC IPVERSION */ -#define _SYSRTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for SYSRTC_IPVERSION */ -#define _SYSRTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_IPVERSION */ -#define _SYSRTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSRTC_IPVERSION */ -#define _SYSRTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_IPVERSION */ -#define _SYSRTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSRTC_IPVERSION */ -#define SYSRTC_IPVERSION_IPVERSION_DEFAULT (_SYSRTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSRTC_IPVERSION */ +#define SYSRTC_IPVERSION_IPVERSION_DEFAULT (_SYSRTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_IPVERSION */ /* Bit fields for SYSRTC EN */ -#define _SYSRTC_EN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_EN */ -#define _SYSRTC_EN_MASK 0x00000003UL /**< Mask for SYSRTC_EN */ -#define SYSRTC_EN_EN (0x1UL << 0) /**< SYSRTC Enable */ -#define _SYSRTC_EN_EN_SHIFT 0 /**< Shift value for SYSRTC_EN */ -#define _SYSRTC_EN_EN_MASK 0x1UL /**< Bit mask for SYSRTC_EN */ -#define _SYSRTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ -#define SYSRTC_EN_EN_DEFAULT (_SYSRTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_EN */ -#define SYSRTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _SYSRTC_EN_DISABLING_SHIFT 1 /**< Shift value for SYSRTC_DISABLING */ -#define _SYSRTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for SYSRTC_DISABLING */ -#define _SYSRTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ -#define SYSRTC_EN_DISABLING_DEFAULT (_SYSRTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_EN */ +#define _SYSRTC_EN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_EN */ +#define _SYSRTC_EN_MASK 0x00000003UL /**< Mask for SYSRTC_EN */ +#define SYSRTC_EN_EN (0x1UL << 0) /**< SYSRTC Enable */ +#define _SYSRTC_EN_EN_SHIFT 0 /**< Shift value for SYSRTC_EN */ +#define _SYSRTC_EN_EN_MASK 0x1UL /**< Bit mask for SYSRTC_EN */ +#define _SYSRTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_EN_DEFAULT (_SYSRTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _SYSRTC_EN_DISABLING_SHIFT 1 /**< Shift value for SYSRTC_DISABLING */ +#define _SYSRTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for SYSRTC_DISABLING */ +#define _SYSRTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_DISABLING_DEFAULT (_SYSRTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_EN */ /* Bit fields for SYSRTC SWRST */ -#define _SYSRTC_SWRST_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SWRST */ -#define _SYSRTC_SWRST_MASK 0x00000003UL /**< Mask for SYSRTC_SWRST */ -#define SYSRTC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ -#define _SYSRTC_SWRST_SWRST_SHIFT 0 /**< Shift value for SYSRTC_SWRST */ -#define _SYSRTC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for SYSRTC_SWRST */ -#define _SYSRTC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ -#define SYSRTC_SWRST_SWRST_DEFAULT (_SYSRTC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ -#define SYSRTC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ -#define _SYSRTC_SWRST_RESETTING_SHIFT 1 /**< Shift value for SYSRTC_RESETTING */ -#define _SYSRTC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for SYSRTC_RESETTING */ -#define _SYSRTC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ -#define SYSRTC_SWRST_RESETTING_DEFAULT (_SYSRTC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_MASK 0x00000003UL /**< Mask for SYSRTC_SWRST */ +#define SYSRTC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _SYSRTC_SWRST_SWRST_SHIFT 0 /**< Shift value for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_SWRST_DEFAULT (_SYSRTC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _SYSRTC_SWRST_RESETTING_SHIFT 1 /**< Shift value for SYSRTC_RESETTING */ +#define _SYSRTC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for SYSRTC_RESETTING */ +#define _SYSRTC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_RESETTING_DEFAULT (_SYSRTC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ /* Bit fields for SYSRTC CFG */ -#define _SYSRTC_CFG_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CFG */ -#define _SYSRTC_CFG_MASK 0x00000001UL /**< Mask for SYSRTC_CFG */ -#define SYSRTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ -#define _SYSRTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for SYSRTC_DEBUGRUN */ -#define _SYSRTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for SYSRTC_DEBUGRUN */ -#define _SYSRTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CFG */ -#define _SYSRTC_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for SYSRTC_CFG */ -#define _SYSRTC_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for SYSRTC_CFG */ -#define SYSRTC_CFG_DEBUGRUN_DEFAULT (_SYSRTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CFG */ -#define SYSRTC_CFG_DEBUGRUN_DISABLE (_SYSRTC_CFG_DEBUGRUN_DISABLE << 0) /**< Shifted mode DISABLE for SYSRTC_CFG */ -#define SYSRTC_CFG_DEBUGRUN_ENABLE (_SYSRTC_CFG_DEBUGRUN_ENABLE << 0) /**< Shifted mode ENABLE for SYSRTC_CFG */ +#define _SYSRTC_CFG_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CFG */ +#define _SYSRTC_CFG_MASK 0x00000001UL /**< Mask for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _SYSRTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for SYSRTC_DEBUGRUN */ +#define _SYSRTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for SYSRTC_DEBUGRUN */ +#define _SYSRTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CFG */ +#define _SYSRTC_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for SYSRTC_CFG */ +#define _SYSRTC_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_DEFAULT (_SYSRTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_DISABLE (_SYSRTC_CFG_DEBUGRUN_DISABLE << 0) /**< Shifted mode DISABLE for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_ENABLE (_SYSRTC_CFG_DEBUGRUN_ENABLE << 0) /**< Shifted mode ENABLE for SYSRTC_CFG */ /* Bit fields for SYSRTC CMD */ -#define _SYSRTC_CMD_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CMD */ -#define _SYSRTC_CMD_MASK 0x00000003UL /**< Mask for SYSRTC_CMD */ -#define SYSRTC_CMD_START (0x1UL << 0) /**< Start SYSRTC */ -#define _SYSRTC_CMD_START_SHIFT 0 /**< Shift value for SYSRTC_START */ -#define _SYSRTC_CMD_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ -#define _SYSRTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ -#define SYSRTC_CMD_START_DEFAULT (_SYSRTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CMD */ -#define SYSRTC_CMD_STOP (0x1UL << 1) /**< Stop SYSRTC */ -#define _SYSRTC_CMD_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ -#define _SYSRTC_CMD_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ -#define _SYSRTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ -#define SYSRTC_CMD_STOP_DEFAULT (_SYSRTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_CMD */ +#define _SYSRTC_CMD_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CMD */ +#define _SYSRTC_CMD_MASK 0x00000003UL /**< Mask for SYSRTC_CMD */ +#define SYSRTC_CMD_START (0x1UL << 0) /**< Start SYSRTC */ +#define _SYSRTC_CMD_START_SHIFT 0 /**< Shift value for SYSRTC_START */ +#define _SYSRTC_CMD_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ +#define _SYSRTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_START_DEFAULT (_SYSRTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_STOP (0x1UL << 1) /**< Stop SYSRTC */ +#define _SYSRTC_CMD_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ +#define _SYSRTC_CMD_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ +#define _SYSRTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_STOP_DEFAULT (_SYSRTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_CMD */ /* Bit fields for SYSRTC STATUS */ -#define _SYSRTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_STATUS */ -#define _SYSRTC_STATUS_MASK 0x00000007UL /**< Mask for SYSRTC_STATUS */ -#define SYSRTC_STATUS_RUNNING (0x1UL << 0) /**< SYSRTC running status */ -#define _SYSRTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for SYSRTC_RUNNING */ -#define _SYSRTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for SYSRTC_RUNNING */ -#define _SYSRTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ -#define SYSRTC_STATUS_RUNNING_DEFAULT (_SYSRTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ -#define SYSRTC_STATUS_LOCKSTATUS (0x1UL << 1) /**< Lock Status */ -#define _SYSRTC_STATUS_LOCKSTATUS_SHIFT 1 /**< Shift value for SYSRTC_LOCKSTATUS */ -#define _SYSRTC_STATUS_LOCKSTATUS_MASK 0x2UL /**< Bit mask for SYSRTC_LOCKSTATUS */ -#define _SYSRTC_STATUS_LOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ -#define _SYSRTC_STATUS_LOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SYSRTC_STATUS */ -#define _SYSRTC_STATUS_LOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for SYSRTC_STATUS */ -#define SYSRTC_STATUS_LOCKSTATUS_DEFAULT (_SYSRTC_STATUS_LOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ -#define SYSRTC_STATUS_LOCKSTATUS_UNLOCKED (_SYSRTC_STATUS_LOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for SYSRTC_STATUS */ -#define SYSRTC_STATUS_LOCKSTATUS_LOCKED (_SYSRTC_STATUS_LOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_MASK 0x00000007UL /**< Mask for SYSRTC_STATUS */ +#define SYSRTC_STATUS_RUNNING (0x1UL << 0) /**< SYSRTC running status */ +#define _SYSRTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for SYSRTC_RUNNING */ +#define _SYSRTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for SYSRTC_RUNNING */ +#define _SYSRTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_RUNNING_DEFAULT (_SYSRTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS (0x1UL << 1) /**< Lock Status */ +#define _SYSRTC_STATUS_LOCKSTATUS_SHIFT 1 /**< Shift value for SYSRTC_LOCKSTATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_MASK 0x2UL /**< Bit mask for SYSRTC_LOCKSTATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_DEFAULT (_SYSRTC_STATUS_LOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_UNLOCKED (_SYSRTC_STATUS_LOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_LOCKED (_SYSRTC_STATUS_LOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for SYSRTC_STATUS */ /* Bit fields for SYSRTC CNT */ -#define _SYSRTC_CNT_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CNT */ -#define _SYSRTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_CNT */ -#define _SYSRTC_CNT_CNT_SHIFT 0 /**< Shift value for SYSRTC_CNT */ -#define _SYSRTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CNT */ -#define _SYSRTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CNT */ -#define SYSRTC_CNT_CNT_DEFAULT (_SYSRTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CNT */ +#define _SYSRTC_CNT_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CNT */ +#define _SYSRTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_SHIFT 0 /**< Shift value for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CNT */ +#define SYSRTC_CNT_CNT_DEFAULT (_SYSRTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CNT */ /* Bit fields for SYSRTC SYNCBUSY */ -#define _SYSRTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SYNCBUSY */ -#define _SYSRTC_SYNCBUSY_MASK 0x0000000FUL /**< Mask for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START bitfield */ -#define _SYSRTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for SYSRTC_START */ -#define _SYSRTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ -#define _SYSRTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_START_DEFAULT (_SYSRTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP bitfield */ -#define _SYSRTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ -#define _SYSRTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ -#define _SYSRTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_STOP_DEFAULT (_SYSRTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_CNT (0x1UL << 2) /**< Sync busy for CNT bitfield */ -#define _SYSRTC_SYNCBUSY_CNT_SHIFT 2 /**< Shift value for SYSRTC_CNT */ -#define _SYSRTC_SYNCBUSY_CNT_MASK 0x4UL /**< Bit mask for SYSRTC_CNT */ -#define _SYSRTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_CNT_DEFAULT (_SYSRTC_SYNCBUSY_CNT_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ +#define _SYSRTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SYNCBUSY */ +#define _SYSRTC_SYNCBUSY_MASK 0x0000000FUL /**< Mask for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START bitfield */ +#define _SYSRTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for SYSRTC_START */ +#define _SYSRTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ +#define _SYSRTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_START_DEFAULT (_SYSRTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP bitfield */ +#define _SYSRTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ +#define _SYSRTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ +#define _SYSRTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_STOP_DEFAULT (_SYSRTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_CNT (0x1UL << 2) /**< Sync busy for CNT bitfield */ +#define _SYSRTC_SYNCBUSY_CNT_SHIFT 2 /**< Shift value for SYSRTC_CNT */ +#define _SYSRTC_SYNCBUSY_CNT_MASK 0x4UL /**< Bit mask for SYSRTC_CNT */ +#define _SYSRTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_CNT_DEFAULT (_SYSRTC_SYNCBUSY_CNT_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ /* Bit fields for SYSRTC LOCK */ -#define _SYSRTC_LOCK_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_LOCK */ -#define _SYSRTC_LOCK_MASK 0x0000FFFFUL /**< Mask for SYSRTC_LOCK */ -#define _SYSRTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for SYSRTC_LOCKKEY */ -#define _SYSRTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for SYSRTC_LOCKKEY */ -#define _SYSRTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_LOCK */ -#define _SYSRTC_LOCK_LOCKKEY_UNLOCK 0x00004776UL /**< Mode UNLOCK for SYSRTC_LOCK */ -#define SYSRTC_LOCK_LOCKKEY_DEFAULT (_SYSRTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_LOCK */ -#define SYSRTC_LOCK_LOCKKEY_UNLOCK (_SYSRTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_MASK 0x0000FFFFUL /**< Mask for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for SYSRTC_LOCKKEY */ +#define _SYSRTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for SYSRTC_LOCKKEY */ +#define _SYSRTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_LOCKKEY_UNLOCK 0x00004776UL /**< Mode UNLOCK for SYSRTC_LOCK */ +#define SYSRTC_LOCK_LOCKKEY_DEFAULT (_SYSRTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_LOCK */ +#define SYSRTC_LOCK_LOCKKEY_UNLOCK (_SYSRTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SYSRTC_LOCK */ /* Bit fields for SYSRTC GRP0_IF */ -#define _SYSRTC_GRP0_IF_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IF */ -#define _SYSRTC_GRP0_IF_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_OVF (0x1UL << 0) /**< Overflow Interrupt Flag */ -#define _SYSRTC_GRP0_IF_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ -#define _SYSRTC_GRP0_IF_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ -#define _SYSRTC_GRP0_IF_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_OVF_DEFAULT (_SYSRTC_GRP0_IF_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Flag */ -#define _SYSRTC_GRP0_IF_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ -#define _SYSRTC_GRP0_IF_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ -#define _SYSRTC_GRP0_IF_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CMP0_DEFAULT (_SYSRTC_GRP0_IF_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Flag */ -#define _SYSRTC_GRP0_IF_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ -#define _SYSRTC_GRP0_IF_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ -#define _SYSRTC_GRP0_IF_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CMP1_DEFAULT (_SYSRTC_GRP0_IF_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Flag */ -#define _SYSRTC_GRP0_IF_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ -#define _SYSRTC_GRP0_IF_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ -#define _SYSRTC_GRP0_IF_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CAP0_DEFAULT (_SYSRTC_GRP0_IF_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define _SYSRTC_GRP0_IF_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IF */ +#define _SYSRTC_GRP0_IF_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_OVF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _SYSRTC_GRP0_IF_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IF_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IF_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_OVF_DEFAULT (_SYSRTC_GRP0_IF_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IF_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IF_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP0_DEFAULT (_SYSRTC_GRP0_IF_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IF_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IF_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP1_DEFAULT (_SYSRTC_GRP0_IF_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IF_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IF_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CAP0_DEFAULT (_SYSRTC_GRP0_IF_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ /* Bit fields for SYSRTC GRP0_IEN */ -#define _SYSRTC_GRP0_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IEN */ -#define _SYSRTC_GRP0_IEN_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_OVF (0x1UL << 0) /**< Overflow Interrupt Enable */ -#define _SYSRTC_GRP0_IEN_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ -#define _SYSRTC_GRP0_IEN_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ -#define _SYSRTC_GRP0_IEN_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_OVF_DEFAULT (_SYSRTC_GRP0_IEN_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Enable */ -#define _SYSRTC_GRP0_IEN_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ -#define _SYSRTC_GRP0_IEN_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ -#define _SYSRTC_GRP0_IEN_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CMP0_DEFAULT (_SYSRTC_GRP0_IEN_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Enable */ -#define _SYSRTC_GRP0_IEN_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ -#define _SYSRTC_GRP0_IEN_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ -#define _SYSRTC_GRP0_IEN_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CMP1_DEFAULT (_SYSRTC_GRP0_IEN_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Enable */ -#define _SYSRTC_GRP0_IEN_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ -#define _SYSRTC_GRP0_IEN_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ -#define _SYSRTC_GRP0_IEN_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CAP0_DEFAULT (_SYSRTC_GRP0_IEN_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define _SYSRTC_GRP0_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IEN */ +#define _SYSRTC_GRP0_IEN_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_OVF (0x1UL << 0) /**< Overflow Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IEN_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IEN_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_OVF_DEFAULT (_SYSRTC_GRP0_IEN_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IEN_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IEN_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP0_DEFAULT (_SYSRTC_GRP0_IEN_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IEN_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IEN_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP1_DEFAULT (_SYSRTC_GRP0_IEN_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IEN_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IEN_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CAP0_DEFAULT (_SYSRTC_GRP0_IEN_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ /* Bit fields for SYSRTC GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_MASK 0x000007FFUL /**< Mask for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0EN (0x1UL << 0) /**< Compare 0 Enable */ -#define _SYSRTC_GRP0_CTRL_CMP0EN_SHIFT 0 /**< Shift value for SYSRTC_CMP0EN */ -#define _SYSRTC_GRP0_CTRL_CMP0EN_MASK 0x1UL /**< Bit mask for SYSRTC_CMP0EN */ -#define _SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1EN (0x1UL << 1) /**< Compare 1 Enable */ -#define _SYSRTC_GRP0_CTRL_CMP1EN_SHIFT 1 /**< Shift value for SYSRTC_CMP1EN */ -#define _SYSRTC_GRP0_CTRL_CMP1EN_MASK 0x2UL /**< Bit mask for SYSRTC_CMP1EN */ -#define _SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EN (0x1UL << 2) /**< Capture 0 Enable */ -#define _SYSRTC_GRP0_CTRL_CAP0EN_SHIFT 2 /**< Shift value for SYSRTC_CAP0EN */ -#define _SYSRTC_GRP0_CTRL_CAP0EN_MASK 0x4UL /**< Bit mask for SYSRTC_CAP0EN */ -#define _SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SHIFT 3 /**< Shift value for SYSRTC_CMP0CMOA */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_MASK 0x38UL /**< Bit mask for SYSRTC_CMP0CMOA */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR << 3) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_SET (_SYSRTC_GRP0_CTRL_CMP0CMOA_SET << 3) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE << 3) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE << 3) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF << 3) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT 6 /**< Shift value for SYSRTC_CMP1CMOA */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_MASK 0x1C0UL /**< Bit mask for SYSRTC_CMP1CMOA */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR << 6) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_SET (_SYSRTC_GRP0_CTRL_CMP1CMOA_SET << 6) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE << 6) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE << 6) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF << 6) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT 9 /**< Shift value for SYSRTC_CAP0EDGE */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_MASK 0x600UL /**< Bit mask for SYSRTC_CAP0EDGE */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_RISING 0x00000000UL /**< Mode RISING for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING 0x00000001UL /**< Mode FALLING for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH 0x00000002UL /**< Mode BOTH for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EDGE_RISING (_SYSRTC_GRP0_CTRL_CAP0EDGE_RISING << 9) /**< Shifted mode RISING for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING (_SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING << 9) /**< Shifted mode FALLING for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH (_SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH << 9) /**< Shifted mode BOTH for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_MASK 0x000007FFUL /**< Mask for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0EN (0x1UL << 0) /**< Compare 0 Enable */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_SHIFT 0 /**< Shift value for SYSRTC_CMP0EN */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_MASK 0x1UL /**< Bit mask for SYSRTC_CMP0EN */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1EN (0x1UL << 1) /**< Compare 1 Enable */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_SHIFT 1 /**< Shift value for SYSRTC_CMP1EN */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_MASK 0x2UL /**< Bit mask for SYSRTC_CMP1EN */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EN (0x1UL << 2) /**< Capture 0 Enable */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_SHIFT 2 /**< Shift value for SYSRTC_CAP0EN */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_MASK 0x4UL /**< Bit mask for SYSRTC_CAP0EN */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SHIFT 3 /**< Shift value for SYSRTC_CMP0CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_MASK 0x38UL /**< Bit mask for SYSRTC_CMP0CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR << 3) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_SET (_SYSRTC_GRP0_CTRL_CMP0CMOA_SET << 3) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE << 3) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE << 3) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF << 3) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT 6 /**< Shift value for SYSRTC_CMP1CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_MASK 0x1C0UL /**< Bit mask for SYSRTC_CMP1CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR << 6) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_SET (_SYSRTC_GRP0_CTRL_CMP1CMOA_SET << 6) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE << 6) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE << 6) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF << 6) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT 9 /**< Shift value for SYSRTC_CAP0EDGE */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_MASK 0x600UL /**< Bit mask for SYSRTC_CAP0EDGE */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_RISING 0x00000000UL /**< Mode RISING for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING 0x00000001UL /**< Mode FALLING for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH 0x00000002UL /**< Mode BOTH for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_RISING (_SYSRTC_GRP0_CTRL_CAP0EDGE_RISING << 9) /**< Shifted mode RISING for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING (_SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING << 9) /**< Shifted mode FALLING for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH (_SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH << 9) /**< Shifted mode BOTH for SYSRTC_GRP0_CTRL */ /* Bit fields for SYSRTC GRP0_CMP0VALUE */ -#define _SYSRTC_GRP0_CMP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP0VALUE */ -#define _SYSRTC_GRP0_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP0VALUE */ -#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP0VALUE */ -#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP0VALUE */ -#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP0VALUE */ -#define SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP0VALUE*/ +#define _SYSRTC_GRP0_CMP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP0VALUE */ +#define SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP0VALUE*/ /* Bit fields for SYSRTC GRP0_CMP1VALUE */ -#define _SYSRTC_GRP0_CMP1VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP1VALUE */ -#define _SYSRTC_GRP0_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP1VALUE */ -#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP1VALUE */ -#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP1VALUE */ -#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP1VALUE */ -#define SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP1VALUE*/ +#define _SYSRTC_GRP0_CMP1VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP1VALUE */ +#define SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP1VALUE*/ /* Bit fields for SYSRTC GRP0_CAP0VALUE */ -#define _SYSRTC_GRP0_CAP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CAP0VALUE */ -#define _SYSRTC_GRP0_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CAP0VALUE */ -#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CAP0VALUE */ -#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CAP0VALUE */ -#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CAP0VALUE */ -#define SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT (_SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CAP0VALUE*/ +#define _SYSRTC_GRP0_CAP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CAP0VALUE */ +#define SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT (_SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CAP0VALUE*/ /* Bit fields for SYSRTC GRP0_SYNCBUSY */ -#define _SYSRTC_GRP0_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_SYNCBUSY */ -#define _SYSRTC_GRP0_SYNCBUSY_MASK 0x00000007UL /**< Mask for SYSRTC_GRP0_SYNCBUSY */ -#define SYSRTC_GRP0_SYNCBUSY_CTRL (0x1UL << 0) /**< Sync busy for CTRL register */ -#define _SYSRTC_GRP0_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for SYSRTC_CTRL */ -#define _SYSRTC_GRP0_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for SYSRTC_CTRL */ -#define _SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ -#define SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ -#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE (0x1UL << 1) /**< Sync busy for CMP0VALUE register */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_SHIFT 1 /**< Shift value for SYSRTC_CMP0VALUE */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0VALUE */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ -#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ -#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE (0x1UL << 2) /**< Sync busy for CMP1VALUE register */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_SHIFT 2 /**< Shift value for SYSRTC_CMP1VALUE */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1VALUE */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ -#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ +#define _SYSRTC_GRP0_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_SYNCBUSY */ +#define _SYSRTC_GRP0_SYNCBUSY_MASK 0x00000007UL /**< Mask for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CTRL (0x1UL << 0) /**< Sync busy for CTRL register */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for SYSRTC_CTRL */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for SYSRTC_CTRL */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ +#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE (0x1UL << 1) /**< Sync busy for CMP0VALUE register */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_SHIFT 1 /**< Shift value for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ +#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE (0x1UL << 2) /**< Sync busy for CMP1VALUE register */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_SHIFT 2 /**< Shift value for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ /** @} End of group EFR32SG23_SYSRTC_BitFields */ /** @} End of group EFR32SG23_SYSRTC */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_timer.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_timer.h index 977a3a0153..70538f849d 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_timer.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_timer.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_TIMER_H #define EFR32SG23_TIMER_H - #define TIMER_HAS_SET_CLEAR /**************************************************************************//** @@ -43,121 +42,118 @@ *****************************************************************************/ /** TIMER CC Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t CFG; /**< CC Channel Configuration Register */ - __IOM uint32_t CTRL; /**< CC Channel Control Register */ - __IOM uint32_t OC; /**< OC Channel Value Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t OCB; /**< OC Channel Value Buffer Register */ - __IM uint32_t ICF; /**< IC Channel Value Register */ - __IM uint32_t ICOF; /**< IC Channel Value Overflow Register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t CFG; /**< CC Channel Configuration Register */ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t OC; /**< OC Channel Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t OCB; /**< OC Channel Value Buffer Register */ + __IM uint32_t ICF; /**< IC Channel Value Register */ + __IM uint32_t ICOF; /**< IC Channel Value Overflow Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ } TIMER_CC_TypeDef; - /** TIMER Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t TOP; /**< Counter Top Value Register */ - __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ - __IOM uint32_t CNT; /**< Counter Value Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ - __IOM uint32_t EN; /**< module en */ - uint32_t RESERVED1[11U]; /**< Reserved for future use */ - TIMER_CC_TypeDef CC[3U]; /**< Compare/Capture Channel */ - uint32_t RESERVED2[8U]; /**< Reserved for future use */ - __IOM uint32_t DTCFG; /**< DTI Configuration Register */ - __IOM uint32_t DTTIMECFG; /**< DTI Time Configuration Register */ - __IOM uint32_t DTFCFG; /**< DTI Fault Configuration Register */ - __IOM uint32_t DTCTRL; /**< DTI Control Register */ - __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ - __IM uint32_t DTFAULT; /**< DTI Fault Register */ - __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ - __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ - uint32_t RESERVED3[960U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t TOP_SET; /**< Counter Top Value Register */ - __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ - __IOM uint32_t CNT_SET; /**< Counter Value Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< TIMER Configuration Lock Register */ - __IOM uint32_t EN_SET; /**< module en */ - uint32_t RESERVED5[11U]; /**< Reserved for future use */ - TIMER_CC_TypeDef CC_SET[3U]; /**< Compare/Capture Channel */ - uint32_t RESERVED6[8U]; /**< Reserved for future use */ - __IOM uint32_t DTCFG_SET; /**< DTI Configuration Register */ - __IOM uint32_t DTTIMECFG_SET; /**< DTI Time Configuration Register */ - __IOM uint32_t DTFCFG_SET; /**< DTI Fault Configuration Register */ - __IOM uint32_t DTCTRL_SET; /**< DTI Control Register */ - __IOM uint32_t DTOGEN_SET; /**< DTI Output Generation Enable Register */ - __IM uint32_t DTFAULT_SET; /**< DTI Fault Register */ - __IOM uint32_t DTFAULTC_SET; /**< DTI Fault Clear Register */ - __IOM uint32_t DTLOCK_SET; /**< DTI Configuration Lock Register */ - uint32_t RESERVED7[960U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t TOP_CLR; /**< Counter Top Value Register */ - __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ - __IOM uint32_t CNT_CLR; /**< Counter Value Register */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< TIMER Configuration Lock Register */ - __IOM uint32_t EN_CLR; /**< module en */ - uint32_t RESERVED9[11U]; /**< Reserved for future use */ - TIMER_CC_TypeDef CC_CLR[3U]; /**< Compare/Capture Channel */ - uint32_t RESERVED10[8U]; /**< Reserved for future use */ - __IOM uint32_t DTCFG_CLR; /**< DTI Configuration Register */ - __IOM uint32_t DTTIMECFG_CLR; /**< DTI Time Configuration Register */ - __IOM uint32_t DTFCFG_CLR; /**< DTI Fault Configuration Register */ - __IOM uint32_t DTCTRL_CLR; /**< DTI Control Register */ - __IOM uint32_t DTOGEN_CLR; /**< DTI Output Generation Enable Register */ - __IM uint32_t DTFAULT_CLR; /**< DTI Fault Register */ - __IOM uint32_t DTFAULTC_CLR; /**< DTI Fault Clear Register */ - __IOM uint32_t DTLOCK_CLR; /**< DTI Configuration Lock Register */ - uint32_t RESERVED11[960U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t TOP_TGL; /**< Counter Top Value Register */ - __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ - __IOM uint32_t CNT_TGL; /**< Counter Value Register */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< TIMER Configuration Lock Register */ - __IOM uint32_t EN_TGL; /**< module en */ - uint32_t RESERVED13[11U]; /**< Reserved for future use */ - TIMER_CC_TypeDef CC_TGL[3U]; /**< Compare/Capture Channel */ - uint32_t RESERVED14[8U]; /**< Reserved for future use */ - __IOM uint32_t DTCFG_TGL; /**< DTI Configuration Register */ - __IOM uint32_t DTTIMECFG_TGL; /**< DTI Time Configuration Register */ - __IOM uint32_t DTFCFG_TGL; /**< DTI Fault Configuration Register */ - __IOM uint32_t DTCTRL_TGL; /**< DTI Control Register */ - __IOM uint32_t DTOGEN_TGL; /**< DTI Output Generation Enable Register */ - __IM uint32_t DTFAULT_TGL; /**< DTI Fault Register */ - __IOM uint32_t DTFAULTC_TGL; /**< DTI Fault Clear Register */ - __IOM uint32_t DTLOCK_TGL; /**< DTI Configuration Lock Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t TOP; /**< Counter Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN; /**< module en */ + uint32_t RESERVED1[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ + uint32_t RESERVED3[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_SET; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_SET; /**< module en */ + uint32_t RESERVED5[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_SET[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED6[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_SET; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_SET; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_SET; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_SET; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_SET; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_SET; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_SET; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_SET; /**< DTI Configuration Lock Register */ + uint32_t RESERVED7[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_CLR; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_CLR; /**< module en */ + uint32_t RESERVED9[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_CLR[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED10[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_CLR; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_CLR; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_CLR; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_CLR; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_CLR; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_CLR; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_CLR; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_CLR; /**< DTI Configuration Lock Register */ + uint32_t RESERVED11[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_TGL; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_TGL; /**< module en */ + uint32_t RESERVED13[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_TGL[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED14[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_TGL; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_TGL; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_TGL; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_TGL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_TGL; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_TGL; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_TGL; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_TGL; /**< DTI Configuration Lock Register */ } TIMER_TypeDef; /** @} End of group EFR32SG23_TIMER */ @@ -169,853 +165,853 @@ typedef struct *****************************************************************************/ /* Bit fields for TIMER IPVERSION */ -#define _TIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for TIMER_IPVERSION */ -#define _TIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for TIMER_IPVERSION */ -#define _TIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for TIMER_IPVERSION */ -#define _TIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_IPVERSION */ -#define _TIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for TIMER_IPVERSION */ -#define TIMER_IPVERSION_IPVERSION_DEFAULT (_TIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for TIMER_IPVERSION */ +#define TIMER_IPVERSION_IPVERSION_DEFAULT (_TIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IPVERSION */ /* Bit fields for TIMER CFG */ -#define _TIMER_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CFG */ -#define _TIMER_CFG_MASK 0x0FFF1FFBUL /**< Mask for TIMER_CFG */ -#define _TIMER_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ -#define _TIMER_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ -#define _TIMER_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CFG */ -#define _TIMER_CFG_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CFG */ -#define _TIMER_CFG_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CFG */ -#define _TIMER_CFG_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CFG */ -#define TIMER_CFG_MODE_DEFAULT (_TIMER_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_MODE_UP (_TIMER_CFG_MODE_UP << 0) /**< Shifted mode UP for TIMER_CFG */ -#define TIMER_CFG_MODE_DOWN (_TIMER_CFG_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CFG */ -#define TIMER_CFG_MODE_UPDOWN (_TIMER_CFG_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CFG */ -#define TIMER_CFG_MODE_QDEC (_TIMER_CFG_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CFG */ -#define TIMER_CFG_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ -#define _TIMER_CFG_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ -#define _TIMER_CFG_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ -#define _TIMER_CFG_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ -#define _TIMER_CFG_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ -#define TIMER_CFG_SYNC_DEFAULT (_TIMER_CFG_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_SYNC_DISABLE (_TIMER_CFG_SYNC_DISABLE << 3) /**< Shifted mode DISABLE for TIMER_CFG */ -#define TIMER_CFG_SYNC_ENABLE (_TIMER_CFG_SYNC_ENABLE << 3) /**< Shifted mode ENABLE for TIMER_CFG */ -#define TIMER_CFG_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ -#define _TIMER_CFG_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ -#define _TIMER_CFG_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ -#define _TIMER_CFG_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_OSMEN_DEFAULT (_TIMER_CFG_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ -#define _TIMER_CFG_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ -#define _TIMER_CFG_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ -#define _TIMER_CFG_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CFG */ -#define _TIMER_CFG_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CFG */ -#define TIMER_CFG_QDM_DEFAULT (_TIMER_CFG_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_QDM_X2 (_TIMER_CFG_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CFG */ -#define TIMER_CFG_QDM_X4 (_TIMER_CFG_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CFG */ -#define TIMER_CFG_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ -#define _TIMER_CFG_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ -#define _TIMER_CFG_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ -#define _TIMER_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_DEBUGRUN_HALT 0x00000000UL /**< Mode HALT for TIMER_CFG */ -#define _TIMER_CFG_DEBUGRUN_RUN 0x00000001UL /**< Mode RUN for TIMER_CFG */ -#define TIMER_CFG_DEBUGRUN_DEFAULT (_TIMER_CFG_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_DEBUGRUN_HALT (_TIMER_CFG_DEBUGRUN_HALT << 6) /**< Shifted mode HALT for TIMER_CFG */ -#define TIMER_CFG_DEBUGRUN_RUN (_TIMER_CFG_DEBUGRUN_RUN << 6) /**< Shifted mode RUN for TIMER_CFG */ -#define TIMER_CFG_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ -#define _TIMER_CFG_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ -#define _TIMER_CFG_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ -#define _TIMER_CFG_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_DMACLRACT_DEFAULT (_TIMER_CFG_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_CLKSEL_SHIFT 8 /**< Shift value for TIMER_CLKSEL */ -#define _TIMER_CFG_CLKSEL_MASK 0x300UL /**< Bit mask for TIMER_CLKSEL */ -#define _TIMER_CFG_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK 0x00000000UL /**< Mode PRESCEM01GRPACLK for TIMER_CFG */ -#define _TIMER_CFG_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CFG */ -#define _TIMER_CFG_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CFG */ -#define TIMER_CFG_CLKSEL_DEFAULT (_TIMER_CFG_CLKSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_CLKSEL_PRESCEM01GRPACLK (_TIMER_CFG_CLKSEL_PRESCEM01GRPACLK << 8) /**< Shifted mode PRESCEM01GRPACLK for TIMER_CFG */ -#define TIMER_CFG_CLKSEL_CC1 (_TIMER_CFG_CLKSEL_CC1 << 8) /**< Shifted mode CC1 for TIMER_CFG */ -#define TIMER_CFG_CLKSEL_TIMEROUF (_TIMER_CFG_CLKSEL_TIMEROUF << 8) /**< Shifted mode TIMEROUF for TIMER_CFG */ -#define TIMER_CFG_RETIMEEN (0x1UL << 10) /**< PWM output retimed enable */ -#define _TIMER_CFG_RETIMEEN_SHIFT 10 /**< Shift value for TIMER_RETIMEEN */ -#define _TIMER_CFG_RETIMEEN_MASK 0x400UL /**< Bit mask for TIMER_RETIMEEN */ -#define _TIMER_CFG_RETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_RETIMEEN_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ -#define _TIMER_CFG_RETIMEEN_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ -#define TIMER_CFG_RETIMEEN_DEFAULT (_TIMER_CFG_RETIMEEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_RETIMEEN_DISABLE (_TIMER_CFG_RETIMEEN_DISABLE << 10) /**< Shifted mode DISABLE for TIMER_CFG */ -#define TIMER_CFG_RETIMEEN_ENABLE (_TIMER_CFG_RETIMEEN_ENABLE << 10) /**< Shifted mode ENABLE for TIMER_CFG */ -#define TIMER_CFG_DISSYNCOUT (0x1UL << 11) /**< Disable Timer Start/Stop/Reload output */ -#define _TIMER_CFG_DISSYNCOUT_SHIFT 11 /**< Shift value for TIMER_DISSYNCOUT */ -#define _TIMER_CFG_DISSYNCOUT_MASK 0x800UL /**< Bit mask for TIMER_DISSYNCOUT */ -#define _TIMER_CFG_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_DISSYNCOUT_EN 0x00000000UL /**< Mode EN for TIMER_CFG */ -#define _TIMER_CFG_DISSYNCOUT_DIS 0x00000001UL /**< Mode DIS for TIMER_CFG */ -#define TIMER_CFG_DISSYNCOUT_DEFAULT (_TIMER_CFG_DISSYNCOUT_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_DISSYNCOUT_EN (_TIMER_CFG_DISSYNCOUT_EN << 11) /**< Shifted mode EN for TIMER_CFG */ -#define TIMER_CFG_DISSYNCOUT_DIS (_TIMER_CFG_DISSYNCOUT_DIS << 11) /**< Shifted mode DIS for TIMER_CFG */ -#define TIMER_CFG_RETIMESEL (0x1UL << 12) /**< PWM output retime select */ -#define _TIMER_CFG_RETIMESEL_SHIFT 12 /**< Shift value for TIMER_RETIMESEL */ -#define _TIMER_CFG_RETIMESEL_MASK 0x1000UL /**< Bit mask for TIMER_RETIMESEL */ -#define _TIMER_CFG_RETIMESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_RETIMESEL_DEFAULT (_TIMER_CFG_RETIMESEL_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_ATI (0x1UL << 16) /**< Always Track Inputs */ -#define _TIMER_CFG_ATI_SHIFT 16 /**< Shift value for TIMER_ATI */ -#define _TIMER_CFG_ATI_MASK 0x10000UL /**< Bit mask for TIMER_ATI */ -#define _TIMER_CFG_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_ATI_DEFAULT (_TIMER_CFG_ATI_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_RSSCOIST (0x1UL << 17) /**< Reload-Start Sets COIST */ -#define _TIMER_CFG_RSSCOIST_SHIFT 17 /**< Shift value for TIMER_RSSCOIST */ -#define _TIMER_CFG_RSSCOIST_MASK 0x20000UL /**< Bit mask for TIMER_RSSCOIST */ -#define _TIMER_CFG_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_RSSCOIST_DEFAULT (_TIMER_CFG_RSSCOIST_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_PRESC_SHIFT 18 /**< Shift value for TIMER_PRESC */ -#define _TIMER_CFG_PRESC_MASK 0xFFC0000UL /**< Bit mask for TIMER_PRESC */ -#define _TIMER_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV8 0x00000007UL /**< Mode DIV8 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV16 0x0000000FUL /**< Mode DIV16 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV32 0x0000001FUL /**< Mode DIV32 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV64 0x0000003FUL /**< Mode DIV64 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV128 0x0000007FUL /**< Mode DIV128 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV256 0x000000FFUL /**< Mode DIV256 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV512 0x000001FFUL /**< Mode DIV512 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV1024 0x000003FFUL /**< Mode DIV1024 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DEFAULT (_TIMER_CFG_PRESC_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV1 (_TIMER_CFG_PRESC_DIV1 << 18) /**< Shifted mode DIV1 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV2 (_TIMER_CFG_PRESC_DIV2 << 18) /**< Shifted mode DIV2 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV4 (_TIMER_CFG_PRESC_DIV4 << 18) /**< Shifted mode DIV4 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV8 (_TIMER_CFG_PRESC_DIV8 << 18) /**< Shifted mode DIV8 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV16 (_TIMER_CFG_PRESC_DIV16 << 18) /**< Shifted mode DIV16 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV32 (_TIMER_CFG_PRESC_DIV32 << 18) /**< Shifted mode DIV32 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV64 (_TIMER_CFG_PRESC_DIV64 << 18) /**< Shifted mode DIV64 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV128 (_TIMER_CFG_PRESC_DIV128 << 18) /**< Shifted mode DIV128 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV256 (_TIMER_CFG_PRESC_DIV256 << 18) /**< Shifted mode DIV256 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV512 (_TIMER_CFG_PRESC_DIV512 << 18) /**< Shifted mode DIV512 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV1024 (_TIMER_CFG_PRESC_DIV1024 << 18) /**< Shifted mode DIV1024 for TIMER_CFG */ +#define _TIMER_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CFG */ +#define _TIMER_CFG_MASK 0x0FFF1FFBUL /**< Mask for TIMER_CFG */ +#define _TIMER_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CFG */ +#define _TIMER_CFG_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CFG */ +#define TIMER_CFG_MODE_DEFAULT (_TIMER_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_MODE_UP (_TIMER_CFG_MODE_UP << 0) /**< Shifted mode UP for TIMER_CFG */ +#define TIMER_CFG_MODE_DOWN (_TIMER_CFG_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_UPDOWN (_TIMER_CFG_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_QDEC (_TIMER_CFG_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CFG */ +#define TIMER_CFG_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _TIMER_CFG_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_DEFAULT (_TIMER_CFG_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_SYNC_DISABLE (_TIMER_CFG_SYNC_DISABLE << 3) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_ENABLE (_TIMER_CFG_SYNC_ENABLE << 3) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _TIMER_CFG_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_OSMEN_DEFAULT (_TIMER_CFG_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _TIMER_CFG_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _TIMER_CFG_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _TIMER_CFG_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CFG */ +#define _TIMER_CFG_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CFG */ +#define TIMER_CFG_QDM_DEFAULT (_TIMER_CFG_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM_X2 (_TIMER_CFG_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CFG */ +#define TIMER_CFG_QDM_X4 (_TIMER_CFG_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _TIMER_CFG_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_HALT 0x00000000UL /**< Mode HALT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_RUN 0x00000001UL /**< Mode RUN for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_DEFAULT (_TIMER_CFG_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_HALT (_TIMER_CFG_DEBUGRUN_HALT << 6) /**< Shifted mode HALT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_RUN (_TIMER_CFG_DEBUGRUN_RUN << 6) /**< Shifted mode RUN for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _TIMER_CFG_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT_DEFAULT (_TIMER_CFG_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_SHIFT 8 /**< Shift value for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_MASK 0x300UL /**< Bit mask for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK 0x00000000UL /**< Mode PRESCEM01GRPACLK for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_DEFAULT (_TIMER_CFG_CLKSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_PRESCEM01GRPACLK (_TIMER_CFG_CLKSEL_PRESCEM01GRPACLK << 8) /**< Shifted mode PRESCEM01GRPACLK for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_CC1 (_TIMER_CFG_CLKSEL_CC1 << 8) /**< Shifted mode CC1 for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_TIMEROUF (_TIMER_CFG_CLKSEL_TIMEROUF << 8) /**< Shifted mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN (0x1UL << 10) /**< PWM output retimed enable */ +#define _TIMER_CFG_RETIMEEN_SHIFT 10 /**< Shift value for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_MASK 0x400UL /**< Bit mask for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DEFAULT (_TIMER_CFG_RETIMEEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DISABLE (_TIMER_CFG_RETIMEEN_DISABLE << 10) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_ENABLE (_TIMER_CFG_RETIMEEN_ENABLE << 10) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT (0x1UL << 11) /**< Disable Timer Start/Stop/Reload output */ +#define _TIMER_CFG_DISSYNCOUT_SHIFT 11 /**< Shift value for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_MASK 0x800UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_EN 0x00000000UL /**< Mode EN for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_DIS 0x00000001UL /**< Mode DIS for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DEFAULT (_TIMER_CFG_DISSYNCOUT_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_EN (_TIMER_CFG_DISSYNCOUT_EN << 11) /**< Shifted mode EN for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DIS (_TIMER_CFG_DISSYNCOUT_DIS << 11) /**< Shifted mode DIS for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL (0x1UL << 12) /**< PWM output retime select */ +#define _TIMER_CFG_RETIMESEL_SHIFT 12 /**< Shift value for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_MASK 0x1000UL /**< Bit mask for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL_DEFAULT (_TIMER_CFG_RETIMESEL_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI (0x1UL << 16) /**< Always Track Inputs */ +#define _TIMER_CFG_ATI_SHIFT 16 /**< Shift value for TIMER_ATI */ +#define _TIMER_CFG_ATI_MASK 0x10000UL /**< Bit mask for TIMER_ATI */ +#define _TIMER_CFG_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI_DEFAULT (_TIMER_CFG_ATI_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST (0x1UL << 17) /**< Reload-Start Sets COIST */ +#define _TIMER_CFG_RSSCOIST_SHIFT 17 /**< Shift value for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_MASK 0x20000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST_DEFAULT (_TIMER_CFG_RSSCOIST_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_SHIFT 18 /**< Shift value for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_MASK 0xFFC0000UL /**< Bit mask for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV8 0x00000007UL /**< Mode DIV8 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV16 0x0000000FUL /**< Mode DIV16 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV32 0x0000001FUL /**< Mode DIV32 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV64 0x0000003FUL /**< Mode DIV64 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV128 0x0000007FUL /**< Mode DIV128 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV256 0x000000FFUL /**< Mode DIV256 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV512 0x000001FFUL /**< Mode DIV512 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1024 0x000003FFUL /**< Mode DIV1024 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DEFAULT (_TIMER_CFG_PRESC_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1 (_TIMER_CFG_PRESC_DIV1 << 18) /**< Shifted mode DIV1 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV2 (_TIMER_CFG_PRESC_DIV2 << 18) /**< Shifted mode DIV2 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV4 (_TIMER_CFG_PRESC_DIV4 << 18) /**< Shifted mode DIV4 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV8 (_TIMER_CFG_PRESC_DIV8 << 18) /**< Shifted mode DIV8 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV16 (_TIMER_CFG_PRESC_DIV16 << 18) /**< Shifted mode DIV16 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV32 (_TIMER_CFG_PRESC_DIV32 << 18) /**< Shifted mode DIV32 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV64 (_TIMER_CFG_PRESC_DIV64 << 18) /**< Shifted mode DIV64 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV128 (_TIMER_CFG_PRESC_DIV128 << 18) /**< Shifted mode DIV128 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV256 (_TIMER_CFG_PRESC_DIV256 << 18) /**< Shifted mode DIV256 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV512 (_TIMER_CFG_PRESC_DIV512 << 18) /**< Shifted mode DIV512 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1024 (_TIMER_CFG_PRESC_DIV1024 << 18) /**< Shifted mode DIV1024 for TIMER_CFG */ /* Bit fields for TIMER CTRL */ -#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ -#define _TIMER_CTRL_MASK 0x0000001FUL /**< Mask for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_SHIFT 0 /**< Shift value for TIMER_RISEA */ -#define _TIMER_CTRL_RISEA_MASK 0x3UL /**< Bit mask for TIMER_RISEA */ -#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 0) /**< Shifted mode NONE for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 0) /**< Shifted mode START for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 0) /**< Shifted mode STOP for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 0) /**< Shifted mode RELOADSTART for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_SHIFT 2 /**< Shift value for TIMER_FALLA */ -#define _TIMER_CTRL_FALLA_MASK 0xCUL /**< Bit mask for TIMER_FALLA */ -#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 2) /**< Shifted mode NONE for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 2) /**< Shifted mode START for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 2) /**< Shifted mode STOP for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 2) /**< Shifted mode RELOADSTART for TIMER_CTRL */ -#define TIMER_CTRL_X2CNT (0x1UL << 4) /**< 2x Count Mode */ -#define _TIMER_CTRL_X2CNT_SHIFT 4 /**< Shift value for TIMER_X2CNT */ -#define _TIMER_CTRL_X2CNT_MASK 0x10UL /**< Bit mask for TIMER_X2CNT */ -#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ -#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ +#define _TIMER_CTRL_MASK 0x0000001FUL /**< Mask for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_SHIFT 0 /**< Shift value for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_MASK 0x3UL /**< Bit mask for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 0) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 0) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 0) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 0) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_SHIFT 2 /**< Shift value for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_MASK 0xCUL /**< Bit mask for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 2) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 2) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 2) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 2) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT (0x1UL << 4) /**< 2x Count Mode */ +#define _TIMER_CTRL_X2CNT_SHIFT 4 /**< Shift value for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_MASK 0x10UL /**< Bit mask for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ /* Bit fields for TIMER CMD */ -#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ -#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ -#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ -#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ -#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ -#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ -#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ -#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ -#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ -#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ -#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ -#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ +#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ +#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ /* Bit fields for TIMER STATUS */ -#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ -#define _TIMER_STATUS_MASK 0x07070777UL /**< Mask for TIMER_STATUS */ -#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ -#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ -#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ -#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ -#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ -#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ -#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ -#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ -#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ -#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ -#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOP Buffer Valid */ -#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ -#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ -#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_TIMERLOCKSTATUS (0x1UL << 4) /**< Timer lock status */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_SHIFT 4 /**< Shift value for TIMER_TIMERLOCKSTATUS */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_MASK 0x10UL /**< Bit mask for TIMER_TIMERLOCKSTATUS */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ -#define TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT (_TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED << 4) /**< Shifted mode UNLOCKED for TIMER_STATUS */ -#define TIMER_STATUS_TIMERLOCKSTATUS_LOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_LOCKED << 4) /**< Shifted mode LOCKED for TIMER_STATUS */ -#define TIMER_STATUS_DTILOCKSTATUS (0x1UL << 5) /**< DTI lock status */ -#define _TIMER_STATUS_DTILOCKSTATUS_SHIFT 5 /**< Shift value for TIMER_DTILOCKSTATUS */ -#define _TIMER_STATUS_DTILOCKSTATUS_MASK 0x20UL /**< Bit mask for TIMER_DTILOCKSTATUS */ -#define _TIMER_STATUS_DTILOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_DTILOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ -#define _TIMER_STATUS_DTILOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ -#define TIMER_STATUS_DTILOCKSTATUS_DEFAULT (_TIMER_STATUS_DTILOCKSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_DTILOCKSTATUS_UNLOCKED (_TIMER_STATUS_DTILOCKSTATUS_UNLOCKED << 5) /**< Shifted mode UNLOCKED for TIMER_STATUS */ -#define TIMER_STATUS_DTILOCKSTATUS_LOCKED (_TIMER_STATUS_DTILOCKSTATUS_LOCKED << 5) /**< Shifted mode LOCKED for TIMER_STATUS */ -#define TIMER_STATUS_SYNCBUSY (0x1UL << 6) /**< Sync Busy */ -#define _TIMER_STATUS_SYNCBUSY_SHIFT 6 /**< Shift value for TIMER_SYNCBUSY */ -#define _TIMER_STATUS_SYNCBUSY_MASK 0x40UL /**< Bit mask for TIMER_SYNCBUSY */ -#define _TIMER_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_SYNCBUSY_DEFAULT (_TIMER_STATUS_SYNCBUSY_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV0 (0x1UL << 8) /**< Output Compare Buffer Valid */ -#define _TIMER_STATUS_OCBV0_SHIFT 8 /**< Shift value for TIMER_OCBV0 */ -#define _TIMER_STATUS_OCBV0_MASK 0x100UL /**< Bit mask for TIMER_OCBV0 */ -#define _TIMER_STATUS_OCBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV0_DEFAULT (_TIMER_STATUS_OCBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV1 (0x1UL << 9) /**< Output Compare Buffer Valid */ -#define _TIMER_STATUS_OCBV1_SHIFT 9 /**< Shift value for TIMER_OCBV1 */ -#define _TIMER_STATUS_OCBV1_MASK 0x200UL /**< Bit mask for TIMER_OCBV1 */ -#define _TIMER_STATUS_OCBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV1_DEFAULT (_TIMER_STATUS_OCBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV2 (0x1UL << 10) /**< Output Compare Buffer Valid */ -#define _TIMER_STATUS_OCBV2_SHIFT 10 /**< Shift value for TIMER_OCBV2 */ -#define _TIMER_STATUS_OCBV2_MASK 0x400UL /**< Bit mask for TIMER_OCBV2 */ -#define _TIMER_STATUS_OCBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV2_DEFAULT (_TIMER_STATUS_OCBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY0 (0x1UL << 16) /**< Input capture fifo empty */ -#define _TIMER_STATUS_ICFEMPTY0_SHIFT 16 /**< Shift value for TIMER_ICFEMPTY0 */ -#define _TIMER_STATUS_ICFEMPTY0_MASK 0x10000UL /**< Bit mask for TIMER_ICFEMPTY0 */ -#define _TIMER_STATUS_ICFEMPTY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY0_DEFAULT (_TIMER_STATUS_ICFEMPTY0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY1 (0x1UL << 17) /**< Input capture fifo empty */ -#define _TIMER_STATUS_ICFEMPTY1_SHIFT 17 /**< Shift value for TIMER_ICFEMPTY1 */ -#define _TIMER_STATUS_ICFEMPTY1_MASK 0x20000UL /**< Bit mask for TIMER_ICFEMPTY1 */ -#define _TIMER_STATUS_ICFEMPTY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY1_DEFAULT (_TIMER_STATUS_ICFEMPTY1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY2 (0x1UL << 18) /**< Input capture fifo empty */ -#define _TIMER_STATUS_ICFEMPTY2_SHIFT 18 /**< Shift value for TIMER_ICFEMPTY2 */ -#define _TIMER_STATUS_ICFEMPTY2_MASK 0x40000UL /**< Bit mask for TIMER_ICFEMPTY2 */ -#define _TIMER_STATUS_ICFEMPTY2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY2_DEFAULT (_TIMER_STATUS_ICFEMPTY2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< Compare/Capture Polarity */ -#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ -#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ -#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< Compare/Capture Polarity */ -#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ -#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ -#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< Compare/Capture Polarity */ -#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ -#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ -#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ +#define _TIMER_STATUS_MASK 0x07070777UL /**< Mask for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOP Buffer Valid */ +#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS (0x1UL << 4) /**< Timer lock status */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_SHIFT 4 /**< Shift value for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_MASK 0x10UL /**< Bit mask for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT (_TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED << 4) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_LOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_LOCKED << 4) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS (0x1UL << 5) /**< DTI lock status */ +#define _TIMER_STATUS_DTILOCKSTATUS_SHIFT 5 /**< Shift value for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_MASK 0x20UL /**< Bit mask for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_DEFAULT (_TIMER_STATUS_DTILOCKSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_UNLOCKED (_TIMER_STATUS_DTILOCKSTATUS_UNLOCKED << 5) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_LOCKED (_TIMER_STATUS_DTILOCKSTATUS_LOCKED << 5) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY (0x1UL << 6) /**< Sync Busy */ +#define _TIMER_STATUS_SYNCBUSY_SHIFT 6 /**< Shift value for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_MASK 0x40UL /**< Bit mask for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY_DEFAULT (_TIMER_STATUS_SYNCBUSY_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0 (0x1UL << 8) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV0_SHIFT 8 /**< Shift value for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_MASK 0x100UL /**< Bit mask for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0_DEFAULT (_TIMER_STATUS_OCBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1 (0x1UL << 9) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV1_SHIFT 9 /**< Shift value for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_MASK 0x200UL /**< Bit mask for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1_DEFAULT (_TIMER_STATUS_OCBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2 (0x1UL << 10) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV2_SHIFT 10 /**< Shift value for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_MASK 0x400UL /**< Bit mask for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2_DEFAULT (_TIMER_STATUS_OCBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0 (0x1UL << 16) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY0_SHIFT 16 /**< Shift value for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_MASK 0x10000UL /**< Bit mask for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0_DEFAULT (_TIMER_STATUS_ICFEMPTY0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1 (0x1UL << 17) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY1_SHIFT 17 /**< Shift value for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_MASK 0x20000UL /**< Bit mask for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1_DEFAULT (_TIMER_STATUS_ICFEMPTY1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2 (0x1UL << 18) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY2_SHIFT 18 /**< Shift value for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_MASK 0x40000UL /**< Bit mask for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2_DEFAULT (_TIMER_STATUS_ICFEMPTY2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ /* Bit fields for TIMER IF */ -#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ -#define _TIMER_IF_MASK 0x07770077UL /**< Mask for TIMER_IF */ -#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ -#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ -#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ -#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ -#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ -#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ -#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ -#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ -#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ -#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC0 (0x1UL << 4) /**< Capture Compare Channel 0 Interrupt Flag */ -#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ -#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ -#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC1 (0x1UL << 5) /**< Capture Compare Channel 1 Interrupt Flag */ -#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ -#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ -#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC2 (0x1UL << 6) /**< Capture Compare Channel 2 Interrupt Flag */ -#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ -#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ -#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL0 (0x1UL << 16) /**< Input Capture Watermark Level Full */ -#define _TIMER_IF_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ -#define _TIMER_IF_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ -#define _TIMER_IF_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL0_DEFAULT (_TIMER_IF_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL1 (0x1UL << 17) /**< Input Capture Watermark Level Full */ -#define _TIMER_IF_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ -#define _TIMER_IF_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ -#define _TIMER_IF_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL1_DEFAULT (_TIMER_IF_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL2 (0x1UL << 18) /**< Input Capture Watermark Level Full */ -#define _TIMER_IF_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ -#define _TIMER_IF_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ -#define _TIMER_IF_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL2_DEFAULT (_TIMER_IF_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF0 (0x1UL << 20) /**< Input Capture FIFO overflow */ -#define _TIMER_IF_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ -#define _TIMER_IF_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ -#define _TIMER_IF_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF0_DEFAULT (_TIMER_IF_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF1 (0x1UL << 21) /**< Input Capture FIFO overflow */ -#define _TIMER_IF_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ -#define _TIMER_IF_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ -#define _TIMER_IF_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF1_DEFAULT (_TIMER_IF_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF2 (0x1UL << 22) /**< Input Capture FIFO overflow */ -#define _TIMER_IF_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ -#define _TIMER_IF_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ -#define _TIMER_IF_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF2_DEFAULT (_TIMER_IF_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF0 (0x1UL << 24) /**< Input capture FIFO underflow */ -#define _TIMER_IF_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ -#define _TIMER_IF_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ -#define _TIMER_IF_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF0_DEFAULT (_TIMER_IF_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF1 (0x1UL << 25) /**< Input capture FIFO underflow */ -#define _TIMER_IF_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ -#define _TIMER_IF_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ -#define _TIMER_IF_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF1_DEFAULT (_TIMER_IF_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF2 (0x1UL << 26) /**< Input capture FIFO underflow */ -#define _TIMER_IF_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ -#define _TIMER_IF_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ -#define _TIMER_IF_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF2_DEFAULT (_TIMER_IF_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IF */ +#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ +#define _TIMER_IF_MASK 0x07770077UL /**< Mask for TIMER_IF */ +#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0 (0x1UL << 4) /**< Capture Compare Channel 0 Interrupt Flag */ +#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1 (0x1UL << 5) /**< Capture Compare Channel 1 Interrupt Flag */ +#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2 (0x1UL << 6) /**< Capture Compare Channel 2 Interrupt Flag */ +#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0 (0x1UL << 16) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0_DEFAULT (_TIMER_IF_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1 (0x1UL << 17) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1_DEFAULT (_TIMER_IF_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2 (0x1UL << 18) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2_DEFAULT (_TIMER_IF_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0 (0x1UL << 20) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0_DEFAULT (_TIMER_IF_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1 (0x1UL << 21) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1_DEFAULT (_TIMER_IF_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2 (0x1UL << 22) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2_DEFAULT (_TIMER_IF_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0 (0x1UL << 24) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0_DEFAULT (_TIMER_IF_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1 (0x1UL << 25) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1_DEFAULT (_TIMER_IF_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2 (0x1UL << 26) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2_DEFAULT (_TIMER_IF_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IF */ /* Bit fields for TIMER IEN */ -#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ -#define _TIMER_IEN_MASK 0x07770077UL /**< Mask for TIMER_IEN */ -#define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ -#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ -#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ -#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */ -#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ -#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ -#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */ -#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ -#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ -#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ -#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ -#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ -#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ -#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ -#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ -#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ -#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ -#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ -#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL0 (0x1UL << 16) /**< ICFWLFULL0 Interrupt Enable */ -#define _TIMER_IEN_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ -#define _TIMER_IEN_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ -#define _TIMER_IEN_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL0_DEFAULT (_TIMER_IEN_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL1 (0x1UL << 17) /**< ICFWLFULL1 Interrupt Enable */ -#define _TIMER_IEN_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ -#define _TIMER_IEN_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ -#define _TIMER_IEN_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL1_DEFAULT (_TIMER_IEN_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL2 (0x1UL << 18) /**< ICFWLFULL2 Interrupt Enable */ -#define _TIMER_IEN_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ -#define _TIMER_IEN_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ -#define _TIMER_IEN_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL2_DEFAULT (_TIMER_IEN_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF0 (0x1UL << 20) /**< ICFOF0 Interrupt Enable */ -#define _TIMER_IEN_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ -#define _TIMER_IEN_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ -#define _TIMER_IEN_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF0_DEFAULT (_TIMER_IEN_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF1 (0x1UL << 21) /**< ICFOF1 Interrupt Enable */ -#define _TIMER_IEN_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ -#define _TIMER_IEN_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ -#define _TIMER_IEN_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF1_DEFAULT (_TIMER_IEN_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF2 (0x1UL << 22) /**< ICFOF2 Interrupt Enable */ -#define _TIMER_IEN_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ -#define _TIMER_IEN_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ -#define _TIMER_IEN_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF2_DEFAULT (_TIMER_IEN_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF0 (0x1UL << 24) /**< ICFUF0 Interrupt Enable */ -#define _TIMER_IEN_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ -#define _TIMER_IEN_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ -#define _TIMER_IEN_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF0_DEFAULT (_TIMER_IEN_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF1 (0x1UL << 25) /**< ICFUF1 Interrupt Enable */ -#define _TIMER_IEN_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ -#define _TIMER_IEN_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ -#define _TIMER_IEN_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF1_DEFAULT (_TIMER_IEN_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF2 (0x1UL << 26) /**< ICFUF2 Interrupt Enable */ -#define _TIMER_IEN_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ -#define _TIMER_IEN_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ -#define _TIMER_IEN_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF2_DEFAULT (_TIMER_IEN_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ +#define _TIMER_IEN_MASK 0x07770077UL /**< Mask for TIMER_IEN */ +#define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ +#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */ +#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */ +#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0 (0x1UL << 16) /**< ICFWLFULL0 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0_DEFAULT (_TIMER_IEN_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1 (0x1UL << 17) /**< ICFWLFULL1 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1_DEFAULT (_TIMER_IEN_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2 (0x1UL << 18) /**< ICFWLFULL2 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2_DEFAULT (_TIMER_IEN_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0 (0x1UL << 20) /**< ICFOF0 Interrupt Enable */ +#define _TIMER_IEN_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0_DEFAULT (_TIMER_IEN_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1 (0x1UL << 21) /**< ICFOF1 Interrupt Enable */ +#define _TIMER_IEN_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1_DEFAULT (_TIMER_IEN_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2 (0x1UL << 22) /**< ICFOF2 Interrupt Enable */ +#define _TIMER_IEN_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2_DEFAULT (_TIMER_IEN_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0 (0x1UL << 24) /**< ICFUF0 Interrupt Enable */ +#define _TIMER_IEN_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0_DEFAULT (_TIMER_IEN_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1 (0x1UL << 25) /**< ICFUF1 Interrupt Enable */ +#define _TIMER_IEN_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1_DEFAULT (_TIMER_IEN_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2 (0x1UL << 26) /**< ICFUF2 Interrupt Enable */ +#define _TIMER_IEN_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2_DEFAULT (_TIMER_IEN_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IEN */ /* Bit fields for TIMER TOP */ -#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ -#define _TIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOP */ -#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ -#define _TIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ -#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ -#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ +#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ +#define _TIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _TIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ +#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ /* Bit fields for TIMER TOPB */ -#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ -#define _TIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOPB */ -#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ -#define _TIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ -#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ -#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ +#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ +#define _TIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ +#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ /* Bit fields for TIMER CNT */ -#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ -#define _TIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CNT */ -#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ -#define _TIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ -#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ -#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ +#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ +#define _TIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _TIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ +#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ /* Bit fields for TIMER LOCK */ -#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ -#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ -#define _TIMER_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ -#define _TIMER_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ -#define _TIMER_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ -#define _TIMER_LOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ -#define TIMER_LOCK_LOCKKEY_DEFAULT (_TIMER_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ -#define TIMER_LOCK_LOCKKEY_UNLOCK (_TIMER_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ +#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ +#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_DEFAULT (_TIMER_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_UNLOCK (_TIMER_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ /* Bit fields for TIMER EN */ -#define _TIMER_EN_RESETVALUE 0x00000000UL /**< Default value for TIMER_EN */ -#define _TIMER_EN_MASK 0x00000003UL /**< Mask for TIMER_EN */ -#define TIMER_EN_EN (0x1UL << 0) /**< Timer Module Enable */ -#define _TIMER_EN_EN_SHIFT 0 /**< Shift value for TIMER_EN */ -#define _TIMER_EN_EN_MASK 0x1UL /**< Bit mask for TIMER_EN */ -#define _TIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ -#define TIMER_EN_EN_DEFAULT (_TIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_EN */ -#define TIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _TIMER_EN_DISABLING_SHIFT 1 /**< Shift value for TIMER_DISABLING */ -#define _TIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for TIMER_DISABLING */ -#define _TIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ -#define TIMER_EN_DISABLING_DEFAULT (_TIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_EN */ +#define _TIMER_EN_RESETVALUE 0x00000000UL /**< Default value for TIMER_EN */ +#define _TIMER_EN_MASK 0x00000003UL /**< Mask for TIMER_EN */ +#define TIMER_EN_EN (0x1UL << 0) /**< Timer Module Enable */ +#define _TIMER_EN_EN_SHIFT 0 /**< Shift value for TIMER_EN */ +#define _TIMER_EN_EN_MASK 0x1UL /**< Bit mask for TIMER_EN */ +#define _TIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ +#define TIMER_EN_EN_DEFAULT (_TIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_EN */ +#define TIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _TIMER_EN_DISABLING_SHIFT 1 /**< Shift value for TIMER_DISABLING */ +#define _TIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for TIMER_DISABLING */ +#define _TIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ +#define TIMER_EN_DISABLING_DEFAULT (_TIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_EN */ /* Bit fields for TIMER CC_CFG */ -#define _TIMER_CC_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MASK 0x003E0013UL /**< Mask for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ -#define _TIMER_CC_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ -#define _TIMER_CC_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_DEFAULT (_TIMER_CC_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_OFF (_TIMER_CC_CFG_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_INPUTCAPTURE (_TIMER_CC_CFG_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_OUTPUTCOMPARE (_TIMER_CC_CFG_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_PWM (_TIMER_CC_CFG_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CFG */ -#define TIMER_CC_CFG_COIST (0x1UL << 4) /**< Compare Output Initial State */ -#define _TIMER_CC_CFG_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ -#define _TIMER_CC_CFG_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ -#define _TIMER_CC_CFG_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_COIST_DEFAULT (_TIMER_CC_CFG_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_SHIFT 17 /**< Shift value for TIMER_INSEL */ -#define _TIMER_CC_CFG_INSEL_MASK 0x60000UL /**< Bit mask for TIMER_INSEL */ -#define _TIMER_CC_CFG_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_PRSSYNC 0x00000001UL /**< Mode PRSSYNC for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL 0x00000002UL /**< Mode PRSASYNCLEVEL for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_PRSASYNCPULSE 0x00000003UL /**< Mode PRSASYNCPULSE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_DEFAULT (_TIMER_CC_CFG_INSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_PIN (_TIMER_CC_CFG_INSEL_PIN << 17) /**< Shifted mode PIN for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_PRSSYNC (_TIMER_CC_CFG_INSEL_PRSSYNC << 17) /**< Shifted mode PRSSYNC for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_PRSASYNCLEVEL (_TIMER_CC_CFG_INSEL_PRSASYNCLEVEL << 17) /**< Shifted mode PRSASYNCLEVEL for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_PRSASYNCPULSE (_TIMER_CC_CFG_INSEL_PRSASYNCPULSE << 17) /**< Shifted mode PRSASYNCPULSE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_PRSCONF (0x1UL << 19) /**< PRS Configuration */ -#define _TIMER_CC_CFG_PRSCONF_SHIFT 19 /**< Shift value for TIMER_PRSCONF */ -#define _TIMER_CC_CFG_PRSCONF_MASK 0x80000UL /**< Bit mask for TIMER_PRSCONF */ -#define _TIMER_CC_CFG_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CFG */ -#define TIMER_CC_CFG_PRSCONF_DEFAULT (_TIMER_CC_CFG_PRSCONF_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_PRSCONF_PULSE (_TIMER_CC_CFG_PRSCONF_PULSE << 19) /**< Shifted mode PULSE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_PRSCONF_LEVEL (_TIMER_CC_CFG_PRSCONF_LEVEL << 19) /**< Shifted mode LEVEL for TIMER_CC_CFG */ -#define TIMER_CC_CFG_FILT (0x1UL << 20) /**< Digital Filter */ -#define _TIMER_CC_CFG_FILT_SHIFT 20 /**< Shift value for TIMER_FILT */ -#define _TIMER_CC_CFG_FILT_MASK 0x100000UL /**< Bit mask for TIMER_FILT */ -#define _TIMER_CC_CFG_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_FILT_DEFAULT (_TIMER_CC_CFG_FILT_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_FILT_DISABLE (_TIMER_CC_CFG_FILT_DISABLE << 20) /**< Shifted mode DISABLE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_FILT_ENABLE (_TIMER_CC_CFG_FILT_ENABLE << 20) /**< Shifted mode ENABLE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_ICFWL (0x1UL << 21) /**< Input Capture FIFO watermark level */ -#define _TIMER_CC_CFG_ICFWL_SHIFT 21 /**< Shift value for TIMER_ICFWL */ -#define _TIMER_CC_CFG_ICFWL_MASK 0x200000UL /**< Bit mask for TIMER_ICFWL */ -#define _TIMER_CC_CFG_ICFWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_ICFWL_DEFAULT (_TIMER_CC_CFG_ICFWL_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MASK 0x003E0013UL /**< Mask for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_DEFAULT (_TIMER_CC_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OFF (_TIMER_CC_CFG_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_INPUTCAPTURE (_TIMER_CC_CFG_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OUTPUTCOMPARE (_TIMER_CC_CFG_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_PWM (_TIMER_CC_CFG_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _TIMER_CC_CFG_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST_DEFAULT (_TIMER_CC_CFG_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_SHIFT 17 /**< Shift value for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_MASK 0x60000UL /**< Bit mask for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSSYNC 0x00000001UL /**< Mode PRSSYNC for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL 0x00000002UL /**< Mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCPULSE 0x00000003UL /**< Mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_DEFAULT (_TIMER_CC_CFG_INSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PIN (_TIMER_CC_CFG_INSEL_PIN << 17) /**< Shifted mode PIN for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSSYNC (_TIMER_CC_CFG_INSEL_PRSSYNC << 17) /**< Shifted mode PRSSYNC for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCLEVEL (_TIMER_CC_CFG_INSEL_PRSASYNCLEVEL << 17) /**< Shifted mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCPULSE (_TIMER_CC_CFG_INSEL_PRSASYNCPULSE << 17) /**< Shifted mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF (0x1UL << 19) /**< PRS Configuration */ +#define _TIMER_CC_CFG_PRSCONF_SHIFT 19 /**< Shift value for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_MASK 0x80000UL /**< Bit mask for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_DEFAULT (_TIMER_CC_CFG_PRSCONF_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_PULSE (_TIMER_CC_CFG_PRSCONF_PULSE << 19) /**< Shifted mode PULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_LEVEL (_TIMER_CC_CFG_PRSCONF_LEVEL << 19) /**< Shifted mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT (0x1UL << 20) /**< Digital Filter */ +#define _TIMER_CC_CFG_FILT_SHIFT 20 /**< Shift value for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_MASK 0x100000UL /**< Bit mask for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DEFAULT (_TIMER_CC_CFG_FILT_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DISABLE (_TIMER_CC_CFG_FILT_DISABLE << 20) /**< Shifted mode DISABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_ENABLE (_TIMER_CC_CFG_FILT_ENABLE << 20) /**< Shifted mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL (0x1UL << 21) /**< Input Capture FIFO watermark level */ +#define _TIMER_CC_CFG_ICFWL_SHIFT 21 /**< Shift value for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_MASK 0x200000UL /**< Bit mask for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL_DEFAULT (_TIMER_CC_CFG_ICFWL_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ /* Bit fields for TIMER CC_CTRL */ -#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_MASK 0x0F003F04UL /**< Mask for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ -#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ -#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ -#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ -#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ -#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ -#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ -#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ -#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ -#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ -#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ -#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL*/ -#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MASK 0x0F003F04UL /**< Mask for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL*/ +#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ /* Bit fields for TIMER CC_OC */ -#define _TIMER_CC_OC_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OC */ -#define _TIMER_CC_OC_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OC */ -#define _TIMER_CC_OC_OC_SHIFT 0 /**< Shift value for TIMER_OC */ -#define _TIMER_CC_OC_OC_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OC */ -#define _TIMER_CC_OC_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OC */ -#define TIMER_CC_OC_OC_DEFAULT (_TIMER_CC_OC_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OC */ +#define _TIMER_CC_OC_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OC */ +#define _TIMER_CC_OC_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OC */ +#define _TIMER_CC_OC_OC_SHIFT 0 /**< Shift value for TIMER_OC */ +#define _TIMER_CC_OC_OC_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OC */ +#define _TIMER_CC_OC_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OC */ +#define TIMER_CC_OC_OC_DEFAULT (_TIMER_CC_OC_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OC */ /* Bit fields for TIMER CC_OCB */ -#define _TIMER_CC_OCB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OCB */ -#define _TIMER_CC_OCB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OCB */ -#define _TIMER_CC_OCB_OCB_SHIFT 0 /**< Shift value for TIMER_OCB */ -#define _TIMER_CC_OCB_OCB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OCB */ -#define _TIMER_CC_OCB_OCB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OCB */ -#define TIMER_CC_OCB_OCB_DEFAULT (_TIMER_CC_OCB_OCB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_OCB_SHIFT 0 /**< Shift value for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OCB */ +#define TIMER_CC_OCB_OCB_DEFAULT (_TIMER_CC_OCB_OCB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OCB */ /* Bit fields for TIMER CC_ICF */ -#define _TIMER_CC_ICF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICF */ -#define _TIMER_CC_ICF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICF */ -#define _TIMER_CC_ICF_ICF_SHIFT 0 /**< Shift value for TIMER_ICF */ -#define _TIMER_CC_ICF_ICF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICF */ -#define _TIMER_CC_ICF_ICF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICF */ -#define TIMER_CC_ICF_ICF_DEFAULT (_TIMER_CC_ICF_ICF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_ICF_SHIFT 0 /**< Shift value for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICF */ +#define TIMER_CC_ICF_ICF_DEFAULT (_TIMER_CC_ICF_ICF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICF */ /* Bit fields for TIMER CC_ICOF */ -#define _TIMER_CC_ICOF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICOF */ -#define _TIMER_CC_ICOF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICOF */ -#define _TIMER_CC_ICOF_ICOF_SHIFT 0 /**< Shift value for TIMER_ICOF */ -#define _TIMER_CC_ICOF_ICOF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICOF */ -#define _TIMER_CC_ICOF_ICOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICOF */ -#define TIMER_CC_ICOF_ICOF_DEFAULT (_TIMER_CC_ICOF_ICOF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_ICOF_SHIFT 0 /**< Shift value for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICOF */ +#define TIMER_CC_ICOF_ICOF_DEFAULT (_TIMER_CC_ICOF_ICOF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICOF */ /* Bit fields for TIMER DTCFG */ -#define _TIMER_DTCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCFG */ -#define _TIMER_DTCFG_MASK 0x00000E03UL /**< Mask for TIMER_DTCFG */ -#define TIMER_DTCFG_DTEN (0x1UL << 0) /**< DTI Enable */ -#define _TIMER_DTCFG_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ -#define _TIMER_DTCFG_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ -#define _TIMER_DTCFG_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTEN_DEFAULT (_TIMER_DTCFG_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ -#define _TIMER_DTCFG_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ -#define _TIMER_DTCFG_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ -#define _TIMER_DTCFG_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define _TIMER_DTCFG_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCFG */ -#define _TIMER_DTCFG_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCFG */ -#define TIMER_DTCFG_DTDAS_DEFAULT (_TIMER_DTCFG_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTDAS_NORESTART (_TIMER_DTCFG_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCFG */ -#define TIMER_DTCFG_DTDAS_RESTART (_TIMER_DTCFG_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCFG */ -#define TIMER_DTCFG_DTAR (0x1UL << 9) /**< DTI Always Run */ -#define _TIMER_DTCFG_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ -#define _TIMER_DTCFG_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ -#define _TIMER_DTCFG_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTAR_DEFAULT (_TIMER_DTCFG_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ -#define _TIMER_DTCFG_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ -#define _TIMER_DTCFG_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ -#define _TIMER_DTCFG_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTFATS_DEFAULT (_TIMER_DTCFG_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTPRSEN (0x1UL << 11) /**< DTI PRS Source Enable */ -#define _TIMER_DTCFG_DTPRSEN_SHIFT 11 /**< Shift value for TIMER_DTPRSEN */ -#define _TIMER_DTCFG_DTPRSEN_MASK 0x800UL /**< Bit mask for TIMER_DTPRSEN */ -#define _TIMER_DTCFG_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTPRSEN_DEFAULT (_TIMER_DTCFG_DTPRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define _TIMER_DTCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCFG */ +#define _TIMER_DTCFG_MASK 0x00000E03UL /**< Mask for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _TIMER_DTCFG_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN_DEFAULT (_TIMER_DTCFG_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _TIMER_DTCFG_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_DEFAULT (_TIMER_DTCFG_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_NORESTART (_TIMER_DTCFG_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_RESTART (_TIMER_DTCFG_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _TIMER_DTCFG_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR_DEFAULT (_TIMER_DTCFG_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _TIMER_DTCFG_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS_DEFAULT (_TIMER_DTCFG_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN (0x1UL << 11) /**< DTI PRS Source Enable */ +#define _TIMER_DTCFG_DTPRSEN_SHIFT 11 /**< Shift value for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_MASK 0x800UL /**< Bit mask for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN_DEFAULT (_TIMER_DTCFG_DTPRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_DTCFG */ /* Bit fields for TIMER DTTIMECFG */ -#define _TIMER_DTTIMECFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIMECFG */ -#define _TIMER_DTTIMECFG_MASK 0x003FFFFFUL /**< Mask for TIMER_DTTIMECFG */ -#define _TIMER_DTTIMECFG_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ -#define _TIMER_DTTIMECFG_DTPRESC_MASK 0x3FFUL /**< Bit mask for TIMER_DTPRESC */ -#define _TIMER_DTTIMECFG_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ -#define TIMER_DTTIMECFG_DTPRESC_DEFAULT (_TIMER_DTTIMECFG_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ -#define _TIMER_DTTIMECFG_DTRISET_SHIFT 10 /**< Shift value for TIMER_DTRISET */ -#define _TIMER_DTTIMECFG_DTRISET_MASK 0xFC00UL /**< Bit mask for TIMER_DTRISET */ -#define _TIMER_DTTIMECFG_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ -#define TIMER_DTTIMECFG_DTRISET_DEFAULT (_TIMER_DTTIMECFG_DTRISET_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ -#define _TIMER_DTTIMECFG_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ -#define _TIMER_DTTIMECFG_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ -#define _TIMER_DTTIMECFG_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ -#define TIMER_DTTIMECFG_DTFALLT_DEFAULT (_TIMER_DTTIMECFG_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_MASK 0x003FFFFFUL /**< Mask for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_MASK 0x3FFUL /**< Bit mask for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTPRESC_DEFAULT (_TIMER_DTTIMECFG_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTRISET_SHIFT 10 /**< Shift value for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_MASK 0xFC00UL /**< Bit mask for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTRISET_DEFAULT (_TIMER_DTTIMECFG_DTRISET_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTFALLT_DEFAULT (_TIMER_DTTIMECFG_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ /* Bit fields for TIMER DTFCFG */ -#define _TIMER_DTFCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_MASK 0x1F030000UL /**< Mask for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ -#define _TIMER_DTFCFG_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ -#define _TIMER_DTFCFG_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_DEFAULT (_TIMER_DTFCFG_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_NONE (_TIMER_DTFCFG_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_INACTIVE (_TIMER_DTFCFG_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_CLEAR (_TIMER_DTFCFG_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_TRISTATE (_TIMER_DTFCFG_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ -#define _TIMER_DTFCFG_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ -#define _TIMER_DTFCFG_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ -#define _TIMER_DTFCFG_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTPRS0FEN_DEFAULT (_TIMER_DTFCFG_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ -#define _TIMER_DTFCFG_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ -#define _TIMER_DTFCFG_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ -#define _TIMER_DTFCFG_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTPRS1FEN_DEFAULT (_TIMER_DTFCFG_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ -#define _TIMER_DTFCFG_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ -#define _TIMER_DTFCFG_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ -#define _TIMER_DTFCFG_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTDBGFEN_DEFAULT (_TIMER_DTFCFG_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ -#define _TIMER_DTFCFG_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ -#define _TIMER_DTFCFG_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ -#define _TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT (_TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTEM23FEN (0x1UL << 28) /**< DTI EM23 Fault Enable */ -#define _TIMER_DTFCFG_DTEM23FEN_SHIFT 28 /**< Shift value for TIMER_DTEM23FEN */ -#define _TIMER_DTFCFG_DTEM23FEN_MASK 0x10000000UL /**< Bit mask for TIMER_DTEM23FEN */ -#define _TIMER_DTFCFG_DTEM23FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTEM23FEN_DEFAULT (_TIMER_DTFCFG_DTEM23FEN_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_MASK 0x1F030000UL /**< Mask for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_DEFAULT (_TIMER_DTFCFG_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_NONE (_TIMER_DTFCFG_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_INACTIVE (_TIMER_DTFCFG_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_CLEAR (_TIMER_DTFCFG_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_TRISTATE (_TIMER_DTFCFG_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN_DEFAULT (_TIMER_DTFCFG_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN_DEFAULT (_TIMER_DTFCFG_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _TIMER_DTFCFG_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN_DEFAULT (_TIMER_DTFCFG_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT (_TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN (0x1UL << 28) /**< DTI EM23 Fault Enable */ +#define _TIMER_DTFCFG_DTEM23FEN_SHIFT 28 /**< Shift value for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_MASK 0x10000000UL /**< Bit mask for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN_DEFAULT (_TIMER_DTFCFG_DTEM23FEN_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ /* Bit fields for TIMER DTCTRL */ -#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ -#define _TIMER_DTCTRL_MASK 0x00000003UL /**< Mask for TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTCINV (0x1UL << 0) /**< DTI Complementary Output Invert. */ -#define _TIMER_DTCTRL_DTCINV_SHIFT 0 /**< Shift value for TIMER_DTCINV */ -#define _TIMER_DTCTRL_DTCINV_MASK 0x1UL /**< Bit mask for TIMER_DTCINV */ -#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTIPOL (0x1UL << 1) /**< DTI Inactive Polarity */ -#define _TIMER_DTCTRL_DTIPOL_SHIFT 1 /**< Shift value for TIMER_DTIPOL */ -#define _TIMER_DTCTRL_DTIPOL_MASK 0x2UL /**< Bit mask for TIMER_DTIPOL */ -#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_MASK 0x00000003UL /**< Mask for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV (0x1UL << 0) /**< DTI Complementary Output Invert. */ +#define _TIMER_DTCTRL_DTCINV_SHIFT 0 /**< Shift value for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_MASK 0x1UL /**< Bit mask for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL (0x1UL << 1) /**< DTI Inactive Polarity */ +#define _TIMER_DTCTRL_DTIPOL_SHIFT 1 /**< Shift value for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_MASK 0x2UL /**< Bit mask for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ /* Bit fields for TIMER DTOGEN */ -#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ -#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CCn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ -#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ -#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CCn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ -#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ -#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CCn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ -#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ -#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTIn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ -#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ -#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTIn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ -#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ -#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTIn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ -#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ -#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ /* Bit fields for TIMER DTFAULT */ -#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ -#define _TIMER_DTFAULT_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ -#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ -#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ -#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ -#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ -#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ -#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ -#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ -#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ -#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ -#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ -#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ -#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTEM23F (0x1UL << 4) /**< DTI EM23 Entry Fault */ -#define _TIMER_DTFAULT_DTEM23F_SHIFT 4 /**< Shift value for TIMER_DTEM23F */ -#define _TIMER_DTFAULT_DTEM23F_MASK 0x10UL /**< Bit mask for TIMER_DTEM23F */ -#define _TIMER_DTFAULT_DTEM23F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTEM23F_DEFAULT (_TIMER_DTFAULT_DTEM23F_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F (0x1UL << 4) /**< DTI EM23 Entry Fault */ +#define _TIMER_DTFAULT_DTEM23F_SHIFT 4 /**< Shift value for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_MASK 0x10UL /**< Bit mask for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F_DEFAULT (_TIMER_DTFAULT_DTEM23F_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ /* Bit fields for TIMER DTFAULTC */ -#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ -#define _TIMER_DTFAULTC_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ -#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ -#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ -#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ -#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ -#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ -#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ -#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ -#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ -#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ -#define _TIMER_DTFAULTC_DTLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPFC */ -#define _TIMER_DTFAULTC_DTLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPFC */ -#define _TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTEM23FC (0x1UL << 4) /**< DTI EM23 Fault Clear */ -#define _TIMER_DTFAULTC_DTEM23FC_SHIFT 4 /**< Shift value for TIMER_DTEM23FC */ -#define _TIMER_DTFAULTC_DTEM23FC_MASK 0x10UL /**< Bit mask for TIMER_DTEM23FC */ -#define _TIMER_DTFAULTC_DTEM23FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTEM23FC_DEFAULT (_TIMER_DTFAULTC_DTEM23FC_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC (0x1UL << 4) /**< DTI EM23 Fault Clear */ +#define _TIMER_DTFAULTC_DTEM23FC_SHIFT 4 /**< Shift value for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_MASK 0x10UL /**< Bit mask for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC_DEFAULT (_TIMER_DTFAULTC_DTEM23FC_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ /* Bit fields for TIMER DTLOCK */ -#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ -#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ -#define _TIMER_DTLOCK_DTILOCKKEY_SHIFT 0 /**< Shift value for TIMER_DTILOCKKEY */ -#define _TIMER_DTLOCK_DTILOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_DTILOCKKEY */ -#define _TIMER_DTLOCK_DTILOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ -#define _TIMER_DTLOCK_DTILOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ -#define TIMER_DTLOCK_DTILOCKKEY_DEFAULT (_TIMER_DTLOCK_DTILOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ -#define TIMER_DTLOCK_DTILOCKKEY_UNLOCK (_TIMER_DTLOCK_DTILOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_SHIFT 0 /**< Shift value for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_DEFAULT (_TIMER_DTLOCK_DTILOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_UNLOCK (_TIMER_DTLOCK_DTILOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ /** @} End of group EFR32SG23_TIMER_BitFields */ /** @} End of group EFR32SG23_TIMER */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ulfrco.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ulfrco.h index 303826f825..ee312766d1 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_ulfrco.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_ULFRCO_H #define EFR32SG23_ULFRCO_H - #define ULFRCO_HAS_SET_CLEAR /**************************************************************************//** @@ -43,35 +42,34 @@ *****************************************************************************/ /** ULFRCO Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - uint32_t RESERVED1[2U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED2[1017U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED5[1017U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - uint32_t RESERVED7[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED8[1017U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - uint32_t RESERVED10[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED8[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED10[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ } ULFRCO_TypeDef; /** @} End of group EFR32SG23_ULFRCO */ @@ -83,64 +81,64 @@ typedef struct *****************************************************************************/ /* Bit fields for ULFRCO IPVERSION */ -#define _ULFRCO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ULFRCO_IPVERSION */ -#define _ULFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ULFRCO_IPVERSION */ -#define _ULFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ULFRCO_IPVERSION */ -#define _ULFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ULFRCO_IPVERSION */ -#define _ULFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ULFRCO_IPVERSION */ -#define ULFRCO_IPVERSION_IPVERSION_DEFAULT (_ULFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ULFRCO_IPVERSION */ +#define ULFRCO_IPVERSION_IPVERSION_DEFAULT (_ULFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IPVERSION */ /* Bit fields for ULFRCO STATUS */ -#define _ULFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_STATUS */ -#define _ULFRCO_STATUS_MASK 0x00010001UL /**< Mask for ULFRCO_STATUS */ -#define ULFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ -#define _ULFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ -#define _ULFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ -#define _ULFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ -#define ULFRCO_STATUS_RDY_DEFAULT (_ULFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ -#define ULFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ -#define _ULFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for ULFRCO_ENS */ -#define _ULFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for ULFRCO_ENS */ -#define _ULFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ -#define ULFRCO_STATUS_ENS_DEFAULT (_ULFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ +#define _ULFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_STATUS */ +#define _ULFRCO_STATUS_MASK 0x00010001UL /**< Mask for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _ULFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY_DEFAULT (_ULFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _ULFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS_DEFAULT (_ULFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ /* Bit fields for ULFRCO IF */ -#define _ULFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IF */ -#define _ULFRCO_IF_MASK 0x00000007UL /**< Mask for ULFRCO_IF */ -#define ULFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ -#define _ULFRCO_IF_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ -#define _ULFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ -#define _ULFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_RDY_DEFAULT (_ULFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_POSEDGE (0x1UL << 1) /**< Positive Edge Interrupt Flag */ -#define _ULFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ -#define _ULFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ -#define _ULFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_POSEDGE_DEFAULT (_ULFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_NEGEDGE (0x1UL << 2) /**< Negative Edge Interrupt Flag */ -#define _ULFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ -#define _ULFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ -#define _ULFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_NEGEDGE_DEFAULT (_ULFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define _ULFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IF */ +#define _ULFRCO_IF_MASK 0x00000007UL /**< Mask for ULFRCO_IF */ +#define ULFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _ULFRCO_IF_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_RDY_DEFAULT (_ULFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE (0x1UL << 1) /**< Positive Edge Interrupt Flag */ +#define _ULFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE_DEFAULT (_ULFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE (0x1UL << 2) /**< Negative Edge Interrupt Flag */ +#define _ULFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE_DEFAULT (_ULFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IF */ /* Bit fields for ULFRCO IEN */ -#define _ULFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IEN */ -#define _ULFRCO_IEN_MASK 0x00000007UL /**< Mask for ULFRCO_IEN */ -#define ULFRCO_IEN_RDY (0x1UL << 0) /**< Enable Ready Interrupt */ -#define _ULFRCO_IEN_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ -#define _ULFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ -#define _ULFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_RDY_DEFAULT (_ULFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_POSEDGE (0x1UL << 1) /**< Enable Positive Edge Interrupt */ -#define _ULFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ -#define _ULFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ -#define _ULFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_POSEDGE_DEFAULT (_ULFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Enable Negative Edge Interrupt */ -#define _ULFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ -#define _ULFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ -#define _ULFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_NEGEDGE_DEFAULT (_ULFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define _ULFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IEN */ +#define _ULFRCO_IEN_MASK 0x00000007UL /**< Mask for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY (0x1UL << 0) /**< Enable Ready Interrupt */ +#define _ULFRCO_IEN_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY_DEFAULT (_ULFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE (0x1UL << 1) /**< Enable Positive Edge Interrupt */ +#define _ULFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE_DEFAULT (_ULFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Enable Negative Edge Interrupt */ +#define _ULFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE_DEFAULT (_ULFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IEN */ /** @} End of group EFR32SG23_ULFRCO_BitFields */ /** @} End of group EFR32SG23_ULFRCO */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_usart.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_usart.h index 7a3d1366a0..96f1c56a1a 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_usart.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_usart.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_USART_H #define EFR32SG23_USART_H - #define USART_HAS_SET_CLEAR /**************************************************************************//** @@ -43,119 +42,118 @@ *****************************************************************************/ /** USART Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< USART Enable */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t FRAME; /**< USART Frame Format Register */ - __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< USART Status Register */ - __IOM uint32_t CLKDIV; /**< Clock Control Register */ - __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ - __IM uint32_t RXDATA; /**< RX Buffer Data Register */ - __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ - __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ - __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ - __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek R... */ - __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ - __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ - __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ - __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t IRCTRL; /**< IrDA Control Register */ - __IOM uint32_t I2SCTRL; /**< I2S Control Register */ - __IOM uint32_t TIMING; /**< Timing Register */ - __IOM uint32_t CTRLX; /**< Control Register Extended */ - __IOM uint32_t TIMECMP0; /**< Timer Compare 0 */ - __IOM uint32_t TIMECMP1; /**< Timer Compare 1 */ - __IOM uint32_t TIMECMP2; /**< Timer Compare 2 */ - uint32_t RESERVED0[997U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< USART Enable */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t FRAME_SET; /**< USART Frame Format Register */ - __IOM uint32_t TRIGCTRL_SET; /**< USART Trigger Control register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< USART Status Register */ - __IOM uint32_t CLKDIV_SET; /**< Clock Control Register */ - __IM uint32_t RXDATAX_SET; /**< RX Buffer Data Extended Register */ - __IM uint32_t RXDATA_SET; /**< RX Buffer Data Register */ - __IM uint32_t RXDOUBLEX_SET; /**< RX Buffer Double Data Extended Register */ - __IM uint32_t RXDOUBLE_SET; /**< RX FIFO Double Data Register */ - __IM uint32_t RXDATAXP_SET; /**< RX Buffer Data Extended Peek Register */ - __IM uint32_t RXDOUBLEXP_SET; /**< RX Buffer Double Data Extended Peek R... */ - __IOM uint32_t TXDATAX_SET; /**< TX Buffer Data Extended Register */ - __IOM uint32_t TXDATA_SET; /**< TX Buffer Data Register */ - __IOM uint32_t TXDOUBLEX_SET; /**< TX Buffer Double Data Extended Register */ - __IOM uint32_t TXDOUBLE_SET; /**< TX Buffer Double Data Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t IRCTRL_SET; /**< IrDA Control Register */ - __IOM uint32_t I2SCTRL_SET; /**< I2S Control Register */ - __IOM uint32_t TIMING_SET; /**< Timing Register */ - __IOM uint32_t CTRLX_SET; /**< Control Register Extended */ - __IOM uint32_t TIMECMP0_SET; /**< Timer Compare 0 */ - __IOM uint32_t TIMECMP1_SET; /**< Timer Compare 1 */ - __IOM uint32_t TIMECMP2_SET; /**< Timer Compare 2 */ - uint32_t RESERVED1[997U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< USART Enable */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t FRAME_CLR; /**< USART Frame Format Register */ - __IOM uint32_t TRIGCTRL_CLR; /**< USART Trigger Control register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< USART Status Register */ - __IOM uint32_t CLKDIV_CLR; /**< Clock Control Register */ - __IM uint32_t RXDATAX_CLR; /**< RX Buffer Data Extended Register */ - __IM uint32_t RXDATA_CLR; /**< RX Buffer Data Register */ - __IM uint32_t RXDOUBLEX_CLR; /**< RX Buffer Double Data Extended Register */ - __IM uint32_t RXDOUBLE_CLR; /**< RX FIFO Double Data Register */ - __IM uint32_t RXDATAXP_CLR; /**< RX Buffer Data Extended Peek Register */ - __IM uint32_t RXDOUBLEXP_CLR; /**< RX Buffer Double Data Extended Peek R... */ - __IOM uint32_t TXDATAX_CLR; /**< TX Buffer Data Extended Register */ - __IOM uint32_t TXDATA_CLR; /**< TX Buffer Data Register */ - __IOM uint32_t TXDOUBLEX_CLR; /**< TX Buffer Double Data Extended Register */ - __IOM uint32_t TXDOUBLE_CLR; /**< TX Buffer Double Data Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t IRCTRL_CLR; /**< IrDA Control Register */ - __IOM uint32_t I2SCTRL_CLR; /**< I2S Control Register */ - __IOM uint32_t TIMING_CLR; /**< Timing Register */ - __IOM uint32_t CTRLX_CLR; /**< Control Register Extended */ - __IOM uint32_t TIMECMP0_CLR; /**< Timer Compare 0 */ - __IOM uint32_t TIMECMP1_CLR; /**< Timer Compare 1 */ - __IOM uint32_t TIMECMP2_CLR; /**< Timer Compare 2 */ - uint32_t RESERVED2[997U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< USART Enable */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t FRAME_TGL; /**< USART Frame Format Register */ - __IOM uint32_t TRIGCTRL_TGL; /**< USART Trigger Control register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< USART Status Register */ - __IOM uint32_t CLKDIV_TGL; /**< Clock Control Register */ - __IM uint32_t RXDATAX_TGL; /**< RX Buffer Data Extended Register */ - __IM uint32_t RXDATA_TGL; /**< RX Buffer Data Register */ - __IM uint32_t RXDOUBLEX_TGL; /**< RX Buffer Double Data Extended Register */ - __IM uint32_t RXDOUBLE_TGL; /**< RX FIFO Double Data Register */ - __IM uint32_t RXDATAXP_TGL; /**< RX Buffer Data Extended Peek Register */ - __IM uint32_t RXDOUBLEXP_TGL; /**< RX Buffer Double Data Extended Peek R... */ - __IOM uint32_t TXDATAX_TGL; /**< TX Buffer Data Extended Register */ - __IOM uint32_t TXDATA_TGL; /**< TX Buffer Data Register */ - __IOM uint32_t TXDOUBLEX_TGL; /**< TX Buffer Double Data Extended Register */ - __IOM uint32_t TXDOUBLE_TGL; /**< TX Buffer Double Data Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t IRCTRL_TGL; /**< IrDA Control Register */ - __IOM uint32_t I2SCTRL_TGL; /**< I2S Control Register */ - __IOM uint32_t TIMING_TGL; /**< Timing Register */ - __IOM uint32_t CTRLX_TGL; /**< Control Register Extended */ - __IOM uint32_t TIMECMP0_TGL; /**< Timer Compare 0 */ - __IOM uint32_t TIMECMP1_TGL; /**< Timer Compare 1 */ - __IOM uint32_t TIMECMP2_TGL; /**< Timer Compare 2 */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< USART Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t FRAME; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< USART Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL; /**< I2S Control Register */ + __IOM uint32_t TIMING; /**< Timing Register */ + __IOM uint32_t CTRLX; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2; /**< Timer Compare 2 */ + uint32_t RESERVED0[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< USART Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t FRAME_SET; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_SET; /**< USART Trigger Control register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< USART Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Control Register */ + __IM uint32_t RXDATAX_SET; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_SET; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_SET; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_SET; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_SET; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_SET; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_SET; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_SET; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_SET; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_SET; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_SET; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_SET; /**< I2S Control Register */ + __IOM uint32_t TIMING_SET; /**< Timing Register */ + __IOM uint32_t CTRLX_SET; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_SET; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_SET; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_SET; /**< Timer Compare 2 */ + uint32_t RESERVED1[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< USART Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t FRAME_CLR; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< USART Trigger Control register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< USART Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Control Register */ + __IM uint32_t RXDATAX_CLR; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_CLR; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_CLR; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_CLR; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_CLR; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_CLR; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_CLR; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_CLR; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_CLR; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_CLR; /**< I2S Control Register */ + __IOM uint32_t TIMING_CLR; /**< Timing Register */ + __IOM uint32_t CTRLX_CLR; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_CLR; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_CLR; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_CLR; /**< Timer Compare 2 */ + uint32_t RESERVED2[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< USART Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t FRAME_TGL; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< USART Trigger Control register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< USART Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Control Register */ + __IM uint32_t RXDATAX_TGL; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_TGL; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_TGL; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_TGL; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_TGL; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_TGL; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_TGL; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_TGL; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_TGL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_TGL; /**< I2S Control Register */ + __IOM uint32_t TIMING_TGL; /**< Timing Register */ + __IOM uint32_t CTRLX_TGL; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_TGL; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_TGL; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_TGL; /**< Timer Compare 2 */ } USART_TypeDef; /** @} End of group EFR32SG23_USART */ @@ -167,11 +165,11 @@ typedef struct *****************************************************************************/ /* Bit fields for USART IPVERSION */ -#define _USART_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for USART_IPVERSION */ -#define _USART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for USART_IPVERSION */ -#define _USART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for USART_IPVERSION */ -#define _USART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for USART_IPVERSION */ -#define _USART_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IPVERSION */ +#define _USART_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for USART_IPVERSION */ +#define _USART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IPVERSION */ #define USART_IPVERSION_IPVERSION_DEFAULT (_USART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IPVERSION */ /* Bit fields for USART EN */ @@ -184,327 +182,327 @@ typedef struct #define USART_EN_EN_DEFAULT (_USART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_EN */ /* Bit fields for USART CTRL */ -#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ -#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ -#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ -#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ -#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ -#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SYNC_DISABLE (_USART_CTRL_SYNC_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_SYNC_ENABLE (_USART_CTRL_SYNC_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ -#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ -#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ -#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_LOOPBK_DISABLE (_USART_CTRL_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_LOOPBK_ENABLE (_USART_CTRL_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ -#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ -#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ -#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CCEN_DISABLE (_USART_CTRL_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_CCEN_ENABLE (_USART_CTRL_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ -#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ -#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ -#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MPM_DISABLE (_USART_CTRL_MPM_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_MPM_ENABLE (_USART_CTRL_MPM_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ -#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ -#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ -#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ -#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ -#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ -#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ -#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ -#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ -#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ -#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ -#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ -#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ -#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ -#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ -#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ -#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ -#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ -#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ -#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ -#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ -#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ -#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ -#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ -#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ -#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ +#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ +#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ +#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ +#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ +#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ +#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SYNC_DISABLE (_USART_CTRL_SYNC_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_SYNC_ENABLE (_USART_CTRL_SYNC_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK_DISABLE (_USART_CTRL_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_ENABLE (_USART_CTRL_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ +#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ +#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN_DISABLE (_USART_CTRL_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CCEN_ENABLE (_USART_CTRL_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ +#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ +#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM_DISABLE (_USART_CTRL_MPM_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MPM_ENABLE (_USART_CTRL_MPM_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ +#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ +#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ +#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ +#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ +#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ +#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ +#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ +#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ +#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ +#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ +#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ +#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ +#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ +#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ #define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ -#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ -#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ -#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ -#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MSBF_DISABLE (_USART_CTRL_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_MSBF_ENABLE (_USART_CTRL_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Chip Select In Main Mode */ -#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ -#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ -#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ -#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ -#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ -#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ -#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ -#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ -#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ -#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ -#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ -#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ -#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ -#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ -#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ -#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ -#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_RXINV_DISABLE (_USART_CTRL_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_RXINV_ENABLE (_USART_CTRL_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ -#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ -#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ -#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_TXINV_DISABLE (_USART_CTRL_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_TXINV_ENABLE (_USART_CTRL_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ -#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ -#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ -#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_CSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CSINV_DISABLE (_USART_CTRL_CSINV_DISABLE << 15) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_CSINV_ENABLE (_USART_CTRL_CSINV_ENABLE << 15) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ -#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ -#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ -#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ -#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ -#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ -#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_AUTOTRI_DISABLE (_USART_CTRL_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_AUTOTRI_ENABLE (_USART_CTRL_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ -#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ -#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ -#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ -#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ -#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ -#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ -#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ -#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ -#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ -#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ -#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ -#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ -#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ -#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ -#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_ERRSDMA_DISABLE (_USART_CTRL_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_ERRSDMA_ENABLE (_USART_CTRL_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ -#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ -#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ -#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_ERRSRX_DISABLE (_USART_CTRL_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_ERRSRX_ENABLE (_USART_CTRL_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ -#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ -#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ -#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_ERRSTX_DISABLE (_USART_CTRL_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_ERRSTX_ENABLE (_USART_CTRL_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Secondary Setup Early */ -#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ -#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ -#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ -#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ -#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ -#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_BYTESWAP_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_BYTESWAP_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_BYTESWAP_DISABLE (_USART_CTRL_BYTESWAP_DISABLE << 28) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_BYTESWAP_ENABLE (_USART_CTRL_BYTESWAP_ENABLE << 28) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ -#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ -#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ -#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ -#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ -#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ -#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Main Sample Delay */ -#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ -#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ -#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ +#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ +#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MSBF_DISABLE (_USART_CTRL_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MSBF_ENABLE (_USART_CTRL_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Chip Select In Main Mode */ +#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ +#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ +#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ +#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ +#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ +#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ +#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ +#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ +#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ +#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ +#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ +#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ +#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ +#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_RXINV_DISABLE (_USART_CTRL_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_RXINV_ENABLE (_USART_CTRL_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ +#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ +#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV_DISABLE (_USART_CTRL_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_TXINV_ENABLE (_USART_CTRL_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ +#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ +#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ +#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV_DISABLE (_USART_CTRL_CSINV_DISABLE << 15) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CSINV_ENABLE (_USART_CTRL_CSINV_ENABLE << 15) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ +#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DISABLE (_USART_CTRL_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_ENABLE (_USART_CTRL_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ +#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ +#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ +#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ +#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ +#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ +#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DISABLE (_USART_CTRL_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_ENABLE (_USART_CTRL_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX_DISABLE (_USART_CTRL_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_ENABLE (_USART_CTRL_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX_DISABLE (_USART_CTRL_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_ENABLE (_USART_CTRL_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Secondary Setup Early */ +#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ +#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DISABLE (_USART_CTRL_BYTESWAP_DISABLE << 28) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_ENABLE (_USART_CTRL_BYTESWAP_ENABLE << 28) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ +#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ +#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ +#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Main Sample Delay */ +#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ /* Bit fields for USART FRAME */ -#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ -#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ -#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ -#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ -#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ -#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ -#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ -#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ -#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ -#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ -#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ -#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ -#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ -#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ -#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ -#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ -#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ -#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ -#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ -#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ -#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ -#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ -#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ -#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ -#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ -#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ -#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ -#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ -#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ -#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ -#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ -#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ -#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ -#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ -#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ -#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ -#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ -#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ -#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ -#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ -#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ -#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ -#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ -#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ -#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ -#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ +#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ +#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ +#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ +#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ +#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ +#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ +#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ +#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ +#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ +#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ +#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ +#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ +#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ +#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ +#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ +#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ +#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ +#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ +#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ +#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ +#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ +#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ +#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ +#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ +#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ #define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ -#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ +#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ /* Bit fields for USART TRIGCTRL */ -#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ -#define _USART_TRIGCTRL_MASK 0x00001FF0UL /**< Mask for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ -#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ -#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ -#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ -#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ -#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ -#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ -#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ -#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ -#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_MASK 0x00001FF0UL /**< Mask for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ +#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ +#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ +#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of */ -#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ -#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ -#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of */ -#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ -#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ -#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of */ -#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ -#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ -#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of f */ -#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ -#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ -#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of f */ -#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ -#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ -#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of f */ -#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ -#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ -#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ /* Bit fields for USART CMD */ @@ -572,99 +570,99 @@ typedef struct #define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ /* Bit fields for USART STATUS */ -#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ -#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ -#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ -#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ -#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ -#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ -#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ -#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ -#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Main Mode */ -#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ -#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ -#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ -#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ -#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ -#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ -#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ -#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ -#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ -#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ -#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ -#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ -#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ -#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ -#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ -#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ -#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ -#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ -#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ -#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ -#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ -#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ -#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ -#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ -#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ -#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ -#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ -#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ -#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ -#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ -#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ -#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ -#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ -#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ -#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ -#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ -#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ -#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ -#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ +#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ +#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ +#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ +#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ +#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ +#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Main Mode */ +#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ +#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ +#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ +#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ +#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ +#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ +#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ +#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ +#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ +#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ +#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ +#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ +#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ +#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ +#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ +#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ +#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ +#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ -#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ -#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ -#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ /* Bit fields for USART CLKDIV */ -#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ -#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ -#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ -#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ -#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ -#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ -#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ -#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ -#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ -#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ +#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ +#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ +#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ +#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ #define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ /* Bit fields for USART RXDATAX */ @@ -694,36 +692,36 @@ typedef struct #define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ /* Bit fields for USART RXDOUBLEX */ -#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ -#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ -#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ -#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ -#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ -#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ -#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ -#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ -#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ -#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ -#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ -#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ -#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ +#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ +#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ #define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ -#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ -#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ -#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ -#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ -#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ -#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ +#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ +#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ /* Bit fields for USART RXDOUBLE */ #define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ @@ -756,36 +754,36 @@ typedef struct #define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ /* Bit fields for USART RXDOUBLEXP */ -#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ -#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ -#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ -#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ -#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ -#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ -#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ -#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ -#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ -#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ -#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ -#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ -#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ +#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ +#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ #define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ -#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ -#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ -#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ -#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ -#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ -#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ +#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ +#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ /* Bit fields for USART TXDATAX */ #define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ @@ -829,66 +827,66 @@ typedef struct #define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ /* Bit fields for USART TXDOUBLEX */ -#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ -#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ -#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ -#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ -#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ -#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ -#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ -#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ -#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ -#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ -#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ -#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ -#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ -#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ -#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ -#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ -#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ -#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ -#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ -#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ -#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ -#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ -#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ -#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ -#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ -#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ -#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ -#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ -#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ -#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ -#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ -#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ -#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ -#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ -#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ -#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ -#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ /* Bit fields for USART TXDOUBLE */ #define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ @@ -1298,133 +1296,133 @@ typedef struct #define USART_CTRLX_CLKPRSEN_DEFAULT (_USART_CTRLX_CLKPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRLX */ /* Bit fields for USART TIMECMP0 */ -#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ -#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ -#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ -#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ -#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ -#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ -#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ -#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ -#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ -#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ -#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ -#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ -#define _USART_TIMECMP0_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ +#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ +#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP0 */ #define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ #define USART_TIMECMP0_RESTARTEN_DISABLE (_USART_TIMECMP0_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP0 */ -#define USART_TIMECMP0_RESTARTEN_ENABLE (_USART_TIMECMP0_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_ENABLE (_USART_TIMECMP0_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP0 */ /* Bit fields for USART TIMECMP1 */ -#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ -#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ -#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ -#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ -#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ -#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ -#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ -#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ -#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ -#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ -#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ -#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ -#define _USART_TIMECMP1_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ +#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ +#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP1 */ #define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ #define USART_TIMECMP1_RESTARTEN_DISABLE (_USART_TIMECMP1_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP1 */ -#define USART_TIMECMP1_RESTARTEN_ENABLE (_USART_TIMECMP1_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_ENABLE (_USART_TIMECMP1_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP1 */ /* Bit fields for USART TIMECMP2 */ -#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ -#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ -#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ -#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ -#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ -#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ -#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ -#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ -#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ -#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ -#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ -#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ -#define _USART_TIMECMP2_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ +#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ +#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP2 */ #define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ #define USART_TIMECMP2_RESTARTEN_DISABLE (_USART_TIMECMP2_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP2 */ -#define USART_TIMECMP2_RESTARTEN_ENABLE (_USART_TIMECMP2_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_ENABLE (_USART_TIMECMP2_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP2 */ /** @} End of group EFR32SG23_USART_BitFields */ /** @} End of group EFR32SG23_USART */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_vdac.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_vdac.h index d69e6464b5..afe142cabe 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_vdac.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_vdac.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_VDAC_H #define EFR32SG23_VDAC_H - #define VDAC_HAS_SET_CLEAR /**************************************************************************//** @@ -43,83 +42,82 @@ *****************************************************************************/ /** VDAC Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< Module Enable */ - __IOM uint32_t SWRST; /**< Software Reset Register */ - __IOM uint32_t CFG; /**< Config Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t CH0CFG; /**< Channel 0 Config Register */ - __IOM uint32_t CH1CFG; /**< Channel 1 Config Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t CH0F; /**< Channel 0 Data Write Fifo */ - __IOM uint32_t CH1F; /**< Channel 1 Data Write Fifo */ - __IOM uint32_t OUTCTRL; /**< DAC Output Control */ - __IOM uint32_t OUTTIMERCFG; /**< DAC Out Timer Config Register */ - uint32_t RESERVED0[50U]; /**< Reserved for future use */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - uint32_t RESERVED2[63U]; /**< Reserved for future use */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - uint32_t RESERVED4[895U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< Module Enable */ - __IOM uint32_t SWRST_SET; /**< Software Reset Register */ - __IOM uint32_t CFG_SET; /**< Config Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t CH0CFG_SET; /**< Channel 0 Config Register */ - __IOM uint32_t CH1CFG_SET; /**< Channel 1 Config Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t CH0F_SET; /**< Channel 0 Data Write Fifo */ - __IOM uint32_t CH1F_SET; /**< Channel 1 Data Write Fifo */ - __IOM uint32_t OUTCTRL_SET; /**< DAC Output Control */ - __IOM uint32_t OUTTIMERCFG_SET; /**< DAC Out Timer Config Register */ - uint32_t RESERVED5[50U]; /**< Reserved for future use */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - uint32_t RESERVED7[63U]; /**< Reserved for future use */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - uint32_t RESERVED9[895U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< Module Enable */ - __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ - __IOM uint32_t CFG_CLR; /**< Config Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t CH0CFG_CLR; /**< Channel 0 Config Register */ - __IOM uint32_t CH1CFG_CLR; /**< Channel 1 Config Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t CH0F_CLR; /**< Channel 0 Data Write Fifo */ - __IOM uint32_t CH1F_CLR; /**< Channel 1 Data Write Fifo */ - __IOM uint32_t OUTCTRL_CLR; /**< DAC Output Control */ - __IOM uint32_t OUTTIMERCFG_CLR; /**< DAC Out Timer Config Register */ - uint32_t RESERVED10[50U]; /**< Reserved for future use */ - uint32_t RESERVED11[1U]; /**< Reserved for future use */ - uint32_t RESERVED12[63U]; /**< Reserved for future use */ - uint32_t RESERVED13[1U]; /**< Reserved for future use */ - uint32_t RESERVED14[895U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< Module Enable */ - __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ - __IOM uint32_t CFG_TGL; /**< Config Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t CH0CFG_TGL; /**< Channel 0 Config Register */ - __IOM uint32_t CH1CFG_TGL; /**< Channel 1 Config Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t CH0F_TGL; /**< Channel 0 Data Write Fifo */ - __IOM uint32_t CH1F_TGL; /**< Channel 1 Data Write Fifo */ - __IOM uint32_t OUTCTRL_TGL; /**< DAC Output Control */ - __IOM uint32_t OUTTIMERCFG_TGL; /**< DAC Out Timer Config Register */ - uint32_t RESERVED15[50U]; /**< Reserved for future use */ - uint32_t RESERVED16[1U]; /**< Reserved for future use */ - uint32_t RESERVED17[63U]; /**< Reserved for future use */ - uint32_t RESERVED18[1U]; /**< Reserved for future use */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Module Enable */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Config Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CH0CFG; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG; /**< Channel 1 Config Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG; /**< DAC Out Timer Config Register */ + uint32_t RESERVED0[50U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[63U]; /**< Reserved for future use */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Module Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Config Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CH0CFG_SET; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_SET; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_SET; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_SET; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_SET; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_SET; /**< DAC Out Timer Config Register */ + uint32_t RESERVED5[50U]; /**< Reserved for future use */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[63U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Module Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Config Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CH0CFG_CLR; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_CLR; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_CLR; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_CLR; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_CLR; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_CLR; /**< DAC Out Timer Config Register */ + uint32_t RESERVED10[50U]; /**< Reserved for future use */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[63U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + uint32_t RESERVED14[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Module Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Config Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CH0CFG_TGL; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_TGL; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_TGL; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_TGL; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_TGL; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_TGL; /**< DAC Out Timer Config Register */ + uint32_t RESERVED15[50U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[63U]; /**< Reserved for future use */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ } VDAC_TypeDef; /** @} End of group EFR32SG23_VDAC */ @@ -131,628 +129,628 @@ typedef struct *****************************************************************************/ /* Bit fields for VDAC IPVERSION */ -#define _VDAC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for VDAC_IPVERSION */ -#define _VDAC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for VDAC_IPVERSION */ -#define _VDAC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for VDAC_IPVERSION */ -#define _VDAC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for VDAC_IPVERSION */ -#define _VDAC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IPVERSION */ -#define VDAC_IPVERSION_IPVERSION_DEFAULT (_VDAC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IPVERSION */ +#define VDAC_IPVERSION_IPVERSION_DEFAULT (_VDAC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IPVERSION */ /* Bit fields for VDAC EN */ -#define _VDAC_EN_RESETVALUE 0x00000000UL /**< Default value for VDAC_EN */ -#define _VDAC_EN_MASK 0x00000003UL /**< Mask for VDAC_EN */ -#define VDAC_EN_EN (0x1UL << 0) /**< VDAC Module Enable */ -#define _VDAC_EN_EN_SHIFT 0 /**< Shift value for VDAC_EN */ -#define _VDAC_EN_EN_MASK 0x1UL /**< Bit mask for VDAC_EN */ -#define _VDAC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ -#define _VDAC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_EN */ -#define _VDAC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for VDAC_EN */ -#define VDAC_EN_EN_DEFAULT (_VDAC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_EN */ -#define VDAC_EN_EN_DISABLE (_VDAC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_EN */ -#define VDAC_EN_EN_ENABLE (_VDAC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for VDAC_EN */ -#define VDAC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _VDAC_EN_DISABLING_SHIFT 1 /**< Shift value for VDAC_DISABLING */ -#define _VDAC_EN_DISABLING_MASK 0x2UL /**< Bit mask for VDAC_DISABLING */ -#define _VDAC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ -#define VDAC_EN_DISABLING_DEFAULT (_VDAC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_EN */ +#define _VDAC_EN_RESETVALUE 0x00000000UL /**< Default value for VDAC_EN */ +#define _VDAC_EN_MASK 0x00000003UL /**< Mask for VDAC_EN */ +#define VDAC_EN_EN (0x1UL << 0) /**< VDAC Module Enable */ +#define _VDAC_EN_EN_SHIFT 0 /**< Shift value for VDAC_EN */ +#define _VDAC_EN_EN_MASK 0x1UL /**< Bit mask for VDAC_EN */ +#define _VDAC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ +#define _VDAC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_EN */ +#define _VDAC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for VDAC_EN */ +#define VDAC_EN_EN_DEFAULT (_VDAC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_EN */ +#define VDAC_EN_EN_DISABLE (_VDAC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_EN */ +#define VDAC_EN_EN_ENABLE (_VDAC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for VDAC_EN */ +#define VDAC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _VDAC_EN_DISABLING_SHIFT 1 /**< Shift value for VDAC_DISABLING */ +#define _VDAC_EN_DISABLING_MASK 0x2UL /**< Bit mask for VDAC_DISABLING */ +#define _VDAC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ +#define VDAC_EN_DISABLING_DEFAULT (_VDAC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_EN */ /* Bit fields for VDAC SWRST */ -#define _VDAC_SWRST_RESETVALUE 0x00000000UL /**< Default value for VDAC_SWRST */ -#define _VDAC_SWRST_MASK 0x00000003UL /**< Mask for VDAC_SWRST */ -#define VDAC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ -#define _VDAC_SWRST_SWRST_SHIFT 0 /**< Shift value for VDAC_SWRST */ -#define _VDAC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for VDAC_SWRST */ -#define _VDAC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ -#define VDAC_SWRST_SWRST_DEFAULT (_VDAC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_SWRST */ -#define VDAC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ -#define _VDAC_SWRST_RESETTING_SHIFT 1 /**< Shift value for VDAC_RESETTING */ -#define _VDAC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for VDAC_RESETTING */ -#define _VDAC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ -#define VDAC_SWRST_RESETTING_DEFAULT (_VDAC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_SWRST */ +#define _VDAC_SWRST_RESETVALUE 0x00000000UL /**< Default value for VDAC_SWRST */ +#define _VDAC_SWRST_MASK 0x00000003UL /**< Mask for VDAC_SWRST */ +#define VDAC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _VDAC_SWRST_SWRST_SHIFT 0 /**< Shift value for VDAC_SWRST */ +#define _VDAC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for VDAC_SWRST */ +#define _VDAC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_SWRST_DEFAULT (_VDAC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _VDAC_SWRST_RESETTING_SHIFT 1 /**< Shift value for VDAC_RESETTING */ +#define _VDAC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for VDAC_RESETTING */ +#define _VDAC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_RESETTING_DEFAULT (_VDAC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_SWRST */ /* Bit fields for VDAC CFG */ -#define _VDAC_CFG_RESETVALUE 0x20000000UL /**< Default value for VDAC_CFG */ -#define _VDAC_CFG_MASK 0x7F773FBFUL /**< Mask for VDAC_CFG */ -#define VDAC_CFG_DIFF (0x1UL << 0) /**< Differential Mode */ -#define _VDAC_CFG_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */ -#define _VDAC_CFG_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */ -#define _VDAC_CFG_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_DIFF_SINGLEENDED 0x00000000UL /**< Mode SINGLEENDED for VDAC_CFG */ -#define _VDAC_CFG_DIFF_DIFFERENTIAL 0x00000001UL /**< Mode DIFFERENTIAL for VDAC_CFG */ -#define VDAC_CFG_DIFF_DEFAULT (_VDAC_CFG_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_DIFF_SINGLEENDED (_VDAC_CFG_DIFF_SINGLEENDED << 0) /**< Shifted mode SINGLEENDED for VDAC_CFG */ -#define VDAC_CFG_DIFF_DIFFERENTIAL (_VDAC_CFG_DIFF_DIFFERENTIAL << 0) /**< Shifted mode DIFFERENTIAL for VDAC_CFG */ -#define VDAC_CFG_SINEMODE (0x1UL << 1) /**< Sine Mode */ -#define _VDAC_CFG_SINEMODE_SHIFT 1 /**< Shift value for VDAC_SINEMODE */ -#define _VDAC_CFG_SINEMODE_MASK 0x2UL /**< Bit mask for VDAC_SINEMODE */ -#define _VDAC_CFG_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_SINEMODE_DISSINEMODE 0x00000000UL /**< Mode DISSINEMODE for VDAC_CFG */ -#define _VDAC_CFG_SINEMODE_ENSINEMODE 0x00000001UL /**< Mode ENSINEMODE for VDAC_CFG */ -#define VDAC_CFG_SINEMODE_DEFAULT (_VDAC_CFG_SINEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_SINEMODE_DISSINEMODE (_VDAC_CFG_SINEMODE_DISSINEMODE << 1) /**< Shifted mode DISSINEMODE for VDAC_CFG */ -#define VDAC_CFG_SINEMODE_ENSINEMODE (_VDAC_CFG_SINEMODE_ENSINEMODE << 1) /**< Shifted mode ENSINEMODE for VDAC_CFG */ -#define VDAC_CFG_SINERESET (0x1UL << 2) /**< Sine Wave Reset When inactive */ -#define _VDAC_CFG_SINERESET_SHIFT 2 /**< Shift value for VDAC_SINERESET */ -#define _VDAC_CFG_SINERESET_MASK 0x4UL /**< Bit mask for VDAC_SINERESET */ -#define _VDAC_CFG_SINERESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_SINERESET_DEFAULT (_VDAC_CFG_SINERESET_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_CH0PRESCRST (0x1UL << 3) /**< Channel 0 Start Reset Prescaler */ -#define _VDAC_CFG_CH0PRESCRST_SHIFT 3 /**< Shift value for VDAC_CH0PRESCRST */ -#define _VDAC_CFG_CH0PRESCRST_MASK 0x8UL /**< Bit mask for VDAC_CH0PRESCRST */ -#define _VDAC_CFG_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_CH0PRESCRST_NORESETPRESC 0x00000000UL /**< Mode NORESETPRESC for VDAC_CFG */ -#define _VDAC_CFG_CH0PRESCRST_RESETPRESC 0x00000001UL /**< Mode RESETPRESC for VDAC_CFG */ -#define VDAC_CFG_CH0PRESCRST_DEFAULT (_VDAC_CFG_CH0PRESCRST_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_CH0PRESCRST_NORESETPRESC (_VDAC_CFG_CH0PRESCRST_NORESETPRESC << 3) /**< Shifted mode NORESETPRESC for VDAC_CFG */ -#define VDAC_CFG_CH0PRESCRST_RESETPRESC (_VDAC_CFG_CH0PRESCRST_RESETPRESC << 3) /**< Shifted mode RESETPRESC for VDAC_CFG */ -#define _VDAC_CFG_REFRSEL_SHIFT 4 /**< Shift value for VDAC_REFRSEL */ -#define _VDAC_CFG_REFRSEL_MASK 0x30UL /**< Bit mask for VDAC_REFRSEL */ -#define _VDAC_CFG_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_REFRSEL_V125 0x00000000UL /**< Mode V125 for VDAC_CFG */ -#define _VDAC_CFG_REFRSEL_V25 0x00000001UL /**< Mode V25 for VDAC_CFG */ -#define _VDAC_CFG_REFRSEL_VDD 0x00000002UL /**< Mode VDD for VDAC_CFG */ -#define _VDAC_CFG_REFRSEL_EXT 0x00000003UL /**< Mode EXT for VDAC_CFG */ -#define VDAC_CFG_REFRSEL_DEFAULT (_VDAC_CFG_REFRSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_REFRSEL_V125 (_VDAC_CFG_REFRSEL_V125 << 4) /**< Shifted mode V125 for VDAC_CFG */ -#define VDAC_CFG_REFRSEL_V25 (_VDAC_CFG_REFRSEL_V25 << 4) /**< Shifted mode V25 for VDAC_CFG */ -#define VDAC_CFG_REFRSEL_VDD (_VDAC_CFG_REFRSEL_VDD << 4) /**< Shifted mode VDD for VDAC_CFG */ -#define VDAC_CFG_REFRSEL_EXT (_VDAC_CFG_REFRSEL_EXT << 4) /**< Shifted mode EXT for VDAC_CFG */ -#define _VDAC_CFG_PRESC_SHIFT 7 /**< Shift value for VDAC_PRESC */ -#define _VDAC_CFG_PRESC_MASK 0x3F80UL /**< Bit mask for VDAC_PRESC */ -#define _VDAC_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_PRESC_DEFAULT (_VDAC_CFG_PRESC_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_SHIFT 16 /**< Shift value for VDAC_TIMEROVRFLOWPERIOD */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_MASK 0x70000UL /**< Bit mask for VDAC_TIMEROVRFLOWPERIOD */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT (_VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 << 16) /**< Shifted mode CYCLES2 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 << 16) /**< Shifted mode CYCLES4 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 << 16) /**< Shifted mode CYCLES8 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 << 16) /**< Shifted mode CYCLES16 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 << 16) /**< Shifted mode CYCLES32 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 << 16) /**< Shifted mode CYCLES64 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_SHIFT 20 /**< Shift value for VDAC_REFRESHPERIOD */ -#define _VDAC_CFG_REFRESHPERIOD_MASK 0x700000UL /**< Bit mask for VDAC_REFRESHPERIOD */ -#define _VDAC_CFG_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES128 0x00000006UL /**< Mode CYCLES128 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES256 0x00000007UL /**< Mode CYCLES256 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_DEFAULT (_VDAC_CFG_REFRESHPERIOD_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES2 (_VDAC_CFG_REFRESHPERIOD_CYCLES2 << 20) /**< Shifted mode CYCLES2 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES4 (_VDAC_CFG_REFRESHPERIOD_CYCLES4 << 20) /**< Shifted mode CYCLES4 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES8 (_VDAC_CFG_REFRESHPERIOD_CYCLES8 << 20) /**< Shifted mode CYCLES8 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES16 (_VDAC_CFG_REFRESHPERIOD_CYCLES16 << 20) /**< Shifted mode CYCLES16 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES32 (_VDAC_CFG_REFRESHPERIOD_CYCLES32 << 20) /**< Shifted mode CYCLES32 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES64 (_VDAC_CFG_REFRESHPERIOD_CYCLES64 << 20) /**< Shifted mode CYCLES64 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES128 (_VDAC_CFG_REFRESHPERIOD_CYCLES128 << 20) /**< Shifted mode CYCLES128 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES256 (_VDAC_CFG_REFRESHPERIOD_CYCLES256 << 20) /**< Shifted mode CYCLES256 for VDAC_CFG */ -#define VDAC_CFG_BIASKEEPWARM (0x1UL << 24) /**< Bias Keepwarm Mode Enable */ -#define _VDAC_CFG_BIASKEEPWARM_SHIFT 24 /**< Shift value for VDAC_BIASKEEPWARM */ -#define _VDAC_CFG_BIASKEEPWARM_MASK 0x1000000UL /**< Bit mask for VDAC_BIASKEEPWARM */ -#define _VDAC_CFG_BIASKEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_BIASKEEPWARM_DEFAULT (_VDAC_CFG_BIASKEEPWARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_DMAWU (0x1UL << 25) /**< VDAC DMA Wakeup */ -#define _VDAC_CFG_DMAWU_SHIFT 25 /**< Shift value for VDAC_DMAWU */ -#define _VDAC_CFG_DMAWU_MASK 0x2000000UL /**< Bit mask for VDAC_DMAWU */ -#define _VDAC_CFG_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_DMAWU_DEFAULT (_VDAC_CFG_DMAWU_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_ONDEMANDCLK (0x1UL << 26) /**< Always allow clk_dac */ -#define _VDAC_CFG_ONDEMANDCLK_SHIFT 26 /**< Shift value for VDAC_ONDEMANDCLK */ -#define _VDAC_CFG_ONDEMANDCLK_MASK 0x4000000UL /**< Bit mask for VDAC_ONDEMANDCLK */ -#define _VDAC_CFG_ONDEMANDCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_ONDEMANDCLK_DEFAULT (_VDAC_CFG_ONDEMANDCLK_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_DBGHALT (0x1UL << 27) /**< Debug Halt */ -#define _VDAC_CFG_DBGHALT_SHIFT 27 /**< Shift value for VDAC_DBGHALT */ -#define _VDAC_CFG_DBGHALT_MASK 0x8000000UL /**< Bit mask for VDAC_DBGHALT */ -#define _VDAC_CFG_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CFG */ -#define _VDAC_CFG_DBGHALT_HALT 0x00000001UL /**< Mode HALT for VDAC_CFG */ -#define VDAC_CFG_DBGHALT_DEFAULT (_VDAC_CFG_DBGHALT_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_DBGHALT_NORMAL (_VDAC_CFG_DBGHALT_NORMAL << 27) /**< Shifted mode NORMAL for VDAC_CFG */ -#define VDAC_CFG_DBGHALT_HALT (_VDAC_CFG_DBGHALT_HALT << 27) /**< Shifted mode HALT for VDAC_CFG */ -#define _VDAC_CFG_WARMUPTIME_SHIFT 28 /**< Shift value for VDAC_WARMUPTIME */ -#define _VDAC_CFG_WARMUPTIME_MASK 0x70000000UL /**< Bit mask for VDAC_WARMUPTIME */ -#define _VDAC_CFG_WARMUPTIME_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_WARMUPTIME_DEFAULT (_VDAC_CFG_WARMUPTIME_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_RESETVALUE 0x20000000UL /**< Default value for VDAC_CFG */ +#define _VDAC_CFG_MASK 0x7F773FBFUL /**< Mask for VDAC_CFG */ +#define VDAC_CFG_DIFF (0x1UL << 0) /**< Differential Mode */ +#define _VDAC_CFG_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */ +#define _VDAC_CFG_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */ +#define _VDAC_CFG_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_DIFF_SINGLEENDED 0x00000000UL /**< Mode SINGLEENDED for VDAC_CFG */ +#define _VDAC_CFG_DIFF_DIFFERENTIAL 0x00000001UL /**< Mode DIFFERENTIAL for VDAC_CFG */ +#define VDAC_CFG_DIFF_DEFAULT (_VDAC_CFG_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DIFF_SINGLEENDED (_VDAC_CFG_DIFF_SINGLEENDED << 0) /**< Shifted mode SINGLEENDED for VDAC_CFG */ +#define VDAC_CFG_DIFF_DIFFERENTIAL (_VDAC_CFG_DIFF_DIFFERENTIAL << 0) /**< Shifted mode DIFFERENTIAL for VDAC_CFG */ +#define VDAC_CFG_SINEMODE (0x1UL << 1) /**< Sine Mode */ +#define _VDAC_CFG_SINEMODE_SHIFT 1 /**< Shift value for VDAC_SINEMODE */ +#define _VDAC_CFG_SINEMODE_MASK 0x2UL /**< Bit mask for VDAC_SINEMODE */ +#define _VDAC_CFG_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_SINEMODE_DISSINEMODE 0x00000000UL /**< Mode DISSINEMODE for VDAC_CFG */ +#define _VDAC_CFG_SINEMODE_ENSINEMODE 0x00000001UL /**< Mode ENSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_DEFAULT (_VDAC_CFG_SINEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_DISSINEMODE (_VDAC_CFG_SINEMODE_DISSINEMODE << 1) /**< Shifted mode DISSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_ENSINEMODE (_VDAC_CFG_SINEMODE_ENSINEMODE << 1) /**< Shifted mode ENSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINERESET (0x1UL << 2) /**< Sine Wave Reset When inactive */ +#define _VDAC_CFG_SINERESET_SHIFT 2 /**< Shift value for VDAC_SINERESET */ +#define _VDAC_CFG_SINERESET_MASK 0x4UL /**< Bit mask for VDAC_SINERESET */ +#define _VDAC_CFG_SINERESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_SINERESET_DEFAULT (_VDAC_CFG_SINERESET_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST (0x1UL << 3) /**< Channel 0 Start Reset Prescaler */ +#define _VDAC_CFG_CH0PRESCRST_SHIFT 3 /**< Shift value for VDAC_CH0PRESCRST */ +#define _VDAC_CFG_CH0PRESCRST_MASK 0x8UL /**< Bit mask for VDAC_CH0PRESCRST */ +#define _VDAC_CFG_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_CH0PRESCRST_NORESETPRESC 0x00000000UL /**< Mode NORESETPRESC for VDAC_CFG */ +#define _VDAC_CFG_CH0PRESCRST_RESETPRESC 0x00000001UL /**< Mode RESETPRESC for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_DEFAULT (_VDAC_CFG_CH0PRESCRST_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_NORESETPRESC (_VDAC_CFG_CH0PRESCRST_NORESETPRESC << 3) /**< Shifted mode NORESETPRESC for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_RESETPRESC (_VDAC_CFG_CH0PRESCRST_RESETPRESC << 3) /**< Shifted mode RESETPRESC for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_SHIFT 4 /**< Shift value for VDAC_REFRSEL */ +#define _VDAC_CFG_REFRSEL_MASK 0x30UL /**< Bit mask for VDAC_REFRSEL */ +#define _VDAC_CFG_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_V125 0x00000000UL /**< Mode V125 for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_V25 0x00000001UL /**< Mode V25 for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_VDD 0x00000002UL /**< Mode VDD for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_EXT 0x00000003UL /**< Mode EXT for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_DEFAULT (_VDAC_CFG_REFRSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_V125 (_VDAC_CFG_REFRSEL_V125 << 4) /**< Shifted mode V125 for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_V25 (_VDAC_CFG_REFRSEL_V25 << 4) /**< Shifted mode V25 for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_VDD (_VDAC_CFG_REFRSEL_VDD << 4) /**< Shifted mode VDD for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_EXT (_VDAC_CFG_REFRSEL_EXT << 4) /**< Shifted mode EXT for VDAC_CFG */ +#define _VDAC_CFG_PRESC_SHIFT 7 /**< Shift value for VDAC_PRESC */ +#define _VDAC_CFG_PRESC_MASK 0x3F80UL /**< Bit mask for VDAC_PRESC */ +#define _VDAC_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_PRESC_DEFAULT (_VDAC_CFG_PRESC_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_SHIFT 16 /**< Shift value for VDAC_TIMEROVRFLOWPERIOD */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_MASK 0x70000UL /**< Bit mask for VDAC_TIMEROVRFLOWPERIOD */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT (_VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 << 16) /**< Shifted mode CYCLES2 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 << 16) /**< Shifted mode CYCLES4 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 << 16) /**< Shifted mode CYCLES8 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 << 16) /**< Shifted mode CYCLES16 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 << 16) /**< Shifted mode CYCLES32 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 << 16) /**< Shifted mode CYCLES64 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_SHIFT 20 /**< Shift value for VDAC_REFRESHPERIOD */ +#define _VDAC_CFG_REFRESHPERIOD_MASK 0x700000UL /**< Bit mask for VDAC_REFRESHPERIOD */ +#define _VDAC_CFG_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES128 0x00000006UL /**< Mode CYCLES128 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES256 0x00000007UL /**< Mode CYCLES256 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_DEFAULT (_VDAC_CFG_REFRESHPERIOD_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES2 (_VDAC_CFG_REFRESHPERIOD_CYCLES2 << 20) /**< Shifted mode CYCLES2 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES4 (_VDAC_CFG_REFRESHPERIOD_CYCLES4 << 20) /**< Shifted mode CYCLES4 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES8 (_VDAC_CFG_REFRESHPERIOD_CYCLES8 << 20) /**< Shifted mode CYCLES8 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES16 (_VDAC_CFG_REFRESHPERIOD_CYCLES16 << 20) /**< Shifted mode CYCLES16 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES32 (_VDAC_CFG_REFRESHPERIOD_CYCLES32 << 20) /**< Shifted mode CYCLES32 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES64 (_VDAC_CFG_REFRESHPERIOD_CYCLES64 << 20) /**< Shifted mode CYCLES64 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES128 (_VDAC_CFG_REFRESHPERIOD_CYCLES128 << 20) /**< Shifted mode CYCLES128 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES256 (_VDAC_CFG_REFRESHPERIOD_CYCLES256 << 20) /**< Shifted mode CYCLES256 for VDAC_CFG */ +#define VDAC_CFG_BIASKEEPWARM (0x1UL << 24) /**< Bias Keepwarm Mode Enable */ +#define _VDAC_CFG_BIASKEEPWARM_SHIFT 24 /**< Shift value for VDAC_BIASKEEPWARM */ +#define _VDAC_CFG_BIASKEEPWARM_MASK 0x1000000UL /**< Bit mask for VDAC_BIASKEEPWARM */ +#define _VDAC_CFG_BIASKEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_BIASKEEPWARM_DEFAULT (_VDAC_CFG_BIASKEEPWARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DMAWU (0x1UL << 25) /**< VDAC DMA Wakeup */ +#define _VDAC_CFG_DMAWU_SHIFT 25 /**< Shift value for VDAC_DMAWU */ +#define _VDAC_CFG_DMAWU_MASK 0x2000000UL /**< Bit mask for VDAC_DMAWU */ +#define _VDAC_CFG_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DMAWU_DEFAULT (_VDAC_CFG_DMAWU_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_ONDEMANDCLK (0x1UL << 26) /**< Always allow clk_dac */ +#define _VDAC_CFG_ONDEMANDCLK_SHIFT 26 /**< Shift value for VDAC_ONDEMANDCLK */ +#define _VDAC_CFG_ONDEMANDCLK_MASK 0x4000000UL /**< Bit mask for VDAC_ONDEMANDCLK */ +#define _VDAC_CFG_ONDEMANDCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_ONDEMANDCLK_DEFAULT (_VDAC_CFG_ONDEMANDCLK_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT (0x1UL << 27) /**< Debug Halt */ +#define _VDAC_CFG_DBGHALT_SHIFT 27 /**< Shift value for VDAC_DBGHALT */ +#define _VDAC_CFG_DBGHALT_MASK 0x8000000UL /**< Bit mask for VDAC_DBGHALT */ +#define _VDAC_CFG_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CFG */ +#define _VDAC_CFG_DBGHALT_HALT 0x00000001UL /**< Mode HALT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_DEFAULT (_VDAC_CFG_DBGHALT_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_NORMAL (_VDAC_CFG_DBGHALT_NORMAL << 27) /**< Shifted mode NORMAL for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_HALT (_VDAC_CFG_DBGHALT_HALT << 27) /**< Shifted mode HALT for VDAC_CFG */ +#define _VDAC_CFG_WARMUPTIME_SHIFT 28 /**< Shift value for VDAC_WARMUPTIME */ +#define _VDAC_CFG_WARMUPTIME_MASK 0x70000000UL /**< Bit mask for VDAC_WARMUPTIME */ +#define _VDAC_CFG_WARMUPTIME_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_WARMUPTIME_DEFAULT (_VDAC_CFG_WARMUPTIME_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CFG */ /* Bit fields for VDAC STATUS */ -#define _VDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for VDAC_STATUS */ -#define _VDAC_STATUS_MASK 0xFCDBF333UL /**< Mask for VDAC_STATUS */ -#define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */ -#define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */ -#define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */ -#define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */ -#define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */ -#define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */ -#define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warmed Status */ -#define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */ -#define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */ -#define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warmed Status */ -#define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */ -#define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */ -#define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOFULL (0x1UL << 8) /**< Channel 0 FIFO Full Status */ -#define _VDAC_STATUS_CH0FIFOFULL_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFULL */ -#define _VDAC_STATUS_CH0FIFOFULL_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFULL */ -#define _VDAC_STATUS_CH0FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOFULL_DEFAULT (_VDAC_STATUS_CH0FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOFULL (0x1UL << 9) /**< Channel 1 FIFO Full Status */ -#define _VDAC_STATUS_CH1FIFOFULL_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFULL */ -#define _VDAC_STATUS_CH1FIFOFULL_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFULL */ -#define _VDAC_STATUS_CH1FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOFULL_DEFAULT (_VDAC_STATUS_CH1FIFOFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define _VDAC_STATUS_CH0FIFOCNT_SHIFT 12 /**< Shift value for VDAC_CH0FIFOCNT */ -#define _VDAC_STATUS_CH0FIFOCNT_MASK 0x7000UL /**< Bit mask for VDAC_CH0FIFOCNT */ -#define _VDAC_STATUS_CH0FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOCNT_DEFAULT (_VDAC_STATUS_CH0FIFOCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define _VDAC_STATUS_CH1FIFOCNT_SHIFT 15 /**< Shift value for VDAC_CH1FIFOCNT */ -#define _VDAC_STATUS_CH1FIFOCNT_MASK 0x38000UL /**< Bit mask for VDAC_CH1FIFOCNT */ -#define _VDAC_STATUS_CH1FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOCNT_DEFAULT (_VDAC_STATUS_CH1FIFOCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0CURRENTSTATE (0x1UL << 19) /**< Channel 0 Current Status */ -#define _VDAC_STATUS_CH0CURRENTSTATE_SHIFT 19 /**< Shift value for VDAC_CH0CURRENTSTATE */ -#define _VDAC_STATUS_CH0CURRENTSTATE_MASK 0x80000UL /**< Bit mask for VDAC_CH0CURRENTSTATE */ -#define _VDAC_STATUS_CH0CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH0CURRENTSTATE_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1CURRENTSTATE (0x1UL << 20) /**< Channel 1 Current Status */ -#define _VDAC_STATUS_CH1CURRENTSTATE_SHIFT 20 /**< Shift value for VDAC_CH1CURRENTSTATE */ -#define _VDAC_STATUS_CH1CURRENTSTATE_MASK 0x100000UL /**< Bit mask for VDAC_CH1CURRENTSTATE */ -#define _VDAC_STATUS_CH1CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH1CURRENTSTATE_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOEMPTY (0x1UL << 22) /**< Channel 0 FIFO Empty Status */ -#define _VDAC_STATUS_CH0FIFOEMPTY_SHIFT 22 /**< Shift value for VDAC_CH0FIFOEMPTY */ -#define _VDAC_STATUS_CH0FIFOEMPTY_MASK 0x400000UL /**< Bit mask for VDAC_CH0FIFOEMPTY */ -#define _VDAC_STATUS_CH0FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH0FIFOEMPTY_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOEMPTY (0x1UL << 23) /**< Channel 1 FIFO Empty Status */ -#define _VDAC_STATUS_CH1FIFOEMPTY_SHIFT 23 /**< Shift value for VDAC_CH1FIFOEMPTY */ -#define _VDAC_STATUS_CH1FIFOEMPTY_MASK 0x800000UL /**< Bit mask for VDAC_CH1FIFOEMPTY */ -#define _VDAC_STATUS_CH1FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH1FIFOEMPTY_DEFAULT << 23) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOFLBUSY (0x1UL << 26) /**< CH0 FIFO Flush Sync Busy */ -#define _VDAC_STATUS_CH0FIFOFLBUSY_SHIFT 26 /**< Shift value for VDAC_CH0FIFOFLBUSY */ -#define _VDAC_STATUS_CH0FIFOFLBUSY_MASK 0x4000000UL /**< Bit mask for VDAC_CH0FIFOFLBUSY */ -#define _VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOFLBUSY (0x1UL << 27) /**< CH1 FIFO Flush Sync Busy */ -#define _VDAC_STATUS_CH1FIFOFLBUSY_SHIFT 27 /**< Shift value for VDAC_CH1FIFOFLBUSY */ -#define _VDAC_STATUS_CH1FIFOFLBUSY_MASK 0x8000000UL /**< Bit mask for VDAC_CH1FIFOFLBUSY */ -#define _VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_ABUSINPUTCONFLICT (0x1UL << 28) /**< ABUS Input Conflict Status */ -#define _VDAC_STATUS_ABUSINPUTCONFLICT_SHIFT 28 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_STATUS_ABUSINPUTCONFLICT_MASK 0x10000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT (_VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_SINEACTIVE (0x1UL << 29) /**< Sine Wave Output Status on Channel */ -#define _VDAC_STATUS_SINEACTIVE_SHIFT 29 /**< Shift value for VDAC_SINEACTIVE */ -#define _VDAC_STATUS_SINEACTIVE_MASK 0x20000000UL /**< Bit mask for VDAC_SINEACTIVE */ -#define _VDAC_STATUS_SINEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_SINEACTIVE_DEFAULT (_VDAC_STATUS_SINEACTIVE_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_ABUSALLOCERR (0x1UL << 30) /**< ABUS Allocation Error Status */ -#define _VDAC_STATUS_ABUSALLOCERR_SHIFT 30 /**< Shift value for VDAC_ABUSALLOCERR */ -#define _VDAC_STATUS_ABUSALLOCERR_MASK 0x40000000UL /**< Bit mask for VDAC_ABUSALLOCERR */ -#define _VDAC_STATUS_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_ABUSALLOCERR_DEFAULT (_VDAC_STATUS_ABUSALLOCERR_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy Combined */ -#define _VDAC_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for VDAC_SYNCBUSY */ -#define _VDAC_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for VDAC_SYNCBUSY */ -#define _VDAC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_SYNCBUSY_DEFAULT (_VDAC_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define _VDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for VDAC_STATUS */ +#define _VDAC_STATUS_MASK 0xFCDBF333UL /**< Mask for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */ +#define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */ +#define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warmed Status */ +#define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warmed Status */ +#define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFULL (0x1UL << 8) /**< Channel 0 FIFO Full Status */ +#define _VDAC_STATUS_CH0FIFOFULL_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFULL */ +#define _VDAC_STATUS_CH0FIFOFULL_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFULL */ +#define _VDAC_STATUS_CH0FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFULL_DEFAULT (_VDAC_STATUS_CH0FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFULL (0x1UL << 9) /**< Channel 1 FIFO Full Status */ +#define _VDAC_STATUS_CH1FIFOFULL_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFULL */ +#define _VDAC_STATUS_CH1FIFOFULL_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFULL */ +#define _VDAC_STATUS_CH1FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFULL_DEFAULT (_VDAC_STATUS_CH1FIFOFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define _VDAC_STATUS_CH0FIFOCNT_SHIFT 12 /**< Shift value for VDAC_CH0FIFOCNT */ +#define _VDAC_STATUS_CH0FIFOCNT_MASK 0x7000UL /**< Bit mask for VDAC_CH0FIFOCNT */ +#define _VDAC_STATUS_CH0FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOCNT_DEFAULT (_VDAC_STATUS_CH0FIFOCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define _VDAC_STATUS_CH1FIFOCNT_SHIFT 15 /**< Shift value for VDAC_CH1FIFOCNT */ +#define _VDAC_STATUS_CH1FIFOCNT_MASK 0x38000UL /**< Bit mask for VDAC_CH1FIFOCNT */ +#define _VDAC_STATUS_CH1FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOCNT_DEFAULT (_VDAC_STATUS_CH1FIFOCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0CURRENTSTATE (0x1UL << 19) /**< Channel 0 Current Status */ +#define _VDAC_STATUS_CH0CURRENTSTATE_SHIFT 19 /**< Shift value for VDAC_CH0CURRENTSTATE */ +#define _VDAC_STATUS_CH0CURRENTSTATE_MASK 0x80000UL /**< Bit mask for VDAC_CH0CURRENTSTATE */ +#define _VDAC_STATUS_CH0CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH0CURRENTSTATE_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1CURRENTSTATE (0x1UL << 20) /**< Channel 1 Current Status */ +#define _VDAC_STATUS_CH1CURRENTSTATE_SHIFT 20 /**< Shift value for VDAC_CH1CURRENTSTATE */ +#define _VDAC_STATUS_CH1CURRENTSTATE_MASK 0x100000UL /**< Bit mask for VDAC_CH1CURRENTSTATE */ +#define _VDAC_STATUS_CH1CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH1CURRENTSTATE_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOEMPTY (0x1UL << 22) /**< Channel 0 FIFO Empty Status */ +#define _VDAC_STATUS_CH0FIFOEMPTY_SHIFT 22 /**< Shift value for VDAC_CH0FIFOEMPTY */ +#define _VDAC_STATUS_CH0FIFOEMPTY_MASK 0x400000UL /**< Bit mask for VDAC_CH0FIFOEMPTY */ +#define _VDAC_STATUS_CH0FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH0FIFOEMPTY_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOEMPTY (0x1UL << 23) /**< Channel 1 FIFO Empty Status */ +#define _VDAC_STATUS_CH1FIFOEMPTY_SHIFT 23 /**< Shift value for VDAC_CH1FIFOEMPTY */ +#define _VDAC_STATUS_CH1FIFOEMPTY_MASK 0x800000UL /**< Bit mask for VDAC_CH1FIFOEMPTY */ +#define _VDAC_STATUS_CH1FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH1FIFOEMPTY_DEFAULT << 23) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFLBUSY (0x1UL << 26) /**< CH0 FIFO Flush Sync Busy */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_SHIFT 26 /**< Shift value for VDAC_CH0FIFOFLBUSY */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_MASK 0x4000000UL /**< Bit mask for VDAC_CH0FIFOFLBUSY */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFLBUSY (0x1UL << 27) /**< CH1 FIFO Flush Sync Busy */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_SHIFT 27 /**< Shift value for VDAC_CH1FIFOFLBUSY */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_MASK 0x8000000UL /**< Bit mask for VDAC_CH1FIFOFLBUSY */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSINPUTCONFLICT (0x1UL << 28) /**< ABUS Input Conflict Status */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_SHIFT 28 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_MASK 0x10000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT (_VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SINEACTIVE (0x1UL << 29) /**< Sine Wave Output Status on Channel */ +#define _VDAC_STATUS_SINEACTIVE_SHIFT 29 /**< Shift value for VDAC_SINEACTIVE */ +#define _VDAC_STATUS_SINEACTIVE_MASK 0x20000000UL /**< Bit mask for VDAC_SINEACTIVE */ +#define _VDAC_STATUS_SINEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SINEACTIVE_DEFAULT (_VDAC_STATUS_SINEACTIVE_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSALLOCERR (0x1UL << 30) /**< ABUS Allocation Error Status */ +#define _VDAC_STATUS_ABUSALLOCERR_SHIFT 30 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_STATUS_ABUSALLOCERR_MASK 0x40000000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_STATUS_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSALLOCERR_DEFAULT (_VDAC_STATUS_ABUSALLOCERR_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy Combined */ +#define _VDAC_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for VDAC_SYNCBUSY */ +#define _VDAC_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for VDAC_SYNCBUSY */ +#define _VDAC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SYNCBUSY_DEFAULT (_VDAC_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_STATUS */ /* Bit fields for VDAC CH0CFG */ -#define _VDAC_CH0CFG_RESETVALUE 0x00000010UL /**< Default value for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH0CFG */ -#define VDAC_CH0CFG_CONVMODE (0x1UL << 0) /**< Channel 0 Conversion Mode */ -#define _VDAC_CH0CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ -#define _VDAC_CH0CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ -#define _VDAC_CH0CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CFG */ -#define VDAC_CH0CFG_CONVMODE_DEFAULT (_VDAC_CH0CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_CONVMODE_CONTINUOUS (_VDAC_CH0CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CFG */ -#define VDAC_CH0CFG_CONVMODE_SAMPLEOFF (_VDAC_CH0CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CFG */ -#define VDAC_CH0CFG_POWERMODE (0x1UL << 2) /**< Channel 0 Power Mode */ -#define _VDAC_CH0CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ -#define _VDAC_CH0CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ -#define _VDAC_CH0CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH0CFG */ -#define VDAC_CH0CFG_POWERMODE_DEFAULT (_VDAC_CH0CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_POWERMODE_HIGHPOWER (_VDAC_CH0CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH0CFG */ -#define VDAC_CH0CFG_POWERMODE_LOWPOWER (_VDAC_CH0CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ -#define _VDAC_CH0CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ -#define _VDAC_CH0CFG_TRIGMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_LESENSE 0x00000003UL /**< Mode LESENSE for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_DEFAULT (_VDAC_CH0CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_NONE (_VDAC_CH0CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_SW (_VDAC_CH0CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_SYNCPRS (_VDAC_CH0CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_LESENSE (_VDAC_CH0CFG_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH0CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_ASYNCPRS (_VDAC_CH0CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ -#define _VDAC_CH0CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ -#define _VDAC_CH0CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ -#define VDAC_CH0CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH0CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_REFRESHSOURCE_NONE (_VDAC_CH0CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH0CFG */ -#define VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH0CFG */ -#define VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ -#define VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ -#define _VDAC_CH0CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ -#define _VDAC_CH0CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_FIFODVL_DEFAULT (_VDAC_CH0CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 0 High Cap Load Mode Enable */ -#define _VDAC_CH0CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ -#define _VDAC_CH0CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ -#define _VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_KEEPWARM (0x1UL << 16) /**< Channel 0 Keepwarm Mode Enable */ -#define _VDAC_CH0CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ -#define _VDAC_CH0CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ -#define _VDAC_CH0CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_KEEPWARM_DEFAULT (_VDAC_CH0CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_RESETVALUE 0x00000010UL /**< Default value for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE (0x1UL << 0) /**< Channel 0 Conversion Mode */ +#define _VDAC_CH0CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH0CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH0CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_DEFAULT (_VDAC_CH0CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_CONTINUOUS (_VDAC_CH0CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_SAMPLEOFF (_VDAC_CH0CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE (0x1UL << 2) /**< Channel 0 Power Mode */ +#define _VDAC_CH0CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ +#define _VDAC_CH0CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ +#define _VDAC_CH0CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_DEFAULT (_VDAC_CH0CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_HIGHPOWER (_VDAC_CH0CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_LOWPOWER (_VDAC_CH0CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH0CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH0CFG_TRIGMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_LESENSE 0x00000003UL /**< Mode LESENSE for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_DEFAULT (_VDAC_CH0CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_NONE (_VDAC_CH0CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_SW (_VDAC_CH0CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_SYNCPRS (_VDAC_CH0CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_LESENSE (_VDAC_CH0CFG_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH0CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_ASYNCPRS (_VDAC_CH0CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ +#define _VDAC_CH0CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ +#define _VDAC_CH0CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH0CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_NONE (_VDAC_CH0CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ +#define _VDAC_CH0CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ +#define _VDAC_CH0CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_FIFODVL_DEFAULT (_VDAC_CH0CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 0 High Cap Load Mode Enable */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_KEEPWARM (0x1UL << 16) /**< Channel 0 Keepwarm Mode Enable */ +#define _VDAC_CH0CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ +#define _VDAC_CH0CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ +#define _VDAC_CH0CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_KEEPWARM_DEFAULT (_VDAC_CH0CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ /* Bit fields for VDAC CH1CFG */ -#define _VDAC_CH1CFG_RESETVALUE 0x00000010UL /**< Default value for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH1CFG */ -#define VDAC_CH1CFG_CONVMODE (0x1UL << 0) /**< Channel 1 Conversion Mode */ -#define _VDAC_CH1CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ -#define _VDAC_CH1CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ -#define _VDAC_CH1CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CFG */ -#define VDAC_CH1CFG_CONVMODE_DEFAULT (_VDAC_CH1CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_CONVMODE_CONTINUOUS (_VDAC_CH1CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CFG */ -#define VDAC_CH1CFG_CONVMODE_SAMPLEOFF (_VDAC_CH1CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CFG */ -#define VDAC_CH1CFG_POWERMODE (0x1UL << 2) /**< Channel 1 Power Mode */ -#define _VDAC_CH1CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ -#define _VDAC_CH1CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ -#define _VDAC_CH1CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH1CFG */ -#define VDAC_CH1CFG_POWERMODE_DEFAULT (_VDAC_CH1CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_POWERMODE_HIGHPOWER (_VDAC_CH1CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH1CFG */ -#define VDAC_CH1CFG_POWERMODE_LOWPOWER (_VDAC_CH1CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ -#define _VDAC_CH1CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ -#define _VDAC_CH1CFG_TRIGMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_DEFAULT (_VDAC_CH1CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_NONE (_VDAC_CH1CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_SW (_VDAC_CH1CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_SYNCPRS (_VDAC_CH1CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH1CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_ASYNCPRS (_VDAC_CH1CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ -#define _VDAC_CH1CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ -#define _VDAC_CH1CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ -#define VDAC_CH1CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH1CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_REFRESHSOURCE_NONE (_VDAC_CH1CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH1CFG */ -#define VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH1CFG */ -#define VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ -#define VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ -#define _VDAC_CH1CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ -#define _VDAC_CH1CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_FIFODVL_DEFAULT (_VDAC_CH1CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 1 High Cap Load Mode Enable */ -#define _VDAC_CH1CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ -#define _VDAC_CH1CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ -#define _VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_KEEPWARM (0x1UL << 16) /**< Channel 1 Keepwarm Mode Enable */ -#define _VDAC_CH1CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ -#define _VDAC_CH1CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ -#define _VDAC_CH1CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_KEEPWARM_DEFAULT (_VDAC_CH1CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_RESETVALUE 0x00000010UL /**< Default value for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE (0x1UL << 0) /**< Channel 1 Conversion Mode */ +#define _VDAC_CH1CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH1CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH1CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_DEFAULT (_VDAC_CH1CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_CONTINUOUS (_VDAC_CH1CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_SAMPLEOFF (_VDAC_CH1CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE (0x1UL << 2) /**< Channel 1 Power Mode */ +#define _VDAC_CH1CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ +#define _VDAC_CH1CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ +#define _VDAC_CH1CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_DEFAULT (_VDAC_CH1CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_HIGHPOWER (_VDAC_CH1CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_LOWPOWER (_VDAC_CH1CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH1CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH1CFG_TRIGMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_DEFAULT (_VDAC_CH1CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_NONE (_VDAC_CH1CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_SW (_VDAC_CH1CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_SYNCPRS (_VDAC_CH1CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH1CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_ASYNCPRS (_VDAC_CH1CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ +#define _VDAC_CH1CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ +#define _VDAC_CH1CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH1CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_NONE (_VDAC_CH1CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ +#define _VDAC_CH1CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ +#define _VDAC_CH1CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_FIFODVL_DEFAULT (_VDAC_CH1CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 1 High Cap Load Mode Enable */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_KEEPWARM (0x1UL << 16) /**< Channel 1 Keepwarm Mode Enable */ +#define _VDAC_CH1CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ +#define _VDAC_CH1CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ +#define _VDAC_CH1CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_KEEPWARM_DEFAULT (_VDAC_CH1CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ /* Bit fields for VDAC CMD */ -#define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */ -#define _VDAC_CMD_MASK 0x00000F33UL /**< Mask for VDAC_CMD */ -#define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */ -#define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */ -#define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */ -#define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */ -#define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */ -#define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */ -#define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1EN (0x1UL << 4) /**< DAC Channel 1 Enable */ -#define _VDAC_CMD_CH1EN_SHIFT 4 /**< Shift value for VDAC_CH1EN */ -#define _VDAC_CMD_CH1EN_MASK 0x10UL /**< Bit mask for VDAC_CH1EN */ -#define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1DIS (0x1UL << 5) /**< DAC Channel 1 Disable */ -#define _VDAC_CMD_CH1DIS_SHIFT 5 /**< Shift value for VDAC_CH1DIS */ -#define _VDAC_CMD_CH1DIS_MASK 0x20UL /**< Bit mask for VDAC_CH1DIS */ -#define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH0FIFOFLUSH (0x1UL << 8) /**< CH0 WFIFO Flush */ -#define _VDAC_CMD_CH0FIFOFLUSH_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFLUSH */ -#define _VDAC_CMD_CH0FIFOFLUSH_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFLUSH */ -#define _VDAC_CMD_CH0FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH0FIFOFLUSH_DEFAULT (_VDAC_CMD_CH0FIFOFLUSH_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1FIFOFLUSH (0x1UL << 9) /**< CH1 WFIFO Flush */ -#define _VDAC_CMD_CH1FIFOFLUSH_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFLUSH */ -#define _VDAC_CMD_CH1FIFOFLUSH_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFLUSH */ -#define _VDAC_CMD_CH1FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1FIFOFLUSH_DEFAULT (_VDAC_CMD_CH1FIFOFLUSH_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_SINEMODESTART (0x1UL << 10) /**< Start Sine Wave Generation */ -#define _VDAC_CMD_SINEMODESTART_SHIFT 10 /**< Shift value for VDAC_SINEMODESTART */ -#define _VDAC_CMD_SINEMODESTART_MASK 0x400UL /**< Bit mask for VDAC_SINEMODESTART */ -#define _VDAC_CMD_SINEMODESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_SINEMODESTART_DEFAULT (_VDAC_CMD_SINEMODESTART_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_SINEMODESTOP (0x1UL << 11) /**< Stop Sine Wave Generation */ -#define _VDAC_CMD_SINEMODESTOP_SHIFT 11 /**< Shift value for VDAC_SINEMODESTOP */ -#define _VDAC_CMD_SINEMODESTOP_MASK 0x800UL /**< Bit mask for VDAC_SINEMODESTOP */ -#define _VDAC_CMD_SINEMODESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_SINEMODESTOP_DEFAULT (_VDAC_CMD_SINEMODESTOP_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */ +#define _VDAC_CMD_MASK 0x00000F33UL /**< Mask for VDAC_CMD */ +#define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */ +#define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */ +#define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN (0x1UL << 4) /**< DAC Channel 1 Enable */ +#define _VDAC_CMD_CH1EN_SHIFT 4 /**< Shift value for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_MASK 0x10UL /**< Bit mask for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS (0x1UL << 5) /**< DAC Channel 1 Disable */ +#define _VDAC_CMD_CH1DIS_SHIFT 5 /**< Shift value for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_MASK 0x20UL /**< Bit mask for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0FIFOFLUSH (0x1UL << 8) /**< CH0 WFIFO Flush */ +#define _VDAC_CMD_CH0FIFOFLUSH_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFLUSH */ +#define _VDAC_CMD_CH0FIFOFLUSH_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFLUSH */ +#define _VDAC_CMD_CH0FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0FIFOFLUSH_DEFAULT (_VDAC_CMD_CH0FIFOFLUSH_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1FIFOFLUSH (0x1UL << 9) /**< CH1 WFIFO Flush */ +#define _VDAC_CMD_CH1FIFOFLUSH_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFLUSH */ +#define _VDAC_CMD_CH1FIFOFLUSH_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFLUSH */ +#define _VDAC_CMD_CH1FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1FIFOFLUSH_DEFAULT (_VDAC_CMD_CH1FIFOFLUSH_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTART (0x1UL << 10) /**< Start Sine Wave Generation */ +#define _VDAC_CMD_SINEMODESTART_SHIFT 10 /**< Shift value for VDAC_SINEMODESTART */ +#define _VDAC_CMD_SINEMODESTART_MASK 0x400UL /**< Bit mask for VDAC_SINEMODESTART */ +#define _VDAC_CMD_SINEMODESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTART_DEFAULT (_VDAC_CMD_SINEMODESTART_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTOP (0x1UL << 11) /**< Stop Sine Wave Generation */ +#define _VDAC_CMD_SINEMODESTOP_SHIFT 11 /**< Shift value for VDAC_SINEMODESTOP */ +#define _VDAC_CMD_SINEMODESTOP_MASK 0x800UL /**< Bit mask for VDAC_SINEMODESTOP */ +#define _VDAC_CMD_SINEMODESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTOP_DEFAULT (_VDAC_CMD_SINEMODESTOP_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CMD */ /* Bit fields for VDAC IF */ -#define _VDAC_IF_RESETVALUE 0x00000000UL /**< Default value for VDAC_IF */ -#define _VDAC_IF_MASK 0x04340333UL /**< Mask for VDAC_IF */ -#define VDAC_IF_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ -#define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ -#define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ -#define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ -#define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ -#define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ -#define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ -#define _VDAC_IF_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ -#define _VDAC_IF_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ -#define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ -#define _VDAC_IF_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ -#define _VDAC_IF_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ -#define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ -#define _VDAC_IF_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ -#define _VDAC_IF_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ -#define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ -#define _VDAC_IF_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ -#define _VDAC_IF_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ -#define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_ABUSALLOCERR (0x1UL << 18) /**< ABUS Port Allocation Error Flag */ -#define _VDAC_IF_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ -#define _VDAC_IF_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ -#define _VDAC_IF_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_ABUSALLOCERR_DEFAULT (_VDAC_IF_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ -#define _VDAC_IF_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ -#define _VDAC_IF_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ -#define _VDAC_IF_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0DVL_DEFAULT (_VDAC_IF_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ -#define _VDAC_IF_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ -#define _VDAC_IF_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ -#define _VDAC_IF_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1DVL_DEFAULT (_VDAC_IF_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Error Flag */ -#define _VDAC_IF_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_IF_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_IF_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IF_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IF */ +#define _VDAC_IF_RESETVALUE 0x00000000UL /**< Default value for VDAC_IF */ +#define _VDAC_IF_MASK 0x04340333UL /**< Mask for VDAC_IF */ +#define VDAC_IF_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSALLOCERR (0x1UL << 18) /**< ABUS Port Allocation Error Flag */ +#define _VDAC_IF_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_IF_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_IF_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSALLOCERR_DEFAULT (_VDAC_IF_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ +#define _VDAC_IF_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ +#define _VDAC_IF_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ +#define _VDAC_IF_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0DVL_DEFAULT (_VDAC_IF_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ +#define _VDAC_IF_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ +#define _VDAC_IF_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ +#define _VDAC_IF_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1DVL_DEFAULT (_VDAC_IF_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Error Flag */ +#define _VDAC_IF_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IF_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IF_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IF_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IF */ /* Bit fields for VDAC IEN */ -#define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */ -#define _VDAC_IEN_MASK 0x04340333UL /**< Mask for VDAC_IEN */ -#define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ -#define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ -#define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ -#define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ -#define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ -#define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ -#define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ -#define _VDAC_IEN_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ -#define _VDAC_IEN_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ -#define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ -#define _VDAC_IEN_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ -#define _VDAC_IEN_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ -#define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ -#define _VDAC_IEN_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ -#define _VDAC_IEN_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ -#define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ -#define _VDAC_IEN_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ -#define _VDAC_IEN_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ -#define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_ABUSALLOCERR (0x1UL << 18) /**< ABUS Allocation Error Interrupt Flag */ -#define _VDAC_IEN_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ -#define _VDAC_IEN_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ -#define _VDAC_IEN_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_ABUSALLOCERR_DEFAULT (_VDAC_IEN_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ -#define _VDAC_IEN_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ -#define _VDAC_IEN_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ -#define _VDAC_IEN_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0DVL_DEFAULT (_VDAC_IEN_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ -#define _VDAC_IEN_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ -#define _VDAC_IEN_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ -#define _VDAC_IEN_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1DVL_DEFAULT (_VDAC_IEN_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Interrupt Flag */ -#define _VDAC_IEN_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_IEN_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */ +#define _VDAC_IEN_MASK 0x04340333UL /**< Mask for VDAC_IEN */ +#define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ +#define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ +#define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ +#define _VDAC_IEN_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ +#define _VDAC_IEN_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ +#define _VDAC_IEN_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ +#define _VDAC_IEN_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSALLOCERR (0x1UL << 18) /**< ABUS Allocation Error Interrupt Flag */ +#define _VDAC_IEN_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_IEN_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_IEN_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSALLOCERR_DEFAULT (_VDAC_IEN_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ +#define _VDAC_IEN_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ +#define _VDAC_IEN_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ +#define _VDAC_IEN_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0DVL_DEFAULT (_VDAC_IEN_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ +#define _VDAC_IEN_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ +#define _VDAC_IEN_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ +#define _VDAC_IEN_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1DVL_DEFAULT (_VDAC_IEN_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Interrupt Flag */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IEN */ /* Bit fields for VDAC CH0F */ -#define _VDAC_CH0F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0F */ -#define _VDAC_CH0F_MASK 0x00000FFFUL /**< Mask for VDAC_CH0F */ -#define _VDAC_CH0F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ -#define _VDAC_CH0F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ -#define _VDAC_CH0F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0F */ -#define VDAC_CH0F_DATA_DEFAULT (_VDAC_CH0F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0F */ +#define _VDAC_CH0F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0F */ +#define _VDAC_CH0F_MASK 0x00000FFFUL /**< Mask for VDAC_CH0F */ +#define _VDAC_CH0F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH0F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH0F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0F */ +#define VDAC_CH0F_DATA_DEFAULT (_VDAC_CH0F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0F */ /* Bit fields for VDAC CH1F */ -#define _VDAC_CH1F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1F */ -#define _VDAC_CH1F_MASK 0x00000FFFUL /**< Mask for VDAC_CH1F */ -#define _VDAC_CH1F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ -#define _VDAC_CH1F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ -#define _VDAC_CH1F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1F */ -#define VDAC_CH1F_DATA_DEFAULT (_VDAC_CH1F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1F */ +#define _VDAC_CH1F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1F */ +#define _VDAC_CH1F_MASK 0x00000FFFUL /**< Mask for VDAC_CH1F */ +#define _VDAC_CH1F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH1F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH1F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1F */ +#define VDAC_CH1F_DATA_DEFAULT (_VDAC_CH1F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1F */ /* Bit fields for VDAC OUTCTRL */ -#define _VDAC_OUTCTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_MASK 0x7FDFF333UL /**< Mask for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_MAINOUTENCH0 (0x1UL << 0) /**< CH0 Main Output Enable */ -#define _VDAC_OUTCTRL_MAINOUTENCH0_SHIFT 0 /**< Shift value for VDAC_MAINOUTENCH0 */ -#define _VDAC_OUTCTRL_MAINOUTENCH0_MASK 0x1UL /**< Bit mask for VDAC_MAINOUTENCH0 */ -#define _VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_MAINOUTENCH1 (0x1UL << 1) /**< CH1 Main Output Enable */ -#define _VDAC_OUTCTRL_MAINOUTENCH1_SHIFT 1 /**< Shift value for VDAC_MAINOUTENCH1 */ -#define _VDAC_OUTCTRL_MAINOUTENCH1_MASK 0x2UL /**< Bit mask for VDAC_MAINOUTENCH1 */ -#define _VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_AUXOUTENCH0 (0x1UL << 4) /**< CH0 Alternative Output Enable */ -#define _VDAC_OUTCTRL_AUXOUTENCH0_SHIFT 4 /**< Shift value for VDAC_AUXOUTENCH0 */ -#define _VDAC_OUTCTRL_AUXOUTENCH0_MASK 0x10UL /**< Bit mask for VDAC_AUXOUTENCH0 */ -#define _VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_AUXOUTENCH1 (0x1UL << 5) /**< CH1 Alternative Output Enable */ -#define _VDAC_OUTCTRL_AUXOUTENCH1_SHIFT 5 /**< Shift value for VDAC_AUXOUTENCH1 */ -#define _VDAC_OUTCTRL_AUXOUTENCH1_MASK 0x20UL /**< Bit mask for VDAC_AUXOUTENCH1 */ -#define _VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_SHORTCH0 (0x1UL << 8) /**< CH1 Main and Alternative Output Short */ -#define _VDAC_OUTCTRL_SHORTCH0_SHIFT 8 /**< Shift value for VDAC_SHORTCH0 */ -#define _VDAC_OUTCTRL_SHORTCH0_MASK 0x100UL /**< Bit mask for VDAC_SHORTCH0 */ -#define _VDAC_OUTCTRL_SHORTCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_SHORTCH0_DEFAULT (_VDAC_OUTCTRL_SHORTCH0_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_SHORTCH1 (0x1UL << 9) /**< CH0 Main and Alternative Output Short */ -#define _VDAC_OUTCTRL_SHORTCH1_SHIFT 9 /**< Shift value for VDAC_SHORTCH1 */ -#define _VDAC_OUTCTRL_SHORTCH1_MASK 0x200UL /**< Bit mask for VDAC_SHORTCH1 */ -#define _VDAC_OUTCTRL_SHORTCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_SHORTCH1_DEFAULT (_VDAC_OUTCTRL_SHORTCH1_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_SHIFT 12 /**< Shift value for VDAC_ABUSPORTSELCH0 */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_MASK 0x7000UL /**< Bit mask for VDAC_ABUSPORTSELCH0 */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH0_NONE << 12) /**< Shifted mode NONE for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA << 12) /**< Shifted mode PORTA for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB << 12) /**< Shifted mode PORTB for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC << 12) /**< Shifted mode PORTC for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD << 12) /**< Shifted mode PORTD for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPINSELCH0_SHIFT 15 /**< Shift value for VDAC_ABUSPINSELCH0 */ -#define _VDAC_OUTCTRL_ABUSPINSELCH0_MASK 0x1F8000UL /**< Bit mask for VDAC_ABUSPINSELCH0 */ -#define _VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_SHIFT 22 /**< Shift value for VDAC_ABUSPORTSELCH1 */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_MASK 0x1C00000UL /**< Bit mask for VDAC_ABUSPORTSELCH1 */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH1_NONE << 22) /**< Shifted mode NONE for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA << 22) /**< Shifted mode PORTA for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB << 22) /**< Shifted mode PORTB for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC << 22) /**< Shifted mode PORTC for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD << 22) /**< Shifted mode PORTD for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPINSELCH1_SHIFT 25 /**< Shift value for VDAC_ABUSPINSELCH1 */ -#define _VDAC_OUTCTRL_ABUSPINSELCH1_MASK 0x7E000000UL /**< Bit mask for VDAC_ABUSPINSELCH1 */ -#define _VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_MASK 0x7FDFF333UL /**< Mask for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH0 (0x1UL << 0) /**< CH0 Main Output Enable */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_SHIFT 0 /**< Shift value for VDAC_MAINOUTENCH0 */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_MASK 0x1UL /**< Bit mask for VDAC_MAINOUTENCH0 */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH1 (0x1UL << 1) /**< CH1 Main Output Enable */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_SHIFT 1 /**< Shift value for VDAC_MAINOUTENCH1 */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_MASK 0x2UL /**< Bit mask for VDAC_MAINOUTENCH1 */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH0 (0x1UL << 4) /**< CH0 Alternative Output Enable */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_SHIFT 4 /**< Shift value for VDAC_AUXOUTENCH0 */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_MASK 0x10UL /**< Bit mask for VDAC_AUXOUTENCH0 */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH1 (0x1UL << 5) /**< CH1 Alternative Output Enable */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_SHIFT 5 /**< Shift value for VDAC_AUXOUTENCH1 */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_MASK 0x20UL /**< Bit mask for VDAC_AUXOUTENCH1 */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH0 (0x1UL << 8) /**< CH1 Main and Alternative Output Short */ +#define _VDAC_OUTCTRL_SHORTCH0_SHIFT 8 /**< Shift value for VDAC_SHORTCH0 */ +#define _VDAC_OUTCTRL_SHORTCH0_MASK 0x100UL /**< Bit mask for VDAC_SHORTCH0 */ +#define _VDAC_OUTCTRL_SHORTCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH0_DEFAULT (_VDAC_OUTCTRL_SHORTCH0_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH1 (0x1UL << 9) /**< CH0 Main and Alternative Output Short */ +#define _VDAC_OUTCTRL_SHORTCH1_SHIFT 9 /**< Shift value for VDAC_SHORTCH1 */ +#define _VDAC_OUTCTRL_SHORTCH1_MASK 0x200UL /**< Bit mask for VDAC_SHORTCH1 */ +#define _VDAC_OUTCTRL_SHORTCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH1_DEFAULT (_VDAC_OUTCTRL_SHORTCH1_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_SHIFT 12 /**< Shift value for VDAC_ABUSPORTSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_MASK 0x7000UL /**< Bit mask for VDAC_ABUSPORTSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH0_NONE << 12) /**< Shifted mode NONE for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA << 12) /**< Shifted mode PORTA for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB << 12) /**< Shifted mode PORTB for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC << 12) /**< Shifted mode PORTC for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD << 12) /**< Shifted mode PORTD for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_SHIFT 15 /**< Shift value for VDAC_ABUSPINSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_MASK 0x1F8000UL /**< Bit mask for VDAC_ABUSPINSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_SHIFT 22 /**< Shift value for VDAC_ABUSPORTSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_MASK 0x1C00000UL /**< Bit mask for VDAC_ABUSPORTSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH1_NONE << 22) /**< Shifted mode NONE for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA << 22) /**< Shifted mode PORTA for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB << 22) /**< Shifted mode PORTB for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC << 22) /**< Shifted mode PORTC for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD << 22) /**< Shifted mode PORTD for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_SHIFT 25 /**< Shift value for VDAC_ABUSPINSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_MASK 0x7E000000UL /**< Bit mask for VDAC_ABUSPINSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ /* Bit fields for VDAC OUTTIMERCFG */ -#define _VDAC_OUTTIMERCFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTTIMERCFG */ -#define _VDAC_OUTTIMERCFG_MASK 0x01FF83FFUL /**< Mask for VDAC_OUTTIMERCFG */ -#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_SHIFT 0 /**< Shift value for VDAC_CH0OUTHOLDTIME */ -#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK 0x3FFUL /**< Bit mask for VDAC_CH0OUTHOLDTIME */ -#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ -#define VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ -#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_SHIFT 15 /**< Shift value for VDAC_CH1OUTHOLDTIME */ -#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_MASK 0x1FF8000UL /**< Bit mask for VDAC_CH1OUTHOLDTIME */ -#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ -#define VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_MASK 0x01FF83FFUL /**< Mask for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_SHIFT 0 /**< Shift value for VDAC_CH0OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK 0x3FFUL /**< Bit mask for VDAC_CH0OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ +#define VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_SHIFT 15 /**< Shift value for VDAC_CH1OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_MASK 0x1FF8000UL /**< Bit mask for VDAC_CH1OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ +#define VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ /** @} End of group EFR32SG23_VDAC_BitFields */ /** @} End of group EFR32SG23_VDAC */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_wdog.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_wdog.h index 38a8f96176..900f786cc7 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_wdog.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23_wdog.h @@ -3,21 +3,21 @@ * @brief EFR32SG23 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG23_WDOG_H #define EFR32SG23_WDOG_H - #define WDOG_HAS_SET_CLEAR /**************************************************************************//** @@ -43,51 +42,50 @@ *****************************************************************************/ /** WDOG Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP Version Register */ - __IOM uint32_t EN; /**< Enable Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CMD; /**< Command Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK; /**< Lock Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version Register */ - __IOM uint32_t EN_SET; /**< Enable Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_SET; /**< Lock Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - uint32_t RESERVED3[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version Register */ - __IOM uint32_t EN_CLR; /**< Enable Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_CLR; /**< Lock Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - uint32_t RESERVED5[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version Register */ - __IOM uint32_t EN_TGL; /**< Enable Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_TGL; /**< Lock Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ } WDOG_TypeDef; /** @} End of group EFR32SG23_WDOG */ @@ -99,276 +97,276 @@ typedef struct *****************************************************************************/ /* Bit fields for WDOG IPVERSION */ -#define _WDOG_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for WDOG_IPVERSION */ -#define _WDOG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for WDOG_IPVERSION */ -#define _WDOG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for WDOG_IPVERSION */ -#define _WDOG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for WDOG_IPVERSION */ -#define _WDOG_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for WDOG_IPVERSION */ -#define WDOG_IPVERSION_IPVERSION_DEFAULT (_WDOG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for WDOG_IPVERSION */ +#define WDOG_IPVERSION_IPVERSION_DEFAULT (_WDOG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IPVERSION */ /* Bit fields for WDOG EN */ -#define _WDOG_EN_RESETVALUE 0x00000000UL /**< Default value for WDOG_EN */ -#define _WDOG_EN_MASK 0x00000003UL /**< Mask for WDOG_EN */ -#define WDOG_EN_EN (0x1UL << 0) /**< Module Enable */ -#define _WDOG_EN_EN_SHIFT 0 /**< Shift value for WDOG_EN */ -#define _WDOG_EN_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ -#define _WDOG_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ -#define WDOG_EN_EN_DEFAULT (_WDOG_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_EN */ -#define WDOG_EN_DISABLING (0x1UL << 1) /**< Disabling busy status */ -#define _WDOG_EN_DISABLING_SHIFT 1 /**< Shift value for WDOG_DISABLING */ -#define _WDOG_EN_DISABLING_MASK 0x2UL /**< Bit mask for WDOG_DISABLING */ -#define _WDOG_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ -#define WDOG_EN_DISABLING_DEFAULT (_WDOG_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_EN */ +#define _WDOG_EN_RESETVALUE 0x00000000UL /**< Default value for WDOG_EN */ +#define _WDOG_EN_MASK 0x00000003UL /**< Mask for WDOG_EN */ +#define WDOG_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _WDOG_EN_EN_SHIFT 0 /**< Shift value for WDOG_EN */ +#define _WDOG_EN_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ +#define _WDOG_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ +#define WDOG_EN_EN_DEFAULT (_WDOG_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_EN */ +#define WDOG_EN_DISABLING (0x1UL << 1) /**< Disabling busy status */ +#define _WDOG_EN_DISABLING_SHIFT 1 /**< Shift value for WDOG_DISABLING */ +#define _WDOG_EN_DISABLING_MASK 0x2UL /**< Bit mask for WDOG_DISABLING */ +#define _WDOG_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ +#define WDOG_EN_DISABLING_DEFAULT (_WDOG_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_EN */ /* Bit fields for WDOG CFG */ -#define _WDOG_CFG_RESETVALUE 0x000F0000UL /**< Default value for WDOG_CFG */ -#define _WDOG_CFG_MASK 0x730F073FUL /**< Mask for WDOG_CFG */ -#define WDOG_CFG_CLRSRC (0x1UL << 0) /**< WDOG Clear Source */ -#define _WDOG_CFG_CLRSRC_SHIFT 0 /**< Shift value for WDOG_CLRSRC */ -#define _WDOG_CFG_CLRSRC_MASK 0x1UL /**< Bit mask for WDOG_CLRSRC */ -#define _WDOG_CFG_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CFG */ -#define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode PRSSRC0 for WDOG_CFG */ -#define WDOG_CFG_CLRSRC_DEFAULT (_WDOG_CFG_CLRSRC_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_CLRSRC_SW (_WDOG_CFG_CLRSRC_SW << 0) /**< Shifted mode SW for WDOG_CFG */ -#define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifted mode PRSSRC0 for WDOG_CFG */ -#define WDOG_CFG_EM1RUN (0x1UL << 1) /**< EM1 Run */ -#define _WDOG_CFG_EM1RUN_SHIFT 1 /**< Shift value for WDOG_EM1RUN */ -#define _WDOG_CFG_EM1RUN_MASK 0x2UL /**< Bit mask for WDOG_EM1RUN */ -#define _WDOG_CFG_EM1RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_EM1RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_EM1RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM1RUN_DEFAULT (_WDOG_CFG_EM1RUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_EM1RUN_DISABLE (_WDOG_CFG_EM1RUN_DISABLE << 1) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_EM1RUN_ENABLE (_WDOG_CFG_EM1RUN_ENABLE << 1) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM2RUN (0x1UL << 2) /**< EM2 Run */ -#define _WDOG_CFG_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ -#define _WDOG_CFG_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ -#define _WDOG_CFG_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_EM2RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_EM2RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM2RUN_DEFAULT (_WDOG_CFG_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_EM2RUN_DISABLE (_WDOG_CFG_EM2RUN_DISABLE << 2) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_EM2RUN_ENABLE (_WDOG_CFG_EM2RUN_ENABLE << 2) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM3RUN (0x1UL << 3) /**< EM3 Run */ -#define _WDOG_CFG_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ -#define _WDOG_CFG_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ -#define _WDOG_CFG_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_EM3RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_EM3RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM3RUN_DEFAULT (_WDOG_CFG_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_EM3RUN_DISABLE (_WDOG_CFG_EM3RUN_DISABLE << 3) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_EM3RUN_ENABLE (_WDOG_CFG_EM3RUN_ENABLE << 3) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM4BLOCK (0x1UL << 4) /**< EM4 Block */ -#define _WDOG_CFG_EM4BLOCK_SHIFT 4 /**< Shift value for WDOG_EM4BLOCK */ -#define _WDOG_CFG_EM4BLOCK_MASK 0x10UL /**< Bit mask for WDOG_EM4BLOCK */ -#define _WDOG_CFG_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_EM4BLOCK_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_EM4BLOCK_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM4BLOCK_DEFAULT (_WDOG_CFG_EM4BLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_EM4BLOCK_DISABLE (_WDOG_CFG_EM4BLOCK_DISABLE << 4) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_EM4BLOCK_ENABLE (_WDOG_CFG_EM4BLOCK_ENABLE << 4) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_DEBUGRUN (0x1UL << 5) /**< Debug Mode Run */ -#define _WDOG_CFG_DEBUGRUN_SHIFT 5 /**< Shift value for WDOG_DEBUGRUN */ -#define _WDOG_CFG_DEBUGRUN_MASK 0x20UL /**< Bit mask for WDOG_DEBUGRUN */ -#define _WDOG_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_DEBUGRUN_DEFAULT (_WDOG_CFG_DEBUGRUN_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_DEBUGRUN_DISABLE (_WDOG_CFG_DEBUGRUN_DISABLE << 5) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_DEBUGRUN_ENABLE (_WDOG_CFG_DEBUGRUN_ENABLE << 5) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_WDOGRSTDIS (0x1UL << 8) /**< WDOG Reset Disable */ -#define _WDOG_CFG_WDOGRSTDIS_SHIFT 8 /**< Shift value for WDOG_WDOGRSTDIS */ -#define _WDOG_CFG_WDOGRSTDIS_MASK 0x100UL /**< Bit mask for WDOG_WDOGRSTDIS */ -#define _WDOG_CFG_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CFG */ -#define _WDOG_CFG_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CFG */ -#define WDOG_CFG_WDOGRSTDIS_DEFAULT (_WDOG_CFG_WDOGRSTDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_WDOGRSTDIS_EN (_WDOG_CFG_WDOGRSTDIS_EN << 8) /**< Shifted mode EN for WDOG_CFG */ -#define WDOG_CFG_WDOGRSTDIS_DIS (_WDOG_CFG_WDOGRSTDIS_DIS << 8) /**< Shifted mode DIS for WDOG_CFG */ -#define WDOG_CFG_PRS0MISSRSTEN (0x1UL << 9) /**< PRS Src0 Missing Event WDOG Reset */ -#define _WDOG_CFG_PRS0MISSRSTEN_SHIFT 9 /**< Shift value for WDOG_PRS0MISSRSTEN */ -#define _WDOG_CFG_PRS0MISSRSTEN_MASK 0x200UL /**< Bit mask for WDOG_PRS0MISSRSTEN */ -#define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_PRS0MISSRSTEN_DEFAULT (_WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_PRS1MISSRSTEN (0x1UL << 10) /**< PRS Src1 Missing Event WDOG Reset */ -#define _WDOG_CFG_PRS1MISSRSTEN_SHIFT 10 /**< Shift value for WDOG_PRS1MISSRSTEN */ -#define _WDOG_CFG_PRS1MISSRSTEN_MASK 0x400UL /**< Bit mask for WDOG_PRS1MISSRSTEN */ -#define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SHIFT 16 /**< Shift value for WDOG_PERSEL */ -#define _WDOG_CFG_PERSEL_MASK 0xF0000UL /**< Bit mask for WDOG_PERSEL */ -#define _WDOG_CFG_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL0 0x00000000UL /**< Mode SEL0 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL8 0x00000008UL /**< Mode SEL8 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL9 0x00000009UL /**< Mode SEL9 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL10 0x0000000AUL /**< Mode SEL10 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL11 0x0000000BUL /**< Mode SEL11 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL12 0x0000000CUL /**< Mode SEL12 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL13 0x0000000DUL /**< Mode SEL13 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL14 0x0000000EUL /**< Mode SEL14 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL15 0x0000000FUL /**< Mode SEL15 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_DEFAULT (_WDOG_CFG_PERSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL0 (_WDOG_CFG_PERSEL_SEL0 << 16) /**< Shifted mode SEL0 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL1 (_WDOG_CFG_PERSEL_SEL1 << 16) /**< Shifted mode SEL1 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL2 (_WDOG_CFG_PERSEL_SEL2 << 16) /**< Shifted mode SEL2 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL3 (_WDOG_CFG_PERSEL_SEL3 << 16) /**< Shifted mode SEL3 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL4 (_WDOG_CFG_PERSEL_SEL4 << 16) /**< Shifted mode SEL4 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL5 (_WDOG_CFG_PERSEL_SEL5 << 16) /**< Shifted mode SEL5 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL6 (_WDOG_CFG_PERSEL_SEL6 << 16) /**< Shifted mode SEL6 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL7 (_WDOG_CFG_PERSEL_SEL7 << 16) /**< Shifted mode SEL7 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL8 (_WDOG_CFG_PERSEL_SEL8 << 16) /**< Shifted mode SEL8 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL9 (_WDOG_CFG_PERSEL_SEL9 << 16) /**< Shifted mode SEL9 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL10 (_WDOG_CFG_PERSEL_SEL10 << 16) /**< Shifted mode SEL10 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL11 (_WDOG_CFG_PERSEL_SEL11 << 16) /**< Shifted mode SEL11 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL12 (_WDOG_CFG_PERSEL_SEL12 << 16) /**< Shifted mode SEL12 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL13 (_WDOG_CFG_PERSEL_SEL13 << 16) /**< Shifted mode SEL13 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL14 (_WDOG_CFG_PERSEL_SEL14 << 16) /**< Shifted mode SEL14 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL15 (_WDOG_CFG_PERSEL_SEL15 << 16) /**< Shifted mode SEL15 for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_SHIFT 24 /**< Shift value for WDOG_WARNSEL */ -#define _WDOG_CFG_WARNSEL_MASK 0x3000000UL /**< Bit mask for WDOG_WARNSEL */ -#define _WDOG_CFG_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_DEFAULT (_WDOG_CFG_WARNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_DIS (_WDOG_CFG_WARNSEL_DIS << 24) /**< Shifted mode DIS for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_SEL1 (_WDOG_CFG_WARNSEL_SEL1 << 24) /**< Shifted mode SEL1 for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_SEL2 (_WDOG_CFG_WARNSEL_SEL2 << 24) /**< Shifted mode SEL2 for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_SEL3 (_WDOG_CFG_WARNSEL_SEL3 << 24) /**< Shifted mode SEL3 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SHIFT 28 /**< Shift value for WDOG_WINSEL */ -#define _WDOG_CFG_WINSEL_MASK 0x70000000UL /**< Bit mask for WDOG_WINSEL */ -#define _WDOG_CFG_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_DEFAULT (_WDOG_CFG_WINSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_WINSEL_DIS (_WDOG_CFG_WINSEL_DIS << 28) /**< Shifted mode DIS for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL1 (_WDOG_CFG_WINSEL_SEL1 << 28) /**< Shifted mode SEL1 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL2 (_WDOG_CFG_WINSEL_SEL2 << 28) /**< Shifted mode SEL2 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL3 (_WDOG_CFG_WINSEL_SEL3 << 28) /**< Shifted mode SEL3 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL4 (_WDOG_CFG_WINSEL_SEL4 << 28) /**< Shifted mode SEL4 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL5 (_WDOG_CFG_WINSEL_SEL5 << 28) /**< Shifted mode SEL5 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL6 (_WDOG_CFG_WINSEL_SEL6 << 28) /**< Shifted mode SEL6 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL7 (_WDOG_CFG_WINSEL_SEL7 << 28) /**< Shifted mode SEL7 for WDOG_CFG */ +#define _WDOG_CFG_RESETVALUE 0x000F0000UL /**< Default value for WDOG_CFG */ +#define _WDOG_CFG_MASK 0x730F073FUL /**< Mask for WDOG_CFG */ +#define WDOG_CFG_CLRSRC (0x1UL << 0) /**< WDOG Clear Source */ +#define _WDOG_CFG_CLRSRC_SHIFT 0 /**< Shift value for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_MASK 0x1UL /**< Bit mask for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_DEFAULT (_WDOG_CFG_CLRSRC_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_SW (_WDOG_CFG_CLRSRC_SW << 0) /**< Shifted mode SW for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifted mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_EM1RUN (0x1UL << 1) /**< EM1 Run */ +#define _WDOG_CFG_EM1RUN_SHIFT 1 /**< Shift value for WDOG_EM1RUN */ +#define _WDOG_CFG_EM1RUN_MASK 0x2UL /**< Bit mask for WDOG_EM1RUN */ +#define _WDOG_CFG_EM1RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM1RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM1RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_DEFAULT (_WDOG_CFG_EM1RUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_DISABLE (_WDOG_CFG_EM1RUN_DISABLE << 1) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_ENABLE (_WDOG_CFG_EM1RUN_ENABLE << 1) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN (0x1UL << 2) /**< EM2 Run */ +#define _WDOG_CFG_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DEFAULT (_WDOG_CFG_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DISABLE (_WDOG_CFG_EM2RUN_DISABLE << 2) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_ENABLE (_WDOG_CFG_EM2RUN_ENABLE << 2) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN (0x1UL << 3) /**< EM3 Run */ +#define _WDOG_CFG_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DEFAULT (_WDOG_CFG_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DISABLE (_WDOG_CFG_EM3RUN_DISABLE << 3) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_ENABLE (_WDOG_CFG_EM3RUN_ENABLE << 3) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK (0x1UL << 4) /**< EM4 Block */ +#define _WDOG_CFG_EM4BLOCK_SHIFT 4 /**< Shift value for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_MASK 0x10UL /**< Bit mask for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DEFAULT (_WDOG_CFG_EM4BLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DISABLE (_WDOG_CFG_EM4BLOCK_DISABLE << 4) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_ENABLE (_WDOG_CFG_EM4BLOCK_ENABLE << 4) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN (0x1UL << 5) /**< Debug Mode Run */ +#define _WDOG_CFG_DEBUGRUN_SHIFT 5 /**< Shift value for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_MASK 0x20UL /**< Bit mask for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DEFAULT (_WDOG_CFG_DEBUGRUN_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DISABLE (_WDOG_CFG_DEBUGRUN_DISABLE << 5) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_ENABLE (_WDOG_CFG_DEBUGRUN_ENABLE << 5) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS (0x1UL << 8) /**< WDOG Reset Disable */ +#define _WDOG_CFG_WDOGRSTDIS_SHIFT 8 /**< Shift value for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_MASK 0x100UL /**< Bit mask for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DEFAULT (_WDOG_CFG_WDOGRSTDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_EN (_WDOG_CFG_WDOGRSTDIS_EN << 8) /**< Shifted mode EN for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DIS (_WDOG_CFG_WDOGRSTDIS_DIS << 8) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN (0x1UL << 9) /**< PRS Src0 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS0MISSRSTEN_SHIFT 9 /**< Shift value for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_MASK 0x200UL /**< Bit mask for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN_DEFAULT (_WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN (0x1UL << 10) /**< PRS Src1 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS1MISSRSTEN_SHIFT 10 /**< Shift value for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_MASK 0x400UL /**< Bit mask for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SHIFT 16 /**< Shift value for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_MASK 0xF0000UL /**< Bit mask for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL0 0x00000000UL /**< Mode SEL0 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL8 0x00000008UL /**< Mode SEL8 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL9 0x00000009UL /**< Mode SEL9 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL10 0x0000000AUL /**< Mode SEL10 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL11 0x0000000BUL /**< Mode SEL11 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL12 0x0000000CUL /**< Mode SEL12 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL13 0x0000000DUL /**< Mode SEL13 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL14 0x0000000EUL /**< Mode SEL14 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL15 0x0000000FUL /**< Mode SEL15 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_DEFAULT (_WDOG_CFG_PERSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL0 (_WDOG_CFG_PERSEL_SEL0 << 16) /**< Shifted mode SEL0 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL1 (_WDOG_CFG_PERSEL_SEL1 << 16) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL2 (_WDOG_CFG_PERSEL_SEL2 << 16) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL3 (_WDOG_CFG_PERSEL_SEL3 << 16) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL4 (_WDOG_CFG_PERSEL_SEL4 << 16) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL5 (_WDOG_CFG_PERSEL_SEL5 << 16) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL6 (_WDOG_CFG_PERSEL_SEL6 << 16) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL7 (_WDOG_CFG_PERSEL_SEL7 << 16) /**< Shifted mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL8 (_WDOG_CFG_PERSEL_SEL8 << 16) /**< Shifted mode SEL8 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL9 (_WDOG_CFG_PERSEL_SEL9 << 16) /**< Shifted mode SEL9 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL10 (_WDOG_CFG_PERSEL_SEL10 << 16) /**< Shifted mode SEL10 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL11 (_WDOG_CFG_PERSEL_SEL11 << 16) /**< Shifted mode SEL11 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL12 (_WDOG_CFG_PERSEL_SEL12 << 16) /**< Shifted mode SEL12 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL13 (_WDOG_CFG_PERSEL_SEL13 << 16) /**< Shifted mode SEL13 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL14 (_WDOG_CFG_PERSEL_SEL14 << 16) /**< Shifted mode SEL14 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL15 (_WDOG_CFG_PERSEL_SEL15 << 16) /**< Shifted mode SEL15 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SHIFT 24 /**< Shift value for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_MASK 0x3000000UL /**< Bit mask for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DEFAULT (_WDOG_CFG_WARNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DIS (_WDOG_CFG_WARNSEL_DIS << 24) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL1 (_WDOG_CFG_WARNSEL_SEL1 << 24) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL2 (_WDOG_CFG_WARNSEL_SEL2 << 24) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL3 (_WDOG_CFG_WARNSEL_SEL3 << 24) /**< Shifted mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SHIFT 28 /**< Shift value for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_MASK 0x70000000UL /**< Bit mask for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DEFAULT (_WDOG_CFG_WINSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DIS (_WDOG_CFG_WINSEL_DIS << 28) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL1 (_WDOG_CFG_WINSEL_SEL1 << 28) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL2 (_WDOG_CFG_WINSEL_SEL2 << 28) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL3 (_WDOG_CFG_WINSEL_SEL3 << 28) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL4 (_WDOG_CFG_WINSEL_SEL4 << 28) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL5 (_WDOG_CFG_WINSEL_SEL5 << 28) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL6 (_WDOG_CFG_WINSEL_SEL6 << 28) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL7 (_WDOG_CFG_WINSEL_SEL7 << 28) /**< Shifted mode SEL7 for WDOG_CFG */ /* Bit fields for WDOG CMD */ -#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ -#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ -#define WDOG_CMD_CLEAR (0x1UL << 0) /**< WDOG Timer Clear */ -#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ -#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ -#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ -#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ -#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ -#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ -#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ -#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ +#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ +#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ +#define WDOG_CMD_CLEAR (0x1UL << 0) /**< WDOG Timer Clear */ +#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ +#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ /* Bit fields for WDOG STATUS */ -#define _WDOG_STATUS_RESETVALUE 0x00000000UL /**< Default value for WDOG_STATUS */ -#define _WDOG_STATUS_MASK 0x80000000UL /**< Mask for WDOG_STATUS */ -#define WDOG_STATUS_LOCK (0x1UL << 31) /**< WDOG Configuration Lock Status */ -#define _WDOG_STATUS_LOCK_SHIFT 31 /**< Shift value for WDOG_LOCK */ -#define _WDOG_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for WDOG_LOCK */ -#define _WDOG_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_STATUS */ -#define _WDOG_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WDOG_STATUS */ -#define _WDOG_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for WDOG_STATUS */ -#define WDOG_STATUS_LOCK_DEFAULT (_WDOG_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_STATUS */ -#define WDOG_STATUS_LOCK_UNLOCKED (_WDOG_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for WDOG_STATUS */ -#define WDOG_STATUS_LOCK_LOCKED (_WDOG_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for WDOG_STATUS */ +#define _WDOG_STATUS_RESETVALUE 0x00000000UL /**< Default value for WDOG_STATUS */ +#define _WDOG_STATUS_MASK 0x80000000UL /**< Mask for WDOG_STATUS */ +#define WDOG_STATUS_LOCK (0x1UL << 31) /**< WDOG Configuration Lock Status */ +#define _WDOG_STATUS_LOCK_SHIFT 31 /**< Shift value for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_DEFAULT (_WDOG_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_UNLOCKED (_WDOG_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_LOCKED (_WDOG_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for WDOG_STATUS */ /* Bit fields for WDOG IF */ -#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ -#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ -#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ -#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ -#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ -#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ -#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ -#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ -#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ -#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ -#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ -#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Flag */ -#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ -#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ -#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Flag */ -#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ -#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ -#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ +#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ +#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ +#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ +#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ +#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ /* Bit fields for WDOG IEN */ -#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ -#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ -#define WDOG_IEN_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Enable */ -#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ -#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ -#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Enable */ -#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ -#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ -#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_WIN (0x1UL << 2) /**< WDOG Window Interrupt Enable */ -#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ -#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ -#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Enable */ -#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ -#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ -#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Enable */ -#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ -#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ -#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ +#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ +#define WDOG_IEN_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Enable */ +#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Enable */ +#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN (0x1UL << 2) /**< WDOG Window Interrupt Enable */ +#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ /* Bit fields for WDOG LOCK */ -#define _WDOG_LOCK_RESETVALUE 0x0000ABE8UL /**< Default value for WDOG_LOCK */ -#define _WDOG_LOCK_MASK 0x0000FFFFUL /**< Mask for WDOG_LOCK */ -#define _WDOG_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for WDOG_LOCKKEY */ -#define _WDOG_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for WDOG_LOCKKEY */ -#define _WDOG_LOCK_LOCKKEY_DEFAULT 0x0000ABE8UL /**< Mode DEFAULT for WDOG_LOCK */ -#define _WDOG_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WDOG_LOCK */ -#define _WDOG_LOCK_LOCKKEY_UNLOCK 0x0000ABE8UL /**< Mode UNLOCK for WDOG_LOCK */ -#define WDOG_LOCK_LOCKKEY_DEFAULT (_WDOG_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_LOCK */ -#define WDOG_LOCK_LOCKKEY_LOCK (_WDOG_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WDOG_LOCK */ -#define WDOG_LOCK_LOCKKEY_UNLOCK (_WDOG_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WDOG_LOCK */ +#define _WDOG_LOCK_RESETVALUE 0x0000ABE8UL /**< Default value for WDOG_LOCK */ +#define _WDOG_LOCK_MASK 0x0000FFFFUL /**< Mask for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_DEFAULT 0x0000ABE8UL /**< Mode DEFAULT for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_UNLOCK 0x0000ABE8UL /**< Mode UNLOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_DEFAULT (_WDOG_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_LOCK (_WDOG_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_UNLOCK (_WDOG_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WDOG_LOCK */ /* Bit fields for WDOG SYNCBUSY */ -#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ -#define _WDOG_SYNCBUSY_MASK 0x00000001UL /**< Mask for WDOG_SYNCBUSY */ -#define WDOG_SYNCBUSY_CMD (0x1UL << 0) /**< Sync Busy for Cmd Register */ -#define _WDOG_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for WDOG_CMD */ -#define _WDOG_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for WDOG_CMD */ -#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ -#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_MASK 0x00000001UL /**< Mask for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD (0x1UL << 0) /**< Sync Busy for Cmd Register */ +#define _WDOG_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ /** @} End of group EFR32SG23_WDOG_BitFields */ /** @} End of group EFR32SG23_WDOG */ diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23b020f512im40.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23b020f512im40.h index f276250919..a906ecebec 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23b020f512im40.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23b020f512im40.h @@ -4,7 +4,7 @@ * for EFR32SG23B020F512IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23b020f512im48.h b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23b020f512im48.h index b21bad7aa5..d8f94cba6a 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23b020f512im48.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/efr32sg23b020f512im48.h @@ -4,7 +4,7 @@ * for EFR32SG23B020F512IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/em_device.h b/platform/Device/SiliconLabs/EFR32SG23/Include/em_device.h index 6b4bf472d9..1c0d5b09a1 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Include/system_efr32sg23.h b/platform/Device/SiliconLabs/EFR32SG23/Include/system_efr32sg23.h index 9a412bf2a9..8e00176386 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Include/system_efr32sg23.h +++ b/platform/Device/SiliconLabs/EFR32SG23/Include/system_efr32sg23.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32SG23 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG23/Source/GCC/efr32sg23.ld b/platform/Device/SiliconLabs/EFR32SG23/Source/GCC/efr32sg23.ld index ac4e89601c..57160397aa 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Source/GCC/efr32sg23.ld +++ b/platform/Device/SiliconLabs/EFR32SG23/Source/GCC/efr32sg23.ld @@ -6,21 +6,21 @@ * Linker script for Silicon Labs EFR32SG23 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be diff --git a/platform/Device/SiliconLabs/EFR32SG23/Source/IAR/startup_efr32sg23.s b/platform/Device/SiliconLabs/EFR32SG23/Source/IAR/startup_efr32sg23.s index 7581823cb0..2881acb222 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Source/IAR/startup_efr32sg23.s +++ b/platform/Device/SiliconLabs/EFR32SG23/Source/IAR/startup_efr32sg23.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFR32SG23/Source/system_efr32sg23.c b/platform/Device/SiliconLabs/EFR32SG23/Source/system_efr32sg23.c index 4262b78c81..fe51ff152d 100644 --- a/platform/Device/SiliconLabs/EFR32SG23/Source/system_efr32sg23.c +++ b/platform/Device/SiliconLabs/EFR32SG23/Source/system_efr32sg23.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32SG23 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_acmp.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_acmp.h index 4228da8ccf..ec495b5ddb 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_acmp.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_acmp.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_ACMP_H #define EFR32SG28_ACMP_H - #define ACMP_HAS_SET_CLEAR /**************************************************************************//** @@ -43,51 +42,50 @@ *****************************************************************************/ /** ACMP Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t EN; /**< ACMP enable */ - __IOM uint32_t SWRST; /**< Software reset */ - __IOM uint32_t CFG; /**< Configuration register */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t INPUTCTRL; /**< Input Control Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY; /**< Syncbusy */ - uint32_t RESERVED0[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t EN_SET; /**< ACMP enable */ - __IOM uint32_t SWRST_SET; /**< Software reset */ - __IOM uint32_t CFG_SET; /**< Configuration register */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t INPUTCTRL_SET; /**< Input Control Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_SET; /**< Syncbusy */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t EN_CLR; /**< ACMP enable */ - __IOM uint32_t SWRST_CLR; /**< Software reset */ - __IOM uint32_t CFG_CLR; /**< Configuration register */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t INPUTCTRL_CLR; /**< Input Control Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy */ - uint32_t RESERVED2[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t EN_TGL; /**< ACMP enable */ - __IOM uint32_t SWRST_TGL; /**< Software reset */ - __IOM uint32_t CFG_TGL; /**< Configuration register */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t INPUTCTRL_TGL; /**< Input Control Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< ACMP enable */ + __IOM uint32_t SWRST; /**< Software reset */ + __IOM uint32_t CFG; /**< Configuration register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t INPUTCTRL; /**< Input Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Syncbusy */ + uint32_t RESERVED0[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< ACMP enable */ + __IOM uint32_t SWRST_SET; /**< Software reset */ + __IOM uint32_t CFG_SET; /**< Configuration register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t INPUTCTRL_SET; /**< Input Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Syncbusy */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< ACMP enable */ + __IOM uint32_t SWRST_CLR; /**< Software reset */ + __IOM uint32_t CFG_CLR; /**< Configuration register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t INPUTCTRL_CLR; /**< Input Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy */ + uint32_t RESERVED2[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< ACMP enable */ + __IOM uint32_t SWRST_TGL; /**< Software reset */ + __IOM uint32_t CFG_TGL; /**< Configuration register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t INPUTCTRL_TGL; /**< Input Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy */ } ACMP_TypeDef; /** @} End of group EFR32SG28_ACMP */ @@ -99,555 +97,555 @@ typedef struct *****************************************************************************/ /* Bit fields for ACMP IPVERSION */ -#define _ACMP_IPVERSION_RESETVALUE 0x00000004UL /**< Default value for ACMP_IPVERSION */ -#define _ACMP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ACMP_IPVERSION */ -#define _ACMP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ACMP_IPVERSION */ -#define _ACMP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ACMP_IPVERSION */ -#define _ACMP_IPVERSION_IPVERSION_DEFAULT 0x00000004UL /**< Mode DEFAULT for ACMP_IPVERSION */ -#define ACMP_IPVERSION_IPVERSION_DEFAULT (_ACMP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_RESETVALUE 0x00000004UL /**< Default value for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_DEFAULT 0x00000004UL /**< Mode DEFAULT for ACMP_IPVERSION */ +#define ACMP_IPVERSION_IPVERSION_DEFAULT (_ACMP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IPVERSION */ /* Bit fields for ACMP EN */ -#define _ACMP_EN_RESETVALUE 0x00000000UL /**< Default value for ACMP_EN */ -#define _ACMP_EN_MASK 0x00000003UL /**< Mask for ACMP_EN */ -#define ACMP_EN_EN (0x1UL << 0) /**< Module enable */ -#define _ACMP_EN_EN_SHIFT 0 /**< Shift value for ACMP_EN */ -#define _ACMP_EN_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ -#define _ACMP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ -#define ACMP_EN_EN_DEFAULT (_ACMP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EN */ -#define ACMP_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _ACMP_EN_DISABLING_SHIFT 1 /**< Shift value for ACMP_DISABLING */ -#define _ACMP_EN_DISABLING_MASK 0x2UL /**< Bit mask for ACMP_DISABLING */ -#define _ACMP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ -#define ACMP_EN_DISABLING_DEFAULT (_ACMP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_EN */ +#define _ACMP_EN_RESETVALUE 0x00000000UL /**< Default value for ACMP_EN */ +#define _ACMP_EN_MASK 0x00000003UL /**< Mask for ACMP_EN */ +#define ACMP_EN_EN (0x1UL << 0) /**< Module enable */ +#define _ACMP_EN_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_EN_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ +#define ACMP_EN_EN_DEFAULT (_ACMP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EN */ +#define ACMP_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _ACMP_EN_DISABLING_SHIFT 1 /**< Shift value for ACMP_DISABLING */ +#define _ACMP_EN_DISABLING_MASK 0x2UL /**< Bit mask for ACMP_DISABLING */ +#define _ACMP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ +#define ACMP_EN_DISABLING_DEFAULT (_ACMP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_EN */ /* Bit fields for ACMP SWRST */ -#define _ACMP_SWRST_RESETVALUE 0x00000000UL /**< Default value for ACMP_SWRST */ -#define _ACMP_SWRST_MASK 0x00000003UL /**< Mask for ACMP_SWRST */ -#define ACMP_SWRST_SWRST (0x1UL << 0) /**< Software reset */ -#define _ACMP_SWRST_SWRST_SHIFT 0 /**< Shift value for ACMP_SWRST */ -#define _ACMP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for ACMP_SWRST */ -#define _ACMP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ -#define ACMP_SWRST_SWRST_DEFAULT (_ACMP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SWRST */ -#define ACMP_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ -#define _ACMP_SWRST_RESETTING_SHIFT 1 /**< Shift value for ACMP_RESETTING */ -#define _ACMP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for ACMP_RESETTING */ -#define _ACMP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ -#define ACMP_SWRST_RESETTING_DEFAULT (_ACMP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_SWRST */ +#define _ACMP_SWRST_RESETVALUE 0x00000000UL /**< Default value for ACMP_SWRST */ +#define _ACMP_SWRST_MASK 0x00000003UL /**< Mask for ACMP_SWRST */ +#define ACMP_SWRST_SWRST (0x1UL << 0) /**< Software reset */ +#define _ACMP_SWRST_SWRST_SHIFT 0 /**< Shift value for ACMP_SWRST */ +#define _ACMP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for ACMP_SWRST */ +#define _ACMP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_SWRST_DEFAULT (_ACMP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _ACMP_SWRST_RESETTING_SHIFT 1 /**< Shift value for ACMP_RESETTING */ +#define _ACMP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for ACMP_RESETTING */ +#define _ACMP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_RESETTING_DEFAULT (_ACMP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_SWRST */ /* Bit fields for ACMP CFG */ -#define _ACMP_CFG_RESETVALUE 0x00000004UL /**< Default value for ACMP_CFG */ -#define _ACMP_CFG_MASK 0x00030F07UL /**< Mask for ACMP_CFG */ -#define _ACMP_CFG_BIAS_SHIFT 0 /**< Shift value for ACMP_BIAS */ -#define _ACMP_CFG_BIAS_MASK 0x7UL /**< Bit mask for ACMP_BIAS */ -#define _ACMP_CFG_BIAS_DEFAULT 0x00000004UL /**< Mode DEFAULT for ACMP_CFG */ -#define ACMP_CFG_BIAS_DEFAULT (_ACMP_CFG_BIAS_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CFG */ -#define _ACMP_CFG_HYST_SHIFT 8 /**< Shift value for ACMP_HYST */ -#define _ACMP_CFG_HYST_MASK 0xF00UL /**< Bit mask for ACMP_HYST */ -#define _ACMP_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ -#define _ACMP_CFG_HYST_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CFG */ -#define _ACMP_CFG_HYST_SYM10MV 0x00000001UL /**< Mode SYM10MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_SYM20MV 0x00000002UL /**< Mode SYM20MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_SYM30MV 0x00000003UL /**< Mode SYM30MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_POS10MV 0x00000004UL /**< Mode POS10MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_POS20MV 0x00000005UL /**< Mode POS20MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_POS30MV 0x00000006UL /**< Mode POS30MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_NEG10MV 0x00000008UL /**< Mode NEG10MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_NEG20MV 0x00000009UL /**< Mode NEG20MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_NEG30MV 0x0000000AUL /**< Mode NEG30MV for ACMP_CFG */ -#define ACMP_CFG_HYST_DEFAULT (_ACMP_CFG_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CFG */ -#define ACMP_CFG_HYST_DISABLED (_ACMP_CFG_HYST_DISABLED << 8) /**< Shifted mode DISABLED for ACMP_CFG */ -#define ACMP_CFG_HYST_SYM10MV (_ACMP_CFG_HYST_SYM10MV << 8) /**< Shifted mode SYM10MV for ACMP_CFG */ -#define ACMP_CFG_HYST_SYM20MV (_ACMP_CFG_HYST_SYM20MV << 8) /**< Shifted mode SYM20MV for ACMP_CFG */ -#define ACMP_CFG_HYST_SYM30MV (_ACMP_CFG_HYST_SYM30MV << 8) /**< Shifted mode SYM30MV for ACMP_CFG */ -#define ACMP_CFG_HYST_POS10MV (_ACMP_CFG_HYST_POS10MV << 8) /**< Shifted mode POS10MV for ACMP_CFG */ -#define ACMP_CFG_HYST_POS20MV (_ACMP_CFG_HYST_POS20MV << 8) /**< Shifted mode POS20MV for ACMP_CFG */ -#define ACMP_CFG_HYST_POS30MV (_ACMP_CFG_HYST_POS30MV << 8) /**< Shifted mode POS30MV for ACMP_CFG */ -#define ACMP_CFG_HYST_NEG10MV (_ACMP_CFG_HYST_NEG10MV << 8) /**< Shifted mode NEG10MV for ACMP_CFG */ -#define ACMP_CFG_HYST_NEG20MV (_ACMP_CFG_HYST_NEG20MV << 8) /**< Shifted mode NEG20MV for ACMP_CFG */ -#define ACMP_CFG_HYST_NEG30MV (_ACMP_CFG_HYST_NEG30MV << 8) /**< Shifted mode NEG30MV for ACMP_CFG */ -#define ACMP_CFG_INPUTRANGE (0x1UL << 16) /**< Input Range */ -#define _ACMP_CFG_INPUTRANGE_SHIFT 16 /**< Shift value for ACMP_INPUTRANGE */ -#define _ACMP_CFG_INPUTRANGE_MASK 0x10000UL /**< Bit mask for ACMP_INPUTRANGE */ -#define _ACMP_CFG_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ -#define _ACMP_CFG_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CFG */ -#define _ACMP_CFG_INPUTRANGE_REDUCED 0x00000001UL /**< Mode REDUCED for ACMP_CFG */ -#define ACMP_CFG_INPUTRANGE_DEFAULT (_ACMP_CFG_INPUTRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CFG */ -#define ACMP_CFG_INPUTRANGE_FULL (_ACMP_CFG_INPUTRANGE_FULL << 16) /**< Shifted mode FULL for ACMP_CFG */ -#define ACMP_CFG_INPUTRANGE_REDUCED (_ACMP_CFG_INPUTRANGE_REDUCED << 16) /**< Shifted mode REDUCED for ACMP_CFG */ -#define ACMP_CFG_ACCURACY (0x1UL << 17) /**< ACMP accuracy mode */ -#define _ACMP_CFG_ACCURACY_SHIFT 17 /**< Shift value for ACMP_ACCURACY */ -#define _ACMP_CFG_ACCURACY_MASK 0x20000UL /**< Bit mask for ACMP_ACCURACY */ -#define _ACMP_CFG_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ -#define _ACMP_CFG_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CFG */ -#define _ACMP_CFG_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CFG */ -#define ACMP_CFG_ACCURACY_DEFAULT (_ACMP_CFG_ACCURACY_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CFG */ -#define ACMP_CFG_ACCURACY_LOW (_ACMP_CFG_ACCURACY_LOW << 17) /**< Shifted mode LOW for ACMP_CFG */ -#define ACMP_CFG_ACCURACY_HIGH (_ACMP_CFG_ACCURACY_HIGH << 17) /**< Shifted mode HIGH for ACMP_CFG */ +#define _ACMP_CFG_RESETVALUE 0x00000004UL /**< Default value for ACMP_CFG */ +#define _ACMP_CFG_MASK 0x00030F07UL /**< Mask for ACMP_CFG */ +#define _ACMP_CFG_BIAS_SHIFT 0 /**< Shift value for ACMP_BIAS */ +#define _ACMP_CFG_BIAS_MASK 0x7UL /**< Bit mask for ACMP_BIAS */ +#define _ACMP_CFG_BIAS_DEFAULT 0x00000004UL /**< Mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_BIAS_DEFAULT (_ACMP_CFG_BIAS_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_HYST_SHIFT 8 /**< Shift value for ACMP_HYST */ +#define _ACMP_CFG_HYST_MASK 0xF00UL /**< Bit mask for ACMP_HYST */ +#define _ACMP_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_HYST_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM10MV 0x00000001UL /**< Mode SYM10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM20MV 0x00000002UL /**< Mode SYM20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM30MV 0x00000003UL /**< Mode SYM30MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS10MV 0x00000004UL /**< Mode POS10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS20MV 0x00000005UL /**< Mode POS20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS30MV 0x00000006UL /**< Mode POS30MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG10MV 0x00000008UL /**< Mode NEG10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG20MV 0x00000009UL /**< Mode NEG20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG30MV 0x0000000AUL /**< Mode NEG30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_DEFAULT (_ACMP_CFG_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_HYST_DISABLED (_ACMP_CFG_HYST_DISABLED << 8) /**< Shifted mode DISABLED for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM10MV (_ACMP_CFG_HYST_SYM10MV << 8) /**< Shifted mode SYM10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM20MV (_ACMP_CFG_HYST_SYM20MV << 8) /**< Shifted mode SYM20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM30MV (_ACMP_CFG_HYST_SYM30MV << 8) /**< Shifted mode SYM30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS10MV (_ACMP_CFG_HYST_POS10MV << 8) /**< Shifted mode POS10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS20MV (_ACMP_CFG_HYST_POS20MV << 8) /**< Shifted mode POS20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS30MV (_ACMP_CFG_HYST_POS30MV << 8) /**< Shifted mode POS30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG10MV (_ACMP_CFG_HYST_NEG10MV << 8) /**< Shifted mode NEG10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG20MV (_ACMP_CFG_HYST_NEG20MV << 8) /**< Shifted mode NEG20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG30MV (_ACMP_CFG_HYST_NEG30MV << 8) /**< Shifted mode NEG30MV for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE (0x1UL << 16) /**< Input Range */ +#define _ACMP_CFG_INPUTRANGE_SHIFT 16 /**< Shift value for ACMP_INPUTRANGE */ +#define _ACMP_CFG_INPUTRANGE_MASK 0x10000UL /**< Bit mask for ACMP_INPUTRANGE */ +#define _ACMP_CFG_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CFG */ +#define _ACMP_CFG_INPUTRANGE_REDUCED 0x00000001UL /**< Mode REDUCED for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_DEFAULT (_ACMP_CFG_INPUTRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_FULL (_ACMP_CFG_INPUTRANGE_FULL << 16) /**< Shifted mode FULL for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_REDUCED (_ACMP_CFG_INPUTRANGE_REDUCED << 16) /**< Shifted mode REDUCED for ACMP_CFG */ +#define ACMP_CFG_ACCURACY (0x1UL << 17) /**< ACMP accuracy mode */ +#define _ACMP_CFG_ACCURACY_SHIFT 17 /**< Shift value for ACMP_ACCURACY */ +#define _ACMP_CFG_ACCURACY_MASK 0x20000UL /**< Bit mask for ACMP_ACCURACY */ +#define _ACMP_CFG_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CFG */ +#define _ACMP_CFG_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_DEFAULT (_ACMP_CFG_ACCURACY_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_LOW (_ACMP_CFG_ACCURACY_LOW << 17) /**< Shifted mode LOW for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_HIGH (_ACMP_CFG_ACCURACY_HIGH << 17) /**< Shifted mode HIGH for ACMP_CFG */ /* Bit fields for ACMP CTRL */ -#define _ACMP_CTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_CTRL */ -#define _ACMP_CTRL_MASK 0x00000003UL /**< Mask for ACMP_CTRL */ -#define ACMP_CTRL_NOTRDYVAL (0x1UL << 0) /**< Not Ready Value */ -#define _ACMP_CTRL_NOTRDYVAL_SHIFT 0 /**< Shift value for ACMP_NOTRDYVAL */ -#define _ACMP_CTRL_NOTRDYVAL_MASK 0x1UL /**< Bit mask for ACMP_NOTRDYVAL */ -#define _ACMP_CTRL_NOTRDYVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ -#define _ACMP_CTRL_NOTRDYVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ -#define _ACMP_CTRL_NOTRDYVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ -#define ACMP_CTRL_NOTRDYVAL_DEFAULT (_ACMP_CTRL_NOTRDYVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ -#define ACMP_CTRL_NOTRDYVAL_LOW (_ACMP_CTRL_NOTRDYVAL_LOW << 0) /**< Shifted mode LOW for ACMP_CTRL */ -#define ACMP_CTRL_NOTRDYVAL_HIGH (_ACMP_CTRL_NOTRDYVAL_HIGH << 0) /**< Shifted mode HIGH for ACMP_CTRL */ -#define ACMP_CTRL_GPIOINV (0x1UL << 1) /**< Comparator GPIO Output Invert */ -#define _ACMP_CTRL_GPIOINV_SHIFT 1 /**< Shift value for ACMP_GPIOINV */ -#define _ACMP_CTRL_GPIOINV_MASK 0x2UL /**< Bit mask for ACMP_GPIOINV */ -#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ -#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ -#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ -#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */ -#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 1) /**< Shifted mode NOTINV for ACMP_CTRL */ -#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 1) /**< Shifted mode INV for ACMP_CTRL */ +#define _ACMP_CTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_CTRL */ +#define _ACMP_CTRL_MASK 0x00000003UL /**< Mask for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL (0x1UL << 0) /**< Not Ready Value */ +#define _ACMP_CTRL_NOTRDYVAL_SHIFT 0 /**< Shift value for ACMP_NOTRDYVAL */ +#define _ACMP_CTRL_NOTRDYVAL_MASK 0x1UL /**< Bit mask for ACMP_NOTRDYVAL */ +#define _ACMP_CTRL_NOTRDYVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_NOTRDYVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_NOTRDYVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_DEFAULT (_ACMP_CTRL_NOTRDYVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_LOW (_ACMP_CTRL_NOTRDYVAL_LOW << 0) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_HIGH (_ACMP_CTRL_NOTRDYVAL_HIGH << 0) /**< Shifted mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV (0x1UL << 1) /**< Comparator GPIO Output Invert */ +#define _ACMP_CTRL_GPIOINV_SHIFT 1 /**< Shift value for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_MASK 0x2UL /**< Bit mask for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 1) /**< Shifted mode NOTINV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 1) /**< Shifted mode INV for ACMP_CTRL */ /* Bit fields for ACMP INPUTCTRL */ -#define _ACMP_INPUTCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_MASK 0x703FFFFFUL /**< Mask for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ -#define _ACMP_INPUTCTRL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */ -#define _ACMP_INPUTCTRL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VDACOUT0 0x00000040UL /**< Mode VDACOUT0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VDACOUT1 0x00000041UL /**< Mode VDACOUT1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_EXTPA 0x00000050UL /**< Mode EXTPA for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_EXTPB 0x00000051UL /**< Mode EXTPB for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_EXTPC 0x00000052UL /**< Mode EXTPC for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_EXTPD 0x00000053UL /**< Mode EXTPD for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_DEFAULT (_ACMP_INPUTCTRL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VSS (_ACMP_INPUTCTRL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD << 0) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP << 0) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 << 0) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP << 0) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 << 0) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP << 0) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 << 0) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP << 0) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 << 0) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP << 0) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VDACOUT0 (_ACMP_INPUTCTRL_POSSEL_VDACOUT0 << 0) /**< Shifted mode VDACOUT0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VDACOUT1 (_ACMP_INPUTCTRL_POSSEL_VDACOUT1 << 0) /**< Shifted mode VDACOUT1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_EXTPA (_ACMP_INPUTCTRL_POSSEL_EXTPA << 0) /**< Shifted mode EXTPA for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_EXTPB (_ACMP_INPUTCTRL_POSSEL_EXTPB << 0) /**< Shifted mode EXTPB for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_EXTPC (_ACMP_INPUTCTRL_POSSEL_EXTPC << 0) /**< Shifted mode EXTPC for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_EXTPD (_ACMP_INPUTCTRL_POSSEL_EXTPD << 0) /**< Shifted mode EXTPD for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA0 (_ACMP_INPUTCTRL_POSSEL_PA0 << 0) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA1 (_ACMP_INPUTCTRL_POSSEL_PA1 << 0) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA2 (_ACMP_INPUTCTRL_POSSEL_PA2 << 0) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA3 (_ACMP_INPUTCTRL_POSSEL_PA3 << 0) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA4 (_ACMP_INPUTCTRL_POSSEL_PA4 << 0) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA5 (_ACMP_INPUTCTRL_POSSEL_PA5 << 0) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA6 (_ACMP_INPUTCTRL_POSSEL_PA6 << 0) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA7 (_ACMP_INPUTCTRL_POSSEL_PA7 << 0) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA8 (_ACMP_INPUTCTRL_POSSEL_PA8 << 0) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA9 (_ACMP_INPUTCTRL_POSSEL_PA9 << 0) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA10 (_ACMP_INPUTCTRL_POSSEL_PA10 << 0) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA11 (_ACMP_INPUTCTRL_POSSEL_PA11 << 0) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA12 (_ACMP_INPUTCTRL_POSSEL_PA12 << 0) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA13 (_ACMP_INPUTCTRL_POSSEL_PA13 << 0) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA14 (_ACMP_INPUTCTRL_POSSEL_PA14 << 0) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA15 (_ACMP_INPUTCTRL_POSSEL_PA15 << 0) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB0 (_ACMP_INPUTCTRL_POSSEL_PB0 << 0) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB1 (_ACMP_INPUTCTRL_POSSEL_PB1 << 0) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB2 (_ACMP_INPUTCTRL_POSSEL_PB2 << 0) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB3 (_ACMP_INPUTCTRL_POSSEL_PB3 << 0) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB4 (_ACMP_INPUTCTRL_POSSEL_PB4 << 0) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB5 (_ACMP_INPUTCTRL_POSSEL_PB5 << 0) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB6 (_ACMP_INPUTCTRL_POSSEL_PB6 << 0) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB7 (_ACMP_INPUTCTRL_POSSEL_PB7 << 0) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB8 (_ACMP_INPUTCTRL_POSSEL_PB8 << 0) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB9 (_ACMP_INPUTCTRL_POSSEL_PB9 << 0) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB10 (_ACMP_INPUTCTRL_POSSEL_PB10 << 0) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB11 (_ACMP_INPUTCTRL_POSSEL_PB11 << 0) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB12 (_ACMP_INPUTCTRL_POSSEL_PB12 << 0) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB13 (_ACMP_INPUTCTRL_POSSEL_PB13 << 0) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB14 (_ACMP_INPUTCTRL_POSSEL_PB14 << 0) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB15 (_ACMP_INPUTCTRL_POSSEL_PB15 << 0) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC0 (_ACMP_INPUTCTRL_POSSEL_PC0 << 0) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC1 (_ACMP_INPUTCTRL_POSSEL_PC1 << 0) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC2 (_ACMP_INPUTCTRL_POSSEL_PC2 << 0) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC3 (_ACMP_INPUTCTRL_POSSEL_PC3 << 0) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC4 (_ACMP_INPUTCTRL_POSSEL_PC4 << 0) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC5 (_ACMP_INPUTCTRL_POSSEL_PC5 << 0) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC6 (_ACMP_INPUTCTRL_POSSEL_PC6 << 0) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC7 (_ACMP_INPUTCTRL_POSSEL_PC7 << 0) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC8 (_ACMP_INPUTCTRL_POSSEL_PC8 << 0) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC9 (_ACMP_INPUTCTRL_POSSEL_PC9 << 0) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC10 (_ACMP_INPUTCTRL_POSSEL_PC10 << 0) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC11 (_ACMP_INPUTCTRL_POSSEL_PC11 << 0) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC12 (_ACMP_INPUTCTRL_POSSEL_PC12 << 0) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC13 (_ACMP_INPUTCTRL_POSSEL_PC13 << 0) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC14 (_ACMP_INPUTCTRL_POSSEL_PC14 << 0) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC15 (_ACMP_INPUTCTRL_POSSEL_PC15 << 0) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD0 (_ACMP_INPUTCTRL_POSSEL_PD0 << 0) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD1 (_ACMP_INPUTCTRL_POSSEL_PD1 << 0) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD2 (_ACMP_INPUTCTRL_POSSEL_PD2 << 0) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD3 (_ACMP_INPUTCTRL_POSSEL_PD3 << 0) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD4 (_ACMP_INPUTCTRL_POSSEL_PD4 << 0) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD5 (_ACMP_INPUTCTRL_POSSEL_PD5 << 0) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD6 (_ACMP_INPUTCTRL_POSSEL_PD6 << 0) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD7 (_ACMP_INPUTCTRL_POSSEL_PD7 << 0) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD8 (_ACMP_INPUTCTRL_POSSEL_PD8 << 0) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD9 (_ACMP_INPUTCTRL_POSSEL_PD9 << 0) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD10 (_ACMP_INPUTCTRL_POSSEL_PD10 << 0) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD11 (_ACMP_INPUTCTRL_POSSEL_PD11 << 0) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD12 (_ACMP_INPUTCTRL_POSSEL_PD12 << 0) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD13 (_ACMP_INPUTCTRL_POSSEL_PD13 << 0) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD14 (_ACMP_INPUTCTRL_POSSEL_PD14 << 0) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD15 (_ACMP_INPUTCTRL_POSSEL_PD15 << 0) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */ -#define _ACMP_INPUTCTRL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */ -#define _ACMP_INPUTCTRL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_CAPSENSE 0x00000030UL /**< Mode CAPSENSE for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VDACOUT0 0x00000040UL /**< Mode VDACOUT0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VDACOUT1 0x00000041UL /**< Mode VDACOUT1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_DEFAULT (_ACMP_INPUTCTRL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VSS (_ACMP_INPUTCTRL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD << 8) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP << 8) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 << 8) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP << 8) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 << 8) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP << 8) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 << 8) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP << 8) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 << 8) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP << 8) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_CAPSENSE (_ACMP_INPUTCTRL_NEGSEL_CAPSENSE << 8) /**< Shifted mode CAPSENSE for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VDACOUT0 (_ACMP_INPUTCTRL_NEGSEL_VDACOUT0 << 8) /**< Shifted mode VDACOUT0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VDACOUT1 (_ACMP_INPUTCTRL_NEGSEL_VDACOUT1 << 8) /**< Shifted mode VDACOUT1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA0 (_ACMP_INPUTCTRL_NEGSEL_PA0 << 8) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA1 (_ACMP_INPUTCTRL_NEGSEL_PA1 << 8) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA2 (_ACMP_INPUTCTRL_NEGSEL_PA2 << 8) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA3 (_ACMP_INPUTCTRL_NEGSEL_PA3 << 8) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA4 (_ACMP_INPUTCTRL_NEGSEL_PA4 << 8) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA5 (_ACMP_INPUTCTRL_NEGSEL_PA5 << 8) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA6 (_ACMP_INPUTCTRL_NEGSEL_PA6 << 8) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA7 (_ACMP_INPUTCTRL_NEGSEL_PA7 << 8) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA8 (_ACMP_INPUTCTRL_NEGSEL_PA8 << 8) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA9 (_ACMP_INPUTCTRL_NEGSEL_PA9 << 8) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA10 (_ACMP_INPUTCTRL_NEGSEL_PA10 << 8) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA11 (_ACMP_INPUTCTRL_NEGSEL_PA11 << 8) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA12 (_ACMP_INPUTCTRL_NEGSEL_PA12 << 8) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA13 (_ACMP_INPUTCTRL_NEGSEL_PA13 << 8) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA14 (_ACMP_INPUTCTRL_NEGSEL_PA14 << 8) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA15 (_ACMP_INPUTCTRL_NEGSEL_PA15 << 8) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB0 (_ACMP_INPUTCTRL_NEGSEL_PB0 << 8) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB1 (_ACMP_INPUTCTRL_NEGSEL_PB1 << 8) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB2 (_ACMP_INPUTCTRL_NEGSEL_PB2 << 8) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB3 (_ACMP_INPUTCTRL_NEGSEL_PB3 << 8) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB4 (_ACMP_INPUTCTRL_NEGSEL_PB4 << 8) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB5 (_ACMP_INPUTCTRL_NEGSEL_PB5 << 8) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB6 (_ACMP_INPUTCTRL_NEGSEL_PB6 << 8) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB7 (_ACMP_INPUTCTRL_NEGSEL_PB7 << 8) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB8 (_ACMP_INPUTCTRL_NEGSEL_PB8 << 8) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB9 (_ACMP_INPUTCTRL_NEGSEL_PB9 << 8) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB10 (_ACMP_INPUTCTRL_NEGSEL_PB10 << 8) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB11 (_ACMP_INPUTCTRL_NEGSEL_PB11 << 8) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB12 (_ACMP_INPUTCTRL_NEGSEL_PB12 << 8) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB13 (_ACMP_INPUTCTRL_NEGSEL_PB13 << 8) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB14 (_ACMP_INPUTCTRL_NEGSEL_PB14 << 8) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB15 (_ACMP_INPUTCTRL_NEGSEL_PB15 << 8) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC0 (_ACMP_INPUTCTRL_NEGSEL_PC0 << 8) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC1 (_ACMP_INPUTCTRL_NEGSEL_PC1 << 8) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC2 (_ACMP_INPUTCTRL_NEGSEL_PC2 << 8) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC3 (_ACMP_INPUTCTRL_NEGSEL_PC3 << 8) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC4 (_ACMP_INPUTCTRL_NEGSEL_PC4 << 8) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC5 (_ACMP_INPUTCTRL_NEGSEL_PC5 << 8) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC6 (_ACMP_INPUTCTRL_NEGSEL_PC6 << 8) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC7 (_ACMP_INPUTCTRL_NEGSEL_PC7 << 8) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC8 (_ACMP_INPUTCTRL_NEGSEL_PC8 << 8) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC9 (_ACMP_INPUTCTRL_NEGSEL_PC9 << 8) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC10 (_ACMP_INPUTCTRL_NEGSEL_PC10 << 8) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC11 (_ACMP_INPUTCTRL_NEGSEL_PC11 << 8) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC12 (_ACMP_INPUTCTRL_NEGSEL_PC12 << 8) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC13 (_ACMP_INPUTCTRL_NEGSEL_PC13 << 8) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC14 (_ACMP_INPUTCTRL_NEGSEL_PC14 << 8) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC15 (_ACMP_INPUTCTRL_NEGSEL_PC15 << 8) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD0 (_ACMP_INPUTCTRL_NEGSEL_PD0 << 8) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD1 (_ACMP_INPUTCTRL_NEGSEL_PD1 << 8) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD2 (_ACMP_INPUTCTRL_NEGSEL_PD2 << 8) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD3 (_ACMP_INPUTCTRL_NEGSEL_PD3 << 8) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD4 (_ACMP_INPUTCTRL_NEGSEL_PD4 << 8) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD5 (_ACMP_INPUTCTRL_NEGSEL_PD5 << 8) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD6 (_ACMP_INPUTCTRL_NEGSEL_PD6 << 8) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD7 (_ACMP_INPUTCTRL_NEGSEL_PD7 << 8) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD8 (_ACMP_INPUTCTRL_NEGSEL_PD8 << 8) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD9 (_ACMP_INPUTCTRL_NEGSEL_PD9 << 8) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD10 (_ACMP_INPUTCTRL_NEGSEL_PD10 << 8) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD11 (_ACMP_INPUTCTRL_NEGSEL_PD11 << 8) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD12 (_ACMP_INPUTCTRL_NEGSEL_PD12 << 8) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD13 (_ACMP_INPUTCTRL_NEGSEL_PD13 << 8) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD14 (_ACMP_INPUTCTRL_NEGSEL_PD14 << 8) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD15 (_ACMP_INPUTCTRL_NEGSEL_PD15 << 8) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_VREFDIV_SHIFT 16 /**< Shift value for ACMP_VREFDIV */ -#define _ACMP_INPUTCTRL_VREFDIV_MASK 0x3F0000UL /**< Bit mask for ACMP_VREFDIV */ -#define _ACMP_INPUTCTRL_VREFDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_VREFDIV_DEFAULT (_ACMP_INPUTCTRL_VREFDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ -#define _ACMP_INPUTCTRL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */ -#define _ACMP_INPUTCTRL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_DEFAULT (_ACMP_INPUTCTRL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES0 (_ACMP_INPUTCTRL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES1 (_ACMP_INPUTCTRL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES2 (_ACMP_INPUTCTRL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES3 (_ACMP_INPUTCTRL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES4 (_ACMP_INPUTCTRL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES5 (_ACMP_INPUTCTRL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES6 (_ACMP_INPUTCTRL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_MASK 0x703FFFFFUL /**< Mask for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ +#define _ACMP_INPUTCTRL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */ +#define _ACMP_INPUTCTRL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VDACOUT0 0x00000040UL /**< Mode VDACOUT0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VDACOUT1 0x00000041UL /**< Mode VDACOUT1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPA 0x00000050UL /**< Mode EXTPA for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPB 0x00000051UL /**< Mode EXTPB for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPC 0x00000052UL /**< Mode EXTPC for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPD 0x00000053UL /**< Mode EXTPD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_DEFAULT (_ACMP_INPUTCTRL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VSS (_ACMP_INPUTCTRL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD << 0) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP << 0) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 << 0) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP << 0) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 << 0) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP << 0) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 << 0) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP << 0) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 << 0) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP << 0) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VDACOUT0 (_ACMP_INPUTCTRL_POSSEL_VDACOUT0 << 0) /**< Shifted mode VDACOUT0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VDACOUT1 (_ACMP_INPUTCTRL_POSSEL_VDACOUT1 << 0) /**< Shifted mode VDACOUT1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPA (_ACMP_INPUTCTRL_POSSEL_EXTPA << 0) /**< Shifted mode EXTPA for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPB (_ACMP_INPUTCTRL_POSSEL_EXTPB << 0) /**< Shifted mode EXTPB for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPC (_ACMP_INPUTCTRL_POSSEL_EXTPC << 0) /**< Shifted mode EXTPC for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPD (_ACMP_INPUTCTRL_POSSEL_EXTPD << 0) /**< Shifted mode EXTPD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA0 (_ACMP_INPUTCTRL_POSSEL_PA0 << 0) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA1 (_ACMP_INPUTCTRL_POSSEL_PA1 << 0) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA2 (_ACMP_INPUTCTRL_POSSEL_PA2 << 0) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA3 (_ACMP_INPUTCTRL_POSSEL_PA3 << 0) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA4 (_ACMP_INPUTCTRL_POSSEL_PA4 << 0) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA5 (_ACMP_INPUTCTRL_POSSEL_PA5 << 0) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA6 (_ACMP_INPUTCTRL_POSSEL_PA6 << 0) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA7 (_ACMP_INPUTCTRL_POSSEL_PA7 << 0) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA8 (_ACMP_INPUTCTRL_POSSEL_PA8 << 0) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA9 (_ACMP_INPUTCTRL_POSSEL_PA9 << 0) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA10 (_ACMP_INPUTCTRL_POSSEL_PA10 << 0) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA11 (_ACMP_INPUTCTRL_POSSEL_PA11 << 0) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA12 (_ACMP_INPUTCTRL_POSSEL_PA12 << 0) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA13 (_ACMP_INPUTCTRL_POSSEL_PA13 << 0) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA14 (_ACMP_INPUTCTRL_POSSEL_PA14 << 0) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA15 (_ACMP_INPUTCTRL_POSSEL_PA15 << 0) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB0 (_ACMP_INPUTCTRL_POSSEL_PB0 << 0) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB1 (_ACMP_INPUTCTRL_POSSEL_PB1 << 0) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB2 (_ACMP_INPUTCTRL_POSSEL_PB2 << 0) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB3 (_ACMP_INPUTCTRL_POSSEL_PB3 << 0) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB4 (_ACMP_INPUTCTRL_POSSEL_PB4 << 0) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB5 (_ACMP_INPUTCTRL_POSSEL_PB5 << 0) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB6 (_ACMP_INPUTCTRL_POSSEL_PB6 << 0) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB7 (_ACMP_INPUTCTRL_POSSEL_PB7 << 0) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB8 (_ACMP_INPUTCTRL_POSSEL_PB8 << 0) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB9 (_ACMP_INPUTCTRL_POSSEL_PB9 << 0) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB10 (_ACMP_INPUTCTRL_POSSEL_PB10 << 0) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB11 (_ACMP_INPUTCTRL_POSSEL_PB11 << 0) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB12 (_ACMP_INPUTCTRL_POSSEL_PB12 << 0) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB13 (_ACMP_INPUTCTRL_POSSEL_PB13 << 0) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB14 (_ACMP_INPUTCTRL_POSSEL_PB14 << 0) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB15 (_ACMP_INPUTCTRL_POSSEL_PB15 << 0) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC0 (_ACMP_INPUTCTRL_POSSEL_PC0 << 0) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC1 (_ACMP_INPUTCTRL_POSSEL_PC1 << 0) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC2 (_ACMP_INPUTCTRL_POSSEL_PC2 << 0) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC3 (_ACMP_INPUTCTRL_POSSEL_PC3 << 0) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC4 (_ACMP_INPUTCTRL_POSSEL_PC4 << 0) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC5 (_ACMP_INPUTCTRL_POSSEL_PC5 << 0) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC6 (_ACMP_INPUTCTRL_POSSEL_PC6 << 0) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC7 (_ACMP_INPUTCTRL_POSSEL_PC7 << 0) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC8 (_ACMP_INPUTCTRL_POSSEL_PC8 << 0) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC9 (_ACMP_INPUTCTRL_POSSEL_PC9 << 0) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC10 (_ACMP_INPUTCTRL_POSSEL_PC10 << 0) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC11 (_ACMP_INPUTCTRL_POSSEL_PC11 << 0) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC12 (_ACMP_INPUTCTRL_POSSEL_PC12 << 0) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC13 (_ACMP_INPUTCTRL_POSSEL_PC13 << 0) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC14 (_ACMP_INPUTCTRL_POSSEL_PC14 << 0) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC15 (_ACMP_INPUTCTRL_POSSEL_PC15 << 0) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD0 (_ACMP_INPUTCTRL_POSSEL_PD0 << 0) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD1 (_ACMP_INPUTCTRL_POSSEL_PD1 << 0) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD2 (_ACMP_INPUTCTRL_POSSEL_PD2 << 0) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD3 (_ACMP_INPUTCTRL_POSSEL_PD3 << 0) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD4 (_ACMP_INPUTCTRL_POSSEL_PD4 << 0) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD5 (_ACMP_INPUTCTRL_POSSEL_PD5 << 0) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD6 (_ACMP_INPUTCTRL_POSSEL_PD6 << 0) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD7 (_ACMP_INPUTCTRL_POSSEL_PD7 << 0) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD8 (_ACMP_INPUTCTRL_POSSEL_PD8 << 0) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD9 (_ACMP_INPUTCTRL_POSSEL_PD9 << 0) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD10 (_ACMP_INPUTCTRL_POSSEL_PD10 << 0) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD11 (_ACMP_INPUTCTRL_POSSEL_PD11 << 0) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD12 (_ACMP_INPUTCTRL_POSSEL_PD12 << 0) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD13 (_ACMP_INPUTCTRL_POSSEL_PD13 << 0) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD14 (_ACMP_INPUTCTRL_POSSEL_PD14 << 0) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD15 (_ACMP_INPUTCTRL_POSSEL_PD15 << 0) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */ +#define _ACMP_INPUTCTRL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */ +#define _ACMP_INPUTCTRL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_CAPSENSE 0x00000030UL /**< Mode CAPSENSE for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VDACOUT0 0x00000040UL /**< Mode VDACOUT0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VDACOUT1 0x00000041UL /**< Mode VDACOUT1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_DEFAULT (_ACMP_INPUTCTRL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VSS (_ACMP_INPUTCTRL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD << 8) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP << 8) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 << 8) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP << 8) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 << 8) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP << 8) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 << 8) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP << 8) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 << 8) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP << 8) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_CAPSENSE (_ACMP_INPUTCTRL_NEGSEL_CAPSENSE << 8) /**< Shifted mode CAPSENSE for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VDACOUT0 (_ACMP_INPUTCTRL_NEGSEL_VDACOUT0 << 8) /**< Shifted mode VDACOUT0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VDACOUT1 (_ACMP_INPUTCTRL_NEGSEL_VDACOUT1 << 8) /**< Shifted mode VDACOUT1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA0 (_ACMP_INPUTCTRL_NEGSEL_PA0 << 8) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA1 (_ACMP_INPUTCTRL_NEGSEL_PA1 << 8) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA2 (_ACMP_INPUTCTRL_NEGSEL_PA2 << 8) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA3 (_ACMP_INPUTCTRL_NEGSEL_PA3 << 8) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA4 (_ACMP_INPUTCTRL_NEGSEL_PA4 << 8) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA5 (_ACMP_INPUTCTRL_NEGSEL_PA5 << 8) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA6 (_ACMP_INPUTCTRL_NEGSEL_PA6 << 8) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA7 (_ACMP_INPUTCTRL_NEGSEL_PA7 << 8) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA8 (_ACMP_INPUTCTRL_NEGSEL_PA8 << 8) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA9 (_ACMP_INPUTCTRL_NEGSEL_PA9 << 8) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA10 (_ACMP_INPUTCTRL_NEGSEL_PA10 << 8) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA11 (_ACMP_INPUTCTRL_NEGSEL_PA11 << 8) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA12 (_ACMP_INPUTCTRL_NEGSEL_PA12 << 8) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA13 (_ACMP_INPUTCTRL_NEGSEL_PA13 << 8) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA14 (_ACMP_INPUTCTRL_NEGSEL_PA14 << 8) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA15 (_ACMP_INPUTCTRL_NEGSEL_PA15 << 8) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB0 (_ACMP_INPUTCTRL_NEGSEL_PB0 << 8) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB1 (_ACMP_INPUTCTRL_NEGSEL_PB1 << 8) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB2 (_ACMP_INPUTCTRL_NEGSEL_PB2 << 8) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB3 (_ACMP_INPUTCTRL_NEGSEL_PB3 << 8) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB4 (_ACMP_INPUTCTRL_NEGSEL_PB4 << 8) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB5 (_ACMP_INPUTCTRL_NEGSEL_PB5 << 8) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB6 (_ACMP_INPUTCTRL_NEGSEL_PB6 << 8) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB7 (_ACMP_INPUTCTRL_NEGSEL_PB7 << 8) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB8 (_ACMP_INPUTCTRL_NEGSEL_PB8 << 8) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB9 (_ACMP_INPUTCTRL_NEGSEL_PB9 << 8) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB10 (_ACMP_INPUTCTRL_NEGSEL_PB10 << 8) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB11 (_ACMP_INPUTCTRL_NEGSEL_PB11 << 8) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB12 (_ACMP_INPUTCTRL_NEGSEL_PB12 << 8) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB13 (_ACMP_INPUTCTRL_NEGSEL_PB13 << 8) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB14 (_ACMP_INPUTCTRL_NEGSEL_PB14 << 8) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB15 (_ACMP_INPUTCTRL_NEGSEL_PB15 << 8) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC0 (_ACMP_INPUTCTRL_NEGSEL_PC0 << 8) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC1 (_ACMP_INPUTCTRL_NEGSEL_PC1 << 8) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC2 (_ACMP_INPUTCTRL_NEGSEL_PC2 << 8) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC3 (_ACMP_INPUTCTRL_NEGSEL_PC3 << 8) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC4 (_ACMP_INPUTCTRL_NEGSEL_PC4 << 8) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC5 (_ACMP_INPUTCTRL_NEGSEL_PC5 << 8) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC6 (_ACMP_INPUTCTRL_NEGSEL_PC6 << 8) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC7 (_ACMP_INPUTCTRL_NEGSEL_PC7 << 8) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC8 (_ACMP_INPUTCTRL_NEGSEL_PC8 << 8) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC9 (_ACMP_INPUTCTRL_NEGSEL_PC9 << 8) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC10 (_ACMP_INPUTCTRL_NEGSEL_PC10 << 8) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC11 (_ACMP_INPUTCTRL_NEGSEL_PC11 << 8) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC12 (_ACMP_INPUTCTRL_NEGSEL_PC12 << 8) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC13 (_ACMP_INPUTCTRL_NEGSEL_PC13 << 8) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC14 (_ACMP_INPUTCTRL_NEGSEL_PC14 << 8) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC15 (_ACMP_INPUTCTRL_NEGSEL_PC15 << 8) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD0 (_ACMP_INPUTCTRL_NEGSEL_PD0 << 8) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD1 (_ACMP_INPUTCTRL_NEGSEL_PD1 << 8) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD2 (_ACMP_INPUTCTRL_NEGSEL_PD2 << 8) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD3 (_ACMP_INPUTCTRL_NEGSEL_PD3 << 8) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD4 (_ACMP_INPUTCTRL_NEGSEL_PD4 << 8) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD5 (_ACMP_INPUTCTRL_NEGSEL_PD5 << 8) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD6 (_ACMP_INPUTCTRL_NEGSEL_PD6 << 8) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD7 (_ACMP_INPUTCTRL_NEGSEL_PD7 << 8) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD8 (_ACMP_INPUTCTRL_NEGSEL_PD8 << 8) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD9 (_ACMP_INPUTCTRL_NEGSEL_PD9 << 8) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD10 (_ACMP_INPUTCTRL_NEGSEL_PD10 << 8) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD11 (_ACMP_INPUTCTRL_NEGSEL_PD11 << 8) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD12 (_ACMP_INPUTCTRL_NEGSEL_PD12 << 8) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD13 (_ACMP_INPUTCTRL_NEGSEL_PD13 << 8) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD14 (_ACMP_INPUTCTRL_NEGSEL_PD14 << 8) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD15 (_ACMP_INPUTCTRL_NEGSEL_PD15 << 8) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_VREFDIV_SHIFT 16 /**< Shift value for ACMP_VREFDIV */ +#define _ACMP_INPUTCTRL_VREFDIV_MASK 0x3F0000UL /**< Bit mask for ACMP_VREFDIV */ +#define _ACMP_INPUTCTRL_VREFDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_VREFDIV_DEFAULT (_ACMP_INPUTCTRL_VREFDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ +#define _ACMP_INPUTCTRL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */ +#define _ACMP_INPUTCTRL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_DEFAULT (_ACMP_INPUTCTRL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES0 (_ACMP_INPUTCTRL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES1 (_ACMP_INPUTCTRL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES2 (_ACMP_INPUTCTRL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES3 (_ACMP_INPUTCTRL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES4 (_ACMP_INPUTCTRL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES5 (_ACMP_INPUTCTRL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES6 (_ACMP_INPUTCTRL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTCTRL */ /* Bit fields for ACMP STATUS */ -#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ -#define _ACMP_STATUS_MASK 0x0000001DUL /**< Mask for ACMP_STATUS */ -#define ACMP_STATUS_ACMPOUT (0x1UL << 0) /**< Analog Comparator Output */ -#define _ACMP_STATUS_ACMPOUT_SHIFT 0 /**< Shift value for ACMP_ACMPOUT */ -#define _ACMP_STATUS_ACMPOUT_MASK 0x1UL /**< Bit mask for ACMP_ACMPOUT */ -#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_ACMPRDY (0x1UL << 2) /**< Analog Comparator Ready */ -#define _ACMP_STATUS_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ -#define _ACMP_STATUS_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ -#define _ACMP_STATUS_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_ACMPRDY_DEFAULT (_ACMP_STATUS_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_INPUTCONFLICT (0x1UL << 3) /**< INPUT conflict */ -#define _ACMP_STATUS_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ -#define _ACMP_STATUS_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ -#define _ACMP_STATUS_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_INPUTCONFLICT_DEFAULT (_ACMP_STATUS_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ -#define _ACMP_STATUS_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ -#define _ACMP_STATUS_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ -#define _ACMP_STATUS_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_PORTALLOCERR_DEFAULT (_ACMP_STATUS_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ +#define _ACMP_STATUS_MASK 0x0000001DUL /**< Mask for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT (0x1UL << 0) /**< Analog Comparator Output */ +#define _ACMP_STATUS_ACMPOUT_SHIFT 0 /**< Shift value for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_MASK 0x1UL /**< Bit mask for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPRDY (0x1UL << 2) /**< Analog Comparator Ready */ +#define _ACMP_STATUS_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_STATUS_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_STATUS_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPRDY_DEFAULT (_ACMP_STATUS_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_INPUTCONFLICT (0x1UL << 3) /**< INPUT conflict */ +#define _ACMP_STATUS_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_STATUS_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_STATUS_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_INPUTCONFLICT_DEFAULT (_ACMP_STATUS_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ +#define _ACMP_STATUS_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_STATUS_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_STATUS_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_PORTALLOCERR_DEFAULT (_ACMP_STATUS_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_STATUS */ /* Bit fields for ACMP IF */ -#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ -#define _ACMP_IF_MASK 0x0000001FUL /**< Mask for ACMP_IF */ -#define ACMP_IF_RISE (0x1UL << 0) /**< Rising Edge Triggered Interrupt Flag */ -#define _ACMP_IF_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ -#define _ACMP_IF_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ -#define _ACMP_IF_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ -#define ACMP_IF_RISE_DEFAULT (_ACMP_IF_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ -#define ACMP_IF_FALL (0x1UL << 1) /**< Falling Edge Triggered Interrupt Flag */ -#define _ACMP_IF_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ -#define _ACMP_IF_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ -#define _ACMP_IF_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ -#define ACMP_IF_FALL_DEFAULT (_ACMP_IF_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ -#define ACMP_IF_ACMPRDY (0x1UL << 2) /**< ACMP ready Interrupt flag */ -#define _ACMP_IF_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ -#define _ACMP_IF_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ -#define _ACMP_IF_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ -#define ACMP_IF_ACMPRDY_DEFAULT (_ACMP_IF_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */ -#define ACMP_IF_INPUTCONFLICT (0x1UL << 3) /**< Input conflict */ -#define _ACMP_IF_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ -#define _ACMP_IF_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ -#define _ACMP_IF_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ -#define ACMP_IF_INPUTCONFLICT_DEFAULT (_ACMP_IF_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IF */ -#define ACMP_IF_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ -#define _ACMP_IF_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ -#define _ACMP_IF_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ -#define _ACMP_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ -#define ACMP_IF_PORTALLOCERR_DEFAULT (_ACMP_IF_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IF */ +#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ +#define _ACMP_IF_MASK 0x0000001FUL /**< Mask for ACMP_IF */ +#define ACMP_IF_RISE (0x1UL << 0) /**< Rising Edge Triggered Interrupt Flag */ +#define _ACMP_IF_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ +#define _ACMP_IF_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ +#define _ACMP_IF_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_RISE_DEFAULT (_ACMP_IF_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_FALL (0x1UL << 1) /**< Falling Edge Triggered Interrupt Flag */ +#define _ACMP_IF_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ +#define _ACMP_IF_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ +#define _ACMP_IF_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_FALL_DEFAULT (_ACMP_IF_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_ACMPRDY (0x1UL << 2) /**< ACMP ready Interrupt flag */ +#define _ACMP_IF_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_IF_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_IF_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_ACMPRDY_DEFAULT (_ACMP_IF_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_INPUTCONFLICT (0x1UL << 3) /**< Input conflict */ +#define _ACMP_IF_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_IF_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_IF_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_INPUTCONFLICT_DEFAULT (_ACMP_IF_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ +#define _ACMP_IF_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_IF_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_PORTALLOCERR_DEFAULT (_ACMP_IF_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IF */ /* Bit fields for ACMP IEN */ -#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ -#define _ACMP_IEN_MASK 0x0000001FUL /**< Mask for ACMP_IEN */ -#define ACMP_IEN_RISE (0x1UL << 0) /**< Rising edge interrupt enable */ -#define _ACMP_IEN_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ -#define _ACMP_IEN_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ -#define _ACMP_IEN_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_RISE_DEFAULT (_ACMP_IEN_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_FALL (0x1UL << 1) /**< Falling edge interrupt enable */ -#define _ACMP_IEN_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ -#define _ACMP_IEN_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ -#define _ACMP_IEN_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_FALL_DEFAULT (_ACMP_IEN_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_ACMPRDY (0x1UL << 2) /**< ACMP ready interrupt enable */ -#define _ACMP_IEN_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ -#define _ACMP_IEN_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ -#define _ACMP_IEN_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_ACMPRDY_DEFAULT (_ACMP_IEN_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_INPUTCONFLICT (0x1UL << 3) /**< Input conflict interrupt enable */ -#define _ACMP_IEN_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ -#define _ACMP_IEN_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ -#define _ACMP_IEN_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_INPUTCONFLICT_DEFAULT (_ACMP_IEN_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_PORTALLOCERR (0x1UL << 4) /**< Port allocation error interrupt enable */ -#define _ACMP_IEN_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ -#define _ACMP_IEN_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ -#define _ACMP_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_PORTALLOCERR_DEFAULT (_ACMP_IEN_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ +#define _ACMP_IEN_MASK 0x0000001FUL /**< Mask for ACMP_IEN */ +#define ACMP_IEN_RISE (0x1UL << 0) /**< Rising edge interrupt enable */ +#define _ACMP_IEN_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ +#define _ACMP_IEN_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ +#define _ACMP_IEN_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_RISE_DEFAULT (_ACMP_IEN_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_FALL (0x1UL << 1) /**< Falling edge interrupt enable */ +#define _ACMP_IEN_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ +#define _ACMP_IEN_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ +#define _ACMP_IEN_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_FALL_DEFAULT (_ACMP_IEN_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_ACMPRDY (0x1UL << 2) /**< ACMP ready interrupt enable */ +#define _ACMP_IEN_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_IEN_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_IEN_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_ACMPRDY_DEFAULT (_ACMP_IEN_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_INPUTCONFLICT (0x1UL << 3) /**< Input conflict interrupt enable */ +#define _ACMP_IEN_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_IEN_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_IEN_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_INPUTCONFLICT_DEFAULT (_ACMP_IEN_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_PORTALLOCERR (0x1UL << 4) /**< Port allocation error interrupt enable */ +#define _ACMP_IEN_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_IEN_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_PORTALLOCERR_DEFAULT (_ACMP_IEN_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IEN */ /* Bit fields for ACMP SYNCBUSY */ -#define _ACMP_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for ACMP_SYNCBUSY */ -#define _ACMP_SYNCBUSY_MASK 0x00000001UL /**< Mask for ACMP_SYNCBUSY */ -#define ACMP_SYNCBUSY_INPUTCTRL (0x1UL << 0) /**< Syncbusy for INPUTCTRL */ -#define _ACMP_SYNCBUSY_INPUTCTRL_SHIFT 0 /**< Shift value for ACMP_INPUTCTRL */ -#define _ACMP_SYNCBUSY_INPUTCTRL_MASK 0x1UL /**< Bit mask for ACMP_INPUTCTRL */ -#define _ACMP_SYNCBUSY_INPUTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SYNCBUSY */ -#define ACMP_SYNCBUSY_INPUTCTRL_DEFAULT (_ACMP_SYNCBUSY_INPUTCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SYNCBUSY */ +#define _ACMP_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for ACMP_SYNCBUSY */ +#define _ACMP_SYNCBUSY_MASK 0x00000001UL /**< Mask for ACMP_SYNCBUSY */ +#define ACMP_SYNCBUSY_INPUTCTRL (0x1UL << 0) /**< Syncbusy for INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_SHIFT 0 /**< Shift value for ACMP_INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_MASK 0x1UL /**< Bit mask for ACMP_INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SYNCBUSY */ +#define ACMP_SYNCBUSY_INPUTCTRL_DEFAULT (_ACMP_SYNCBUSY_INPUTCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SYNCBUSY */ /** @} End of group EFR32SG28_ACMP_BitFields */ /** @} End of group EFR32SG28_ACMP */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_aes.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_aes.h index 1ad5e111fa..77a5040241 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_aes.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_aes.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -41,30 +41,29 @@ *****************************************************************************/ /** AES Register Declaration. */ -typedef struct -{ - __IOM uint32_t FETCHADDR; /**< Fetcher Address */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t FETCHLEN; /**< Fetcher Length */ - __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ - __IOM uint32_t PUSHADDR; /**< Pusher Address */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t PUSHLEN; /**< Pusher Length */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IM uint32_t IF; /**< Interrupt Flags */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt status clear */ - __IOM uint32_t CTRL; /**< Control register */ - __IOM uint32_t CMD; /**< Command register */ - __IM uint32_t STATUS; /**< Status register */ - uint32_t RESERVED4[240U]; /**< Reserved for future use */ - __IM uint32_t INCL_IPS_HW_CFG; /**< INCL_IPS_HW_CFG */ - __IM uint32_t BA411E_HW_CFG_1; /**< BA411E_HW_CFG_1 */ - __IM uint32_t BA411E_HW_CFG_2; /**< BA411E_HW_CFG_2 */ - __IM uint32_t BA413_HW_CFG; /**< BA413_HW_CFG */ - __IM uint32_t BA418_HW_CFG; /**< BA418_HW_CFG */ - __IM uint32_t BA419_HW_CFG; /**< BA419_HW_CFG */ +typedef struct { + __IOM uint32_t FETCHADDR; /**< Fetcher Address */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t FETCHLEN; /**< Fetcher Length */ + __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ + __IOM uint32_t PUSHADDR; /**< Pusher Address */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t PUSHLEN; /**< Pusher Length */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IM uint32_t IF; /**< Interrupt Flags */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt status clear */ + __IOM uint32_t CTRL; /**< Control register */ + __IOM uint32_t CMD; /**< Command register */ + __IM uint32_t STATUS; /**< Status register */ + uint32_t RESERVED4[240U]; /**< Reserved for future use */ + __IM uint32_t INCL_IPS_HW_CFG; /**< INCL_IPS_HW_CFG */ + __IM uint32_t BA411E_HW_CFG_1; /**< BA411E_HW_CFG_1 */ + __IM uint32_t BA411E_HW_CFG_2; /**< BA411E_HW_CFG_2 */ + __IM uint32_t BA413_HW_CFG; /**< BA413_HW_CFG */ + __IM uint32_t BA418_HW_CFG; /**< BA418_HW_CFG */ + __IM uint32_t BA419_HW_CFG; /**< BA419_HW_CFG */ } AES_TypeDef; /** @} End of group EFR32SG28_AES */ @@ -76,376 +75,376 @@ typedef struct *****************************************************************************/ /* Bit fields for AES FETCHADDR */ -#define _AES_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHADDR */ -#define _AES_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHADDR */ -#define _AES_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ -#define _AES_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ -#define _AES_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHADDR */ -#define AES_FETCHADDR_ADDR_DEFAULT (_AES_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHADDR */ +#define _AES_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHADDR */ +#define _AES_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHADDR */ +#define _AES_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHADDR */ +#define AES_FETCHADDR_ADDR_DEFAULT (_AES_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHADDR */ /* Bit fields for AES FETCHLEN */ -#define _AES_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHLEN */ -#define _AES_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for AES_FETCHLEN */ -#define _AES_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ -#define _AES_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ -#define _AES_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_LENGTH_DEFAULT (_AES_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ -#define _AES_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ -#define _AES_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ -#define _AES_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_CONSTADDR_DEFAULT (_AES_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign lengh */ -#define _AES_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ -#define _AES_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ -#define _AES_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_REALIGN_DEFAULT (_AES_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define _AES_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHLEN */ +#define _AES_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for AES_FETCHLEN */ +#define _AES_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_LENGTH_DEFAULT (_AES_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR_DEFAULT (_AES_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign lengh */ +#define _AES_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN_DEFAULT (_AES_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_FETCHLEN */ /* Bit fields for AES FETCHTAG */ -#define _AES_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHTAG */ -#define _AES_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHTAG */ -#define _AES_FETCHTAG_TAG_SHIFT 0 /**< Shift value for AES_TAG */ -#define _AES_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for AES_TAG */ -#define _AES_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHTAG */ -#define AES_FETCHTAG_TAG_DEFAULT (_AES_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHTAG */ +#define _AES_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHTAG */ +#define _AES_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHTAG */ +#define _AES_FETCHTAG_TAG_SHIFT 0 /**< Shift value for AES_TAG */ +#define _AES_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for AES_TAG */ +#define _AES_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHTAG */ +#define AES_FETCHTAG_TAG_DEFAULT (_AES_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHTAG */ /* Bit fields for AES PUSHADDR */ -#define _AES_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHADDR */ -#define _AES_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHADDR */ -#define _AES_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ -#define _AES_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ -#define _AES_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHADDR */ -#define AES_PUSHADDR_ADDR_DEFAULT (_AES_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHADDR */ +#define _AES_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHADDR */ +#define _AES_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHADDR */ +#define _AES_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHADDR */ +#define AES_PUSHADDR_ADDR_DEFAULT (_AES_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHADDR */ /* Bit fields for AES PUSHLEN */ -#define _AES_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHLEN */ -#define _AES_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for AES_PUSHLEN */ -#define _AES_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ -#define _AES_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ -#define _AES_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_LENGTH_DEFAULT (_AES_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ -#define _AES_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ -#define _AES_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ -#define _AES_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_CONSTADDR_DEFAULT (_AES_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ -#define _AES_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ -#define _AES_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ -#define _AES_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_REALIGN_DEFAULT (_AES_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ -#define _AES_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for AES_DISCARD */ -#define _AES_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for AES_DISCARD */ -#define _AES_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_DISCARD_DEFAULT (_AES_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define _AES_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHLEN */ +#define _AES_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for AES_PUSHLEN */ +#define _AES_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_LENGTH_DEFAULT (_AES_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR_DEFAULT (_AES_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ +#define _AES_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN_DEFAULT (_AES_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ +#define _AES_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD_DEFAULT (_AES_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for AES_PUSHLEN */ /* Bit fields for AES IEN */ -#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ -#define _AES_IEN_MASK 0x0000003FUL /**< Mask for AES_IEN */ -#define AES_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ -#define _AES_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ -#define _AES_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ -#define _AES_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERENDOFBLOCK_DEFAULT (_AES_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ -#define _AES_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ -#define _AES_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ -#define _AES_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERSTOPPED_DEFAULT (_AES_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ -#define _AES_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ -#define _AES_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ -#define _AES_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERERROR_DEFAULT (_AES_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ -#define _AES_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ -#define _AES_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ -#define _AES_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERENDOFBLOCK_DEFAULT (_AES_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ -#define _AES_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ -#define _AES_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ -#define _AES_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERSTOPPED_DEFAULT (_AES_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ -#define _AES_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ -#define _AES_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ -#define _AES_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERERROR_DEFAULT (_AES_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IEN */ +#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ +#define _AES_IEN_MASK 0x0000003FUL /**< Mask for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ +#define _AES_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK_DEFAULT (_AES_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ +#define _AES_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED_DEFAULT (_AES_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ +#define _AES_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR_DEFAULT (_AES_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ +#define _AES_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK_DEFAULT (_AES_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ +#define _AES_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED_DEFAULT (_AES_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ +#define _AES_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR_DEFAULT (_AES_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IEN */ /* Bit fields for AES IF */ -#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ -#define _AES_IF_MASK 0x0000003FUL /**< Mask for AES_IF */ -#define AES_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ -#define _AES_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ -#define _AES_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ -#define _AES_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ -#define _AES_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ -#define _AES_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ -#define _AES_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERSTOPPED_DEFAULT (_AES_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ -#define _AES_IF_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ -#define _AES_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ -#define _AES_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERERROR_DEFAULT (_AES_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ -#define _AES_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ -#define _AES_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ -#define _AES_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ -#define _AES_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ -#define _AES_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ -#define _AES_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERSTOPPED_DEFAULT (_AES_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ -#define _AES_IF_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ -#define _AES_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ -#define _AES_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERERROR_DEFAULT (_AES_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF */ +#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ +#define _AES_IF_MASK 0x0000003FUL /**< Mask for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ +#define _AES_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ +#define _AES_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED_DEFAULT (_AES_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ +#define _AES_IF_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR_DEFAULT (_AES_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ +#define _AES_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ +#define _AES_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED_DEFAULT (_AES_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ +#define _AES_IF_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR_DEFAULT (_AES_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF */ /* Bit fields for AES IF_CLR */ -#define _AES_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for AES_IF_CLR */ -#define _AES_IF_CLR_MASK 0x0000003FUL /**< Mask for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ -#define _AES_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ -#define _AES_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ -#define _AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ -#define _AES_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ -#define _AES_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ -#define _AES_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERSTOPPED_DEFAULT (_AES_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ -#define _AES_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ -#define _AES_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ -#define _AES_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERERROR_DEFAULT (_AES_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< FETCHERENDOFBLOCKIFC */ -#define _AES_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ -#define _AES_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ -#define _AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< FETCHERSTOPPEDIFC */ -#define _AES_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ -#define _AES_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ -#define _AES_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERSTOPPED_DEFAULT (_AES_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERERROR (0x1UL << 5) /**< FETCHERERRORIFC */ -#define _AES_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ -#define _AES_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ -#define _AES_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERERROR_DEFAULT (_AES_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define _AES_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for AES_IF_CLR */ +#define _AES_IF_CLR_MASK 0x0000003FUL /**< Mask for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ +#define _AES_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED_DEFAULT (_AES_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ +#define _AES_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR_DEFAULT (_AES_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< FETCHERENDOFBLOCKIFC */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< FETCHERSTOPPEDIFC */ +#define _AES_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED_DEFAULT (_AES_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR (0x1UL << 5) /**< FETCHERERRORIFC */ +#define _AES_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR_DEFAULT (_AES_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF_CLR */ /* Bit fields for AES CTRL */ -#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ -#define _AES_CTRL_MASK 0x0000001FUL /**< Mask for AES_CTRL */ -#define AES_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ -#define _AES_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for AES_FETCHERSCATTERGATHER */ -#define _AES_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for AES_FETCHERSCATTERGATHER */ -#define _AES_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_FETCHERSCATTERGATHER_DEFAULT (_AES_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */ -#define AES_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ -#define _AES_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for AES_PUSHERSCATTERGATHER */ -#define _AES_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for AES_PUSHERSCATTERGATHER */ -#define _AES_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_PUSHERSCATTERGATHER_DEFAULT (_AES_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */ -#define AES_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ -#define _AES_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for AES_STOPFETCHER */ -#define _AES_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for AES_STOPFETCHER */ -#define _AES_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_STOPFETCHER_DEFAULT (_AES_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */ -#define AES_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ -#define _AES_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for AES_STOPPUSHER */ -#define _AES_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for AES_STOPPUSHER */ -#define _AES_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_STOPPUSHER_DEFAULT (_AES_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_CTRL */ -#define AES_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ -#define _AES_CTRL_SWRESET_SHIFT 4 /**< Shift value for AES_SWRESET */ -#define _AES_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for AES_SWRESET */ -#define _AES_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_SWRESET_DEFAULT (_AES_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */ +#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ +#define _AES_CTRL_MASK 0x0000001FUL /**< Mask for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ +#define _AES_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER_DEFAULT (_AES_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ +#define _AES_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER_DEFAULT (_AES_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ +#define _AES_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER_DEFAULT (_AES_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ +#define _AES_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER_DEFAULT (_AES_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ +#define _AES_CTRL_SWRESET_SHIFT 4 /**< Shift value for AES_SWRESET */ +#define _AES_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for AES_SWRESET */ +#define _AES_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET_DEFAULT (_AES_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */ /* Bit fields for AES CMD */ -#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ -#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ -#define AES_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ -#define _AES_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for AES_STARTFETCHER */ -#define _AES_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for AES_STARTFETCHER */ -#define _AES_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ -#define AES_CMD_STARTFETCHER_DEFAULT (_AES_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */ -#define AES_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ -#define _AES_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for AES_STARTPUSHER */ -#define _AES_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for AES_STARTPUSHER */ -#define _AES_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ -#define AES_CMD_STARTPUSHER_DEFAULT (_AES_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */ +#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ +#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ +#define AES_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ +#define _AES_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTFETCHER_DEFAULT (_AES_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ +#define _AES_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER_DEFAULT (_AES_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */ /* Bit fields for AES STATUS */ -#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ -#define _AES_STATUS_MASK 0xFFFF0073UL /**< Mask for AES_STATUS */ -#define AES_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ -#define _AES_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for AES_FETCHERBSY */ -#define _AES_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for AES_FETCHERBSY */ -#define _AES_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_FETCHERBSY_DEFAULT (_AES_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */ -#define AES_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ -#define _AES_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for AES_PUSHERBSY */ -#define _AES_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for AES_PUSHERBSY */ -#define _AES_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_PUSHERBSY_DEFAULT (_AES_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_STATUS */ -#define AES_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ -#define _AES_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for AES_NOTEMPTY */ -#define _AES_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for AES_NOTEMPTY */ -#define _AES_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_NOTEMPTY_DEFAULT (_AES_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_STATUS */ -#define AES_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ -#define _AES_STATUS_WAITING_SHIFT 5 /**< Shift value for AES_WAITING */ -#define _AES_STATUS_WAITING_MASK 0x20UL /**< Bit mask for AES_WAITING */ -#define _AES_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_WAITING_DEFAULT (_AES_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_STATUS */ -#define AES_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ -#define _AES_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for AES_SOFTRSTBSY */ -#define _AES_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for AES_SOFTRSTBSY */ -#define _AES_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_SOFTRSTBSY_DEFAULT (_AES_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_STATUS */ -#define _AES_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for AES_FIFODATANUM */ -#define _AES_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for AES_FIFODATANUM */ -#define _AES_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_FIFODATANUM_DEFAULT (_AES_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_STATUS */ +#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ +#define _AES_STATUS_MASK 0xFFFF0073UL /**< Mask for AES_STATUS */ +#define AES_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ +#define _AES_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FETCHERBSY_DEFAULT (_AES_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ +#define _AES_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY_DEFAULT (_AES_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ +#define _AES_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY_DEFAULT (_AES_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ +#define _AES_STATUS_WAITING_SHIFT 5 /**< Shift value for AES_WAITING */ +#define _AES_STATUS_WAITING_MASK 0x20UL /**< Bit mask for AES_WAITING */ +#define _AES_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING_DEFAULT (_AES_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ +#define _AES_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY_DEFAULT (_AES_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_STATUS */ +#define _AES_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FIFODATANUM_DEFAULT (_AES_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_STATUS */ /* Bit fields for AES INCL_IPS_HW_CFG */ -#define _AES_INCL_IPS_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_INCL_IPS_HW_CFG */ -#define _AES_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for AES_g_IncludeAES */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for AES_g_IncludeAES */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for AES_g_IncludeAESGCM */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for AES_g_IncludeAESGCM */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for AES_g_IncludeAESXTS */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for AES_g_IncludeAESXTS */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for AES_g_IncludeDES */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for AES_g_IncludeDES */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for AES_g_IncludeHASH */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for AES_g_IncludeHASH */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for AES_g_IncludeChachaPoly */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for AES_g_IncludeChachaPoly */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for AES_g_IncludeSHA3 */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for AES_g_IncludeSHA3 */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for AES_g_IncludeZUC */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for AES_g_IncludeZUC */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for AES_g_IncludeSM4 */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for AES_g_IncludeSM4 */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for AES_g_IncludePKE */ -#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for AES_g_IncludePKE */ -#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for AES_g_IncludeNDRNG */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for AES_g_IncludeNDRNG */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define _AES_INCL_IPS_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_INCL_IPS_HW_CFG */ +#define _AES_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ /* Bit fields for AES BA411E_HW_CFG_1 */ -#define _AES_BA411E_HW_CFG_1_RESETVALUE 0x05010127UL /**< Default value for AES_BA411E_HW_CFG_1 */ -#define _AES_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for AES_BA411E_HW_CFG_1 */ -#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for AES_g_AesModesPoss */ -#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for AES_g_AesModesPoss */ -#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x00000127UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ -#define AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ -#define AES_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */ -#define _AES_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for AES_g_CS */ -#define _AES_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for AES_g_CS */ -#define _AES_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ -#define AES_BA411E_HW_CFG_1_g_CS_DEFAULT (_AES_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ -#define AES_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */ -#define _AES_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for AES_g_UseMasking */ -#define _AES_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for AES_g_UseMasking */ -#define _AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ -#define AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ -#define _AES_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for AES_g_Keysize */ -#define _AES_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for AES_g_Keysize */ -#define _AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000005UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ -#define AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define _AES_BA411E_HW_CFG_1_RESETVALUE 0x05010127UL /**< Default value for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x00000127UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */ +#define _AES_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_CS_DEFAULT (_AES_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define _AES_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000005UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ /* Bit fields for AES BA411E_HW_CFG_2 */ -#define _AES_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for AES_BA411E_HW_CFG_2 */ -#define _AES_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for AES_BA411E_HW_CFG_2 */ -#define _AES_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for AES_g_CtrSize */ -#define _AES_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for AES_g_CtrSize */ -#define _AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_2 */ -#define AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_2*/ +#define _AES_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_2 */ +#define AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_2*/ /* Bit fields for AES BA413_HW_CFG */ -#define _AES_BA413_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA413_HW_CFG */ -#define _AES_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for AES_BA413_HW_CFG */ -#define _AES_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for AES_g_HashMaskFunc */ -#define _AES_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for AES_g_HashMaskFunc */ -#define _AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */ -#define _AES_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for AES_g_HashPadding */ -#define _AES_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for AES_g_HashPadding */ -#define _AES_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashPadding_DEFAULT (_AES_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */ -#define _AES_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for AES_g_HMAC_enabled */ -#define _AES_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for AES_g_HMAC_enabled */ -#define _AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */ -#define _AES_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for AES_g_HashVerifyDigest */ -#define _AES_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for AES_g_HashVerifyDigest */ -#define _AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */ +#define _AES_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding_DEFAULT (_AES_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ /* Bit fields for AES BA418_HW_CFG */ -#define _AES_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_BA418_HW_CFG */ -#define _AES_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for AES_BA418_HW_CFG */ -#define AES_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */ -#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for AES_g_Sha3CtxtEn */ -#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for AES_g_Sha3CtxtEn */ -#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA418_HW_CFG */ -#define AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA418_HW_CFG */ /* Bit fields for AES BA419_HW_CFG */ -#define _AES_BA419_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA419_HW_CFG */ -#define _AES_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for AES_BA419_HW_CFG */ -#define _AES_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for AES_g_SM4ModesPoss */ -#define _AES_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for AES_g_SM4ModesPoss */ -#define _AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA419_HW_CFG */ -#define AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA419_HW_CFG */ +#define AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA419_HW_CFG */ /** @} End of group EFR32SG28_AES_BitFields */ /** @} End of group EFR32SG28_AES */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_buram.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_buram.h index 82528fdd28..05499c16fa 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_buram.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_buram.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_BURAM_H #define EFR32SG28_BURAM_H - #define BURAM_HAS_SET_CLEAR /**************************************************************************//** @@ -43,22 +42,19 @@ *****************************************************************************/ /** BURAM RET Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t REG; /**< Retention Register */ +typedef struct { + __IOM uint32_t REG; /**< Retention Register */ } BURAM_RET_TypeDef; - /** BURAM Register Declaration. */ -typedef struct -{ - BURAM_RET_TypeDef RET[32U]; /**< RetentionReg */ - uint32_t RESERVED0[992U]; /**< Reserved for future use */ - BURAM_RET_TypeDef RET_SET[32U]; /**< RetentionReg */ - uint32_t RESERVED1[992U]; /**< Reserved for future use */ - BURAM_RET_TypeDef RET_CLR[32U]; /**< RetentionReg */ - uint32_t RESERVED2[992U]; /**< Reserved for future use */ - BURAM_RET_TypeDef RET_TGL[32U]; /**< RetentionReg */ +typedef struct { + BURAM_RET_TypeDef RET[32U]; /**< RetentionReg */ + uint32_t RESERVED0[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_SET[32U]; /**< RetentionReg */ + uint32_t RESERVED1[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_CLR[32U]; /**< RetentionReg */ + uint32_t RESERVED2[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_TGL[32U]; /**< RetentionReg */ } BURAM_TypeDef; /** @} End of group EFR32SG28_BURAM */ @@ -70,12 +66,12 @@ typedef struct *****************************************************************************/ /* Bit fields for BURAM RET_REG */ -#define _BURAM_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURAM_RET_REG */ -#define _BURAM_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURAM_RET_REG */ -#define _BURAM_RET_REG_RETREG_SHIFT 0 /**< Shift value for BURAM_RETREG */ -#define _BURAM_RET_REG_RETREG_MASK 0xFFFFFFFFUL /**< Bit mask for BURAM_RETREG */ -#define _BURAM_RET_REG_RETREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURAM_RET_REG */ -#define BURAM_RET_REG_RETREG_DEFAULT (_BURAM_RET_REG_RETREG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURAM_RET_REG */ +#define _BURAM_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURAM_RET_REG */ +#define _BURAM_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURAM_RET_REG */ +#define _BURAM_RET_REG_RETREG_SHIFT 0 /**< Shift value for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_MASK 0xFFFFFFFFUL /**< Bit mask for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURAM_RET_REG */ +#define BURAM_RET_REG_RETREG_DEFAULT (_BURAM_RET_REG_RETREG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURAM_RET_REG */ /** @} End of group EFR32SG28_BURAM_BitFields */ /** @} End of group EFR32SG28_BURAM */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_burtc.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_burtc.h index 57c724e141..dd0642f3d4 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_burtc.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_burtc.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_BURTC_H #define EFR32SG28_BURTC_H - #define BURTC_HAS_SET_CLEAR /**************************************************************************//** @@ -43,63 +42,62 @@ *****************************************************************************/ /** BURTC Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t EN; /**< Module Enable Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT; /**< Counter Value Register */ - __IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - __IOM uint32_t COMP; /**< Compare Value Register */ - uint32_t RESERVED0[1011U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t EN_SET; /**< Module Enable Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT_SET; /**< Counter Value Register */ - __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - __IOM uint32_t COMP_SET; /**< Compare Value Register */ - uint32_t RESERVED1[1011U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t EN_CLR; /**< Module Enable Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT_CLR; /**< Counter Value Register */ - __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - __IOM uint32_t COMP_CLR; /**< Compare Value Register */ - uint32_t RESERVED2[1011U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t EN_TGL; /**< Module Enable Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT_TGL; /**< Counter Value Register */ - __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - __IOM uint32_t COMP_TGL; /**< Compare Value Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t COMP; /**< Compare Value Register */ + uint32_t RESERVED0[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t COMP_SET; /**< Compare Value Register */ + uint32_t RESERVED1[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t COMP_CLR; /**< Compare Value Register */ + uint32_t RESERVED2[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t COMP_TGL; /**< Compare Value Register */ } BURTC_TypeDef; /** @} End of group EFR32SG28_BURTC */ @@ -111,221 +109,221 @@ typedef struct *****************************************************************************/ /* Bit fields for BURTC IPVERSION */ -#define _BURTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for BURTC_IPVERSION */ -#define _BURTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BURTC_IPVERSION */ -#define _BURTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BURTC_IPVERSION */ -#define _BURTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_IPVERSION */ -#define _BURTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for BURTC_IPVERSION */ -#define BURTC_IPVERSION_IPVERSION_DEFAULT (_BURTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for BURTC_IPVERSION */ +#define BURTC_IPVERSION_IPVERSION_DEFAULT (_BURTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IPVERSION */ /* Bit fields for BURTC EN */ -#define _BURTC_EN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EN */ -#define _BURTC_EN_MASK 0x00000003UL /**< Mask for BURTC_EN */ -#define BURTC_EN_EN (0x1UL << 0) /**< BURTC Enable */ -#define _BURTC_EN_EN_SHIFT 0 /**< Shift value for BURTC_EN */ -#define _BURTC_EN_EN_MASK 0x1UL /**< Bit mask for BURTC_EN */ -#define _BURTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ -#define BURTC_EN_EN_DEFAULT (_BURTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EN */ -#define BURTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _BURTC_EN_DISABLING_SHIFT 1 /**< Shift value for BURTC_DISABLING */ -#define _BURTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for BURTC_DISABLING */ -#define _BURTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ -#define BURTC_EN_DISABLING_DEFAULT (_BURTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EN */ +#define _BURTC_EN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EN */ +#define _BURTC_EN_MASK 0x00000003UL /**< Mask for BURTC_EN */ +#define BURTC_EN_EN (0x1UL << 0) /**< BURTC Enable */ +#define _BURTC_EN_EN_SHIFT 0 /**< Shift value for BURTC_EN */ +#define _BURTC_EN_EN_MASK 0x1UL /**< Bit mask for BURTC_EN */ +#define _BURTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ +#define BURTC_EN_EN_DEFAULT (_BURTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EN */ +#define BURTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _BURTC_EN_DISABLING_SHIFT 1 /**< Shift value for BURTC_DISABLING */ +#define _BURTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for BURTC_DISABLING */ +#define _BURTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ +#define BURTC_EN_DISABLING_DEFAULT (_BURTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EN */ /* Bit fields for BURTC CFG */ -#define _BURTC_CFG_RESETVALUE 0x00000000UL /**< Default value for BURTC_CFG */ -#define _BURTC_CFG_MASK 0x000000F3UL /**< Mask for BURTC_CFG */ -#define BURTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ -#define _BURTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for BURTC_DEBUGRUN */ -#define _BURTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for BURTC_DEBUGRUN */ -#define _BURTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ -#define _BURTC_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for BURTC_CFG */ -#define _BURTC_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for BURTC_CFG */ -#define BURTC_CFG_DEBUGRUN_DEFAULT (_BURTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CFG */ -#define BURTC_CFG_DEBUGRUN_X0 (_BURTC_CFG_DEBUGRUN_X0 << 0) /**< Shifted mode X0 for BURTC_CFG */ -#define BURTC_CFG_DEBUGRUN_X1 (_BURTC_CFG_DEBUGRUN_X1 << 0) /**< Shifted mode X1 for BURTC_CFG */ -#define BURTC_CFG_COMPTOP (0x1UL << 1) /**< Compare Channel is Top Value */ -#define _BURTC_CFG_COMPTOP_SHIFT 1 /**< Shift value for BURTC_COMPTOP */ -#define _BURTC_CFG_COMPTOP_MASK 0x2UL /**< Bit mask for BURTC_COMPTOP */ -#define _BURTC_CFG_COMPTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ -#define _BURTC_CFG_COMPTOP_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ -#define _BURTC_CFG_COMPTOP_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ -#define BURTC_CFG_COMPTOP_DEFAULT (_BURTC_CFG_COMPTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CFG */ -#define BURTC_CFG_COMPTOP_DISABLE (_BURTC_CFG_COMPTOP_DISABLE << 1) /**< Shifted mode DISABLE for BURTC_CFG */ -#define BURTC_CFG_COMPTOP_ENABLE (_BURTC_CFG_COMPTOP_ENABLE << 1) /**< Shifted mode ENABLE for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for BURTC_CNTPRESC */ -#define _BURTC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for BURTC_CNTPRESC */ -#define _BURTC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DEFAULT (_BURTC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV1 (_BURTC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV2 (_BURTC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV4 (_BURTC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV8 (_BURTC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV16 (_BURTC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV32 (_BURTC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV64 (_BURTC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV128 (_BURTC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV256 (_BURTC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV512 (_BURTC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV1024 (_BURTC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV2048 (_BURTC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV4096 (_BURTC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV8192 (_BURTC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV16384 (_BURTC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV32768 (_BURTC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for BURTC_CFG */ +#define _BURTC_CFG_RESETVALUE 0x00000000UL /**< Default value for BURTC_CFG */ +#define _BURTC_CFG_MASK 0x000000F3UL /**< Mask for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _BURTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_DEFAULT (_BURTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_X0 (_BURTC_CFG_DEBUGRUN_X0 << 0) /**< Shifted mode X0 for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_X1 (_BURTC_CFG_DEBUGRUN_X1 << 0) /**< Shifted mode X1 for BURTC_CFG */ +#define BURTC_CFG_COMPTOP (0x1UL << 1) /**< Compare Channel is Top Value */ +#define _BURTC_CFG_COMPTOP_SHIFT 1 /**< Shift value for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_MASK 0x2UL /**< Bit mask for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DEFAULT (_BURTC_CFG_COMPTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DISABLE (_BURTC_CFG_COMPTOP_DISABLE << 1) /**< Shifted mode DISABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_ENABLE (_BURTC_CFG_COMPTOP_ENABLE << 1) /**< Shifted mode ENABLE for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DEFAULT (_BURTC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1 (_BURTC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2 (_BURTC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4 (_BURTC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8 (_BURTC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16 (_BURTC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32 (_BURTC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV64 (_BURTC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV128 (_BURTC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV256 (_BURTC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV512 (_BURTC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1024 (_BURTC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2048 (_BURTC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4096 (_BURTC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8192 (_BURTC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16384 (_BURTC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32768 (_BURTC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for BURTC_CFG */ /* Bit fields for BURTC CMD */ -#define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */ -#define _BURTC_CMD_MASK 0x00000003UL /**< Mask for BURTC_CMD */ -#define BURTC_CMD_START (0x1UL << 0) /**< Start BURTC counter */ -#define _BURTC_CMD_START_SHIFT 0 /**< Shift value for BURTC_START */ -#define _BURTC_CMD_START_MASK 0x1UL /**< Bit mask for BURTC_START */ -#define _BURTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ -#define BURTC_CMD_START_DEFAULT (_BURTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */ -#define BURTC_CMD_STOP (0x1UL << 1) /**< Stop BURTC counter */ -#define _BURTC_CMD_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ -#define _BURTC_CMD_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ -#define _BURTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ -#define BURTC_CMD_STOP_DEFAULT (_BURTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CMD */ +#define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */ +#define _BURTC_CMD_MASK 0x00000003UL /**< Mask for BURTC_CMD */ +#define BURTC_CMD_START (0x1UL << 0) /**< Start BURTC counter */ +#define _BURTC_CMD_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_CMD_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_START_DEFAULT (_BURTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP (0x1UL << 1) /**< Stop BURTC counter */ +#define _BURTC_CMD_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_CMD_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP_DEFAULT (_BURTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CMD */ /* Bit fields for BURTC STATUS */ -#define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */ -#define _BURTC_STATUS_MASK 0x00000003UL /**< Mask for BURTC_STATUS */ -#define BURTC_STATUS_RUNNING (0x1UL << 0) /**< BURTC running status */ -#define _BURTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for BURTC_RUNNING */ -#define _BURTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for BURTC_RUNNING */ -#define _BURTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ -#define BURTC_STATUS_RUNNING_DEFAULT (_BURTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */ -#define BURTC_STATUS_LOCK (0x1UL << 1) /**< Configuration Lock Status */ -#define _BURTC_STATUS_LOCK_SHIFT 1 /**< Shift value for BURTC_LOCK */ -#define _BURTC_STATUS_LOCK_MASK 0x2UL /**< Bit mask for BURTC_LOCK */ -#define _BURTC_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ -#define _BURTC_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_STATUS */ -#define _BURTC_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_STATUS */ -#define BURTC_STATUS_LOCK_DEFAULT (_BURTC_STATUS_LOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */ -#define BURTC_STATUS_LOCK_UNLOCKED (_BURTC_STATUS_LOCK_UNLOCKED << 1) /**< Shifted mode UNLOCKED for BURTC_STATUS */ -#define BURTC_STATUS_LOCK_LOCKED (_BURTC_STATUS_LOCK_LOCKED << 1) /**< Shifted mode LOCKED for BURTC_STATUS */ +#define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */ +#define _BURTC_STATUS_MASK 0x00000003UL /**< Mask for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING (0x1UL << 0) /**< BURTC running status */ +#define _BURTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING_DEFAULT (_BURTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK (0x1UL << 1) /**< Configuration Lock Status */ +#define _BURTC_STATUS_LOCK_SHIFT 1 /**< Shift value for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_MASK 0x2UL /**< Bit mask for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_DEFAULT (_BURTC_STATUS_LOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_UNLOCKED (_BURTC_STATUS_LOCK_UNLOCKED << 1) /**< Shifted mode UNLOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_LOCKED (_BURTC_STATUS_LOCK_LOCKED << 1) /**< Shifted mode LOCKED for BURTC_STATUS */ /* Bit fields for BURTC IF */ -#define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */ -#define _BURTC_IF_MASK 0x00000003UL /**< Mask for BURTC_IF */ -#define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ -#define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */ -#define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ -#define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ -#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */ -#define BURTC_IF_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ -#define _BURTC_IF_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ -#define _BURTC_IF_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ -#define _BURTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ -#define BURTC_IF_COMP_DEFAULT (_BURTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */ +#define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */ +#define _BURTC_IF_MASK 0x00000003UL /**< Mask for BURTC_IF */ +#define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IF_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IF_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP_DEFAULT (_BURTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */ /* Bit fields for BURTC IEN */ -#define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */ -#define _BURTC_IEN_MASK 0x00000003UL /**< Mask for BURTC_IEN */ -#define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ -#define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */ -#define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ -#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ -#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */ -#define BURTC_IEN_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ -#define _BURTC_IEN_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ -#define _BURTC_IEN_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ -#define _BURTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ -#define BURTC_IEN_COMP_DEFAULT (_BURTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */ +#define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */ +#define _BURTC_IEN_MASK 0x00000003UL /**< Mask for BURTC_IEN */ +#define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IEN_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IEN_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP_DEFAULT (_BURTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */ /* Bit fields for BURTC PRECNT */ -#define _BURTC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_PRECNT */ -#define _BURTC_PRECNT_MASK 0x00007FFFUL /**< Mask for BURTC_PRECNT */ -#define _BURTC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for BURTC_PRECNT */ -#define _BURTC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for BURTC_PRECNT */ -#define _BURTC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_PRECNT */ -#define BURTC_PRECNT_PRECNT_DEFAULT (_BURTC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_PRECNT */ +#define _BURTC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_PRECNT */ +#define _BURTC_PRECNT_MASK 0x00007FFFUL /**< Mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_PRECNT */ +#define BURTC_PRECNT_PRECNT_DEFAULT (_BURTC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_PRECNT */ /* Bit fields for BURTC CNT */ -#define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */ -#define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */ -#define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */ -#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */ -#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */ -#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */ +#define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */ +#define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */ +#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */ +#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */ /* Bit fields for BURTC EM4WUEN */ -#define _BURTC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EM4WUEN */ -#define _BURTC_EM4WUEN_MASK 0x00000003UL /**< Mask for BURTC_EM4WUEN */ -#define BURTC_EM4WUEN_OFEM4WUEN (0x1UL << 0) /**< Overflow EM4 Wakeup Enable */ -#define _BURTC_EM4WUEN_OFEM4WUEN_SHIFT 0 /**< Shift value for BURTC_OFEM4WUEN */ -#define _BURTC_EM4WUEN_OFEM4WUEN_MASK 0x1UL /**< Bit mask for BURTC_OFEM4WUEN */ -#define _BURTC_EM4WUEN_OFEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ -#define BURTC_EM4WUEN_OFEM4WUEN_DEFAULT (_BURTC_EM4WUEN_OFEM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ -#define BURTC_EM4WUEN_COMPEM4WUEN (0x1UL << 1) /**< Compare Match EM4 Wakeup Enable */ -#define _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT 1 /**< Shift value for BURTC_COMPEM4WUEN */ -#define _BURTC_EM4WUEN_COMPEM4WUEN_MASK 0x2UL /**< Bit mask for BURTC_COMPEM4WUEN */ -#define _BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ -#define BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT (_BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ +#define _BURTC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EM4WUEN */ +#define _BURTC_EM4WUEN_MASK 0x00000003UL /**< Mask for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN (0x1UL << 0) /**< Overflow EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_OFEM4WUEN_SHIFT 0 /**< Shift value for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_MASK 0x1UL /**< Bit mask for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN_DEFAULT (_BURTC_EM4WUEN_OFEM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN (0x1UL << 1) /**< Compare Match EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT 1 /**< Shift value for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_MASK 0x2UL /**< Bit mask for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT (_BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ /* Bit fields for BURTC SYNCBUSY */ -#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */ -#define _BURTC_SYNCBUSY_MASK 0x0000001FUL /**< Mask for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ -#define _BURTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for BURTC_START */ -#define _BURTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for BURTC_START */ -#define _BURTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_START_DEFAULT (_BURTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ -#define _BURTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ -#define _BURTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ -#define _BURTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_STOP_DEFAULT (_BURTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ -#define _BURTC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for BURTC_PRECNT */ -#define _BURTC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for BURTC_PRECNT */ -#define _BURTC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_PRECNT_DEFAULT (_BURTC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ -#define _BURTC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for BURTC_CNT */ -#define _BURTC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for BURTC_CNT */ -#define _BURTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_CNT_DEFAULT (_BURTC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_COMP (0x1UL << 4) /**< Sync busy for COMP */ -#define _BURTC_SYNCBUSY_COMP_SHIFT 4 /**< Shift value for BURTC_COMP */ -#define _BURTC_SYNCBUSY_COMP_MASK 0x10UL /**< Bit mask for BURTC_COMP */ -#define _BURTC_SYNCBUSY_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_COMP_DEFAULT (_BURTC_SYNCBUSY_COMP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */ +#define _BURTC_SYNCBUSY_MASK 0x0000001FUL /**< Mask for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ +#define _BURTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START_DEFAULT (_BURTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ +#define _BURTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP_DEFAULT (_BURTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT_DEFAULT (_BURTC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ +#define _BURTC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT_DEFAULT (_BURTC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP (0x1UL << 4) /**< Sync busy for COMP */ +#define _BURTC_SYNCBUSY_COMP_SHIFT 4 /**< Shift value for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_MASK 0x10UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP_DEFAULT (_BURTC_SYNCBUSY_COMP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ /* Bit fields for BURTC LOCK */ -#define _BURTC_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for BURTC_LOCK */ -#define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */ -#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */ -#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */ -#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for BURTC_LOCK */ -#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */ -#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */ -#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */ +#define _BURTC_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for BURTC_LOCK */ +#define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */ /* Bit fields for BURTC COMP */ -#define _BURTC_COMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP */ -#define _BURTC_COMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP */ -#define _BURTC_COMP_COMP_SHIFT 0 /**< Shift value for BURTC_COMP */ -#define _BURTC_COMP_COMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP */ -#define _BURTC_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP */ -#define BURTC_COMP_COMP_DEFAULT (_BURTC_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP */ +#define _BURTC_COMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP */ +#define _BURTC_COMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_SHIFT 0 /**< Shift value for BURTC_COMP */ +#define _BURTC_COMP_COMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP */ +#define BURTC_COMP_COMP_DEFAULT (_BURTC_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP */ /** @} End of group EFR32SG28_BURTC_BitFields */ /** @} End of group EFR32SG28_BURTC */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_cmu.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_cmu.h index 71c0385997..018540c2fb 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_cmu.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_cmu.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_CMU_H #define EFR32SG28_CMU_H - #define CMU_HAS_SET_CLEAR /**************************************************************************//** @@ -43,227 +42,226 @@ *****************************************************************************/ /** CMU Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version ID */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - __IOM uint32_t WDOGLOCK; /**< WDOG Configuration Lock Register */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED3[10U]; /**< Reserved for future use */ - __IOM uint32_t CALCMD; /**< Calibration Command Register */ - __IOM uint32_t CALCTRL; /**< Calibration Control Register */ - __IM uint32_t CALCNT; /**< Calibration Result Counter Register */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t CLKEN0; /**< Clock Enable Register 0 */ - __IOM uint32_t CLKEN1; /**< Clock Enable Register 1 */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IOM uint32_t SYSCLKCTRL; /**< System Clock Control */ - uint32_t RESERVED6[3U]; /**< Reserved for future use */ - __IOM uint32_t TRACECLKCTRL; /**< Debug Trace Clock Control */ - uint32_t RESERVED7[3U]; /**< Reserved for future use */ - __IOM uint32_t EXPORTCLKCTRL; /**< Export Clock Control */ - uint32_t RESERVED8[27U]; /**< Reserved for future use */ - __IOM uint32_t DPLLREFCLKCTRL; /**< Digital PLL Reference Clock Control */ - uint32_t RESERVED9[7U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPACLKCTRL; /**< EM01 Peripheral Group A Clock Control */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPCCLKCTRL; /**< EM01 Peripheral Group C Clock Control */ - uint32_t RESERVED11[5U]; /**< Reserved for future use */ - __IOM uint32_t EM23GRPACLKCTRL; /**< EM23 Peripheral Group A Clock Control */ - uint32_t RESERVED12[7U]; /**< Reserved for future use */ - __IOM uint32_t EM4GRPACLKCTRL; /**< EM4 Peripheral Group A Clock Control */ - uint32_t RESERVED13[7U]; /**< Reserved for future use */ - __IOM uint32_t IADCCLKCTRL; /**< IADC Clock Control */ - uint32_t RESERVED14[31U]; /**< Reserved for future use */ - __IOM uint32_t WDOG0CLKCTRL; /**< Watchdog0 Clock Control */ - uint32_t RESERVED15[1U]; /**< Reserved for future use */ - __IOM uint32_t WDOG1CLKCTRL; /**< Watchdog1 Clock Control */ - uint32_t RESERVED16[5U]; /**< Reserved for future use */ - __IOM uint32_t EUSART0CLKCTRL; /**< EUSART0 Clock Control */ - uint32_t RESERVED17[7U]; /**< Reserved for future use */ - __IOM uint32_t SYSRTC0CLKCTRL; /**< System RTC0 Clock Control */ - uint32_t RESERVED18[3U]; /**< Reserved for future use */ - __IOM uint32_t LCDCLKCTRL; /**< LCD Clock Control */ - uint32_t RESERVED19[3U]; /**< Reserved for future use */ - __IOM uint32_t VDAC0CLKCTRL; /**< VDAC0 Clock Control */ - uint32_t RESERVED20[3U]; /**< Reserved for future use */ - __IOM uint32_t PCNT0CLKCTRL; /**< Pulse counter 0 Clock Control */ - uint32_t RESERVED21[3U]; /**< Reserved for future use */ - __IOM uint32_t RADIOCLKCTRL; /**< Radio Clock Control */ - uint32_t RESERVED22[3U]; /**< Reserved for future use */ - __IOM uint32_t LESENSEHFCLKCTRL; /**< LESENSE HF Clock Control */ - uint32_t RESERVED23[1U]; /**< Reserved for future use */ - uint32_t RESERVED24[1U]; /**< Reserved for future use */ - uint32_t RESERVED25[857U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - uint32_t RESERVED26[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - uint32_t RESERVED27[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - __IOM uint32_t WDOGLOCK_SET; /**< WDOG Configuration Lock Register */ - uint32_t RESERVED28[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED29[10U]; /**< Reserved for future use */ - __IOM uint32_t CALCMD_SET; /**< Calibration Command Register */ - __IOM uint32_t CALCTRL_SET; /**< Calibration Control Register */ - __IM uint32_t CALCNT_SET; /**< Calibration Result Counter Register */ - uint32_t RESERVED30[2U]; /**< Reserved for future use */ - __IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 */ - __IOM uint32_t CLKEN1_SET; /**< Clock Enable Register 1 */ - uint32_t RESERVED31[1U]; /**< Reserved for future use */ - __IOM uint32_t SYSCLKCTRL_SET; /**< System Clock Control */ - uint32_t RESERVED32[3U]; /**< Reserved for future use */ - __IOM uint32_t TRACECLKCTRL_SET; /**< Debug Trace Clock Control */ - uint32_t RESERVED33[3U]; /**< Reserved for future use */ - __IOM uint32_t EXPORTCLKCTRL_SET; /**< Export Clock Control */ - uint32_t RESERVED34[27U]; /**< Reserved for future use */ - __IOM uint32_t DPLLREFCLKCTRL_SET; /**< Digital PLL Reference Clock Control */ - uint32_t RESERVED35[7U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPACLKCTRL_SET; /**< EM01 Peripheral Group A Clock Control */ - uint32_t RESERVED36[1U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPCCLKCTRL_SET; /**< EM01 Peripheral Group C Clock Control */ - uint32_t RESERVED37[5U]; /**< Reserved for future use */ - __IOM uint32_t EM23GRPACLKCTRL_SET; /**< EM23 Peripheral Group A Clock Control */ - uint32_t RESERVED38[7U]; /**< Reserved for future use */ - __IOM uint32_t EM4GRPACLKCTRL_SET; /**< EM4 Peripheral Group A Clock Control */ - uint32_t RESERVED39[7U]; /**< Reserved for future use */ - __IOM uint32_t IADCCLKCTRL_SET; /**< IADC Clock Control */ - uint32_t RESERVED40[31U]; /**< Reserved for future use */ - __IOM uint32_t WDOG0CLKCTRL_SET; /**< Watchdog0 Clock Control */ - uint32_t RESERVED41[1U]; /**< Reserved for future use */ - __IOM uint32_t WDOG1CLKCTRL_SET; /**< Watchdog1 Clock Control */ - uint32_t RESERVED42[5U]; /**< Reserved for future use */ - __IOM uint32_t EUSART0CLKCTRL_SET; /**< EUSART0 Clock Control */ - uint32_t RESERVED43[7U]; /**< Reserved for future use */ - __IOM uint32_t SYSRTC0CLKCTRL_SET; /**< System RTC0 Clock Control */ - uint32_t RESERVED44[3U]; /**< Reserved for future use */ - __IOM uint32_t LCDCLKCTRL_SET; /**< LCD Clock Control */ - uint32_t RESERVED45[3U]; /**< Reserved for future use */ - __IOM uint32_t VDAC0CLKCTRL_SET; /**< VDAC0 Clock Control */ - uint32_t RESERVED46[3U]; /**< Reserved for future use */ - __IOM uint32_t PCNT0CLKCTRL_SET; /**< Pulse counter 0 Clock Control */ - uint32_t RESERVED47[3U]; /**< Reserved for future use */ - __IOM uint32_t RADIOCLKCTRL_SET; /**< Radio Clock Control */ - uint32_t RESERVED48[3U]; /**< Reserved for future use */ - __IOM uint32_t LESENSEHFCLKCTRL_SET; /**< LESENSE HF Clock Control */ - uint32_t RESERVED49[1U]; /**< Reserved for future use */ - uint32_t RESERVED50[1U]; /**< Reserved for future use */ - uint32_t RESERVED51[857U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - uint32_t RESERVED52[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - uint32_t RESERVED53[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - __IOM uint32_t WDOGLOCK_CLR; /**< WDOG Configuration Lock Register */ - uint32_t RESERVED54[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED55[10U]; /**< Reserved for future use */ - __IOM uint32_t CALCMD_CLR; /**< Calibration Command Register */ - __IOM uint32_t CALCTRL_CLR; /**< Calibration Control Register */ - __IM uint32_t CALCNT_CLR; /**< Calibration Result Counter Register */ - uint32_t RESERVED56[2U]; /**< Reserved for future use */ - __IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 */ - __IOM uint32_t CLKEN1_CLR; /**< Clock Enable Register 1 */ - uint32_t RESERVED57[1U]; /**< Reserved for future use */ - __IOM uint32_t SYSCLKCTRL_CLR; /**< System Clock Control */ - uint32_t RESERVED58[3U]; /**< Reserved for future use */ - __IOM uint32_t TRACECLKCTRL_CLR; /**< Debug Trace Clock Control */ - uint32_t RESERVED59[3U]; /**< Reserved for future use */ - __IOM uint32_t EXPORTCLKCTRL_CLR; /**< Export Clock Control */ - uint32_t RESERVED60[27U]; /**< Reserved for future use */ - __IOM uint32_t DPLLREFCLKCTRL_CLR; /**< Digital PLL Reference Clock Control */ - uint32_t RESERVED61[7U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPACLKCTRL_CLR; /**< EM01 Peripheral Group A Clock Control */ - uint32_t RESERVED62[1U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPCCLKCTRL_CLR; /**< EM01 Peripheral Group C Clock Control */ - uint32_t RESERVED63[5U]; /**< Reserved for future use */ - __IOM uint32_t EM23GRPACLKCTRL_CLR; /**< EM23 Peripheral Group A Clock Control */ - uint32_t RESERVED64[7U]; /**< Reserved for future use */ - __IOM uint32_t EM4GRPACLKCTRL_CLR; /**< EM4 Peripheral Group A Clock Control */ - uint32_t RESERVED65[7U]; /**< Reserved for future use */ - __IOM uint32_t IADCCLKCTRL_CLR; /**< IADC Clock Control */ - uint32_t RESERVED66[31U]; /**< Reserved for future use */ - __IOM uint32_t WDOG0CLKCTRL_CLR; /**< Watchdog0 Clock Control */ - uint32_t RESERVED67[1U]; /**< Reserved for future use */ - __IOM uint32_t WDOG1CLKCTRL_CLR; /**< Watchdog1 Clock Control */ - uint32_t RESERVED68[5U]; /**< Reserved for future use */ - __IOM uint32_t EUSART0CLKCTRL_CLR; /**< EUSART0 Clock Control */ - uint32_t RESERVED69[7U]; /**< Reserved for future use */ - __IOM uint32_t SYSRTC0CLKCTRL_CLR; /**< System RTC0 Clock Control */ - uint32_t RESERVED70[3U]; /**< Reserved for future use */ - __IOM uint32_t LCDCLKCTRL_CLR; /**< LCD Clock Control */ - uint32_t RESERVED71[3U]; /**< Reserved for future use */ - __IOM uint32_t VDAC0CLKCTRL_CLR; /**< VDAC0 Clock Control */ - uint32_t RESERVED72[3U]; /**< Reserved for future use */ - __IOM uint32_t PCNT0CLKCTRL_CLR; /**< Pulse counter 0 Clock Control */ - uint32_t RESERVED73[3U]; /**< Reserved for future use */ - __IOM uint32_t RADIOCLKCTRL_CLR; /**< Radio Clock Control */ - uint32_t RESERVED74[3U]; /**< Reserved for future use */ - __IOM uint32_t LESENSEHFCLKCTRL_CLR; /**< LESENSE HF Clock Control */ - uint32_t RESERVED75[1U]; /**< Reserved for future use */ - uint32_t RESERVED76[1U]; /**< Reserved for future use */ - uint32_t RESERVED77[857U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - uint32_t RESERVED78[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - uint32_t RESERVED79[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - __IOM uint32_t WDOGLOCK_TGL; /**< WDOG Configuration Lock Register */ - uint32_t RESERVED80[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED81[10U]; /**< Reserved for future use */ - __IOM uint32_t CALCMD_TGL; /**< Calibration Command Register */ - __IOM uint32_t CALCTRL_TGL; /**< Calibration Control Register */ - __IM uint32_t CALCNT_TGL; /**< Calibration Result Counter Register */ - uint32_t RESERVED82[2U]; /**< Reserved for future use */ - __IOM uint32_t CLKEN0_TGL; /**< Clock Enable Register 0 */ - __IOM uint32_t CLKEN1_TGL; /**< Clock Enable Register 1 */ - uint32_t RESERVED83[1U]; /**< Reserved for future use */ - __IOM uint32_t SYSCLKCTRL_TGL; /**< System Clock Control */ - uint32_t RESERVED84[3U]; /**< Reserved for future use */ - __IOM uint32_t TRACECLKCTRL_TGL; /**< Debug Trace Clock Control */ - uint32_t RESERVED85[3U]; /**< Reserved for future use */ - __IOM uint32_t EXPORTCLKCTRL_TGL; /**< Export Clock Control */ - uint32_t RESERVED86[27U]; /**< Reserved for future use */ - __IOM uint32_t DPLLREFCLKCTRL_TGL; /**< Digital PLL Reference Clock Control */ - uint32_t RESERVED87[7U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPACLKCTRL_TGL; /**< EM01 Peripheral Group A Clock Control */ - uint32_t RESERVED88[1U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPCCLKCTRL_TGL; /**< EM01 Peripheral Group C Clock Control */ - uint32_t RESERVED89[5U]; /**< Reserved for future use */ - __IOM uint32_t EM23GRPACLKCTRL_TGL; /**< EM23 Peripheral Group A Clock Control */ - uint32_t RESERVED90[7U]; /**< Reserved for future use */ - __IOM uint32_t EM4GRPACLKCTRL_TGL; /**< EM4 Peripheral Group A Clock Control */ - uint32_t RESERVED91[7U]; /**< Reserved for future use */ - __IOM uint32_t IADCCLKCTRL_TGL; /**< IADC Clock Control */ - uint32_t RESERVED92[31U]; /**< Reserved for future use */ - __IOM uint32_t WDOG0CLKCTRL_TGL; /**< Watchdog0 Clock Control */ - uint32_t RESERVED93[1U]; /**< Reserved for future use */ - __IOM uint32_t WDOG1CLKCTRL_TGL; /**< Watchdog1 Clock Control */ - uint32_t RESERVED94[5U]; /**< Reserved for future use */ - __IOM uint32_t EUSART0CLKCTRL_TGL; /**< EUSART0 Clock Control */ - uint32_t RESERVED95[7U]; /**< Reserved for future use */ - __IOM uint32_t SYSRTC0CLKCTRL_TGL; /**< System RTC0 Clock Control */ - uint32_t RESERVED96[3U]; /**< Reserved for future use */ - __IOM uint32_t LCDCLKCTRL_TGL; /**< LCD Clock Control */ - uint32_t RESERVED97[3U]; /**< Reserved for future use */ - __IOM uint32_t VDAC0CLKCTRL_TGL; /**< VDAC0 Clock Control */ - uint32_t RESERVED98[3U]; /**< Reserved for future use */ - __IOM uint32_t PCNT0CLKCTRL_TGL; /**< Pulse counter 0 Clock Control */ - uint32_t RESERVED99[3U]; /**< Reserved for future use */ - __IOM uint32_t RADIOCLKCTRL_TGL; /**< Radio Clock Control */ - uint32_t RESERVED100[3U]; /**< Reserved for future use */ - __IOM uint32_t LESENSEHFCLKCTRL_TGL; /**< LESENSE HF Clock Control */ - uint32_t RESERVED101[1U]; /**< Reserved for future use */ - uint32_t RESERVED102[1U]; /**< Reserved for future use */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED3[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IM uint32_t CALCNT; /**< Calibration Result Counter Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1; /**< Clock Enable Register 1 */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL; /**< System Clock Control */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL; /**< Debug Trace Clock Control */ + uint32_t RESERVED7[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL; /**< Export Clock Control */ + uint32_t RESERVED8[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED11[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL; /**< IADC Clock Control */ + uint32_t RESERVED14[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL; /**< Watchdog1 Clock Control */ + uint32_t RESERVED16[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL; /**< EUSART0 Clock Control */ + uint32_t RESERVED17[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL; /**< System RTC0 Clock Control */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCLKCTRL; /**< LCD Clock Control */ + uint32_t RESERVED19[3U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL; /**< VDAC0 Clock Control */ + uint32_t RESERVED20[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED21[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL; /**< Radio Clock Control */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + __IOM uint32_t LESENSEHFCLKCTRL; /**< LESENSE HF Clock Control */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + uint32_t RESERVED25[857U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_SET; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED28[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED29[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_SET; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_SET; /**< Calibration Control Register */ + __IM uint32_t CALCNT_SET; /**< Calibration Result Counter Register */ + uint32_t RESERVED30[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_SET; /**< Clock Enable Register 1 */ + uint32_t RESERVED31[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_SET; /**< System Clock Control */ + uint32_t RESERVED32[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_SET; /**< Debug Trace Clock Control */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_SET; /**< Export Clock Control */ + uint32_t RESERVED34[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_SET; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED35[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_SET; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED36[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_SET; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED37[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_SET; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED38[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_SET; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED39[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_SET; /**< IADC Clock Control */ + uint32_t RESERVED40[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_SET; /**< Watchdog0 Clock Control */ + uint32_t RESERVED41[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_SET; /**< Watchdog1 Clock Control */ + uint32_t RESERVED42[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_SET; /**< EUSART0 Clock Control */ + uint32_t RESERVED43[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_SET; /**< System RTC0 Clock Control */ + uint32_t RESERVED44[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCLKCTRL_SET; /**< LCD Clock Control */ + uint32_t RESERVED45[3U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_SET; /**< VDAC0 Clock Control */ + uint32_t RESERVED46[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_SET; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED47[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_SET; /**< Radio Clock Control */ + uint32_t RESERVED48[3U]; /**< Reserved for future use */ + __IOM uint32_t LESENSEHFCLKCTRL_SET; /**< LESENSE HF Clock Control */ + uint32_t RESERVED49[1U]; /**< Reserved for future use */ + uint32_t RESERVED50[1U]; /**< Reserved for future use */ + uint32_t RESERVED51[857U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED52[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED53[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_CLR; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED54[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED55[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_CLR; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_CLR; /**< Calibration Control Register */ + __IM uint32_t CALCNT_CLR; /**< Calibration Result Counter Register */ + uint32_t RESERVED56[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_CLR; /**< Clock Enable Register 1 */ + uint32_t RESERVED57[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_CLR; /**< System Clock Control */ + uint32_t RESERVED58[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_CLR; /**< Debug Trace Clock Control */ + uint32_t RESERVED59[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_CLR; /**< Export Clock Control */ + uint32_t RESERVED60[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_CLR; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED61[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_CLR; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED62[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_CLR; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED63[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_CLR; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED64[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_CLR; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED65[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_CLR; /**< IADC Clock Control */ + uint32_t RESERVED66[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_CLR; /**< Watchdog0 Clock Control */ + uint32_t RESERVED67[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_CLR; /**< Watchdog1 Clock Control */ + uint32_t RESERVED68[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_CLR; /**< EUSART0 Clock Control */ + uint32_t RESERVED69[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_CLR; /**< System RTC0 Clock Control */ + uint32_t RESERVED70[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCLKCTRL_CLR; /**< LCD Clock Control */ + uint32_t RESERVED71[3U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_CLR; /**< VDAC0 Clock Control */ + uint32_t RESERVED72[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_CLR; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED73[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_CLR; /**< Radio Clock Control */ + uint32_t RESERVED74[3U]; /**< Reserved for future use */ + __IOM uint32_t LESENSEHFCLKCTRL_CLR; /**< LESENSE HF Clock Control */ + uint32_t RESERVED75[1U]; /**< Reserved for future use */ + uint32_t RESERVED76[1U]; /**< Reserved for future use */ + uint32_t RESERVED77[857U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED78[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED79[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_TGL; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED80[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED81[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_TGL; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_TGL; /**< Calibration Control Register */ + __IM uint32_t CALCNT_TGL; /**< Calibration Result Counter Register */ + uint32_t RESERVED82[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_TGL; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_TGL; /**< Clock Enable Register 1 */ + uint32_t RESERVED83[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_TGL; /**< System Clock Control */ + uint32_t RESERVED84[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_TGL; /**< Debug Trace Clock Control */ + uint32_t RESERVED85[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_TGL; /**< Export Clock Control */ + uint32_t RESERVED86[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_TGL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED87[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_TGL; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED88[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_TGL; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED89[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_TGL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED90[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_TGL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED91[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_TGL; /**< IADC Clock Control */ + uint32_t RESERVED92[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_TGL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED93[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_TGL; /**< Watchdog1 Clock Control */ + uint32_t RESERVED94[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_TGL; /**< EUSART0 Clock Control */ + uint32_t RESERVED95[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_TGL; /**< System RTC0 Clock Control */ + uint32_t RESERVED96[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCLKCTRL_TGL; /**< LCD Clock Control */ + uint32_t RESERVED97[3U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_TGL; /**< VDAC0 Clock Control */ + uint32_t RESERVED98[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_TGL; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED99[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_TGL; /**< Radio Clock Control */ + uint32_t RESERVED100[3U]; /**< Reserved for future use */ + __IOM uint32_t LESENSEHFCLKCTRL_TGL; /**< LESENSE HF Clock Control */ + uint32_t RESERVED101[1U]; /**< Reserved for future use */ + uint32_t RESERVED102[1U]; /**< Reserved for future use */ } CMU_TypeDef; /** @} End of group EFR32SG28_CMU */ @@ -275,876 +273,876 @@ typedef struct *****************************************************************************/ /* Bit fields for CMU IPVERSION */ -#define _CMU_IPVERSION_RESETVALUE 0x00000006UL /**< Default value for CMU_IPVERSION */ -#define _CMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for CMU_IPVERSION */ -#define _CMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for CMU_IPVERSION */ -#define _CMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for CMU_IPVERSION */ -#define _CMU_IPVERSION_IPVERSION_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_IPVERSION */ -#define CMU_IPVERSION_IPVERSION_DEFAULT (_CMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IPVERSION */ +#define _CMU_IPVERSION_RESETVALUE 0x00000006UL /**< Default value for CMU_IPVERSION */ +#define _CMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_IPVERSION */ +#define CMU_IPVERSION_IPVERSION_DEFAULT (_CMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IPVERSION */ /* Bit fields for CMU STATUS */ -#define _CMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_STATUS */ -#define _CMU_STATUS_MASK 0xC0038001UL /**< Mask for CMU_STATUS */ -#define CMU_STATUS_CALRDY (0x1UL << 0) /**< Calibration Ready */ -#define _CMU_STATUS_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ -#define _CMU_STATUS_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ -#define _CMU_STATUS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ -#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ -#define CMU_STATUS_WDOGLOCK (0x1UL << 30) /**< Configuration Lock Status for WDOG */ -#define _CMU_STATUS_WDOGLOCK_SHIFT 30 /**< Shift value for CMU_WDOGLOCK */ -#define _CMU_STATUS_WDOGLOCK_MASK 0x40000000UL /**< Bit mask for CMU_WDOGLOCK */ -#define _CMU_STATUS_WDOGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ -#define _CMU_STATUS_WDOGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ -#define _CMU_STATUS_WDOGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ -#define CMU_STATUS_WDOGLOCK_DEFAULT (_CMU_STATUS_WDOGLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_STATUS */ -#define CMU_STATUS_WDOGLOCK_UNLOCKED (_CMU_STATUS_WDOGLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for CMU_STATUS */ -#define CMU_STATUS_WDOGLOCK_LOCKED (_CMU_STATUS_WDOGLOCK_LOCKED << 30) /**< Shifted mode LOCKED for CMU_STATUS */ -#define CMU_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ -#define _CMU_STATUS_LOCK_SHIFT 31 /**< Shift value for CMU_LOCK */ -#define _CMU_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for CMU_LOCK */ -#define _CMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ -#define _CMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ -#define _CMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ -#define CMU_STATUS_LOCK_DEFAULT (_CMU_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_STATUS */ -#define CMU_STATUS_LOCK_UNLOCKED (_CMU_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for CMU_STATUS */ -#define CMU_STATUS_LOCK_LOCKED (_CMU_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for CMU_STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0xC0038001UL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 0) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK (0x1UL << 30) /**< Configuration Lock Status for WDOG */ +#define _CMU_STATUS_WDOGLOCK_SHIFT 30 /**< Shift value for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_MASK 0x40000000UL /**< Bit mask for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_DEFAULT (_CMU_STATUS_WDOGLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_UNLOCKED (_CMU_STATUS_WDOGLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_LOCKED (_CMU_STATUS_WDOGLOCK_LOCKED << 30) /**< Shifted mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _CMU_STATUS_LOCK_SHIFT 31 /**< Shift value for CMU_LOCK */ +#define _CMU_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for CMU_LOCK */ +#define _CMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_DEFAULT (_CMU_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LOCK_UNLOCKED (_CMU_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_LOCKED (_CMU_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for CMU_STATUS */ /* Bit fields for CMU LOCK */ -#define _CMU_LOCK_RESETVALUE 0x000093F7UL /**< Default value for CMU_LOCK */ -#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ -#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ -#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ -#define _CMU_LOCK_LOCKKEY_DEFAULT 0x000093F7UL /**< Mode DEFAULT for CMU_LOCK */ -#define _CMU_LOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_LOCK */ -#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ -#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ +#define _CMU_LOCK_RESETVALUE 0x000093F7UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x000093F7UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ /* Bit fields for CMU WDOGLOCK */ -#define _CMU_WDOGLOCK_RESETVALUE 0x00005257UL /**< Default value for CMU_WDOGLOCK */ -#define _CMU_WDOGLOCK_MASK 0x0000FFFFUL /**< Mask for CMU_WDOGLOCK */ -#define _CMU_WDOGLOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ -#define _CMU_WDOGLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ -#define _CMU_WDOGLOCK_LOCKKEY_DEFAULT 0x00005257UL /**< Mode DEFAULT for CMU_WDOGLOCK */ -#define _CMU_WDOGLOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_WDOGLOCK */ -#define CMU_WDOGLOCK_LOCKKEY_DEFAULT (_CMU_WDOGLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOGLOCK */ -#define CMU_WDOGLOCK_LOCKKEY_UNLOCK (_CMU_WDOGLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_RESETVALUE 0x00005257UL /**< Default value for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_MASK 0x0000FFFFUL /**< Mask for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_DEFAULT 0x00005257UL /**< Mode DEFAULT for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_DEFAULT (_CMU_WDOGLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_UNLOCK (_CMU_WDOGLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_WDOGLOCK */ /* Bit fields for CMU IF */ -#define _CMU_IF_RESETVALUE 0x00000000UL /**< Default value for CMU_IF */ -#define _CMU_IF_MASK 0x00000003UL /**< Mask for CMU_IF */ -#define CMU_IF_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Flag */ -#define _CMU_IF_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ -#define _CMU_IF_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ -#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ -#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ -#define CMU_IF_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Flag */ -#define _CMU_IF_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ -#define _CMU_IF_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ -#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ -#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define _CMU_IF_RESETVALUE 0x00000000UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0x00000003UL /**< Mask for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ /* Bit fields for CMU IEN */ -#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ -#define _CMU_IEN_MASK 0x00000003UL /**< Mask for CMU_IEN */ -#define CMU_IEN_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Enable */ -#define _CMU_IEN_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ -#define _CMU_IEN_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ -#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ -#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ -#define CMU_IEN_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Enable */ -#define _CMU_IEN_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ -#define _CMU_IEN_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ -#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ -#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0x00000003UL /**< Mask for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ /* Bit fields for CMU CALCMD */ -#define _CMU_CALCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCMD */ -#define _CMU_CALCMD_MASK 0x00000003UL /**< Mask for CMU_CALCMD */ -#define CMU_CALCMD_CALSTART (0x1UL << 0) /**< Calibration Start */ -#define _CMU_CALCMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ -#define _CMU_CALCMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ -#define _CMU_CALCMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ -#define CMU_CALCMD_CALSTART_DEFAULT (_CMU_CALCMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCMD */ -#define CMU_CALCMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ -#define _CMU_CALCMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ -#define _CMU_CALCMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ -#define _CMU_CALCMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ -#define CMU_CALCMD_CALSTOP_DEFAULT (_CMU_CALCMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CALCMD */ +#define _CMU_CALCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCMD */ +#define _CMU_CALCMD_MASK 0x00000003UL /**< Mask for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CALCMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART_DEFAULT (_CMU_CALCMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CALCMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP_DEFAULT (_CMU_CALCMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CALCMD */ /* Bit fields for CMU CALCTRL */ -#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ -#define _CMU_CALCTRL_MASK 0xFF8FFFFFUL /**< Mask for CMU_CALCTRL */ -#define _CMU_CALCTRL_CALTOP_SHIFT 0 /**< Shift value for CMU_CALTOP */ -#define _CMU_CALCTRL_CALTOP_MASK 0xFFFFFUL /**< Bit mask for CMU_CALTOP */ -#define _CMU_CALCTRL_CALTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_CALTOP_DEFAULT (_CMU_CALCTRL_CALTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_CONT (0x1UL << 23) /**< Continuous Calibration */ -#define _CMU_CALCTRL_CONT_SHIFT 23 /**< Shift value for CMU_CONT */ -#define _CMU_CALCTRL_CONT_MASK 0x800000UL /**< Bit mask for CMU_CONT */ -#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_SHIFT 24 /**< Shift value for CMU_UPSEL */ -#define _CMU_CALCTRL_UPSEL_MASK 0xF000000UL /**< Bit mask for CMU_UPSEL */ -#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_PRS 0x00000001UL /**< Mode PRS for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_LFXO 0x00000003UL /**< Mode LFXO for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_HFRCODPLL 0x00000004UL /**< Mode HFRCODPLL for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_HFRCOEM23 0x00000005UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000009UL /**< Mode LFRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_ULFRCO 0x0000000AUL /**< Mode ULFRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_DISABLED (_CMU_CALCTRL_UPSEL_DISABLED << 24) /**< Shifted mode DISABLED for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 24) /**< Shifted mode PRS for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 24) /**< Shifted mode HFXO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 24) /**< Shifted mode LFXO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_HFRCODPLL (_CMU_CALCTRL_UPSEL_HFRCODPLL << 24) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_HFRCOEM23 (_CMU_CALCTRL_UPSEL_HFRCOEM23 << 24) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_FSRCO (_CMU_CALCTRL_UPSEL_FSRCO << 24) /**< Shifted mode FSRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 24) /**< Shifted mode LFRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_ULFRCO (_CMU_CALCTRL_UPSEL_ULFRCO << 24) /**< Shifted mode ULFRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_SHIFT 28 /**< Shift value for CMU_DOWNSEL */ -#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0000000UL /**< Bit mask for CMU_DOWNSEL */ -#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_HCLK 0x00000001UL /**< Mode HCLK for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000002UL /**< Mode PRS for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_HFRCODPLL 0x00000005UL /**< Mode HFRCODPLL for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_HFRCOEM23 0x00000006UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x0000000AUL /**< Mode LFRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_ULFRCO 0x0000000BUL /**< Mode ULFRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_DISABLED (_CMU_CALCTRL_DOWNSEL_DISABLED << 28) /**< Shifted mode DISABLED for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_HCLK (_CMU_CALCTRL_DOWNSEL_HCLK << 28) /**< Shifted mode HCLK for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 28) /**< Shifted mode PRS for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 28) /**< Shifted mode HFXO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 28) /**< Shifted mode LFXO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_HFRCODPLL (_CMU_CALCTRL_DOWNSEL_HFRCODPLL << 28) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_HFRCOEM23 (_CMU_CALCTRL_DOWNSEL_HFRCOEM23 << 28) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_FSRCO (_CMU_CALCTRL_DOWNSEL_FSRCO << 28) /**< Shifted mode FSRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 28) /**< Shifted mode LFRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_ULFRCO (_CMU_CALCTRL_DOWNSEL_ULFRCO << 28) /**< Shifted mode ULFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0xFF8FFFFFUL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_CALTOP_SHIFT 0 /**< Shift value for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_MASK 0xFFFFFUL /**< Bit mask for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CALTOP_DEFAULT (_CMU_CALCTRL_CALTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 23) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 23 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x800000UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 24 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0xF000000UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000001UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000003UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCODPLL 0x00000004UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCOEM23 0x00000005UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000009UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_ULFRCO 0x0000000AUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DISABLED (_CMU_CALCTRL_UPSEL_DISABLED << 24) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 24) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 24) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 24) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCODPLL (_CMU_CALCTRL_UPSEL_HFRCODPLL << 24) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCOEM23 (_CMU_CALCTRL_UPSEL_HFRCOEM23 << 24) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_FSRCO (_CMU_CALCTRL_UPSEL_FSRCO << 24) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 24) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_ULFRCO (_CMU_CALCTRL_UPSEL_ULFRCO << 24) /**< Shifted mode ULFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 28 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0000000UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HCLK 0x00000001UL /**< Mode HCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000002UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCODPLL 0x00000005UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCOEM23 0x00000006UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x0000000AUL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_ULFRCO 0x0000000BUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DISABLED (_CMU_CALCTRL_DOWNSEL_DISABLED << 28) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HCLK (_CMU_CALCTRL_DOWNSEL_HCLK << 28) /**< Shifted mode HCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 28) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 28) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 28) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCODPLL (_CMU_CALCTRL_DOWNSEL_HFRCODPLL << 28) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCOEM23 (_CMU_CALCTRL_DOWNSEL_HFRCOEM23 << 28) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_FSRCO (_CMU_CALCTRL_DOWNSEL_FSRCO << 28) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 28) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_ULFRCO (_CMU_CALCTRL_DOWNSEL_ULFRCO << 28) /**< Shifted mode ULFRCO for CMU_CALCTRL */ /* Bit fields for CMU CALCNT */ -#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ -#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ -#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ -#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ -#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ -#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ /* Bit fields for CMU CLKEN0 */ -#define _CMU_CLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN0 */ -#define _CMU_CLKEN0_MASK 0xFFFFFFFFUL /**< Mask for CMU_CLKEN0 */ -#define CMU_CLKEN0_LDMA (0x1UL << 0) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LDMA_SHIFT 0 /**< Shift value for CMU_LDMA */ -#define _CMU_CLKEN0_LDMA_MASK 0x1UL /**< Bit mask for CMU_LDMA */ -#define _CMU_CLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LDMA_DEFAULT (_CMU_CLKEN0_LDMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LDMAXBAR (0x1UL << 1) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LDMAXBAR_SHIFT 1 /**< Shift value for CMU_LDMAXBAR */ -#define _CMU_CLKEN0_LDMAXBAR_MASK 0x2UL /**< Bit mask for CMU_LDMAXBAR */ -#define _CMU_CLKEN0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LDMAXBAR_DEFAULT (_CMU_CLKEN0_LDMAXBAR_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_RADIOAES (0x1UL << 2) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_RADIOAES_SHIFT 2 /**< Shift value for CMU_RADIOAES */ -#define _CMU_CLKEN0_RADIOAES_MASK 0x4UL /**< Bit mask for CMU_RADIOAES */ -#define _CMU_CLKEN0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_RADIOAES_DEFAULT (_CMU_CLKEN0_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_GPCRC (0x1UL << 3) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_GPCRC_SHIFT 3 /**< Shift value for CMU_GPCRC */ -#define _CMU_CLKEN0_GPCRC_MASK 0x8UL /**< Bit mask for CMU_GPCRC */ -#define _CMU_CLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_GPCRC_DEFAULT (_CMU_CLKEN0_GPCRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER0 (0x1UL << 4) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER0_SHIFT 4 /**< Shift value for CMU_TIMER0 */ -#define _CMU_CLKEN0_TIMER0_MASK 0x10UL /**< Bit mask for CMU_TIMER0 */ -#define _CMU_CLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER0_DEFAULT (_CMU_CLKEN0_TIMER0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER1 (0x1UL << 5) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER1_SHIFT 5 /**< Shift value for CMU_TIMER1 */ -#define _CMU_CLKEN0_TIMER1_MASK 0x20UL /**< Bit mask for CMU_TIMER1 */ -#define _CMU_CLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER1_DEFAULT (_CMU_CLKEN0_TIMER1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER2 (0x1UL << 6) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER2_SHIFT 6 /**< Shift value for CMU_TIMER2 */ -#define _CMU_CLKEN0_TIMER2_MASK 0x40UL /**< Bit mask for CMU_TIMER2 */ -#define _CMU_CLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER2_DEFAULT (_CMU_CLKEN0_TIMER2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER3 (0x1UL << 7) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER3_SHIFT 7 /**< Shift value for CMU_TIMER3 */ -#define _CMU_CLKEN0_TIMER3_MASK 0x80UL /**< Bit mask for CMU_TIMER3 */ -#define _CMU_CLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER3_DEFAULT (_CMU_CLKEN0_TIMER3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER4 (0x1UL << 8) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER4_SHIFT 8 /**< Shift value for CMU_TIMER4 */ -#define _CMU_CLKEN0_TIMER4_MASK 0x100UL /**< Bit mask for CMU_TIMER4 */ -#define _CMU_CLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER4_DEFAULT (_CMU_CLKEN0_TIMER4_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_USART0 (0x1UL << 9) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_USART0_SHIFT 9 /**< Shift value for CMU_USART0 */ -#define _CMU_CLKEN0_USART0_MASK 0x200UL /**< Bit mask for CMU_USART0 */ -#define _CMU_CLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_USART0_DEFAULT (_CMU_CLKEN0_USART0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_IADC0 (0x1UL << 10) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_IADC0_SHIFT 10 /**< Shift value for CMU_IADC0 */ -#define _CMU_CLKEN0_IADC0_MASK 0x400UL /**< Bit mask for CMU_IADC0 */ -#define _CMU_CLKEN0_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_IADC0_DEFAULT (_CMU_CLKEN0_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_AMUXCP0 (0x1UL << 11) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_AMUXCP0_SHIFT 11 /**< Shift value for CMU_AMUXCP0 */ -#define _CMU_CLKEN0_AMUXCP0_MASK 0x800UL /**< Bit mask for CMU_AMUXCP0 */ -#define _CMU_CLKEN0_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_AMUXCP0_DEFAULT (_CMU_CLKEN0_AMUXCP0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LETIMER0 (0x1UL << 12) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LETIMER0_SHIFT 12 /**< Shift value for CMU_LETIMER0 */ -#define _CMU_CLKEN0_LETIMER0_MASK 0x1000UL /**< Bit mask for CMU_LETIMER0 */ -#define _CMU_CLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LETIMER0_DEFAULT (_CMU_CLKEN0_LETIMER0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_WDOG0 (0x1UL << 13) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_WDOG0_SHIFT 13 /**< Shift value for CMU_WDOG0 */ -#define _CMU_CLKEN0_WDOG0_MASK 0x2000UL /**< Bit mask for CMU_WDOG0 */ -#define _CMU_CLKEN0_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_WDOG0_DEFAULT (_CMU_CLKEN0_WDOG0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_I2C0 (0x1UL << 14) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_I2C0_SHIFT 14 /**< Shift value for CMU_I2C0 */ -#define _CMU_CLKEN0_I2C0_MASK 0x4000UL /**< Bit mask for CMU_I2C0 */ -#define _CMU_CLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_I2C0_DEFAULT (_CMU_CLKEN0_I2C0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_I2C1 (0x1UL << 15) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_I2C1_SHIFT 15 /**< Shift value for CMU_I2C1 */ -#define _CMU_CLKEN0_I2C1_MASK 0x8000UL /**< Bit mask for CMU_I2C1 */ -#define _CMU_CLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_I2C1_DEFAULT (_CMU_CLKEN0_I2C1_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_SYSCFG (0x1UL << 16) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_SYSCFG_SHIFT 16 /**< Shift value for CMU_SYSCFG */ -#define _CMU_CLKEN0_SYSCFG_MASK 0x10000UL /**< Bit mask for CMU_SYSCFG */ -#define _CMU_CLKEN0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_SYSCFG_DEFAULT (_CMU_CLKEN0_SYSCFG_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_DPLL0 (0x1UL << 17) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_DPLL0_SHIFT 17 /**< Shift value for CMU_DPLL0 */ -#define _CMU_CLKEN0_DPLL0_MASK 0x20000UL /**< Bit mask for CMU_DPLL0 */ -#define _CMU_CLKEN0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_DPLL0_DEFAULT (_CMU_CLKEN0_DPLL0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFRCO0 (0x1UL << 18) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_HFRCO0_SHIFT 18 /**< Shift value for CMU_HFRCO0 */ -#define _CMU_CLKEN0_HFRCO0_MASK 0x40000UL /**< Bit mask for CMU_HFRCO0 */ -#define _CMU_CLKEN0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFRCO0_DEFAULT (_CMU_CLKEN0_HFRCO0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFRCOEM23 (0x1UL << 19) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_HFRCOEM23_SHIFT 19 /**< Shift value for CMU_HFRCOEM23 */ -#define _CMU_CLKEN0_HFRCOEM23_MASK 0x80000UL /**< Bit mask for CMU_HFRCOEM23 */ -#define _CMU_CLKEN0_HFRCOEM23_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFRCOEM23_DEFAULT (_CMU_CLKEN0_HFRCOEM23_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFXO0 (0x1UL << 20) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_HFXO0_SHIFT 20 /**< Shift value for CMU_HFXO0 */ -#define _CMU_CLKEN0_HFXO0_MASK 0x100000UL /**< Bit mask for CMU_HFXO0 */ -#define _CMU_CLKEN0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFXO0_DEFAULT (_CMU_CLKEN0_HFXO0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_FSRCO (0x1UL << 21) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_FSRCO_SHIFT 21 /**< Shift value for CMU_FSRCO */ -#define _CMU_CLKEN0_FSRCO_MASK 0x200000UL /**< Bit mask for CMU_FSRCO */ -#define _CMU_CLKEN0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_FSRCO_DEFAULT (_CMU_CLKEN0_FSRCO_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LFRCO (0x1UL << 22) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LFRCO_SHIFT 22 /**< Shift value for CMU_LFRCO */ -#define _CMU_CLKEN0_LFRCO_MASK 0x400000UL /**< Bit mask for CMU_LFRCO */ -#define _CMU_CLKEN0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LFRCO_DEFAULT (_CMU_CLKEN0_LFRCO_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LFXO (0x1UL << 23) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LFXO_SHIFT 23 /**< Shift value for CMU_LFXO */ -#define _CMU_CLKEN0_LFXO_MASK 0x800000UL /**< Bit mask for CMU_LFXO */ -#define _CMU_CLKEN0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LFXO_DEFAULT (_CMU_CLKEN0_LFXO_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_ULFRCO (0x1UL << 24) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_ULFRCO_SHIFT 24 /**< Shift value for CMU_ULFRCO */ -#define _CMU_CLKEN0_ULFRCO_MASK 0x1000000UL /**< Bit mask for CMU_ULFRCO */ -#define _CMU_CLKEN0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_ULFRCO_DEFAULT (_CMU_CLKEN0_ULFRCO_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LESENSE (0x1UL << 25) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LESENSE_SHIFT 25 /**< Shift value for CMU_LESENSE */ -#define _CMU_CLKEN0_LESENSE_MASK 0x2000000UL /**< Bit mask for CMU_LESENSE */ -#define _CMU_CLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LESENSE_DEFAULT (_CMU_CLKEN0_LESENSE_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_GPIO (0x1UL << 26) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_GPIO_SHIFT 26 /**< Shift value for CMU_GPIO */ -#define _CMU_CLKEN0_GPIO_MASK 0x4000000UL /**< Bit mask for CMU_GPIO */ -#define _CMU_CLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_GPIO_DEFAULT (_CMU_CLKEN0_GPIO_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_PRS (0x1UL << 27) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_PRS_SHIFT 27 /**< Shift value for CMU_PRS */ -#define _CMU_CLKEN0_PRS_MASK 0x8000000UL /**< Bit mask for CMU_PRS */ -#define _CMU_CLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_PRS_DEFAULT (_CMU_CLKEN0_PRS_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_BURAM (0x1UL << 28) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_BURAM_SHIFT 28 /**< Shift value for CMU_BURAM */ -#define _CMU_CLKEN0_BURAM_MASK 0x10000000UL /**< Bit mask for CMU_BURAM */ -#define _CMU_CLKEN0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_BURAM_DEFAULT (_CMU_CLKEN0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_BURTC (0x1UL << 29) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_BURTC_SHIFT 29 /**< Shift value for CMU_BURTC */ -#define _CMU_CLKEN0_BURTC_MASK 0x20000000UL /**< Bit mask for CMU_BURTC */ -#define _CMU_CLKEN0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_BURTC_DEFAULT (_CMU_CLKEN0_BURTC_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_SYSRTC0 (0x1UL << 30) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_SYSRTC0_SHIFT 30 /**< Shift value for CMU_SYSRTC0 */ -#define _CMU_CLKEN0_SYSRTC0_MASK 0x40000000UL /**< Bit mask for CMU_SYSRTC0 */ -#define _CMU_CLKEN0_SYSRTC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_SYSRTC0_DEFAULT (_CMU_CLKEN0_SYSRTC0_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_DCDC (0x1UL << 31) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_DCDC_SHIFT 31 /**< Shift value for CMU_DCDC */ -#define _CMU_CLKEN0_DCDC_MASK 0x80000000UL /**< Bit mask for CMU_DCDC */ -#define _CMU_CLKEN0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_DCDC_DEFAULT (_CMU_CLKEN0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define _CMU_CLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN0 */ +#define _CMU_CLKEN0_MASK 0xFFFFFFFFUL /**< Mask for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMA_SHIFT 0 /**< Shift value for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_MASK 0x1UL /**< Bit mask for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA_DEFAULT (_CMU_CLKEN0_LDMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMAXBAR_SHIFT 1 /**< Shift value for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_MASK 0x2UL /**< Bit mask for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR_DEFAULT (_CMU_CLKEN0_LDMAXBAR_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_RADIOAES_SHIFT 2 /**< Shift value for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_MASK 0x4UL /**< Bit mask for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES_DEFAULT (_CMU_CLKEN0_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPCRC_SHIFT 3 /**< Shift value for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_MASK 0x8UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC_DEFAULT (_CMU_CLKEN0_GPCRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0 (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER0_SHIFT 4 /**< Shift value for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_MASK 0x10UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0_DEFAULT (_CMU_CLKEN0_TIMER0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1 (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER1_SHIFT 5 /**< Shift value for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_MASK 0x20UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1_DEFAULT (_CMU_CLKEN0_TIMER1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2 (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER2_SHIFT 6 /**< Shift value for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_MASK 0x40UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2_DEFAULT (_CMU_CLKEN0_TIMER2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3 (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER3_SHIFT 7 /**< Shift value for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_MASK 0x80UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3_DEFAULT (_CMU_CLKEN0_TIMER3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER4 (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER4_SHIFT 8 /**< Shift value for CMU_TIMER4 */ +#define _CMU_CLKEN0_TIMER4_MASK 0x100UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_CLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER4_DEFAULT (_CMU_CLKEN0_TIMER4_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0 (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_USART0_SHIFT 9 /**< Shift value for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_MASK 0x200UL /**< Bit mask for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0_DEFAULT (_CMU_CLKEN0_USART0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0 (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_IADC0_SHIFT 10 /**< Shift value for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_MASK 0x400UL /**< Bit mask for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0_DEFAULT (_CMU_CLKEN0_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0 (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_AMUXCP0_SHIFT 11 /**< Shift value for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_MASK 0x800UL /**< Bit mask for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0_DEFAULT (_CMU_CLKEN0_AMUXCP0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0 (0x1UL << 12) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LETIMER0_SHIFT 12 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_MASK 0x1000UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0_DEFAULT (_CMU_CLKEN0_LETIMER0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0 (0x1UL << 13) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_WDOG0_SHIFT 13 /**< Shift value for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_MASK 0x2000UL /**< Bit mask for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0_DEFAULT (_CMU_CLKEN0_WDOG0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0 (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C0_SHIFT 14 /**< Shift value for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_MASK 0x4000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0_DEFAULT (_CMU_CLKEN0_I2C0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1 (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C1_SHIFT 15 /**< Shift value for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_MASK 0x8000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1_DEFAULT (_CMU_CLKEN0_I2C1_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_SYSCFG_SHIFT 16 /**< Shift value for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_MASK 0x10000UL /**< Bit mask for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG_DEFAULT (_CMU_CLKEN0_SYSCFG_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0 (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DPLL0_SHIFT 17 /**< Shift value for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_MASK 0x20000UL /**< Bit mask for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0_DEFAULT (_CMU_CLKEN0_DPLL0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFRCO0_SHIFT 18 /**< Shift value for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_MASK 0x40000UL /**< Bit mask for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0_DEFAULT (_CMU_CLKEN0_HFRCO0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCOEM23 (0x1UL << 19) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFRCOEM23_SHIFT 19 /**< Shift value for CMU_HFRCOEM23 */ +#define _CMU_CLKEN0_HFRCOEM23_MASK 0x80000UL /**< Bit mask for CMU_HFRCOEM23 */ +#define _CMU_CLKEN0_HFRCOEM23_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCOEM23_DEFAULT (_CMU_CLKEN0_HFRCOEM23_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0 (0x1UL << 20) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFXO0_SHIFT 20 /**< Shift value for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_MASK 0x100000UL /**< Bit mask for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0_DEFAULT (_CMU_CLKEN0_HFXO0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO (0x1UL << 21) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_FSRCO_SHIFT 21 /**< Shift value for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_MASK 0x200000UL /**< Bit mask for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO_DEFAULT (_CMU_CLKEN0_FSRCO_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO (0x1UL << 22) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFRCO_SHIFT 22 /**< Shift value for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_MASK 0x400000UL /**< Bit mask for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO_DEFAULT (_CMU_CLKEN0_LFRCO_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO (0x1UL << 23) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFXO_SHIFT 23 /**< Shift value for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_MASK 0x800000UL /**< Bit mask for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO_DEFAULT (_CMU_CLKEN0_LFXO_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO (0x1UL << 24) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_ULFRCO_SHIFT 24 /**< Shift value for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_MASK 0x1000000UL /**< Bit mask for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO_DEFAULT (_CMU_CLKEN0_ULFRCO_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LESENSE (0x1UL << 25) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LESENSE_SHIFT 25 /**< Shift value for CMU_LESENSE */ +#define _CMU_CLKEN0_LESENSE_MASK 0x2000000UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_CLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LESENSE_DEFAULT (_CMU_CLKEN0_LESENSE_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO (0x1UL << 26) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPIO_SHIFT 26 /**< Shift value for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_MASK 0x4000000UL /**< Bit mask for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO_DEFAULT (_CMU_CLKEN0_GPIO_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS (0x1UL << 27) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_PRS_SHIFT 27 /**< Shift value for CMU_PRS */ +#define _CMU_CLKEN0_PRS_MASK 0x8000000UL /**< Bit mask for CMU_PRS */ +#define _CMU_CLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS_DEFAULT (_CMU_CLKEN0_PRS_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM (0x1UL << 28) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURAM_SHIFT 28 /**< Shift value for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_MASK 0x10000000UL /**< Bit mask for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM_DEFAULT (_CMU_CLKEN0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC (0x1UL << 29) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURTC_SHIFT 29 /**< Shift value for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_MASK 0x20000000UL /**< Bit mask for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC_DEFAULT (_CMU_CLKEN0_BURTC_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSRTC0 (0x1UL << 30) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_SYSRTC0_SHIFT 30 /**< Shift value for CMU_SYSRTC0 */ +#define _CMU_CLKEN0_SYSRTC0_MASK 0x40000000UL /**< Bit mask for CMU_SYSRTC0 */ +#define _CMU_CLKEN0_SYSRTC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSRTC0_DEFAULT (_CMU_CLKEN0_SYSRTC0_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC (0x1UL << 31) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DCDC_SHIFT 31 /**< Shift value for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_MASK 0x80000000UL /**< Bit mask for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC_DEFAULT (_CMU_CLKEN0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ /* Bit fields for CMU CLKEN1 */ -#define _CMU_CLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN1 */ -#define _CMU_CLKEN1_MASK 0x3FFFFFFFUL /**< Mask for CMU_CLKEN1 */ -#define CMU_CLKEN1_AGC (0x1UL << 0) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_AGC_SHIFT 0 /**< Shift value for CMU_AGC */ -#define _CMU_CLKEN1_AGC_MASK 0x1UL /**< Bit mask for CMU_AGC */ -#define _CMU_CLKEN1_AGC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_AGC_DEFAULT (_CMU_CLKEN1_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MODEM (0x1UL << 1) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_MODEM_SHIFT 1 /**< Shift value for CMU_MODEM */ -#define _CMU_CLKEN1_MODEM_MASK 0x2UL /**< Bit mask for CMU_MODEM */ -#define _CMU_CLKEN1_MODEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MODEM_DEFAULT (_CMU_CLKEN1_MODEM_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFCRC (0x1UL << 2) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RFCRC_SHIFT 2 /**< Shift value for CMU_RFCRC */ -#define _CMU_CLKEN1_RFCRC_MASK 0x4UL /**< Bit mask for CMU_RFCRC */ -#define _CMU_CLKEN1_RFCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFCRC_DEFAULT (_CMU_CLKEN1_RFCRC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_FRC (0x1UL << 3) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_FRC_SHIFT 3 /**< Shift value for CMU_FRC */ -#define _CMU_CLKEN1_FRC_MASK 0x8UL /**< Bit mask for CMU_FRC */ -#define _CMU_CLKEN1_FRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_FRC_DEFAULT (_CMU_CLKEN1_FRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_PROTIMER (0x1UL << 4) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_PROTIMER_SHIFT 4 /**< Shift value for CMU_PROTIMER */ -#define _CMU_CLKEN1_PROTIMER_MASK 0x10UL /**< Bit mask for CMU_PROTIMER */ -#define _CMU_CLKEN1_PROTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_PROTIMER_DEFAULT (_CMU_CLKEN1_PROTIMER_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RAC (0x1UL << 5) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RAC_SHIFT 5 /**< Shift value for CMU_RAC */ -#define _CMU_CLKEN1_RAC_MASK 0x20UL /**< Bit mask for CMU_RAC */ -#define _CMU_CLKEN1_RAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RAC_DEFAULT (_CMU_CLKEN1_RAC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SYNTH (0x1UL << 6) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_SYNTH_SHIFT 6 /**< Shift value for CMU_SYNTH */ -#define _CMU_CLKEN1_SYNTH_MASK 0x40UL /**< Bit mask for CMU_SYNTH */ -#define _CMU_CLKEN1_SYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SYNTH_DEFAULT (_CMU_CLKEN1_SYNTH_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFSCRATCHPAD (0x1UL << 7) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RFSCRATCHPAD_SHIFT 7 /**< Shift value for CMU_RFSCRATCHPAD */ -#define _CMU_CLKEN1_RFSCRATCHPAD_MASK 0x80UL /**< Bit mask for CMU_RFSCRATCHPAD */ -#define _CMU_CLKEN1_RFSCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFSCRATCHPAD_DEFAULT (_CMU_CLKEN1_RFSCRATCHPAD_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_HOSTMAILBOX (0x1UL << 8) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_HOSTMAILBOX_SHIFT 8 /**< Shift value for CMU_HOSTMAILBOX */ -#define _CMU_CLKEN1_HOSTMAILBOX_MASK 0x100UL /**< Bit mask for CMU_HOSTMAILBOX */ -#define _CMU_CLKEN1_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_HOSTMAILBOX_DEFAULT (_CMU_CLKEN1_HOSTMAILBOX_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFMAILBOX (0x1UL << 9) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RFMAILBOX_SHIFT 9 /**< Shift value for CMU_RFMAILBOX */ -#define _CMU_CLKEN1_RFMAILBOX_MASK 0x200UL /**< Bit mask for CMU_RFMAILBOX */ -#define _CMU_CLKEN1_RFMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFMAILBOX_DEFAULT (_CMU_CLKEN1_RFMAILBOX_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SEMAILBOXHOST (0x1UL << 10) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_SEMAILBOXHOST_SHIFT 10 /**< Shift value for CMU_SEMAILBOXHOST */ -#define _CMU_CLKEN1_SEMAILBOXHOST_MASK 0x400UL /**< Bit mask for CMU_SEMAILBOXHOST */ -#define _CMU_CLKEN1_SEMAILBOXHOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SEMAILBOXHOST_DEFAULT (_CMU_CLKEN1_SEMAILBOXHOST_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_BUFC (0x1UL << 11) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_BUFC_SHIFT 11 /**< Shift value for CMU_BUFC */ -#define _CMU_CLKEN1_BUFC_MASK 0x800UL /**< Bit mask for CMU_BUFC */ -#define _CMU_CLKEN1_BUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_BUFC_DEFAULT (_CMU_CLKEN1_BUFC_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_LCD (0x1UL << 12) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ -#define _CMU_CLKEN1_LCD_MASK 0x1000UL /**< Bit mask for CMU_LCD */ -#define _CMU_CLKEN1_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_LCD_DEFAULT (_CMU_CLKEN1_LCD_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_KEYSCAN (0x1UL << 13) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_KEYSCAN_SHIFT 13 /**< Shift value for CMU_KEYSCAN */ -#define _CMU_CLKEN1_KEYSCAN_MASK 0x2000UL /**< Bit mask for CMU_KEYSCAN */ -#define _CMU_CLKEN1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_KEYSCAN_DEFAULT (_CMU_CLKEN1_KEYSCAN_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SMU (0x1UL << 14) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_SMU_SHIFT 14 /**< Shift value for CMU_SMU */ -#define _CMU_CLKEN1_SMU_MASK 0x4000UL /**< Bit mask for CMU_SMU */ -#define _CMU_CLKEN1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SMU_DEFAULT (_CMU_CLKEN1_SMU_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ICACHE0 (0x1UL << 15) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_ICACHE0_SHIFT 15 /**< Shift value for CMU_ICACHE0 */ -#define _CMU_CLKEN1_ICACHE0_MASK 0x8000UL /**< Bit mask for CMU_ICACHE0 */ -#define _CMU_CLKEN1_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ICACHE0_DEFAULT (_CMU_CLKEN1_ICACHE0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MSC (0x1UL << 16) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_MSC_SHIFT 16 /**< Shift value for CMU_MSC */ -#define _CMU_CLKEN1_MSC_MASK 0x10000UL /**< Bit mask for CMU_MSC */ -#define _CMU_CLKEN1_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MSC_DEFAULT (_CMU_CLKEN1_MSC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_WDOG1 (0x1UL << 17) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_WDOG1_SHIFT 17 /**< Shift value for CMU_WDOG1 */ -#define _CMU_CLKEN1_WDOG1_MASK 0x20000UL /**< Bit mask for CMU_WDOG1 */ -#define _CMU_CLKEN1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_WDOG1_DEFAULT (_CMU_CLKEN1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ACMP0 (0x1UL << 18) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_ACMP0_SHIFT 18 /**< Shift value for CMU_ACMP0 */ -#define _CMU_CLKEN1_ACMP0_MASK 0x40000UL /**< Bit mask for CMU_ACMP0 */ -#define _CMU_CLKEN1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ACMP0_DEFAULT (_CMU_CLKEN1_ACMP0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ACMP1 (0x1UL << 19) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_ACMP1_SHIFT 19 /**< Shift value for CMU_ACMP1 */ -#define _CMU_CLKEN1_ACMP1_MASK 0x80000UL /**< Bit mask for CMU_ACMP1 */ -#define _CMU_CLKEN1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ACMP1_DEFAULT (_CMU_CLKEN1_ACMP1_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_VDAC0 (0x1UL << 20) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_VDAC0_SHIFT 20 /**< Shift value for CMU_VDAC0 */ -#define _CMU_CLKEN1_VDAC0_MASK 0x100000UL /**< Bit mask for CMU_VDAC0 */ -#define _CMU_CLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_VDAC0_DEFAULT (_CMU_CLKEN1_VDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_PCNT0 (0x1UL << 21) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_PCNT0_SHIFT 21 /**< Shift value for CMU_PCNT0 */ -#define _CMU_CLKEN1_PCNT0_MASK 0x200000UL /**< Bit mask for CMU_PCNT0 */ -#define _CMU_CLKEN1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_PCNT0_DEFAULT (_CMU_CLKEN1_PCNT0_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_EUSART0 (0x1UL << 22) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_EUSART0_SHIFT 22 /**< Shift value for CMU_EUSART0 */ -#define _CMU_CLKEN1_EUSART0_MASK 0x400000UL /**< Bit mask for CMU_EUSART0 */ -#define _CMU_CLKEN1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_EUSART0_DEFAULT (_CMU_CLKEN1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_EUSART1 (0x1UL << 23) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_EUSART1_SHIFT 23 /**< Shift value for CMU_EUSART1 */ -#define _CMU_CLKEN1_EUSART1_MASK 0x800000UL /**< Bit mask for CMU_EUSART1 */ -#define _CMU_CLKEN1_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_EUSART1_DEFAULT (_CMU_CLKEN1_EUSART1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_EUSART2 (0x1UL << 24) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_EUSART2_SHIFT 24 /**< Shift value for CMU_EUSART2 */ -#define _CMU_CLKEN1_EUSART2_MASK 0x1000000UL /**< Bit mask for CMU_EUSART2 */ -#define _CMU_CLKEN1_EUSART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_EUSART2_DEFAULT (_CMU_CLKEN1_EUSART2_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFECA0 (0x1UL << 25) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RFECA0_SHIFT 25 /**< Shift value for CMU_RFECA0 */ -#define _CMU_CLKEN1_RFECA0_MASK 0x2000000UL /**< Bit mask for CMU_RFECA0 */ -#define _CMU_CLKEN1_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFECA0_DEFAULT (_CMU_CLKEN1_RFECA0_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFECA1 (0x1UL << 26) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RFECA1_SHIFT 26 /**< Shift value for CMU_RFECA1 */ -#define _CMU_CLKEN1_RFECA1_MASK 0x4000000UL /**< Bit mask for CMU_RFECA1 */ -#define _CMU_CLKEN1_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFECA1_DEFAULT (_CMU_CLKEN1_RFECA1_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_DMEM (0x1UL << 27) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_DMEM_SHIFT 27 /**< Shift value for CMU_DMEM */ -#define _CMU_CLKEN1_DMEM_MASK 0x8000000UL /**< Bit mask for CMU_DMEM */ -#define _CMU_CLKEN1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_DMEM_DEFAULT (_CMU_CLKEN1_DMEM_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ECAIFADC (0x1UL << 28) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_ECAIFADC_SHIFT 28 /**< Shift value for CMU_ECAIFADC */ -#define _CMU_CLKEN1_ECAIFADC_MASK 0x10000000UL /**< Bit mask for CMU_ECAIFADC */ -#define _CMU_CLKEN1_ECAIFADC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ECAIFADC_DEFAULT (_CMU_CLKEN1_ECAIFADC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MVP (0x1UL << 29) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_MVP_SHIFT 29 /**< Shift value for CMU_MVP */ -#define _CMU_CLKEN1_MVP_MASK 0x20000000UL /**< Bit mask for CMU_MVP */ -#define _CMU_CLKEN1_MVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MVP_DEFAULT (_CMU_CLKEN1_MVP_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define _CMU_CLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN1 */ +#define _CMU_CLKEN1_MASK 0x3FFFFFFFUL /**< Mask for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_AGC_SHIFT 0 /**< Shift value for CMU_AGC */ +#define _CMU_CLKEN1_AGC_MASK 0x1UL /**< Bit mask for CMU_AGC */ +#define _CMU_CLKEN1_AGC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC_DEFAULT (_CMU_CLKEN1_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MODEM_SHIFT 1 /**< Shift value for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_MASK 0x2UL /**< Bit mask for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM_DEFAULT (_CMU_CLKEN1_MODEM_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFCRC_SHIFT 2 /**< Shift value for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_MASK 0x4UL /**< Bit mask for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC_DEFAULT (_CMU_CLKEN1_RFCRC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_FRC_SHIFT 3 /**< Shift value for CMU_FRC */ +#define _CMU_CLKEN1_FRC_MASK 0x8UL /**< Bit mask for CMU_FRC */ +#define _CMU_CLKEN1_FRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC_DEFAULT (_CMU_CLKEN1_FRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PROTIMER_SHIFT 4 /**< Shift value for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_MASK 0x10UL /**< Bit mask for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER_DEFAULT (_CMU_CLKEN1_PROTIMER_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RAC_SHIFT 5 /**< Shift value for CMU_RAC */ +#define _CMU_CLKEN1_RAC_MASK 0x20UL /**< Bit mask for CMU_RAC */ +#define _CMU_CLKEN1_RAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC_DEFAULT (_CMU_CLKEN1_RAC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SYNTH_SHIFT 6 /**< Shift value for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_MASK 0x40UL /**< Bit mask for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH_DEFAULT (_CMU_CLKEN1_SYNTH_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSCRATCHPAD (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFSCRATCHPAD_SHIFT 7 /**< Shift value for CMU_RFSCRATCHPAD */ +#define _CMU_CLKEN1_RFSCRATCHPAD_MASK 0x80UL /**< Bit mask for CMU_RFSCRATCHPAD */ +#define _CMU_CLKEN1_RFSCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSCRATCHPAD_DEFAULT (_CMU_CLKEN1_RFSCRATCHPAD_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_HOSTMAILBOX (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_HOSTMAILBOX_SHIFT 8 /**< Shift value for CMU_HOSTMAILBOX */ +#define _CMU_CLKEN1_HOSTMAILBOX_MASK 0x100UL /**< Bit mask for CMU_HOSTMAILBOX */ +#define _CMU_CLKEN1_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_HOSTMAILBOX_DEFAULT (_CMU_CLKEN1_HOSTMAILBOX_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFMAILBOX (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFMAILBOX_SHIFT 9 /**< Shift value for CMU_RFMAILBOX */ +#define _CMU_CLKEN1_RFMAILBOX_MASK 0x200UL /**< Bit mask for CMU_RFMAILBOX */ +#define _CMU_CLKEN1_RFMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFMAILBOX_DEFAULT (_CMU_CLKEN1_RFMAILBOX_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SEMAILBOXHOST (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SEMAILBOXHOST_SHIFT 10 /**< Shift value for CMU_SEMAILBOXHOST */ +#define _CMU_CLKEN1_SEMAILBOXHOST_MASK 0x400UL /**< Bit mask for CMU_SEMAILBOXHOST */ +#define _CMU_CLKEN1_SEMAILBOXHOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SEMAILBOXHOST_DEFAULT (_CMU_CLKEN1_SEMAILBOXHOST_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_BUFC_SHIFT 11 /**< Shift value for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_MASK 0x800UL /**< Bit mask for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC_DEFAULT (_CMU_CLKEN1_BUFC_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_LCD (0x1UL << 12) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_CLKEN1_LCD_MASK 0x1000UL /**< Bit mask for CMU_LCD */ +#define _CMU_CLKEN1_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_LCD_DEFAULT (_CMU_CLKEN1_LCD_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_KEYSCAN (0x1UL << 13) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_KEYSCAN_SHIFT 13 /**< Shift value for CMU_KEYSCAN */ +#define _CMU_CLKEN1_KEYSCAN_MASK 0x2000UL /**< Bit mask for CMU_KEYSCAN */ +#define _CMU_CLKEN1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_KEYSCAN_DEFAULT (_CMU_CLKEN1_KEYSCAN_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SMU_SHIFT 14 /**< Shift value for CMU_SMU */ +#define _CMU_CLKEN1_SMU_MASK 0x4000UL /**< Bit mask for CMU_SMU */ +#define _CMU_CLKEN1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU_DEFAULT (_CMU_CLKEN1_SMU_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0 (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ICACHE0_SHIFT 15 /**< Shift value for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_MASK 0x8000UL /**< Bit mask for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0_DEFAULT (_CMU_CLKEN1_ICACHE0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MSC_SHIFT 16 /**< Shift value for CMU_MSC */ +#define _CMU_CLKEN1_MSC_MASK 0x10000UL /**< Bit mask for CMU_MSC */ +#define _CMU_CLKEN1_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC_DEFAULT (_CMU_CLKEN1_MSC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_WDOG1 (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_WDOG1_SHIFT 17 /**< Shift value for CMU_WDOG1 */ +#define _CMU_CLKEN1_WDOG1_MASK 0x20000UL /**< Bit mask for CMU_WDOG1 */ +#define _CMU_CLKEN1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_WDOG1_DEFAULT (_CMU_CLKEN1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP0 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ACMP0_SHIFT 18 /**< Shift value for CMU_ACMP0 */ +#define _CMU_CLKEN1_ACMP0_MASK 0x40000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_CLKEN1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP0_DEFAULT (_CMU_CLKEN1_ACMP0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP1 (0x1UL << 19) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ACMP1_SHIFT 19 /**< Shift value for CMU_ACMP1 */ +#define _CMU_CLKEN1_ACMP1_MASK 0x80000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_CLKEN1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP1_DEFAULT (_CMU_CLKEN1_ACMP1_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC0 (0x1UL << 20) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_VDAC0_SHIFT 20 /**< Shift value for CMU_VDAC0 */ +#define _CMU_CLKEN1_VDAC0_MASK 0x100000UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_CLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC0_DEFAULT (_CMU_CLKEN1_VDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PCNT0 (0x1UL << 21) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PCNT0_SHIFT 21 /**< Shift value for CMU_PCNT0 */ +#define _CMU_CLKEN1_PCNT0_MASK 0x200000UL /**< Bit mask for CMU_PCNT0 */ +#define _CMU_CLKEN1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PCNT0_DEFAULT (_CMU_CLKEN1_PCNT0_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART0 (0x1UL << 22) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART0_SHIFT 22 /**< Shift value for CMU_EUSART0 */ +#define _CMU_CLKEN1_EUSART0_MASK 0x400000UL /**< Bit mask for CMU_EUSART0 */ +#define _CMU_CLKEN1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART0_DEFAULT (_CMU_CLKEN1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART1 (0x1UL << 23) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART1_SHIFT 23 /**< Shift value for CMU_EUSART1 */ +#define _CMU_CLKEN1_EUSART1_MASK 0x800000UL /**< Bit mask for CMU_EUSART1 */ +#define _CMU_CLKEN1_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART1_DEFAULT (_CMU_CLKEN1_EUSART1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART2 (0x1UL << 24) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART2_SHIFT 24 /**< Shift value for CMU_EUSART2 */ +#define _CMU_CLKEN1_EUSART2_MASK 0x1000000UL /**< Bit mask for CMU_EUSART2 */ +#define _CMU_CLKEN1_EUSART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART2_DEFAULT (_CMU_CLKEN1_EUSART2_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA0 (0x1UL << 25) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFECA0_SHIFT 25 /**< Shift value for CMU_RFECA0 */ +#define _CMU_CLKEN1_RFECA0_MASK 0x2000000UL /**< Bit mask for CMU_RFECA0 */ +#define _CMU_CLKEN1_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA0_DEFAULT (_CMU_CLKEN1_RFECA0_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA1 (0x1UL << 26) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFECA1_SHIFT 26 /**< Shift value for CMU_RFECA1 */ +#define _CMU_CLKEN1_RFECA1_MASK 0x4000000UL /**< Bit mask for CMU_RFECA1 */ +#define _CMU_CLKEN1_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA1_DEFAULT (_CMU_CLKEN1_RFECA1_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_DMEM (0x1UL << 27) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_DMEM_SHIFT 27 /**< Shift value for CMU_DMEM */ +#define _CMU_CLKEN1_DMEM_MASK 0x8000000UL /**< Bit mask for CMU_DMEM */ +#define _CMU_CLKEN1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_DMEM_DEFAULT (_CMU_CLKEN1_DMEM_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ECAIFADC (0x1UL << 28) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ECAIFADC_SHIFT 28 /**< Shift value for CMU_ECAIFADC */ +#define _CMU_CLKEN1_ECAIFADC_MASK 0x10000000UL /**< Bit mask for CMU_ECAIFADC */ +#define _CMU_CLKEN1_ECAIFADC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ECAIFADC_DEFAULT (_CMU_CLKEN1_ECAIFADC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MVP (0x1UL << 29) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MVP_SHIFT 29 /**< Shift value for CMU_MVP */ +#define _CMU_CLKEN1_MVP_MASK 0x20000000UL /**< Bit mask for CMU_MVP */ +#define _CMU_CLKEN1_MVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MVP_DEFAULT (_CMU_CLKEN1_MVP_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ /* Bit fields for CMU SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_MASK 0x0001F507UL /**< Mask for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_SYSCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_SYSCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL 0x00000002UL /**< Mode HFRCODPLL for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_DEFAULT (_CMU_SYSCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_FSRCO (_CMU_SYSCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL (_CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_HFXO (_CMU_SYSCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_CLKIN0 (_CMU_SYSCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_PCLKPRESC (0x1UL << 10) /**< PCLK Prescaler */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT 10 /**< Shift value for CMU_PCLKPRESC */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_MASK 0x400UL /**< Bit mask for CMU_PCLKPRESC */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_PCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV1 << 10) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_PCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV2 << 10) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT 12 /**< Shift value for CMU_HCLKPRESC */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_MASK 0xF000UL /**< Bit mask for CMU_HCLKPRESC */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV8 0x00000007UL /**< Mode DIV8 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV16 0x0000000FUL /**< Mode DIV16 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV1 << 12) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV2 << 12) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV4 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV4 << 12) /**< Shifted mode DIV4 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV8 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV8 << 12) /**< Shifted mode DIV8 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV16 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV16 << 12) /**< Shifted mode DIV16 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_RHCLKPRESC (0x1UL << 16) /**< Radio HCLK Prescaler */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_SHIFT 16 /**< Shift value for CMU_RHCLKPRESC */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_MASK 0x10000UL /**< Bit mask for CMU_RHCLKPRESC */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_MASK 0x0001F507UL /**< Mask for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL 0x00000002UL /**< Mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_DEFAULT (_CMU_SYSCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_FSRCO (_CMU_SYSCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL (_CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFXO (_CMU_SYSCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_CLKIN0 (_CMU_SYSCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC (0x1UL << 10) /**< PCLK Prescaler */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT 10 /**< Shift value for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_MASK 0x400UL /**< Bit mask for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV1 << 10) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV2 << 10) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT 12 /**< Shift value for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_MASK 0xF000UL /**< Bit mask for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV8 0x00000007UL /**< Mode DIV8 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV16 0x0000000FUL /**< Mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV1 << 12) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV2 << 12) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV4 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV4 << 12) /**< Shifted mode DIV4 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV8 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV8 << 12) /**< Shifted mode DIV8 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV16 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV16 << 12) /**< Shifted mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC (0x1UL << 16) /**< Radio HCLK Prescaler */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_SHIFT 16 /**< Shift value for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_MASK 0x10000UL /**< Bit mask for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ /* Bit fields for CMU TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_MASK 0x00000033UL /**< Mask for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_TRACECLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_TRACECLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_CLKSEL_DISABLE 0x00000000UL /**< Mode DISABLE for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_CLKSEL_SYSCLK 0x00000001UL /**< Mode SYSCLK for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT 0x00000003UL /**< Mode HFRCODPLLRT for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_CLKSEL_DEFAULT (_CMU_TRACECLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_CLKSEL_DISABLE (_CMU_TRACECLKCTRL_CLKSEL_DISABLE << 0) /**< Shifted mode DISABLE for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_CLKSEL_SYSCLK (_CMU_TRACECLKCTRL_CLKSEL_SYSCLK << 0) /**< Shifted mode SYSCLK for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 (_CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_TRACECLKCTRL*/ -#define _CMU_TRACECLKCTRL_PRESC_SHIFT 4 /**< Shift value for CMU_PRESC */ -#define _CMU_TRACECLKCTRL_PRESC_MASK 0x30UL /**< Bit mask for CMU_PRESC */ -#define _CMU_TRACECLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_PRESC_DIV3 0x00000002UL /**< Mode DIV3 for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DEFAULT (_CMU_TRACECLKCTRL_PRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DIV1 (_CMU_TRACECLKCTRL_PRESC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DIV2 (_CMU_TRACECLKCTRL_PRESC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DIV3 (_CMU_TRACECLKCTRL_PRESC_DIV3 << 4) /**< Shifted mode DIV3 for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DIV4 (_CMU_TRACECLKCTRL_PRESC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_MASK 0x00000033UL /**< Mask for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_TRACECLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_TRACECLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_DISABLE 0x00000000UL /**< Mode DISABLE for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_SYSCLK 0x00000001UL /**< Mode SYSCLK for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT 0x00000003UL /**< Mode HFRCODPLLRT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_DEFAULT (_CMU_TRACECLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_DISABLE (_CMU_TRACECLKCTRL_CLKSEL_DISABLE << 0) /**< Shifted mode DISABLE for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_SYSCLK (_CMU_TRACECLKCTRL_CLKSEL_SYSCLK << 0) /**< Shifted mode SYSCLK for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 (_CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_TRACECLKCTRL*/ +#define _CMU_TRACECLKCTRL_PRESC_SHIFT 4 /**< Shift value for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_MASK 0x30UL /**< Bit mask for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV3 0x00000002UL /**< Mode DIV3 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DEFAULT (_CMU_TRACECLKCTRL_PRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV1 (_CMU_TRACECLKCTRL_PRESC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV2 (_CMU_TRACECLKCTRL_PRESC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV3 (_CMU_TRACECLKCTRL_PRESC_DIV3 << 4) /**< Shifted mode DIV3 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV4 (_CMU_TRACECLKCTRL_PRESC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_TRACECLKCTRL */ /* Bit fields for CMU EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_MASK 0x1F0F0F0FUL /**< Mask for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK << 0) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT 8 /**< Shift value for CMU_CLKOUTSEL1 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK 0xF00UL /**< Bit mask for CMU_CLKOUTSEL1 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED << 8) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK << 8) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK << 8) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO << 8) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO << 8) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO << 8) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL << 8) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO << 8) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO << 8) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 << 8) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_SHIFT 16 /**< Shift value for CMU_CLKOUTSEL2 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK 0xF0000UL /**< Bit mask for CMU_CLKOUTSEL2 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED << 16) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK << 16) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK << 16) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO << 16) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO << 16) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL << 16) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO << 16) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO << 16) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 << 16) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ -#define _CMU_EXPORTCLKCTRL_PRESC_SHIFT 24 /**< Shift value for CMU_PRESC */ -#define _CMU_EXPORTCLKCTRL_PRESC_MASK 0x1F000000UL /**< Bit mask for CMU_PRESC */ -#define _CMU_EXPORTCLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_PRESC_DEFAULT (_CMU_EXPORTCLKCTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_MASK 0x1F0F0F0FUL /**< Mask for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK << 0) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT 8 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK 0xF00UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED << 8) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK << 8) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK << 8) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO << 8) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO << 8) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO << 8) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL << 8) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO << 8) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO << 8) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 << 8) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_SHIFT 16 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK 0xF0000UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED << 16) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK << 16) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK << 16) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO << 16) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO << 16) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL << 16) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO << 16) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO << 16) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 << 16) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_PRESC_SHIFT 24 /**< Shift value for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_MASK 0x1F000000UL /**< Bit mask for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_PRESC_DEFAULT (_CMU_EXPORTCLKCTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ /* Bit fields for CMU DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLREFCLKCTRL */ -#define CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT (_CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLREFCLKCTRL */ -#define CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED (_CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_DPLLREFCLKCTRL*/ -#define CMU_DPLLREFCLKCTRL_CLKSEL_HFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_DPLLREFCLKCTRL */ -#define CMU_DPLLREFCLKCTRL_CLKSEL_LFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_DPLLREFCLKCTRL */ -#define CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 (_CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT (_CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED (_CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_DPLLREFCLKCTRL*/ +#define CMU_DPLLREFCLKCTRL_CLKSEL_HFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_LFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 (_CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_DPLLREFCLKCTRL */ /* Bit fields for CMU EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPACLKCTRL */ -#define CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPACLKCTRL*/ -#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPACLKCTRL*/ -#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPACLKCTRL */ -#define CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPACLKCTRL */ -#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPACLKCTRL*/ -#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL*/ -#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPACLKCTRL */ /* Bit fields for CMU EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPCCLKCTRL */ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPCCLKCTRL*/ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPCCLKCTRL*/ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPCCLKCTRL */ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPCCLKCTRL */ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL*/ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL*/ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPCCLKCTRL */ /* Bit fields for CMU EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM23GRPACLKCTRL */ -#define CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM23GRPACLKCTRL*/ -#define CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM23GRPACLKCTRL */ -#define CMU_EM23GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM23GRPACLKCTRL */ -#define CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM23GRPACLKCTRL*/ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM23GRPACLKCTRL */ /* Bit fields for CMU EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM4GRPACLKCTRL */ /* Bit fields for CMU IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_IADCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_IADCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_CLKSEL_FSRCO 0x00000002UL /**< Mode FSRCO for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 0x00000003UL /**< Mode HFRCOEM23 for CMU_IADCCLKCTRL */ -#define CMU_IADCCLKCTRL_CLKSEL_DEFAULT (_CMU_IADCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IADCCLKCTRL */ -#define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_IADCCLKCTRL*/ -#define CMU_IADCCLKCTRL_CLKSEL_FSRCO (_CMU_IADCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_IADCCLKCTRL */ -#define CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_FSRCO 0x00000002UL /**< Mode FSRCO for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 0x00000003UL /**< Mode HFRCOEM23 for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_DEFAULT (_CMU_IADCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_IADCCLKCTRL*/ +#define CMU_IADCCLKCTRL_CLKSEL_FSRCO (_CMU_IADCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_IADCCLKCTRL */ /* Bit fields for CMU WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_LFXO (_CMU_WDOG0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG0CLKCTRL*/ +#define _CMU_WDOG0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFXO (_CMU_WDOG0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG0CLKCTRL*/ /* Bit fields for CMU WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG1CLKCTRL */ -#define CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG1CLKCTRL */ -#define CMU_WDOG1CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG1CLKCTRL */ -#define CMU_WDOG1CLKCTRL_CLKSEL_LFXO (_CMU_WDOG1CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG1CLKCTRL */ -#define CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG1CLKCTRL */ -#define CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG1CLKCTRL*/ +#define _CMU_WDOG1CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_LFXO (_CMU_WDOG1CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG1CLKCTRL*/ /* Bit fields for CMU EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK 0x00000001UL /**< Mode EM01GRPCCLK for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_EUSART0CLKCTRL */ -#define CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT (_CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EUSART0CLKCTRL */ -#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/ -#define CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK (_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK << 0) /**< Shifted mode EM01GRPCCLK for CMU_EUSART0CLKCTRL*/ -#define CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EUSART0CLKCTRL*/ -#define CMU_EUSART0CLKCTRL_CLKSEL_LFRCO (_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EUSART0CLKCTRL */ -#define CMU_EUSART0CLKCTRL_CLKSEL_LFXO (_CMU_EUSART0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK 0x00000001UL /**< Mode EM01GRPCCLK for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT (_CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK (_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK << 0) /**< Shifted mode EM01GRPCCLK for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_LFRCO (_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_LFXO (_CMU_EUSART0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EUSART0CLKCTRL */ /* Bit fields for CMU SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_SYSRTC0CLKCTRL */ -#define CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT (_CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSRTC0CLKCTRL */ -#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_SYSRTC0CLKCTRL */ -#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_SYSRTC0CLKCTRL */ -#define CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT (_CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_SYSRTC0CLKCTRL */ /* Bit fields for CMU LCDCLKCTRL */ -#define _CMU_LCDCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_LCDCLKCTRL */ -#define _CMU_LCDCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_LCDCLKCTRL */ -#define _CMU_LCDCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_LCDCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_LCDCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LCDCLKCTRL */ -#define _CMU_LCDCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LCDCLKCTRL */ -#define _CMU_LCDCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_LCDCLKCTRL */ -#define _CMU_LCDCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_LCDCLKCTRL */ -#define CMU_LCDCLKCTRL_CLKSEL_DEFAULT (_CMU_LCDCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCLKCTRL */ -#define CMU_LCDCLKCTRL_CLKSEL_LFRCO (_CMU_LCDCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LCDCLKCTRL */ -#define CMU_LCDCLKCTRL_CLKSEL_LFXO (_CMU_LCDCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_LCDCLKCTRL */ -#define CMU_LCDCLKCTRL_CLKSEL_ULFRCO (_CMU_LCDCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_LCDCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_LCDCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_LCDCLKCTRL */ +#define CMU_LCDCLKCTRL_CLKSEL_DEFAULT (_CMU_LCDCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCLKCTRL */ +#define CMU_LCDCLKCTRL_CLKSEL_LFRCO (_CMU_LCDCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LCDCLKCTRL */ +#define CMU_LCDCLKCTRL_CLKSEL_LFXO (_CMU_LCDCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_LCDCLKCTRL */ +#define CMU_LCDCLKCTRL_CLKSEL_ULFRCO (_CMU_LCDCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LCDCLKCTRL */ /* Bit fields for CMU VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ -#define CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT (_CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_VDAC0CLKCTRL */ -#define CMU_VDAC0CLKCTRL_CLKSEL_DISABLED (_CMU_VDAC0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_VDAC0CLKCTRL */ -#define CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_VDAC0CLKCTRL*/ -#define CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_VDAC0CLKCTRL*/ -#define CMU_VDAC0CLKCTRL_CLKSEL_FSRCO (_CMU_VDAC0CLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_VDAC0CLKCTRL */ -#define CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT (_CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_DISABLED (_CMU_VDAC0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_VDAC0CLKCTRL*/ +#define CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_VDAC0CLKCTRL*/ +#define CMU_VDAC0CLKCTRL_CLKSEL_FSRCO (_CMU_VDAC0CLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ /* Bit fields for CMU PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000001UL /**< Mode EM23GRPACLK for CMU_PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 0x00000002UL /**< Mode PCNTS0 for CMU_PCNT0CLKCTRL */ -#define CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT (_CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNT0CLKCTRL */ -#define CMU_PCNT0CLKCTRL_CLKSEL_DISABLED (_CMU_PCNT0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_PCNT0CLKCTRL */ -#define CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_PCNT0CLKCTRL*/ -#define CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 (_CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 << 0) /**< Shifted mode PCNTS0 for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000001UL /**< Mode EM23GRPACLK for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 0x00000002UL /**< Mode PCNTS0 for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT (_CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_DISABLED (_CMU_PCNT0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_PCNT0CLKCTRL*/ +#define CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 (_CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 << 0) /**< Shifted mode PCNTS0 for CMU_PCNT0CLKCTRL */ /* Bit fields for CMU RADIOCLKCTRL */ -#define _CMU_RADIOCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_RADIOCLKCTRL */ -#define _CMU_RADIOCLKCTRL_MASK 0x80000003UL /**< Mask for CMU_RADIOCLKCTRL */ -#define CMU_RADIOCLKCTRL_EN (0x1UL << 0) /**< Enable */ -#define _CMU_RADIOCLKCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */ -#define _CMU_RADIOCLKCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */ -#define _CMU_RADIOCLKCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ -#define CMU_RADIOCLKCTRL_EN_DEFAULT (_CMU_RADIOCLKCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ -#define CMU_RADIOCLKCTRL_DBGCLK (0x1UL << 31) /**< Enable Clock for Debugger */ -#define _CMU_RADIOCLKCTRL_DBGCLK_SHIFT 31 /**< Shift value for CMU_DBGCLK */ -#define _CMU_RADIOCLKCTRL_DBGCLK_MASK 0x80000000UL /**< Bit mask for CMU_DBGCLK */ -#define _CMU_RADIOCLKCTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ -#define CMU_RADIOCLKCTRL_DBGCLK_DEFAULT (_CMU_RADIOCLKCTRL_DBGCLK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_MASK 0x80000003UL /**< Mask for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN (0x1UL << 0) /**< Enable */ +#define _CMU_RADIOCLKCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN_DEFAULT (_CMU_RADIOCLKCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK (0x1UL << 31) /**< Enable Clock for Debugger */ +#define _CMU_RADIOCLKCTRL_DBGCLK_SHIFT 31 /**< Shift value for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_MASK 0x80000000UL /**< Bit mask for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK_DEFAULT (_CMU_RADIOCLKCTRL_DBGCLK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ /* Bit fields for CMU LESENSEHFCLKCTRL */ -#define _CMU_LESENSEHFCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_LESENSEHFCLKCTRL */ -#define _CMU_LESENSEHFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_LESENSEHFCLKCTRL */ -#define _CMU_LESENSEHFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_LESENSEHFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_LESENSEHFCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LESENSEHFCLKCTRL */ -#define _CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_LESENSEHFCLKCTRL */ -#define _CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_LESENSEHFCLKCTRL */ -#define CMU_LESENSEHFCLKCTRL_CLKSEL_DEFAULT (_CMU_LESENSEHFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LESENSEHFCLKCTRL*/ -#define CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO (_CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_LESENSEHFCLKCTRL */ -#define CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_LESENSEHFCLKCTRL*/ +#define _CMU_LESENSEHFCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_LESENSEHFCLKCTRL */ +#define _CMU_LESENSEHFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_LESENSEHFCLKCTRL */ +#define _CMU_LESENSEHFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_LESENSEHFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_LESENSEHFCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LESENSEHFCLKCTRL */ +#define _CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_LESENSEHFCLKCTRL */ +#define _CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_LESENSEHFCLKCTRL */ +#define CMU_LESENSEHFCLKCTRL_CLKSEL_DEFAULT (_CMU_LESENSEHFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LESENSEHFCLKCTRL*/ +#define CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO (_CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_LESENSEHFCLKCTRL */ +#define CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_LESENSEHFCLKCTRL*/ /** @} End of group EFR32SG28_CMU_BitFields */ /** @} End of group EFR32SG28_CMU */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dcdc.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dcdc.h index bb832990e0..b8d9c3ce6e 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_devinfo.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_devinfo.h index fd0236ea78..b0644b97de 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dma_descriptor.h index d600112b7d..d535a43949 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dma_descriptor.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dpll.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dpll.h index eb0172ec1e..9ddc341992 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dpll.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_dpll.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_DPLL_H #define EFR32SG28_DPLL_H - #define DPLL_HAS_SET_CLEAR /**************************************************************************//** @@ -43,47 +42,46 @@ *****************************************************************************/ /** DPLL Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP Version */ - __IOM uint32_t EN; /**< Enable */ - __IOM uint32_t CFG; /**< Config */ - __IOM uint32_t CFG1; /**< Config1 */ - __IOM uint32_t IF; /**< Interrupt Flag */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - __IM uint32_t STATUS; /**< Status */ - uint32_t RESERVED0[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Lock */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - __IOM uint32_t EN_SET; /**< Enable */ - __IOM uint32_t CFG_SET; /**< Config */ - __IOM uint32_t CFG1_SET; /**< Config1 */ - __IOM uint32_t IF_SET; /**< Interrupt Flag */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - __IM uint32_t STATUS_SET; /**< Status */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Lock */ - uint32_t RESERVED3[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - __IOM uint32_t EN_CLR; /**< Enable */ - __IOM uint32_t CFG_CLR; /**< Config */ - __IOM uint32_t CFG1_CLR; /**< Config1 */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - __IM uint32_t STATUS_CLR; /**< Status */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Lock */ - uint32_t RESERVED5[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ - __IOM uint32_t EN_TGL; /**< Enable */ - __IOM uint32_t CFG_TGL; /**< Config */ - __IOM uint32_t CFG1_TGL; /**< Config1 */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - __IM uint32_t STATUS_TGL; /**< Status */ - uint32_t RESERVED6[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Lock */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CFG; /**< Config */ + __IOM uint32_t CFG1; /**< Config1 */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IM uint32_t STATUS; /**< Status */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CFG_SET; /**< Config */ + __IOM uint32_t CFG1_SET; /**< Config1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IM uint32_t STATUS_SET; /**< Status */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CFG_CLR; /**< Config */ + __IOM uint32_t CFG1_CLR; /**< Config1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IM uint32_t STATUS_CLR; /**< Status */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CFG_TGL; /**< Config */ + __IOM uint32_t CFG1_TGL; /**< Config1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IM uint32_t STATUS_TGL; /**< Status */ + uint32_t RESERVED6[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock */ } DPLL_TypeDef; /** @} End of group EFR32SG28_DPLL */ @@ -95,137 +93,137 @@ typedef struct *****************************************************************************/ /* Bit fields for DPLL IPVERSION */ -#define _DPLL_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for DPLL_IPVERSION */ -#define _DPLL_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DPLL_IPVERSION */ -#define _DPLL_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DPLL_IPVERSION */ -#define _DPLL_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DPLL_IPVERSION */ -#define _DPLL_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for DPLL_IPVERSION */ -#define DPLL_IPVERSION_IPVERSION_DEFAULT (_DPLL_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for DPLL_IPVERSION */ +#define DPLL_IPVERSION_IPVERSION_DEFAULT (_DPLL_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IPVERSION */ /* Bit fields for DPLL EN */ -#define _DPLL_EN_RESETVALUE 0x00000000UL /**< Default value for DPLL_EN */ -#define _DPLL_EN_MASK 0x00000003UL /**< Mask for DPLL_EN */ -#define DPLL_EN_EN (0x1UL << 0) /**< Module Enable */ -#define _DPLL_EN_EN_SHIFT 0 /**< Shift value for DPLL_EN */ -#define _DPLL_EN_EN_MASK 0x1UL /**< Bit mask for DPLL_EN */ -#define _DPLL_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ -#define DPLL_EN_EN_DEFAULT (_DPLL_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_EN */ -#define DPLL_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ -#define _DPLL_EN_DISABLING_SHIFT 1 /**< Shift value for DPLL_DISABLING */ -#define _DPLL_EN_DISABLING_MASK 0x2UL /**< Bit mask for DPLL_DISABLING */ -#define _DPLL_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ -#define DPLL_EN_DISABLING_DEFAULT (_DPLL_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_EN */ +#define _DPLL_EN_RESETVALUE 0x00000000UL /**< Default value for DPLL_EN */ +#define _DPLL_EN_MASK 0x00000003UL /**< Mask for DPLL_EN */ +#define DPLL_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _DPLL_EN_EN_SHIFT 0 /**< Shift value for DPLL_EN */ +#define _DPLL_EN_EN_MASK 0x1UL /**< Bit mask for DPLL_EN */ +#define _DPLL_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ +#define DPLL_EN_EN_DEFAULT (_DPLL_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_EN */ +#define DPLL_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ +#define _DPLL_EN_DISABLING_SHIFT 1 /**< Shift value for DPLL_DISABLING */ +#define _DPLL_EN_DISABLING_MASK 0x2UL /**< Bit mask for DPLL_DISABLING */ +#define _DPLL_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ +#define DPLL_EN_DISABLING_DEFAULT (_DPLL_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_EN */ /* Bit fields for DPLL CFG */ -#define _DPLL_CFG_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG */ -#define _DPLL_CFG_MASK 0x00000047UL /**< Mask for DPLL_CFG */ -#define DPLL_CFG_MODE (0x1UL << 0) /**< Operating Mode Control */ -#define _DPLL_CFG_MODE_SHIFT 0 /**< Shift value for DPLL_MODE */ -#define _DPLL_CFG_MODE_MASK 0x1UL /**< Bit mask for DPLL_MODE */ -#define _DPLL_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ -#define _DPLL_CFG_MODE_FLL 0x00000000UL /**< Mode FLL for DPLL_CFG */ -#define _DPLL_CFG_MODE_PLL 0x00000001UL /**< Mode PLL for DPLL_CFG */ -#define DPLL_CFG_MODE_DEFAULT (_DPLL_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_MODE_FLL (_DPLL_CFG_MODE_FLL << 0) /**< Shifted mode FLL for DPLL_CFG */ -#define DPLL_CFG_MODE_PLL (_DPLL_CFG_MODE_PLL << 0) /**< Shifted mode PLL for DPLL_CFG */ -#define DPLL_CFG_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ -#define _DPLL_CFG_EDGESEL_SHIFT 1 /**< Shift value for DPLL_EDGESEL */ -#define _DPLL_CFG_EDGESEL_MASK 0x2UL /**< Bit mask for DPLL_EDGESEL */ -#define _DPLL_CFG_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_EDGESEL_DEFAULT (_DPLL_CFG_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Control */ -#define _DPLL_CFG_AUTORECOVER_SHIFT 2 /**< Shift value for DPLL_AUTORECOVER */ -#define _DPLL_CFG_AUTORECOVER_MASK 0x4UL /**< Bit mask for DPLL_AUTORECOVER */ -#define _DPLL_CFG_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_AUTORECOVER_DEFAULT (_DPLL_CFG_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_DITHEN (0x1UL << 6) /**< Dither Enable Control */ -#define _DPLL_CFG_DITHEN_SHIFT 6 /**< Shift value for DPLL_DITHEN */ -#define _DPLL_CFG_DITHEN_MASK 0x40UL /**< Bit mask for DPLL_DITHEN */ -#define _DPLL_CFG_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_DITHEN_DEFAULT (_DPLL_CFG_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define _DPLL_CFG_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG */ +#define _DPLL_CFG_MASK 0x00000047UL /**< Mask for DPLL_CFG */ +#define DPLL_CFG_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _DPLL_CFG_MODE_SHIFT 0 /**< Shift value for DPLL_MODE */ +#define _DPLL_CFG_MODE_MASK 0x1UL /**< Bit mask for DPLL_MODE */ +#define _DPLL_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define _DPLL_CFG_MODE_FLL 0x00000000UL /**< Mode FLL for DPLL_CFG */ +#define _DPLL_CFG_MODE_PLL 0x00000001UL /**< Mode PLL for DPLL_CFG */ +#define DPLL_CFG_MODE_DEFAULT (_DPLL_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_MODE_FLL (_DPLL_CFG_MODE_FLL << 0) /**< Shifted mode FLL for DPLL_CFG */ +#define DPLL_CFG_MODE_PLL (_DPLL_CFG_MODE_PLL << 0) /**< Shifted mode PLL for DPLL_CFG */ +#define DPLL_CFG_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _DPLL_CFG_EDGESEL_SHIFT 1 /**< Shift value for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_MASK 0x2UL /**< Bit mask for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_EDGESEL_DEFAULT (_DPLL_CFG_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Control */ +#define _DPLL_CFG_AUTORECOVER_SHIFT 2 /**< Shift value for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_MASK 0x4UL /**< Bit mask for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER_DEFAULT (_DPLL_CFG_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _DPLL_CFG_DITHEN_SHIFT 6 /**< Shift value for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_MASK 0x40UL /**< Bit mask for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN_DEFAULT (_DPLL_CFG_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for DPLL_CFG */ /* Bit fields for DPLL CFG1 */ -#define _DPLL_CFG1_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG1 */ -#define _DPLL_CFG1_MASK 0x0FFF0FFFUL /**< Mask for DPLL_CFG1 */ -#define _DPLL_CFG1_M_SHIFT 0 /**< Shift value for DPLL_M */ -#define _DPLL_CFG1_M_MASK 0xFFFUL /**< Bit mask for DPLL_M */ -#define _DPLL_CFG1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ -#define DPLL_CFG1_M_DEFAULT (_DPLL_CFG1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG1 */ -#define _DPLL_CFG1_N_SHIFT 16 /**< Shift value for DPLL_N */ -#define _DPLL_CFG1_N_MASK 0xFFF0000UL /**< Bit mask for DPLL_N */ -#define _DPLL_CFG1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ -#define DPLL_CFG1_N_DEFAULT (_DPLL_CFG1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for DPLL_CFG1 */ +#define _DPLL_CFG1_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG1 */ +#define _DPLL_CFG1_MASK 0x0FFF0FFFUL /**< Mask for DPLL_CFG1 */ +#define _DPLL_CFG1_M_SHIFT 0 /**< Shift value for DPLL_M */ +#define _DPLL_CFG1_M_MASK 0xFFFUL /**< Bit mask for DPLL_M */ +#define _DPLL_CFG1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_M_DEFAULT (_DPLL_CFG1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG1 */ +#define _DPLL_CFG1_N_SHIFT 16 /**< Shift value for DPLL_N */ +#define _DPLL_CFG1_N_MASK 0xFFF0000UL /**< Bit mask for DPLL_N */ +#define _DPLL_CFG1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_N_DEFAULT (_DPLL_CFG1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for DPLL_CFG1 */ /* Bit fields for DPLL IF */ -#define _DPLL_IF_RESETVALUE 0x00000000UL /**< Default value for DPLL_IF */ -#define _DPLL_IF_MASK 0x00000007UL /**< Mask for DPLL_IF */ -#define DPLL_IF_LOCK (0x1UL << 0) /**< Lock Interrupt Flag */ -#define _DPLL_IF_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ -#define _DPLL_IF_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ -#define _DPLL_IF_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCK_DEFAULT (_DPLL_IF_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCKFAILLOW (0x1UL << 1) /**< Lock Failure Low Interrupt Flag */ -#define _DPLL_IF_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ -#define _DPLL_IF_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ -#define _DPLL_IF_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCKFAILLOW_DEFAULT (_DPLL_IF_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCKFAILHIGH (0x1UL << 2) /**< Lock Failure High Interrupt Flag */ -#define _DPLL_IF_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ -#define _DPLL_IF_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ -#define _DPLL_IF_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCKFAILHIGH_DEFAULT (_DPLL_IF_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IF */ +#define _DPLL_IF_RESETVALUE 0x00000000UL /**< Default value for DPLL_IF */ +#define _DPLL_IF_MASK 0x00000007UL /**< Mask for DPLL_IF */ +#define DPLL_IF_LOCK (0x1UL << 0) /**< Lock Interrupt Flag */ +#define _DPLL_IF_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IF_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IF_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCK_DEFAULT (_DPLL_IF_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW (0x1UL << 1) /**< Lock Failure Low Interrupt Flag */ +#define _DPLL_IF_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW_DEFAULT (_DPLL_IF_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH (0x1UL << 2) /**< Lock Failure High Interrupt Flag */ +#define _DPLL_IF_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH_DEFAULT (_DPLL_IF_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IF */ /* Bit fields for DPLL IEN */ -#define _DPLL_IEN_RESETVALUE 0x00000000UL /**< Default value for DPLL_IEN */ -#define _DPLL_IEN_MASK 0x00000007UL /**< Mask for DPLL_IEN */ -#define DPLL_IEN_LOCK (0x1UL << 0) /**< LOCK interrupt Enable */ -#define _DPLL_IEN_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ -#define _DPLL_IEN_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ -#define _DPLL_IEN_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCK_DEFAULT (_DPLL_IEN_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCKFAILLOW (0x1UL << 1) /**< LOCKFAILLOW Interrupe Enable */ -#define _DPLL_IEN_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ -#define _DPLL_IEN_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ -#define _DPLL_IEN_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCKFAILLOW_DEFAULT (_DPLL_IEN_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCKFAILHIGH (0x1UL << 2) /**< LOCKFAILHIGH Interrupt Enable */ -#define _DPLL_IEN_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ -#define _DPLL_IEN_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ -#define _DPLL_IEN_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCKFAILHIGH_DEFAULT (_DPLL_IEN_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define _DPLL_IEN_RESETVALUE 0x00000000UL /**< Default value for DPLL_IEN */ +#define _DPLL_IEN_MASK 0x00000007UL /**< Mask for DPLL_IEN */ +#define DPLL_IEN_LOCK (0x1UL << 0) /**< LOCK interrupt Enable */ +#define _DPLL_IEN_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCK_DEFAULT (_DPLL_IEN_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW (0x1UL << 1) /**< LOCKFAILLOW Interrupe Enable */ +#define _DPLL_IEN_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW_DEFAULT (_DPLL_IEN_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH (0x1UL << 2) /**< LOCKFAILHIGH Interrupt Enable */ +#define _DPLL_IEN_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH_DEFAULT (_DPLL_IEN_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IEN */ /* Bit fields for DPLL STATUS */ -#define _DPLL_STATUS_RESETVALUE 0x00000000UL /**< Default value for DPLL_STATUS */ -#define _DPLL_STATUS_MASK 0x80000003UL /**< Mask for DPLL_STATUS */ -#define DPLL_STATUS_RDY (0x1UL << 0) /**< Ready Status */ -#define _DPLL_STATUS_RDY_SHIFT 0 /**< Shift value for DPLL_RDY */ -#define _DPLL_STATUS_RDY_MASK 0x1UL /**< Bit mask for DPLL_RDY */ -#define _DPLL_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_RDY_DEFAULT (_DPLL_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_ENS (0x1UL << 1) /**< Enable Status */ -#define _DPLL_STATUS_ENS_SHIFT 1 /**< Shift value for DPLL_ENS */ -#define _DPLL_STATUS_ENS_MASK 0x2UL /**< Bit mask for DPLL_ENS */ -#define _DPLL_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_ENS_DEFAULT (_DPLL_STATUS_ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ -#define _DPLL_STATUS_LOCK_SHIFT 31 /**< Shift value for DPLL_LOCK */ -#define _DPLL_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for DPLL_LOCK */ -#define _DPLL_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ -#define _DPLL_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DPLL_STATUS */ -#define _DPLL_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DPLL_STATUS */ -#define DPLL_STATUS_LOCK_DEFAULT (_DPLL_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_LOCK_UNLOCKED (_DPLL_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for DPLL_STATUS */ -#define DPLL_STATUS_LOCK_LOCKED (_DPLL_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for DPLL_STATUS */ +#define _DPLL_STATUS_RESETVALUE 0x00000000UL /**< Default value for DPLL_STATUS */ +#define _DPLL_STATUS_MASK 0x80000003UL /**< Mask for DPLL_STATUS */ +#define DPLL_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _DPLL_STATUS_RDY_SHIFT 0 /**< Shift value for DPLL_RDY */ +#define _DPLL_STATUS_RDY_MASK 0x1UL /**< Bit mask for DPLL_RDY */ +#define _DPLL_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_RDY_DEFAULT (_DPLL_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS (0x1UL << 1) /**< Enable Status */ +#define _DPLL_STATUS_ENS_SHIFT 1 /**< Shift value for DPLL_ENS */ +#define _DPLL_STATUS_ENS_MASK 0x2UL /**< Bit mask for DPLL_ENS */ +#define _DPLL_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS_DEFAULT (_DPLL_STATUS_ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _DPLL_STATUS_LOCK_SHIFT 31 /**< Shift value for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_DEFAULT (_DPLL_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_UNLOCKED (_DPLL_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_LOCKED (_DPLL_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for DPLL_STATUS */ /* Bit fields for DPLL LOCK */ -#define _DPLL_LOCK_RESETVALUE 0x00007102UL /**< Default value for DPLL_LOCK */ -#define _DPLL_LOCK_MASK 0x0000FFFFUL /**< Mask for DPLL_LOCK */ -#define _DPLL_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DPLL_LOCKKEY */ -#define _DPLL_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DPLL_LOCKKEY */ -#define _DPLL_LOCK_LOCKKEY_DEFAULT 0x00007102UL /**< Mode DEFAULT for DPLL_LOCK */ -#define _DPLL_LOCK_LOCKKEY_UNLOCK 0x00007102UL /**< Mode UNLOCK for DPLL_LOCK */ -#define DPLL_LOCK_LOCKKEY_DEFAULT (_DPLL_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_LOCK */ -#define DPLL_LOCK_LOCKKEY_UNLOCK (_DPLL_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for DPLL_LOCK */ +#define _DPLL_LOCK_RESETVALUE 0x00007102UL /**< Default value for DPLL_LOCK */ +#define _DPLL_LOCK_MASK 0x0000FFFFUL /**< Mask for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_DEFAULT 0x00007102UL /**< Mode DEFAULT for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_UNLOCK 0x00007102UL /**< Mode UNLOCK for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_DEFAULT (_DPLL_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_UNLOCK (_DPLL_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for DPLL_LOCK */ /** @} End of group EFR32SG28_DPLL_BitFields */ /** @} End of group EFR32SG28_DPLL */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_emu.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_emu.h index 55f77eac81..095da256db 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_emu.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_emu.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_EMU_H #define EFR32SG28_EMU_H - #define EMU_HAS_SET_CLEAR /**************************************************************************//** @@ -43,151 +42,150 @@ *****************************************************************************/ /** EMU Register Declaration. */ -typedef struct -{ - uint32_t RESERVED0[4U]; /**< Reserved for future use */ - __IOM uint32_t DECBOD; /**< DECOUPLE LVBOD Control register */ - uint32_t RESERVED1[3U]; /**< Reserved for future use */ - __IOM uint32_t BOD3SENSE; /**< BOD3SENSE Control register */ - uint32_t RESERVED2[6U]; /**< Reserved for future use */ - __IOM uint32_t VREGVDDCMPCTRL; /**< DC-DC VREGVDD Comparator Control Register */ - __IOM uint32_t PD1PARETCTRL; /**< PD1 Partial Retention Control */ - uint32_t RESERVED3[6U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION; /**< IP Version */ - __IOM uint32_t LOCK; /**< EMU Configuration lock register */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enables */ - __IOM uint32_t EM4CTRL; /**< EM4 Control */ - __IOM uint32_t CMD; /**< EMU Command register */ - __IOM uint32_t CTRL; /**< EMU Control register */ - __IOM uint32_t TEMPLIMITS; /**< EMU Temperature thresholds */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< EMU Status register */ - __IM uint32_t TEMP; /**< Temperature */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IOM uint32_t RSTCTRL; /**< Reset Management Control register */ - __IM uint32_t RSTCAUSE; /**< Reset cause */ - __IM uint32_t TAMPERRSTCAUSE; /**< Tamper Reset cause */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IOM uint32_t DGIF; /**< Interrupt Flags Debug */ - __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */ - uint32_t RESERVED7[6U]; /**< Reserved for future use */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - uint32_t RESERVED9[15U]; /**< Reserved for future use */ - __IOM uint32_t EFPIF; /**< EFP Interrupt Register */ - __IOM uint32_t EFPIEN; /**< EFP Interrupt Enable Register */ - uint32_t RESERVED10[14U]; /**< Reserved for future use */ - uint32_t RESERVED11[1U]; /**< Reserved for future use */ - uint32_t RESERVED12[18U]; /**< Reserved for future use */ - uint32_t RESERVED13[1U]; /**< Reserved for future use */ - uint32_t RESERVED14[924U]; /**< Reserved for future use */ - uint32_t RESERVED15[4U]; /**< Reserved for future use */ - __IOM uint32_t DECBOD_SET; /**< DECOUPLE LVBOD Control register */ - uint32_t RESERVED16[3U]; /**< Reserved for future use */ - __IOM uint32_t BOD3SENSE_SET; /**< BOD3SENSE Control register */ - uint32_t RESERVED17[6U]; /**< Reserved for future use */ - __IOM uint32_t VREGVDDCMPCTRL_SET; /**< DC-DC VREGVDD Comparator Control Register */ - __IOM uint32_t PD1PARETCTRL_SET; /**< PD1 Partial Retention Control */ - uint32_t RESERVED18[6U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - __IOM uint32_t LOCK_SET; /**< EMU Configuration lock register */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enables */ - __IOM uint32_t EM4CTRL_SET; /**< EM4 Control */ - __IOM uint32_t CMD_SET; /**< EMU Command register */ - __IOM uint32_t CTRL_SET; /**< EMU Control register */ - __IOM uint32_t TEMPLIMITS_SET; /**< EMU Temperature thresholds */ - uint32_t RESERVED19[2U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< EMU Status register */ - __IM uint32_t TEMP_SET; /**< Temperature */ - uint32_t RESERVED20[1U]; /**< Reserved for future use */ - __IOM uint32_t RSTCTRL_SET; /**< Reset Management Control register */ - __IM uint32_t RSTCAUSE_SET; /**< Reset cause */ - __IM uint32_t TAMPERRSTCAUSE_SET; /**< Tamper Reset cause */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */ - __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */ - uint32_t RESERVED22[6U]; /**< Reserved for future use */ - uint32_t RESERVED23[1U]; /**< Reserved for future use */ - uint32_t RESERVED24[15U]; /**< Reserved for future use */ - __IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */ - __IOM uint32_t EFPIEN_SET; /**< EFP Interrupt Enable Register */ - uint32_t RESERVED25[14U]; /**< Reserved for future use */ - uint32_t RESERVED26[1U]; /**< Reserved for future use */ - uint32_t RESERVED27[18U]; /**< Reserved for future use */ - uint32_t RESERVED28[1U]; /**< Reserved for future use */ - uint32_t RESERVED29[924U]; /**< Reserved for future use */ - uint32_t RESERVED30[4U]; /**< Reserved for future use */ - __IOM uint32_t DECBOD_CLR; /**< DECOUPLE LVBOD Control register */ - uint32_t RESERVED31[3U]; /**< Reserved for future use */ - __IOM uint32_t BOD3SENSE_CLR; /**< BOD3SENSE Control register */ - uint32_t RESERVED32[6U]; /**< Reserved for future use */ - __IOM uint32_t VREGVDDCMPCTRL_CLR; /**< DC-DC VREGVDD Comparator Control Register */ - __IOM uint32_t PD1PARETCTRL_CLR; /**< PD1 Partial Retention Control */ - uint32_t RESERVED33[6U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - __IOM uint32_t LOCK_CLR; /**< EMU Configuration lock register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ - __IOM uint32_t EM4CTRL_CLR; /**< EM4 Control */ - __IOM uint32_t CMD_CLR; /**< EMU Command register */ - __IOM uint32_t CTRL_CLR; /**< EMU Control register */ - __IOM uint32_t TEMPLIMITS_CLR; /**< EMU Temperature thresholds */ - uint32_t RESERVED34[2U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< EMU Status register */ - __IM uint32_t TEMP_CLR; /**< Temperature */ - uint32_t RESERVED35[1U]; /**< Reserved for future use */ - __IOM uint32_t RSTCTRL_CLR; /**< Reset Management Control register */ - __IM uint32_t RSTCAUSE_CLR; /**< Reset cause */ - __IM uint32_t TAMPERRSTCAUSE_CLR; /**< Tamper Reset cause */ - uint32_t RESERVED36[1U]; /**< Reserved for future use */ - __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */ - __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */ - uint32_t RESERVED37[6U]; /**< Reserved for future use */ - uint32_t RESERVED38[1U]; /**< Reserved for future use */ - uint32_t RESERVED39[15U]; /**< Reserved for future use */ - __IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */ - __IOM uint32_t EFPIEN_CLR; /**< EFP Interrupt Enable Register */ - uint32_t RESERVED40[14U]; /**< Reserved for future use */ - uint32_t RESERVED41[1U]; /**< Reserved for future use */ - uint32_t RESERVED42[18U]; /**< Reserved for future use */ - uint32_t RESERVED43[1U]; /**< Reserved for future use */ - uint32_t RESERVED44[924U]; /**< Reserved for future use */ - uint32_t RESERVED45[4U]; /**< Reserved for future use */ - __IOM uint32_t DECBOD_TGL; /**< DECOUPLE LVBOD Control register */ - uint32_t RESERVED46[3U]; /**< Reserved for future use */ - __IOM uint32_t BOD3SENSE_TGL; /**< BOD3SENSE Control register */ - uint32_t RESERVED47[6U]; /**< Reserved for future use */ - __IOM uint32_t VREGVDDCMPCTRL_TGL; /**< DC-DC VREGVDD Comparator Control Register */ - __IOM uint32_t PD1PARETCTRL_TGL; /**< PD1 Partial Retention Control */ - uint32_t RESERVED48[6U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ - __IOM uint32_t LOCK_TGL; /**< EMU Configuration lock register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ - __IOM uint32_t EM4CTRL_TGL; /**< EM4 Control */ - __IOM uint32_t CMD_TGL; /**< EMU Command register */ - __IOM uint32_t CTRL_TGL; /**< EMU Control register */ - __IOM uint32_t TEMPLIMITS_TGL; /**< EMU Temperature thresholds */ - uint32_t RESERVED49[2U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< EMU Status register */ - __IM uint32_t TEMP_TGL; /**< Temperature */ - uint32_t RESERVED50[1U]; /**< Reserved for future use */ - __IOM uint32_t RSTCTRL_TGL; /**< Reset Management Control register */ - __IM uint32_t RSTCAUSE_TGL; /**< Reset cause */ - __IM uint32_t TAMPERRSTCAUSE_TGL; /**< Tamper Reset cause */ - uint32_t RESERVED51[1U]; /**< Reserved for future use */ - __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */ - __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */ - uint32_t RESERVED52[6U]; /**< Reserved for future use */ - uint32_t RESERVED53[1U]; /**< Reserved for future use */ - uint32_t RESERVED54[15U]; /**< Reserved for future use */ - __IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */ - __IOM uint32_t EFPIEN_TGL; /**< EFP Interrupt Enable Register */ - uint32_t RESERVED55[14U]; /**< Reserved for future use */ - uint32_t RESERVED56[1U]; /**< Reserved for future use */ - uint32_t RESERVED57[18U]; /**< Reserved for future use */ - uint32_t RESERVED58[1U]; /**< Reserved for future use */ +typedef struct { + uint32_t RESERVED0[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE; /**< BOD3SENSE Control register */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED3[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t LOCK; /**< EMU Configuration lock register */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL; /**< EM4 Control */ + __IOM uint32_t CMD; /**< EMU Command register */ + __IOM uint32_t CTRL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS; /**< EMU Temperature thresholds */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< EMU Status register */ + __IM uint32_t TEMP; /**< Temperature */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE; /**< Tamper Reset cause */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */ + uint32_t RESERVED7[6U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED10[14U]; /**< Reserved for future use */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[18U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + uint32_t RESERVED14[924U]; /**< Reserved for future use */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_SET; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED16[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_SET; /**< BOD3SENSE Control register */ + uint32_t RESERVED17[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_SET; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_SET; /**< PD1 Partial Retention Control */ + uint32_t RESERVED18[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t LOCK_SET; /**< EMU Configuration lock register */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_SET; /**< EM4 Control */ + __IOM uint32_t CMD_SET; /**< EMU Command register */ + __IOM uint32_t CTRL_SET; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_SET; /**< EMU Temperature thresholds */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< EMU Status register */ + __IM uint32_t TEMP_SET; /**< Temperature */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_SET; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_SET; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_SET; /**< Tamper Reset cause */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */ + uint32_t RESERVED22[6U]; /**< Reserved for future use */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + uint32_t RESERVED24[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_SET; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED25[14U]; /**< Reserved for future use */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + uint32_t RESERVED27[18U]; /**< Reserved for future use */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + uint32_t RESERVED29[924U]; /**< Reserved for future use */ + uint32_t RESERVED30[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_CLR; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED31[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_CLR; /**< BOD3SENSE Control register */ + uint32_t RESERVED32[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_CLR; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_CLR; /**< PD1 Partial Retention Control */ + uint32_t RESERVED33[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t LOCK_CLR; /**< EMU Configuration lock register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_CLR; /**< EM4 Control */ + __IOM uint32_t CMD_CLR; /**< EMU Command register */ + __IOM uint32_t CTRL_CLR; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_CLR; /**< EMU Temperature thresholds */ + uint32_t RESERVED34[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< EMU Status register */ + __IM uint32_t TEMP_CLR; /**< Temperature */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_CLR; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_CLR; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_CLR; /**< Tamper Reset cause */ + uint32_t RESERVED36[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */ + uint32_t RESERVED37[6U]; /**< Reserved for future use */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + uint32_t RESERVED39[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_CLR; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED40[14U]; /**< Reserved for future use */ + uint32_t RESERVED41[1U]; /**< Reserved for future use */ + uint32_t RESERVED42[18U]; /**< Reserved for future use */ + uint32_t RESERVED43[1U]; /**< Reserved for future use */ + uint32_t RESERVED44[924U]; /**< Reserved for future use */ + uint32_t RESERVED45[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_TGL; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED46[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_TGL; /**< BOD3SENSE Control register */ + uint32_t RESERVED47[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_TGL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_TGL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED48[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t LOCK_TGL; /**< EMU Configuration lock register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_TGL; /**< EM4 Control */ + __IOM uint32_t CMD_TGL; /**< EMU Command register */ + __IOM uint32_t CTRL_TGL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_TGL; /**< EMU Temperature thresholds */ + uint32_t RESERVED49[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< EMU Status register */ + __IM uint32_t TEMP_TGL; /**< Temperature */ + uint32_t RESERVED50[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_TGL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_TGL; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_TGL; /**< Tamper Reset cause */ + uint32_t RESERVED51[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */ + uint32_t RESERVED52[6U]; /**< Reserved for future use */ + uint32_t RESERVED53[1U]; /**< Reserved for future use */ + uint32_t RESERVED54[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_TGL; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED55[14U]; /**< Reserved for future use */ + uint32_t RESERVED56[1U]; /**< Reserved for future use */ + uint32_t RESERVED57[18U]; /**< Reserved for future use */ + uint32_t RESERVED58[1U]; /**< Reserved for future use */ } EMU_TypeDef; /** @} End of group EFR32SG28_EMU */ @@ -199,580 +197,580 @@ typedef struct *****************************************************************************/ /* Bit fields for EMU DECBOD */ -#define _EMU_DECBOD_RESETVALUE 0x00000022UL /**< Default value for EMU_DECBOD */ -#define _EMU_DECBOD_MASK 0x00000033UL /**< Mask for EMU_DECBOD */ -#define EMU_DECBOD_DECBODEN (0x1UL << 0) /**< DECBOD enable */ -#define _EMU_DECBOD_DECBODEN_SHIFT 0 /**< Shift value for EMU_DECBODEN */ -#define _EMU_DECBOD_DECBODEN_MASK 0x1UL /**< Bit mask for EMU_DECBODEN */ -#define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECBODEN_DEFAULT (_EMU_DECBOD_DECBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECBODMASK (0x1UL << 1) /**< DECBOD Mask */ -#define _EMU_DECBOD_DECBODMASK_SHIFT 1 /**< Shift value for EMU_DECBODMASK */ -#define _EMU_DECBOD_DECBODMASK_MASK 0x2UL /**< Bit mask for EMU_DECBODMASK */ -#define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECBODMASK_DEFAULT (_EMU_DECBOD_DECBODMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECOVMBODEN (0x1UL << 4) /**< Over Voltage Monitor enable */ -#define _EMU_DECBOD_DECOVMBODEN_SHIFT 4 /**< Shift value for EMU_DECOVMBODEN */ -#define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL /**< Bit mask for EMU_DECOVMBODEN */ -#define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECOVMBODEN_DEFAULT (_EMU_DECBOD_DECOVMBODEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5) /**< Over Voltage Monitor Mask */ -#define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5 /**< Shift value for EMU_DECOVMBODMASK */ -#define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL /**< Bit mask for EMU_DECOVMBODMASK */ -#define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECOVMBODMASK_DEFAULT (_EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define _EMU_DECBOD_RESETVALUE 0x00000022UL /**< Default value for EMU_DECBOD */ +#define _EMU_DECBOD_MASK 0x00000033UL /**< Mask for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN (0x1UL << 0) /**< DECBOD enable */ +#define _EMU_DECBOD_DECBODEN_SHIFT 0 /**< Shift value for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_MASK 0x1UL /**< Bit mask for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN_DEFAULT (_EMU_DECBOD_DECBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK (0x1UL << 1) /**< DECBOD Mask */ +#define _EMU_DECBOD_DECBODMASK_SHIFT 1 /**< Shift value for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_MASK 0x2UL /**< Bit mask for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK_DEFAULT (_EMU_DECBOD_DECBODMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN (0x1UL << 4) /**< Over Voltage Monitor enable */ +#define _EMU_DECBOD_DECOVMBODEN_SHIFT 4 /**< Shift value for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL /**< Bit mask for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN_DEFAULT (_EMU_DECBOD_DECOVMBODEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5) /**< Over Voltage Monitor Mask */ +#define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5 /**< Shift value for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL /**< Bit mask for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK_DEFAULT (_EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DECBOD */ /* Bit fields for EMU BOD3SENSE */ -#define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL /**< Default value for EMU_BOD3SENSE */ -#define _EMU_BOD3SENSE_MASK 0x00000077UL /**< Mask for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0) /**< AVDD BOD enable */ -#define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0 /**< Shift value for EMU_AVDDBODEN */ -#define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL /**< Bit mask for EMU_AVDDBODEN */ -#define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_AVDDBODEN_DEFAULT (_EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_VDDIO0BODEN (0x1UL << 1) /**< VDDIO0 BOD enable */ -#define _EMU_BOD3SENSE_VDDIO0BODEN_SHIFT 1 /**< Shift value for EMU_VDDIO0BODEN */ -#define _EMU_BOD3SENSE_VDDIO0BODEN_MASK 0x2UL /**< Bit mask for EMU_VDDIO0BODEN */ -#define _EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_VDDIO1BODEN (0x1UL << 2) /**< VDDIO1 BOD enable */ -#define _EMU_BOD3SENSE_VDDIO1BODEN_SHIFT 2 /**< Shift value for EMU_VDDIO1BODEN */ -#define _EMU_BOD3SENSE_VDDIO1BODEN_MASK 0x4UL /**< Bit mask for EMU_VDDIO1BODEN */ -#define _EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL /**< Default value for EMU_BOD3SENSE */ +#define _EMU_BOD3SENSE_MASK 0x00000077UL /**< Mask for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0) /**< AVDD BOD enable */ +#define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0 /**< Shift value for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL /**< Bit mask for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN_DEFAULT (_EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN (0x1UL << 1) /**< VDDIO0 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_SHIFT 1 /**< Shift value for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_MASK 0x2UL /**< Bit mask for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN (0x1UL << 2) /**< VDDIO1 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_SHIFT 2 /**< Shift value for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_MASK 0x4UL /**< Bit mask for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ /* Bit fields for EMU VREGVDDCMPCTRL */ -#define _EMU_VREGVDDCMPCTRL_RESETVALUE 0x00000006UL /**< Default value for EMU_VREGVDDCMPCTRL */ -#define _EMU_VREGVDDCMPCTRL_MASK 0x00000007UL /**< Mask for EMU_VREGVDDCMPCTRL */ -#define EMU_VREGVDDCMPCTRL_VREGINCMPEN (0x1UL << 0) /**< VREGVDD comparator enable */ -#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_SHIFT 0 /**< Shift value for EMU_VREGINCMPEN */ -#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_MASK 0x1UL /**< Bit mask for EMU_VREGINCMPEN */ -#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ -#define EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT (_EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ -#define _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT 1 /**< Shift value for EMU_THRESSEL */ -#define _EMU_VREGVDDCMPCTRL_THRESSEL_MASK 0x6UL /**< Bit mask for EMU_THRESSEL */ -#define _EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ -#define EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT (_EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_RESETVALUE 0x00000006UL /**< Default value for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_MASK 0x00000007UL /**< Mask for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN (0x1UL << 0) /**< VREGVDD comparator enable */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_SHIFT 0 /**< Shift value for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_MASK 0x1UL /**< Bit mask for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT (_EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT 1 /**< Shift value for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_MASK 0x6UL /**< Bit mask for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT (_EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ /* Bit fields for EMU PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_SHIFT 0 /**< Shift value for EMU_PD1PARETDIS */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_MASK 0xFFFFUL /**< Bit mask for EMU_PD1PARETDIS */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN 0x00000001UL /**< Mode PERIPHNORETAIN for EMU_PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN 0x00000002UL /**< Mode RADIONORETAIN for EMU_PD1PARETCTRL */ -#define EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT (_EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PD1PARETCTRL */ -#define EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN << 0) /**< Shifted mode PERIPHNORETAIN for EMU_PD1PARETCTRL*/ -#define EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN << 0) /**< Shifted mode RADIONORETAIN for EMU_PD1PARETCTRL*/ +#define _EMU_PD1PARETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_SHIFT 0 /**< Shift value for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_MASK 0xFFFFUL /**< Bit mask for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN 0x00000001UL /**< Mode PERIPHNORETAIN for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN 0x00000002UL /**< Mode RADIONORETAIN for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT (_EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN << 0) /**< Shifted mode PERIPHNORETAIN for EMU_PD1PARETCTRL*/ +#define EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN << 0) /**< Shifted mode RADIONORETAIN for EMU_PD1PARETCTRL*/ /* Bit fields for EMU IPVERSION */ -#define _EMU_IPVERSION_RESETVALUE 0x00000007UL /**< Default value for EMU_IPVERSION */ -#define _EMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EMU_IPVERSION */ -#define _EMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EMU_IPVERSION */ -#define _EMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_IPVERSION */ -#define _EMU_IPVERSION_IPVERSION_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_IPVERSION */ -#define EMU_IPVERSION_IPVERSION_DEFAULT (_EMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IPVERSION */ +#define _EMU_IPVERSION_RESETVALUE 0x00000007UL /**< Default value for EMU_IPVERSION */ +#define _EMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_IPVERSION */ +#define EMU_IPVERSION_IPVERSION_DEFAULT (_EMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IPVERSION */ /* Bit fields for EMU LOCK */ -#define _EMU_LOCK_RESETVALUE 0x0000ADE8UL /**< Default value for EMU_LOCK */ -#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ -#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ -#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ -#define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL /**< Mode DEFAULT for EMU_LOCK */ -#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ -#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ -#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ +#define _EMU_LOCK_RESETVALUE 0x0000ADE8UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ /* Bit fields for EMU IF */ -#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ -#define _EMU_IF_MASK 0xEB070000UL /**< Mask for EMU_IF */ -#define EMU_IF_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt flag */ -#define _EMU_IF_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ -#define _EMU_IF_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ -#define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_AVDDBOD_DEFAULT (_EMU_IF_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt flag */ -#define _EMU_IF_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ -#define _EMU_IF_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ -#define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_IOVDD0BOD_DEFAULT (_EMU_IF_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ -#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ -#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ -#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt flag */ -#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ -#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ -#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPAVG (0x1UL << 27) /**< Temperature Average Interrupt flag */ -#define _EMU_IF_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ -#define _EMU_IF_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ -#define _EMU_IF_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPAVG_DEFAULT (_EMU_IF_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ -#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ -#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ -#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */ -#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ -#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ -#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */ -#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ -#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ -#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xEB070000UL /**< Mask for EMU_IF */ +#define EMU_IF_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt flag */ +#define _EMU_IF_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_AVDDBOD_DEFAULT (_EMU_IF_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt flag */ +#define _EMU_IF_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD_DEFAULT (_EMU_IF_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt flag */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG (0x1UL << 27) /**< Temperature Average Interrupt flag */ +#define _EMU_IF_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG_DEFAULT (_EMU_IF_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ /* Bit fields for EMU IEN */ -#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ -#define _EMU_IEN_MASK 0xEB070000UL /**< Mask for EMU_IEN */ -#define EMU_IEN_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt enable */ -#define _EMU_IEN_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ -#define _EMU_IEN_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ -#define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_AVDDBOD_DEFAULT (_EMU_IEN_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt enable */ -#define _EMU_IEN_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ -#define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ -#define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_IOVDD0BOD_DEFAULT (_EMU_IEN_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ -#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ -#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ -#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt enable */ -#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ -#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ -#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPAVG (0x1UL << 27) /**< Temperature Interrupt enable */ -#define _EMU_IEN_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ -#define _EMU_IEN_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ -#define _EMU_IEN_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPAVG_DEFAULT (_EMU_IEN_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ -#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ -#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ -#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ -#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ -#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ -#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ -#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ -#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ -#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xEB070000UL /**< Mask for EMU_IEN */ +#define EMU_IEN_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt enable */ +#define _EMU_IEN_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_AVDDBOD_DEFAULT (_EMU_IEN_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt enable */ +#define _EMU_IEN_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD_DEFAULT (_EMU_IEN_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG (0x1UL << 27) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG_DEFAULT (_EMU_IEN_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ /* Bit fields for EMU EM4CTRL */ -#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_MASK 0x00000133UL /**< Mask for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0 /**< Shift value for EMU_EM4ENTRY */ -#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL /**< Bit mask for EMU_EM4ENTRY */ -#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ -#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ -#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ -#define EMU_EM4CTRL_BOD3SENSEEM4WU (0x1UL << 8) /**< Set BOD3SENSE as EM4 wakeup */ -#define _EMU_EM4CTRL_BOD3SENSEEM4WU_SHIFT 8 /**< Shift value for EMU_BOD3SENSEEM4WU */ -#define _EMU_EM4CTRL_BOD3SENSEEM4WU_MASK 0x100UL /**< Bit mask for EMU_BOD3SENSEEM4WU */ -#define _EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ -#define EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT (_EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x00000133UL /**< Mask for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU (0x1UL << 8) /**< Set BOD3SENSE as EM4 wakeup */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_SHIFT 8 /**< Shift value for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_MASK 0x100UL /**< Bit mask for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT (_EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ /* Bit fields for EMU CMD */ -#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ -#define _EMU_CMD_MASK 0x00060E12UL /**< Mask for EMU_CMD */ -#define EMU_CMD_EM4UNLATCH (0x1UL << 1) /**< EM4 unlatch */ -#define _EMU_CMD_EM4UNLATCH_SHIFT 1 /**< Shift value for EMU_EM4UNLATCH */ -#define _EMU_CMD_EM4UNLATCH_MASK 0x2UL /**< Bit mask for EMU_EM4UNLATCH */ -#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_TEMPAVGREQ (0x1UL << 4) /**< Temperature Average Request */ -#define _EMU_CMD_TEMPAVGREQ_SHIFT 4 /**< Shift value for EMU_TEMPAVGREQ */ -#define _EMU_CMD_TEMPAVGREQ_MASK 0x10UL /**< Bit mask for EMU_TEMPAVGREQ */ -#define _EMU_CMD_TEMPAVGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_TEMPAVGREQ_DEFAULT (_EMU_CMD_TEMPAVGREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM01VSCALE1 (0x1UL << 10) /**< Scale voltage to Vscale1 */ -#define _EMU_CMD_EM01VSCALE1_SHIFT 10 /**< Shift value for EMU_EM01VSCALE1 */ -#define _EMU_CMD_EM01VSCALE1_MASK 0x400UL /**< Bit mask for EMU_EM01VSCALE1 */ -#define _EMU_CMD_EM01VSCALE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM01VSCALE1_DEFAULT (_EMU_CMD_EM01VSCALE1_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM01VSCALE2 (0x1UL << 11) /**< Scale voltage to Vscale2 */ -#define _EMU_CMD_EM01VSCALE2_SHIFT 11 /**< Shift value for EMU_EM01VSCALE2 */ -#define _EMU_CMD_EM01VSCALE2_MASK 0x800UL /**< Bit mask for EMU_EM01VSCALE2 */ -#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_RSTCAUSECLR (0x1UL << 17) /**< Reset Cause Clear */ -#define _EMU_CMD_RSTCAUSECLR_SHIFT 17 /**< Shift value for EMU_RSTCAUSECLR */ -#define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL /**< Bit mask for EMU_RSTCAUSECLR */ -#define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_RSTCAUSECLR_DEFAULT (_EMU_CMD_RSTCAUSECLR_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_TAMPERRCCLR (0x1UL << 18) /**< Tamper Reset Cause Clear */ -#define _EMU_CMD_TAMPERRCCLR_SHIFT 18 /**< Shift value for EMU_TAMPERRCCLR */ -#define _EMU_CMD_TAMPERRCCLR_MASK 0x40000UL /**< Bit mask for EMU_TAMPERRCCLR */ -#define _EMU_CMD_TAMPERRCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_TAMPERRCCLR_DEFAULT (_EMU_CMD_TAMPERRCCLR_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00060E12UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 1) /**< EM4 unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 1 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x2UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ (0x1UL << 4) /**< Temperature Average Request */ +#define _EMU_CMD_TEMPAVGREQ_SHIFT 4 /**< Shift value for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_MASK 0x10UL /**< Bit mask for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ_DEFAULT (_EMU_CMD_TEMPAVGREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1 (0x1UL << 10) /**< Scale voltage to Vscale1 */ +#define _EMU_CMD_EM01VSCALE1_SHIFT 10 /**< Shift value for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_MASK 0x400UL /**< Bit mask for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1_DEFAULT (_EMU_CMD_EM01VSCALE1_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 11) /**< Scale voltage to Vscale2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 11 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x800UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR (0x1UL << 17) /**< Reset Cause Clear */ +#define _EMU_CMD_RSTCAUSECLR_SHIFT 17 /**< Shift value for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL /**< Bit mask for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR_DEFAULT (_EMU_CMD_RSTCAUSECLR_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TAMPERRCCLR (0x1UL << 18) /**< Tamper Reset Cause Clear */ +#define _EMU_CMD_TAMPERRCCLR_SHIFT 18 /**< Shift value for EMU_TAMPERRCCLR */ +#define _EMU_CMD_TAMPERRCCLR_MASK 0x40000UL /**< Bit mask for EMU_TAMPERRCCLR */ +#define _EMU_CMD_TAMPERRCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TAMPERRCCLR_DEFAULT (_EMU_CMD_TAMPERRCCLR_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_CMD */ /* Bit fields for EMU CTRL */ -#define _EMU_CTRL_RESETVALUE 0x00000200UL /**< Default value for EMU_CTRL */ -#define _EMU_CTRL_MASK 0xE0010309UL /**< Mask for EMU_CTRL */ -#define EMU_CTRL_EM2DBGEN (0x1UL << 0) /**< Enable debugging in EM2 */ -#define _EMU_CTRL_EM2DBGEN_SHIFT 0 /**< Shift value for EMU_EM2DBGEN */ -#define _EMU_CTRL_EM2DBGEN_MASK 0x1UL /**< Bit mask for EMU_EM2DBGEN */ -#define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EM2DBGEN_DEFAULT (_EMU_CTRL_EM2DBGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_TEMPAVGNUM (0x1UL << 3) /**< Averaged Temperature samples num */ -#define _EMU_CTRL_TEMPAVGNUM_SHIFT 3 /**< Shift value for EMU_TEMPAVGNUM */ -#define _EMU_CTRL_TEMPAVGNUM_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGNUM */ -#define _EMU_CTRL_TEMPAVGNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define _EMU_CTRL_TEMPAVGNUM_N16 0x00000000UL /**< Mode N16 for EMU_CTRL */ -#define _EMU_CTRL_TEMPAVGNUM_N64 0x00000001UL /**< Mode N64 for EMU_CTRL */ -#define EMU_CTRL_TEMPAVGNUM_DEFAULT (_EMU_CTRL_TEMPAVGNUM_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_TEMPAVGNUM_N16 (_EMU_CTRL_TEMPAVGNUM_N16 << 3) /**< Shifted mode N16 for EMU_CTRL */ -#define EMU_CTRL_TEMPAVGNUM_N64 (_EMU_CTRL_TEMPAVGNUM_N64 << 3) /**< Shifted mode N64 for EMU_CTRL */ -#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ -#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ -#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_CTRL */ -#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_CTRL */ -#define _EMU_CTRL_EM23VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_CTRL */ -#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_CTRL */ -#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ -#define EMU_CTRL_EM23VSCALE_VSCALE1 (_EMU_CTRL_EM23VSCALE_VSCALE1 << 8) /**< Shifted mode VSCALE1 for EMU_CTRL */ -#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ -#define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16) /**< Enable flash on demand wakeup */ -#define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16 /**< Shift value for EMU_FLASHPWRUPONDEMAND */ -#define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL /**< Bit mask for EMU_FLASHPWRUPONDEMAND */ -#define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT (_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDIRECTMODEEN (0x1UL << 29) /**< EFP Direct Mode Enable */ -#define _EMU_CTRL_EFPDIRECTMODEEN_SHIFT 29 /**< Shift value for EMU_EFPDIRECTMODEEN */ -#define _EMU_CTRL_EFPDIRECTMODEEN_MASK 0x20000000UL /**< Bit mask for EMU_EFPDIRECTMODEEN */ -#define _EMU_CTRL_EFPDIRECTMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDIRECTMODEEN_DEFAULT (_EMU_CTRL_EFPDIRECTMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDRVDECOUPLE (0x1UL << 30) /**< EFP drives DECOUPLE */ -#define _EMU_CTRL_EFPDRVDECOUPLE_SHIFT 30 /**< Shift value for EMU_EFPDRVDECOUPLE */ -#define _EMU_CTRL_EFPDRVDECOUPLE_MASK 0x40000000UL /**< Bit mask for EMU_EFPDRVDECOUPLE */ -#define _EMU_CTRL_EFPDRVDECOUPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDRVDECOUPLE_DEFAULT (_EMU_CTRL_EFPDRVDECOUPLE_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDRVDVDD (0x1UL << 31) /**< EFP drives DVDD */ -#define _EMU_CTRL_EFPDRVDVDD_SHIFT 31 /**< Shift value for EMU_EFPDRVDVDD */ -#define _EMU_CTRL_EFPDRVDVDD_MASK 0x80000000UL /**< Bit mask for EMU_EFPDRVDVDD */ -#define _EMU_CTRL_EFPDRVDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDRVDVDD_DEFAULT (_EMU_CTRL_EFPDRVDVDD_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000200UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0xE0010309UL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN (0x1UL << 0) /**< Enable debugging in EM2 */ +#define _EMU_CTRL_EM2DBGEN_SHIFT 0 /**< Shift value for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_MASK 0x1UL /**< Bit mask for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN_DEFAULT (_EMU_CTRL_EM2DBGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM (0x1UL << 3) /**< Averaged Temperature samples num */ +#define _EMU_CTRL_TEMPAVGNUM_SHIFT 3 /**< Shift value for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N16 0x00000000UL /**< Mode N16 for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N64 0x00000001UL /**< Mode N64 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_DEFAULT (_EMU_CTRL_TEMPAVGNUM_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N16 (_EMU_CTRL_TEMPAVGNUM_N16 << 3) /**< Shifted mode N16 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N64 (_EMU_CTRL_TEMPAVGNUM_N64 << 3) /**< Shifted mode N64 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE1 (_EMU_CTRL_EM23VSCALE_VSCALE1 << 8) /**< Shifted mode VSCALE1 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16) /**< Enable flash on demand wakeup */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16 /**< Shift value for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL /**< Bit mask for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT (_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN (0x1UL << 29) /**< EFP Direct Mode Enable */ +#define _EMU_CTRL_EFPDIRECTMODEEN_SHIFT 29 /**< Shift value for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_MASK 0x20000000UL /**< Bit mask for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN_DEFAULT (_EMU_CTRL_EFPDIRECTMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE (0x1UL << 30) /**< EFP drives DECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_SHIFT 30 /**< Shift value for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_MASK 0x40000000UL /**< Bit mask for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE_DEFAULT (_EMU_CTRL_EFPDRVDECOUPLE_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD (0x1UL << 31) /**< EFP drives DVDD */ +#define _EMU_CTRL_EFPDRVDVDD_SHIFT 31 /**< Shift value for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_MASK 0x80000000UL /**< Bit mask for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD_DEFAULT (_EMU_CTRL_EFPDRVDVDD_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_CTRL */ /* Bit fields for EMU TEMPLIMITS */ -#define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL /**< Default value for EMU_TEMPLIMITS */ -#define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL /**< Mask for EMU_TEMPLIMITS */ -#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ -#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL /**< Bit mask for EMU_TEMPLOW */ -#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ -#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ -#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16 /**< Shift value for EMU_TEMPHIGH */ -#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL /**< Bit mask for EMU_TEMPHIGH */ -#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ -#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ /* Bit fields for EMU STATUS */ -#define _EMU_STATUS_RESETVALUE 0x00000080UL /**< Default value for EMU_STATUS */ -#define _EMU_STATUS_MASK 0xFFFFDFFFUL /**< Mask for EMU_STATUS */ -#define EMU_STATUS_LOCK (0x1UL << 0) /**< Lock status */ -#define _EMU_STATUS_LOCK_SHIFT 0 /**< Shift value for EMU_LOCK */ -#define _EMU_STATUS_LOCK_MASK 0x1UL /**< Bit mask for EMU_LOCK */ -#define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_STATUS */ -#define _EMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_STATUS */ -#define EMU_STATUS_LOCK_DEFAULT (_EMU_STATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_LOCK_UNLOCKED (_EMU_STATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_STATUS */ -#define EMU_STATUS_LOCK_LOCKED (_EMU_STATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for EMU_STATUS */ -#define EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1) /**< First Temp done */ -#define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1 /**< Shift value for EMU_FIRSTTEMPDONE */ -#define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL /**< Bit mask for EMU_FIRSTTEMPDONE */ -#define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_FIRSTTEMPDONE_DEFAULT (_EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_TEMPACTIVE (0x1UL << 2) /**< Temp active */ -#define _EMU_STATUS_TEMPACTIVE_SHIFT 2 /**< Shift value for EMU_TEMPACTIVE */ -#define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL /**< Bit mask for EMU_TEMPACTIVE */ -#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_TEMPAVGACTIVE (0x1UL << 3) /**< Temp Average active */ -#define _EMU_STATUS_TEMPAVGACTIVE_SHIFT 3 /**< Shift value for EMU_TEMPAVGACTIVE */ -#define _EMU_STATUS_TEMPAVGACTIVE_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGACTIVE */ -#define _EMU_STATUS_TEMPAVGACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_TEMPAVGACTIVE_DEFAULT (_EMU_STATUS_TEMPAVGACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALEBUSY (0x1UL << 4) /**< Vscale busy */ -#define _EMU_STATUS_VSCALEBUSY_SHIFT 4 /**< Shift value for EMU_VSCALEBUSY */ -#define _EMU_STATUS_VSCALEBUSY_MASK 0x10UL /**< Bit mask for EMU_VSCALEBUSY */ -#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALEFAILED (0x1UL << 5) /**< Vscale failed */ -#define _EMU_STATUS_VSCALEFAILED_SHIFT 5 /**< Shift value for EMU_VSCALEFAILED */ -#define _EMU_STATUS_VSCALEFAILED_MASK 0x20UL /**< Bit mask for EMU_VSCALEFAILED */ -#define _EMU_STATUS_VSCALEFAILED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALEFAILED_DEFAULT (_EMU_STATUS_VSCALEFAILED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define _EMU_STATUS_VSCALE_SHIFT 6 /**< Shift value for EMU_VSCALE */ -#define _EMU_STATUS_VSCALE_MASK 0xC0UL /**< Bit mask for EMU_VSCALE */ -#define _EMU_STATUS_VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_STATUS */ -#define _EMU_STATUS_VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_STATUS */ -#define _EMU_STATUS_VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_STATUS */ -#define _EMU_STATUS_VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_STATUS */ -#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 6) /**< Shifted mode VSCALE0 for EMU_STATUS */ -#define EMU_STATUS_VSCALE_VSCALE1 (_EMU_STATUS_VSCALE_VSCALE1 << 6) /**< Shifted mode VSCALE1 for EMU_STATUS */ -#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 6) /**< Shifted mode VSCALE2 for EMU_STATUS */ -#define EMU_STATUS_RACACTIVE (0x1UL << 10) /**< RAC active */ -#define _EMU_STATUS_RACACTIVE_SHIFT 10 /**< Shift value for EMU_RACACTIVE */ -#define _EMU_STATUS_RACACTIVE_MASK 0x400UL /**< Bit mask for EMU_RACACTIVE */ -#define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_RACACTIVE_DEFAULT (_EMU_STATUS_RACACTIVE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_EM4IORET (0x1UL << 12) /**< EM4 IO retention status */ -#define _EMU_STATUS_EM4IORET_SHIFT 12 /**< Shift value for EMU_EM4IORET */ -#define _EMU_STATUS_EM4IORET_MASK 0x1000UL /**< Bit mask for EMU_EM4IORET */ -#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_EM2ENTERED (0x1UL << 14) /**< EM2 entered */ -#define _EMU_STATUS_EM2ENTERED_SHIFT 14 /**< Shift value for EMU_EM2ENTERED */ -#define _EMU_STATUS_EM2ENTERED_MASK 0x4000UL /**< Bit mask for EMU_EM2ENTERED */ -#define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_EM2ENTERED_DEFAULT (_EMU_STATUS_EM2ENTERED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000080UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0xFFFFDFFFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_LOCK (0x1UL << 0) /**< Lock status */ +#define _EMU_STATUS_LOCK_SHIFT 0 /**< Shift value for EMU_LOCK */ +#define _EMU_STATUS_LOCK_MASK 0x1UL /**< Bit mask for EMU_LOCK */ +#define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_STATUS */ +#define _EMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_DEFAULT (_EMU_STATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_LOCK_UNLOCKED (_EMU_STATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_LOCKED (_EMU_STATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1) /**< First Temp done */ +#define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1 /**< Shift value for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL /**< Bit mask for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE_DEFAULT (_EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 2) /**< Temp active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 2 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE (0x1UL << 3) /**< Temp Average active */ +#define _EMU_STATUS_TEMPAVGACTIVE_SHIFT 3 /**< Shift value for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE_DEFAULT (_EMU_STATUS_TEMPAVGACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 4) /**< Vscale busy */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 4 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x10UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED (0x1UL << 5) /**< Vscale failed */ +#define _EMU_STATUS_VSCALEFAILED_SHIFT 5 /**< Shift value for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_MASK 0x20UL /**< Bit mask for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED_DEFAULT (_EMU_STATUS_VSCALEFAILED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 6 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0xC0UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 6) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE1 (_EMU_STATUS_VSCALE_VSCALE1 << 6) /**< Shifted mode VSCALE1 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 6) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE (0x1UL << 10) /**< RAC active */ +#define _EMU_STATUS_RACACTIVE_SHIFT 10 /**< Shift value for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_MASK 0x400UL /**< Bit mask for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE_DEFAULT (_EMU_STATUS_RACACTIVE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 12) /**< EM4 IO retention status */ +#define _EMU_STATUS_EM4IORET_SHIFT 12 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x1000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED (0x1UL << 14) /**< EM2 entered */ +#define _EMU_STATUS_EM2ENTERED_SHIFT 14 /**< Shift value for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_MASK 0x4000UL /**< Bit mask for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED_DEFAULT (_EMU_STATUS_EM2ENTERED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_STATUS */ /* Bit fields for EMU TEMP */ -#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ -#define _EMU_TEMP_MASK 0x07FF07FFUL /**< Mask for EMU_TEMP */ -#define _EMU_TEMP_TEMPLSB_SHIFT 0 /**< Shift value for EMU_TEMPLSB */ -#define _EMU_TEMP_TEMPLSB_MASK 0x3UL /**< Bit mask for EMU_TEMPLSB */ -#define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ -#define EMU_TEMP_TEMPLSB_DEFAULT (_EMU_TEMP_TEMPLSB_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ -#define _EMU_TEMP_TEMP_SHIFT 2 /**< Shift value for EMU_TEMP */ -#define _EMU_TEMP_TEMP_MASK 0x7FCUL /**< Bit mask for EMU_TEMP */ -#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ -#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_TEMP */ -#define _EMU_TEMP_TEMPAVG_SHIFT 16 /**< Shift value for EMU_TEMPAVG */ -#define _EMU_TEMP_TEMPAVG_MASK 0x7FF0000UL /**< Bit mask for EMU_TEMPAVG */ -#define _EMU_TEMP_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ -#define EMU_TEMP_TEMPAVG_DEFAULT (_EMU_TEMP_TEMPAVG_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x07FF07FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMPLSB_SHIFT 0 /**< Shift value for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_MASK 0x3UL /**< Bit mask for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPLSB_DEFAULT (_EMU_TEMP_TEMPLSB_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 2 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0x7FCUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMPAVG_SHIFT 16 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_MASK 0x7FF0000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPAVG_DEFAULT (_EMU_TEMP_TEMPAVG_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMP */ /* Bit fields for EMU RSTCTRL */ -#define _EMU_RSTCTRL_RESETVALUE 0x00060407UL /**< Default value for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_MASK 0xC006C5CFUL /**< Mask for EMU_RSTCTRL */ -#define EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0) /**< Enable WDOG0 reset */ -#define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0 /**< Shift value for EMU_WDOG0RMODE */ -#define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL /**< Bit mask for EMU_WDOG0RMODE */ -#define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_WDOG0RMODE_DEFAULT (_EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_WDOG0RMODE_DISABLED (_EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_WDOG0RMODE_ENABLED (_EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_SYSRMODE (0x1UL << 2) /**< Enable M33 System reset */ -#define _EMU_RSTCTRL_SYSRMODE_SHIFT 2 /**< Shift value for EMU_SYSRMODE */ -#define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL /**< Bit mask for EMU_SYSRMODE */ -#define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_SYSRMODE_DEFAULT (_EMU_RSTCTRL_SYSRMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_SYSRMODE_DISABLED (_EMU_RSTCTRL_SYSRMODE_DISABLED << 2) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_SYSRMODE_ENABLED (_EMU_RSTCTRL_SYSRMODE_ENABLED << 2) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3) /**< Enable M33 Lockup reset */ -#define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3 /**< Shift value for EMU_LOCKUPRMODE */ -#define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL /**< Bit mask for EMU_LOCKUPRMODE */ -#define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_LOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_LOCKUPRMODE_DISABLED (_EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_LOCKUPRMODE_ENABLED (_EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6) /**< Enable AVDD BOD reset */ -#define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6 /**< Shift value for EMU_AVDDBODRMODE */ -#define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL /**< Bit mask for EMU_AVDDBODRMODE */ -#define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_AVDDBODRMODE_DEFAULT (_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_AVDDBODRMODE_DISABLED (_EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_AVDDBODRMODE_ENABLED (_EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7) /**< Enable VDDIO0 BOD reset */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7 /**< Shift value for EMU_IOVDD0BODRMODE */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL /**< Bit mask for EMU_IOVDD0BODRMODE */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT (_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DECBODRMODE (0x1UL << 10) /**< Enable DECBOD reset */ -#define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10 /**< Shift value for EMU_DECBODRMODE */ -#define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL /**< Bit mask for EMU_DECBODRMODE */ -#define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DECBODRMODE_DEFAULT (_EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DECBODRMODE_DISABLED (_EMU_RSTCTRL_DECBODRMODE_DISABLED << 10) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DECBODRMODE_ENABLED (_EMU_RSTCTRL_DECBODRMODE_ENABLED << 10) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_RESETVALUE 0x00060407UL /**< Default value for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_MASK 0xC006C5CFUL /**< Mask for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0) /**< Enable WDOG0 reset */ +#define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0 /**< Shift value for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL /**< Bit mask for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DEFAULT (_EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DISABLED (_EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_ENABLED (_EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE (0x1UL << 2) /**< Enable M33 System reset */ +#define _EMU_RSTCTRL_SYSRMODE_SHIFT 2 /**< Shift value for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL /**< Bit mask for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DEFAULT (_EMU_RSTCTRL_SYSRMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DISABLED (_EMU_RSTCTRL_SYSRMODE_DISABLED << 2) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_ENABLED (_EMU_RSTCTRL_SYSRMODE_ENABLED << 2) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3) /**< Enable M33 Lockup reset */ +#define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3 /**< Shift value for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL /**< Bit mask for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DISABLED (_EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_ENABLED (_EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6) /**< Enable AVDD BOD reset */ +#define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6 /**< Shift value for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL /**< Bit mask for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DEFAULT (_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DISABLED (_EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_ENABLED (_EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7) /**< Enable VDDIO0 BOD reset */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7 /**< Shift value for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL /**< Bit mask for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT (_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE (0x1UL << 10) /**< Enable DECBOD reset */ +#define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10 /**< Shift value for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL /**< Bit mask for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DEFAULT (_EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DISABLED (_EMU_RSTCTRL_DECBODRMODE_DISABLED << 10) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_ENABLED (_EMU_RSTCTRL_DECBODRMODE_ENABLED << 10) /**< Shifted mode ENABLED for EMU_RSTCTRL */ /* Bit fields for EMU RSTCAUSE */ -#define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_RSTCAUSE */ -#define _EMU_RSTCAUSE_MASK 0x8006FFFFUL /**< Mask for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_POR (0x1UL << 0) /**< Power On Reset */ -#define _EMU_RSTCAUSE_POR_SHIFT 0 /**< Shift value for EMU_POR */ -#define _EMU_RSTCAUSE_POR_MASK 0x1UL /**< Bit mask for EMU_POR */ -#define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_POR_DEFAULT (_EMU_RSTCAUSE_POR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_PIN (0x1UL << 1) /**< Pin Reset */ -#define _EMU_RSTCAUSE_PIN_SHIFT 1 /**< Shift value for EMU_PIN */ -#define _EMU_RSTCAUSE_PIN_MASK 0x2UL /**< Bit mask for EMU_PIN */ -#define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_PIN_DEFAULT (_EMU_RSTCAUSE_PIN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_EM4 (0x1UL << 2) /**< EM4 Wakeup Reset */ -#define _EMU_RSTCAUSE_EM4_SHIFT 2 /**< Shift value for EMU_EM4 */ -#define _EMU_RSTCAUSE_EM4_MASK 0x4UL /**< Bit mask for EMU_EM4 */ -#define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_EM4_DEFAULT (_EMU_RSTCAUSE_EM4_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_WDOG0 (0x1UL << 3) /**< Watchdog 0 Reset */ -#define _EMU_RSTCAUSE_WDOG0_SHIFT 3 /**< Shift value for EMU_WDOG0 */ -#define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL /**< Bit mask for EMU_WDOG0 */ -#define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_WDOG0_DEFAULT (_EMU_RSTCAUSE_WDOG0_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_WDOG1 (0x1UL << 4) /**< Watchdog 1 Reset */ -#define _EMU_RSTCAUSE_WDOG1_SHIFT 4 /**< Shift value for EMU_WDOG1 */ -#define _EMU_RSTCAUSE_WDOG1_MASK 0x10UL /**< Bit mask for EMU_WDOG1 */ -#define _EMU_RSTCAUSE_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_WDOG1_DEFAULT (_EMU_RSTCAUSE_WDOG1_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_LOCKUP (0x1UL << 5) /**< M33 Core Lockup Reset */ -#define _EMU_RSTCAUSE_LOCKUP_SHIFT 5 /**< Shift value for EMU_LOCKUP */ -#define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL /**< Bit mask for EMU_LOCKUP */ -#define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_LOCKUP_DEFAULT (_EMU_RSTCAUSE_LOCKUP_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_SYSREQ (0x1UL << 6) /**< M33 Core Sys Reset */ -#define _EMU_RSTCAUSE_SYSREQ_SHIFT 6 /**< Shift value for EMU_SYSREQ */ -#define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL /**< Bit mask for EMU_SYSREQ */ -#define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_SYSREQ_DEFAULT (_EMU_RSTCAUSE_SYSREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DVDDBOD (0x1UL << 7) /**< HVBOD Reset */ -#define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7 /**< Shift value for EMU_DVDDBOD */ -#define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL /**< Bit mask for EMU_DVDDBOD */ -#define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DVDDBOD_DEFAULT (_EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8) /**< LEBOD Reset */ -#define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8 /**< Shift value for EMU_DVDDLEBOD */ -#define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL /**< Bit mask for EMU_DVDDLEBOD */ -#define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DVDDLEBOD_DEFAULT (_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DECBOD (0x1UL << 9) /**< LVBOD Reset */ -#define _EMU_RSTCAUSE_DECBOD_SHIFT 9 /**< Shift value for EMU_DECBOD */ -#define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL /**< Bit mask for EMU_DECBOD */ -#define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DECBOD_DEFAULT (_EMU_RSTCAUSE_DECBOD_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10) /**< LEBOD1 Reset */ -#define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10 /**< Shift value for EMU_AVDDBOD */ -#define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL /**< Bit mask for EMU_AVDDBOD */ -#define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_AVDDBOD_DEFAULT (_EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11) /**< LEBOD2 Reset */ -#define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11 /**< Shift value for EMU_IOVDD0BOD */ -#define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL /**< Bit mask for EMU_IOVDD0BOD */ -#define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_IOVDD0BOD_DEFAULT (_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_SETAMPER (0x1UL << 13) /**< SE Tamper event Reset */ -#define _EMU_RSTCAUSE_SETAMPER_SHIFT 13 /**< Shift value for EMU_SETAMPER */ -#define _EMU_RSTCAUSE_SETAMPER_MASK 0x2000UL /**< Bit mask for EMU_SETAMPER */ -#define _EMU_RSTCAUSE_SETAMPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_SETAMPER_DEFAULT (_EMU_RSTCAUSE_SETAMPER_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_VREGIN (0x1UL << 31) /**< DCDC VREGIN comparator */ -#define _EMU_RSTCAUSE_VREGIN_SHIFT 31 /**< Shift value for EMU_VREGIN */ -#define _EMU_RSTCAUSE_VREGIN_MASK 0x80000000UL /**< Bit mask for EMU_VREGIN */ -#define _EMU_RSTCAUSE_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_VREGIN_DEFAULT (_EMU_RSTCAUSE_VREGIN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_RSTCAUSE */ +#define _EMU_RSTCAUSE_MASK 0x8006FFFFUL /**< Mask for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR (0x1UL << 0) /**< Power On Reset */ +#define _EMU_RSTCAUSE_POR_SHIFT 0 /**< Shift value for EMU_POR */ +#define _EMU_RSTCAUSE_POR_MASK 0x1UL /**< Bit mask for EMU_POR */ +#define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR_DEFAULT (_EMU_RSTCAUSE_POR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN (0x1UL << 1) /**< Pin Reset */ +#define _EMU_RSTCAUSE_PIN_SHIFT 1 /**< Shift value for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_MASK 0x2UL /**< Bit mask for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN_DEFAULT (_EMU_RSTCAUSE_PIN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4 (0x1UL << 2) /**< EM4 Wakeup Reset */ +#define _EMU_RSTCAUSE_EM4_SHIFT 2 /**< Shift value for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_MASK 0x4UL /**< Bit mask for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4_DEFAULT (_EMU_RSTCAUSE_EM4_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0 (0x1UL << 3) /**< Watchdog 0 Reset */ +#define _EMU_RSTCAUSE_WDOG0_SHIFT 3 /**< Shift value for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL /**< Bit mask for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0_DEFAULT (_EMU_RSTCAUSE_WDOG0_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG1 (0x1UL << 4) /**< Watchdog 1 Reset */ +#define _EMU_RSTCAUSE_WDOG1_SHIFT 4 /**< Shift value for EMU_WDOG1 */ +#define _EMU_RSTCAUSE_WDOG1_MASK 0x10UL /**< Bit mask for EMU_WDOG1 */ +#define _EMU_RSTCAUSE_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG1_DEFAULT (_EMU_RSTCAUSE_WDOG1_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP (0x1UL << 5) /**< M33 Core Lockup Reset */ +#define _EMU_RSTCAUSE_LOCKUP_SHIFT 5 /**< Shift value for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL /**< Bit mask for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP_DEFAULT (_EMU_RSTCAUSE_LOCKUP_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ (0x1UL << 6) /**< M33 Core Sys Reset */ +#define _EMU_RSTCAUSE_SYSREQ_SHIFT 6 /**< Shift value for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL /**< Bit mask for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ_DEFAULT (_EMU_RSTCAUSE_SYSREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD (0x1UL << 7) /**< HVBOD Reset */ +#define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7 /**< Shift value for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL /**< Bit mask for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD_DEFAULT (_EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8) /**< LEBOD Reset */ +#define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8 /**< Shift value for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL /**< Bit mask for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD_DEFAULT (_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD (0x1UL << 9) /**< LVBOD Reset */ +#define _EMU_RSTCAUSE_DECBOD_SHIFT 9 /**< Shift value for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL /**< Bit mask for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD_DEFAULT (_EMU_RSTCAUSE_DECBOD_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10) /**< LEBOD1 Reset */ +#define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD_DEFAULT (_EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11) /**< LEBOD2 Reset */ +#define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD_DEFAULT (_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SETAMPER (0x1UL << 13) /**< SE Tamper event Reset */ +#define _EMU_RSTCAUSE_SETAMPER_SHIFT 13 /**< Shift value for EMU_SETAMPER */ +#define _EMU_RSTCAUSE_SETAMPER_MASK 0x2000UL /**< Bit mask for EMU_SETAMPER */ +#define _EMU_RSTCAUSE_SETAMPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SETAMPER_DEFAULT (_EMU_RSTCAUSE_SETAMPER_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN (0x1UL << 31) /**< DCDC VREGIN comparator */ +#define _EMU_RSTCAUSE_VREGIN_SHIFT 31 /**< Shift value for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_MASK 0x80000000UL /**< Bit mask for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN_DEFAULT (_EMU_RSTCAUSE_VREGIN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ /* Bit fields for EMU TAMPERRSTCAUSE */ -#define _EMU_TAMPERRSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_TAMPERRSTCAUSE */ -#define _EMU_TAMPERRSTCAUSE_MASK 0xFFFFFFFFUL /**< Mask for EMU_TAMPERRSTCAUSE */ -#define _EMU_TAMPERRSTCAUSE_TAMPERRST_SHIFT 0 /**< Shift value for EMU_TAMPERRST */ -#define _EMU_TAMPERRSTCAUSE_TAMPERRST_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_TAMPERRST */ -#define _EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TAMPERRSTCAUSE */ -#define EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT (_EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_MASK 0xFFFFFFFFUL /**< Mask for EMU_TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_SHIFT 0 /**< Shift value for EMU_TAMPERRST */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_TAMPERRST */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TAMPERRSTCAUSE */ +#define EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT (_EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TAMPERRSTCAUSE */ /* Bit fields for EMU DGIF */ -#define _EMU_DGIF_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIF */ -#define _EMU_DGIF_MASK 0xE1000000UL /**< Mask for EMU_DGIF */ -#define EMU_DGIF_EM23WAKEUPDGIF (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ -#define _EMU_DGIF_EM23WAKEUPDGIF_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIF */ -#define _EMU_DGIF_EM23WAKEUPDGIF_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIF */ -#define _EMU_DGIF_EM23WAKEUPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_EM23WAKEUPDGIF_DEFAULT (_EMU_DGIF_EM23WAKEUPDGIF_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPDGIF (0x1UL << 29) /**< Temperature Interrupt flag */ -#define _EMU_DGIF_TEMPDGIF_SHIFT 29 /**< Shift value for EMU_TEMPDGIF */ -#define _EMU_DGIF_TEMPDGIF_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIF */ -#define _EMU_DGIF_TEMPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPDGIF_DEFAULT (_EMU_DGIF_TEMPDGIF_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPLOWDGIF (0x1UL << 30) /**< Temperature low Interrupt flag */ -#define _EMU_DGIF_TEMPLOWDGIF_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIF */ -#define _EMU_DGIF_TEMPLOWDGIF_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIF */ -#define _EMU_DGIF_TEMPLOWDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPLOWDGIF_DEFAULT (_EMU_DGIF_TEMPLOWDGIF_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPHIGHDGIF (0x1UL << 31) /**< Temperature high Interrupt flag */ -#define _EMU_DGIF_TEMPHIGHDGIF_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIF */ -#define _EMU_DGIF_TEMPHIGHDGIF_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIF */ -#define _EMU_DGIF_TEMPHIGHDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPHIGHDGIF_DEFAULT (_EMU_DGIF_TEMPHIGHDGIF_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define _EMU_DGIF_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIF */ +#define _EMU_DGIF_MASK 0xE1000000UL /**< Mask for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_DGIF_EM23WAKEUPDGIF_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF_DEFAULT (_EMU_DGIF_EM23WAKEUPDGIF_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_DGIF_TEMPDGIF_SHIFT 29 /**< Shift value for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF_DEFAULT (_EMU_DGIF_TEMPDGIF_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_DGIF_TEMPLOWDGIF_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF_DEFAULT (_EMU_DGIF_TEMPLOWDGIF_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_DGIF_TEMPHIGHDGIF_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF_DEFAULT (_EMU_DGIF_TEMPHIGHDGIF_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIF */ /* Bit fields for EMU DGIEN */ -#define _EMU_DGIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIEN */ -#define _EMU_DGIEN_MASK 0xE1000000UL /**< Mask for EMU_DGIEN */ -#define EMU_DGIEN_EM23WAKEUPDGIEN (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ -#define _EMU_DGIEN_EM23WAKEUPDGIEN_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIEN */ -#define _EMU_DGIEN_EM23WAKEUPDGIEN_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIEN */ -#define _EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT (_EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPDGIEN (0x1UL << 29) /**< Temperature Interrupt enable */ -#define _EMU_DGIEN_TEMPDGIEN_SHIFT 29 /**< Shift value for EMU_TEMPDGIEN */ -#define _EMU_DGIEN_TEMPDGIEN_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIEN */ -#define _EMU_DGIEN_TEMPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPDGIEN_DEFAULT (_EMU_DGIEN_TEMPDGIEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPLOWDGIEN (0x1UL << 30) /**< Temperature low Interrupt enable */ -#define _EMU_DGIEN_TEMPLOWDGIEN_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIEN */ -#define _EMU_DGIEN_TEMPLOWDGIEN_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIEN */ -#define _EMU_DGIEN_TEMPLOWDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPLOWDGIEN_DEFAULT (_EMU_DGIEN_TEMPLOWDGIEN_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPHIGHDGIEN (0x1UL << 31) /**< Temperature high Interrupt enable */ -#define _EMU_DGIEN_TEMPHIGHDGIEN_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIEN */ -#define _EMU_DGIEN_TEMPHIGHDGIEN_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIEN */ -#define _EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT (_EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define _EMU_DGIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIEN */ +#define _EMU_DGIEN_MASK 0xE1000000UL /**< Mask for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT (_EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_DGIEN_TEMPDGIEN_SHIFT 29 /**< Shift value for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN_DEFAULT (_EMU_DGIEN_TEMPDGIEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_DGIEN_TEMPLOWDGIEN_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN_DEFAULT (_EMU_DGIEN_TEMPLOWDGIEN_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT (_EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIEN */ /* Bit fields for EMU EFPIF */ -#define _EMU_EFPIF_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIF */ -#define _EMU_EFPIF_MASK 0x00000001UL /**< Mask for EMU_EFPIF */ -#define EMU_EFPIF_EFPIF (0x1UL << 0) /**< EFP Interrupt Flag */ -#define _EMU_EFPIF_EFPIF_SHIFT 0 /**< Shift value for EMU_EFPIF */ -#define _EMU_EFPIF_EFPIF_MASK 0x1UL /**< Bit mask for EMU_EFPIF */ -#define _EMU_EFPIF_EFPIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIF */ -#define EMU_EFPIF_EFPIF_DEFAULT (_EMU_EFPIF_EFPIF_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIF */ +#define _EMU_EFPIF_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIF */ +#define _EMU_EFPIF_MASK 0x00000001UL /**< Mask for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF (0x1UL << 0) /**< EFP Interrupt Flag */ +#define _EMU_EFPIF_EFPIF_SHIFT 0 /**< Shift value for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_MASK 0x1UL /**< Bit mask for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF_DEFAULT (_EMU_EFPIF_EFPIF_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIF */ /* Bit fields for EMU EFPIEN */ -#define _EMU_EFPIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIEN */ -#define _EMU_EFPIEN_MASK 0x00000001UL /**< Mask for EMU_EFPIEN */ -#define EMU_EFPIEN_EFPIEN (0x1UL << 0) /**< EFP Interrupt enable */ -#define _EMU_EFPIEN_EFPIEN_SHIFT 0 /**< Shift value for EMU_EFPIEN */ -#define _EMU_EFPIEN_EFPIEN_MASK 0x1UL /**< Bit mask for EMU_EFPIEN */ -#define _EMU_EFPIEN_EFPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIEN */ -#define EMU_EFPIEN_EFPIEN_DEFAULT (_EMU_EFPIEN_EFPIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIEN */ +#define _EMU_EFPIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIEN */ +#define _EMU_EFPIEN_MASK 0x00000001UL /**< Mask for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN (0x1UL << 0) /**< EFP Interrupt enable */ +#define _EMU_EFPIEN_EFPIEN_SHIFT 0 /**< Shift value for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_MASK 0x1UL /**< Bit mask for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN_DEFAULT (_EMU_EFPIEN_EFPIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIEN */ /** @} End of group EFR32SG28_EMU_BitFields */ /** @} End of group EFR32SG28_EMU */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_eusart.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_eusart.h index e37ac4f247..3d29b1e178 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_eusart.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_eusart.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_EUSART_H #define EFR32SG28_EUSART_H - #define EUSART_HAS_SET_CLEAR /**************************************************************************//** @@ -43,107 +42,106 @@ *****************************************************************************/ /** EUSART Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t EN; /**< Enable Register */ - __IOM uint32_t CFG0; /**< Configuration 0 Register */ - __IOM uint32_t CFG1; /**< Configuration 1 Register */ - __IOM uint32_t CFG2; /**< Configuration 2 Register */ - __IOM uint32_t FRAMECFG; /**< Frame Format Register */ - __IOM uint32_t DTXDATCFG; /**< Default TX DATA Register */ - __IOM uint32_t IRHFCFG; /**< HF IrDA Mod Config Register */ - __IOM uint32_t IRLFCFG; /**< LF IrDA Pulse Config Register */ - __IOM uint32_t TIMINGCFG; /**< Timing Register */ - __IOM uint32_t STARTFRAMECFG; /**< Start Frame Register */ - __IOM uint32_t SIGFRAMECFG; /**< Signal Frame Register */ - __IOM uint32_t CLKDIV; /**< Clock Divider Register */ - __IOM uint32_t TRIGCTRL; /**< Trigger Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t RXDATA; /**< RX Data Register */ - __IM uint32_t RXDATAP; /**< RX Data Peek Register */ - __IOM uint32_t TXDATA; /**< TX Data Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - uint32_t RESERVED0[42U]; /**< Reserved for future use */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - uint32_t RESERVED2[959U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t EN_SET; /**< Enable Register */ - __IOM uint32_t CFG0_SET; /**< Configuration 0 Register */ - __IOM uint32_t CFG1_SET; /**< Configuration 1 Register */ - __IOM uint32_t CFG2_SET; /**< Configuration 2 Register */ - __IOM uint32_t FRAMECFG_SET; /**< Frame Format Register */ - __IOM uint32_t DTXDATCFG_SET; /**< Default TX DATA Register */ - __IOM uint32_t IRHFCFG_SET; /**< HF IrDA Mod Config Register */ - __IOM uint32_t IRLFCFG_SET; /**< LF IrDA Pulse Config Register */ - __IOM uint32_t TIMINGCFG_SET; /**< Timing Register */ - __IOM uint32_t STARTFRAMECFG_SET; /**< Start Frame Register */ - __IOM uint32_t SIGFRAMECFG_SET; /**< Signal Frame Register */ - __IOM uint32_t CLKDIV_SET; /**< Clock Divider Register */ - __IOM uint32_t TRIGCTRL_SET; /**< Trigger Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t RXDATA_SET; /**< RX Data Register */ - __IM uint32_t RXDATAP_SET; /**< RX Data Peek Register */ - __IOM uint32_t TXDATA_SET; /**< TX Data Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - uint32_t RESERVED3[42U]; /**< Reserved for future use */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - uint32_t RESERVED5[959U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t EN_CLR; /**< Enable Register */ - __IOM uint32_t CFG0_CLR; /**< Configuration 0 Register */ - __IOM uint32_t CFG1_CLR; /**< Configuration 1 Register */ - __IOM uint32_t CFG2_CLR; /**< Configuration 2 Register */ - __IOM uint32_t FRAMECFG_CLR; /**< Frame Format Register */ - __IOM uint32_t DTXDATCFG_CLR; /**< Default TX DATA Register */ - __IOM uint32_t IRHFCFG_CLR; /**< HF IrDA Mod Config Register */ - __IOM uint32_t IRLFCFG_CLR; /**< LF IrDA Pulse Config Register */ - __IOM uint32_t TIMINGCFG_CLR; /**< Timing Register */ - __IOM uint32_t STARTFRAMECFG_CLR; /**< Start Frame Register */ - __IOM uint32_t SIGFRAMECFG_CLR; /**< Signal Frame Register */ - __IOM uint32_t CLKDIV_CLR; /**< Clock Divider Register */ - __IOM uint32_t TRIGCTRL_CLR; /**< Trigger Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t RXDATA_CLR; /**< RX Data Register */ - __IM uint32_t RXDATAP_CLR; /**< RX Data Peek Register */ - __IOM uint32_t TXDATA_CLR; /**< TX Data Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - uint32_t RESERVED6[42U]; /**< Reserved for future use */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - uint32_t RESERVED8[959U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t EN_TGL; /**< Enable Register */ - __IOM uint32_t CFG0_TGL; /**< Configuration 0 Register */ - __IOM uint32_t CFG1_TGL; /**< Configuration 1 Register */ - __IOM uint32_t CFG2_TGL; /**< Configuration 2 Register */ - __IOM uint32_t FRAMECFG_TGL; /**< Frame Format Register */ - __IOM uint32_t DTXDATCFG_TGL; /**< Default TX DATA Register */ - __IOM uint32_t IRHFCFG_TGL; /**< HF IrDA Mod Config Register */ - __IOM uint32_t IRLFCFG_TGL; /**< LF IrDA Pulse Config Register */ - __IOM uint32_t TIMINGCFG_TGL; /**< Timing Register */ - __IOM uint32_t STARTFRAMECFG_TGL; /**< Start Frame Register */ - __IOM uint32_t SIGFRAMECFG_TGL; /**< Signal Frame Register */ - __IOM uint32_t CLKDIV_TGL; /**< Clock Divider Register */ - __IOM uint32_t TRIGCTRL_TGL; /**< Trigger Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t RXDATA_TGL; /**< RX Data Register */ - __IM uint32_t RXDATAP_TGL; /**< RX Data Peek Register */ - __IOM uint32_t TXDATA_TGL; /**< TX Data Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - uint32_t RESERVED9[42U]; /**< Reserved for future use */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG0; /**< Configuration 0 Register */ + __IOM uint32_t CFG1; /**< Configuration 1 Register */ + __IOM uint32_t CFG2; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL; /**< Trigger Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t RXDATA; /**< RX Data Register */ + __IM uint32_t RXDATAP; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA; /**< TX Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED0[42U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG0_SET; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_SET; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_SET; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_SET; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_SET; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_SET; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_SET; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_SET; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_SET; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_SET; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_SET; /**< Trigger Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t RXDATA_SET; /**< RX Data Register */ + __IM uint32_t RXDATAP_SET; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< TX Data Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED3[42U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG0_CLR; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_CLR; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_CLR; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_CLR; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_CLR; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_CLR; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_CLR; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_CLR; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_CLR; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_CLR; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< Trigger Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t RXDATA_CLR; /**< RX Data Register */ + __IM uint32_t RXDATAP_CLR; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Data Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED6[42U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG0_TGL; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_TGL; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_TGL; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_TGL; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_TGL; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_TGL; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_TGL; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_TGL; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_TGL; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_TGL; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< Trigger Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t RXDATA_TGL; /**< RX Data Register */ + __IM uint32_t RXDATAP_TGL; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Data Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + uint32_t RESERVED9[42U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ } EUSART_TypeDef; /** @} End of group EFR32SG28_EUSART */ @@ -155,1038 +153,1038 @@ typedef struct *****************************************************************************/ /* Bit fields for EUSART IPVERSION */ -#define _EUSART_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for EUSART_IPVERSION */ -#define _EUSART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EUSART_IPVERSION */ -#define _EUSART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EUSART_IPVERSION */ -#define _EUSART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_IPVERSION */ -#define _EUSART_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_IPVERSION */ -#define EUSART_IPVERSION_IPVERSION_DEFAULT (_EUSART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_IPVERSION */ +#define EUSART_IPVERSION_IPVERSION_DEFAULT (_EUSART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IPVERSION */ /* Bit fields for EUSART EN */ -#define _EUSART_EN_RESETVALUE 0x00000000UL /**< Default value for EUSART_EN */ -#define _EUSART_EN_MASK 0x00000003UL /**< Mask for EUSART_EN */ -#define EUSART_EN_EN (0x1UL << 0) /**< Module enable */ -#define _EUSART_EN_EN_SHIFT 0 /**< Shift value for EUSART_EN */ -#define _EUSART_EN_EN_MASK 0x1UL /**< Bit mask for EUSART_EN */ -#define _EUSART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ -#define EUSART_EN_EN_DEFAULT (_EUSART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_EN */ -#define EUSART_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _EUSART_EN_DISABLING_SHIFT 1 /**< Shift value for EUSART_DISABLING */ -#define _EUSART_EN_DISABLING_MASK 0x2UL /**< Bit mask for EUSART_DISABLING */ -#define _EUSART_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ -#define EUSART_EN_DISABLING_DEFAULT (_EUSART_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_EN */ +#define _EUSART_EN_RESETVALUE 0x00000000UL /**< Default value for EUSART_EN */ +#define _EUSART_EN_MASK 0x00000003UL /**< Mask for EUSART_EN */ +#define EUSART_EN_EN (0x1UL << 0) /**< Module enable */ +#define _EUSART_EN_EN_SHIFT 0 /**< Shift value for EUSART_EN */ +#define _EUSART_EN_EN_MASK 0x1UL /**< Bit mask for EUSART_EN */ +#define _EUSART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ +#define EUSART_EN_EN_DEFAULT (_EUSART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_EN */ +#define EUSART_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _EUSART_EN_DISABLING_SHIFT 1 /**< Shift value for EUSART_DISABLING */ +#define _EUSART_EN_DISABLING_MASK 0x2UL /**< Bit mask for EUSART_DISABLING */ +#define _EUSART_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ +#define EUSART_EN_DISABLING_DEFAULT (_EUSART_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_EN */ /* Bit fields for EUSART CFG0 */ -#define _EUSART_CFG0_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG0 */ -#define _EUSART_CFG0_MASK 0xC1D264FFUL /**< Mask for EUSART_CFG0 */ -#define EUSART_CFG0_SYNC (0x1UL << 0) /**< Synchronous Mode */ -#define _EUSART_CFG0_SYNC_SHIFT 0 /**< Shift value for EUSART_SYNC */ -#define _EUSART_CFG0_SYNC_MASK 0x1UL /**< Bit mask for EUSART_SYNC */ -#define _EUSART_CFG0_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_SYNC_ASYNC 0x00000000UL /**< Mode ASYNC for EUSART_CFG0 */ -#define _EUSART_CFG0_SYNC_SYNC 0x00000001UL /**< Mode SYNC for EUSART_CFG0 */ -#define EUSART_CFG0_SYNC_DEFAULT (_EUSART_CFG0_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_SYNC_ASYNC (_EUSART_CFG0_SYNC_ASYNC << 0) /**< Shifted mode ASYNC for EUSART_CFG0 */ -#define EUSART_CFG0_SYNC_SYNC (_EUSART_CFG0_SYNC_SYNC << 0) /**< Shifted mode SYNC for EUSART_CFG0 */ -#define EUSART_CFG0_LOOPBK (0x1UL << 1) /**< Loopback Enable */ -#define _EUSART_CFG0_LOOPBK_SHIFT 1 /**< Shift value for EUSART_LOOPBK */ -#define _EUSART_CFG0_LOOPBK_MASK 0x2UL /**< Bit mask for EUSART_LOOPBK */ -#define _EUSART_CFG0_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_LOOPBK_DEFAULT (_EUSART_CFG0_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_LOOPBK_DISABLE (_EUSART_CFG0_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_LOOPBK_ENABLE (_EUSART_CFG0_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_CCEN (0x1UL << 2) /**< Collision Check Enable */ -#define _EUSART_CFG0_CCEN_SHIFT 2 /**< Shift value for EUSART_CCEN */ -#define _EUSART_CFG0_CCEN_MASK 0x4UL /**< Bit mask for EUSART_CCEN */ -#define _EUSART_CFG0_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_CCEN_DEFAULT (_EUSART_CFG0_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_CCEN_DISABLE (_EUSART_CFG0_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_CCEN_ENABLE (_EUSART_CFG0_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MPM (0x1UL << 3) /**< Multi-Processor Mode */ -#define _EUSART_CFG0_MPM_SHIFT 3 /**< Shift value for EUSART_MPM */ -#define _EUSART_CFG0_MPM_MASK 0x8UL /**< Bit mask for EUSART_MPM */ -#define _EUSART_CFG0_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MPM_DEFAULT (_EUSART_CFG0_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_MPM_DISABLE (_EUSART_CFG0_MPM_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MPM_ENABLE (_EUSART_CFG0_MPM_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ -#define _EUSART_CFG0_MPAB_SHIFT 4 /**< Shift value for EUSART_MPAB */ -#define _EUSART_CFG0_MPAB_MASK 0x10UL /**< Bit mask for EUSART_MPAB */ -#define _EUSART_CFG0_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_MPAB_DEFAULT (_EUSART_CFG0_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_SHIFT 5 /**< Shift value for EUSART_OVS */ -#define _EUSART_CFG0_OVS_MASK 0xE0UL /**< Bit mask for EUSART_OVS */ -#define _EUSART_CFG0_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_X16 0x00000000UL /**< Mode X16 for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_X8 0x00000001UL /**< Mode X8 for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_X6 0x00000002UL /**< Mode X6 for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_X4 0x00000003UL /**< Mode X4 for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_DISABLE 0x00000004UL /**< Mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_DEFAULT (_EUSART_CFG0_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_X16 (_EUSART_CFG0_OVS_X16 << 5) /**< Shifted mode X16 for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_X8 (_EUSART_CFG0_OVS_X8 << 5) /**< Shifted mode X8 for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_X6 (_EUSART_CFG0_OVS_X6 << 5) /**< Shifted mode X6 for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_X4 (_EUSART_CFG0_OVS_X4 << 5) /**< Shifted mode X4 for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_DISABLE (_EUSART_CFG0_OVS_DISABLE << 5) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MSBF (0x1UL << 10) /**< Most Significant Bit First */ -#define _EUSART_CFG0_MSBF_SHIFT 10 /**< Shift value for EUSART_MSBF */ -#define _EUSART_CFG0_MSBF_MASK 0x400UL /**< Bit mask for EUSART_MSBF */ -#define _EUSART_CFG0_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MSBF_DEFAULT (_EUSART_CFG0_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_MSBF_DISABLE (_EUSART_CFG0_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MSBF_ENABLE (_EUSART_CFG0_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_RXINV (0x1UL << 13) /**< Receiver Input Invert */ -#define _EUSART_CFG0_RXINV_SHIFT 13 /**< Shift value for EUSART_RXINV */ -#define _EUSART_CFG0_RXINV_MASK 0x2000UL /**< Bit mask for EUSART_RXINV */ -#define _EUSART_CFG0_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_RXINV_DEFAULT (_EUSART_CFG0_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_RXINV_DISABLE (_EUSART_CFG0_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_RXINV_ENABLE (_EUSART_CFG0_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_TXINV (0x1UL << 14) /**< Transmitter output Invert */ -#define _EUSART_CFG0_TXINV_SHIFT 14 /**< Shift value for EUSART_TXINV */ -#define _EUSART_CFG0_TXINV_MASK 0x4000UL /**< Bit mask for EUSART_TXINV */ -#define _EUSART_CFG0_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_TXINV_DEFAULT (_EUSART_CFG0_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_TXINV_DISABLE (_EUSART_CFG0_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_TXINV_ENABLE (_EUSART_CFG0_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ -#define _EUSART_CFG0_AUTOTRI_SHIFT 17 /**< Shift value for EUSART_AUTOTRI */ -#define _EUSART_CFG0_AUTOTRI_MASK 0x20000UL /**< Bit mask for EUSART_AUTOTRI */ -#define _EUSART_CFG0_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOTRI_DEFAULT (_EUSART_CFG0_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOTRI_DISABLE (_EUSART_CFG0_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOTRI_ENABLE (_EUSART_CFG0_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ -#define _EUSART_CFG0_SKIPPERRF_SHIFT 20 /**< Shift value for EUSART_SKIPPERRF */ -#define _EUSART_CFG0_SKIPPERRF_MASK 0x100000UL /**< Bit mask for EUSART_SKIPPERRF */ -#define _EUSART_CFG0_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_SKIPPERRF_DEFAULT (_EUSART_CFG0_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSDMA (0x1UL << 22) /**< Halt DMA Read On Error */ -#define _EUSART_CFG0_ERRSDMA_SHIFT 22 /**< Shift value for EUSART_ERRSDMA */ -#define _EUSART_CFG0_ERRSDMA_MASK 0x400000UL /**< Bit mask for EUSART_ERRSDMA */ -#define _EUSART_CFG0_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSDMA_DEFAULT (_EUSART_CFG0_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSDMA_DISABLE (_EUSART_CFG0_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSDMA_ENABLE (_EUSART_CFG0_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ -#define _EUSART_CFG0_ERRSRX_SHIFT 23 /**< Shift value for EUSART_ERRSRX */ -#define _EUSART_CFG0_ERRSRX_MASK 0x800000UL /**< Bit mask for EUSART_ERRSRX */ -#define _EUSART_CFG0_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSRX_DEFAULT (_EUSART_CFG0_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSRX_DISABLE (_EUSART_CFG0_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSRX_ENABLE (_EUSART_CFG0_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ -#define _EUSART_CFG0_ERRSTX_SHIFT 24 /**< Shift value for EUSART_ERRSTX */ -#define _EUSART_CFG0_ERRSTX_MASK 0x1000000UL /**< Bit mask for EUSART_ERRSTX */ -#define _EUSART_CFG0_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSTX_DEFAULT (_EUSART_CFG0_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSTX_DISABLE (_EUSART_CFG0_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSTX_ENABLE (_EUSART_CFG0_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ -#define _EUSART_CFG0_MVDIS_SHIFT 30 /**< Shift value for EUSART_MVDIS */ -#define _EUSART_CFG0_MVDIS_MASK 0x40000000UL /**< Bit mask for EUSART_MVDIS */ -#define _EUSART_CFG0_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_MVDIS_DEFAULT (_EUSART_CFG0_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ -#define _EUSART_CFG0_AUTOBAUDEN_SHIFT 31 /**< Shift value for EUSART_AUTOBAUDEN */ -#define _EUSART_CFG0_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for EUSART_AUTOBAUDEN */ -#define _EUSART_CFG0_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOBAUDEN_DEFAULT (_EUSART_CFG0_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG0 */ +#define _EUSART_CFG0_MASK 0xC1D264FFUL /**< Mask for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC (0x1UL << 0) /**< Synchronous Mode */ +#define _EUSART_CFG0_SYNC_SHIFT 0 /**< Shift value for EUSART_SYNC */ +#define _EUSART_CFG0_SYNC_MASK 0x1UL /**< Bit mask for EUSART_SYNC */ +#define _EUSART_CFG0_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_SYNC_ASYNC 0x00000000UL /**< Mode ASYNC for EUSART_CFG0 */ +#define _EUSART_CFG0_SYNC_SYNC 0x00000001UL /**< Mode SYNC for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_DEFAULT (_EUSART_CFG0_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_ASYNC (_EUSART_CFG0_SYNC_ASYNC << 0) /**< Shifted mode ASYNC for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_SYNC (_EUSART_CFG0_SYNC_SYNC << 0) /**< Shifted mode SYNC for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _EUSART_CFG0_LOOPBK_SHIFT 1 /**< Shift value for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_MASK 0x2UL /**< Bit mask for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DEFAULT (_EUSART_CFG0_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DISABLE (_EUSART_CFG0_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_ENABLE (_EUSART_CFG0_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _EUSART_CFG0_CCEN_SHIFT 2 /**< Shift value for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_MASK 0x4UL /**< Bit mask for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DEFAULT (_EUSART_CFG0_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DISABLE (_EUSART_CFG0_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_ENABLE (_EUSART_CFG0_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _EUSART_CFG0_MPM_SHIFT 3 /**< Shift value for EUSART_MPM */ +#define _EUSART_CFG0_MPM_MASK 0x8UL /**< Bit mask for EUSART_MPM */ +#define _EUSART_CFG0_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DEFAULT (_EUSART_CFG0_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DISABLE (_EUSART_CFG0_MPM_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_ENABLE (_EUSART_CFG0_MPM_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _EUSART_CFG0_MPAB_SHIFT 4 /**< Shift value for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_MASK 0x10UL /**< Bit mask for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB_DEFAULT (_EUSART_CFG0_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_SHIFT 5 /**< Shift value for EUSART_OVS */ +#define _EUSART_CFG0_OVS_MASK 0xE0UL /**< Bit mask for EUSART_OVS */ +#define _EUSART_CFG0_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X16 0x00000000UL /**< Mode X16 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X8 0x00000001UL /**< Mode X8 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X6 0x00000002UL /**< Mode X6 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X4 0x00000003UL /**< Mode X4 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_DISABLE 0x00000004UL /**< Mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DEFAULT (_EUSART_CFG0_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X16 (_EUSART_CFG0_OVS_X16 << 5) /**< Shifted mode X16 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X8 (_EUSART_CFG0_OVS_X8 << 5) /**< Shifted mode X8 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X6 (_EUSART_CFG0_OVS_X6 << 5) /**< Shifted mode X6 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X4 (_EUSART_CFG0_OVS_X4 << 5) /**< Shifted mode X4 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DISABLE (_EUSART_CFG0_OVS_DISABLE << 5) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _EUSART_CFG0_MSBF_SHIFT 10 /**< Shift value for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_MASK 0x400UL /**< Bit mask for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DEFAULT (_EUSART_CFG0_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DISABLE (_EUSART_CFG0_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_ENABLE (_EUSART_CFG0_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _EUSART_CFG0_RXINV_SHIFT 13 /**< Shift value for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_MASK 0x2000UL /**< Bit mask for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DEFAULT (_EUSART_CFG0_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DISABLE (_EUSART_CFG0_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_ENABLE (_EUSART_CFG0_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _EUSART_CFG0_TXINV_SHIFT 14 /**< Shift value for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_MASK 0x4000UL /**< Bit mask for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DEFAULT (_EUSART_CFG0_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DISABLE (_EUSART_CFG0_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_ENABLE (_EUSART_CFG0_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _EUSART_CFG0_AUTOTRI_SHIFT 17 /**< Shift value for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_MASK 0x20000UL /**< Bit mask for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DEFAULT (_EUSART_CFG0_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DISABLE (_EUSART_CFG0_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_ENABLE (_EUSART_CFG0_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _EUSART_CFG0_SKIPPERRF_SHIFT 20 /**< Shift value for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_MASK 0x100000UL /**< Bit mask for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF_DEFAULT (_EUSART_CFG0_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA (0x1UL << 22) /**< Halt DMA Read On Error */ +#define _EUSART_CFG0_ERRSDMA_SHIFT 22 /**< Shift value for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_MASK 0x400000UL /**< Bit mask for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DEFAULT (_EUSART_CFG0_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DISABLE (_EUSART_CFG0_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_ENABLE (_EUSART_CFG0_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _EUSART_CFG0_ERRSRX_SHIFT 23 /**< Shift value for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_MASK 0x800000UL /**< Bit mask for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DEFAULT (_EUSART_CFG0_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DISABLE (_EUSART_CFG0_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_ENABLE (_EUSART_CFG0_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _EUSART_CFG0_ERRSTX_SHIFT 24 /**< Shift value for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_MASK 0x1000000UL /**< Bit mask for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DEFAULT (_EUSART_CFG0_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DISABLE (_EUSART_CFG0_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_ENABLE (_EUSART_CFG0_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _EUSART_CFG0_MVDIS_SHIFT 30 /**< Shift value for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_MASK 0x40000000UL /**< Bit mask for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS_DEFAULT (_EUSART_CFG0_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _EUSART_CFG0_AUTOBAUDEN_SHIFT 31 /**< Shift value for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN_DEFAULT (_EUSART_CFG0_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EUSART_CFG0 */ /* Bit fields for EUSART CFG1 */ -#define _EUSART_CFG1_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG1 */ -#define _EUSART_CFG1_MASK 0x7BCF8E7FUL /**< Mask for EUSART_CFG1 */ -#define EUSART_CFG1_DBGHALT (0x1UL << 0) /**< Debug halt */ -#define _EUSART_CFG1_DBGHALT_SHIFT 0 /**< Shift value for EUSART_DBGHALT */ -#define _EUSART_CFG1_DBGHALT_MASK 0x1UL /**< Bit mask for EUSART_DBGHALT */ -#define _EUSART_CFG1_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_DBGHALT_DEFAULT (_EUSART_CFG1_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_DBGHALT_DISABLE (_EUSART_CFG1_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for EUSART_CFG1 */ -#define EUSART_CFG1_DBGHALT_ENABLE (_EUSART_CFG1_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSINV (0x1UL << 1) /**< Clear-to-send Invert Enable */ -#define _EUSART_CFG1_CTSINV_SHIFT 1 /**< Shift value for EUSART_CTSINV */ -#define _EUSART_CFG1_CTSINV_MASK 0x2UL /**< Bit mask for EUSART_CTSINV */ -#define _EUSART_CFG1_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSINV_DEFAULT (_EUSART_CFG1_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_CTSINV_DISABLE (_EUSART_CFG1_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSINV_ENABLE (_EUSART_CFG1_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSEN (0x1UL << 2) /**< Clear-to-send Enable */ -#define _EUSART_CFG1_CTSEN_SHIFT 2 /**< Shift value for EUSART_CTSEN */ -#define _EUSART_CFG1_CTSEN_MASK 0x4UL /**< Bit mask for EUSART_CTSEN */ -#define _EUSART_CFG1_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSEN_DEFAULT (_EUSART_CFG1_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_CTSEN_DISABLE (_EUSART_CFG1_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSEN_ENABLE (_EUSART_CFG1_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_RTSINV (0x1UL << 3) /**< Request-to-send Invert Enable */ -#define _EUSART_CFG1_RTSINV_SHIFT 3 /**< Shift value for EUSART_RTSINV */ -#define _EUSART_CFG1_RTSINV_MASK 0x8UL /**< Bit mask for EUSART_RTSINV */ -#define _EUSART_CFG1_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_RTSINV_DEFAULT (_EUSART_CFG1_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RTSINV_DISABLE (_EUSART_CFG1_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG1 */ -#define EUSART_CFG1_RTSINV_ENABLE (_EUSART_CFG1_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_SHIFT 4 /**< Shift value for EUSART_RXTIMEOUT */ -#define _EUSART_CFG1_RXTIMEOUT_MASK 0x70UL /**< Bit mask for EUSART_RXTIMEOUT */ -#define _EUSART_CFG1_RXTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_DISABLED 0x00000000UL /**< Mode DISABLED for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_ONEFRAME 0x00000001UL /**< Mode ONEFRAME for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_TWOFRAMES 0x00000002UL /**< Mode TWOFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_THREEFRAMES 0x00000003UL /**< Mode THREEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_FOURFRAMES 0x00000004UL /**< Mode FOURFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_FIVEFRAMES 0x00000005UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_SIXFRAMES 0x00000006UL /**< Mode SIXFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_SEVENFRAMES 0x00000007UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_DEFAULT (_EUSART_CFG1_RXTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_DISABLED (_EUSART_CFG1_RXTIMEOUT_DISABLED << 4) /**< Shifted mode DISABLED for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_ONEFRAME (_EUSART_CFG1_RXTIMEOUT_ONEFRAME << 4) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_TWOFRAMES (_EUSART_CFG1_RXTIMEOUT_TWOFRAMES << 4) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_THREEFRAMES (_EUSART_CFG1_RXTIMEOUT_THREEFRAMES << 4) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_FOURFRAMES (_EUSART_CFG1_RXTIMEOUT_FOURFRAMES << 4) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_FIVEFRAMES (_EUSART_CFG1_RXTIMEOUT_FIVEFRAMES << 4) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_SIXFRAMES (_EUSART_CFG1_RXTIMEOUT_SIXFRAMES << 4) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_SEVENFRAMES (_EUSART_CFG1_RXTIMEOUT_SEVENFRAMES << 4) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXDMAWU (0x1UL << 9) /**< Transmitter DMA Wakeup */ -#define _EUSART_CFG1_TXDMAWU_SHIFT 9 /**< Shift value for EUSART_TXDMAWU */ -#define _EUSART_CFG1_TXDMAWU_MASK 0x200UL /**< Bit mask for EUSART_TXDMAWU */ -#define _EUSART_CFG1_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_TXDMAWU_DEFAULT (_EUSART_CFG1_TXDMAWU_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXDMAWU (0x1UL << 10) /**< Receiver DMA Wakeup */ -#define _EUSART_CFG1_RXDMAWU_SHIFT 10 /**< Shift value for EUSART_RXDMAWU */ -#define _EUSART_CFG1_RXDMAWU_MASK 0x400UL /**< Bit mask for EUSART_RXDMAWU */ -#define _EUSART_CFG1_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXDMAWU_DEFAULT (_EUSART_CFG1_RXDMAWU_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_SFUBRX (0x1UL << 11) /**< Start Frame Unblock Receiver */ -#define _EUSART_CFG1_SFUBRX_SHIFT 11 /**< Shift value for EUSART_SFUBRX */ -#define _EUSART_CFG1_SFUBRX_MASK 0x800UL /**< Bit mask for EUSART_SFUBRX */ -#define _EUSART_CFG1_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_SFUBRX_DEFAULT (_EUSART_CFG1_SFUBRX_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXPRSEN (0x1UL << 15) /**< PRS RX Enable */ -#define _EUSART_CFG1_RXPRSEN_SHIFT 15 /**< Shift value for EUSART_RXPRSEN */ -#define _EUSART_CFG1_RXPRSEN_MASK 0x8000UL /**< Bit mask for EUSART_RXPRSEN */ -#define _EUSART_CFG1_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXPRSEN_DEFAULT (_EUSART_CFG1_RXPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_SHIFT 16 /**< Shift value for EUSART_TXFIW */ -#define _EUSART_CFG1_TXFIW_MASK 0xF0000UL /**< Bit mask for EUSART_TXFIW */ -#define _EUSART_CFG1_TXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_DEFAULT (_EUSART_CFG1_TXFIW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_ONEFRAME (_EUSART_CFG1_TXFIW_ONEFRAME << 16) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_TWOFRAMES (_EUSART_CFG1_TXFIW_TWOFRAMES << 16) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_THREEFRAMES (_EUSART_CFG1_TXFIW_THREEFRAMES << 16) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_FOURFRAMES (_EUSART_CFG1_TXFIW_FOURFRAMES << 16) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_FIVEFRAMES (_EUSART_CFG1_TXFIW_FIVEFRAMES << 16) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_SIXFRAMES (_EUSART_CFG1_TXFIW_SIXFRAMES << 16) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_SEVENFRAMES (_EUSART_CFG1_TXFIW_SEVENFRAMES << 16) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_EIGHTFRAMES (_EUSART_CFG1_TXFIW_EIGHTFRAMES << 16) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_NINEFRAMES (_EUSART_CFG1_TXFIW_NINEFRAMES << 16) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_TENFRAMES (_EUSART_CFG1_TXFIW_TENFRAMES << 16) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_ELEVENFRAMES (_EUSART_CFG1_TXFIW_ELEVENFRAMES << 16) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_TWELVEFRAMES (_EUSART_CFG1_TXFIW_TWELVEFRAMES << 16) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_THIRTEENFRAMES (_EUSART_CFG1_TXFIW_THIRTEENFRAMES << 16) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_FOURTEENFRAMES (_EUSART_CFG1_TXFIW_FOURTEENFRAMES << 16) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_FIFTEENFRAMES (_EUSART_CFG1_TXFIW_FIFTEENFRAMES << 16) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_SIXTEENFRAMES (_EUSART_CFG1_TXFIW_SIXTEENFRAMES << 16) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_SHIFT 22 /**< Shift value for EUSART_RTSRXFW */ -#define _EUSART_CFG1_RTSRXFW_MASK 0x3C00000UL /**< Bit mask for EUSART_RTSRXFW */ -#define _EUSART_CFG1_RTSRXFW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_DEFAULT (_EUSART_CFG1_RTSRXFW_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_ONEFRAME (_EUSART_CFG1_RTSRXFW_ONEFRAME << 22) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_TWOFRAMES (_EUSART_CFG1_RTSRXFW_TWOFRAMES << 22) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_THREEFRAMES (_EUSART_CFG1_RTSRXFW_THREEFRAMES << 22) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_FOURFRAMES (_EUSART_CFG1_RTSRXFW_FOURFRAMES << 22) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_FIVEFRAMES (_EUSART_CFG1_RTSRXFW_FIVEFRAMES << 22) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_SIXFRAMES (_EUSART_CFG1_RTSRXFW_SIXFRAMES << 22) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_SEVENFRAMES (_EUSART_CFG1_RTSRXFW_SEVENFRAMES << 22) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_EIGHTFRAMES (_EUSART_CFG1_RTSRXFW_EIGHTFRAMES << 22) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_NINEFRAMES (_EUSART_CFG1_RTSRXFW_NINEFRAMES << 22) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_TENFRAMES (_EUSART_CFG1_RTSRXFW_TENFRAMES << 22) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_ELEVENFRAMES (_EUSART_CFG1_RTSRXFW_ELEVENFRAMES << 22) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_TWELVEFRAMES (_EUSART_CFG1_RTSRXFW_TWELVEFRAMES << 22) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_THIRTEENFRAMES (_EUSART_CFG1_RTSRXFW_THIRTEENFRAMES << 22) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_FOURTEENFRAMES (_EUSART_CFG1_RTSRXFW_FOURTEENFRAMES << 22) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_FIFTEENFRAMES (_EUSART_CFG1_RTSRXFW_FIFTEENFRAMES << 22) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_SIXTEENFRAMES (_EUSART_CFG1_RTSRXFW_SIXTEENFRAMES << 22) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_SHIFT 27 /**< Shift value for EUSART_RXFIW */ -#define _EUSART_CFG1_RXFIW_MASK 0x78000000UL /**< Bit mask for EUSART_RXFIW */ -#define _EUSART_CFG1_RXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_DEFAULT (_EUSART_CFG1_RXFIW_DEFAULT << 27) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_ONEFRAME (_EUSART_CFG1_RXFIW_ONEFRAME << 27) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_TWOFRAMES (_EUSART_CFG1_RXFIW_TWOFRAMES << 27) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_THREEFRAMES (_EUSART_CFG1_RXFIW_THREEFRAMES << 27) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_FOURFRAMES (_EUSART_CFG1_RXFIW_FOURFRAMES << 27) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_FIVEFRAMES (_EUSART_CFG1_RXFIW_FIVEFRAMES << 27) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_SIXFRAMES (_EUSART_CFG1_RXFIW_SIXFRAMES << 27) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_SEVENFRAMES (_EUSART_CFG1_RXFIW_SEVENFRAMES << 27) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_EIGHTFRAMES (_EUSART_CFG1_RXFIW_EIGHTFRAMES << 27) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_NINEFRAMES (_EUSART_CFG1_RXFIW_NINEFRAMES << 27) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_TENFRAMES (_EUSART_CFG1_RXFIW_TENFRAMES << 27) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_ELEVENFRAMES (_EUSART_CFG1_RXFIW_ELEVENFRAMES << 27) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_TWELVEFRAMES (_EUSART_CFG1_RXFIW_TWELVEFRAMES << 27) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_THIRTEENFRAMES (_EUSART_CFG1_RXFIW_THIRTEENFRAMES << 27) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_FOURTEENFRAMES (_EUSART_CFG1_RXFIW_FOURTEENFRAMES << 27) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_FIFTEENFRAMES (_EUSART_CFG1_RXFIW_FIFTEENFRAMES << 27) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_SIXTEENFRAMES (_EUSART_CFG1_RXFIW_SIXTEENFRAMES << 27) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG1 */ +#define _EUSART_CFG1_MASK 0x7BCF8E7FUL /**< Mask for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _EUSART_CFG1_DBGHALT_SHIFT 0 /**< Shift value for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_MASK 0x1UL /**< Bit mask for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DEFAULT (_EUSART_CFG1_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DISABLE (_EUSART_CFG1_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_ENABLE (_EUSART_CFG1_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV (0x1UL << 1) /**< Clear-to-send Invert Enable */ +#define _EUSART_CFG1_CTSINV_SHIFT 1 /**< Shift value for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_MASK 0x2UL /**< Bit mask for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DEFAULT (_EUSART_CFG1_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DISABLE (_EUSART_CFG1_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_ENABLE (_EUSART_CFG1_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN (0x1UL << 2) /**< Clear-to-send Enable */ +#define _EUSART_CFG1_CTSEN_SHIFT 2 /**< Shift value for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_MASK 0x4UL /**< Bit mask for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DEFAULT (_EUSART_CFG1_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DISABLE (_EUSART_CFG1_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_ENABLE (_EUSART_CFG1_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV (0x1UL << 3) /**< Request-to-send Invert Enable */ +#define _EUSART_CFG1_RTSINV_SHIFT 3 /**< Shift value for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_MASK 0x8UL /**< Bit mask for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DEFAULT (_EUSART_CFG1_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DISABLE (_EUSART_CFG1_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_ENABLE (_EUSART_CFG1_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SHIFT 4 /**< Shift value for EUSART_RXTIMEOUT */ +#define _EUSART_CFG1_RXTIMEOUT_MASK 0x70UL /**< Bit mask for EUSART_RXTIMEOUT */ +#define _EUSART_CFG1_RXTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_DISABLED 0x00000000UL /**< Mode DISABLED for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_ONEFRAME 0x00000001UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_TWOFRAMES 0x00000002UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_THREEFRAMES 0x00000003UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_FOURFRAMES 0x00000004UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_FIVEFRAMES 0x00000005UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SIXFRAMES 0x00000006UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SEVENFRAMES 0x00000007UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_DEFAULT (_EUSART_CFG1_RXTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_DISABLED (_EUSART_CFG1_RXTIMEOUT_DISABLED << 4) /**< Shifted mode DISABLED for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_ONEFRAME (_EUSART_CFG1_RXTIMEOUT_ONEFRAME << 4) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_TWOFRAMES (_EUSART_CFG1_RXTIMEOUT_TWOFRAMES << 4) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_THREEFRAMES (_EUSART_CFG1_RXTIMEOUT_THREEFRAMES << 4) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_FOURFRAMES (_EUSART_CFG1_RXTIMEOUT_FOURFRAMES << 4) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_FIVEFRAMES (_EUSART_CFG1_RXTIMEOUT_FIVEFRAMES << 4) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_SIXFRAMES (_EUSART_CFG1_RXTIMEOUT_SIXFRAMES << 4) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_SEVENFRAMES (_EUSART_CFG1_RXTIMEOUT_SEVENFRAMES << 4) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU (0x1UL << 9) /**< Transmitter DMA Wakeup */ +#define _EUSART_CFG1_TXDMAWU_SHIFT 9 /**< Shift value for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_MASK 0x200UL /**< Bit mask for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU_DEFAULT (_EUSART_CFG1_TXDMAWU_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU (0x1UL << 10) /**< Receiver DMA Wakeup */ +#define _EUSART_CFG1_RXDMAWU_SHIFT 10 /**< Shift value for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_MASK 0x400UL /**< Bit mask for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU_DEFAULT (_EUSART_CFG1_RXDMAWU_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX (0x1UL << 11) /**< Start Frame Unblock Receiver */ +#define _EUSART_CFG1_SFUBRX_SHIFT 11 /**< Shift value for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_MASK 0x800UL /**< Bit mask for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX_DEFAULT (_EUSART_CFG1_SFUBRX_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN (0x1UL << 15) /**< PRS RX Enable */ +#define _EUSART_CFG1_RXPRSEN_SHIFT 15 /**< Shift value for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_MASK 0x8000UL /**< Bit mask for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN_DEFAULT (_EUSART_CFG1_RXPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SHIFT 16 /**< Shift value for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_MASK 0xF0000UL /**< Bit mask for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_DEFAULT (_EUSART_CFG1_TXFIW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_ONEFRAME (_EUSART_CFG1_TXFIW_ONEFRAME << 16) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TWOFRAMES (_EUSART_CFG1_TXFIW_TWOFRAMES << 16) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_THREEFRAMES (_EUSART_CFG1_TXFIW_THREEFRAMES << 16) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FOURFRAMES (_EUSART_CFG1_TXFIW_FOURFRAMES << 16) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FIVEFRAMES (_EUSART_CFG1_TXFIW_FIVEFRAMES << 16) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SIXFRAMES (_EUSART_CFG1_TXFIW_SIXFRAMES << 16) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SEVENFRAMES (_EUSART_CFG1_TXFIW_SEVENFRAMES << 16) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_EIGHTFRAMES (_EUSART_CFG1_TXFIW_EIGHTFRAMES << 16) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_NINEFRAMES (_EUSART_CFG1_TXFIW_NINEFRAMES << 16) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TENFRAMES (_EUSART_CFG1_TXFIW_TENFRAMES << 16) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_ELEVENFRAMES (_EUSART_CFG1_TXFIW_ELEVENFRAMES << 16) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TWELVEFRAMES (_EUSART_CFG1_TXFIW_TWELVEFRAMES << 16) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_THIRTEENFRAMES (_EUSART_CFG1_TXFIW_THIRTEENFRAMES << 16) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FOURTEENFRAMES (_EUSART_CFG1_TXFIW_FOURTEENFRAMES << 16) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FIFTEENFRAMES (_EUSART_CFG1_TXFIW_FIFTEENFRAMES << 16) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SIXTEENFRAMES (_EUSART_CFG1_TXFIW_SIXTEENFRAMES << 16) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SHIFT 22 /**< Shift value for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_MASK 0x3C00000UL /**< Bit mask for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_DEFAULT (_EUSART_CFG1_RTSRXFW_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_ONEFRAME (_EUSART_CFG1_RTSRXFW_ONEFRAME << 22) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TWOFRAMES (_EUSART_CFG1_RTSRXFW_TWOFRAMES << 22) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_THREEFRAMES (_EUSART_CFG1_RTSRXFW_THREEFRAMES << 22) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FOURFRAMES (_EUSART_CFG1_RTSRXFW_FOURFRAMES << 22) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FIVEFRAMES (_EUSART_CFG1_RTSRXFW_FIVEFRAMES << 22) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SIXFRAMES (_EUSART_CFG1_RTSRXFW_SIXFRAMES << 22) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SEVENFRAMES (_EUSART_CFG1_RTSRXFW_SEVENFRAMES << 22) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_EIGHTFRAMES (_EUSART_CFG1_RTSRXFW_EIGHTFRAMES << 22) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_NINEFRAMES (_EUSART_CFG1_RTSRXFW_NINEFRAMES << 22) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TENFRAMES (_EUSART_CFG1_RTSRXFW_TENFRAMES << 22) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_ELEVENFRAMES (_EUSART_CFG1_RTSRXFW_ELEVENFRAMES << 22) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TWELVEFRAMES (_EUSART_CFG1_RTSRXFW_TWELVEFRAMES << 22) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_THIRTEENFRAMES (_EUSART_CFG1_RTSRXFW_THIRTEENFRAMES << 22) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FOURTEENFRAMES (_EUSART_CFG1_RTSRXFW_FOURTEENFRAMES << 22) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FIFTEENFRAMES (_EUSART_CFG1_RTSRXFW_FIFTEENFRAMES << 22) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SIXTEENFRAMES (_EUSART_CFG1_RTSRXFW_SIXTEENFRAMES << 22) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SHIFT 27 /**< Shift value for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_MASK 0x78000000UL /**< Bit mask for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_DEFAULT (_EUSART_CFG1_RXFIW_DEFAULT << 27) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_ONEFRAME (_EUSART_CFG1_RXFIW_ONEFRAME << 27) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TWOFRAMES (_EUSART_CFG1_RXFIW_TWOFRAMES << 27) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_THREEFRAMES (_EUSART_CFG1_RXFIW_THREEFRAMES << 27) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FOURFRAMES (_EUSART_CFG1_RXFIW_FOURFRAMES << 27) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FIVEFRAMES (_EUSART_CFG1_RXFIW_FIVEFRAMES << 27) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SIXFRAMES (_EUSART_CFG1_RXFIW_SIXFRAMES << 27) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SEVENFRAMES (_EUSART_CFG1_RXFIW_SEVENFRAMES << 27) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_EIGHTFRAMES (_EUSART_CFG1_RXFIW_EIGHTFRAMES << 27) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_NINEFRAMES (_EUSART_CFG1_RXFIW_NINEFRAMES << 27) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TENFRAMES (_EUSART_CFG1_RXFIW_TENFRAMES << 27) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_ELEVENFRAMES (_EUSART_CFG1_RXFIW_ELEVENFRAMES << 27) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TWELVEFRAMES (_EUSART_CFG1_RXFIW_TWELVEFRAMES << 27) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_THIRTEENFRAMES (_EUSART_CFG1_RXFIW_THIRTEENFRAMES << 27) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FOURTEENFRAMES (_EUSART_CFG1_RXFIW_FOURTEENFRAMES << 27) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FIFTEENFRAMES (_EUSART_CFG1_RXFIW_FIFTEENFRAMES << 27) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SIXTEENFRAMES (_EUSART_CFG1_RXFIW_SIXTEENFRAMES << 27) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ /* Bit fields for EUSART CFG2 */ -#define _EUSART_CFG2_RESETVALUE 0x00000020UL /**< Default value for EUSART_CFG2 */ -#define _EUSART_CFG2_MASK 0xFF0000FFUL /**< Mask for EUSART_CFG2 */ -#define EUSART_CFG2_MASTER (0x1UL << 0) /**< Main mode */ -#define _EUSART_CFG2_MASTER_SHIFT 0 /**< Shift value for EUSART_MASTER */ -#define _EUSART_CFG2_MASTER_MASK 0x1UL /**< Bit mask for EUSART_MASTER */ -#define _EUSART_CFG2_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define _EUSART_CFG2_MASTER_SLAVE 0x00000000UL /**< Mode SLAVE for EUSART_CFG2 */ -#define _EUSART_CFG2_MASTER_MASTER 0x00000001UL /**< Mode MASTER for EUSART_CFG2 */ -#define EUSART_CFG2_MASTER_DEFAULT (_EUSART_CFG2_MASTER_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_MASTER_SLAVE (_EUSART_CFG2_MASTER_SLAVE << 0) /**< Shifted mode SLAVE for EUSART_CFG2 */ -#define EUSART_CFG2_MASTER_MASTER (_EUSART_CFG2_MASTER_MASTER << 0) /**< Shifted mode MASTER for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPOL (0x1UL << 1) /**< Clock Polarity */ -#define _EUSART_CFG2_CLKPOL_SHIFT 1 /**< Shift value for EUSART_CLKPOL */ -#define _EUSART_CFG2_CLKPOL_MASK 0x2UL /**< Bit mask for EUSART_CLKPOL */ -#define _EUSART_CFG2_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define _EUSART_CFG2_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for EUSART_CFG2 */ -#define _EUSART_CFG2_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPOL_DEFAULT (_EUSART_CFG2_CLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPOL_IDLELOW (_EUSART_CFG2_CLKPOL_IDLELOW << 1) /**< Shifted mode IDLELOW for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPOL_IDLEHIGH (_EUSART_CFG2_CLKPOL_IDLEHIGH << 1) /**< Shifted mode IDLEHIGH for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPHA (0x1UL << 2) /**< Clock Edge for Setup/Sample */ -#define _EUSART_CFG2_CLKPHA_SHIFT 2 /**< Shift value for EUSART_CLKPHA */ -#define _EUSART_CFG2_CLKPHA_MASK 0x4UL /**< Bit mask for EUSART_CLKPHA */ -#define _EUSART_CFG2_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define _EUSART_CFG2_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for EUSART_CFG2 */ -#define _EUSART_CFG2_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPHA_DEFAULT (_EUSART_CFG2_CLKPHA_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPHA_SAMPLELEADING (_EUSART_CFG2_CLKPHA_SAMPLELEADING << 2) /**< Shifted mode SAMPLELEADING for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPHA_SAMPLETRAILING (_EUSART_CFG2_CLKPHA_SAMPLETRAILING << 2) /**< Shifted mode SAMPLETRAILING for EUSART_CFG2 */ -#define EUSART_CFG2_CSINV (0x1UL << 3) /**< Chip Select Invert */ -#define _EUSART_CFG2_CSINV_SHIFT 3 /**< Shift value for EUSART_CSINV */ -#define _EUSART_CFG2_CSINV_MASK 0x8UL /**< Bit mask for EUSART_CSINV */ -#define _EUSART_CFG2_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define _EUSART_CFG2_CSINV_AL 0x00000000UL /**< Mode AL for EUSART_CFG2 */ -#define _EUSART_CFG2_CSINV_AH 0x00000001UL /**< Mode AH for EUSART_CFG2 */ -#define EUSART_CFG2_CSINV_DEFAULT (_EUSART_CFG2_CSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_CSINV_AL (_EUSART_CFG2_CSINV_AL << 3) /**< Shifted mode AL for EUSART_CFG2 */ -#define EUSART_CFG2_CSINV_AH (_EUSART_CFG2_CSINV_AH << 3) /**< Shifted mode AH for EUSART_CFG2 */ -#define EUSART_CFG2_AUTOTX (0x1UL << 4) /**< Always Transmit When RXFIFO Not Full */ -#define _EUSART_CFG2_AUTOTX_SHIFT 4 /**< Shift value for EUSART_AUTOTX */ -#define _EUSART_CFG2_AUTOTX_MASK 0x10UL /**< Bit mask for EUSART_AUTOTX */ -#define _EUSART_CFG2_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_AUTOTX_DEFAULT (_EUSART_CFG2_AUTOTX_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_AUTOCS (0x1UL << 5) /**< Automatic Chip Select */ -#define _EUSART_CFG2_AUTOCS_SHIFT 5 /**< Shift value for EUSART_AUTOCS */ -#define _EUSART_CFG2_AUTOCS_MASK 0x20UL /**< Bit mask for EUSART_AUTOCS */ -#define _EUSART_CFG2_AUTOCS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_AUTOCS_DEFAULT (_EUSART_CFG2_AUTOCS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPRSEN (0x1UL << 6) /**< PRS CLK Enable */ -#define _EUSART_CFG2_CLKPRSEN_SHIFT 6 /**< Shift value for EUSART_CLKPRSEN */ -#define _EUSART_CFG2_CLKPRSEN_MASK 0x40UL /**< Bit mask for EUSART_CLKPRSEN */ -#define _EUSART_CFG2_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPRSEN_DEFAULT (_EUSART_CFG2_CLKPRSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_FORCELOAD (0x1UL << 7) /**< Force Load to Shift Register */ -#define _EUSART_CFG2_FORCELOAD_SHIFT 7 /**< Shift value for EUSART_FORCELOAD */ -#define _EUSART_CFG2_FORCELOAD_MASK 0x80UL /**< Bit mask for EUSART_FORCELOAD */ -#define _EUSART_CFG2_FORCELOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_FORCELOAD_DEFAULT (_EUSART_CFG2_FORCELOAD_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define _EUSART_CFG2_SDIV_SHIFT 24 /**< Shift value for EUSART_SDIV */ -#define _EUSART_CFG2_SDIV_MASK 0xFF000000UL /**< Bit mask for EUSART_SDIV */ -#define _EUSART_CFG2_SDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_SDIV_DEFAULT (_EUSART_CFG2_SDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_RESETVALUE 0x00000020UL /**< Default value for EUSART_CFG2 */ +#define _EUSART_CFG2_MASK 0xFF0000FFUL /**< Mask for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER (0x1UL << 0) /**< Main mode */ +#define _EUSART_CFG2_MASTER_SHIFT 0 /**< Shift value for EUSART_MASTER */ +#define _EUSART_CFG2_MASTER_MASK 0x1UL /**< Bit mask for EUSART_MASTER */ +#define _EUSART_CFG2_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_MASTER_SLAVE 0x00000000UL /**< Mode SLAVE for EUSART_CFG2 */ +#define _EUSART_CFG2_MASTER_MASTER 0x00000001UL /**< Mode MASTER for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_DEFAULT (_EUSART_CFG2_MASTER_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_SLAVE (_EUSART_CFG2_MASTER_SLAVE << 0) /**< Shifted mode SLAVE for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_MASTER (_EUSART_CFG2_MASTER_MASTER << 0) /**< Shifted mode MASTER for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL (0x1UL << 1) /**< Clock Polarity */ +#define _EUSART_CFG2_CLKPOL_SHIFT 1 /**< Shift value for EUSART_CLKPOL */ +#define _EUSART_CFG2_CLKPOL_MASK 0x2UL /**< Bit mask for EUSART_CLKPOL */ +#define _EUSART_CFG2_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_DEFAULT (_EUSART_CFG2_CLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_IDLELOW (_EUSART_CFG2_CLKPOL_IDLELOW << 1) /**< Shifted mode IDLELOW for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_IDLEHIGH (_EUSART_CFG2_CLKPOL_IDLEHIGH << 1) /**< Shifted mode IDLEHIGH for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA (0x1UL << 2) /**< Clock Edge for Setup/Sample */ +#define _EUSART_CFG2_CLKPHA_SHIFT 2 /**< Shift value for EUSART_CLKPHA */ +#define _EUSART_CFG2_CLKPHA_MASK 0x4UL /**< Bit mask for EUSART_CLKPHA */ +#define _EUSART_CFG2_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_DEFAULT (_EUSART_CFG2_CLKPHA_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_SAMPLELEADING (_EUSART_CFG2_CLKPHA_SAMPLELEADING << 2) /**< Shifted mode SAMPLELEADING for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_SAMPLETRAILING (_EUSART_CFG2_CLKPHA_SAMPLETRAILING << 2) /**< Shifted mode SAMPLETRAILING for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV (0x1UL << 3) /**< Chip Select Invert */ +#define _EUSART_CFG2_CSINV_SHIFT 3 /**< Shift value for EUSART_CSINV */ +#define _EUSART_CFG2_CSINV_MASK 0x8UL /**< Bit mask for EUSART_CSINV */ +#define _EUSART_CFG2_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CSINV_AL 0x00000000UL /**< Mode AL for EUSART_CFG2 */ +#define _EUSART_CFG2_CSINV_AH 0x00000001UL /**< Mode AH for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_DEFAULT (_EUSART_CFG2_CSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_AL (_EUSART_CFG2_CSINV_AL << 3) /**< Shifted mode AL for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_AH (_EUSART_CFG2_CSINV_AH << 3) /**< Shifted mode AH for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOTX (0x1UL << 4) /**< Always Transmit When RXFIFO Not Full */ +#define _EUSART_CFG2_AUTOTX_SHIFT 4 /**< Shift value for EUSART_AUTOTX */ +#define _EUSART_CFG2_AUTOTX_MASK 0x10UL /**< Bit mask for EUSART_AUTOTX */ +#define _EUSART_CFG2_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOTX_DEFAULT (_EUSART_CFG2_AUTOTX_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOCS (0x1UL << 5) /**< Automatic Chip Select */ +#define _EUSART_CFG2_AUTOCS_SHIFT 5 /**< Shift value for EUSART_AUTOCS */ +#define _EUSART_CFG2_AUTOCS_MASK 0x20UL /**< Bit mask for EUSART_AUTOCS */ +#define _EUSART_CFG2_AUTOCS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOCS_DEFAULT (_EUSART_CFG2_AUTOCS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPRSEN (0x1UL << 6) /**< PRS CLK Enable */ +#define _EUSART_CFG2_CLKPRSEN_SHIFT 6 /**< Shift value for EUSART_CLKPRSEN */ +#define _EUSART_CFG2_CLKPRSEN_MASK 0x40UL /**< Bit mask for EUSART_CLKPRSEN */ +#define _EUSART_CFG2_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPRSEN_DEFAULT (_EUSART_CFG2_CLKPRSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_FORCELOAD (0x1UL << 7) /**< Force Load to Shift Register */ +#define _EUSART_CFG2_FORCELOAD_SHIFT 7 /**< Shift value for EUSART_FORCELOAD */ +#define _EUSART_CFG2_FORCELOAD_MASK 0x80UL /**< Bit mask for EUSART_FORCELOAD */ +#define _EUSART_CFG2_FORCELOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_FORCELOAD_DEFAULT (_EUSART_CFG2_FORCELOAD_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_SDIV_SHIFT 24 /**< Shift value for EUSART_SDIV */ +#define _EUSART_CFG2_SDIV_MASK 0xFF000000UL /**< Bit mask for EUSART_SDIV */ +#define _EUSART_CFG2_SDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_SDIV_DEFAULT (_EUSART_CFG2_SDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG2 */ /* Bit fields for EUSART FRAMECFG */ -#define _EUSART_FRAMECFG_RESETVALUE 0x00001002UL /**< Default value for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_MASK 0x0000330FUL /**< Mask for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_SHIFT 0 /**< Shift value for EUSART_DATABITS */ -#define _EUSART_FRAMECFG_DATABITS_MASK 0xFUL /**< Bit mask for EUSART_DATABITS */ -#define _EUSART_FRAMECFG_DATABITS_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_SEVEN 0x00000001UL /**< Mode SEVEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_EIGHT 0x00000002UL /**< Mode EIGHT for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_NINE 0x00000003UL /**< Mode NINE for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_TEN 0x00000004UL /**< Mode TEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_ELEVEN 0x00000005UL /**< Mode ELEVEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_TWELVE 0x00000006UL /**< Mode TWELVE for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_THIRTEEN 0x00000007UL /**< Mode THIRTEEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_FOURTEEN 0x00000008UL /**< Mode FOURTEEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_FIFTEEN 0x00000009UL /**< Mode FIFTEEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_SIXTEEN 0x0000000AUL /**< Mode SIXTEEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_DEFAULT (_EUSART_FRAMECFG_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_SEVEN (_EUSART_FRAMECFG_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_EIGHT (_EUSART_FRAMECFG_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_NINE (_EUSART_FRAMECFG_DATABITS_NINE << 0) /**< Shifted mode NINE for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_TEN (_EUSART_FRAMECFG_DATABITS_TEN << 0) /**< Shifted mode TEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_ELEVEN (_EUSART_FRAMECFG_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_TWELVE (_EUSART_FRAMECFG_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_THIRTEEN (_EUSART_FRAMECFG_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_FOURTEEN (_EUSART_FRAMECFG_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_FIFTEEN (_EUSART_FRAMECFG_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_SIXTEEN (_EUSART_FRAMECFG_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_PARITY_SHIFT 8 /**< Shift value for EUSART_PARITY */ -#define _EUSART_FRAMECFG_PARITY_MASK 0x300UL /**< Bit mask for EUSART_PARITY */ -#define _EUSART_FRAMECFG_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_PARITY_NONE 0x00000000UL /**< Mode NONE for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_PARITY_EVEN 0x00000002UL /**< Mode EVEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_PARITY_ODD 0x00000003UL /**< Mode ODD for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_PARITY_DEFAULT (_EUSART_FRAMECFG_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_PARITY_NONE (_EUSART_FRAMECFG_PARITY_NONE << 8) /**< Shifted mode NONE for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_PARITY_EVEN (_EUSART_FRAMECFG_PARITY_EVEN << 8) /**< Shifted mode EVEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_PARITY_ODD (_EUSART_FRAMECFG_PARITY_ODD << 8) /**< Shifted mode ODD for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_SHIFT 12 /**< Shift value for EUSART_STOPBITS */ -#define _EUSART_FRAMECFG_STOPBITS_MASK 0x3000UL /**< Bit mask for EUSART_STOPBITS */ -#define _EUSART_FRAMECFG_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_HALF 0x00000000UL /**< Mode HALF for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_ONE 0x00000001UL /**< Mode ONE for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_TWO 0x00000003UL /**< Mode TWO for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_STOPBITS_DEFAULT (_EUSART_FRAMECFG_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_STOPBITS_HALF (_EUSART_FRAMECFG_STOPBITS_HALF << 12) /**< Shifted mode HALF for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_STOPBITS_ONE (_EUSART_FRAMECFG_STOPBITS_ONE << 12) /**< Shifted mode ONE for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_STOPBITS_ONEANDAHALF (_EUSART_FRAMECFG_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for EUSART_FRAMECFG*/ -#define EUSART_FRAMECFG_STOPBITS_TWO (_EUSART_FRAMECFG_STOPBITS_TWO << 12) /**< Shifted mode TWO for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_RESETVALUE 0x00001002UL /**< Default value for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_MASK 0x0000330FUL /**< Mask for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SHIFT 0 /**< Shift value for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_MASK 0xFUL /**< Bit mask for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SEVEN 0x00000001UL /**< Mode SEVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_EIGHT 0x00000002UL /**< Mode EIGHT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_NINE 0x00000003UL /**< Mode NINE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_TEN 0x00000004UL /**< Mode TEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_ELEVEN 0x00000005UL /**< Mode ELEVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_TWELVE 0x00000006UL /**< Mode TWELVE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_THIRTEEN 0x00000007UL /**< Mode THIRTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_FOURTEEN 0x00000008UL /**< Mode FOURTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_FIFTEEN 0x00000009UL /**< Mode FIFTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SIXTEEN 0x0000000AUL /**< Mode SIXTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_DEFAULT (_EUSART_FRAMECFG_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_SEVEN (_EUSART_FRAMECFG_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_EIGHT (_EUSART_FRAMECFG_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_NINE (_EUSART_FRAMECFG_DATABITS_NINE << 0) /**< Shifted mode NINE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_TEN (_EUSART_FRAMECFG_DATABITS_TEN << 0) /**< Shifted mode TEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_ELEVEN (_EUSART_FRAMECFG_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_TWELVE (_EUSART_FRAMECFG_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_THIRTEEN (_EUSART_FRAMECFG_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_FOURTEEN (_EUSART_FRAMECFG_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_FIFTEEN (_EUSART_FRAMECFG_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_SIXTEEN (_EUSART_FRAMECFG_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_SHIFT 8 /**< Shift value for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_MASK 0x300UL /**< Bit mask for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_NONE 0x00000000UL /**< Mode NONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_EVEN 0x00000002UL /**< Mode EVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_ODD 0x00000003UL /**< Mode ODD for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_DEFAULT (_EUSART_FRAMECFG_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_NONE (_EUSART_FRAMECFG_PARITY_NONE << 8) /**< Shifted mode NONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_EVEN (_EUSART_FRAMECFG_PARITY_EVEN << 8) /**< Shifted mode EVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_ODD (_EUSART_FRAMECFG_PARITY_ODD << 8) /**< Shifted mode ODD for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_SHIFT 12 /**< Shift value for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_MASK 0x3000UL /**< Bit mask for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_HALF 0x00000000UL /**< Mode HALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONE 0x00000001UL /**< Mode ONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_TWO 0x00000003UL /**< Mode TWO for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_DEFAULT (_EUSART_FRAMECFG_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_HALF (_EUSART_FRAMECFG_STOPBITS_HALF << 12) /**< Shifted mode HALF for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONE (_EUSART_FRAMECFG_STOPBITS_ONE << 12) /**< Shifted mode ONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONEANDAHALF (_EUSART_FRAMECFG_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for EUSART_FRAMECFG*/ +#define EUSART_FRAMECFG_STOPBITS_TWO (_EUSART_FRAMECFG_STOPBITS_TWO << 12) /**< Shifted mode TWO for EUSART_FRAMECFG */ /* Bit fields for EUSART DTXDATCFG */ -#define _EUSART_DTXDATCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DTXDATCFG */ -#define _EUSART_DTXDATCFG_MASK 0x0000FFFFUL /**< Mask for EUSART_DTXDATCFG */ -#define _EUSART_DTXDATCFG_DTXDAT_SHIFT 0 /**< Shift value for EUSART_DTXDAT */ -#define _EUSART_DTXDATCFG_DTXDAT_MASK 0xFFFFUL /**< Bit mask for EUSART_DTXDAT */ -#define _EUSART_DTXDATCFG_DTXDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DTXDATCFG */ -#define EUSART_DTXDATCFG_DTXDAT_DEFAULT (_EUSART_DTXDATCFG_DTXDAT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_MASK 0x0000FFFFUL /**< Mask for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_DTXDAT_SHIFT 0 /**< Shift value for EUSART_DTXDAT */ +#define _EUSART_DTXDATCFG_DTXDAT_MASK 0xFFFFUL /**< Bit mask for EUSART_DTXDAT */ +#define _EUSART_DTXDATCFG_DTXDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DTXDATCFG */ +#define EUSART_DTXDATCFG_DTXDAT_DEFAULT (_EUSART_DTXDATCFG_DTXDAT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DTXDATCFG */ /* Bit fields for EUSART IRHFCFG */ -#define _EUSART_IRHFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_MASK 0x0000000FUL /**< Mask for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFEN (0x1UL << 0) /**< Enable IrDA Module */ -#define _EUSART_IRHFCFG_IRHFEN_SHIFT 0 /**< Shift value for EUSART_IRHFEN */ -#define _EUSART_IRHFCFG_IRHFEN_MASK 0x1UL /**< Bit mask for EUSART_IRHFEN */ -#define _EUSART_IRHFCFG_IRHFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFEN_DEFAULT (_EUSART_IRHFCFG_IRHFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_SHIFT 1 /**< Shift value for EUSART_IRHFPW */ -#define _EUSART_IRHFCFG_IRHFPW_MASK 0x6UL /**< Bit mask for EUSART_IRHFPW */ -#define _EUSART_IRHFCFG_IRHFPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_ONE 0x00000000UL /**< Mode ONE for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_TWO 0x00000001UL /**< Mode TWO for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_THREE 0x00000002UL /**< Mode THREE for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_FOUR 0x00000003UL /**< Mode FOUR for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_DEFAULT (_EUSART_IRHFCFG_IRHFPW_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_ONE (_EUSART_IRHFCFG_IRHFPW_ONE << 1) /**< Shifted mode ONE for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_TWO (_EUSART_IRHFCFG_IRHFPW_TWO << 1) /**< Shifted mode TWO for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_THREE (_EUSART_IRHFCFG_IRHFPW_THREE << 1) /**< Shifted mode THREE for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_FOUR (_EUSART_IRHFCFG_IRHFPW_FOUR << 1) /**< Shifted mode FOUR for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFFILT (0x1UL << 3) /**< IrDA RX Filter */ -#define _EUSART_IRHFCFG_IRHFFILT_SHIFT 3 /**< Shift value for EUSART_IRHFFILT */ -#define _EUSART_IRHFCFG_IRHFFILT_MASK 0x8UL /**< Bit mask for EUSART_IRHFFILT */ -#define _EUSART_IRHFCFG_IRHFFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFFILT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFFILT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFFILT_DEFAULT (_EUSART_IRHFCFG_IRHFFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFFILT_DISABLE (_EUSART_IRHFCFG_IRHFFILT_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFFILT_ENABLE (_EUSART_IRHFCFG_IRHFFILT_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_MASK 0x0000000FUL /**< Mask for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN (0x1UL << 0) /**< Enable IrDA Module */ +#define _EUSART_IRHFCFG_IRHFEN_SHIFT 0 /**< Shift value for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_MASK 0x1UL /**< Bit mask for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN_DEFAULT (_EUSART_IRHFCFG_IRHFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_SHIFT 1 /**< Shift value for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_MASK 0x6UL /**< Bit mask for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_ONE 0x00000000UL /**< Mode ONE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_TWO 0x00000001UL /**< Mode TWO for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_THREE 0x00000002UL /**< Mode THREE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_FOUR 0x00000003UL /**< Mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_DEFAULT (_EUSART_IRHFCFG_IRHFPW_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_ONE (_EUSART_IRHFCFG_IRHFPW_ONE << 1) /**< Shifted mode ONE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_TWO (_EUSART_IRHFCFG_IRHFPW_TWO << 1) /**< Shifted mode TWO for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_THREE (_EUSART_IRHFCFG_IRHFPW_THREE << 1) /**< Shifted mode THREE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_FOUR (_EUSART_IRHFCFG_IRHFPW_FOUR << 1) /**< Shifted mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _EUSART_IRHFCFG_IRHFFILT_SHIFT 3 /**< Shift value for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_MASK 0x8UL /**< Bit mask for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DEFAULT (_EUSART_IRHFCFG_IRHFFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DISABLE (_EUSART_IRHFCFG_IRHFFILT_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_ENABLE (_EUSART_IRHFCFG_IRHFFILT_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_IRHFCFG */ /* Bit fields for EUSART IRLFCFG */ -#define _EUSART_IRLFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRLFCFG */ -#define _EUSART_IRLFCFG_MASK 0x00000001UL /**< Mask for EUSART_IRLFCFG */ -#define EUSART_IRLFCFG_IRLFEN (0x1UL << 0) /**< Pulse Generator/Extender Enable */ -#define _EUSART_IRLFCFG_IRLFEN_SHIFT 0 /**< Shift value for EUSART_IRLFEN */ -#define _EUSART_IRLFCFG_IRLFEN_MASK 0x1UL /**< Bit mask for EUSART_IRLFEN */ -#define _EUSART_IRLFCFG_IRLFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRLFCFG */ -#define EUSART_IRLFCFG_IRLFEN_DEFAULT (_EUSART_IRLFCFG_IRLFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRLFCFG */ +#define _EUSART_IRLFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRLFCFG */ +#define _EUSART_IRLFCFG_MASK 0x00000001UL /**< Mask for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN (0x1UL << 0) /**< Pulse Generator/Extender Enable */ +#define _EUSART_IRLFCFG_IRLFEN_SHIFT 0 /**< Shift value for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_MASK 0x1UL /**< Bit mask for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN_DEFAULT (_EUSART_IRLFCFG_IRLFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRLFCFG */ /* Bit fields for EUSART TIMINGCFG */ -#define _EUSART_TIMINGCFG_RESETVALUE 0x00050000UL /**< Default value for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_MASK 0x000F7773UL /**< Mask for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_SHIFT 0 /**< Shift value for EUSART_TXDELAY */ -#define _EUSART_TIMINGCFG_TXDELAY_MASK 0x3UL /**< Bit mask for EUSART_TXDELAY */ -#define _EUSART_TIMINGCFG_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_NONE 0x00000000UL /**< Mode NONE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_TRIPPLE 0x00000003UL /**< Mode TRIPPLE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_DEFAULT (_EUSART_TIMINGCFG_TXDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_NONE (_EUSART_TIMINGCFG_TXDELAY_NONE << 0) /**< Shifted mode NONE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_SINGLE (_EUSART_TIMINGCFG_TXDELAY_SINGLE << 0) /**< Shifted mode SINGLE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_DOUBLE (_EUSART_TIMINGCFG_TXDELAY_DOUBLE << 0) /**< Shifted mode DOUBLE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_TRIPPLE (_EUSART_TIMINGCFG_TXDELAY_TRIPPLE << 0) /**< Shifted mode TRIPPLE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_SHIFT 4 /**< Shift value for EUSART_CSSETUP */ -#define _EUSART_TIMINGCFG_CSSETUP_MASK 0x70UL /**< Bit mask for EUSART_CSSETUP */ -#define _EUSART_TIMINGCFG_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_DEFAULT (_EUSART_TIMINGCFG_CSSETUP_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_ZERO (_EUSART_TIMINGCFG_CSSETUP_ZERO << 4) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_ONE (_EUSART_TIMINGCFG_CSSETUP_ONE << 4) /**< Shifted mode ONE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_TWO (_EUSART_TIMINGCFG_CSSETUP_TWO << 4) /**< Shifted mode TWO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_THREE (_EUSART_TIMINGCFG_CSSETUP_THREE << 4) /**< Shifted mode THREE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_FOUR (_EUSART_TIMINGCFG_CSSETUP_FOUR << 4) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_FIVE (_EUSART_TIMINGCFG_CSSETUP_FIVE << 4) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_SIX (_EUSART_TIMINGCFG_CSSETUP_SIX << 4) /**< Shifted mode SIX for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_SEVEN (_EUSART_TIMINGCFG_CSSETUP_SEVEN << 4) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_SHIFT 8 /**< Shift value for EUSART_CSHOLD */ -#define _EUSART_TIMINGCFG_CSHOLD_MASK 0x700UL /**< Bit mask for EUSART_CSHOLD */ -#define _EUSART_TIMINGCFG_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_DEFAULT (_EUSART_TIMINGCFG_CSHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_ZERO (_EUSART_TIMINGCFG_CSHOLD_ZERO << 8) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_ONE (_EUSART_TIMINGCFG_CSHOLD_ONE << 8) /**< Shifted mode ONE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_TWO (_EUSART_TIMINGCFG_CSHOLD_TWO << 8) /**< Shifted mode TWO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_THREE (_EUSART_TIMINGCFG_CSHOLD_THREE << 8) /**< Shifted mode THREE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_FOUR (_EUSART_TIMINGCFG_CSHOLD_FOUR << 8) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_FIVE (_EUSART_TIMINGCFG_CSHOLD_FIVE << 8) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_SIX (_EUSART_TIMINGCFG_CSHOLD_SIX << 8) /**< Shifted mode SIX for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_SEVEN (_EUSART_TIMINGCFG_CSHOLD_SEVEN << 8) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_SHIFT 12 /**< Shift value for EUSART_ICS */ -#define _EUSART_TIMINGCFG_ICS_MASK 0x7000UL /**< Bit mask for EUSART_ICS */ -#define _EUSART_TIMINGCFG_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_DEFAULT (_EUSART_TIMINGCFG_ICS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_ZERO (_EUSART_TIMINGCFG_ICS_ZERO << 12) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_ONE (_EUSART_TIMINGCFG_ICS_ONE << 12) /**< Shifted mode ONE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_TWO (_EUSART_TIMINGCFG_ICS_TWO << 12) /**< Shifted mode TWO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_THREE (_EUSART_TIMINGCFG_ICS_THREE << 12) /**< Shifted mode THREE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_FOUR (_EUSART_TIMINGCFG_ICS_FOUR << 12) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_FIVE (_EUSART_TIMINGCFG_ICS_FIVE << 12) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_SIX (_EUSART_TIMINGCFG_ICS_SIX << 12) /**< Shifted mode SIX for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_SEVEN (_EUSART_TIMINGCFG_ICS_SEVEN << 12) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT 16 /**< Shift value for EUSART_SETUPWINDOW */ -#define _EUSART_TIMINGCFG_SETUPWINDOW_MASK 0xF0000UL /**< Bit mask for EUSART_SETUPWINDOW */ -#define _EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT 0x00000005UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT (_EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_RESETVALUE 0x00050000UL /**< Default value for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_MASK 0x000F7773UL /**< Mask for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SHIFT 0 /**< Shift value for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_MASK 0x3UL /**< Bit mask for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_NONE 0x00000000UL /**< Mode NONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_TRIPPLE 0x00000003UL /**< Mode TRIPPLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DEFAULT (_EUSART_TIMINGCFG_TXDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_NONE (_EUSART_TIMINGCFG_TXDELAY_NONE << 0) /**< Shifted mode NONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_SINGLE (_EUSART_TIMINGCFG_TXDELAY_SINGLE << 0) /**< Shifted mode SINGLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DOUBLE (_EUSART_TIMINGCFG_TXDELAY_DOUBLE << 0) /**< Shifted mode DOUBLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_TRIPPLE (_EUSART_TIMINGCFG_TXDELAY_TRIPPLE << 0) /**< Shifted mode TRIPPLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SHIFT 4 /**< Shift value for EUSART_CSSETUP */ +#define _EUSART_TIMINGCFG_CSSETUP_MASK 0x70UL /**< Bit mask for EUSART_CSSETUP */ +#define _EUSART_TIMINGCFG_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_DEFAULT (_EUSART_TIMINGCFG_CSSETUP_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_ZERO (_EUSART_TIMINGCFG_CSSETUP_ZERO << 4) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_ONE (_EUSART_TIMINGCFG_CSSETUP_ONE << 4) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_TWO (_EUSART_TIMINGCFG_CSSETUP_TWO << 4) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_THREE (_EUSART_TIMINGCFG_CSSETUP_THREE << 4) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_FOUR (_EUSART_TIMINGCFG_CSSETUP_FOUR << 4) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_FIVE (_EUSART_TIMINGCFG_CSSETUP_FIVE << 4) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_SIX (_EUSART_TIMINGCFG_CSSETUP_SIX << 4) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_SEVEN (_EUSART_TIMINGCFG_CSSETUP_SEVEN << 4) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SHIFT 8 /**< Shift value for EUSART_CSHOLD */ +#define _EUSART_TIMINGCFG_CSHOLD_MASK 0x700UL /**< Bit mask for EUSART_CSHOLD */ +#define _EUSART_TIMINGCFG_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_DEFAULT (_EUSART_TIMINGCFG_CSHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_ZERO (_EUSART_TIMINGCFG_CSHOLD_ZERO << 8) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_ONE (_EUSART_TIMINGCFG_CSHOLD_ONE << 8) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_TWO (_EUSART_TIMINGCFG_CSHOLD_TWO << 8) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_THREE (_EUSART_TIMINGCFG_CSHOLD_THREE << 8) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_FOUR (_EUSART_TIMINGCFG_CSHOLD_FOUR << 8) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_FIVE (_EUSART_TIMINGCFG_CSHOLD_FIVE << 8) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_SIX (_EUSART_TIMINGCFG_CSHOLD_SIX << 8) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_SEVEN (_EUSART_TIMINGCFG_CSHOLD_SEVEN << 8) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SHIFT 12 /**< Shift value for EUSART_ICS */ +#define _EUSART_TIMINGCFG_ICS_MASK 0x7000UL /**< Bit mask for EUSART_ICS */ +#define _EUSART_TIMINGCFG_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_DEFAULT (_EUSART_TIMINGCFG_ICS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_ZERO (_EUSART_TIMINGCFG_ICS_ZERO << 12) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_ONE (_EUSART_TIMINGCFG_ICS_ONE << 12) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_TWO (_EUSART_TIMINGCFG_ICS_TWO << 12) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_THREE (_EUSART_TIMINGCFG_ICS_THREE << 12) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_FOUR (_EUSART_TIMINGCFG_ICS_FOUR << 12) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_FIVE (_EUSART_TIMINGCFG_ICS_FIVE << 12) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_SIX (_EUSART_TIMINGCFG_ICS_SIX << 12) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_SEVEN (_EUSART_TIMINGCFG_ICS_SEVEN << 12) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT 16 /**< Shift value for EUSART_SETUPWINDOW */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_MASK 0xF0000UL /**< Bit mask for EUSART_SETUPWINDOW */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT 0x00000005UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT (_EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ /* Bit fields for EUSART STARTFRAMECFG */ -#define _EUSART_STARTFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_STARTFRAMECFG */ -#define _EUSART_STARTFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_STARTFRAMECFG */ -#define _EUSART_STARTFRAMECFG_STARTFRAME_SHIFT 0 /**< Shift value for EUSART_STARTFRAME */ -#define _EUSART_STARTFRAMECFG_STARTFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_STARTFRAME */ -#define _EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STARTFRAMECFG */ -#define EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT (_EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STARTFRAMECFG*/ +#define _EUSART_STARTFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_SHIFT 0 /**< Shift value for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STARTFRAMECFG */ +#define EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT (_EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STARTFRAMECFG*/ /* Bit fields for EUSART SIGFRAMECFG */ -#define _EUSART_SIGFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_SIGFRAMECFG */ -#define _EUSART_SIGFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_SIGFRAMECFG */ -#define _EUSART_SIGFRAMECFG_SIGFRAME_SHIFT 0 /**< Shift value for EUSART_SIGFRAME */ -#define _EUSART_SIGFRAMECFG_SIGFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_SIGFRAME */ -#define _EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SIGFRAMECFG */ -#define EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT (_EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_SHIFT 0 /**< Shift value for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SIGFRAMECFG */ +#define EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT (_EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SIGFRAMECFG */ /* Bit fields for EUSART CLKDIV */ -#define _EUSART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for EUSART_CLKDIV */ -#define _EUSART_CLKDIV_MASK 0x007FFFF8UL /**< Mask for EUSART_CLKDIV */ -#define _EUSART_CLKDIV_DIV_SHIFT 3 /**< Shift value for EUSART_DIV */ -#define _EUSART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for EUSART_DIV */ -#define _EUSART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CLKDIV */ -#define EUSART_CLKDIV_DIV_DEFAULT (_EUSART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_MASK 0x007FFFF8UL /**< Mask for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_DIV_SHIFT 3 /**< Shift value for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CLKDIV */ +#define EUSART_CLKDIV_DIV_DEFAULT (_EUSART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CLKDIV */ /* Bit fields for EUSART TRIGCTRL */ -#define _EUSART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for EUSART_TRIGCTRL */ -#define _EUSART_TRIGCTRL_MASK 0x00000007UL /**< Mask for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_RXTEN (0x1UL << 0) /**< Receive Trigger Enable */ -#define _EUSART_TRIGCTRL_RXTEN_SHIFT 0 /**< Shift value for EUSART_RXTEN */ -#define _EUSART_TRIGCTRL_RXTEN_MASK 0x1UL /**< Bit mask for EUSART_RXTEN */ -#define _EUSART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_RXTEN_DEFAULT (_EUSART_TRIGCTRL_RXTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_TXTEN (0x1UL << 1) /**< Transmit Trigger Enable */ -#define _EUSART_TRIGCTRL_TXTEN_SHIFT 1 /**< Shift value for EUSART_TXTEN */ -#define _EUSART_TRIGCTRL_TXTEN_MASK 0x2UL /**< Bit mask for EUSART_TXTEN */ -#define _EUSART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_TXTEN_DEFAULT (_EUSART_TRIGCTRL_TXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_AUTOTXTEN (0x1UL << 2) /**< AUTOTX Trigger Enable */ -#define _EUSART_TRIGCTRL_AUTOTXTEN_SHIFT 2 /**< Shift value for EUSART_AUTOTXTEN */ -#define _EUSART_TRIGCTRL_AUTOTXTEN_MASK 0x4UL /**< Bit mask for EUSART_AUTOTXTEN */ -#define _EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT (_EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define _EUSART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for EUSART_TRIGCTRL */ +#define _EUSART_TRIGCTRL_MASK 0x00000007UL /**< Mask for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN (0x1UL << 0) /**< Receive Trigger Enable */ +#define _EUSART_TRIGCTRL_RXTEN_SHIFT 0 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_MASK 0x1UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN_DEFAULT (_EUSART_TRIGCTRL_RXTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN (0x1UL << 1) /**< Transmit Trigger Enable */ +#define _EUSART_TRIGCTRL_TXTEN_SHIFT 1 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_MASK 0x2UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN_DEFAULT (_EUSART_TRIGCTRL_TXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_AUTOTXTEN (0x1UL << 2) /**< AUTOTX Trigger Enable */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_SHIFT 2 /**< Shift value for EUSART_AUTOTXTEN */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_MASK 0x4UL /**< Bit mask for EUSART_AUTOTXTEN */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT (_EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ /* Bit fields for EUSART CMD */ -#define _EUSART_CMD_RESETVALUE 0x00000000UL /**< Default value for EUSART_CMD */ -#define _EUSART_CMD_MASK 0x000001FFUL /**< Mask for EUSART_CMD */ -#define EUSART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ -#define _EUSART_CMD_RXEN_SHIFT 0 /**< Shift value for EUSART_RXEN */ -#define _EUSART_CMD_RXEN_MASK 0x1UL /**< Bit mask for EUSART_RXEN */ -#define _EUSART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXEN_DEFAULT (_EUSART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ -#define _EUSART_CMD_RXDIS_SHIFT 1 /**< Shift value for EUSART_RXDIS */ -#define _EUSART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for EUSART_RXDIS */ -#define _EUSART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXDIS_DEFAULT (_EUSART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ -#define _EUSART_CMD_TXEN_SHIFT 2 /**< Shift value for EUSART_TXEN */ -#define _EUSART_CMD_TXEN_MASK 0x4UL /**< Bit mask for EUSART_TXEN */ -#define _EUSART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXEN_DEFAULT (_EUSART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ -#define _EUSART_CMD_TXDIS_SHIFT 3 /**< Shift value for EUSART_TXDIS */ -#define _EUSART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for EUSART_TXDIS */ -#define _EUSART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXDIS_DEFAULT (_EUSART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ -#define _EUSART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for EUSART_RXBLOCKEN */ -#define _EUSART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for EUSART_RXBLOCKEN */ -#define _EUSART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXBLOCKEN_DEFAULT (_EUSART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ -#define _EUSART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for EUSART_RXBLOCKDIS */ -#define _EUSART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for EUSART_RXBLOCKDIS */ -#define _EUSART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXBLOCKDIS_DEFAULT (_EUSART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXTRIEN (0x1UL << 6) /**< Transmitter Tristate Enable */ -#define _EUSART_CMD_TXTRIEN_SHIFT 6 /**< Shift value for EUSART_TXTRIEN */ -#define _EUSART_CMD_TXTRIEN_MASK 0x40UL /**< Bit mask for EUSART_TXTRIEN */ -#define _EUSART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXTRIEN_DEFAULT (_EUSART_CMD_TXTRIEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXTRIDIS (0x1UL << 7) /**< Transmitter Tristate Disable */ -#define _EUSART_CMD_TXTRIDIS_SHIFT 7 /**< Shift value for EUSART_TXTRIDIS */ -#define _EUSART_CMD_TXTRIDIS_MASK 0x80UL /**< Bit mask for EUSART_TXTRIDIS */ -#define _EUSART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXTRIDIS_DEFAULT (_EUSART_CMD_TXTRIDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_CLEARTX (0x1UL << 8) /**< Clear TX FIFO */ -#define _EUSART_CMD_CLEARTX_SHIFT 8 /**< Shift value for EUSART_CLEARTX */ -#define _EUSART_CMD_CLEARTX_MASK 0x100UL /**< Bit mask for EUSART_CLEARTX */ -#define _EUSART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_CLEARTX_DEFAULT (_EUSART_CMD_CLEARTX_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define _EUSART_CMD_RESETVALUE 0x00000000UL /**< Default value for EUSART_CMD */ +#define _EUSART_CMD_MASK 0x000001FFUL /**< Mask for EUSART_CMD */ +#define EUSART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _EUSART_CMD_RXEN_SHIFT 0 /**< Shift value for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_MASK 0x1UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXEN_DEFAULT (_EUSART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _EUSART_CMD_RXDIS_SHIFT 1 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS_DEFAULT (_EUSART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _EUSART_CMD_TXEN_SHIFT 2 /**< Shift value for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_MASK 0x4UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN_DEFAULT (_EUSART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _EUSART_CMD_TXDIS_SHIFT 3 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS_DEFAULT (_EUSART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ +#define _EUSART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN_DEFAULT (_EUSART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ +#define _EUSART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS_DEFAULT (_EUSART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN (0x1UL << 6) /**< Transmitter Tristate Enable */ +#define _EUSART_CMD_TXTRIEN_SHIFT 6 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_MASK 0x40UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN_DEFAULT (_EUSART_CMD_TXTRIEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS (0x1UL << 7) /**< Transmitter Tristate Disable */ +#define _EUSART_CMD_TXTRIDIS_SHIFT 7 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_MASK 0x80UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS_DEFAULT (_EUSART_CMD_TXTRIDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX (0x1UL << 8) /**< Clear TX FIFO */ +#define _EUSART_CMD_CLEARTX_SHIFT 8 /**< Shift value for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_MASK 0x100UL /**< Bit mask for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX_DEFAULT (_EUSART_CMD_CLEARTX_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_CMD */ /* Bit fields for EUSART RXDATA */ -#define _EUSART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATA */ -#define _EUSART_RXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATA */ -#define _EUSART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for EUSART_RXDATA */ -#define _EUSART_RXDATA_RXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATA */ -#define _EUSART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ -#define EUSART_RXDATA_RXDATA_DEFAULT (_EUSART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATA */ +#define _EUSART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATA */ +#define _EUSART_RXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ +#define EUSART_RXDATA_RXDATA_DEFAULT (_EUSART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATA */ /* Bit fields for EUSART RXDATAP */ -#define _EUSART_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATAP */ -#define _EUSART_RXDATAP_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATAP */ -#define _EUSART_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for EUSART_RXDATAP */ -#define _EUSART_RXDATAP_RXDATAP_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATAP */ -#define _EUSART_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ -#define EUSART_RXDATAP_RXDATAP_DEFAULT (_EUSART_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ +#define EUSART_RXDATAP_RXDATAP_DEFAULT (_EUSART_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ /* Bit fields for EUSART TXDATA */ -#define _EUSART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_TXDATA */ -#define _EUSART_TXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_TXDATA */ -#define _EUSART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for EUSART_TXDATA */ -#define _EUSART_TXDATA_TXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_TXDATA */ -#define _EUSART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ -#define EUSART_TXDATA_TXDATA_DEFAULT (_EUSART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TXDATA */ +#define _EUSART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_TXDATA */ +#define _EUSART_TXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_TXDATA_DEFAULT (_EUSART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TXDATA */ /* Bit fields for EUSART STATUS */ -#define _EUSART_STATUS_RESETVALUE 0x00003040UL /**< Default value for EUSART_STATUS */ -#define _EUSART_STATUS_MASK 0x031F31FBUL /**< Mask for EUSART_STATUS */ -#define EUSART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ -#define _EUSART_STATUS_RXENS_SHIFT 0 /**< Shift value for EUSART_RXENS */ -#define _EUSART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for EUSART_RXENS */ -#define _EUSART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXENS_DEFAULT (_EUSART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ -#define _EUSART_STATUS_TXENS_SHIFT 1 /**< Shift value for EUSART_TXENS */ -#define _EUSART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for EUSART_TXENS */ -#define _EUSART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXENS_DEFAULT (_EUSART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ -#define _EUSART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for EUSART_RXBLOCK */ -#define _EUSART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for EUSART_RXBLOCK */ -#define _EUSART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXBLOCK_DEFAULT (_EUSART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ -#define _EUSART_STATUS_TXTRI_SHIFT 4 /**< Shift value for EUSART_TXTRI */ -#define _EUSART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for EUSART_TXTRI */ -#define _EUSART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXTRI_DEFAULT (_EUSART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ -#define _EUSART_STATUS_TXC_SHIFT 5 /**< Shift value for EUSART_TXC */ -#define _EUSART_STATUS_TXC_MASK 0x20UL /**< Bit mask for EUSART_TXC */ -#define _EUSART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXC_DEFAULT (_EUSART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXFL (0x1UL << 6) /**< TX FIFO Level */ -#define _EUSART_STATUS_TXFL_SHIFT 6 /**< Shift value for EUSART_TXFL */ -#define _EUSART_STATUS_TXFL_MASK 0x40UL /**< Bit mask for EUSART_TXFL */ -#define _EUSART_STATUS_TXFL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXFL_DEFAULT (_EUSART_STATUS_TXFL_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXFL (0x1UL << 7) /**< RX FIFO Level */ -#define _EUSART_STATUS_RXFL_SHIFT 7 /**< Shift value for EUSART_RXFL */ -#define _EUSART_STATUS_RXFL_MASK 0x80UL /**< Bit mask for EUSART_RXFL */ -#define _EUSART_STATUS_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXFL_DEFAULT (_EUSART_STATUS_RXFL_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ -#define _EUSART_STATUS_RXFULL_SHIFT 8 /**< Shift value for EUSART_RXFULL */ -#define _EUSART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for EUSART_RXFULL */ -#define _EUSART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXFULL_DEFAULT (_EUSART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXIDLE (0x1UL << 12) /**< RX Idle */ -#define _EUSART_STATUS_RXIDLE_SHIFT 12 /**< Shift value for EUSART_RXIDLE */ -#define _EUSART_STATUS_RXIDLE_MASK 0x1000UL /**< Bit mask for EUSART_RXIDLE */ -#define _EUSART_STATUS_RXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXIDLE_DEFAULT (_EUSART_STATUS_RXIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ -#define _EUSART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ -#define _EUSART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ -#define _EUSART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXIDLE_DEFAULT (_EUSART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define _EUSART_STATUS_TXFCNT_SHIFT 16 /**< Shift value for EUSART_TXFCNT */ -#define _EUSART_STATUS_TXFCNT_MASK 0x1F0000UL /**< Bit mask for EUSART_TXFCNT */ -#define _EUSART_STATUS_TXFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXFCNT_DEFAULT (_EUSART_STATUS_TXFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Rate Detection Completed */ -#define _EUSART_STATUS_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ -#define _EUSART_STATUS_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ -#define _EUSART_STATUS_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_AUTOBAUDDONE_DEFAULT (_EUSART_STATUS_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_CLEARTXBUSY (0x1UL << 25) /**< TX FIFO Clear Busy */ -#define _EUSART_STATUS_CLEARTXBUSY_SHIFT 25 /**< Shift value for EUSART_CLEARTXBUSY */ -#define _EUSART_STATUS_CLEARTXBUSY_MASK 0x2000000UL /**< Bit mask for EUSART_CLEARTXBUSY */ -#define _EUSART_STATUS_CLEARTXBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_CLEARTXBUSY_DEFAULT (_EUSART_STATUS_CLEARTXBUSY_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define _EUSART_STATUS_RESETVALUE 0x00003040UL /**< Default value for EUSART_STATUS */ +#define _EUSART_STATUS_MASK 0x031F31FBUL /**< Mask for EUSART_STATUS */ +#define EUSART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _EUSART_STATUS_RXENS_SHIFT 0 /**< Shift value for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXENS_DEFAULT (_EUSART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _EUSART_STATUS_TXENS_SHIFT 1 /**< Shift value for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS_DEFAULT (_EUSART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _EUSART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK_DEFAULT (_EUSART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _EUSART_STATUS_TXTRI_SHIFT 4 /**< Shift value for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI_DEFAULT (_EUSART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _EUSART_STATUS_TXC_SHIFT 5 /**< Shift value for EUSART_TXC */ +#define _EUSART_STATUS_TXC_MASK 0x20UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC_DEFAULT (_EUSART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL (0x1UL << 6) /**< TX FIFO Level */ +#define _EUSART_STATUS_TXFL_SHIFT 6 /**< Shift value for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_MASK 0x40UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL_DEFAULT (_EUSART_STATUS_TXFL_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL (0x1UL << 7) /**< RX FIFO Level */ +#define _EUSART_STATUS_RXFL_SHIFT 7 /**< Shift value for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_MASK 0x80UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL_DEFAULT (_EUSART_STATUS_RXFL_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _EUSART_STATUS_RXFULL_SHIFT 8 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL_DEFAULT (_EUSART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE (0x1UL << 12) /**< RX Idle */ +#define _EUSART_STATUS_RXIDLE_SHIFT 12 /**< Shift value for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_MASK 0x1000UL /**< Bit mask for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE_DEFAULT (_EUSART_STATUS_RXIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _EUSART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE_DEFAULT (_EUSART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define _EUSART_STATUS_TXFCNT_SHIFT 16 /**< Shift value for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_MASK 0x1F0000UL /**< Bit mask for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFCNT_DEFAULT (_EUSART_STATUS_TXFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Rate Detection Completed */ +#define _EUSART_STATUS_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE_DEFAULT (_EUSART_STATUS_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY (0x1UL << 25) /**< TX FIFO Clear Busy */ +#define _EUSART_STATUS_CLEARTXBUSY_SHIFT 25 /**< Shift value for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_MASK 0x2000000UL /**< Bit mask for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY_DEFAULT (_EUSART_STATUS_CLEARTXBUSY_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_STATUS */ /* Bit fields for EUSART IF */ -#define _EUSART_IF_RESETVALUE 0x00000000UL /**< Default value for EUSART_IF */ -#define _EUSART_IF_MASK 0x030D3FFFUL /**< Mask for EUSART_IF */ -#define EUSART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ -#define _EUSART_IF_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ -#define _EUSART_IF_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ -#define _EUSART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXC_DEFAULT (_EUSART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXFL (0x1UL << 1) /**< TX FIFO Level Interrupt Flag */ -#define _EUSART_IF_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ -#define _EUSART_IF_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ -#define _EUSART_IF_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXFL_DEFAULT (_EUSART_IF_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXFL (0x1UL << 2) /**< RX FIFO Level Interrupt Flag */ -#define _EUSART_IF_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ -#define _EUSART_IF_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ -#define _EUSART_IF_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXFL_DEFAULT (_EUSART_IF_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXFULL (0x1UL << 3) /**< RX FIFO Full Interrupt Flag */ -#define _EUSART_IF_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ -#define _EUSART_IF_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ -#define _EUSART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXFULL_DEFAULT (_EUSART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXOF (0x1UL << 4) /**< RX FIFO Overflow Interrupt Flag */ -#define _EUSART_IF_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ -#define _EUSART_IF_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ -#define _EUSART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXOF_DEFAULT (_EUSART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXUF (0x1UL << 5) /**< RX FIFO Underflow Interrupt Flag */ -#define _EUSART_IF_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ -#define _EUSART_IF_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ -#define _EUSART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXUF_DEFAULT (_EUSART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXOF (0x1UL << 6) /**< TX FIFO Overflow Interrupt Flag */ -#define _EUSART_IF_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ -#define _EUSART_IF_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ -#define _EUSART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXOF_DEFAULT (_EUSART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXUF (0x1UL << 7) /**< TX FIFO Underflow Interrupt Flag */ -#define _EUSART_IF_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ -#define _EUSART_IF_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ -#define _EUSART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXUF_DEFAULT (_EUSART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ -#define _EUSART_IF_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ -#define _EUSART_IF_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ -#define _EUSART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_PERR_DEFAULT (_EUSART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ -#define _EUSART_IF_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ -#define _EUSART_IF_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ -#define _EUSART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_FERR_DEFAULT (_EUSART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ -#define _EUSART_IF_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ -#define _EUSART_IF_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ -#define _EUSART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_MPAF_DEFAULT (_EUSART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_LOADERR (0x1UL << 11) /**< Load Error Interrupt Flag */ -#define _EUSART_IF_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ -#define _EUSART_IF_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ -#define _EUSART_IF_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_LOADERR_DEFAULT (_EUSART_IF_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ -#define _EUSART_IF_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ -#define _EUSART_IF_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ -#define _EUSART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_CCF_DEFAULT (_EUSART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ -#define _EUSART_IF_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ -#define _EUSART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ -#define _EUSART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXIDLE_DEFAULT (_EUSART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_CSWU (0x1UL << 16) /**< CS Wake-up Interrupt Flag */ -#define _EUSART_IF_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ -#define _EUSART_IF_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ -#define _EUSART_IF_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_CSWU_DEFAULT (_EUSART_IF_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_STARTF (0x1UL << 18) /**< Start Frame Interrupt Flag */ -#define _EUSART_IF_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ -#define _EUSART_IF_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ -#define _EUSART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_STARTF_DEFAULT (_EUSART_IF_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_SIGF (0x1UL << 19) /**< Signal Frame Interrupt Flag */ -#define _EUSART_IF_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ -#define _EUSART_IF_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ -#define _EUSART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_SIGF_DEFAULT (_EUSART_IF_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Interrupt Flag */ -#define _EUSART_IF_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ -#define _EUSART_IF_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ -#define _EUSART_IF_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_AUTOBAUDDONE_DEFAULT (_EUSART_IF_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXTO (0x1UL << 25) /**< RX Timeout Interrupt Flag */ -#define _EUSART_IF_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ -#define _EUSART_IF_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ -#define _EUSART_IF_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXTO_DEFAULT (_EUSART_IF_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IF */ +#define _EUSART_IF_RESETVALUE 0x00000000UL /**< Default value for EUSART_IF */ +#define _EUSART_IF_MASK 0x030D3FFFUL /**< Mask for EUSART_IF */ +#define EUSART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _EUSART_IF_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IF_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXC_DEFAULT (_EUSART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL (0x1UL << 1) /**< TX FIFO Level Interrupt Flag */ +#define _EUSART_IF_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IF_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IF_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL_DEFAULT (_EUSART_IF_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL (0x1UL << 2) /**< RX FIFO Level Interrupt Flag */ +#define _EUSART_IF_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IF_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IF_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL_DEFAULT (_EUSART_IF_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL (0x1UL << 3) /**< RX FIFO Full Interrupt Flag */ +#define _EUSART_IF_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL_DEFAULT (_EUSART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF (0x1UL << 4) /**< RX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IF_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF_DEFAULT (_EUSART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF (0x1UL << 5) /**< RX FIFO Underflow Interrupt Flag */ +#define _EUSART_IF_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IF_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF_DEFAULT (_EUSART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF (0x1UL << 6) /**< TX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IF_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF_DEFAULT (_EUSART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXUF (0x1UL << 7) /**< TX FIFO Underflow Interrupt Flag */ +#define _EUSART_IF_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ +#define _EUSART_IF_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ +#define _EUSART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXUF_DEFAULT (_EUSART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _EUSART_IF_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IF_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR_DEFAULT (_EUSART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _EUSART_IF_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IF_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR_DEFAULT (_EUSART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _EUSART_IF_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IF_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF_DEFAULT (_EUSART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_LOADERR (0x1UL << 11) /**< Load Error Interrupt Flag */ +#define _EUSART_IF_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ +#define _EUSART_IF_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ +#define _EUSART_IF_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_LOADERR_DEFAULT (_EUSART_IF_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _EUSART_IF_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IF_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF_DEFAULT (_EUSART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _EUSART_IF_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE_DEFAULT (_EUSART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CSWU (0x1UL << 16) /**< CS Wake-up Interrupt Flag */ +#define _EUSART_IF_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ +#define _EUSART_IF_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ +#define _EUSART_IF_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CSWU_DEFAULT (_EUSART_IF_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF (0x1UL << 18) /**< Start Frame Interrupt Flag */ +#define _EUSART_IF_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IF_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF_DEFAULT (_EUSART_IF_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF (0x1UL << 19) /**< Signal Frame Interrupt Flag */ +#define _EUSART_IF_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IF_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF_DEFAULT (_EUSART_IF_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Interrupt Flag */ +#define _EUSART_IF_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE_DEFAULT (_EUSART_IF_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXTO (0x1UL << 25) /**< RX Timeout Interrupt Flag */ +#define _EUSART_IF_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ +#define _EUSART_IF_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ +#define _EUSART_IF_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXTO_DEFAULT (_EUSART_IF_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IF */ /* Bit fields for EUSART IEN */ -#define _EUSART_IEN_RESETVALUE 0x00000000UL /**< Default value for EUSART_IEN */ -#define _EUSART_IEN_MASK 0x030D3FFFUL /**< Mask for EUSART_IEN */ -#define EUSART_IEN_TXC (0x1UL << 0) /**< TX Complete Enable */ -#define _EUSART_IEN_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ -#define _EUSART_IEN_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ -#define _EUSART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXC_DEFAULT (_EUSART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXFL (0x1UL << 1) /**< TX FIFO Level Enable */ -#define _EUSART_IEN_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ -#define _EUSART_IEN_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ -#define _EUSART_IEN_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXFL_DEFAULT (_EUSART_IEN_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXFL (0x1UL << 2) /**< RX FIFO Level Enable */ -#define _EUSART_IEN_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ -#define _EUSART_IEN_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ -#define _EUSART_IEN_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXFL_DEFAULT (_EUSART_IEN_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXFULL (0x1UL << 3) /**< RX FIFO Full Enable */ -#define _EUSART_IEN_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ -#define _EUSART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ -#define _EUSART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXFULL_DEFAULT (_EUSART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXOF (0x1UL << 4) /**< RX FIFO Overflow Enable */ -#define _EUSART_IEN_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ -#define _EUSART_IEN_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ -#define _EUSART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXOF_DEFAULT (_EUSART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXUF (0x1UL << 5) /**< RX FIFO Underflow Enable */ -#define _EUSART_IEN_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ -#define _EUSART_IEN_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ -#define _EUSART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXUF_DEFAULT (_EUSART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXOF (0x1UL << 6) /**< TX FIFO Overflow Enable */ -#define _EUSART_IEN_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ -#define _EUSART_IEN_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ -#define _EUSART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXOF_DEFAULT (_EUSART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXUF (0x1UL << 7) /**< TX FIFO Underflow Enable */ -#define _EUSART_IEN_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ -#define _EUSART_IEN_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ -#define _EUSART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXUF_DEFAULT (_EUSART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_PERR (0x1UL << 8) /**< Parity Error Enable */ -#define _EUSART_IEN_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ -#define _EUSART_IEN_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ -#define _EUSART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_PERR_DEFAULT (_EUSART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_FERR (0x1UL << 9) /**< Framing Error Enable */ -#define _EUSART_IEN_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ -#define _EUSART_IEN_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ -#define _EUSART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_FERR_DEFAULT (_EUSART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Addr Frame Enable */ -#define _EUSART_IEN_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ -#define _EUSART_IEN_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ -#define _EUSART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_MPAF_DEFAULT (_EUSART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_LOADERR (0x1UL << 11) /**< Load Error Enable */ -#define _EUSART_IEN_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ -#define _EUSART_IEN_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ -#define _EUSART_IEN_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_LOADERR_DEFAULT (_EUSART_IEN_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Enable */ -#define _EUSART_IEN_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ -#define _EUSART_IEN_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ -#define _EUSART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_CCF_DEFAULT (_EUSART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXIDLE (0x1UL << 13) /**< TX IDLE Enable */ -#define _EUSART_IEN_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ -#define _EUSART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ -#define _EUSART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXIDLE_DEFAULT (_EUSART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_CSWU (0x1UL << 16) /**< CS Wake-up Enable */ -#define _EUSART_IEN_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ -#define _EUSART_IEN_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ -#define _EUSART_IEN_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_CSWU_DEFAULT (_EUSART_IEN_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_STARTF (0x1UL << 18) /**< Start Frame Enable */ -#define _EUSART_IEN_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ -#define _EUSART_IEN_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ -#define _EUSART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_STARTF_DEFAULT (_EUSART_IEN_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_SIGF (0x1UL << 19) /**< Signal Frame Enable */ -#define _EUSART_IEN_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ -#define _EUSART_IEN_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ -#define _EUSART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_SIGF_DEFAULT (_EUSART_IEN_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Enable */ -#define _EUSART_IEN_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ -#define _EUSART_IEN_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ -#define _EUSART_IEN_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_AUTOBAUDDONE_DEFAULT (_EUSART_IEN_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXTO (0x1UL << 25) /**< RX Timeout Enable */ -#define _EUSART_IEN_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ -#define _EUSART_IEN_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ -#define _EUSART_IEN_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXTO_DEFAULT (_EUSART_IEN_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define _EUSART_IEN_RESETVALUE 0x00000000UL /**< Default value for EUSART_IEN */ +#define _EUSART_IEN_MASK 0x030D3FFFUL /**< Mask for EUSART_IEN */ +#define EUSART_IEN_TXC (0x1UL << 0) /**< TX Complete Enable */ +#define _EUSART_IEN_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IEN_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXC_DEFAULT (_EUSART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL (0x1UL << 1) /**< TX FIFO Level Enable */ +#define _EUSART_IEN_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL_DEFAULT (_EUSART_IEN_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL (0x1UL << 2) /**< RX FIFO Level Enable */ +#define _EUSART_IEN_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL_DEFAULT (_EUSART_IEN_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL (0x1UL << 3) /**< RX FIFO Full Enable */ +#define _EUSART_IEN_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL_DEFAULT (_EUSART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF (0x1UL << 4) /**< RX FIFO Overflow Enable */ +#define _EUSART_IEN_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF_DEFAULT (_EUSART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF (0x1UL << 5) /**< RX FIFO Underflow Enable */ +#define _EUSART_IEN_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF_DEFAULT (_EUSART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF (0x1UL << 6) /**< TX FIFO Overflow Enable */ +#define _EUSART_IEN_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF_DEFAULT (_EUSART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXUF (0x1UL << 7) /**< TX FIFO Underflow Enable */ +#define _EUSART_IEN_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ +#define _EUSART_IEN_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ +#define _EUSART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXUF_DEFAULT (_EUSART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR (0x1UL << 8) /**< Parity Error Enable */ +#define _EUSART_IEN_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IEN_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR_DEFAULT (_EUSART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR (0x1UL << 9) /**< Framing Error Enable */ +#define _EUSART_IEN_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IEN_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR_DEFAULT (_EUSART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Addr Frame Enable */ +#define _EUSART_IEN_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF_DEFAULT (_EUSART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_LOADERR (0x1UL << 11) /**< Load Error Enable */ +#define _EUSART_IEN_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ +#define _EUSART_IEN_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ +#define _EUSART_IEN_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_LOADERR_DEFAULT (_EUSART_IEN_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Enable */ +#define _EUSART_IEN_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IEN_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF_DEFAULT (_EUSART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE (0x1UL << 13) /**< TX IDLE Enable */ +#define _EUSART_IEN_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE_DEFAULT (_EUSART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CSWU (0x1UL << 16) /**< CS Wake-up Enable */ +#define _EUSART_IEN_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ +#define _EUSART_IEN_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ +#define _EUSART_IEN_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CSWU_DEFAULT (_EUSART_IEN_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF (0x1UL << 18) /**< Start Frame Enable */ +#define _EUSART_IEN_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF_DEFAULT (_EUSART_IEN_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF (0x1UL << 19) /**< Signal Frame Enable */ +#define _EUSART_IEN_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF_DEFAULT (_EUSART_IEN_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Enable */ +#define _EUSART_IEN_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE_DEFAULT (_EUSART_IEN_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXTO (0x1UL << 25) /**< RX Timeout Enable */ +#define _EUSART_IEN_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ +#define _EUSART_IEN_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ +#define _EUSART_IEN_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXTO_DEFAULT (_EUSART_IEN_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IEN */ /* Bit fields for EUSART SYNCBUSY */ -#define _EUSART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for EUSART_SYNCBUSY */ -#define _EUSART_SYNCBUSY_MASK 0x00000FFFUL /**< Mask for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_DIV (0x1UL << 0) /**< SYNCBUSY for DIV in CLKDIV */ -#define _EUSART_SYNCBUSY_DIV_SHIFT 0 /**< Shift value for EUSART_DIV */ -#define _EUSART_SYNCBUSY_DIV_MASK 0x1UL /**< Bit mask for EUSART_DIV */ -#define _EUSART_SYNCBUSY_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_DIV_DEFAULT (_EUSART_SYNCBUSY_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXTEN (0x1UL << 1) /**< SYNCBUSY for RXTEN in TRIGCTRL */ -#define _EUSART_SYNCBUSY_RXTEN_SHIFT 1 /**< Shift value for EUSART_RXTEN */ -#define _EUSART_SYNCBUSY_RXTEN_MASK 0x2UL /**< Bit mask for EUSART_RXTEN */ -#define _EUSART_SYNCBUSY_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXTEN_DEFAULT (_EUSART_SYNCBUSY_RXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTEN (0x1UL << 2) /**< SYNCBUSY for TXTEN in TRIGCTRL */ -#define _EUSART_SYNCBUSY_TXTEN_SHIFT 2 /**< Shift value for EUSART_TXTEN */ -#define _EUSART_SYNCBUSY_TXTEN_MASK 0x4UL /**< Bit mask for EUSART_TXTEN */ -#define _EUSART_SYNCBUSY_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTEN_DEFAULT (_EUSART_SYNCBUSY_TXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXEN (0x1UL << 3) /**< SYNCBUSY for RXEN in CMD */ -#define _EUSART_SYNCBUSY_RXEN_SHIFT 3 /**< Shift value for EUSART_RXEN */ -#define _EUSART_SYNCBUSY_RXEN_MASK 0x8UL /**< Bit mask for EUSART_RXEN */ -#define _EUSART_SYNCBUSY_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXEN_DEFAULT (_EUSART_SYNCBUSY_RXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXDIS (0x1UL << 4) /**< SYNCBUSY for RXDIS in CMD */ -#define _EUSART_SYNCBUSY_RXDIS_SHIFT 4 /**< Shift value for EUSART_RXDIS */ -#define _EUSART_SYNCBUSY_RXDIS_MASK 0x10UL /**< Bit mask for EUSART_RXDIS */ -#define _EUSART_SYNCBUSY_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXDIS_DEFAULT (_EUSART_SYNCBUSY_RXDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXEN (0x1UL << 5) /**< SYNCBUSY for TXEN in CMD */ -#define _EUSART_SYNCBUSY_TXEN_SHIFT 5 /**< Shift value for EUSART_TXEN */ -#define _EUSART_SYNCBUSY_TXEN_MASK 0x20UL /**< Bit mask for EUSART_TXEN */ -#define _EUSART_SYNCBUSY_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXEN_DEFAULT (_EUSART_SYNCBUSY_TXEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXDIS (0x1UL << 6) /**< SYNCBUSY for TXDIS in CMD */ -#define _EUSART_SYNCBUSY_TXDIS_SHIFT 6 /**< Shift value for EUSART_TXDIS */ -#define _EUSART_SYNCBUSY_TXDIS_MASK 0x40UL /**< Bit mask for EUSART_TXDIS */ -#define _EUSART_SYNCBUSY_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXDIS_DEFAULT (_EUSART_SYNCBUSY_TXDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXBLOCKEN (0x1UL << 7) /**< SYNCBUSY for RXBLOCKEN in CMD */ -#define _EUSART_SYNCBUSY_RXBLOCKEN_SHIFT 7 /**< Shift value for EUSART_RXBLOCKEN */ -#define _EUSART_SYNCBUSY_RXBLOCKEN_MASK 0x80UL /**< Bit mask for EUSART_RXBLOCKEN */ -#define _EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXBLOCKDIS (0x1UL << 8) /**< SYNCBUSY for RXBLOCKDIS in CMD */ -#define _EUSART_SYNCBUSY_RXBLOCKDIS_SHIFT 8 /**< Shift value for EUSART_RXBLOCKDIS */ -#define _EUSART_SYNCBUSY_RXBLOCKDIS_MASK 0x100UL /**< Bit mask for EUSART_RXBLOCKDIS */ -#define _EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTRIEN (0x1UL << 9) /**< SYNCBUSY for TXTRIEN in CMD */ -#define _EUSART_SYNCBUSY_TXTRIEN_SHIFT 9 /**< Shift value for EUSART_TXTRIEN */ -#define _EUSART_SYNCBUSY_TXTRIEN_MASK 0x200UL /**< Bit mask for EUSART_TXTRIEN */ -#define _EUSART_SYNCBUSY_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTRIEN_DEFAULT (_EUSART_SYNCBUSY_TXTRIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTRIDIS (0x1UL << 10) /**< SYNCBUSY in TXTRIDIS in CMD */ -#define _EUSART_SYNCBUSY_TXTRIDIS_SHIFT 10 /**< Shift value for EUSART_TXTRIDIS */ -#define _EUSART_SYNCBUSY_TXTRIDIS_MASK 0x400UL /**< Bit mask for EUSART_TXTRIDIS */ -#define _EUSART_SYNCBUSY_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTRIDIS_DEFAULT (_EUSART_SYNCBUSY_TXTRIDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_AUTOTXTEN (0x1UL << 11) /**< SYNCBUSY for AUTOTXTEN in TRIGCTRL */ -#define _EUSART_SYNCBUSY_AUTOTXTEN_SHIFT 11 /**< Shift value for EUSART_AUTOTXTEN */ -#define _EUSART_SYNCBUSY_AUTOTXTEN_MASK 0x800UL /**< Bit mask for EUSART_AUTOTXTEN */ -#define _EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT (_EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define _EUSART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for EUSART_SYNCBUSY */ +#define _EUSART_SYNCBUSY_MASK 0x00000FFFUL /**< Mask for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV (0x1UL << 0) /**< SYNCBUSY for DIV in CLKDIV */ +#define _EUSART_SYNCBUSY_DIV_SHIFT 0 /**< Shift value for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_MASK 0x1UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV_DEFAULT (_EUSART_SYNCBUSY_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN (0x1UL << 1) /**< SYNCBUSY for RXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_RXTEN_SHIFT 1 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_MASK 0x2UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN_DEFAULT (_EUSART_SYNCBUSY_RXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN (0x1UL << 2) /**< SYNCBUSY for TXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_TXTEN_SHIFT 2 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_MASK 0x4UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN_DEFAULT (_EUSART_SYNCBUSY_TXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN (0x1UL << 3) /**< SYNCBUSY for RXEN in CMD */ +#define _EUSART_SYNCBUSY_RXEN_SHIFT 3 /**< Shift value for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_MASK 0x8UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN_DEFAULT (_EUSART_SYNCBUSY_RXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS (0x1UL << 4) /**< SYNCBUSY for RXDIS in CMD */ +#define _EUSART_SYNCBUSY_RXDIS_SHIFT 4 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_MASK 0x10UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS_DEFAULT (_EUSART_SYNCBUSY_RXDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN (0x1UL << 5) /**< SYNCBUSY for TXEN in CMD */ +#define _EUSART_SYNCBUSY_TXEN_SHIFT 5 /**< Shift value for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_MASK 0x20UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN_DEFAULT (_EUSART_SYNCBUSY_TXEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS (0x1UL << 6) /**< SYNCBUSY for TXDIS in CMD */ +#define _EUSART_SYNCBUSY_TXDIS_SHIFT 6 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_MASK 0x40UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS_DEFAULT (_EUSART_SYNCBUSY_TXDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN (0x1UL << 7) /**< SYNCBUSY for RXBLOCKEN in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_SHIFT 7 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_MASK 0x80UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS (0x1UL << 8) /**< SYNCBUSY for RXBLOCKDIS in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_SHIFT 8 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_MASK 0x100UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN (0x1UL << 9) /**< SYNCBUSY for TXTRIEN in CMD */ +#define _EUSART_SYNCBUSY_TXTRIEN_SHIFT 9 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_MASK 0x200UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN_DEFAULT (_EUSART_SYNCBUSY_TXTRIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS (0x1UL << 10) /**< SYNCBUSY in TXTRIDIS in CMD */ +#define _EUSART_SYNCBUSY_TXTRIDIS_SHIFT 10 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_MASK 0x400UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS_DEFAULT (_EUSART_SYNCBUSY_TXTRIDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_AUTOTXTEN (0x1UL << 11) /**< SYNCBUSY for AUTOTXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_SHIFT 11 /**< Shift value for EUSART_AUTOTXTEN */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_MASK 0x800UL /**< Bit mask for EUSART_AUTOTXTEN */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT (_EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ /** @} End of group EFR32SG28_EUSART_BitFields */ /** @} End of group EFR32SG28_EUSART */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_fsrco.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_fsrco.h index 75fe8efc98..1f4f86e3d6 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_fsrco.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_FSRCO_H #define EFR32SG28_FSRCO_H - #define FSRCO_HAS_SET_CLEAR /**************************************************************************//** @@ -43,15 +42,14 @@ *****************************************************************************/ /** FSRCO Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP Version */ - uint32_t RESERVED0[1023U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - uint32_t RESERVED1[1023U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - uint32_t RESERVED2[1023U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + uint32_t RESERVED0[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + uint32_t RESERVED1[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + uint32_t RESERVED2[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ } FSRCO_TypeDef; /** @} End of group EFR32SG28_FSRCO */ @@ -63,12 +61,12 @@ typedef struct *****************************************************************************/ /* Bit fields for FSRCO IPVERSION */ -#define _FSRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for FSRCO_IPVERSION */ -#define _FSRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for FSRCO_IPVERSION */ -#define _FSRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for FSRCO_IPVERSION */ -#define _FSRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for FSRCO_IPVERSION */ -#define _FSRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for FSRCO_IPVERSION */ -#define FSRCO_IPVERSION_IPVERSION_DEFAULT (_FSRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for FSRCO_IPVERSION */ +#define FSRCO_IPVERSION_IPVERSION_DEFAULT (_FSRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for FSRCO_IPVERSION */ /** @} End of group EFR32SG28_FSRCO_BitFields */ /** @} End of group EFR32SG28_FSRCO */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpcrc.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpcrc.h index 356d50cf3c..53dc1a1a8a 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpcrc.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_GPCRC_H #define EFR32SG28_GPCRC_H - #define GPCRC_HAS_SET_CLEAR /**************************************************************************//** @@ -43,59 +42,58 @@ *****************************************************************************/ /** GPCRC Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP Version ID */ - __IOM uint32_t EN; /**< CRC Enable */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IOM uint32_t INIT; /**< CRC Init Value */ - __IOM uint32_t POLY; /**< CRC Polynomial Value */ - __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ - __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ - __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ - __IM uint32_t DATA; /**< CRC Data Register */ - __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ - __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ - uint32_t RESERVED0[1012U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version ID */ - __IOM uint32_t EN_SET; /**< CRC Enable */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IOM uint32_t INIT_SET; /**< CRC Init Value */ - __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */ - __IOM uint32_t INPUTDATA_SET; /**< Input 32-bit Data Register */ - __IOM uint32_t INPUTDATAHWORD_SET; /**< Input 16-bit Data Register */ - __IOM uint32_t INPUTDATABYTE_SET; /**< Input 8-bit Data Register */ - __IM uint32_t DATA_SET; /**< CRC Data Register */ - __IM uint32_t DATAREV_SET; /**< CRC Data Reverse Register */ - __IM uint32_t DATABYTEREV_SET; /**< CRC Data Byte Reverse Register */ - uint32_t RESERVED1[1012U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ - __IOM uint32_t EN_CLR; /**< CRC Enable */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IOM uint32_t INIT_CLR; /**< CRC Init Value */ - __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */ - __IOM uint32_t INPUTDATA_CLR; /**< Input 32-bit Data Register */ - __IOM uint32_t INPUTDATAHWORD_CLR; /**< Input 16-bit Data Register */ - __IOM uint32_t INPUTDATABYTE_CLR; /**< Input 8-bit Data Register */ - __IM uint32_t DATA_CLR; /**< CRC Data Register */ - __IM uint32_t DATAREV_CLR; /**< CRC Data Reverse Register */ - __IM uint32_t DATABYTEREV_CLR; /**< CRC Data Byte Reverse Register */ - uint32_t RESERVED2[1012U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ - __IOM uint32_t EN_TGL; /**< CRC Enable */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IOM uint32_t INIT_TGL; /**< CRC Init Value */ - __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */ - __IOM uint32_t INPUTDATA_TGL; /**< Input 32-bit Data Register */ - __IOM uint32_t INPUTDATAHWORD_TGL; /**< Input 16-bit Data Register */ - __IOM uint32_t INPUTDATABYTE_TGL; /**< Input 8-bit Data Register */ - __IM uint32_t DATA_TGL; /**< CRC Data Register */ - __IM uint32_t DATAREV_TGL; /**< CRC Data Reverse Register */ - __IM uint32_t DATABYTEREV_TGL; /**< CRC Data Byte Reverse Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t EN; /**< CRC Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t INIT; /**< CRC Init Value */ + __IOM uint32_t POLY; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ + __IM uint32_t DATA; /**< CRC Data Register */ + __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED0[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t EN_SET; /**< CRC Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t INIT_SET; /**< CRC Init Value */ + __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_SET; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_SET; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_SET; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_SET; /**< CRC Data Register */ + __IM uint32_t DATAREV_SET; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_SET; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED1[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t EN_CLR; /**< CRC Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t INIT_CLR; /**< CRC Init Value */ + __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_CLR; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_CLR; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_CLR; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_CLR; /**< CRC Data Register */ + __IM uint32_t DATAREV_CLR; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_CLR; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED2[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t EN_TGL; /**< CRC Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t INIT_TGL; /**< CRC Init Value */ + __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_TGL; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_TGL; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_TGL; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_TGL; /**< CRC Data Register */ + __IM uint32_t DATAREV_TGL; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_TGL; /**< CRC Data Byte Reverse Register */ } GPCRC_TypeDef; /** @} End of group EFR32SG28_GPCRC */ @@ -107,139 +105,139 @@ typedef struct *****************************************************************************/ /* Bit fields for GPCRC IPVERSION */ -#define _GPCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for GPCRC_IPVERSION */ -#define _GPCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_IPVERSION */ -#define _GPCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPCRC_IPVERSION */ -#define _GPCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_IPVERSION */ -#define _GPCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_IPVERSION */ -#define GPCRC_IPVERSION_IPVERSION_DEFAULT (_GPCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_IPVERSION */ +#define GPCRC_IPVERSION_IPVERSION_DEFAULT (_GPCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_IPVERSION */ /* Bit fields for GPCRC EN */ -#define _GPCRC_EN_RESETVALUE 0x00000000UL /**< Default value for GPCRC_EN */ -#define _GPCRC_EN_MASK 0x00000001UL /**< Mask for GPCRC_EN */ -#define GPCRC_EN_EN (0x1UL << 0) /**< CRC Enable */ -#define _GPCRC_EN_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ -#define _GPCRC_EN_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ -#define _GPCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_EN */ -#define _GPCRC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_EN */ -#define _GPCRC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_EN */ -#define GPCRC_EN_EN_DEFAULT (_GPCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_EN */ -#define GPCRC_EN_EN_DISABLE (_GPCRC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_EN */ -#define GPCRC_EN_EN_ENABLE (_GPCRC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_EN */ +#define _GPCRC_EN_RESETVALUE 0x00000000UL /**< Default value for GPCRC_EN */ +#define _GPCRC_EN_MASK 0x00000001UL /**< Mask for GPCRC_EN */ +#define GPCRC_EN_EN (0x1UL << 0) /**< CRC Enable */ +#define _GPCRC_EN_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ +#define _GPCRC_EN_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ +#define _GPCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_EN */ +#define _GPCRC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_EN */ +#define _GPCRC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_EN */ +#define GPCRC_EN_EN_DEFAULT (_GPCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_EN */ +#define GPCRC_EN_EN_DISABLE (_GPCRC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_EN */ +#define GPCRC_EN_EN_ENABLE (_GPCRC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_EN */ /* Bit fields for GPCRC CTRL */ -#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ -#define _GPCRC_CTRL_MASK 0x00002710UL /**< Mask for GPCRC_CTRL */ -#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ -#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ -#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ -#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ -#define _GPCRC_CTRL_POLYSEL_CRC16 0x00000001UL /**< Mode CRC16 for GPCRC_CTRL */ -#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ -#define GPCRC_CTRL_POLYSEL_CRC16 (_GPCRC_CTRL_POLYSEL_CRC16 << 4) /**< Shifted mode CRC16 for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ -#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ -#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ -#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ -#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ -#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ -#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ -#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ -#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ -#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ -#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ -#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ -#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ -#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ -#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ -#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ -#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ -#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ +#define _GPCRC_CTRL_MASK 0x00002710UL /**< Mask for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ +#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC16 0x00000001UL /**< Mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC16 (_GPCRC_CTRL_POLYSEL_CRC16 << 4) /**< Shifted mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ +#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ +#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ +#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ +#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ /* Bit fields for GPCRC CMD */ -#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ -#define _GPCRC_CMD_MASK 0x80000001UL /**< Mask for GPCRC_CMD */ -#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ -#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ -#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ -#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ -#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ +#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ +#define _GPCRC_CMD_MASK 0x80000001UL /**< Mask for GPCRC_CMD */ +#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ +#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ +#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ /* Bit fields for GPCRC INIT */ -#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ -#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ -#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ -#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ -#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ -#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ +#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ +#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ +#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ /* Bit fields for GPCRC POLY */ -#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ -#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ -#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ -#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ -#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ -#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ +#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ +#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ +#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ /* Bit fields for GPCRC INPUTDATA */ -#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ -#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ -#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ -#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ -#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ -#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ +#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ /* Bit fields for GPCRC INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ -#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD*/ +#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ +#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD*/ /* Bit fields for GPCRC INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ -#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE*/ +#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ +#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE*/ /* Bit fields for GPCRC DATA */ -#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ -#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ -#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ -#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ -#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ -#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ +#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ +#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ +#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ /* Bit fields for GPCRC DATAREV */ -#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ -#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ -#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ -#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ -#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ -#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ +#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ /* Bit fields for GPCRC DATABYTEREV */ -#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ -#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ -#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ -#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ -#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ -#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ +#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ /** @} End of group EFR32SG28_GPCRC_BitFields */ /** @} End of group EFR32SG28_GPCRC */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpio.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpio.h index b8b995f2ca..53a475f126 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpio.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpio.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_GPIO_H #define EFR32SG28_GPIO_H - #define GPIO_HAS_SET_CLEAR /**************************************************************************//** @@ -39,2953 +38,2923 @@ #include "efr32sg28_gpio_port.h" - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< ACMP0 pin enable */ - __IOM uint32_t ACMPOUTROUTE; /**< ACMPOUT port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< ACMP0 pin enable */ + __IOM uint32_t ACMPOUTROUTE; /**< ACMPOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_ACMPROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< CMU pin enable */ - __IOM uint32_t CLKIN0ROUTE; /**< CLKIN0 port/pin select */ - __IOM uint32_t CLKOUT0ROUTE; /**< CLKOUT0 port/pin select */ - __IOM uint32_t CLKOUT1ROUTE; /**< CLKOUT1 port/pin select */ - __IOM uint32_t CLKOUT2ROUTE; /**< CLKOUT2 port/pin select */ - uint32_t RESERVED0[2U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< CMU pin enable */ + __IOM uint32_t CLKIN0ROUTE; /**< CLKIN0 port/pin select */ + __IOM uint32_t CLKOUT0ROUTE; /**< CLKOUT0 port/pin select */ + __IOM uint32_t CLKOUT1ROUTE; /**< CLKOUT1 port/pin select */ + __IOM uint32_t CLKOUT2ROUTE; /**< CLKOUT2 port/pin select */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ } GPIO_CMUROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< EUSART0 pin enable */ - __IOM uint32_t CSROUTE; /**< CS port/pin select */ - __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ - __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ - __IOM uint32_t RXROUTE; /**< RX port/pin select */ - __IOM uint32_t SCLKROUTE; /**< SCLK port/pin select */ - __IOM uint32_t TXROUTE; /**< TX port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< EUSART0 pin enable */ + __IOM uint32_t CSROUTE; /**< CS port/pin select */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t SCLKROUTE; /**< SCLK port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_EUSARTROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< FRC pin enable */ - __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ - __IOM uint32_t DFRAMEROUTE; /**< DFRAME port/pin select */ - __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< FRC pin enable */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DFRAMEROUTE; /**< DFRAME port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_FRCROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< I2C0 pin enable */ - __IOM uint32_t SCLROUTE; /**< SCL port/pin select */ - __IOM uint32_t SDAROUTE; /**< SDA port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< I2C0 pin enable */ + __IOM uint32_t SCLROUTE; /**< SCL port/pin select */ + __IOM uint32_t SDAROUTE; /**< SDA port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_I2CROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< KEYSCAN pin enable */ - __IOM uint32_t COLOUT0ROUTE; /**< COLOUT0 port/pin select */ - __IOM uint32_t COLOUT1ROUTE; /**< COLOUT1 port/pin select */ - __IOM uint32_t COLOUT2ROUTE; /**< COLOUT2 port/pin select */ - __IOM uint32_t COLOUT3ROUTE; /**< COLOUT3 port/pin select */ - __IOM uint32_t COLOUT4ROUTE; /**< COLOUT4 port/pin select */ - __IOM uint32_t COLOUT5ROUTE; /**< COLOUT5 port/pin select */ - __IOM uint32_t COLOUT6ROUTE; /**< COLOUT6 port/pin select */ - __IOM uint32_t COLOUT7ROUTE; /**< COLOUT7 port/pin select */ - __IOM uint32_t ROWSENSE0ROUTE; /**< ROWSENSE0 port/pin select */ - __IOM uint32_t ROWSENSE1ROUTE; /**< ROWSENSE1 port/pin select */ - __IOM uint32_t ROWSENSE2ROUTE; /**< ROWSENSE2 port/pin select */ - __IOM uint32_t ROWSENSE3ROUTE; /**< ROWSENSE3 port/pin select */ - __IOM uint32_t ROWSENSE4ROUTE; /**< ROWSENSE4 port/pin select */ - __IOM uint32_t ROWSENSE5ROUTE; /**< ROWSENSE5 port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< KEYSCAN pin enable */ + __IOM uint32_t COLOUT0ROUTE; /**< COLOUT0 port/pin select */ + __IOM uint32_t COLOUT1ROUTE; /**< COLOUT1 port/pin select */ + __IOM uint32_t COLOUT2ROUTE; /**< COLOUT2 port/pin select */ + __IOM uint32_t COLOUT3ROUTE; /**< COLOUT3 port/pin select */ + __IOM uint32_t COLOUT4ROUTE; /**< COLOUT4 port/pin select */ + __IOM uint32_t COLOUT5ROUTE; /**< COLOUT5 port/pin select */ + __IOM uint32_t COLOUT6ROUTE; /**< COLOUT6 port/pin select */ + __IOM uint32_t COLOUT7ROUTE; /**< COLOUT7 port/pin select */ + __IOM uint32_t ROWSENSE0ROUTE; /**< ROWSENSE0 port/pin select */ + __IOM uint32_t ROWSENSE1ROUTE; /**< ROWSENSE1 port/pin select */ + __IOM uint32_t ROWSENSE2ROUTE; /**< ROWSENSE2 port/pin select */ + __IOM uint32_t ROWSENSE3ROUTE; /**< ROWSENSE3 port/pin select */ + __IOM uint32_t ROWSENSE4ROUTE; /**< ROWSENSE4 port/pin select */ + __IOM uint32_t ROWSENSE5ROUTE; /**< ROWSENSE5 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_KEYSCANROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< LESENSE pin enable */ - __IOM uint32_t CH0OUTROUTE; /**< CH0OUT port/pin select */ - __IOM uint32_t CH1OUTROUTE; /**< CH1OUT port/pin select */ - __IOM uint32_t CH2OUTROUTE; /**< CH2OUT port/pin select */ - __IOM uint32_t CH3OUTROUTE; /**< CH3OUT port/pin select */ - __IOM uint32_t CH4OUTROUTE; /**< CH4OUT port/pin select */ - __IOM uint32_t CH5OUTROUTE; /**< CH5OUT port/pin select */ - __IOM uint32_t CH6OUTROUTE; /**< CH6OUT port/pin select */ - __IOM uint32_t CH7OUTROUTE; /**< CH7OUT port/pin select */ - __IOM uint32_t CH8OUTROUTE; /**< CH8OUT port/pin select */ - __IOM uint32_t CH9OUTROUTE; /**< CH9OUT port/pin select */ - __IOM uint32_t CH10OUTROUTE; /**< CH10OUT port/pin select */ - __IOM uint32_t CH11OUTROUTE; /**< CH11OUT port/pin select */ - __IOM uint32_t CH12OUTROUTE; /**< CH12OUT port/pin select */ - __IOM uint32_t CH13OUTROUTE; /**< CH13OUT port/pin select */ - __IOM uint32_t CH14OUTROUTE; /**< CH14OUT port/pin select */ - __IOM uint32_t CH15OUTROUTE; /**< CH15OUT port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< LESENSE pin enable */ + __IOM uint32_t CH0OUTROUTE; /**< CH0OUT port/pin select */ + __IOM uint32_t CH1OUTROUTE; /**< CH1OUT port/pin select */ + __IOM uint32_t CH2OUTROUTE; /**< CH2OUT port/pin select */ + __IOM uint32_t CH3OUTROUTE; /**< CH3OUT port/pin select */ + __IOM uint32_t CH4OUTROUTE; /**< CH4OUT port/pin select */ + __IOM uint32_t CH5OUTROUTE; /**< CH5OUT port/pin select */ + __IOM uint32_t CH6OUTROUTE; /**< CH6OUT port/pin select */ + __IOM uint32_t CH7OUTROUTE; /**< CH7OUT port/pin select */ + __IOM uint32_t CH8OUTROUTE; /**< CH8OUT port/pin select */ + __IOM uint32_t CH9OUTROUTE; /**< CH9OUT port/pin select */ + __IOM uint32_t CH10OUTROUTE; /**< CH10OUT port/pin select */ + __IOM uint32_t CH11OUTROUTE; /**< CH11OUT port/pin select */ + __IOM uint32_t CH12OUTROUTE; /**< CH12OUT port/pin select */ + __IOM uint32_t CH13OUTROUTE; /**< CH13OUT port/pin select */ + __IOM uint32_t CH14OUTROUTE; /**< CH14OUT port/pin select */ + __IOM uint32_t CH15OUTROUTE; /**< CH15OUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_LESENSEROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< LETIMER pin enable */ - __IOM uint32_t OUT0ROUTE; /**< OUT0 port/pin select */ - __IOM uint32_t OUT1ROUTE; /**< OUT1 port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< LETIMER pin enable */ + __IOM uint32_t OUT0ROUTE; /**< OUT0 port/pin select */ + __IOM uint32_t OUT1ROUTE; /**< OUT1 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_LETIMERROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< MODEM pin enable */ - __IOM uint32_t ANT0ROUTE; /**< ANT0 port/pin select */ - __IOM uint32_t ANT1ROUTE; /**< ANT1 port/pin select */ - __IOM uint32_t ANTROLLOVERROUTE; /**< ANTROLLOVER port/pin select */ - __IOM uint32_t ANTRR0ROUTE; /**< ANTRR0 port/pin select */ - __IOM uint32_t ANTRR1ROUTE; /**< ANTRR1 port/pin select */ - __IOM uint32_t ANTRR2ROUTE; /**< ANTRR2 port/pin select */ - __IOM uint32_t ANTRR3ROUTE; /**< ANTRR3 port/pin select */ - __IOM uint32_t ANTRR4ROUTE; /**< ANTRR4 port/pin select */ - __IOM uint32_t ANTRR5ROUTE; /**< ANTRR5 port/pin select */ - __IOM uint32_t ANTSWENROUTE; /**< ANTSWEN port/pin select */ - __IOM uint32_t ANTSWUSROUTE; /**< ANTSWUS port/pin select */ - __IOM uint32_t ANTTRIGROUTE; /**< ANTTRIG port/pin select */ - __IOM uint32_t ANTTRIGSTOPROUTE; /**< ANTTRIGSTOP port/pin select */ - __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ - __IOM uint32_t DINROUTE; /**< DIN port/pin select */ - __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< MODEM pin enable */ + __IOM uint32_t ANT0ROUTE; /**< ANT0 port/pin select */ + __IOM uint32_t ANT1ROUTE; /**< ANT1 port/pin select */ + __IOM uint32_t ANTROLLOVERROUTE; /**< ANTROLLOVER port/pin select */ + __IOM uint32_t ANTRR0ROUTE; /**< ANTRR0 port/pin select */ + __IOM uint32_t ANTRR1ROUTE; /**< ANTRR1 port/pin select */ + __IOM uint32_t ANTRR2ROUTE; /**< ANTRR2 port/pin select */ + __IOM uint32_t ANTRR3ROUTE; /**< ANTRR3 port/pin select */ + __IOM uint32_t ANTRR4ROUTE; /**< ANTRR4 port/pin select */ + __IOM uint32_t ANTRR5ROUTE; /**< ANTRR5 port/pin select */ + __IOM uint32_t ANTSWENROUTE; /**< ANTSWEN port/pin select */ + __IOM uint32_t ANTSWUSROUTE; /**< ANTSWUS port/pin select */ + __IOM uint32_t ANTTRIGROUTE; /**< ANTTRIG port/pin select */ + __IOM uint32_t ANTTRIGSTOPROUTE; /**< ANTTRIGSTOP port/pin select */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DINROUTE; /**< DIN port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_MODEMROUTE_TypeDef; - -typedef struct -{ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t S0INROUTE; /**< S0IN port/pin select */ - __IOM uint32_t S1INROUTE; /**< S1IN port/pin select */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t S0INROUTE; /**< S0IN port/pin select */ + __IOM uint32_t S1INROUTE; /**< S1IN port/pin select */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ } GPIO_PCNTROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< PRS0 pin enable */ - __IOM uint32_t ASYNCH0ROUTE; /**< ASYNCH0 port/pin select */ - __IOM uint32_t ASYNCH1ROUTE; /**< ASYNCH1 port/pin select */ - __IOM uint32_t ASYNCH2ROUTE; /**< ASYNCH2 port/pin select */ - __IOM uint32_t ASYNCH3ROUTE; /**< ASYNCH3 port/pin select */ - __IOM uint32_t ASYNCH4ROUTE; /**< ASYNCH4 port/pin select */ - __IOM uint32_t ASYNCH5ROUTE; /**< ASYNCH5 port/pin select */ - __IOM uint32_t ASYNCH6ROUTE; /**< ASYNCH6 port/pin select */ - __IOM uint32_t ASYNCH7ROUTE; /**< ASYNCH7 port/pin select */ - __IOM uint32_t ASYNCH8ROUTE; /**< ASYNCH8 port/pin select */ - __IOM uint32_t ASYNCH9ROUTE; /**< ASYNCH9 port/pin select */ - __IOM uint32_t ASYNCH10ROUTE; /**< ASYNCH10 port/pin select */ - __IOM uint32_t ASYNCH11ROUTE; /**< ASYNCH11 port/pin select */ - __IOM uint32_t SYNCH0ROUTE; /**< SYNCH0 port/pin select */ - __IOM uint32_t SYNCH1ROUTE; /**< SYNCH1 port/pin select */ - __IOM uint32_t SYNCH2ROUTE; /**< SYNCH2 port/pin select */ - __IOM uint32_t SYNCH3ROUTE; /**< SYNCH3 port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< PRS0 pin enable */ + __IOM uint32_t ASYNCH0ROUTE; /**< ASYNCH0 port/pin select */ + __IOM uint32_t ASYNCH1ROUTE; /**< ASYNCH1 port/pin select */ + __IOM uint32_t ASYNCH2ROUTE; /**< ASYNCH2 port/pin select */ + __IOM uint32_t ASYNCH3ROUTE; /**< ASYNCH3 port/pin select */ + __IOM uint32_t ASYNCH4ROUTE; /**< ASYNCH4 port/pin select */ + __IOM uint32_t ASYNCH5ROUTE; /**< ASYNCH5 port/pin select */ + __IOM uint32_t ASYNCH6ROUTE; /**< ASYNCH6 port/pin select */ + __IOM uint32_t ASYNCH7ROUTE; /**< ASYNCH7 port/pin select */ + __IOM uint32_t ASYNCH8ROUTE; /**< ASYNCH8 port/pin select */ + __IOM uint32_t ASYNCH9ROUTE; /**< ASYNCH9 port/pin select */ + __IOM uint32_t ASYNCH10ROUTE; /**< ASYNCH10 port/pin select */ + __IOM uint32_t ASYNCH11ROUTE; /**< ASYNCH11 port/pin select */ + __IOM uint32_t SYNCH0ROUTE; /**< SYNCH0 port/pin select */ + __IOM uint32_t SYNCH1ROUTE; /**< SYNCH1 port/pin select */ + __IOM uint32_t SYNCH2ROUTE; /**< SYNCH2 port/pin select */ + __IOM uint32_t SYNCH3ROUTE; /**< SYNCH3 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_PRSROUTE_TypeDef; - -typedef struct -{ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t BUFOUTREQINASYNCROUTE; /**< BUFOUTREQINASYNC port/pin select */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTREQINASYNCROUTE; /**< BUFOUTREQINASYNC port/pin select */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ } GPIO_SYXOROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< TIMER0 pin enable */ - __IOM uint32_t CC0ROUTE; /**< CC0 port/pin select */ - __IOM uint32_t CC1ROUTE; /**< CC1 port/pin select */ - __IOM uint32_t CC2ROUTE; /**< CC2 port/pin select */ - __IOM uint32_t CDTI0ROUTE; /**< CDTI0 port/pin select */ - __IOM uint32_t CDTI1ROUTE; /**< CDTI1 port/pin select */ - __IOM uint32_t CDTI2ROUTE; /**< CDTI2 port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< TIMER0 pin enable */ + __IOM uint32_t CC0ROUTE; /**< CC0 port/pin select */ + __IOM uint32_t CC1ROUTE; /**< CC1 port/pin select */ + __IOM uint32_t CC2ROUTE; /**< CC2 port/pin select */ + __IOM uint32_t CDTI0ROUTE; /**< CDTI0 port/pin select */ + __IOM uint32_t CDTI1ROUTE; /**< CDTI1 port/pin select */ + __IOM uint32_t CDTI2ROUTE; /**< CDTI2 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_TIMERROUTE_TypeDef; - -typedef struct -{ - __IOM uint32_t ROUTEEN; /**< USART0 pin enable */ - __IOM uint32_t CSROUTE; /**< CS port/pin select */ - __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ - __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ - __IOM uint32_t RXROUTE; /**< RX port/pin select */ - __IOM uint32_t CLKROUTE; /**< SCLK port/pin select */ - __IOM uint32_t TXROUTE; /**< TX port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t ROUTEEN; /**< USART0 pin enable */ + __IOM uint32_t CSROUTE; /**< CS port/pin select */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t CLKROUTE; /**< SCLK port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ } GPIO_USARTROUTE_TypeDef; -typedef struct -{ - __IM uint32_t IPVERSION; /**< main */ - uint32_t RESERVED0[11U]; /**< Reserved for future use */ - GPIO_PORT_TypeDef P[4U]; /**< */ - uint32_t RESERVED1[132U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Lock Register */ - uint32_t RESERVED2[3U]; /**< Reserved for future use */ - __IM uint32_t GPIOLOCKSTATUS; /**< Lock Status */ - uint32_t RESERVED3[3U]; /**< Reserved for future use */ - __IOM uint32_t ABUSALLOC; /**< A Bus allocation */ - __IOM uint32_t BBUSALLOC; /**< B Bus allocation */ - __IOM uint32_t CDBUSALLOC; /**< CD Bus allocation */ - uint32_t RESERVED4[53U]; /**< Reserved for future use */ - __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low */ - __IOM uint32_t EXTIPSELH; /**< External interrupt Port Select High */ - __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low */ - __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High */ - __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger */ - __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger */ - uint32_t RESERVED5[2U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IOM uint32_t EM4WUEN; /**< EM4 wakeup enable */ - __IOM uint32_t EM4WUPOL; /**< EM4 wakeup polarity */ - uint32_t RESERVED7[3U]; /**< Reserved for future use */ - __IOM uint32_t DBGROUTEPEN; /**< Debugger Route Pin enable */ - __IOM uint32_t TRACEROUTEPEN; /**< Trace Route Pin Enable */ - uint32_t RESERVED8[2U]; /**< Reserved for future use */ - uint32_t RESERVED9[4U]; /**< Reserved for future use */ - __IOM uint32_t LCDSEG; /**< LCD Segment Enable */ - uint32_t RESERVED10[3U]; /**< Reserved for future use */ - __IOM uint32_t LCDCOM; /**< LCD Common Enable */ - uint32_t RESERVED11[3U]; /**< Reserved for future use */ - GPIO_ACMPROUTE_TypeDef ACMPROUTE[2U]; /**< acmp0 DBUS config registers */ - GPIO_CMUROUTE_TypeDef CMUROUTE; /**< cmu DBUS config registers */ - uint32_t RESERVED12[4U]; /**< Reserved for future use */ - GPIO_EUSARTROUTE_TypeDef EUSARTROUTE[3U]; /**< eusart0 DBUS config registers */ - GPIO_FRCROUTE_TypeDef FRCROUTE; /**< frc DBUS config registers */ - GPIO_I2CROUTE_TypeDef I2CROUTE[2U]; /**< i2c0 DBUS config registers */ - GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE; /**< keyscan DBUS config registers */ - GPIO_LESENSEROUTE_TypeDef LESENSEROUTE; /**< lesense DBUS config registers */ - GPIO_LETIMERROUTE_TypeDef LETIMERROUTE; /**< letimer DBUS config registers */ - GPIO_MODEMROUTE_TypeDef MODEMROUTE; /**< modem DBUS config registers */ - GPIO_PCNTROUTE_TypeDef PCNTROUTE[1U]; /**< pcnt0 DBUS config registers */ - GPIO_PRSROUTE_TypeDef PRSROUTE[1U]; /**< prs0 DBUS config registers */ - uint32_t RESERVED13[23U]; /**< Reserved for future use */ - GPIO_SYXOROUTE_TypeDef SYXOROUTE[1U]; /**< syxo0 DBUS config registers */ - GPIO_TIMERROUTE_TypeDef TIMERROUTE[5U]; /**< timer0 DBUS config registers */ - GPIO_USARTROUTE_TypeDef USARTROUTE[1U]; /**< usart0 DBUS config registers */ - uint32_t RESERVED14[530U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< main */ - uint32_t RESERVED15[11U]; /**< Reserved for future use */ - GPIO_PORT_TypeDef P_SET[4U]; /**< */ - uint32_t RESERVED16[132U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Lock Register */ - uint32_t RESERVED17[3U]; /**< Reserved for future use */ - __IM uint32_t GPIOLOCKSTATUS_SET; /**< Lock Status */ - uint32_t RESERVED18[3U]; /**< Reserved for future use */ - __IOM uint32_t ABUSALLOC_SET; /**< A Bus allocation */ - __IOM uint32_t BBUSALLOC_SET; /**< B Bus allocation */ - __IOM uint32_t CDBUSALLOC_SET; /**< CD Bus allocation */ - uint32_t RESERVED19[53U]; /**< Reserved for future use */ - __IOM uint32_t EXTIPSELL_SET; /**< External Interrupt Port Select Low */ - __IOM uint32_t EXTIPSELH_SET; /**< External interrupt Port Select High */ - __IOM uint32_t EXTIPINSELL_SET; /**< External Interrupt Pin Select Low */ - __IOM uint32_t EXTIPINSELH_SET; /**< External Interrupt Pin Select High */ - __IOM uint32_t EXTIRISE_SET; /**< External Interrupt Rising Edge Trigger */ - __IOM uint32_t EXTIFALL_SET; /**< External Interrupt Falling Edge Trigger */ - uint32_t RESERVED20[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup enable */ - __IOM uint32_t EM4WUPOL_SET; /**< EM4 wakeup polarity */ - uint32_t RESERVED22[3U]; /**< Reserved for future use */ - __IOM uint32_t DBGROUTEPEN_SET; /**< Debugger Route Pin enable */ - __IOM uint32_t TRACEROUTEPEN_SET; /**< Trace Route Pin Enable */ - uint32_t RESERVED23[2U]; /**< Reserved for future use */ - uint32_t RESERVED24[4U]; /**< Reserved for future use */ - __IOM uint32_t LCDSEG_SET; /**< LCD Segment Enable */ - uint32_t RESERVED25[3U]; /**< Reserved for future use */ - __IOM uint32_t LCDCOM_SET; /**< LCD Common Enable */ - uint32_t RESERVED26[3U]; /**< Reserved for future use */ - GPIO_ACMPROUTE_TypeDef ACMPROUTE_SET[2U]; /**< acmp0 DBUS config registers */ - GPIO_CMUROUTE_TypeDef CMUROUTE_SET; /**< cmu DBUS config registers */ - uint32_t RESERVED27[4U]; /**< Reserved for future use */ - GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_SET[3U]; /**< eusart0 DBUS config registers */ - GPIO_FRCROUTE_TypeDef FRCROUTE_SET; /**< frc DBUS config registers */ - GPIO_I2CROUTE_TypeDef I2CROUTE_SET[2U]; /**< i2c0 DBUS config registers */ - GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_SET; /**< keyscan DBUS config registers */ - GPIO_LESENSEROUTE_TypeDef LESENSEROUTE_SET; /**< lesense DBUS config registers */ - GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_SET; /**< letimer DBUS config registers */ - GPIO_MODEMROUTE_TypeDef MODEMROUTE_SET; /**< modem DBUS config registers */ - GPIO_PCNTROUTE_TypeDef PCNTROUTE_SET[1U]; /**< pcnt0 DBUS config registers */ - GPIO_PRSROUTE_TypeDef PRSROUTE_SET[1U]; /**< prs0 DBUS config registers */ - uint32_t RESERVED28[23U]; /**< Reserved for future use */ - GPIO_SYXOROUTE_TypeDef SYXOROUTE_SET[1U]; /**< syxo0 DBUS config registers */ - GPIO_TIMERROUTE_TypeDef TIMERROUTE_SET[5U]; /**< timer0 DBUS config registers */ - GPIO_USARTROUTE_TypeDef USARTROUTE_SET[1U]; /**< usart0 DBUS config registers */ - uint32_t RESERVED29[530U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< main */ - uint32_t RESERVED30[11U]; /**< Reserved for future use */ - GPIO_PORT_TypeDef P_CLR[4U]; /**< */ - uint32_t RESERVED31[132U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Lock Register */ - uint32_t RESERVED32[3U]; /**< Reserved for future use */ - __IM uint32_t GPIOLOCKSTATUS_CLR; /**< Lock Status */ - uint32_t RESERVED33[3U]; /**< Reserved for future use */ - __IOM uint32_t ABUSALLOC_CLR; /**< A Bus allocation */ - __IOM uint32_t BBUSALLOC_CLR; /**< B Bus allocation */ - __IOM uint32_t CDBUSALLOC_CLR; /**< CD Bus allocation */ - uint32_t RESERVED34[53U]; /**< Reserved for future use */ - __IOM uint32_t EXTIPSELL_CLR; /**< External Interrupt Port Select Low */ - __IOM uint32_t EXTIPSELH_CLR; /**< External interrupt Port Select High */ - __IOM uint32_t EXTIPINSELL_CLR; /**< External Interrupt Pin Select Low */ - __IOM uint32_t EXTIPINSELH_CLR; /**< External Interrupt Pin Select High */ - __IOM uint32_t EXTIRISE_CLR; /**< External Interrupt Rising Edge Trigger */ - __IOM uint32_t EXTIFALL_CLR; /**< External Interrupt Falling Edge Trigger */ - uint32_t RESERVED35[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - uint32_t RESERVED36[1U]; /**< Reserved for future use */ - __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup enable */ - __IOM uint32_t EM4WUPOL_CLR; /**< EM4 wakeup polarity */ - uint32_t RESERVED37[3U]; /**< Reserved for future use */ - __IOM uint32_t DBGROUTEPEN_CLR; /**< Debugger Route Pin enable */ - __IOM uint32_t TRACEROUTEPEN_CLR; /**< Trace Route Pin Enable */ - uint32_t RESERVED38[2U]; /**< Reserved for future use */ - uint32_t RESERVED39[4U]; /**< Reserved for future use */ - __IOM uint32_t LCDSEG_CLR; /**< LCD Segment Enable */ - uint32_t RESERVED40[3U]; /**< Reserved for future use */ - __IOM uint32_t LCDCOM_CLR; /**< LCD Common Enable */ - uint32_t RESERVED41[3U]; /**< Reserved for future use */ - GPIO_ACMPROUTE_TypeDef ACMPROUTE_CLR[2U]; /**< acmp0 DBUS config registers */ - GPIO_CMUROUTE_TypeDef CMUROUTE_CLR; /**< cmu DBUS config registers */ - uint32_t RESERVED42[4U]; /**< Reserved for future use */ - GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_CLR[3U]; /**< eusart0 DBUS config registers */ - GPIO_FRCROUTE_TypeDef FRCROUTE_CLR; /**< frc DBUS config registers */ - GPIO_I2CROUTE_TypeDef I2CROUTE_CLR[2U]; /**< i2c0 DBUS config registers */ - GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_CLR; /**< keyscan DBUS config registers */ - GPIO_LESENSEROUTE_TypeDef LESENSEROUTE_CLR; /**< lesense DBUS config registers */ - GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_CLR; /**< letimer DBUS config registers */ - GPIO_MODEMROUTE_TypeDef MODEMROUTE_CLR; /**< modem DBUS config registers */ - GPIO_PCNTROUTE_TypeDef PCNTROUTE_CLR[1U]; /**< pcnt0 DBUS config registers */ - GPIO_PRSROUTE_TypeDef PRSROUTE_CLR[1U]; /**< prs0 DBUS config registers */ - uint32_t RESERVED43[23U]; /**< Reserved for future use */ - GPIO_SYXOROUTE_TypeDef SYXOROUTE_CLR[1U]; /**< syxo0 DBUS config registers */ - GPIO_TIMERROUTE_TypeDef TIMERROUTE_CLR[5U]; /**< timer0 DBUS config registers */ - GPIO_USARTROUTE_TypeDef USARTROUTE_CLR[1U]; /**< usart0 DBUS config registers */ - uint32_t RESERVED44[530U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< main */ - uint32_t RESERVED45[11U]; /**< Reserved for future use */ - GPIO_PORT_TypeDef P_TGL[4U]; /**< */ - uint32_t RESERVED46[132U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Lock Register */ - uint32_t RESERVED47[3U]; /**< Reserved for future use */ - __IM uint32_t GPIOLOCKSTATUS_TGL; /**< Lock Status */ - uint32_t RESERVED48[3U]; /**< Reserved for future use */ - __IOM uint32_t ABUSALLOC_TGL; /**< A Bus allocation */ - __IOM uint32_t BBUSALLOC_TGL; /**< B Bus allocation */ - __IOM uint32_t CDBUSALLOC_TGL; /**< CD Bus allocation */ - uint32_t RESERVED49[53U]; /**< Reserved for future use */ - __IOM uint32_t EXTIPSELL_TGL; /**< External Interrupt Port Select Low */ - __IOM uint32_t EXTIPSELH_TGL; /**< External interrupt Port Select High */ - __IOM uint32_t EXTIPINSELL_TGL; /**< External Interrupt Pin Select Low */ - __IOM uint32_t EXTIPINSELH_TGL; /**< External Interrupt Pin Select High */ - __IOM uint32_t EXTIRISE_TGL; /**< External Interrupt Rising Edge Trigger */ - __IOM uint32_t EXTIFALL_TGL; /**< External Interrupt Falling Edge Trigger */ - uint32_t RESERVED50[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - uint32_t RESERVED51[1U]; /**< Reserved for future use */ - __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup enable */ - __IOM uint32_t EM4WUPOL_TGL; /**< EM4 wakeup polarity */ - uint32_t RESERVED52[3U]; /**< Reserved for future use */ - __IOM uint32_t DBGROUTEPEN_TGL; /**< Debugger Route Pin enable */ - __IOM uint32_t TRACEROUTEPEN_TGL; /**< Trace Route Pin Enable */ - uint32_t RESERVED53[2U]; /**< Reserved for future use */ - uint32_t RESERVED54[4U]; /**< Reserved for future use */ - __IOM uint32_t LCDSEG_TGL; /**< LCD Segment Enable */ - uint32_t RESERVED55[3U]; /**< Reserved for future use */ - __IOM uint32_t LCDCOM_TGL; /**< LCD Common Enable */ - uint32_t RESERVED56[3U]; /**< Reserved for future use */ - GPIO_ACMPROUTE_TypeDef ACMPROUTE_TGL[2U]; /**< acmp0 DBUS config registers */ - GPIO_CMUROUTE_TypeDef CMUROUTE_TGL; /**< cmu DBUS config registers */ - uint32_t RESERVED57[4U]; /**< Reserved for future use */ - GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_TGL[3U]; /**< eusart0 DBUS config registers */ - GPIO_FRCROUTE_TypeDef FRCROUTE_TGL; /**< frc DBUS config registers */ - GPIO_I2CROUTE_TypeDef I2CROUTE_TGL[2U]; /**< i2c0 DBUS config registers */ - GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_TGL; /**< keyscan DBUS config registers */ - GPIO_LESENSEROUTE_TypeDef LESENSEROUTE_TGL; /**< lesense DBUS config registers */ - GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_TGL; /**< letimer DBUS config registers */ - GPIO_MODEMROUTE_TypeDef MODEMROUTE_TGL; /**< modem DBUS config registers */ - GPIO_PCNTROUTE_TypeDef PCNTROUTE_TGL[1U]; /**< pcnt0 DBUS config registers */ - GPIO_PRSROUTE_TypeDef PRSROUTE_TGL[1U]; /**< prs0 DBUS config registers */ - uint32_t RESERVED58[23U]; /**< Reserved for future use */ - GPIO_SYXOROUTE_TypeDef SYXOROUTE_TGL[1U]; /**< syxo0 DBUS config registers */ - GPIO_TIMERROUTE_TypeDef TIMERROUTE_TGL[5U]; /**< timer0 DBUS config registers */ - GPIO_USARTROUTE_TypeDef USARTROUTE_TGL[1U]; /**< usart0 DBUS config registers */ +typedef struct { + __IM uint32_t IPVERSION; /**< main */ + uint32_t RESERVED0[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P[4U]; /**< */ + uint32_t RESERVED1[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS; /**< Lock Status */ + uint32_t RESERVED3[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC; /**< CD Bus allocation */ + uint32_t RESERVED4[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED5[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL; /**< EM4 wakeup polarity */ + uint32_t RESERVED7[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN; /**< Trace Route Pin Enable */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + uint32_t RESERVED9[4U]; /**< Reserved for future use */ + __IOM uint32_t LCDSEG; /**< LCD Segment Enable */ + uint32_t RESERVED10[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCOM; /**< LCD Common Enable */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE; /**< cmu DBUS config registers */ + uint32_t RESERVED12[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE[3U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE; /**< keyscan DBUS config registers */ + GPIO_LESENSEROUTE_TypeDef LESENSEROUTE; /**< lesense DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE[1U]; /**< prs0 DBUS config registers */ + uint32_t RESERVED13[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE[1U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED14[530U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< main */ + uint32_t RESERVED15[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_SET[4U]; /**< */ + uint32_t RESERVED16[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED17[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_SET; /**< Lock Status */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_SET; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_SET; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_SET; /**< CD Bus allocation */ + uint32_t RESERVED19[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_SET; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_SET; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_SET; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_SET; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_SET; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_SET; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_SET; /**< EM4 wakeup polarity */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_SET; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_SET; /**< Trace Route Pin Enable */ + uint32_t RESERVED23[2U]; /**< Reserved for future use */ + uint32_t RESERVED24[4U]; /**< Reserved for future use */ + __IOM uint32_t LCDSEG_SET; /**< LCD Segment Enable */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCOM_SET; /**< LCD Common Enable */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_SET[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_SET; /**< cmu DBUS config registers */ + uint32_t RESERVED27[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_SET[3U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_SET; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_SET[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_SET; /**< keyscan DBUS config registers */ + GPIO_LESENSEROUTE_TypeDef LESENSEROUTE_SET; /**< lesense DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_SET; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_SET; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_SET[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_SET[1U]; /**< prs0 DBUS config registers */ + uint32_t RESERVED28[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_SET[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_SET[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_SET[1U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED29[530U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< main */ + uint32_t RESERVED30[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_CLR[4U]; /**< */ + uint32_t RESERVED31[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED32[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_CLR; /**< Lock Status */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_CLR; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_CLR; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_CLR; /**< CD Bus allocation */ + uint32_t RESERVED34[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_CLR; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_CLR; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_CLR; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_CLR; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_CLR; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_CLR; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED35[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED36[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_CLR; /**< EM4 wakeup polarity */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_CLR; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_CLR; /**< Trace Route Pin Enable */ + uint32_t RESERVED38[2U]; /**< Reserved for future use */ + uint32_t RESERVED39[4U]; /**< Reserved for future use */ + __IOM uint32_t LCDSEG_CLR; /**< LCD Segment Enable */ + uint32_t RESERVED40[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCOM_CLR; /**< LCD Common Enable */ + uint32_t RESERVED41[3U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_CLR[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_CLR; /**< cmu DBUS config registers */ + uint32_t RESERVED42[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_CLR[3U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_CLR; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_CLR[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_CLR; /**< keyscan DBUS config registers */ + GPIO_LESENSEROUTE_TypeDef LESENSEROUTE_CLR; /**< lesense DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_CLR; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_CLR; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_CLR[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_CLR[1U]; /**< prs0 DBUS config registers */ + uint32_t RESERVED43[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_CLR[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_CLR[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_CLR[1U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED44[530U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< main */ + uint32_t RESERVED45[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_TGL[4U]; /**< */ + uint32_t RESERVED46[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + uint32_t RESERVED47[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_TGL; /**< Lock Status */ + uint32_t RESERVED48[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_TGL; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_TGL; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_TGL; /**< CD Bus allocation */ + uint32_t RESERVED49[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_TGL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_TGL; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_TGL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_TGL; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_TGL; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_TGL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED50[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED51[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_TGL; /**< EM4 wakeup polarity */ + uint32_t RESERVED52[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_TGL; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_TGL; /**< Trace Route Pin Enable */ + uint32_t RESERVED53[2U]; /**< Reserved for future use */ + uint32_t RESERVED54[4U]; /**< Reserved for future use */ + __IOM uint32_t LCDSEG_TGL; /**< LCD Segment Enable */ + uint32_t RESERVED55[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCOM_TGL; /**< LCD Common Enable */ + uint32_t RESERVED56[3U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_TGL[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_TGL; /**< cmu DBUS config registers */ + uint32_t RESERVED57[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_TGL[3U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_TGL; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_TGL[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_TGL; /**< keyscan DBUS config registers */ + GPIO_LESENSEROUTE_TypeDef LESENSEROUTE_TGL; /**< lesense DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_TGL; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_TGL; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_TGL[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_TGL[1U]; /**< prs0 DBUS config registers */ + uint32_t RESERVED58[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_TGL[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_TGL[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_TGL[1U]; /**< usart0 DBUS config registers */ } GPIO_TypeDef; - /* Bit fields for GPIO IPVERSION */ -#define _GPIO_IPVERSION_RESETVALUE 0x00000006UL /**< Default value for GPIO_IPVERSION */ -#define _GPIO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IPVERSION */ -#define _GPIO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPIO_IPVERSION */ -#define _GPIO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPIO_IPVERSION */ -#define _GPIO_IPVERSION_IPVERSION_DEFAULT 0x00000006UL /**< Mode DEFAULT for GPIO_IPVERSION */ -#define GPIO_IPVERSION_IPVERSION_DEFAULT (_GPIO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IPVERSION */ -#define GPIO_PORTA 0x00000000UL /**< PORTA index */ -#define GPIO_PORTB 0x00000001UL /**< PORTB index */ -#define GPIO_PORTC 0x00000002UL /**< PORTC index */ -#define GPIO_PORTD 0x00000003UL /**< PORTD index */ +#define _GPIO_IPVERSION_RESETVALUE 0x00000006UL /**< Default value for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_DEFAULT 0x00000006UL /**< Mode DEFAULT for GPIO_IPVERSION */ +#define GPIO_IPVERSION_IPVERSION_DEFAULT (_GPIO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IPVERSION */ +#define GPIO_PORTA 0x00000000UL /**< PORTA index */ +#define GPIO_PORTB 0x00000001UL /**< PORTB index */ +#define GPIO_PORTC 0x00000002UL /**< PORTC index */ +#define GPIO_PORTD 0x00000003UL /**< PORTD index */ /* Bit fields for GPIO LOCK */ -#define _GPIO_LOCK_RESETVALUE 0x0000A534UL /**< Default value for GPIO_LOCK */ -#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ -#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ -#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ -#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x0000A534UL /**< Mode DEFAULT for GPIO_LOCK */ -#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ -#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ -#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ +#define _GPIO_LOCK_RESETVALUE 0x0000A534UL /**< Default value for GPIO_LOCK */ +#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x0000A534UL /**< Mode DEFAULT for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ /* Bit fields for GPIO GPIOLOCKSTATUS */ -#define _GPIO_GPIOLOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for GPIO_GPIOLOCKSTATUS */ -#define _GPIO_GPIOLOCKSTATUS_MASK 0x00000001UL /**< Mask for GPIO_GPIOLOCKSTATUS */ -#define GPIO_GPIOLOCKSTATUS_LOCK (0x1UL << 0) /**< GPIO LOCK status */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for GPIO_LOCK */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for GPIO_LOCK */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_GPIOLOCKSTATUS */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_GPIOLOCKSTATUS */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_GPIOLOCKSTATUS */ -#define GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT (_GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_GPIOLOCKSTATUS*/ -#define GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_GPIOLOCKSTATUS*/ -#define GPIO_GPIOLOCKSTATUS_LOCK_LOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_MASK 0x00000001UL /**< Mask for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK (0x1UL << 0) /**< GPIO LOCK status */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT (_GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_LOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_GPIOLOCKSTATUS */ /* Bit fields for GPIO ABUSALLOC */ -#define _GPIO_ABUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_SHIFT 0 /**< Shift value for GPIO_AEVEN0 */ -#define _GPIO_ABUSALLOC_AEVEN0_MASK 0xFUL /**< Bit mask for GPIO_AEVEN0 */ -#define _GPIO_ABUSALLOC_AEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_DEFAULT (_GPIO_ABUSALLOC_AEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_TRISTATE (_GPIO_ABUSALLOC_AEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_ADC0 (_GPIO_ABUSALLOC_AEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_ACMP0 (_GPIO_ABUSALLOC_AEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_ACMP1 (_GPIO_ABUSALLOC_AEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 (_GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_SHIFT 8 /**< Shift value for GPIO_AEVEN1 */ -#define _GPIO_ABUSALLOC_AEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_AEVEN1 */ -#define _GPIO_ABUSALLOC_AEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_DEFAULT (_GPIO_ABUSALLOC_AEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_TRISTATE (_GPIO_ABUSALLOC_AEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_ADC0 (_GPIO_ABUSALLOC_AEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_ACMP0 (_GPIO_ABUSALLOC_AEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_ACMP1 (_GPIO_ABUSALLOC_AEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 (_GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_SHIFT 16 /**< Shift value for GPIO_AODD0 */ -#define _GPIO_ABUSALLOC_AODD0_MASK 0xF0000UL /**< Bit mask for GPIO_AODD0 */ -#define _GPIO_ABUSALLOC_AODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_DEFAULT (_GPIO_ABUSALLOC_AODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_TRISTATE (_GPIO_ABUSALLOC_AODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_ADC0 (_GPIO_ABUSALLOC_AODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_ACMP0 (_GPIO_ABUSALLOC_AODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_ACMP1 (_GPIO_ABUSALLOC_AODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_VDAC0CH0 (_GPIO_ABUSALLOC_AODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_SHIFT 24 /**< Shift value for GPIO_AODD1 */ -#define _GPIO_ABUSALLOC_AODD1_MASK 0xF000000UL /**< Bit mask for GPIO_AODD1 */ -#define _GPIO_ABUSALLOC_AODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_DEFAULT (_GPIO_ABUSALLOC_AODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_TRISTATE (_GPIO_ABUSALLOC_AODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_ADC0 (_GPIO_ABUSALLOC_AODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_ACMP0 (_GPIO_ABUSALLOC_AODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_ACMP1 (_GPIO_ABUSALLOC_AODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_VDAC0CH1 (_GPIO_ABUSALLOC_AODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_SHIFT 0 /**< Shift value for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_MASK 0xFUL /**< Bit mask for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_DEFAULT (_GPIO_ABUSALLOC_AEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_TRISTATE (_GPIO_ABUSALLOC_AEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ADC0 (_GPIO_ABUSALLOC_AEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ACMP0 (_GPIO_ABUSALLOC_AEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ACMP1 (_GPIO_ABUSALLOC_AEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 (_GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_SHIFT 8 /**< Shift value for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_DEFAULT (_GPIO_ABUSALLOC_AEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_TRISTATE (_GPIO_ABUSALLOC_AEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ADC0 (_GPIO_ABUSALLOC_AEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ACMP0 (_GPIO_ABUSALLOC_AEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ACMP1 (_GPIO_ABUSALLOC_AEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 (_GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_SHIFT 16 /**< Shift value for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_MASK 0xF0000UL /**< Bit mask for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_DEFAULT (_GPIO_ABUSALLOC_AODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_TRISTATE (_GPIO_ABUSALLOC_AODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ADC0 (_GPIO_ABUSALLOC_AODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ACMP0 (_GPIO_ABUSALLOC_AODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ACMP1 (_GPIO_ABUSALLOC_AODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_VDAC0CH0 (_GPIO_ABUSALLOC_AODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_SHIFT 24 /**< Shift value for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_MASK 0xF000000UL /**< Bit mask for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_DEFAULT (_GPIO_ABUSALLOC_AODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_TRISTATE (_GPIO_ABUSALLOC_AODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ADC0 (_GPIO_ABUSALLOC_AODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ACMP0 (_GPIO_ABUSALLOC_AODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ACMP1 (_GPIO_ABUSALLOC_AODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_VDAC0CH1 (_GPIO_ABUSALLOC_AODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ /* Bit fields for GPIO BBUSALLOC */ -#define _GPIO_BBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_SHIFT 0 /**< Shift value for GPIO_BEVEN0 */ -#define _GPIO_BBUSALLOC_BEVEN0_MASK 0xFUL /**< Bit mask for GPIO_BEVEN0 */ -#define _GPIO_BBUSALLOC_BEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_DEFAULT (_GPIO_BBUSALLOC_BEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_TRISTATE (_GPIO_BBUSALLOC_BEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_ADC0 (_GPIO_BBUSALLOC_BEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_ACMP0 (_GPIO_BBUSALLOC_BEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_ACMP1 (_GPIO_BBUSALLOC_BEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 (_GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_SHIFT 8 /**< Shift value for GPIO_BEVEN1 */ -#define _GPIO_BBUSALLOC_BEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_BEVEN1 */ -#define _GPIO_BBUSALLOC_BEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_DEFAULT (_GPIO_BBUSALLOC_BEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_TRISTATE (_GPIO_BBUSALLOC_BEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_ADC0 (_GPIO_BBUSALLOC_BEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_ACMP0 (_GPIO_BBUSALLOC_BEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_ACMP1 (_GPIO_BBUSALLOC_BEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 (_GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_SHIFT 16 /**< Shift value for GPIO_BODD0 */ -#define _GPIO_BBUSALLOC_BODD0_MASK 0xF0000UL /**< Bit mask for GPIO_BODD0 */ -#define _GPIO_BBUSALLOC_BODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_DEFAULT (_GPIO_BBUSALLOC_BODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_TRISTATE (_GPIO_BBUSALLOC_BODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_ADC0 (_GPIO_BBUSALLOC_BODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_ACMP0 (_GPIO_BBUSALLOC_BODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_ACMP1 (_GPIO_BBUSALLOC_BODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_VDAC0CH0 (_GPIO_BBUSALLOC_BODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_SHIFT 24 /**< Shift value for GPIO_BODD1 */ -#define _GPIO_BBUSALLOC_BODD1_MASK 0xF000000UL /**< Bit mask for GPIO_BODD1 */ -#define _GPIO_BBUSALLOC_BODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_DEFAULT (_GPIO_BBUSALLOC_BODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_TRISTATE (_GPIO_BBUSALLOC_BODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_ADC0 (_GPIO_BBUSALLOC_BODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_ACMP0 (_GPIO_BBUSALLOC_BODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_ACMP1 (_GPIO_BBUSALLOC_BODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_VDAC0CH1 (_GPIO_BBUSALLOC_BODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_SHIFT 0 /**< Shift value for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_MASK 0xFUL /**< Bit mask for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_DEFAULT (_GPIO_BBUSALLOC_BEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_TRISTATE (_GPIO_BBUSALLOC_BEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ADC0 (_GPIO_BBUSALLOC_BEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ACMP0 (_GPIO_BBUSALLOC_BEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ACMP1 (_GPIO_BBUSALLOC_BEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 (_GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_SHIFT 8 /**< Shift value for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_DEFAULT (_GPIO_BBUSALLOC_BEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_TRISTATE (_GPIO_BBUSALLOC_BEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ADC0 (_GPIO_BBUSALLOC_BEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ACMP0 (_GPIO_BBUSALLOC_BEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ACMP1 (_GPIO_BBUSALLOC_BEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 (_GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_SHIFT 16 /**< Shift value for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_MASK 0xF0000UL /**< Bit mask for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_DEFAULT (_GPIO_BBUSALLOC_BODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_TRISTATE (_GPIO_BBUSALLOC_BODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ADC0 (_GPIO_BBUSALLOC_BODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ACMP0 (_GPIO_BBUSALLOC_BODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ACMP1 (_GPIO_BBUSALLOC_BODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_VDAC0CH0 (_GPIO_BBUSALLOC_BODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_SHIFT 24 /**< Shift value for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_MASK 0xF000000UL /**< Bit mask for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_DEFAULT (_GPIO_BBUSALLOC_BODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_TRISTATE (_GPIO_BBUSALLOC_BODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ADC0 (_GPIO_BBUSALLOC_BODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ACMP0 (_GPIO_BBUSALLOC_BODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ACMP1 (_GPIO_BBUSALLOC_BODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_VDAC0CH1 (_GPIO_BBUSALLOC_BODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ /* Bit fields for GPIO CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_SHIFT 0 /**< Shift value for GPIO_CDEVEN0 */ -#define _GPIO_CDBUSALLOC_CDEVEN0_MASK 0xFUL /**< Bit mask for GPIO_CDEVEN0 */ -#define _GPIO_CDBUSALLOC_CDEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_ADC0 (_GPIO_CDBUSALLOC_CDEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_SHIFT 8 /**< Shift value for GPIO_CDEVEN1 */ -#define _GPIO_CDBUSALLOC_CDEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_CDEVEN1 */ -#define _GPIO_CDBUSALLOC_CDEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_ADC0 (_GPIO_CDBUSALLOC_CDEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_SHIFT 16 /**< Shift value for GPIO_CDODD0 */ -#define _GPIO_CDBUSALLOC_CDODD0_MASK 0xF0000UL /**< Bit mask for GPIO_CDODD0 */ -#define _GPIO_CDBUSALLOC_CDODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_DEFAULT (_GPIO_CDBUSALLOC_CDODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_TRISTATE (_GPIO_CDBUSALLOC_CDODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_ADC0 (_GPIO_CDBUSALLOC_CDODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_ACMP0 (_GPIO_CDBUSALLOC_CDODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_ACMP1 (_GPIO_CDBUSALLOC_CDODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_SHIFT 24 /**< Shift value for GPIO_CDODD1 */ -#define _GPIO_CDBUSALLOC_CDODD1_MASK 0xF000000UL /**< Bit mask for GPIO_CDODD1 */ -#define _GPIO_CDBUSALLOC_CDODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_DEFAULT (_GPIO_CDBUSALLOC_CDODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_TRISTATE (_GPIO_CDBUSALLOC_CDODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_ADC0 (_GPIO_CDBUSALLOC_CDODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_ACMP0 (_GPIO_CDBUSALLOC_CDODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_ACMP1 (_GPIO_CDBUSALLOC_CDODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_SHIFT 0 /**< Shift value for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_MASK 0xFUL /**< Bit mask for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ADC0 (_GPIO_CDBUSALLOC_CDEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_SHIFT 8 /**< Shift value for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ADC0 (_GPIO_CDBUSALLOC_CDEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_SHIFT 16 /**< Shift value for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_MASK 0xF0000UL /**< Bit mask for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_DEFAULT (_GPIO_CDBUSALLOC_CDODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_TRISTATE (_GPIO_CDBUSALLOC_CDODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ADC0 (_GPIO_CDBUSALLOC_CDODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ACMP0 (_GPIO_CDBUSALLOC_CDODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ACMP1 (_GPIO_CDBUSALLOC_CDODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_SHIFT 24 /**< Shift value for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_MASK 0xF000000UL /**< Bit mask for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_DEFAULT (_GPIO_CDBUSALLOC_CDODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_TRISTATE (_GPIO_CDBUSALLOC_CDODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ADC0 (_GPIO_CDBUSALLOC_CDODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ACMP0 (_GPIO_CDBUSALLOC_CDODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ACMP1 (_GPIO_CDBUSALLOC_CDODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ /* Bit fields for GPIO EXTIPSELL */ -#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPSEL4 */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPSEL5 */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ /* Bit fields for GPIO EXTIPSELH */ -#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_MASK 0x33333333UL /**< Mask for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_PORTA (_GPIO_EXTIPSELH_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_PORTB (_GPIO_EXTIPSELH_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_PORTC (_GPIO_EXTIPSELH_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_PORTD (_GPIO_EXTIPSELH_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_PORTA (_GPIO_EXTIPSELH_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_PORTB (_GPIO_EXTIPSELH_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_PORTC (_GPIO_EXTIPSELH_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_PORTD (_GPIO_EXTIPSELH_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_PORTA (_GPIO_EXTIPSELH_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_PORTB (_GPIO_EXTIPSELH_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_PORTC (_GPIO_EXTIPSELH_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_PORTD (_GPIO_EXTIPSELH_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_PORTA (_GPIO_EXTIPSELH_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_PORTB (_GPIO_EXTIPSELH_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_PORTC (_GPIO_EXTIPSELH_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_PORTD (_GPIO_EXTIPSELH_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ -#define _GPIO_EXTIPSELH_EXTIPSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPSEL4 */ -#define _GPIO_EXTIPSELH_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL4_PORTA (_GPIO_EXTIPSELH_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL4_PORTB (_GPIO_EXTIPSELH_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL4_PORTC (_GPIO_EXTIPSELH_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL4_PORTD (_GPIO_EXTIPSELH_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ -#define _GPIO_EXTIPSELH_EXTIPSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPSEL5 */ -#define _GPIO_EXTIPSELH_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL5_PORTA (_GPIO_EXTIPSELH_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL5_PORTB (_GPIO_EXTIPSELH_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL5_PORTC (_GPIO_EXTIPSELH_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL5_PORTD (_GPIO_EXTIPSELH_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ -#define _GPIO_EXTIPSELH_EXTIPSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ -#define _GPIO_EXTIPSELH_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL6_PORTA (_GPIO_EXTIPSELH_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL6_PORTB (_GPIO_EXTIPSELH_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL6_PORTC (_GPIO_EXTIPSELH_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL6_PORTD (_GPIO_EXTIPSELH_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ -#define _GPIO_EXTIPSELH_EXTIPSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ -#define _GPIO_EXTIPSELH_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL7_PORTA (_GPIO_EXTIPSELH_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL7_PORTB (_GPIO_EXTIPSELH_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL7_PORTC (_GPIO_EXTIPSELH_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL7_PORTD (_GPIO_EXTIPSELH_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_MASK 0x33333333UL /**< Mask for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTA (_GPIO_EXTIPSELH_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTB (_GPIO_EXTIPSELH_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTC (_GPIO_EXTIPSELH_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTD (_GPIO_EXTIPSELH_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTA (_GPIO_EXTIPSELH_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTB (_GPIO_EXTIPSELH_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTC (_GPIO_EXTIPSELH_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTD (_GPIO_EXTIPSELH_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTA (_GPIO_EXTIPSELH_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTB (_GPIO_EXTIPSELH_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTC (_GPIO_EXTIPSELH_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTD (_GPIO_EXTIPSELH_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTA (_GPIO_EXTIPSELH_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTB (_GPIO_EXTIPSELH_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTC (_GPIO_EXTIPSELH_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTD (_GPIO_EXTIPSELH_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELH_EXTIPSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELH_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL4_PORTA (_GPIO_EXTIPSELH_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL4_PORTB (_GPIO_EXTIPSELH_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL4_PORTC (_GPIO_EXTIPSELH_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL4_PORTD (_GPIO_EXTIPSELH_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELH_EXTIPSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELH_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL5_PORTA (_GPIO_EXTIPSELH_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL5_PORTB (_GPIO_EXTIPSELH_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL5_PORTC (_GPIO_EXTIPSELH_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL5_PORTD (_GPIO_EXTIPSELH_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELH_EXTIPSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELH_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL6_PORTA (_GPIO_EXTIPSELH_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL6_PORTB (_GPIO_EXTIPSELH_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL6_PORTC (_GPIO_EXTIPSELH_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL6_PORTD (_GPIO_EXTIPSELH_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELH_EXTIPSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELH_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL7_PORTA (_GPIO_EXTIPSELH_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL7_PORTB (_GPIO_EXTIPSELH_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL7_PORTC (_GPIO_EXTIPSELH_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL7_PORTD (_GPIO_EXTIPSELH_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ /* Bit fields for GPIO EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 << 16) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 << 16) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 << 16) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 << 16) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 << 20) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 << 20) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 << 20) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 << 20) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 << 24) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 << 24) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 << 24) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 << 24) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 << 28) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 << 28) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 << 28) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 << 28) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 << 16) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 << 16) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 << 16) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 << 16) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 << 20) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 << 20) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 << 20) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 << 20) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 << 24) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 << 24) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 << 24) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 << 24) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 << 28) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 << 28) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 << 28) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 << 28) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ /* Bit fields for GPIO EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL4_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL4_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL4_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL4_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL4_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL4_PIN8 << 16) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL4_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL4_PIN9 << 16) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL4_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL4_PIN10 << 16) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL4_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL4_PIN11 << 16) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL5_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL5_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL5_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL5_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL5_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL5_PIN8 << 20) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL5_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL5_PIN9 << 20) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL5_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL5_PIN10 << 20) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL5_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL5_PIN11 << 20) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL6_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL6_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL6_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL6_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL6_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL6_PIN8 << 24) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL6_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL6_PIN9 << 24) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL6_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL6_PIN10 << 24) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL6_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL6_PIN11 << 24) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL7_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL7_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL7_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL7_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL7_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL7_PIN8 << 28) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL7_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL7_PIN9 << 28) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL7_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL7_PIN10 << 28) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL7_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL7_PIN11 << 28) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL4_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL4_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL4_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL4_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL4_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL4_PIN8 << 16) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL4_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL4_PIN9 << 16) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL4_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL4_PIN10 << 16) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL4_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL4_PIN11 << 16) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL5_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL5_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL5_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL5_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL5_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL5_PIN8 << 20) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL5_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL5_PIN9 << 20) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL5_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL5_PIN10 << 20) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL5_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL5_PIN11 << 20) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL6_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL6_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL6_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL6_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL6_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL6_PIN8 << 24) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL6_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL6_PIN9 << 24) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL6_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL6_PIN10 << 24) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL6_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL6_PIN11 << 24) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL7_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL7_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL7_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL7_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL7_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL7_PIN8 << 28) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL7_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL7_PIN9 << 28) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL7_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL7_PIN10 << 28) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL7_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL7_PIN11 << 28) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ /* Bit fields for GPIO EXTIRISE */ -#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ -#define _GPIO_EXTIRISE_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIRISE */ -#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ -#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIRISE */ -#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ -#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ +#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ /* Bit fields for GPIO EXTIFALL */ -#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ -#define _GPIO_EXTIFALL_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIFALL */ -#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ -#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIFALL */ -#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ -#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ +#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ /* Bit fields for GPIO IF */ -#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ -#define _GPIO_IF_MASK 0x0FFFFFFFUL /**< Mask for GPIO_IF */ -#define GPIO_IF_EXTIF0 (0x1UL << 0) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF0_SHIFT 0 /**< Shift value for GPIO_EXTIF0 */ -#define _GPIO_IF_EXTIF0_MASK 0x1UL /**< Bit mask for GPIO_EXTIF0 */ -#define _GPIO_IF_EXTIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF0_DEFAULT (_GPIO_IF_EXTIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF1 (0x1UL << 1) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF1_SHIFT 1 /**< Shift value for GPIO_EXTIF1 */ -#define _GPIO_IF_EXTIF1_MASK 0x2UL /**< Bit mask for GPIO_EXTIF1 */ -#define _GPIO_IF_EXTIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF1_DEFAULT (_GPIO_IF_EXTIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF2 (0x1UL << 2) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF2_SHIFT 2 /**< Shift value for GPIO_EXTIF2 */ -#define _GPIO_IF_EXTIF2_MASK 0x4UL /**< Bit mask for GPIO_EXTIF2 */ -#define _GPIO_IF_EXTIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF2_DEFAULT (_GPIO_IF_EXTIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF3 (0x1UL << 3) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF3_SHIFT 3 /**< Shift value for GPIO_EXTIF3 */ -#define _GPIO_IF_EXTIF3_MASK 0x8UL /**< Bit mask for GPIO_EXTIF3 */ -#define _GPIO_IF_EXTIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF3_DEFAULT (_GPIO_IF_EXTIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF4 (0x1UL << 4) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF4_SHIFT 4 /**< Shift value for GPIO_EXTIF4 */ -#define _GPIO_IF_EXTIF4_MASK 0x10UL /**< Bit mask for GPIO_EXTIF4 */ -#define _GPIO_IF_EXTIF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF4_DEFAULT (_GPIO_IF_EXTIF4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF5 (0x1UL << 5) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF5_SHIFT 5 /**< Shift value for GPIO_EXTIF5 */ -#define _GPIO_IF_EXTIF5_MASK 0x20UL /**< Bit mask for GPIO_EXTIF5 */ -#define _GPIO_IF_EXTIF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF5_DEFAULT (_GPIO_IF_EXTIF5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF6 (0x1UL << 6) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF6_SHIFT 6 /**< Shift value for GPIO_EXTIF6 */ -#define _GPIO_IF_EXTIF6_MASK 0x40UL /**< Bit mask for GPIO_EXTIF6 */ -#define _GPIO_IF_EXTIF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF6_DEFAULT (_GPIO_IF_EXTIF6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF7 (0x1UL << 7) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF7_SHIFT 7 /**< Shift value for GPIO_EXTIF7 */ -#define _GPIO_IF_EXTIF7_MASK 0x80UL /**< Bit mask for GPIO_EXTIF7 */ -#define _GPIO_IF_EXTIF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF7_DEFAULT (_GPIO_IF_EXTIF7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF8 (0x1UL << 8) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF8_SHIFT 8 /**< Shift value for GPIO_EXTIF8 */ -#define _GPIO_IF_EXTIF8_MASK 0x100UL /**< Bit mask for GPIO_EXTIF8 */ -#define _GPIO_IF_EXTIF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF8_DEFAULT (_GPIO_IF_EXTIF8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF9 (0x1UL << 9) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF9_SHIFT 9 /**< Shift value for GPIO_EXTIF9 */ -#define _GPIO_IF_EXTIF9_MASK 0x200UL /**< Bit mask for GPIO_EXTIF9 */ -#define _GPIO_IF_EXTIF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF9_DEFAULT (_GPIO_IF_EXTIF9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF10 (0x1UL << 10) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF10_SHIFT 10 /**< Shift value for GPIO_EXTIF10 */ -#define _GPIO_IF_EXTIF10_MASK 0x400UL /**< Bit mask for GPIO_EXTIF10 */ -#define _GPIO_IF_EXTIF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF10_DEFAULT (_GPIO_IF_EXTIF10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF11 (0x1UL << 11) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF11_SHIFT 11 /**< Shift value for GPIO_EXTIF11 */ -#define _GPIO_IF_EXTIF11_MASK 0x800UL /**< Bit mask for GPIO_EXTIF11 */ -#define _GPIO_IF_EXTIF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF11_DEFAULT (_GPIO_IF_EXTIF11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF12 (0x1UL << 12) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF12_SHIFT 12 /**< Shift value for GPIO_EXTIF12 */ -#define _GPIO_IF_EXTIF12_MASK 0x1000UL /**< Bit mask for GPIO_EXTIF12 */ -#define _GPIO_IF_EXTIF12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF12_DEFAULT (_GPIO_IF_EXTIF12_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF13 (0x1UL << 13) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF13_SHIFT 13 /**< Shift value for GPIO_EXTIF13 */ -#define _GPIO_IF_EXTIF13_MASK 0x2000UL /**< Bit mask for GPIO_EXTIF13 */ -#define _GPIO_IF_EXTIF13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF13_DEFAULT (_GPIO_IF_EXTIF13_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF14 (0x1UL << 14) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF14_SHIFT 14 /**< Shift value for GPIO_EXTIF14 */ -#define _GPIO_IF_EXTIF14_MASK 0x4000UL /**< Bit mask for GPIO_EXTIF14 */ -#define _GPIO_IF_EXTIF14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF14_DEFAULT (_GPIO_IF_EXTIF14_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF15 (0x1UL << 15) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF15_SHIFT 15 /**< Shift value for GPIO_EXTIF15 */ -#define _GPIO_IF_EXTIF15_MASK 0x8000UL /**< Bit mask for GPIO_EXTIF15 */ -#define _GPIO_IF_EXTIF15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF15_DEFAULT (_GPIO_IF_EXTIF15_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_IF */ -#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ -#define _GPIO_IF_EM4WU_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WU */ -#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ +#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ +#define _GPIO_IF_MASK 0x0FFFFFFFUL /**< Mask for GPIO_IF */ +#define GPIO_IF_EXTIF0 (0x1UL << 0) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF0_SHIFT 0 /**< Shift value for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_MASK 0x1UL /**< Bit mask for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF0_DEFAULT (_GPIO_IF_EXTIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1 (0x1UL << 1) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF1_SHIFT 1 /**< Shift value for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_MASK 0x2UL /**< Bit mask for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1_DEFAULT (_GPIO_IF_EXTIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2 (0x1UL << 2) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF2_SHIFT 2 /**< Shift value for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_MASK 0x4UL /**< Bit mask for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2_DEFAULT (_GPIO_IF_EXTIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3 (0x1UL << 3) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF3_SHIFT 3 /**< Shift value for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_MASK 0x8UL /**< Bit mask for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3_DEFAULT (_GPIO_IF_EXTIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4 (0x1UL << 4) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF4_SHIFT 4 /**< Shift value for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_MASK 0x10UL /**< Bit mask for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4_DEFAULT (_GPIO_IF_EXTIF4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5 (0x1UL << 5) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF5_SHIFT 5 /**< Shift value for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_MASK 0x20UL /**< Bit mask for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5_DEFAULT (_GPIO_IF_EXTIF5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6 (0x1UL << 6) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF6_SHIFT 6 /**< Shift value for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_MASK 0x40UL /**< Bit mask for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6_DEFAULT (_GPIO_IF_EXTIF6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7 (0x1UL << 7) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF7_SHIFT 7 /**< Shift value for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_MASK 0x80UL /**< Bit mask for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7_DEFAULT (_GPIO_IF_EXTIF7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8 (0x1UL << 8) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF8_SHIFT 8 /**< Shift value for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_MASK 0x100UL /**< Bit mask for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8_DEFAULT (_GPIO_IF_EXTIF8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9 (0x1UL << 9) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF9_SHIFT 9 /**< Shift value for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_MASK 0x200UL /**< Bit mask for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9_DEFAULT (_GPIO_IF_EXTIF9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10 (0x1UL << 10) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF10_SHIFT 10 /**< Shift value for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_MASK 0x400UL /**< Bit mask for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10_DEFAULT (_GPIO_IF_EXTIF10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11 (0x1UL << 11) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF11_SHIFT 11 /**< Shift value for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_MASK 0x800UL /**< Bit mask for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11_DEFAULT (_GPIO_IF_EXTIF11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF12 (0x1UL << 12) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF12_SHIFT 12 /**< Shift value for GPIO_EXTIF12 */ +#define _GPIO_IF_EXTIF12_MASK 0x1000UL /**< Bit mask for GPIO_EXTIF12 */ +#define _GPIO_IF_EXTIF12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF12_DEFAULT (_GPIO_IF_EXTIF12_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF13 (0x1UL << 13) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF13_SHIFT 13 /**< Shift value for GPIO_EXTIF13 */ +#define _GPIO_IF_EXTIF13_MASK 0x2000UL /**< Bit mask for GPIO_EXTIF13 */ +#define _GPIO_IF_EXTIF13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF13_DEFAULT (_GPIO_IF_EXTIF13_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF14 (0x1UL << 14) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF14_SHIFT 14 /**< Shift value for GPIO_EXTIF14 */ +#define _GPIO_IF_EXTIF14_MASK 0x4000UL /**< Bit mask for GPIO_EXTIF14 */ +#define _GPIO_IF_EXTIF14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF14_DEFAULT (_GPIO_IF_EXTIF14_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF15 (0x1UL << 15) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF15_SHIFT 15 /**< Shift value for GPIO_EXTIF15 */ +#define _GPIO_IF_EXTIF15_MASK 0x8000UL /**< Bit mask for GPIO_EXTIF15 */ +#define _GPIO_IF_EXTIF15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF15_DEFAULT (_GPIO_IF_EXTIF15_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_IF */ +#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ /* Bit fields for GPIO IEN */ -#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ -#define _GPIO_IEN_MASK 0x0FFFFFFFUL /**< Mask for GPIO_IEN */ -#define GPIO_IEN_EXTIEN0 (0x1UL << 0) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN0_SHIFT 0 /**< Shift value for GPIO_EXTIEN0 */ -#define _GPIO_IEN_EXTIEN0_MASK 0x1UL /**< Bit mask for GPIO_EXTIEN0 */ -#define _GPIO_IEN_EXTIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN0_DEFAULT (_GPIO_IEN_EXTIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN1 (0x1UL << 1) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN1_SHIFT 1 /**< Shift value for GPIO_EXTIEN1 */ -#define _GPIO_IEN_EXTIEN1_MASK 0x2UL /**< Bit mask for GPIO_EXTIEN1 */ -#define _GPIO_IEN_EXTIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN1_DEFAULT (_GPIO_IEN_EXTIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN2 (0x1UL << 2) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN2_SHIFT 2 /**< Shift value for GPIO_EXTIEN2 */ -#define _GPIO_IEN_EXTIEN2_MASK 0x4UL /**< Bit mask for GPIO_EXTIEN2 */ -#define _GPIO_IEN_EXTIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN2_DEFAULT (_GPIO_IEN_EXTIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN3 (0x1UL << 3) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN3_SHIFT 3 /**< Shift value for GPIO_EXTIEN3 */ -#define _GPIO_IEN_EXTIEN3_MASK 0x8UL /**< Bit mask for GPIO_EXTIEN3 */ -#define _GPIO_IEN_EXTIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN3_DEFAULT (_GPIO_IEN_EXTIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN4 (0x1UL << 4) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN4_SHIFT 4 /**< Shift value for GPIO_EXTIEN4 */ -#define _GPIO_IEN_EXTIEN4_MASK 0x10UL /**< Bit mask for GPIO_EXTIEN4 */ -#define _GPIO_IEN_EXTIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN4_DEFAULT (_GPIO_IEN_EXTIEN4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN5 (0x1UL << 5) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN5_SHIFT 5 /**< Shift value for GPIO_EXTIEN5 */ -#define _GPIO_IEN_EXTIEN5_MASK 0x20UL /**< Bit mask for GPIO_EXTIEN5 */ -#define _GPIO_IEN_EXTIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN5_DEFAULT (_GPIO_IEN_EXTIEN5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN6 (0x1UL << 6) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN6_SHIFT 6 /**< Shift value for GPIO_EXTIEN6 */ -#define _GPIO_IEN_EXTIEN6_MASK 0x40UL /**< Bit mask for GPIO_EXTIEN6 */ -#define _GPIO_IEN_EXTIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN6_DEFAULT (_GPIO_IEN_EXTIEN6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN7 (0x1UL << 7) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN7_SHIFT 7 /**< Shift value for GPIO_EXTIEN7 */ -#define _GPIO_IEN_EXTIEN7_MASK 0x80UL /**< Bit mask for GPIO_EXTIEN7 */ -#define _GPIO_IEN_EXTIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN7_DEFAULT (_GPIO_IEN_EXTIEN7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN8 (0x1UL << 8) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN8_SHIFT 8 /**< Shift value for GPIO_EXTIEN8 */ -#define _GPIO_IEN_EXTIEN8_MASK 0x100UL /**< Bit mask for GPIO_EXTIEN8 */ -#define _GPIO_IEN_EXTIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN8_DEFAULT (_GPIO_IEN_EXTIEN8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN9 (0x1UL << 9) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN9_SHIFT 9 /**< Shift value for GPIO_EXTIEN9 */ -#define _GPIO_IEN_EXTIEN9_MASK 0x200UL /**< Bit mask for GPIO_EXTIEN9 */ -#define _GPIO_IEN_EXTIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN9_DEFAULT (_GPIO_IEN_EXTIEN9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN10 (0x1UL << 10) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN10_SHIFT 10 /**< Shift value for GPIO_EXTIEN10 */ -#define _GPIO_IEN_EXTIEN10_MASK 0x400UL /**< Bit mask for GPIO_EXTIEN10 */ -#define _GPIO_IEN_EXTIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN10_DEFAULT (_GPIO_IEN_EXTIEN10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN11 (0x1UL << 11) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN11_SHIFT 11 /**< Shift value for GPIO_EXTIEN11 */ -#define _GPIO_IEN_EXTIEN11_MASK 0x800UL /**< Bit mask for GPIO_EXTIEN11 */ -#define _GPIO_IEN_EXTIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN11_DEFAULT (_GPIO_IEN_EXTIEN11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN12 (0x1UL << 12) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN12_SHIFT 12 /**< Shift value for GPIO_EXTIEN12 */ -#define _GPIO_IEN_EXTIEN12_MASK 0x1000UL /**< Bit mask for GPIO_EXTIEN12 */ -#define _GPIO_IEN_EXTIEN12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN12_DEFAULT (_GPIO_IEN_EXTIEN12_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN13 (0x1UL << 13) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN13_SHIFT 13 /**< Shift value for GPIO_EXTIEN13 */ -#define _GPIO_IEN_EXTIEN13_MASK 0x2000UL /**< Bit mask for GPIO_EXTIEN13 */ -#define _GPIO_IEN_EXTIEN13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN13_DEFAULT (_GPIO_IEN_EXTIEN13_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN14 (0x1UL << 14) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN14_SHIFT 14 /**< Shift value for GPIO_EXTIEN14 */ -#define _GPIO_IEN_EXTIEN14_MASK 0x4000UL /**< Bit mask for GPIO_EXTIEN14 */ -#define _GPIO_IEN_EXTIEN14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN14_DEFAULT (_GPIO_IEN_EXTIEN14_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN15 (0x1UL << 15) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN15_SHIFT 15 /**< Shift value for GPIO_EXTIEN15 */ -#define _GPIO_IEN_EXTIEN15_MASK 0x8000UL /**< Bit mask for GPIO_EXTIEN15 */ -#define _GPIO_IEN_EXTIEN15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN15_DEFAULT (_GPIO_IEN_EXTIEN15_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN0 (0x1UL << 16) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN0_SHIFT 16 /**< Shift value for GPIO_EM4WUIEN0 */ -#define _GPIO_IEN_EM4WUIEN0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WUIEN0 */ -#define _GPIO_IEN_EM4WUIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN0_DEFAULT (_GPIO_IEN_EM4WUIEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN1 (0x1UL << 17) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN1_SHIFT 17 /**< Shift value for GPIO_EM4WUIEN1 */ -#define _GPIO_IEN_EM4WUIEN1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WUIEN1 */ -#define _GPIO_IEN_EM4WUIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN1_DEFAULT (_GPIO_IEN_EM4WUIEN1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN2 (0x1UL << 18) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN2_SHIFT 18 /**< Shift value for GPIO_EM4WUIEN2 */ -#define _GPIO_IEN_EM4WUIEN2_MASK 0x40000UL /**< Bit mask for GPIO_EM4WUIEN2 */ -#define _GPIO_IEN_EM4WUIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN2_DEFAULT (_GPIO_IEN_EM4WUIEN2_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN3 (0x1UL << 19) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN3_SHIFT 19 /**< Shift value for GPIO_EM4WUIEN3 */ -#define _GPIO_IEN_EM4WUIEN3_MASK 0x80000UL /**< Bit mask for GPIO_EM4WUIEN3 */ -#define _GPIO_IEN_EM4WUIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN3_DEFAULT (_GPIO_IEN_EM4WUIEN3_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN4 (0x1UL << 20) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN4_SHIFT 20 /**< Shift value for GPIO_EM4WUIEN4 */ -#define _GPIO_IEN_EM4WUIEN4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WUIEN4 */ -#define _GPIO_IEN_EM4WUIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN4_DEFAULT (_GPIO_IEN_EM4WUIEN4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN5 (0x1UL << 21) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN5_SHIFT 21 /**< Shift value for GPIO_EM4WUIEN5 */ -#define _GPIO_IEN_EM4WUIEN5_MASK 0x200000UL /**< Bit mask for GPIO_EM4WUIEN5 */ -#define _GPIO_IEN_EM4WUIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN5_DEFAULT (_GPIO_IEN_EM4WUIEN5_DEFAULT << 21) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN6 (0x1UL << 22) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN6_SHIFT 22 /**< Shift value for GPIO_EM4WUIEN6 */ -#define _GPIO_IEN_EM4WUIEN6_MASK 0x400000UL /**< Bit mask for GPIO_EM4WUIEN6 */ -#define _GPIO_IEN_EM4WUIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN6_DEFAULT (_GPIO_IEN_EM4WUIEN6_DEFAULT << 22) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN7 (0x1UL << 23) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN7_SHIFT 23 /**< Shift value for GPIO_EM4WUIEN7 */ -#define _GPIO_IEN_EM4WUIEN7_MASK 0x800000UL /**< Bit mask for GPIO_EM4WUIEN7 */ -#define _GPIO_IEN_EM4WUIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN7_DEFAULT (_GPIO_IEN_EM4WUIEN7_DEFAULT << 23) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN8 (0x1UL << 24) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN8_SHIFT 24 /**< Shift value for GPIO_EM4WUIEN8 */ -#define _GPIO_IEN_EM4WUIEN8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WUIEN8 */ -#define _GPIO_IEN_EM4WUIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN8_DEFAULT (_GPIO_IEN_EM4WUIEN8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN9 (0x1UL << 25) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN9_SHIFT 25 /**< Shift value for GPIO_EM4WUIEN9 */ -#define _GPIO_IEN_EM4WUIEN9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WUIEN9 */ -#define _GPIO_IEN_EM4WUIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN9_DEFAULT (_GPIO_IEN_EM4WUIEN9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN10 (0x1UL << 26) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN10_SHIFT 26 /**< Shift value for GPIO_EM4WUIEN10 */ -#define _GPIO_IEN_EM4WUIEN10_MASK 0x4000000UL /**< Bit mask for GPIO_EM4WUIEN10 */ -#define _GPIO_IEN_EM4WUIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN10_DEFAULT (_GPIO_IEN_EM4WUIEN10_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN11 (0x1UL << 27) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN11_SHIFT 27 /**< Shift value for GPIO_EM4WUIEN11 */ -#define _GPIO_IEN_EM4WUIEN11_MASK 0x8000000UL /**< Bit mask for GPIO_EM4WUIEN11 */ -#define _GPIO_IEN_EM4WUIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN11_DEFAULT (_GPIO_IEN_EM4WUIEN11_DEFAULT << 27) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ +#define _GPIO_IEN_MASK 0x0FFFFFFFUL /**< Mask for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0 (0x1UL << 0) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN0_SHIFT 0 /**< Shift value for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_MASK 0x1UL /**< Bit mask for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0_DEFAULT (_GPIO_IEN_EXTIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1 (0x1UL << 1) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN1_SHIFT 1 /**< Shift value for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_MASK 0x2UL /**< Bit mask for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1_DEFAULT (_GPIO_IEN_EXTIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2 (0x1UL << 2) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN2_SHIFT 2 /**< Shift value for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_MASK 0x4UL /**< Bit mask for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2_DEFAULT (_GPIO_IEN_EXTIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3 (0x1UL << 3) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN3_SHIFT 3 /**< Shift value for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_MASK 0x8UL /**< Bit mask for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3_DEFAULT (_GPIO_IEN_EXTIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4 (0x1UL << 4) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN4_SHIFT 4 /**< Shift value for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_MASK 0x10UL /**< Bit mask for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4_DEFAULT (_GPIO_IEN_EXTIEN4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5 (0x1UL << 5) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN5_SHIFT 5 /**< Shift value for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_MASK 0x20UL /**< Bit mask for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5_DEFAULT (_GPIO_IEN_EXTIEN5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6 (0x1UL << 6) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN6_SHIFT 6 /**< Shift value for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_MASK 0x40UL /**< Bit mask for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6_DEFAULT (_GPIO_IEN_EXTIEN6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7 (0x1UL << 7) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN7_SHIFT 7 /**< Shift value for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_MASK 0x80UL /**< Bit mask for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7_DEFAULT (_GPIO_IEN_EXTIEN7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8 (0x1UL << 8) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN8_SHIFT 8 /**< Shift value for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_MASK 0x100UL /**< Bit mask for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8_DEFAULT (_GPIO_IEN_EXTIEN8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9 (0x1UL << 9) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN9_SHIFT 9 /**< Shift value for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_MASK 0x200UL /**< Bit mask for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9_DEFAULT (_GPIO_IEN_EXTIEN9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10 (0x1UL << 10) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN10_SHIFT 10 /**< Shift value for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_MASK 0x400UL /**< Bit mask for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10_DEFAULT (_GPIO_IEN_EXTIEN10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11 (0x1UL << 11) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN11_SHIFT 11 /**< Shift value for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_MASK 0x800UL /**< Bit mask for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11_DEFAULT (_GPIO_IEN_EXTIEN11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN12 (0x1UL << 12) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN12_SHIFT 12 /**< Shift value for GPIO_EXTIEN12 */ +#define _GPIO_IEN_EXTIEN12_MASK 0x1000UL /**< Bit mask for GPIO_EXTIEN12 */ +#define _GPIO_IEN_EXTIEN12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN12_DEFAULT (_GPIO_IEN_EXTIEN12_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN13 (0x1UL << 13) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN13_SHIFT 13 /**< Shift value for GPIO_EXTIEN13 */ +#define _GPIO_IEN_EXTIEN13_MASK 0x2000UL /**< Bit mask for GPIO_EXTIEN13 */ +#define _GPIO_IEN_EXTIEN13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN13_DEFAULT (_GPIO_IEN_EXTIEN13_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN14 (0x1UL << 14) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN14_SHIFT 14 /**< Shift value for GPIO_EXTIEN14 */ +#define _GPIO_IEN_EXTIEN14_MASK 0x4000UL /**< Bit mask for GPIO_EXTIEN14 */ +#define _GPIO_IEN_EXTIEN14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN14_DEFAULT (_GPIO_IEN_EXTIEN14_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN15 (0x1UL << 15) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN15_SHIFT 15 /**< Shift value for GPIO_EXTIEN15 */ +#define _GPIO_IEN_EXTIEN15_MASK 0x8000UL /**< Bit mask for GPIO_EXTIEN15 */ +#define _GPIO_IEN_EXTIEN15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN15_DEFAULT (_GPIO_IEN_EXTIEN15_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0 (0x1UL << 16) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN0_SHIFT 16 /**< Shift value for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0_DEFAULT (_GPIO_IEN_EM4WUIEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1 (0x1UL << 17) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN1_SHIFT 17 /**< Shift value for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1_DEFAULT (_GPIO_IEN_EM4WUIEN1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2 (0x1UL << 18) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN2_SHIFT 18 /**< Shift value for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_MASK 0x40000UL /**< Bit mask for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2_DEFAULT (_GPIO_IEN_EM4WUIEN2_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3 (0x1UL << 19) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN3_SHIFT 19 /**< Shift value for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_MASK 0x80000UL /**< Bit mask for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3_DEFAULT (_GPIO_IEN_EM4WUIEN3_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4 (0x1UL << 20) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN4_SHIFT 20 /**< Shift value for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4_DEFAULT (_GPIO_IEN_EM4WUIEN4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5 (0x1UL << 21) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN5_SHIFT 21 /**< Shift value for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_MASK 0x200000UL /**< Bit mask for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5_DEFAULT (_GPIO_IEN_EM4WUIEN5_DEFAULT << 21) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6 (0x1UL << 22) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN6_SHIFT 22 /**< Shift value for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_MASK 0x400000UL /**< Bit mask for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6_DEFAULT (_GPIO_IEN_EM4WUIEN6_DEFAULT << 22) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7 (0x1UL << 23) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN7_SHIFT 23 /**< Shift value for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_MASK 0x800000UL /**< Bit mask for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7_DEFAULT (_GPIO_IEN_EM4WUIEN7_DEFAULT << 23) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8 (0x1UL << 24) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN8_SHIFT 24 /**< Shift value for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8_DEFAULT (_GPIO_IEN_EM4WUIEN8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9 (0x1UL << 25) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN9_SHIFT 25 /**< Shift value for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9_DEFAULT (_GPIO_IEN_EM4WUIEN9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10 (0x1UL << 26) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN10_SHIFT 26 /**< Shift value for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_MASK 0x4000000UL /**< Bit mask for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10_DEFAULT (_GPIO_IEN_EM4WUIEN10_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11 (0x1UL << 27) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN11_SHIFT 27 /**< Shift value for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_MASK 0x8000000UL /**< Bit mask for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11_DEFAULT (_GPIO_IEN_EM4WUIEN11_DEFAULT << 27) /**< Shifted mode DEFAULT for GPIO_IEN */ /* Bit fields for GPIO EM4WUEN */ -#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ -#define _GPIO_EM4WUEN_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUEN */ -#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ -#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ -#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ -#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ +#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ /* Bit fields for GPIO EM4WUPOL */ -#define _GPIO_EM4WUPOL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUPOL */ -#define _GPIO_EM4WUPOL_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUPOL */ -#define _GPIO_EM4WUPOL_EM4WUPOL_SHIFT 16 /**< Shift value for GPIO_EM4WUPOL */ -#define _GPIO_EM4WUPOL_EM4WUPOL_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUPOL */ -#define _GPIO_EM4WUPOL_EM4WUPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUPOL */ -#define GPIO_EM4WUPOL_EM4WUPOL_DEFAULT (_GPIO_EM4WUPOL_EM4WUPOL_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_SHIFT 16 /**< Shift value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUPOL */ +#define GPIO_EM4WUPOL_EM4WUPOL_DEFAULT (_GPIO_EM4WUPOL_EM4WUPOL_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUPOL */ /* Bit fields for GPIO DBGROUTEPEN */ -#define _GPIO_DBGROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_DBGROUTEPEN */ -#define _GPIO_DBGROUTEPEN_MASK 0x0000000FUL /**< Mask for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Route Pin Enable */ -#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ -#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ -#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Route Location 0 */ -#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ -#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ -#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ -#define _GPIO_DBGROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ -#define _GPIO_DBGROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ -#define _GPIO_DBGROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_TDOPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ -#define _GPIO_DBGROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ -#define _GPIO_DBGROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ -#define _GPIO_DBGROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_TDIPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_MASK 0x0000000FUL /**< Mask for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Route Pin Enable */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Route Location 0 */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ /* Bit fields for GPIO TRACEROUTEPEN */ -#define _GPIO_TRACEROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TRACEROUTEPEN */ -#define _GPIO_TRACEROUTEPEN_MASK 0x0000003FUL /**< Mask for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_SWVPEN (0x1UL << 0) /**< Serial Wire Viewer Output Pin Enable */ -#define _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT 0 /**< Shift value for GPIO_SWVPEN */ -#define _GPIO_TRACEROUTEPEN_SWVPEN_MASK 0x1UL /**< Bit mask for GPIO_SWVPEN */ -#define _GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT (_GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACECLKPEN (0x1UL << 1) /**< Trace Clk Pin Enable */ -#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_SHIFT 1 /**< Shift value for GPIO_TRACECLKPEN */ -#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_MASK 0x2UL /**< Bit mask for GPIO_TRACECLKPEN */ -#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN (0x1UL << 2) /**< Trace Data0 Pin Enable */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_SHIFT 2 /**< Shift value for GPIO_TRACEDATA0PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_MASK 0x4UL /**< Bit mask for GPIO_TRACEDATA0PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN (0x1UL << 3) /**< Trace Data1 Pin Enable */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_SHIFT 3 /**< Shift value for GPIO_TRACEDATA1PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_MASK 0x8UL /**< Bit mask for GPIO_TRACEDATA1PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN (0x1UL << 4) /**< Trace Data2 Pin Enable */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_SHIFT 4 /**< Shift value for GPIO_TRACEDATA2PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_MASK 0x10UL /**< Bit mask for GPIO_TRACEDATA2PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN (0x1UL << 5) /**< Trace Data3 Pin Enable */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_SHIFT 5 /**< Shift value for GPIO_TRACEDATA3PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_MASK 0x20UL /**< Bit mask for GPIO_TRACEDATA3PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_MASK 0x0000003FUL /**< Mask for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN (0x1UL << 0) /**< Serial Wire Viewer Output Pin Enable */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT 0 /**< Shift value for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_MASK 0x1UL /**< Bit mask for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT (_GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN (0x1UL << 1) /**< Trace Clk Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_SHIFT 1 /**< Shift value for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_MASK 0x2UL /**< Bit mask for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN (0x1UL << 2) /**< Trace Data0 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_SHIFT 2 /**< Shift value for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_MASK 0x4UL /**< Bit mask for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN (0x1UL << 3) /**< Trace Data1 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_SHIFT 3 /**< Shift value for GPIO_TRACEDATA1PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_MASK 0x8UL /**< Bit mask for GPIO_TRACEDATA1PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN (0x1UL << 4) /**< Trace Data2 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_SHIFT 4 /**< Shift value for GPIO_TRACEDATA2PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_MASK 0x10UL /**< Bit mask for GPIO_TRACEDATA2PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN (0x1UL << 5) /**< Trace Data3 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_SHIFT 5 /**< Shift value for GPIO_TRACEDATA3PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_MASK 0x20UL /**< Bit mask for GPIO_TRACEDATA3PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ /* Bit fields for GPIO LCDSEG */ -#define _GPIO_LCDSEG_RESETVALUE 0x00000000UL /**< Default value for GPIO_LCDSEG */ -#define _GPIO_LCDSEG_MASK 0x0FFFFFFFUL /**< Mask for GPIO_LCDSEG */ -#define _GPIO_LCDSEG_LCDSEGALLOC_SHIFT 0 /**< Shift value for GPIO_LCDSEGALLOC */ -#define _GPIO_LCDSEG_LCDSEGALLOC_MASK 0xFFFFFFFUL /**< Bit mask for GPIO_LCDSEGALLOC */ -#define _GPIO_LCDSEG_LCDSEGALLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LCDSEG */ -#define GPIO_LCDSEG_LCDSEGALLOC_DEFAULT (_GPIO_LCDSEG_LCDSEGALLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LCDSEG */ +#define _GPIO_LCDSEG_RESETVALUE 0x00000000UL /**< Default value for GPIO_LCDSEG */ +#define _GPIO_LCDSEG_MASK 0x0FFFFFFFUL /**< Mask for GPIO_LCDSEG */ +#define _GPIO_LCDSEG_LCDSEGALLOC_SHIFT 0 /**< Shift value for GPIO_LCDSEGALLOC */ +#define _GPIO_LCDSEG_LCDSEGALLOC_MASK 0xFFFFFFFUL /**< Bit mask for GPIO_LCDSEGALLOC */ +#define _GPIO_LCDSEG_LCDSEGALLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LCDSEG */ +#define GPIO_LCDSEG_LCDSEGALLOC_DEFAULT (_GPIO_LCDSEG_LCDSEGALLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LCDSEG */ /* Bit fields for GPIO LCDCOM */ -#define _GPIO_LCDCOM_RESETVALUE 0x00000000UL /**< Default value for GPIO_LCDCOM */ -#define _GPIO_LCDCOM_MASK 0x0000000FUL /**< Mask for GPIO_LCDCOM */ -#define _GPIO_LCDCOM_LCDCOMALLOC_SHIFT 0 /**< Shift value for GPIO_LCDCOMALLOC */ -#define _GPIO_LCDCOM_LCDCOMALLOC_MASK 0xFUL /**< Bit mask for GPIO_LCDCOMALLOC */ -#define _GPIO_LCDCOM_LCDCOMALLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LCDCOM */ -#define GPIO_LCDCOM_LCDCOMALLOC_DEFAULT (_GPIO_LCDCOM_LCDCOMALLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LCDCOM */ +#define _GPIO_LCDCOM_RESETVALUE 0x00000000UL /**< Default value for GPIO_LCDCOM */ +#define _GPIO_LCDCOM_MASK 0x0000000FUL /**< Mask for GPIO_LCDCOM */ +#define _GPIO_LCDCOM_LCDCOMALLOC_SHIFT 0 /**< Shift value for GPIO_LCDCOMALLOC */ +#define _GPIO_LCDCOM_LCDCOMALLOC_MASK 0xFUL /**< Bit mask for GPIO_LCDCOMALLOC */ +#define _GPIO_LCDCOM_LCDCOMALLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LCDCOM */ +#define GPIO_LCDCOM_LCDCOMALLOC_DEFAULT (_GPIO_LCDCOM_LCDCOMALLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LCDCOM */ /* Bit fields for GPIO_ACMP ROUTEEN */ -#define _GPIO_ACMP_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ROUTEEN */ -#define _GPIO_ACMP_ROUTEEN_MASK 0x00000001UL /**< Mask for GPIO_ACMP_ROUTEEN */ -#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN (0x1UL << 0) /**< ACMPOUT pin enable control bit */ -#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_SHIFT 0 /**< Shift value for GPIO_ACMPOUTPEN */ -#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_MASK 0x1UL /**< Bit mask for GPIO_ACMPOUTPEN */ -#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ROUTEEN */ -#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT (_GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ROUTEEN */ +#define _GPIO_ACMP_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ROUTEEN */ +#define _GPIO_ACMP_ROUTEEN_MASK 0x00000001UL /**< Mask for GPIO_ACMP_ROUTEEN */ +#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN (0x1UL << 0) /**< ACMPOUT pin enable control bit */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_SHIFT 0 /**< Shift value for GPIO_ACMPOUTPEN */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_MASK 0x1UL /**< Bit mask for GPIO_ACMPOUTPEN */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ROUTEEN */ +#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT (_GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ROUTEEN */ /* Bit fields for GPIO_ACMP ACMPOUTROUTE */ -#define _GPIO_ACMP_ACMPOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ACMPOUTROUTE */ -#define _GPIO_ACMP_ACMPOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_ACMP_ACMPOUTROUTE */ -#define _GPIO_ACMP_ACMPOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_ACMP_ACMPOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ -#define GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ -#define _GPIO_ACMP_ACMPOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_ACMP_ACMPOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ -#define GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ +#define _GPIO_ACMP_ACMPOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_ACMP_ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ +#define GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ +#define GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ /* Bit fields for GPIO_CMU ROUTEEN */ -#define _GPIO_CMU_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_ROUTEEN */ -#define _GPIO_CMU_ROUTEEN_MASK 0x0000000FUL /**< Mask for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 pin enable control bit */ -#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for GPIO_CLKOUT0PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_CLKOUT0PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 pin enable control bit */ -#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for GPIO_CLKOUT1PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_CLKOUT1PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 pin enable control bit */ -#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for GPIO_CLKOUT2PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_CLKOUT2PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_MASK 0x0000000FUL /**< Mask for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ /* Bit fields for GPIO_CMU CLKIN0ROUTE */ -#define _GPIO_CMU_CLKIN0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKIN0ROUTE */ -#define _GPIO_CMU_CLKIN0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKIN0ROUTE */ -#define _GPIO_CMU_CLKIN0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_CMU_CLKIN0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ -#define GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ -#define _GPIO_CMU_CLKIN0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_CMU_CLKIN0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ -#define GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ +#define _GPIO_CMU_CLKIN0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ /* Bit fields for GPIO_CMU CLKOUT0ROUTE */ -#define _GPIO_CMU_CLKOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT0ROUTE */ -#define _GPIO_CMU_CLKOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT0ROUTE */ -#define _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ -#define GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ -#define _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ -#define GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ +#define _GPIO_CMU_CLKOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ /* Bit fields for GPIO_CMU CLKOUT1ROUTE */ -#define _GPIO_CMU_CLKOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT1ROUTE */ -#define _GPIO_CMU_CLKOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT1ROUTE */ -#define _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ -#define GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ -#define _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ -#define GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ +#define _GPIO_CMU_CLKOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ /* Bit fields for GPIO_CMU CLKOUT2ROUTE */ -#define _GPIO_CMU_CLKOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT2ROUTE */ -#define _GPIO_CMU_CLKOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT2ROUTE */ -#define _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ -#define GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ -#define _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ -#define GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ +#define _GPIO_CMU_CLKOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ /* Bit fields for GPIO_EUSART ROUTEEN */ -#define _GPIO_EUSART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_ROUTEEN */ -#define _GPIO_EUSART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ -#define _GPIO_EUSART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ -#define _GPIO_EUSART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ -#define _GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ -#define GPIO_EUSART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ -#define _GPIO_EUSART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ -#define _GPIO_EUSART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ -#define _GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ -#define GPIO_EUSART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ -#define _GPIO_EUSART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ -#define _GPIO_EUSART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ -#define _GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ -#define GPIO_EUSART_ROUTEEN_SCLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ -#define _GPIO_EUSART_ROUTEEN_SCLKPEN_SHIFT 3 /**< Shift value for GPIO_SCLKPEN */ -#define _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK 0x8UL /**< Bit mask for GPIO_SCLKPEN */ -#define _GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ -#define GPIO_EUSART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ -#define _GPIO_EUSART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ -#define _GPIO_EUSART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ -#define _GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define _GPIO_EUSART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_ROUTEEN */ +#define _GPIO_EUSART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_SCLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_SHIFT 3 /**< Shift value for GPIO_SCLKPEN */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK 0x8UL /**< Bit mask for GPIO_SCLKPEN */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ /* Bit fields for GPIO_EUSART CSROUTE */ -#define _GPIO_EUSART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CSROUTE */ -#define _GPIO_EUSART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CSROUTE */ -#define _GPIO_EUSART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ -#define GPIO_EUSART_CSROUTE_PORT_DEFAULT (_GPIO_EUSART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ -#define _GPIO_EUSART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ -#define GPIO_EUSART_CSROUTE_PIN_DEFAULT (_GPIO_EUSART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ +#define _GPIO_EUSART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CSROUTE */ +#define _GPIO_EUSART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CSROUTE */ +#define _GPIO_EUSART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ +#define GPIO_EUSART_CSROUTE_PORT_DEFAULT (_GPIO_EUSART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ +#define _GPIO_EUSART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ +#define GPIO_EUSART_CSROUTE_PIN_DEFAULT (_GPIO_EUSART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ /* Bit fields for GPIO_EUSART CTSROUTE */ -#define _GPIO_EUSART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CTSROUTE */ -#define _GPIO_EUSART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CTSROUTE */ -#define _GPIO_EUSART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ -#define GPIO_EUSART_CTSROUTE_PORT_DEFAULT (_GPIO_EUSART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ -#define _GPIO_EUSART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ -#define GPIO_EUSART_CTSROUTE_PIN_DEFAULT (_GPIO_EUSART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ +#define _GPIO_EUSART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ +#define GPIO_EUSART_CTSROUTE_PORT_DEFAULT (_GPIO_EUSART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ +#define _GPIO_EUSART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ +#define GPIO_EUSART_CTSROUTE_PIN_DEFAULT (_GPIO_EUSART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ /* Bit fields for GPIO_EUSART RTSROUTE */ -#define _GPIO_EUSART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RTSROUTE */ -#define _GPIO_EUSART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RTSROUTE */ -#define _GPIO_EUSART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ -#define GPIO_EUSART_RTSROUTE_PORT_DEFAULT (_GPIO_EUSART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ -#define _GPIO_EUSART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ -#define GPIO_EUSART_RTSROUTE_PIN_DEFAULT (_GPIO_EUSART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ +#define _GPIO_EUSART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ +#define GPIO_EUSART_RTSROUTE_PORT_DEFAULT (_GPIO_EUSART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ +#define _GPIO_EUSART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ +#define GPIO_EUSART_RTSROUTE_PIN_DEFAULT (_GPIO_EUSART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ /* Bit fields for GPIO_EUSART RXROUTE */ -#define _GPIO_EUSART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RXROUTE */ -#define _GPIO_EUSART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RXROUTE */ -#define _GPIO_EUSART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ -#define GPIO_EUSART_RXROUTE_PORT_DEFAULT (_GPIO_EUSART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ -#define _GPIO_EUSART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ -#define GPIO_EUSART_RXROUTE_PIN_DEFAULT (_GPIO_EUSART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ +#define _GPIO_EUSART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RXROUTE */ +#define _GPIO_EUSART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RXROUTE */ +#define _GPIO_EUSART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ +#define GPIO_EUSART_RXROUTE_PORT_DEFAULT (_GPIO_EUSART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ +#define _GPIO_EUSART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ +#define GPIO_EUSART_RXROUTE_PIN_DEFAULT (_GPIO_EUSART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ /* Bit fields for GPIO_EUSART SCLKROUTE */ -#define _GPIO_EUSART_SCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_SCLKROUTE */ -#define _GPIO_EUSART_SCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_SCLKROUTE */ -#define _GPIO_EUSART_SCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_SCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_SCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ -#define GPIO_EUSART_SCLKROUTE_PORT_DEFAULT (_GPIO_EUSART_SCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ -#define _GPIO_EUSART_SCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_SCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_SCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ -#define GPIO_EUSART_SCLKROUTE_PIN_DEFAULT (_GPIO_EUSART_SCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ +#define _GPIO_EUSART_SCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_SCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_SCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ +#define GPIO_EUSART_SCLKROUTE_PORT_DEFAULT (_GPIO_EUSART_SCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ +#define _GPIO_EUSART_SCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_SCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_SCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ +#define GPIO_EUSART_SCLKROUTE_PIN_DEFAULT (_GPIO_EUSART_SCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ /* Bit fields for GPIO_EUSART TXROUTE */ -#define _GPIO_EUSART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_TXROUTE */ -#define _GPIO_EUSART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_TXROUTE */ -#define _GPIO_EUSART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ -#define GPIO_EUSART_TXROUTE_PORT_DEFAULT (_GPIO_EUSART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ -#define _GPIO_EUSART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ -#define GPIO_EUSART_TXROUTE_PIN_DEFAULT (_GPIO_EUSART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ +#define _GPIO_EUSART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_TXROUTE */ +#define _GPIO_EUSART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_TXROUTE */ +#define _GPIO_EUSART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ +#define GPIO_EUSART_TXROUTE_PORT_DEFAULT (_GPIO_EUSART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ +#define _GPIO_EUSART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ +#define GPIO_EUSART_TXROUTE_PIN_DEFAULT (_GPIO_EUSART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ /* Bit fields for GPIO_FRC ROUTEEN */ -#define _GPIO_FRC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_ROUTEEN */ -#define _GPIO_FRC_ROUTEEN_MASK 0x00000007UL /**< Mask for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DCLKPEN (0x1UL << 0) /**< DCLK pin enable control bit */ -#define _GPIO_FRC_ROUTEEN_DCLKPEN_SHIFT 0 /**< Shift value for GPIO_DCLKPEN */ -#define _GPIO_FRC_ROUTEEN_DCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_DCLKPEN */ -#define _GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DFRAMEPEN (0x1UL << 1) /**< DFRAME pin enable control bit */ -#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_SHIFT 1 /**< Shift value for GPIO_DFRAMEPEN */ -#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_MASK 0x2UL /**< Bit mask for GPIO_DFRAMEPEN */ -#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DOUTPEN (0x1UL << 2) /**< DOUT pin enable control bit */ -#define _GPIO_FRC_ROUTEEN_DOUTPEN_SHIFT 2 /**< Shift value for GPIO_DOUTPEN */ -#define _GPIO_FRC_ROUTEEN_DOUTPEN_MASK 0x4UL /**< Bit mask for GPIO_DOUTPEN */ -#define _GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_MASK 0x00000007UL /**< Mask for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN (0x1UL << 0) /**< DCLK pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_SHIFT 0 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN (0x1UL << 1) /**< DFRAME pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_SHIFT 1 /**< Shift value for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_MASK 0x2UL /**< Bit mask for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN (0x1UL << 2) /**< DOUT pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_SHIFT 2 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_MASK 0x4UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ /* Bit fields for GPIO_FRC DCLKROUTE */ -#define _GPIO_FRC_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DCLKROUTE */ -#define _GPIO_FRC_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DCLKROUTE */ -#define _GPIO_FRC_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_FRC_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_FRC_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ -#define GPIO_FRC_DCLKROUTE_PORT_DEFAULT (_GPIO_FRC_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ -#define _GPIO_FRC_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_FRC_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_FRC_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ -#define GPIO_FRC_DCLKROUTE_PIN_DEFAULT (_GPIO_FRC_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PORT_DEFAULT (_GPIO_FRC_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PIN_DEFAULT (_GPIO_FRC_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ /* Bit fields for GPIO_FRC DFRAMEROUTE */ -#define _GPIO_FRC_DFRAMEROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DFRAMEROUTE */ -#define _GPIO_FRC_DFRAMEROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DFRAMEROUTE */ -#define _GPIO_FRC_DFRAMEROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_FRC_DFRAMEROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ -#define GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ -#define _GPIO_FRC_DFRAMEROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_FRC_DFRAMEROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ -#define GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ +#define _GPIO_FRC_DFRAMEROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ +#define _GPIO_FRC_DFRAMEROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ /* Bit fields for GPIO_FRC DOUTROUTE */ -#define _GPIO_FRC_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DOUTROUTE */ -#define _GPIO_FRC_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DOUTROUTE */ -#define _GPIO_FRC_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_FRC_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_FRC_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ -#define GPIO_FRC_DOUTROUTE_PORT_DEFAULT (_GPIO_FRC_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ -#define _GPIO_FRC_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_FRC_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_FRC_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ -#define GPIO_FRC_DOUTROUTE_PIN_DEFAULT (_GPIO_FRC_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PORT_DEFAULT (_GPIO_FRC_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PIN_DEFAULT (_GPIO_FRC_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ /* Bit fields for GPIO_I2C ROUTEEN */ -#define _GPIO_I2C_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_ROUTEEN */ -#define _GPIO_I2C_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_I2C_ROUTEEN */ -#define GPIO_I2C_ROUTEEN_SCLPEN (0x1UL << 0) /**< SCL pin enable control bit */ -#define _GPIO_I2C_ROUTEEN_SCLPEN_SHIFT 0 /**< Shift value for GPIO_SCLPEN */ -#define _GPIO_I2C_ROUTEEN_SCLPEN_MASK 0x1UL /**< Bit mask for GPIO_SCLPEN */ -#define _GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ -#define GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ -#define GPIO_I2C_ROUTEEN_SDAPEN (0x1UL << 1) /**< SDA pin enable control bit */ -#define _GPIO_I2C_ROUTEEN_SDAPEN_SHIFT 1 /**< Shift value for GPIO_SDAPEN */ -#define _GPIO_I2C_ROUTEEN_SDAPEN_MASK 0x2UL /**< Bit mask for GPIO_SDAPEN */ -#define _GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ -#define GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN (0x1UL << 0) /**< SCL pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_SHIFT 0 /**< Shift value for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_MASK 0x1UL /**< Bit mask for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN (0x1UL << 1) /**< SDA pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_SHIFT 1 /**< Shift value for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_MASK 0x2UL /**< Bit mask for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ /* Bit fields for GPIO_I2C SCLROUTE */ -#define _GPIO_I2C_SCLROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SCLROUTE */ -#define _GPIO_I2C_SCLROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SCLROUTE */ -#define _GPIO_I2C_SCLROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_I2C_SCLROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_I2C_SCLROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ -#define GPIO_I2C_SCLROUTE_PORT_DEFAULT (_GPIO_I2C_SCLROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ -#define _GPIO_I2C_SCLROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_I2C_SCLROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_I2C_SCLROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ -#define GPIO_I2C_SCLROUTE_PIN_DEFAULT (_GPIO_I2C_SCLROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PORT_DEFAULT (_GPIO_I2C_SCLROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PIN_DEFAULT (_GPIO_I2C_SCLROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ /* Bit fields for GPIO_I2C SDAROUTE */ -#define _GPIO_I2C_SDAROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SDAROUTE */ -#define _GPIO_I2C_SDAROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SDAROUTE */ -#define _GPIO_I2C_SDAROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_I2C_SDAROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_I2C_SDAROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ -#define GPIO_I2C_SDAROUTE_PORT_DEFAULT (_GPIO_I2C_SDAROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ -#define _GPIO_I2C_SDAROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_I2C_SDAROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_I2C_SDAROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ -#define GPIO_I2C_SDAROUTE_PIN_DEFAULT (_GPIO_I2C_SDAROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PORT_DEFAULT (_GPIO_I2C_SDAROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PIN_DEFAULT (_GPIO_I2C_SDAROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ /* Bit fields for GPIO_KEYSCAN ROUTEEN */ -#define _GPIO_KEYSCAN_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROUTEEN */ -#define _GPIO_KEYSCAN_ROUTEEN_MASK 0x000000FFUL /**< Mask for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN (0x1UL << 0) /**< COLOUT0 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_SHIFT 0 /**< Shift value for GPIO_COLOUT0PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_COLOUT0PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN (0x1UL << 1) /**< COLOUT1 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_SHIFT 1 /**< Shift value for GPIO_COLOUT1PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_COLOUT1PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN (0x1UL << 2) /**< COLOUT2 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_SHIFT 2 /**< Shift value for GPIO_COLOUT2PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_COLOUT2PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN (0x1UL << 3) /**< COLOUT3 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_SHIFT 3 /**< Shift value for GPIO_COLOUT3PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_MASK 0x8UL /**< Bit mask for GPIO_COLOUT3PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN (0x1UL << 4) /**< COLOUT4 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_SHIFT 4 /**< Shift value for GPIO_COLOUT4PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_MASK 0x10UL /**< Bit mask for GPIO_COLOUT4PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN (0x1UL << 5) /**< COLOUT5 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_SHIFT 5 /**< Shift value for GPIO_COLOUT5PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_MASK 0x20UL /**< Bit mask for GPIO_COLOUT5PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN (0x1UL << 6) /**< COLOUT6 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_SHIFT 6 /**< Shift value for GPIO_COLOUT6PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_MASK 0x40UL /**< Bit mask for GPIO_COLOUT6PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN (0x1UL << 7) /**< COLOUT7 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_SHIFT 7 /**< Shift value for GPIO_COLOUT7PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_MASK 0x80UL /**< Bit mask for GPIO_COLOUT7PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define _GPIO_KEYSCAN_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROUTEEN */ +#define _GPIO_KEYSCAN_ROUTEEN_MASK 0x000000FFUL /**< Mask for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN (0x1UL << 0) /**< COLOUT0 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_SHIFT 0 /**< Shift value for GPIO_COLOUT0PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_COLOUT0PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN (0x1UL << 1) /**< COLOUT1 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_SHIFT 1 /**< Shift value for GPIO_COLOUT1PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_COLOUT1PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN (0x1UL << 2) /**< COLOUT2 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_SHIFT 2 /**< Shift value for GPIO_COLOUT2PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_COLOUT2PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN (0x1UL << 3) /**< COLOUT3 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_SHIFT 3 /**< Shift value for GPIO_COLOUT3PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_MASK 0x8UL /**< Bit mask for GPIO_COLOUT3PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN (0x1UL << 4) /**< COLOUT4 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_SHIFT 4 /**< Shift value for GPIO_COLOUT4PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_MASK 0x10UL /**< Bit mask for GPIO_COLOUT4PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN (0x1UL << 5) /**< COLOUT5 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_SHIFT 5 /**< Shift value for GPIO_COLOUT5PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_MASK 0x20UL /**< Bit mask for GPIO_COLOUT5PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN (0x1UL << 6) /**< COLOUT6 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_SHIFT 6 /**< Shift value for GPIO_COLOUT6PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_MASK 0x40UL /**< Bit mask for GPIO_COLOUT6PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN (0x1UL << 7) /**< COLOUT7 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_SHIFT 7 /**< Shift value for GPIO_COLOUT7PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_MASK 0x80UL /**< Bit mask for GPIO_COLOUT7PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ /* Bit fields for GPIO_KEYSCAN COLOUT0ROUTE */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT0ROUTE */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT0ROUTE */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ -#define GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ -#define GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ /* Bit fields for GPIO_KEYSCAN COLOUT1ROUTE */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT1ROUTE */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT1ROUTE */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ -#define GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ -#define GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ /* Bit fields for GPIO_KEYSCAN COLOUT2ROUTE */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT2ROUTE */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT2ROUTE */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ -#define GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ -#define GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ /* Bit fields for GPIO_KEYSCAN COLOUT3ROUTE */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT3ROUTE */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT3ROUTE */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ -#define GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ -#define GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ /* Bit fields for GPIO_KEYSCAN COLOUT4ROUTE */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT4ROUTE */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT4ROUTE */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ -#define GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ -#define GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ /* Bit fields for GPIO_KEYSCAN COLOUT5ROUTE */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT5ROUTE */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT5ROUTE */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ -#define GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ -#define GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ /* Bit fields for GPIO_KEYSCAN COLOUT6ROUTE */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT6ROUTE */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT6ROUTE */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ -#define GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ -#define GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ /* Bit fields for GPIO_KEYSCAN COLOUT7ROUTE */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT7ROUTE */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT7ROUTE */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ -#define GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ -#define GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ /* Bit fields for GPIO_KEYSCAN ROWSENSE0ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE0ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE0ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ /* Bit fields for GPIO_KEYSCAN ROWSENSE1ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE1ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE1ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ /* Bit fields for GPIO_KEYSCAN ROWSENSE2ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE2ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE2ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ /* Bit fields for GPIO_KEYSCAN ROWSENSE3ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE3ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE3ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ /* Bit fields for GPIO_KEYSCAN ROWSENSE4ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE4ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE4ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ /* Bit fields for GPIO_KEYSCAN ROWSENSE5ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE5ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE5ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ /* Bit fields for GPIO_LESENSE ROUTEEN */ -#define _GPIO_LESENSE_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_ROUTEEN */ -#define _GPIO_LESENSE_ROUTEEN_MASK 0x0000FFFFUL /**< Mask for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH0OUTPEN (0x1UL << 0) /**< CH0OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH0OUTPEN_SHIFT 0 /**< Shift value for GPIO_CH0OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH0OUTPEN_MASK 0x1UL /**< Bit mask for GPIO_CH0OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH0OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH0OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH0OUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH1OUTPEN (0x1UL << 1) /**< CH1OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH1OUTPEN_SHIFT 1 /**< Shift value for GPIO_CH1OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH1OUTPEN_MASK 0x2UL /**< Bit mask for GPIO_CH1OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH1OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH1OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH1OUTPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH2OUTPEN (0x1UL << 2) /**< CH2OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH2OUTPEN_SHIFT 2 /**< Shift value for GPIO_CH2OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH2OUTPEN_MASK 0x4UL /**< Bit mask for GPIO_CH2OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH2OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH2OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH2OUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH3OUTPEN (0x1UL << 3) /**< CH3OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH3OUTPEN_SHIFT 3 /**< Shift value for GPIO_CH3OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH3OUTPEN_MASK 0x8UL /**< Bit mask for GPIO_CH3OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH3OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH3OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH3OUTPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH4OUTPEN (0x1UL << 4) /**< CH4OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH4OUTPEN_SHIFT 4 /**< Shift value for GPIO_CH4OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH4OUTPEN_MASK 0x10UL /**< Bit mask for GPIO_CH4OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH4OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH4OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH4OUTPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH5OUTPEN (0x1UL << 5) /**< CH5OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH5OUTPEN_SHIFT 5 /**< Shift value for GPIO_CH5OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH5OUTPEN_MASK 0x20UL /**< Bit mask for GPIO_CH5OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH5OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH5OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH5OUTPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH6OUTPEN (0x1UL << 6) /**< CH6OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH6OUTPEN_SHIFT 6 /**< Shift value for GPIO_CH6OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH6OUTPEN_MASK 0x40UL /**< Bit mask for GPIO_CH6OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH6OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH6OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH6OUTPEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH7OUTPEN (0x1UL << 7) /**< CH7OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH7OUTPEN_SHIFT 7 /**< Shift value for GPIO_CH7OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH7OUTPEN_MASK 0x80UL /**< Bit mask for GPIO_CH7OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH7OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH7OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH7OUTPEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH8OUTPEN (0x1UL << 8) /**< CH8OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH8OUTPEN_SHIFT 8 /**< Shift value for GPIO_CH8OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH8OUTPEN_MASK 0x100UL /**< Bit mask for GPIO_CH8OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH8OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH8OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH8OUTPEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH9OUTPEN (0x1UL << 9) /**< CH9OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH9OUTPEN_SHIFT 9 /**< Shift value for GPIO_CH9OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH9OUTPEN_MASK 0x200UL /**< Bit mask for GPIO_CH9OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH9OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH9OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH9OUTPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH10OUTPEN (0x1UL << 10) /**< CH10OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH10OUTPEN_SHIFT 10 /**< Shift value for GPIO_CH10OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH10OUTPEN_MASK 0x400UL /**< Bit mask for GPIO_CH10OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH10OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH10OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH10OUTPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH11OUTPEN (0x1UL << 11) /**< CH11OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH11OUTPEN_SHIFT 11 /**< Shift value for GPIO_CH11OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH11OUTPEN_MASK 0x800UL /**< Bit mask for GPIO_CH11OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH11OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH11OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH11OUTPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH12OUTPEN (0x1UL << 12) /**< CH12OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH12OUTPEN_SHIFT 12 /**< Shift value for GPIO_CH12OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH12OUTPEN_MASK 0x1000UL /**< Bit mask for GPIO_CH12OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH12OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH12OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH12OUTPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH13OUTPEN (0x1UL << 13) /**< CH13OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH13OUTPEN_SHIFT 13 /**< Shift value for GPIO_CH13OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH13OUTPEN_MASK 0x2000UL /**< Bit mask for GPIO_CH13OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH13OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH13OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH13OUTPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH14OUTPEN (0x1UL << 14) /**< CH14OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH14OUTPEN_SHIFT 14 /**< Shift value for GPIO_CH14OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH14OUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_CH14OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH14OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH14OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH14OUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ -#define GPIO_LESENSE_ROUTEEN_CH15OUTPEN (0x1UL << 15) /**< CH15OUT pin enable control bit */ -#define _GPIO_LESENSE_ROUTEEN_CH15OUTPEN_SHIFT 15 /**< Shift value for GPIO_CH15OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH15OUTPEN_MASK 0x8000UL /**< Bit mask for GPIO_CH15OUTPEN */ -#define _GPIO_LESENSE_ROUTEEN_CH15OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ -#define GPIO_LESENSE_ROUTEEN_CH15OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH15OUTPEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define _GPIO_LESENSE_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_ROUTEEN */ +#define _GPIO_LESENSE_ROUTEEN_MASK 0x0000FFFFUL /**< Mask for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH0OUTPEN (0x1UL << 0) /**< CH0OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH0OUTPEN_SHIFT 0 /**< Shift value for GPIO_CH0OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH0OUTPEN_MASK 0x1UL /**< Bit mask for GPIO_CH0OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH0OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH0OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH0OUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH1OUTPEN (0x1UL << 1) /**< CH1OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH1OUTPEN_SHIFT 1 /**< Shift value for GPIO_CH1OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH1OUTPEN_MASK 0x2UL /**< Bit mask for GPIO_CH1OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH1OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH1OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH1OUTPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH2OUTPEN (0x1UL << 2) /**< CH2OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH2OUTPEN_SHIFT 2 /**< Shift value for GPIO_CH2OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH2OUTPEN_MASK 0x4UL /**< Bit mask for GPIO_CH2OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH2OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH2OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH2OUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH3OUTPEN (0x1UL << 3) /**< CH3OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH3OUTPEN_SHIFT 3 /**< Shift value for GPIO_CH3OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH3OUTPEN_MASK 0x8UL /**< Bit mask for GPIO_CH3OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH3OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH3OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH3OUTPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH4OUTPEN (0x1UL << 4) /**< CH4OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH4OUTPEN_SHIFT 4 /**< Shift value for GPIO_CH4OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH4OUTPEN_MASK 0x10UL /**< Bit mask for GPIO_CH4OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH4OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH4OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH4OUTPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH5OUTPEN (0x1UL << 5) /**< CH5OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH5OUTPEN_SHIFT 5 /**< Shift value for GPIO_CH5OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH5OUTPEN_MASK 0x20UL /**< Bit mask for GPIO_CH5OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH5OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH5OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH5OUTPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH6OUTPEN (0x1UL << 6) /**< CH6OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH6OUTPEN_SHIFT 6 /**< Shift value for GPIO_CH6OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH6OUTPEN_MASK 0x40UL /**< Bit mask for GPIO_CH6OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH6OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH6OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH6OUTPEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH7OUTPEN (0x1UL << 7) /**< CH7OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH7OUTPEN_SHIFT 7 /**< Shift value for GPIO_CH7OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH7OUTPEN_MASK 0x80UL /**< Bit mask for GPIO_CH7OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH7OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH7OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH7OUTPEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH8OUTPEN (0x1UL << 8) /**< CH8OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH8OUTPEN_SHIFT 8 /**< Shift value for GPIO_CH8OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH8OUTPEN_MASK 0x100UL /**< Bit mask for GPIO_CH8OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH8OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH8OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH8OUTPEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH9OUTPEN (0x1UL << 9) /**< CH9OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH9OUTPEN_SHIFT 9 /**< Shift value for GPIO_CH9OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH9OUTPEN_MASK 0x200UL /**< Bit mask for GPIO_CH9OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH9OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH9OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH9OUTPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH10OUTPEN (0x1UL << 10) /**< CH10OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH10OUTPEN_SHIFT 10 /**< Shift value for GPIO_CH10OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH10OUTPEN_MASK 0x400UL /**< Bit mask for GPIO_CH10OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH10OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH10OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH10OUTPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH11OUTPEN (0x1UL << 11) /**< CH11OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH11OUTPEN_SHIFT 11 /**< Shift value for GPIO_CH11OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH11OUTPEN_MASK 0x800UL /**< Bit mask for GPIO_CH11OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH11OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH11OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH11OUTPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH12OUTPEN (0x1UL << 12) /**< CH12OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH12OUTPEN_SHIFT 12 /**< Shift value for GPIO_CH12OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH12OUTPEN_MASK 0x1000UL /**< Bit mask for GPIO_CH12OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH12OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH12OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH12OUTPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH13OUTPEN (0x1UL << 13) /**< CH13OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH13OUTPEN_SHIFT 13 /**< Shift value for GPIO_CH13OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH13OUTPEN_MASK 0x2000UL /**< Bit mask for GPIO_CH13OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH13OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH13OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH13OUTPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH14OUTPEN (0x1UL << 14) /**< CH14OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH14OUTPEN_SHIFT 14 /**< Shift value for GPIO_CH14OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH14OUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_CH14OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH14OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH14OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH14OUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH15OUTPEN (0x1UL << 15) /**< CH15OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH15OUTPEN_SHIFT 15 /**< Shift value for GPIO_CH15OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH15OUTPEN_MASK 0x8000UL /**< Bit mask for GPIO_CH15OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH15OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH15OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH15OUTPEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ /* Bit fields for GPIO_LESENSE CH0OUTROUTE */ -#define _GPIO_LESENSE_CH0OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH0OUTROUTE */ -#define _GPIO_LESENSE_CH0OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH0OUTROUTE */ -#define _GPIO_LESENSE_CH0OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH0OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH0OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE */ -#define GPIO_LESENSE_CH0OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH0OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE*/ -#define _GPIO_LESENSE_CH0OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH0OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH0OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE */ -#define GPIO_LESENSE_CH0OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH0OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE*/ +#define _GPIO_LESENSE_CH0OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH0OUTROUTE */ +#define _GPIO_LESENSE_CH0OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH0OUTROUTE */ +#define _GPIO_LESENSE_CH0OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH0OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH0OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE */ +#define GPIO_LESENSE_CH0OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH0OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE*/ +#define _GPIO_LESENSE_CH0OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH0OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH0OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE */ +#define GPIO_LESENSE_CH0OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH0OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH1OUTROUTE */ -#define _GPIO_LESENSE_CH1OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH1OUTROUTE */ -#define _GPIO_LESENSE_CH1OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH1OUTROUTE */ -#define _GPIO_LESENSE_CH1OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH1OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH1OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE */ -#define GPIO_LESENSE_CH1OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH1OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE*/ -#define _GPIO_LESENSE_CH1OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH1OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH1OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE */ -#define GPIO_LESENSE_CH1OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH1OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE*/ +#define _GPIO_LESENSE_CH1OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH1OUTROUTE */ +#define _GPIO_LESENSE_CH1OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH1OUTROUTE */ +#define _GPIO_LESENSE_CH1OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH1OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH1OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE */ +#define GPIO_LESENSE_CH1OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH1OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE*/ +#define _GPIO_LESENSE_CH1OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH1OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH1OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE */ +#define GPIO_LESENSE_CH1OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH1OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH2OUTROUTE */ -#define _GPIO_LESENSE_CH2OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH2OUTROUTE */ -#define _GPIO_LESENSE_CH2OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH2OUTROUTE */ -#define _GPIO_LESENSE_CH2OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH2OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH2OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE */ -#define GPIO_LESENSE_CH2OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH2OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE*/ -#define _GPIO_LESENSE_CH2OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH2OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH2OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE */ -#define GPIO_LESENSE_CH2OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH2OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE*/ +#define _GPIO_LESENSE_CH2OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH2OUTROUTE */ +#define _GPIO_LESENSE_CH2OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH2OUTROUTE */ +#define _GPIO_LESENSE_CH2OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH2OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH2OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE */ +#define GPIO_LESENSE_CH2OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH2OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE*/ +#define _GPIO_LESENSE_CH2OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH2OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH2OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE */ +#define GPIO_LESENSE_CH2OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH2OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH3OUTROUTE */ -#define _GPIO_LESENSE_CH3OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH3OUTROUTE */ -#define _GPIO_LESENSE_CH3OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH3OUTROUTE */ -#define _GPIO_LESENSE_CH3OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH3OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH3OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE */ -#define GPIO_LESENSE_CH3OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH3OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE*/ -#define _GPIO_LESENSE_CH3OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH3OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH3OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE */ -#define GPIO_LESENSE_CH3OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH3OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE*/ +#define _GPIO_LESENSE_CH3OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH3OUTROUTE */ +#define _GPIO_LESENSE_CH3OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH3OUTROUTE */ +#define _GPIO_LESENSE_CH3OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH3OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH3OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE */ +#define GPIO_LESENSE_CH3OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH3OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE*/ +#define _GPIO_LESENSE_CH3OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH3OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH3OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE */ +#define GPIO_LESENSE_CH3OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH3OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH4OUTROUTE */ -#define _GPIO_LESENSE_CH4OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH4OUTROUTE */ -#define _GPIO_LESENSE_CH4OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH4OUTROUTE */ -#define _GPIO_LESENSE_CH4OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH4OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH4OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE */ -#define GPIO_LESENSE_CH4OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH4OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE*/ -#define _GPIO_LESENSE_CH4OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH4OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH4OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE */ -#define GPIO_LESENSE_CH4OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH4OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE*/ +#define _GPIO_LESENSE_CH4OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH4OUTROUTE */ +#define _GPIO_LESENSE_CH4OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH4OUTROUTE */ +#define _GPIO_LESENSE_CH4OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH4OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH4OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE */ +#define GPIO_LESENSE_CH4OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH4OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE*/ +#define _GPIO_LESENSE_CH4OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH4OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH4OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE */ +#define GPIO_LESENSE_CH4OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH4OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH5OUTROUTE */ -#define _GPIO_LESENSE_CH5OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH5OUTROUTE */ -#define _GPIO_LESENSE_CH5OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH5OUTROUTE */ -#define _GPIO_LESENSE_CH5OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH5OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH5OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE */ -#define GPIO_LESENSE_CH5OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH5OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE*/ -#define _GPIO_LESENSE_CH5OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH5OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH5OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE */ -#define GPIO_LESENSE_CH5OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH5OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE*/ +#define _GPIO_LESENSE_CH5OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH5OUTROUTE */ +#define _GPIO_LESENSE_CH5OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH5OUTROUTE */ +#define _GPIO_LESENSE_CH5OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH5OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH5OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE */ +#define GPIO_LESENSE_CH5OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH5OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE*/ +#define _GPIO_LESENSE_CH5OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH5OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH5OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE */ +#define GPIO_LESENSE_CH5OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH5OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH6OUTROUTE */ -#define _GPIO_LESENSE_CH6OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH6OUTROUTE */ -#define _GPIO_LESENSE_CH6OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH6OUTROUTE */ -#define _GPIO_LESENSE_CH6OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH6OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH6OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE */ -#define GPIO_LESENSE_CH6OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH6OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE*/ -#define _GPIO_LESENSE_CH6OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH6OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH6OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE */ -#define GPIO_LESENSE_CH6OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH6OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE*/ +#define _GPIO_LESENSE_CH6OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH6OUTROUTE */ +#define _GPIO_LESENSE_CH6OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH6OUTROUTE */ +#define _GPIO_LESENSE_CH6OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH6OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH6OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE */ +#define GPIO_LESENSE_CH6OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH6OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE*/ +#define _GPIO_LESENSE_CH6OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH6OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH6OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE */ +#define GPIO_LESENSE_CH6OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH6OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH7OUTROUTE */ -#define _GPIO_LESENSE_CH7OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH7OUTROUTE */ -#define _GPIO_LESENSE_CH7OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH7OUTROUTE */ -#define _GPIO_LESENSE_CH7OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH7OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH7OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE */ -#define GPIO_LESENSE_CH7OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH7OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE*/ -#define _GPIO_LESENSE_CH7OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH7OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH7OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE */ -#define GPIO_LESENSE_CH7OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH7OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE*/ +#define _GPIO_LESENSE_CH7OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH7OUTROUTE */ +#define _GPIO_LESENSE_CH7OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH7OUTROUTE */ +#define _GPIO_LESENSE_CH7OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH7OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH7OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE */ +#define GPIO_LESENSE_CH7OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH7OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE*/ +#define _GPIO_LESENSE_CH7OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH7OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH7OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE */ +#define GPIO_LESENSE_CH7OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH7OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH8OUTROUTE */ -#define _GPIO_LESENSE_CH8OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH8OUTROUTE */ -#define _GPIO_LESENSE_CH8OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH8OUTROUTE */ -#define _GPIO_LESENSE_CH8OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH8OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH8OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE */ -#define GPIO_LESENSE_CH8OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH8OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE*/ -#define _GPIO_LESENSE_CH8OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH8OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH8OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE */ -#define GPIO_LESENSE_CH8OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH8OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE*/ +#define _GPIO_LESENSE_CH8OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH8OUTROUTE */ +#define _GPIO_LESENSE_CH8OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH8OUTROUTE */ +#define _GPIO_LESENSE_CH8OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH8OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH8OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE */ +#define GPIO_LESENSE_CH8OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH8OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE*/ +#define _GPIO_LESENSE_CH8OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH8OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH8OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE */ +#define GPIO_LESENSE_CH8OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH8OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH9OUTROUTE */ -#define _GPIO_LESENSE_CH9OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH9OUTROUTE */ -#define _GPIO_LESENSE_CH9OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH9OUTROUTE */ -#define _GPIO_LESENSE_CH9OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH9OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH9OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE */ -#define GPIO_LESENSE_CH9OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH9OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE*/ -#define _GPIO_LESENSE_CH9OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH9OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH9OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE */ -#define GPIO_LESENSE_CH9OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH9OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE*/ +#define _GPIO_LESENSE_CH9OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH9OUTROUTE */ +#define _GPIO_LESENSE_CH9OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH9OUTROUTE */ +#define _GPIO_LESENSE_CH9OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH9OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH9OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE */ +#define GPIO_LESENSE_CH9OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH9OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE*/ +#define _GPIO_LESENSE_CH9OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH9OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH9OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE */ +#define GPIO_LESENSE_CH9OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH9OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH10OUTROUTE */ -#define _GPIO_LESENSE_CH10OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH10OUTROUTE */ -#define _GPIO_LESENSE_CH10OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH10OUTROUTE */ -#define _GPIO_LESENSE_CH10OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH10OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH10OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE */ -#define GPIO_LESENSE_CH10OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH10OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE*/ -#define _GPIO_LESENSE_CH10OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH10OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH10OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE */ -#define GPIO_LESENSE_CH10OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH10OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE*/ +#define _GPIO_LESENSE_CH10OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH10OUTROUTE */ +#define _GPIO_LESENSE_CH10OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH10OUTROUTE */ +#define _GPIO_LESENSE_CH10OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH10OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH10OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE */ +#define GPIO_LESENSE_CH10OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH10OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE*/ +#define _GPIO_LESENSE_CH10OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH10OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH10OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE */ +#define GPIO_LESENSE_CH10OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH10OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH11OUTROUTE */ -#define _GPIO_LESENSE_CH11OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH11OUTROUTE */ -#define _GPIO_LESENSE_CH11OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH11OUTROUTE */ -#define _GPIO_LESENSE_CH11OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH11OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH11OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE */ -#define GPIO_LESENSE_CH11OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH11OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE*/ -#define _GPIO_LESENSE_CH11OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH11OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH11OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE */ -#define GPIO_LESENSE_CH11OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH11OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE*/ +#define _GPIO_LESENSE_CH11OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH11OUTROUTE */ +#define _GPIO_LESENSE_CH11OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH11OUTROUTE */ +#define _GPIO_LESENSE_CH11OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH11OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH11OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE */ +#define GPIO_LESENSE_CH11OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH11OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE*/ +#define _GPIO_LESENSE_CH11OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH11OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH11OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE */ +#define GPIO_LESENSE_CH11OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH11OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH12OUTROUTE */ -#define _GPIO_LESENSE_CH12OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH12OUTROUTE */ -#define _GPIO_LESENSE_CH12OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH12OUTROUTE */ -#define _GPIO_LESENSE_CH12OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH12OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH12OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE */ -#define GPIO_LESENSE_CH12OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH12OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE*/ -#define _GPIO_LESENSE_CH12OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH12OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH12OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE */ -#define GPIO_LESENSE_CH12OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH12OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE*/ +#define _GPIO_LESENSE_CH12OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH12OUTROUTE */ +#define _GPIO_LESENSE_CH12OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH12OUTROUTE */ +#define _GPIO_LESENSE_CH12OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH12OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH12OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE */ +#define GPIO_LESENSE_CH12OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH12OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE*/ +#define _GPIO_LESENSE_CH12OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH12OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH12OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE */ +#define GPIO_LESENSE_CH12OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH12OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH13OUTROUTE */ -#define _GPIO_LESENSE_CH13OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH13OUTROUTE */ -#define _GPIO_LESENSE_CH13OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH13OUTROUTE */ -#define _GPIO_LESENSE_CH13OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH13OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH13OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE */ -#define GPIO_LESENSE_CH13OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH13OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE*/ -#define _GPIO_LESENSE_CH13OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH13OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH13OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE */ -#define GPIO_LESENSE_CH13OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH13OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE*/ +#define _GPIO_LESENSE_CH13OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH13OUTROUTE */ +#define _GPIO_LESENSE_CH13OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH13OUTROUTE */ +#define _GPIO_LESENSE_CH13OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH13OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH13OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE */ +#define GPIO_LESENSE_CH13OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH13OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE*/ +#define _GPIO_LESENSE_CH13OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH13OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH13OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE */ +#define GPIO_LESENSE_CH13OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH13OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH14OUTROUTE */ -#define _GPIO_LESENSE_CH14OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH14OUTROUTE */ -#define _GPIO_LESENSE_CH14OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH14OUTROUTE */ -#define _GPIO_LESENSE_CH14OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH14OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH14OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE */ -#define GPIO_LESENSE_CH14OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH14OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE*/ -#define _GPIO_LESENSE_CH14OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH14OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH14OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE */ -#define GPIO_LESENSE_CH14OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH14OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE*/ +#define _GPIO_LESENSE_CH14OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH14OUTROUTE */ +#define _GPIO_LESENSE_CH14OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH14OUTROUTE */ +#define _GPIO_LESENSE_CH14OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH14OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH14OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE */ +#define GPIO_LESENSE_CH14OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH14OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE*/ +#define _GPIO_LESENSE_CH14OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH14OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH14OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE */ +#define GPIO_LESENSE_CH14OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH14OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE*/ /* Bit fields for GPIO_LESENSE CH15OUTROUTE */ -#define _GPIO_LESENSE_CH15OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH15OUTROUTE */ -#define _GPIO_LESENSE_CH15OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH15OUTROUTE */ -#define _GPIO_LESENSE_CH15OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LESENSE_CH15OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LESENSE_CH15OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE */ -#define GPIO_LESENSE_CH15OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH15OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE*/ -#define _GPIO_LESENSE_CH15OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LESENSE_CH15OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LESENSE_CH15OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE */ -#define GPIO_LESENSE_CH15OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH15OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE*/ +#define _GPIO_LESENSE_CH15OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH15OUTROUTE */ +#define _GPIO_LESENSE_CH15OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH15OUTROUTE */ +#define _GPIO_LESENSE_CH15OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH15OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH15OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE */ +#define GPIO_LESENSE_CH15OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH15OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE*/ +#define _GPIO_LESENSE_CH15OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH15OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH15OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE */ +#define GPIO_LESENSE_CH15OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH15OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE*/ /* Bit fields for GPIO_LETIMER ROUTEEN */ -#define _GPIO_LETIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_ROUTEEN */ -#define _GPIO_LETIMER_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_LETIMER_ROUTEEN */ -#define GPIO_LETIMER_ROUTEEN_OUT0PEN (0x1UL << 0) /**< OUT0 pin enable control bit */ -#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_SHIFT 0 /**< Shift value for GPIO_OUT0PEN */ -#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_OUT0PEN */ -#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ -#define GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ -#define GPIO_LETIMER_ROUTEEN_OUT1PEN (0x1UL << 1) /**< OUT1 pin enable control bit */ -#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_SHIFT 1 /**< Shift value for GPIO_OUT1PEN */ -#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_OUT1PEN */ -#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ -#define GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ +#define _GPIO_LETIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_ROUTEEN */ +#define _GPIO_LETIMER_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN (0x1UL << 0) /**< OUT0 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_SHIFT 0 /**< Shift value for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN (0x1UL << 1) /**< OUT1 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_SHIFT 1 /**< Shift value for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ /* Bit fields for GPIO_LETIMER OUT0ROUTE */ -#define _GPIO_LETIMER_OUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT0ROUTE */ -#define _GPIO_LETIMER_OUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT0ROUTE */ -#define _GPIO_LETIMER_OUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LETIMER_OUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ -#define GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ -#define _GPIO_LETIMER_OUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LETIMER_OUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ -#define GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ +#define _GPIO_LETIMER_OUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ /* Bit fields for GPIO_LETIMER OUT1ROUTE */ -#define _GPIO_LETIMER_OUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT1ROUTE */ -#define _GPIO_LETIMER_OUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT1ROUTE */ -#define _GPIO_LETIMER_OUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LETIMER_OUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ -#define GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ -#define _GPIO_LETIMER_OUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LETIMER_OUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ -#define GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ +#define _GPIO_LETIMER_OUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ /* Bit fields for GPIO_MODEM ROUTEEN */ -#define _GPIO_MODEM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ROUTEEN */ -#define _GPIO_MODEM_ROUTEEN_MASK 0x00007FFFUL /**< Mask for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANT0PEN (0x1UL << 0) /**< ANT0 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANT0PEN_SHIFT 0 /**< Shift value for GPIO_ANT0PEN */ -#define _GPIO_MODEM_ROUTEEN_ANT0PEN_MASK 0x1UL /**< Bit mask for GPIO_ANT0PEN */ -#define _GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANT1PEN (0x1UL << 1) /**< ANT1 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANT1PEN_SHIFT 1 /**< Shift value for GPIO_ANT1PEN */ -#define _GPIO_MODEM_ROUTEEN_ANT1PEN_MASK 0x2UL /**< Bit mask for GPIO_ANT1PEN */ -#define _GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN (0x1UL << 2) /**< ANTROLLOVER pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_SHIFT 2 /**< Shift value for GPIO_ANTROLLOVERPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_MASK 0x4UL /**< Bit mask for GPIO_ANTROLLOVERPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR0PEN (0x1UL << 3) /**< ANTRR0 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_SHIFT 3 /**< Shift value for GPIO_ANTRR0PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_MASK 0x8UL /**< Bit mask for GPIO_ANTRR0PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR1PEN (0x1UL << 4) /**< ANTRR1 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_SHIFT 4 /**< Shift value for GPIO_ANTRR1PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_MASK 0x10UL /**< Bit mask for GPIO_ANTRR1PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR2PEN (0x1UL << 5) /**< ANTRR2 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_SHIFT 5 /**< Shift value for GPIO_ANTRR2PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_MASK 0x20UL /**< Bit mask for GPIO_ANTRR2PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR3PEN (0x1UL << 6) /**< ANTRR3 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_SHIFT 6 /**< Shift value for GPIO_ANTRR3PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_MASK 0x40UL /**< Bit mask for GPIO_ANTRR3PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR4PEN (0x1UL << 7) /**< ANTRR4 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_SHIFT 7 /**< Shift value for GPIO_ANTRR4PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_MASK 0x80UL /**< Bit mask for GPIO_ANTRR4PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR5PEN (0x1UL << 8) /**< ANTRR5 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_SHIFT 8 /**< Shift value for GPIO_ANTRR5PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_MASK 0x100UL /**< Bit mask for GPIO_ANTRR5PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTSWENPEN (0x1UL << 9) /**< ANTSWEN pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_SHIFT 9 /**< Shift value for GPIO_ANTSWENPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_MASK 0x200UL /**< Bit mask for GPIO_ANTSWENPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN (0x1UL << 10) /**< ANTSWUS pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_SHIFT 10 /**< Shift value for GPIO_ANTSWUSPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_MASK 0x400UL /**< Bit mask for GPIO_ANTSWUSPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN (0x1UL << 11) /**< ANTTRIG pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_SHIFT 11 /**< Shift value for GPIO_ANTTRIGPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_MASK 0x800UL /**< Bit mask for GPIO_ANTTRIGPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN (0x1UL << 12) /**< ANTTRIGSTOP pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_SHIFT 12 /**< Shift value for GPIO_ANTTRIGSTOPPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_MASK 0x1000UL /**< Bit mask for GPIO_ANTTRIGSTOPPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_DCLKPEN (0x1UL << 13) /**< DCLK pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_DCLKPEN_SHIFT 13 /**< Shift value for GPIO_DCLKPEN */ -#define _GPIO_MODEM_ROUTEEN_DCLKPEN_MASK 0x2000UL /**< Bit mask for GPIO_DCLKPEN */ -#define _GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_DOUTPEN (0x1UL << 14) /**< DOUT pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_DOUTPEN_SHIFT 14 /**< Shift value for GPIO_DOUTPEN */ -#define _GPIO_MODEM_ROUTEEN_DOUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_DOUTPEN */ -#define _GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_MASK 0x00007FFFUL /**< Mask for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN (0x1UL << 0) /**< ANT0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_SHIFT 0 /**< Shift value for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_MASK 0x1UL /**< Bit mask for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN (0x1UL << 1) /**< ANT1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_SHIFT 1 /**< Shift value for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_MASK 0x2UL /**< Bit mask for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN (0x1UL << 2) /**< ANTROLLOVER pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_SHIFT 2 /**< Shift value for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_MASK 0x4UL /**< Bit mask for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN (0x1UL << 3) /**< ANTRR0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_SHIFT 3 /**< Shift value for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_MASK 0x8UL /**< Bit mask for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN (0x1UL << 4) /**< ANTRR1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_SHIFT 4 /**< Shift value for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_MASK 0x10UL /**< Bit mask for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN (0x1UL << 5) /**< ANTRR2 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_SHIFT 5 /**< Shift value for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_MASK 0x20UL /**< Bit mask for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN (0x1UL << 6) /**< ANTRR3 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_SHIFT 6 /**< Shift value for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_MASK 0x40UL /**< Bit mask for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN (0x1UL << 7) /**< ANTRR4 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_SHIFT 7 /**< Shift value for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_MASK 0x80UL /**< Bit mask for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN (0x1UL << 8) /**< ANTRR5 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_SHIFT 8 /**< Shift value for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_MASK 0x100UL /**< Bit mask for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN (0x1UL << 9) /**< ANTSWEN pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_SHIFT 9 /**< Shift value for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_MASK 0x200UL /**< Bit mask for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN (0x1UL << 10) /**< ANTSWUS pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_SHIFT 10 /**< Shift value for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_MASK 0x400UL /**< Bit mask for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN (0x1UL << 11) /**< ANTTRIG pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_SHIFT 11 /**< Shift value for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_MASK 0x800UL /**< Bit mask for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN (0x1UL << 12) /**< ANTTRIGSTOP pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_SHIFT 12 /**< Shift value for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_MASK 0x1000UL /**< Bit mask for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN (0x1UL << 13) /**< DCLK pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_SHIFT 13 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_MASK 0x2000UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN (0x1UL << 14) /**< DOUT pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_SHIFT 14 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ /* Bit fields for GPIO_MODEM ANT0ROUTE */ -#define _GPIO_MODEM_ANT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT0ROUTE */ -#define _GPIO_MODEM_ANT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT0ROUTE */ -#define _GPIO_MODEM_ANT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ -#define GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ -#define _GPIO_MODEM_ANT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ -#define GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ +#define _GPIO_MODEM_ANT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ +#define _GPIO_MODEM_ANT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ /* Bit fields for GPIO_MODEM ANT1ROUTE */ -#define _GPIO_MODEM_ANT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT1ROUTE */ -#define _GPIO_MODEM_ANT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT1ROUTE */ -#define _GPIO_MODEM_ANT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ -#define GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ -#define _GPIO_MODEM_ANT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ -#define GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ +#define _GPIO_MODEM_ANT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ +#define _GPIO_MODEM_ANT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ /* Bit fields for GPIO_MODEM ANTROLLOVERROUTE */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTROLLOVERROUTE*/ -#define _GPIO_MODEM_ANTROLLOVERROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTROLLOVERROUTE */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ -#define GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ -#define GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTROLLOVERROUTE */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ /* Bit fields for GPIO_MODEM ANTRR0ROUTE */ -#define _GPIO_MODEM_ANTRR0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR0ROUTE */ -#define _GPIO_MODEM_ANTRR0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR0ROUTE */ -#define _GPIO_MODEM_ANTRR0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ -#define GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ -#define _GPIO_MODEM_ANTRR0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ -#define GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ +#define _GPIO_MODEM_ANTRR0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ /* Bit fields for GPIO_MODEM ANTRR1ROUTE */ -#define _GPIO_MODEM_ANTRR1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR1ROUTE */ -#define _GPIO_MODEM_ANTRR1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR1ROUTE */ -#define _GPIO_MODEM_ANTRR1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ -#define GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ -#define _GPIO_MODEM_ANTRR1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ -#define GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ +#define _GPIO_MODEM_ANTRR1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ /* Bit fields for GPIO_MODEM ANTRR2ROUTE */ -#define _GPIO_MODEM_ANTRR2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR2ROUTE */ -#define _GPIO_MODEM_ANTRR2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR2ROUTE */ -#define _GPIO_MODEM_ANTRR2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ -#define GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ -#define _GPIO_MODEM_ANTRR2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ -#define GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ +#define _GPIO_MODEM_ANTRR2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ /* Bit fields for GPIO_MODEM ANTRR3ROUTE */ -#define _GPIO_MODEM_ANTRR3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR3ROUTE */ -#define _GPIO_MODEM_ANTRR3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR3ROUTE */ -#define _GPIO_MODEM_ANTRR3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ -#define GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ -#define _GPIO_MODEM_ANTRR3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ -#define GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ +#define _GPIO_MODEM_ANTRR3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ /* Bit fields for GPIO_MODEM ANTRR4ROUTE */ -#define _GPIO_MODEM_ANTRR4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR4ROUTE */ -#define _GPIO_MODEM_ANTRR4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR4ROUTE */ -#define _GPIO_MODEM_ANTRR4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ -#define GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ -#define _GPIO_MODEM_ANTRR4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ -#define GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ +#define _GPIO_MODEM_ANTRR4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ /* Bit fields for GPIO_MODEM ANTRR5ROUTE */ -#define _GPIO_MODEM_ANTRR5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR5ROUTE */ -#define _GPIO_MODEM_ANTRR5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR5ROUTE */ -#define _GPIO_MODEM_ANTRR5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ -#define GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ -#define _GPIO_MODEM_ANTRR5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ -#define GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ +#define _GPIO_MODEM_ANTRR5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ /* Bit fields for GPIO_MODEM ANTSWENROUTE */ -#define _GPIO_MODEM_ANTSWENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWENROUTE */ -#define _GPIO_MODEM_ANTSWENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWENROUTE */ -#define _GPIO_MODEM_ANTSWENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTSWENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ -#define GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ -#define _GPIO_MODEM_ANTSWENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTSWENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ -#define GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ +#define _GPIO_MODEM_ANTSWENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ /* Bit fields for GPIO_MODEM ANTSWUSROUTE */ -#define _GPIO_MODEM_ANTSWUSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWUSROUTE */ -#define _GPIO_MODEM_ANTSWUSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWUSROUTE */ -#define _GPIO_MODEM_ANTSWUSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTSWUSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ -#define GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ -#define _GPIO_MODEM_ANTSWUSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTSWUSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ -#define GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ +#define _GPIO_MODEM_ANTSWUSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ /* Bit fields for GPIO_MODEM ANTTRIGROUTE */ -#define _GPIO_MODEM_ANTTRIGROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGROUTE */ -#define _GPIO_MODEM_ANTTRIGROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGROUTE */ -#define _GPIO_MODEM_ANTTRIGROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTTRIGROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ -#define GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ -#define _GPIO_MODEM_ANTTRIGROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTTRIGROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ -#define GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ +#define _GPIO_MODEM_ANTTRIGROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ /* Bit fields for GPIO_MODEM ANTTRIGSTOPROUTE */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGSTOPROUTE*/ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGSTOPROUTE */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ -#define GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ -#define GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGSTOPROUTE */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ /* Bit fields for GPIO_MODEM DCLKROUTE */ -#define _GPIO_MODEM_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DCLKROUTE */ -#define _GPIO_MODEM_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DCLKROUTE */ -#define _GPIO_MODEM_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ -#define GPIO_MODEM_DCLKROUTE_PORT_DEFAULT (_GPIO_MODEM_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ -#define _GPIO_MODEM_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ -#define GPIO_MODEM_DCLKROUTE_PIN_DEFAULT (_GPIO_MODEM_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ +#define _GPIO_MODEM_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PORT_DEFAULT (_GPIO_MODEM_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ +#define _GPIO_MODEM_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PIN_DEFAULT (_GPIO_MODEM_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ /* Bit fields for GPIO_MODEM DINROUTE */ -#define _GPIO_MODEM_DINROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DINROUTE */ -#define _GPIO_MODEM_DINROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DINROUTE */ -#define _GPIO_MODEM_DINROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_DINROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_DINROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ -#define GPIO_MODEM_DINROUTE_PORT_DEFAULT (_GPIO_MODEM_DINROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ -#define _GPIO_MODEM_DINROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_DINROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_DINROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ -#define GPIO_MODEM_DINROUTE_PIN_DEFAULT (_GPIO_MODEM_DINROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ +#define _GPIO_MODEM_DINROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PORT_DEFAULT (_GPIO_MODEM_DINROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ +#define _GPIO_MODEM_DINROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PIN_DEFAULT (_GPIO_MODEM_DINROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ /* Bit fields for GPIO_MODEM DOUTROUTE */ -#define _GPIO_MODEM_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DOUTROUTE */ -#define _GPIO_MODEM_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DOUTROUTE */ -#define _GPIO_MODEM_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ -#define GPIO_MODEM_DOUTROUTE_PORT_DEFAULT (_GPIO_MODEM_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ -#define _GPIO_MODEM_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ -#define GPIO_MODEM_DOUTROUTE_PIN_DEFAULT (_GPIO_MODEM_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ +#define _GPIO_MODEM_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PORT_DEFAULT (_GPIO_MODEM_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ +#define _GPIO_MODEM_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PIN_DEFAULT (_GPIO_MODEM_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ /* Bit fields for GPIO_PCNT S0INROUTE */ -#define _GPIO_PCNT_S0INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S0INROUTE */ -#define _GPIO_PCNT_S0INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S0INROUTE */ -#define _GPIO_PCNT_S0INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PCNT_S0INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PCNT_S0INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ -#define GPIO_PCNT_S0INROUTE_PORT_DEFAULT (_GPIO_PCNT_S0INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ -#define _GPIO_PCNT_S0INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PCNT_S0INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PCNT_S0INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ -#define GPIO_PCNT_S0INROUTE_PIN_DEFAULT (_GPIO_PCNT_S0INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ +#define _GPIO_PCNT_S0INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S0INROUTE */ +#define _GPIO_PCNT_S0INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S0INROUTE */ +#define _GPIO_PCNT_S0INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PCNT_S0INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PCNT_S0INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ +#define GPIO_PCNT_S0INROUTE_PORT_DEFAULT (_GPIO_PCNT_S0INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ +#define _GPIO_PCNT_S0INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PCNT_S0INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PCNT_S0INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ +#define GPIO_PCNT_S0INROUTE_PIN_DEFAULT (_GPIO_PCNT_S0INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ /* Bit fields for GPIO_PCNT S1INROUTE */ -#define _GPIO_PCNT_S1INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S1INROUTE */ -#define _GPIO_PCNT_S1INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S1INROUTE */ -#define _GPIO_PCNT_S1INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PCNT_S1INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PCNT_S1INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ -#define GPIO_PCNT_S1INROUTE_PORT_DEFAULT (_GPIO_PCNT_S1INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ -#define _GPIO_PCNT_S1INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PCNT_S1INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PCNT_S1INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ -#define GPIO_PCNT_S1INROUTE_PIN_DEFAULT (_GPIO_PCNT_S1INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ +#define _GPIO_PCNT_S1INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S1INROUTE */ +#define _GPIO_PCNT_S1INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S1INROUTE */ +#define _GPIO_PCNT_S1INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PCNT_S1INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PCNT_S1INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ +#define GPIO_PCNT_S1INROUTE_PORT_DEFAULT (_GPIO_PCNT_S1INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ +#define _GPIO_PCNT_S1INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PCNT_S1INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PCNT_S1INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ +#define GPIO_PCNT_S1INROUTE_PIN_DEFAULT (_GPIO_PCNT_S1INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ /* Bit fields for GPIO_PRS ROUTEEN */ -#define _GPIO_PRS_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ROUTEEN */ -#define _GPIO_PRS_ROUTEEN_MASK 0x0000FFFFUL /**< Mask for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH0PEN (0x1UL << 0) /**< ASYNCH0 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT 0 /**< Shift value for GPIO_ASYNCH0PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_MASK 0x1UL /**< Bit mask for GPIO_ASYNCH0PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH1PEN (0x1UL << 1) /**< ASYNCH1 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_SHIFT 1 /**< Shift value for GPIO_ASYNCH1PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_MASK 0x2UL /**< Bit mask for GPIO_ASYNCH1PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH2PEN (0x1UL << 2) /**< ASYNCH2 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_SHIFT 2 /**< Shift value for GPIO_ASYNCH2PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_MASK 0x4UL /**< Bit mask for GPIO_ASYNCH2PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH3PEN (0x1UL << 3) /**< ASYNCH3 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_SHIFT 3 /**< Shift value for GPIO_ASYNCH3PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_MASK 0x8UL /**< Bit mask for GPIO_ASYNCH3PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH4PEN (0x1UL << 4) /**< ASYNCH4 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_SHIFT 4 /**< Shift value for GPIO_ASYNCH4PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_MASK 0x10UL /**< Bit mask for GPIO_ASYNCH4PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH5PEN (0x1UL << 5) /**< ASYNCH5 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_SHIFT 5 /**< Shift value for GPIO_ASYNCH5PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_MASK 0x20UL /**< Bit mask for GPIO_ASYNCH5PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH6PEN (0x1UL << 6) /**< ASYNCH6 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_SHIFT 6 /**< Shift value for GPIO_ASYNCH6PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_MASK 0x40UL /**< Bit mask for GPIO_ASYNCH6PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH7PEN (0x1UL << 7) /**< ASYNCH7 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_SHIFT 7 /**< Shift value for GPIO_ASYNCH7PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_MASK 0x80UL /**< Bit mask for GPIO_ASYNCH7PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH8PEN (0x1UL << 8) /**< ASYNCH8 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_SHIFT 8 /**< Shift value for GPIO_ASYNCH8PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_MASK 0x100UL /**< Bit mask for GPIO_ASYNCH8PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH9PEN (0x1UL << 9) /**< ASYNCH9 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_SHIFT 9 /**< Shift value for GPIO_ASYNCH9PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_MASK 0x200UL /**< Bit mask for GPIO_ASYNCH9PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH10PEN (0x1UL << 10) /**< ASYNCH10 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_SHIFT 10 /**< Shift value for GPIO_ASYNCH10PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_MASK 0x400UL /**< Bit mask for GPIO_ASYNCH10PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH11PEN (0x1UL << 11) /**< ASYNCH11 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_SHIFT 11 /**< Shift value for GPIO_ASYNCH11PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_MASK 0x800UL /**< Bit mask for GPIO_ASYNCH11PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH0PEN (0x1UL << 12) /**< SYNCH0 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT 12 /**< Shift value for GPIO_SYNCH0PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_MASK 0x1000UL /**< Bit mask for GPIO_SYNCH0PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH1PEN (0x1UL << 13) /**< SYNCH1 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_SHIFT 13 /**< Shift value for GPIO_SYNCH1PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_MASK 0x2000UL /**< Bit mask for GPIO_SYNCH1PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH2PEN (0x1UL << 14) /**< SYNCH2 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_SHIFT 14 /**< Shift value for GPIO_SYNCH2PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_MASK 0x4000UL /**< Bit mask for GPIO_SYNCH2PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH3PEN (0x1UL << 15) /**< SYNCH3 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_SHIFT 15 /**< Shift value for GPIO_SYNCH3PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_MASK 0x8000UL /**< Bit mask for GPIO_SYNCH3PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_MASK 0x0000FFFFUL /**< Mask for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN (0x1UL << 0) /**< ASYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT 0 /**< Shift value for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_MASK 0x1UL /**< Bit mask for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN (0x1UL << 1) /**< ASYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_SHIFT 1 /**< Shift value for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_MASK 0x2UL /**< Bit mask for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN (0x1UL << 2) /**< ASYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_SHIFT 2 /**< Shift value for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_MASK 0x4UL /**< Bit mask for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN (0x1UL << 3) /**< ASYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_SHIFT 3 /**< Shift value for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_MASK 0x8UL /**< Bit mask for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN (0x1UL << 4) /**< ASYNCH4 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_SHIFT 4 /**< Shift value for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_MASK 0x10UL /**< Bit mask for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN (0x1UL << 5) /**< ASYNCH5 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_SHIFT 5 /**< Shift value for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_MASK 0x20UL /**< Bit mask for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN (0x1UL << 6) /**< ASYNCH6 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_SHIFT 6 /**< Shift value for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_MASK 0x40UL /**< Bit mask for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN (0x1UL << 7) /**< ASYNCH7 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_SHIFT 7 /**< Shift value for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_MASK 0x80UL /**< Bit mask for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN (0x1UL << 8) /**< ASYNCH8 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_SHIFT 8 /**< Shift value for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_MASK 0x100UL /**< Bit mask for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN (0x1UL << 9) /**< ASYNCH9 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_SHIFT 9 /**< Shift value for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_MASK 0x200UL /**< Bit mask for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN (0x1UL << 10) /**< ASYNCH10 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_SHIFT 10 /**< Shift value for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_MASK 0x400UL /**< Bit mask for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN (0x1UL << 11) /**< ASYNCH11 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_SHIFT 11 /**< Shift value for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_MASK 0x800UL /**< Bit mask for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN (0x1UL << 12) /**< SYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT 12 /**< Shift value for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_MASK 0x1000UL /**< Bit mask for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN (0x1UL << 13) /**< SYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_SHIFT 13 /**< Shift value for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_MASK 0x2000UL /**< Bit mask for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN (0x1UL << 14) /**< SYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_SHIFT 14 /**< Shift value for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_MASK 0x4000UL /**< Bit mask for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN (0x1UL << 15) /**< SYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_SHIFT 15 /**< Shift value for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_MASK 0x8000UL /**< Bit mask for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ /* Bit fields for GPIO_PRS ASYNCH0ROUTE */ -#define _GPIO_PRS_ASYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH0ROUTE */ -#define _GPIO_PRS_ASYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH0ROUTE */ -#define _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ -#define GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ -#define _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ -#define GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ +#define _GPIO_PRS_ASYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH1ROUTE */ -#define _GPIO_PRS_ASYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH1ROUTE */ -#define _GPIO_PRS_ASYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH1ROUTE */ -#define _GPIO_PRS_ASYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ -#define GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ -#define _GPIO_PRS_ASYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ -#define GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ +#define _GPIO_PRS_ASYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH2ROUTE */ -#define _GPIO_PRS_ASYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH2ROUTE */ -#define _GPIO_PRS_ASYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH2ROUTE */ -#define _GPIO_PRS_ASYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ -#define GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ -#define _GPIO_PRS_ASYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ -#define GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ +#define _GPIO_PRS_ASYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH3ROUTE */ -#define _GPIO_PRS_ASYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH3ROUTE */ -#define _GPIO_PRS_ASYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH3ROUTE */ -#define _GPIO_PRS_ASYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ -#define GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ -#define _GPIO_PRS_ASYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ -#define GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ +#define _GPIO_PRS_ASYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH4ROUTE */ -#define _GPIO_PRS_ASYNCH4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH4ROUTE */ -#define _GPIO_PRS_ASYNCH4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH4ROUTE */ -#define _GPIO_PRS_ASYNCH4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ -#define GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ -#define _GPIO_PRS_ASYNCH4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ -#define GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ +#define _GPIO_PRS_ASYNCH4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH5ROUTE */ -#define _GPIO_PRS_ASYNCH5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH5ROUTE */ -#define _GPIO_PRS_ASYNCH5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH5ROUTE */ -#define _GPIO_PRS_ASYNCH5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ -#define GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ -#define _GPIO_PRS_ASYNCH5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ -#define GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ +#define _GPIO_PRS_ASYNCH5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH6ROUTE */ -#define _GPIO_PRS_ASYNCH6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH6ROUTE */ -#define _GPIO_PRS_ASYNCH6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH6ROUTE */ -#define _GPIO_PRS_ASYNCH6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ -#define GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ -#define _GPIO_PRS_ASYNCH6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ -#define GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ +#define _GPIO_PRS_ASYNCH6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH7ROUTE */ -#define _GPIO_PRS_ASYNCH7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH7ROUTE */ -#define _GPIO_PRS_ASYNCH7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH7ROUTE */ -#define _GPIO_PRS_ASYNCH7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ -#define GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ -#define _GPIO_PRS_ASYNCH7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ -#define GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ +#define _GPIO_PRS_ASYNCH7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH8ROUTE */ -#define _GPIO_PRS_ASYNCH8ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH8ROUTE */ -#define _GPIO_PRS_ASYNCH8ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH8ROUTE */ -#define _GPIO_PRS_ASYNCH8ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH8ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ -#define GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ -#define _GPIO_PRS_ASYNCH8ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH8ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ -#define GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ +#define _GPIO_PRS_ASYNCH8ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH9ROUTE */ -#define _GPIO_PRS_ASYNCH9ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH9ROUTE */ -#define _GPIO_PRS_ASYNCH9ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH9ROUTE */ -#define _GPIO_PRS_ASYNCH9ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH9ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ -#define GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ -#define _GPIO_PRS_ASYNCH9ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH9ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ -#define GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ +#define _GPIO_PRS_ASYNCH9ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH10ROUTE */ -#define _GPIO_PRS_ASYNCH10ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH10ROUTE */ -#define _GPIO_PRS_ASYNCH10ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH10ROUTE */ -#define _GPIO_PRS_ASYNCH10ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH10ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ -#define GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ -#define _GPIO_PRS_ASYNCH10ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH10ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ -#define GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ +#define _GPIO_PRS_ASYNCH10ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ /* Bit fields for GPIO_PRS ASYNCH11ROUTE */ -#define _GPIO_PRS_ASYNCH11ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH11ROUTE */ -#define _GPIO_PRS_ASYNCH11ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH11ROUTE */ -#define _GPIO_PRS_ASYNCH11ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH11ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ -#define GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ -#define _GPIO_PRS_ASYNCH11ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH11ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ -#define GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ +#define _GPIO_PRS_ASYNCH11ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ /* Bit fields for GPIO_PRS SYNCH0ROUTE */ -#define _GPIO_PRS_SYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH0ROUTE */ -#define _GPIO_PRS_SYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH0ROUTE */ -#define _GPIO_PRS_SYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_SYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ -#define GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ -#define _GPIO_PRS_SYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_SYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ -#define GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ +#define _GPIO_PRS_SYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ /* Bit fields for GPIO_PRS SYNCH1ROUTE */ -#define _GPIO_PRS_SYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH1ROUTE */ -#define _GPIO_PRS_SYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH1ROUTE */ -#define _GPIO_PRS_SYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_SYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ -#define GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ -#define _GPIO_PRS_SYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_SYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ -#define GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ +#define _GPIO_PRS_SYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ /* Bit fields for GPIO_PRS SYNCH2ROUTE */ -#define _GPIO_PRS_SYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH2ROUTE */ -#define _GPIO_PRS_SYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH2ROUTE */ -#define _GPIO_PRS_SYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_SYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ -#define GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ -#define _GPIO_PRS_SYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_SYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ -#define GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ +#define _GPIO_PRS_SYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ /* Bit fields for GPIO_PRS SYNCH3ROUTE */ -#define _GPIO_PRS_SYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH3ROUTE */ -#define _GPIO_PRS_SYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH3ROUTE */ -#define _GPIO_PRS_SYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_SYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ -#define GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ -#define _GPIO_PRS_SYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_SYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ -#define GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ +#define _GPIO_PRS_SYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ /* Bit fields for GPIO_SYXO BUFOUTREQINASYNCROUTE */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_MASK 0x000F0003UL /**< Mask for GPIO_SYXO_BUFOUTREQINASYNCROUTE */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ -#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ -#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_MASK 0x000F0003UL /**< Mask for GPIO_SYXO_BUFOUTREQINASYNCROUTE */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ /* Bit fields for GPIO_TIMER ROUTEEN */ -#define _GPIO_TIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_ROUTEEN */ -#define _GPIO_TIMER_ROUTEEN_MASK 0x0000003FUL /**< Mask for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC0PEN (0x1UL << 0) /**< CC0 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CC0PEN_SHIFT 0 /**< Shift value for GPIO_CC0PEN */ -#define _GPIO_TIMER_ROUTEEN_CC0PEN_MASK 0x1UL /**< Bit mask for GPIO_CC0PEN */ -#define _GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC1PEN (0x1UL << 1) /**< CC1 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CC1PEN_SHIFT 1 /**< Shift value for GPIO_CC1PEN */ -#define _GPIO_TIMER_ROUTEEN_CC1PEN_MASK 0x2UL /**< Bit mask for GPIO_CC1PEN */ -#define _GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC2PEN (0x1UL << 2) /**< CC2 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CC2PEN_SHIFT 2 /**< Shift value for GPIO_CC2PEN */ -#define _GPIO_TIMER_ROUTEEN_CC2PEN_MASK 0x4UL /**< Bit mask for GPIO_CC2PEN */ -#define _GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC0PEN (0x1UL << 3) /**< CDTI0 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CCC0PEN_SHIFT 3 /**< Shift value for GPIO_CCC0PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC0PEN_MASK 0x8UL /**< Bit mask for GPIO_CCC0PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC1PEN (0x1UL << 4) /**< CDTI1 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CCC1PEN_SHIFT 4 /**< Shift value for GPIO_CCC1PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC1PEN_MASK 0x10UL /**< Bit mask for GPIO_CCC1PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC2PEN (0x1UL << 5) /**< CDTI2 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CCC2PEN_SHIFT 5 /**< Shift value for GPIO_CCC2PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC2PEN_MASK 0x20UL /**< Bit mask for GPIO_CCC2PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_MASK 0x0000003FUL /**< Mask for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN (0x1UL << 0) /**< CC0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_SHIFT 0 /**< Shift value for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_MASK 0x1UL /**< Bit mask for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN (0x1UL << 1) /**< CC1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_SHIFT 1 /**< Shift value for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_MASK 0x2UL /**< Bit mask for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN (0x1UL << 2) /**< CC2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_SHIFT 2 /**< Shift value for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_MASK 0x4UL /**< Bit mask for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN (0x1UL << 3) /**< CDTI0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_SHIFT 3 /**< Shift value for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_MASK 0x8UL /**< Bit mask for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN (0x1UL << 4) /**< CDTI1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_SHIFT 4 /**< Shift value for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_MASK 0x10UL /**< Bit mask for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN (0x1UL << 5) /**< CDTI2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_SHIFT 5 /**< Shift value for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_MASK 0x20UL /**< Bit mask for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ /* Bit fields for GPIO_TIMER CC0ROUTE */ -#define _GPIO_TIMER_CC0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC0ROUTE */ -#define _GPIO_TIMER_CC0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC0ROUTE */ -#define _GPIO_TIMER_CC0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CC0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CC0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ -#define GPIO_TIMER_CC0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ -#define _GPIO_TIMER_CC0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CC0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CC0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ -#define GPIO_TIMER_CC0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ +#define _GPIO_TIMER_CC0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ +#define _GPIO_TIMER_CC0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ /* Bit fields for GPIO_TIMER CC1ROUTE */ -#define _GPIO_TIMER_CC1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC1ROUTE */ -#define _GPIO_TIMER_CC1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC1ROUTE */ -#define _GPIO_TIMER_CC1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CC1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CC1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ -#define GPIO_TIMER_CC1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ -#define _GPIO_TIMER_CC1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CC1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CC1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ -#define GPIO_TIMER_CC1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ +#define _GPIO_TIMER_CC1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ +#define _GPIO_TIMER_CC1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ /* Bit fields for GPIO_TIMER CC2ROUTE */ -#define _GPIO_TIMER_CC2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC2ROUTE */ -#define _GPIO_TIMER_CC2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC2ROUTE */ -#define _GPIO_TIMER_CC2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CC2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CC2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ -#define GPIO_TIMER_CC2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ -#define _GPIO_TIMER_CC2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CC2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CC2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ -#define GPIO_TIMER_CC2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ +#define _GPIO_TIMER_CC2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ +#define _GPIO_TIMER_CC2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ /* Bit fields for GPIO_TIMER CDTI0ROUTE */ -#define _GPIO_TIMER_CDTI0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI0ROUTE */ -#define _GPIO_TIMER_CDTI0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI0ROUTE */ -#define _GPIO_TIMER_CDTI0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CDTI0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ -#define GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ -#define _GPIO_TIMER_CDTI0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CDTI0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ -#define GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ +#define _GPIO_TIMER_CDTI0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ /* Bit fields for GPIO_TIMER CDTI1ROUTE */ -#define _GPIO_TIMER_CDTI1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI1ROUTE */ -#define _GPIO_TIMER_CDTI1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI1ROUTE */ -#define _GPIO_TIMER_CDTI1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CDTI1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ -#define GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ -#define _GPIO_TIMER_CDTI1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CDTI1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ -#define GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ +#define _GPIO_TIMER_CDTI1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ /* Bit fields for GPIO_TIMER CDTI2ROUTE */ -#define _GPIO_TIMER_CDTI2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI2ROUTE */ -#define _GPIO_TIMER_CDTI2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI2ROUTE */ -#define _GPIO_TIMER_CDTI2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CDTI2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ -#define GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ -#define _GPIO_TIMER_CDTI2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CDTI2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ -#define GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ +#define _GPIO_TIMER_CDTI2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ /* Bit fields for GPIO_USART ROUTEEN */ -#define _GPIO_USART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_ROUTEEN */ -#define _GPIO_USART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ -#define _GPIO_USART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ -#define _GPIO_USART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ -#define _GPIO_USART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_CSPEN_DEFAULT (_GPIO_USART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ -#define _GPIO_USART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ -#define _GPIO_USART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ -#define _GPIO_USART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_USART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ -#define _GPIO_USART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ -#define _GPIO_USART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ -#define _GPIO_USART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_RXPEN_DEFAULT (_GPIO_USART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_CLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ -#define _GPIO_USART_ROUTEEN_CLKPEN_SHIFT 3 /**< Shift value for GPIO_CLKPEN */ -#define _GPIO_USART_ROUTEEN_CLKPEN_MASK 0x8UL /**< Bit mask for GPIO_CLKPEN */ -#define _GPIO_USART_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_CLKPEN_DEFAULT (_GPIO_USART_ROUTEEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ -#define _GPIO_USART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ -#define _GPIO_USART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ -#define _GPIO_USART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_TXPEN_DEFAULT (_GPIO_USART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define _GPIO_USART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_ROUTEEN */ +#define _GPIO_USART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN_DEFAULT (_GPIO_USART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_USART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN_DEFAULT (_GPIO_USART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CLKPEN_SHIFT 3 /**< Shift value for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_MASK 0x8UL /**< Bit mask for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN_DEFAULT (_GPIO_USART_ROUTEEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN_DEFAULT (_GPIO_USART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ /* Bit fields for GPIO_USART CSROUTE */ -#define _GPIO_USART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CSROUTE */ -#define _GPIO_USART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CSROUTE */ -#define _GPIO_USART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ -#define GPIO_USART_CSROUTE_PORT_DEFAULT (_GPIO_USART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ -#define _GPIO_USART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ -#define GPIO_USART_CSROUTE_PIN_DEFAULT (_GPIO_USART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PORT_DEFAULT (_GPIO_USART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PIN_DEFAULT (_GPIO_USART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ /* Bit fields for GPIO_USART CTSROUTE */ -#define _GPIO_USART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CTSROUTE */ -#define _GPIO_USART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CTSROUTE */ -#define _GPIO_USART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ -#define GPIO_USART_CTSROUTE_PORT_DEFAULT (_GPIO_USART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ -#define _GPIO_USART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ -#define GPIO_USART_CTSROUTE_PIN_DEFAULT (_GPIO_USART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ +#define _GPIO_USART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PORT_DEFAULT (_GPIO_USART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ +#define _GPIO_USART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PIN_DEFAULT (_GPIO_USART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ /* Bit fields for GPIO_USART RTSROUTE */ -#define _GPIO_USART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RTSROUTE */ -#define _GPIO_USART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RTSROUTE */ -#define _GPIO_USART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ -#define GPIO_USART_RTSROUTE_PORT_DEFAULT (_GPIO_USART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ -#define _GPIO_USART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ -#define GPIO_USART_RTSROUTE_PIN_DEFAULT (_GPIO_USART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ +#define _GPIO_USART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PORT_DEFAULT (_GPIO_USART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ +#define _GPIO_USART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PIN_DEFAULT (_GPIO_USART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ /* Bit fields for GPIO_USART RXROUTE */ -#define _GPIO_USART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RXROUTE */ -#define _GPIO_USART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RXROUTE */ -#define _GPIO_USART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ -#define GPIO_USART_RXROUTE_PORT_DEFAULT (_GPIO_USART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ -#define _GPIO_USART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ -#define GPIO_USART_RXROUTE_PIN_DEFAULT (_GPIO_USART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PORT_DEFAULT (_GPIO_USART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PIN_DEFAULT (_GPIO_USART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ /* Bit fields for GPIO_USART CLKROUTE */ -#define _GPIO_USART_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CLKROUTE */ -#define _GPIO_USART_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CLKROUTE */ -#define _GPIO_USART_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ -#define GPIO_USART_CLKROUTE_PORT_DEFAULT (_GPIO_USART_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ -#define _GPIO_USART_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ -#define GPIO_USART_CLKROUTE_PIN_DEFAULT (_GPIO_USART_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ +#define _GPIO_USART_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PORT_DEFAULT (_GPIO_USART_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ +#define _GPIO_USART_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PIN_DEFAULT (_GPIO_USART_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ /* Bit fields for GPIO_USART TXROUTE */ -#define _GPIO_USART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_TXROUTE */ -#define _GPIO_USART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_TXROUTE */ -#define _GPIO_USART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ -#define GPIO_USART_TXROUTE_PORT_DEFAULT (_GPIO_USART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ -#define _GPIO_USART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ -#define GPIO_USART_TXROUTE_PIN_DEFAULT (_GPIO_USART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PORT_DEFAULT (_GPIO_USART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PIN_DEFAULT (_GPIO_USART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ /** @} End of group Parts */ #endif // EFR32SG28_GPIO_H diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpio_port.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpio_port.h index e1cc32636e..1925bcfac1 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_gpio_port.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -30,7 +30,6 @@ #ifndef GPIO_PORT_H #define GPIO_PORT_H - /**************************************************************************//** * @addtogroup Parts * @{ @@ -38,604 +37,601 @@ /**************************************************************************//** * @brief EFR32SG28 GPIO PORT *****************************************************************************/ -typedef struct -{ - __IOM uint32_t CTRL; /**< Port control */ - __IOM uint32_t MODEL; /**< mode low */ - uint32_t RESERVED0[1]; /**< Reserved for future use */ - __IOM uint32_t MODEH; /**< mode high */ - __IOM uint32_t DOUT; /**< data out */ - __IM uint32_t DIN; /**< data in */ - uint32_t RESERVED1[6]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t CTRL; /**< Port control */ + __IOM uint32_t MODEL; /**< mode low */ + uint32_t RESERVED0[1]; /**< Reserved for future use */ + __IOM uint32_t MODEH; /**< mode high */ + __IOM uint32_t DOUT; /**< data out */ + __IM uint32_t DIN; /**< data in */ + uint32_t RESERVED1[6]; /**< Reserved for future use */ } GPIO_PORT_TypeDef; - /* Bit fields for GPIO_P CTRL */ -#define _GPIO_P_CTRL_RESETVALUE 0x00400040UL /**< Default value for GPIO_P_CTRL */ -#define _GPIO_P_CTRL_MASK 0x10701070UL /**< Mask for GPIO_P_CTRL */ -#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ -#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ -#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */ -#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ -#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ -#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ -#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ -#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ -#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Data In Disable Alt */ -#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ -#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ -#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_RESETVALUE 0x00400040UL /**< Default value for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_MASK 0x10701070UL /**< Mask for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */ +#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Data In Disable Alt */ +#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ /* Bit fields for GPIO_P MODEL */ -#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ -#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ -#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ -#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ -#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ -#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ -#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ -#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ -#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ -#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ -#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ -#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ -#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ -#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ -#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ -#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ -#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ /* Bit fields for GPIO_P MODEH */ -#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MASK 0x0FFFFFFFUL /**< Mask for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ -#define _GPIO_P_MODEH_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ -#define _GPIO_P_MODEH_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_DEFAULT (_GPIO_P_MODEH_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_DISABLED (_GPIO_P_MODEH_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_INPUT (_GPIO_P_MODEH_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_INPUTPULL (_GPIO_P_MODEH_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_INPUTPULLFILTER (_GPIO_P_MODEH_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_PUSHPULL (_GPIO_P_MODEH_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_PUSHPULLALT (_GPIO_P_MODEH_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_WIREDOR (_GPIO_P_MODEH_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDAND (_GPIO_P_MODEH_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_WIREDANDFILTER (_GPIO_P_MODEH_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDALT (_GPIO_P_MODEH_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define _GPIO_P_MODEH_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ -#define _GPIO_P_MODEH_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ -#define _GPIO_P_MODEH_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_DEFAULT (_GPIO_P_MODEH_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_DISABLED (_GPIO_P_MODEH_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_INPUT (_GPIO_P_MODEH_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_INPUTPULL (_GPIO_P_MODEH_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_INPUTPULLFILTER (_GPIO_P_MODEH_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_PUSHPULL (_GPIO_P_MODEH_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_PUSHPULLALT (_GPIO_P_MODEH_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_WIREDOR (_GPIO_P_MODEH_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDAND (_GPIO_P_MODEH_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_WIREDANDFILTER (_GPIO_P_MODEH_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDANDPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDANDALT (_GPIO_P_MODEH_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define _GPIO_P_MODEH_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ -#define _GPIO_P_MODEH_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ -#define _GPIO_P_MODEH_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE2_DEFAULT (_GPIO_P_MODEH_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_DISABLED (_GPIO_P_MODEH_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_INPUT (_GPIO_P_MODEH_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_INPUTPULL (_GPIO_P_MODEH_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_INPUTPULLFILTER (_GPIO_P_MODEH_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE2_PUSHPULL (_GPIO_P_MODEH_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_PUSHPULLALT (_GPIO_P_MODEH_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_WIREDOR (_GPIO_P_MODEH_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE2_WIREDAND (_GPIO_P_MODEH_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_WIREDANDFILTER (_GPIO_P_MODEH_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE2_WIREDANDPULLUP (_GPIO_P_MODEH_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE2_WIREDANDALT (_GPIO_P_MODEH_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define _GPIO_P_MODEH_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ -#define _GPIO_P_MODEH_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ -#define _GPIO_P_MODEH_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE3_DEFAULT (_GPIO_P_MODEH_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE3_DISABLED (_GPIO_P_MODEH_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE3_INPUT (_GPIO_P_MODEH_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE3_INPUTPULL (_GPIO_P_MODEH_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE3_INPUTPULLFILTER (_GPIO_P_MODEH_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE3_PUSHPULL (_GPIO_P_MODEH_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE3_PUSHPULLALT (_GPIO_P_MODEH_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE3_WIREDOR (_GPIO_P_MODEH_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE3_WIREDAND (_GPIO_P_MODEH_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE3_WIREDANDFILTER (_GPIO_P_MODEH_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE3_WIREDANDPULLUP (_GPIO_P_MODEH_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE3_WIREDANDALT (_GPIO_P_MODEH_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define _GPIO_P_MODEH_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ -#define _GPIO_P_MODEH_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ -#define _GPIO_P_MODEH_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE4_DEFAULT (_GPIO_P_MODEH_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE4_DISABLED (_GPIO_P_MODEH_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE4_INPUT (_GPIO_P_MODEH_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE4_INPUTPULL (_GPIO_P_MODEH_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE4_INPUTPULLFILTER (_GPIO_P_MODEH_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE4_PUSHPULL (_GPIO_P_MODEH_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE4_PUSHPULLALT (_GPIO_P_MODEH_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE4_WIREDOR (_GPIO_P_MODEH_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE4_WIREDAND (_GPIO_P_MODEH_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE4_WIREDANDFILTER (_GPIO_P_MODEH_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE4_WIREDANDPULLUP (_GPIO_P_MODEH_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE4_WIREDANDALT (_GPIO_P_MODEH_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define _GPIO_P_MODEH_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ -#define _GPIO_P_MODEH_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ -#define _GPIO_P_MODEH_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE5_DEFAULT (_GPIO_P_MODEH_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE5_DISABLED (_GPIO_P_MODEH_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE5_INPUT (_GPIO_P_MODEH_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE5_INPUTPULL (_GPIO_P_MODEH_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE5_INPUTPULLFILTER (_GPIO_P_MODEH_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE5_PUSHPULL (_GPIO_P_MODEH_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE5_PUSHPULLALT (_GPIO_P_MODEH_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE5_WIREDOR (_GPIO_P_MODEH_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE5_WIREDAND (_GPIO_P_MODEH_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE5_WIREDANDFILTER (_GPIO_P_MODEH_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE5_WIREDANDPULLUP (_GPIO_P_MODEH_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE5_WIREDANDALT (_GPIO_P_MODEH_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define _GPIO_P_MODEH_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ -#define _GPIO_P_MODEH_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ -#define _GPIO_P_MODEH_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE6_DEFAULT (_GPIO_P_MODEH_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE6_DISABLED (_GPIO_P_MODEH_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE6_INPUT (_GPIO_P_MODEH_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE6_INPUTPULL (_GPIO_P_MODEH_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE6_INPUTPULLFILTER (_GPIO_P_MODEH_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE6_PUSHPULL (_GPIO_P_MODEH_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE6_PUSHPULLALT (_GPIO_P_MODEH_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE6_WIREDOR (_GPIO_P_MODEH_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE6_WIREDAND (_GPIO_P_MODEH_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE6_WIREDANDFILTER (_GPIO_P_MODEH_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE6_WIREDANDPULLUP (_GPIO_P_MODEH_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE6_WIREDANDALT (_GPIO_P_MODEH_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MASK 0x0FFFFFFFUL /**< Mask for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_DEFAULT (_GPIO_P_MODEH_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_DISABLED (_GPIO_P_MODEH_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUT (_GPIO_P_MODEH_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULL (_GPIO_P_MODEH_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULLFILTER (_GPIO_P_MODEH_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_PUSHPULL (_GPIO_P_MODEH_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_PUSHPULLALT (_GPIO_P_MODEH_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDOR (_GPIO_P_MODEH_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDAND (_GPIO_P_MODEH_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDFILTER (_GPIO_P_MODEH_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALT (_GPIO_P_MODEH_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEH_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEH_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_DEFAULT (_GPIO_P_MODEH_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_DISABLED (_GPIO_P_MODEH_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUT (_GPIO_P_MODEH_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUTPULL (_GPIO_P_MODEH_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUTPULLFILTER (_GPIO_P_MODEH_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_PUSHPULL (_GPIO_P_MODEH_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_PUSHPULLALT (_GPIO_P_MODEH_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDOR (_GPIO_P_MODEH_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDAND (_GPIO_P_MODEH_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDANDFILTER (_GPIO_P_MODEH_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALT (_GPIO_P_MODEH_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEH_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEH_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_DEFAULT (_GPIO_P_MODEH_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_DISABLED (_GPIO_P_MODEH_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_INPUT (_GPIO_P_MODEH_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_INPUTPULL (_GPIO_P_MODEH_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_INPUTPULLFILTER (_GPIO_P_MODEH_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_PUSHPULL (_GPIO_P_MODEH_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_PUSHPULLALT (_GPIO_P_MODEH_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_WIREDOR (_GPIO_P_MODEH_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDAND (_GPIO_P_MODEH_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_WIREDANDFILTER (_GPIO_P_MODEH_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDPULLUP (_GPIO_P_MODEH_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDALT (_GPIO_P_MODEH_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ +#define _GPIO_P_MODEH_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ +#define _GPIO_P_MODEH_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE3_DEFAULT (_GPIO_P_MODEH_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_DISABLED (_GPIO_P_MODEH_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_INPUT (_GPIO_P_MODEH_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_INPUTPULL (_GPIO_P_MODEH_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_INPUTPULLFILTER (_GPIO_P_MODEH_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE3_PUSHPULL (_GPIO_P_MODEH_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_PUSHPULLALT (_GPIO_P_MODEH_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_WIREDOR (_GPIO_P_MODEH_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE3_WIREDAND (_GPIO_P_MODEH_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_WIREDANDFILTER (_GPIO_P_MODEH_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE3_WIREDANDPULLUP (_GPIO_P_MODEH_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE3_WIREDANDALT (_GPIO_P_MODEH_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ +#define _GPIO_P_MODEH_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ +#define _GPIO_P_MODEH_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE4_DEFAULT (_GPIO_P_MODEH_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_DISABLED (_GPIO_P_MODEH_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_INPUT (_GPIO_P_MODEH_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_INPUTPULL (_GPIO_P_MODEH_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_INPUTPULLFILTER (_GPIO_P_MODEH_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE4_PUSHPULL (_GPIO_P_MODEH_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_PUSHPULLALT (_GPIO_P_MODEH_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_WIREDOR (_GPIO_P_MODEH_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE4_WIREDAND (_GPIO_P_MODEH_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_WIREDANDFILTER (_GPIO_P_MODEH_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE4_WIREDANDPULLUP (_GPIO_P_MODEH_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE4_WIREDANDALT (_GPIO_P_MODEH_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ +#define _GPIO_P_MODEH_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ +#define _GPIO_P_MODEH_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE5_DEFAULT (_GPIO_P_MODEH_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_DISABLED (_GPIO_P_MODEH_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_INPUT (_GPIO_P_MODEH_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_INPUTPULL (_GPIO_P_MODEH_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_INPUTPULLFILTER (_GPIO_P_MODEH_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE5_PUSHPULL (_GPIO_P_MODEH_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_PUSHPULLALT (_GPIO_P_MODEH_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_WIREDOR (_GPIO_P_MODEH_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE5_WIREDAND (_GPIO_P_MODEH_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_WIREDANDFILTER (_GPIO_P_MODEH_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE5_WIREDANDPULLUP (_GPIO_P_MODEH_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE5_WIREDANDALT (_GPIO_P_MODEH_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ +#define _GPIO_P_MODEH_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ +#define _GPIO_P_MODEH_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE6_DEFAULT (_GPIO_P_MODEH_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_DISABLED (_GPIO_P_MODEH_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_INPUT (_GPIO_P_MODEH_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_INPUTPULL (_GPIO_P_MODEH_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_INPUTPULLFILTER (_GPIO_P_MODEH_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE6_PUSHPULL (_GPIO_P_MODEH_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_PUSHPULLALT (_GPIO_P_MODEH_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_WIREDOR (_GPIO_P_MODEH_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE6_WIREDAND (_GPIO_P_MODEH_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_WIREDANDFILTER (_GPIO_P_MODEH_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE6_WIREDANDPULLUP (_GPIO_P_MODEH_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE6_WIREDANDALT (_GPIO_P_MODEH_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ /* Bit fields for GPIO_P DOUT */ -#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ -#define _GPIO_P_DOUT_MASK 0x00007FFFUL /**< Mask for GPIO_P_DOUT */ -#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ -#define _GPIO_P_DOUT_DOUT_MASK 0x7FFFUL /**< Bit mask for GPIO_DOUT */ -#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ -#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_MASK 0x00007FFFUL /**< Mask for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_MASK 0x7FFFUL /**< Bit mask for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ +#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ /* Bit fields for GPIO_P DIN */ -#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ -#define _GPIO_P_DIN_MASK 0x00007FFFUL /**< Mask for GPIO_P_DIN */ -#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ -#define _GPIO_P_DIN_DIN_MASK 0x7FFFUL /**< Bit mask for GPIO_DIN */ -#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ -#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ +#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ +#define _GPIO_P_DIN_MASK 0x00007FFFUL /**< Mask for GPIO_P_DIN */ +#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_MASK 0x7FFFUL /**< Bit mask for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ +#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ /** @} End of group Parts */ - #endif // GPIO_PORT_H diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_hfrco.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_hfrco.h index 3d8b05ab93..7017e057bc 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_hfrco.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_HFRCO_H #define EFR32SG28_HFRCO_H - #define HFRCO_HAS_SET_CLEAR /**************************************************************************//** @@ -43,43 +42,42 @@ *****************************************************************************/ /** HFRCO Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP Version ID */ - __IOM uint32_t CTRL; /**< Ctrl Register */ - __IOM uint32_t CAL; /**< Calibration Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Lock Register */ - uint32_t RESERVED1[1016U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version ID */ - __IOM uint32_t CTRL_SET; /**< Ctrl Register */ - __IOM uint32_t CAL_SET; /**< Calibration Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Lock Register */ - uint32_t RESERVED3[1016U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ - __IOM uint32_t CTRL_CLR; /**< Ctrl Register */ - __IOM uint32_t CAL_CLR; /**< Calibration Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Lock Register */ - uint32_t RESERVED5[1016U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ - __IOM uint32_t CTRL_TGL; /**< Ctrl Register */ - __IOM uint32_t CAL_TGL; /**< Calibration Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Lock Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t CTRL; /**< Ctrl Register */ + __IOM uint32_t CAL; /**< Calibration Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED1[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t CTRL_SET; /**< Ctrl Register */ + __IOM uint32_t CAL_SET; /**< Calibration Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED3[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t CTRL_CLR; /**< Ctrl Register */ + __IOM uint32_t CAL_CLR; /**< Calibration Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED5[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t CTRL_TGL; /**< Ctrl Register */ + __IOM uint32_t CAL_TGL; /**< Calibration Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ } HFRCO_TypeDef; /** @} End of group EFR32SG28_HFRCO */ @@ -91,135 +89,135 @@ typedef struct *****************************************************************************/ /* Bit fields for HFRCO IPVERSION */ -#define _HFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFRCO_IPVERSION */ -#define _HFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFRCO_IPVERSION */ -#define _HFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFRCO_IPVERSION */ -#define _HFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFRCO_IPVERSION */ -#define _HFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_IPVERSION */ -#define HFRCO_IPVERSION_IPVERSION_DEFAULT (_HFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_IPVERSION */ +#define HFRCO_IPVERSION_IPVERSION_DEFAULT (_HFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IPVERSION */ /* Bit fields for HFRCO CTRL */ -#define _HFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for HFRCO_CTRL */ -#define _HFRCO_CTRL_MASK 0x00000007UL /**< Mask for HFRCO_CTRL */ -#define HFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ -#define _HFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFRCO_FORCEEN */ -#define _HFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFRCO_FORCEEN */ -#define _HFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_FORCEEN_DEFAULT (_HFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand */ -#define _HFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFRCO_DISONDEMAND */ -#define _HFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFRCO_DISONDEMAND */ -#define _HFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_DISONDEMAND_DEFAULT (_HFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_EM23ONDEMAND (0x1UL << 2) /**< EM23 On-demand */ -#define _HFRCO_CTRL_EM23ONDEMAND_SHIFT 2 /**< Shift value for HFRCO_EM23ONDEMAND */ -#define _HFRCO_CTRL_EM23ONDEMAND_MASK 0x4UL /**< Bit mask for HFRCO_EM23ONDEMAND */ -#define _HFRCO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_EM23ONDEMAND_DEFAULT (_HFRCO_CTRL_EM23ONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define _HFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for HFRCO_CTRL */ +#define _HFRCO_CTRL_MASK 0x00000007UL /**< Mask for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _HFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN_DEFAULT (_HFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand */ +#define _HFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND_DEFAULT (_HFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_EM23ONDEMAND (0x1UL << 2) /**< EM23 On-demand */ +#define _HFRCO_CTRL_EM23ONDEMAND_SHIFT 2 /**< Shift value for HFRCO_EM23ONDEMAND */ +#define _HFRCO_CTRL_EM23ONDEMAND_MASK 0x4UL /**< Bit mask for HFRCO_EM23ONDEMAND */ +#define _HFRCO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_EM23ONDEMAND_DEFAULT (_HFRCO_CTRL_EM23ONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_CTRL */ /* Bit fields for HFRCO CAL */ -#define _HFRCO_CAL_RESETVALUE 0xA8689F7FUL /**< Default value for HFRCO_CAL */ -#define _HFRCO_CAL_MASK 0xFFFFBF7FUL /**< Mask for HFRCO_CAL */ -#define _HFRCO_CAL_TUNING_SHIFT 0 /**< Shift value for HFRCO_TUNING */ -#define _HFRCO_CAL_TUNING_MASK 0x7FUL /**< Bit mask for HFRCO_TUNING */ -#define _HFRCO_CAL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_TUNING_DEFAULT (_HFRCO_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_FINETUNING_SHIFT 8 /**< Shift value for HFRCO_FINETUNING */ -#define _HFRCO_CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for HFRCO_FINETUNING */ -#define _HFRCO_CAL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_FINETUNING_DEFAULT (_HFRCO_CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_LDOHP (0x1UL << 15) /**< LDO High Power Mode */ -#define _HFRCO_CAL_LDOHP_SHIFT 15 /**< Shift value for HFRCO_LDOHP */ -#define _HFRCO_CAL_LDOHP_MASK 0x8000UL /**< Bit mask for HFRCO_LDOHP */ -#define _HFRCO_CAL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_LDOHP_DEFAULT (_HFRCO_CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_FREQRANGE_SHIFT 16 /**< Shift value for HFRCO_FREQRANGE */ -#define _HFRCO_CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for HFRCO_FREQRANGE */ -#define _HFRCO_CAL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_FREQRANGE_DEFAULT (_HFRCO_CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_CMPBIAS_SHIFT 21 /**< Shift value for HFRCO_CMPBIAS */ -#define _HFRCO_CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for HFRCO_CMPBIAS */ -#define _HFRCO_CAL_CMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_CMPBIAS_DEFAULT (_HFRCO_CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_CLKDIV_SHIFT 24 /**< Shift value for HFRCO_CLKDIV */ -#define _HFRCO_CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for HFRCO_CLKDIV */ -#define _HFRCO_CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for HFRCO_CAL */ -#define _HFRCO_CAL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for HFRCO_CAL */ -#define _HFRCO_CAL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for HFRCO_CAL */ -#define HFRCO_CAL_CLKDIV_DEFAULT (_HFRCO_CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_CLKDIV_DIV1 (_HFRCO_CAL_CLKDIV_DIV1 << 24) /**< Shifted mode DIV1 for HFRCO_CAL */ -#define HFRCO_CAL_CLKDIV_DIV2 (_HFRCO_CAL_CLKDIV_DIV2 << 24) /**< Shifted mode DIV2 for HFRCO_CAL */ -#define HFRCO_CAL_CLKDIV_DIV4 (_HFRCO_CAL_CLKDIV_DIV4 << 24) /**< Shifted mode DIV4 for HFRCO_CAL */ -#define _HFRCO_CAL_CMPSEL_SHIFT 26 /**< Shift value for HFRCO_CMPSEL */ -#define _HFRCO_CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for HFRCO_CMPSEL */ -#define _HFRCO_CAL_CMPSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_CMPSEL_DEFAULT (_HFRCO_CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_IREFTC_SHIFT 28 /**< Shift value for HFRCO_IREFTC */ -#define _HFRCO_CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for HFRCO_IREFTC */ -#define _HFRCO_CAL_IREFTC_DEFAULT 0x0000000AUL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_IREFTC_DEFAULT (_HFRCO_CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_RESETVALUE 0xA8689F7FUL /**< Default value for HFRCO_CAL */ +#define _HFRCO_CAL_MASK 0xFFFFBF7FUL /**< Mask for HFRCO_CAL */ +#define _HFRCO_CAL_TUNING_SHIFT 0 /**< Shift value for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_MASK 0x7FUL /**< Bit mask for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_TUNING_DEFAULT (_HFRCO_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FINETUNING_SHIFT 8 /**< Shift value for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FINETUNING_DEFAULT (_HFRCO_CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP (0x1UL << 15) /**< LDO High Power Mode */ +#define _HFRCO_CAL_LDOHP_SHIFT 15 /**< Shift value for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_MASK 0x8000UL /**< Bit mask for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP_DEFAULT (_HFRCO_CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FREQRANGE_SHIFT 16 /**< Shift value for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FREQRANGE_DEFAULT (_HFRCO_CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CMPBIAS_SHIFT 21 /**< Shift value for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPBIAS_DEFAULT (_HFRCO_CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_SHIFT 24 /**< Shift value for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DEFAULT (_HFRCO_CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV1 (_HFRCO_CAL_CLKDIV_DIV1 << 24) /**< Shifted mode DIV1 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV2 (_HFRCO_CAL_CLKDIV_DIV2 << 24) /**< Shifted mode DIV2 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV4 (_HFRCO_CAL_CLKDIV_DIV4 << 24) /**< Shifted mode DIV4 for HFRCO_CAL */ +#define _HFRCO_CAL_CMPSEL_SHIFT 26 /**< Shift value for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPSEL_DEFAULT (_HFRCO_CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_IREFTC_SHIFT 28 /**< Shift value for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_DEFAULT 0x0000000AUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_IREFTC_DEFAULT (_HFRCO_CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for HFRCO_CAL */ /* Bit fields for HFRCO STATUS */ -#define _HFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFRCO_STATUS */ -#define _HFRCO_STATUS_MASK 0x80010007UL /**< Mask for HFRCO_STATUS */ -#define HFRCO_STATUS_RDY (0x1UL << 0) /**< Ready */ -#define _HFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ -#define _HFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ -#define _HFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_RDY_DEFAULT (_HFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_FREQBSY (0x1UL << 1) /**< Frequency Updating Busy */ -#define _HFRCO_STATUS_FREQBSY_SHIFT 1 /**< Shift value for HFRCO_FREQBSY */ -#define _HFRCO_STATUS_FREQBSY_MASK 0x2UL /**< Bit mask for HFRCO_FREQBSY */ -#define _HFRCO_STATUS_FREQBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_FREQBSY_DEFAULT (_HFRCO_STATUS_FREQBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_SYNCBUSY (0x1UL << 2) /**< Synchronization Busy */ -#define _HFRCO_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for HFRCO_SYNCBUSY */ -#define _HFRCO_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for HFRCO_SYNCBUSY */ -#define _HFRCO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_SYNCBUSY_DEFAULT (_HFRCO_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ -#define _HFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for HFRCO_ENS */ -#define _HFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFRCO_ENS */ -#define _HFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_ENS_DEFAULT (_HFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ -#define _HFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFRCO_LOCK */ -#define _HFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFRCO_LOCK */ -#define _HFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define _HFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFRCO_STATUS */ -#define _HFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFRCO_STATUS */ -#define HFRCO_STATUS_LOCK_DEFAULT (_HFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_LOCK_UNLOCKED (_HFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFRCO_STATUS */ -#define HFRCO_STATUS_LOCK_LOCKED (_HFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFRCO_STATUS */ +#define _HFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFRCO_STATUS */ +#define _HFRCO_STATUS_MASK 0x80010007UL /**< Mask for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY (0x1UL << 0) /**< Ready */ +#define _HFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY_DEFAULT (_HFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY (0x1UL << 1) /**< Frequency Updating Busy */ +#define _HFRCO_STATUS_FREQBSY_SHIFT 1 /**< Shift value for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_MASK 0x2UL /**< Bit mask for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY_DEFAULT (_HFRCO_STATUS_FREQBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY (0x1UL << 2) /**< Synchronization Busy */ +#define _HFRCO_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY_DEFAULT (_HFRCO_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _HFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS_DEFAULT (_HFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _HFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_DEFAULT (_HFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_UNLOCKED (_HFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_LOCKED (_HFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFRCO_STATUS */ /* Bit fields for HFRCO IF */ -#define _HFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IF */ -#define _HFRCO_IF_MASK 0x00000001UL /**< Mask for HFRCO_IF */ -#define HFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ -#define _HFRCO_IF_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ -#define _HFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ -#define _HFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IF */ -#define HFRCO_IF_RDY_DEFAULT (_HFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IF */ +#define _HFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IF */ +#define _HFRCO_IF_MASK 0x00000001UL /**< Mask for HFRCO_IF */ +#define HFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _HFRCO_IF_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IF */ +#define HFRCO_IF_RDY_DEFAULT (_HFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IF */ /* Bit fields for HFRCO IEN */ -#define _HFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IEN */ -#define _HFRCO_IEN_MASK 0x00000001UL /**< Mask for HFRCO_IEN */ -#define HFRCO_IEN_RDY (0x1UL << 0) /**< RDY Interrupt Enable */ -#define _HFRCO_IEN_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ -#define _HFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ -#define _HFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IEN */ -#define HFRCO_IEN_RDY_DEFAULT (_HFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IEN */ +#define _HFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IEN */ +#define _HFRCO_IEN_MASK 0x00000001UL /**< Mask for HFRCO_IEN */ +#define HFRCO_IEN_RDY (0x1UL << 0) /**< RDY Interrupt Enable */ +#define _HFRCO_IEN_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IEN */ +#define HFRCO_IEN_RDY_DEFAULT (_HFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IEN */ /* Bit fields for HFRCO LOCK */ -#define _HFRCO_LOCK_RESETVALUE 0x00008195UL /**< Default value for HFRCO_LOCK */ -#define _HFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFRCO_LOCK */ -#define _HFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFRCO_LOCKKEY */ -#define _HFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFRCO_LOCKKEY */ -#define _HFRCO_LOCK_LOCKKEY_DEFAULT 0x00008195UL /**< Mode DEFAULT for HFRCO_LOCK */ -#define _HFRCO_LOCK_LOCKKEY_UNLOCK 0x00008195UL /**< Mode UNLOCK for HFRCO_LOCK */ -#define HFRCO_LOCK_LOCKKEY_DEFAULT (_HFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_LOCK */ -#define HFRCO_LOCK_LOCKKEY_UNLOCK (_HFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFRCO_LOCK */ +#define _HFRCO_LOCK_RESETVALUE 0x00008195UL /**< Default value for HFRCO_LOCK */ +#define _HFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_DEFAULT 0x00008195UL /**< Mode DEFAULT for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_UNLOCK 0x00008195UL /**< Mode UNLOCK for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_DEFAULT (_HFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_UNLOCK (_HFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFRCO_LOCK */ /** @} End of group EFR32SG28_HFRCO_BitFields */ /** @} End of group EFR32SG28_HFRCO */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_hfxo.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_hfxo.h index abd3a88d70..8082460d2e 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_hfxo.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_HFXO_H #define EFR32SG28_HFXO_H - #define HFXO_HAS_SET_CLEAR /**************************************************************************//** @@ -43,95 +42,94 @@ *****************************************************************************/ /** HFXO Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version ID */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - __IOM uint32_t XTALCFG; /**< Crystal Configuration Register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t XTALCTRL; /**< Crystal Control Register */ - __IOM uint32_t XTALCTRL1; /**< BUFOUT Crystal Control Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IOM uint32_t CTRL; /**< Control Register */ - uint32_t RESERVED3[5U]; /**< Reserved for future use */ - __IOM uint32_t BUFOUTTRIM; /**< BUFOUT Trim Configuration Register */ - __IOM uint32_t BUFOUTCTRL; /**< BUFOUT Control Register */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t CMD; /**< Command Register */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - uint32_t RESERVED6[5U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED7[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - uint32_t RESERVED8[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - uint32_t RESERVED9[3U]; /**< Reserved for future use */ - __IOM uint32_t XTALCFG_SET; /**< Crystal Configuration Register */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - __IOM uint32_t XTALCTRL_SET; /**< Crystal Control Register */ - __IOM uint32_t XTALCTRL1_SET; /**< BUFOUT Crystal Control Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - uint32_t RESERVED11[1U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - uint32_t RESERVED12[5U]; /**< Reserved for future use */ - __IOM uint32_t BUFOUTTRIM_SET; /**< BUFOUT Trim Configuration Register */ - __IOM uint32_t BUFOUTCTRL_SET; /**< BUFOUT Control Register */ - uint32_t RESERVED13[2U]; /**< Reserved for future use */ - __IOM uint32_t CMD_SET; /**< Command Register */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - uint32_t RESERVED15[5U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED16[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - uint32_t RESERVED17[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - uint32_t RESERVED18[3U]; /**< Reserved for future use */ - __IOM uint32_t XTALCFG_CLR; /**< Crystal Configuration Register */ - uint32_t RESERVED19[1U]; /**< Reserved for future use */ - __IOM uint32_t XTALCTRL_CLR; /**< Crystal Control Register */ - __IOM uint32_t XTALCTRL1_CLR; /**< BUFOUT Crystal Control Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - uint32_t RESERVED20[1U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - uint32_t RESERVED21[5U]; /**< Reserved for future use */ - __IOM uint32_t BUFOUTTRIM_CLR; /**< BUFOUT Trim Configuration Register */ - __IOM uint32_t BUFOUTCTRL_CLR; /**< BUFOUT Control Register */ - uint32_t RESERVED22[2U]; /**< Reserved for future use */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - uint32_t RESERVED23[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - uint32_t RESERVED24[5U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED25[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - uint32_t RESERVED26[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - uint32_t RESERVED27[3U]; /**< Reserved for future use */ - __IOM uint32_t XTALCFG_TGL; /**< Crystal Configuration Register */ - uint32_t RESERVED28[1U]; /**< Reserved for future use */ - __IOM uint32_t XTALCTRL_TGL; /**< Crystal Control Register */ - __IOM uint32_t XTALCTRL1_TGL; /**< BUFOUT Crystal Control Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - uint32_t RESERVED29[1U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - uint32_t RESERVED30[5U]; /**< Reserved for future use */ - __IOM uint32_t BUFOUTTRIM_TGL; /**< BUFOUT Trim Configuration Register */ - __IOM uint32_t BUFOUTCTRL_TGL; /**< BUFOUT Control Register */ - uint32_t RESERVED31[2U]; /**< Reserved for future use */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - uint32_t RESERVED32[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - uint32_t RESERVED33[5U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED34[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG; /**< Crystal Configuration Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Control Register */ + uint32_t RESERVED3[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL; /**< BUFOUT Control Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED6[5U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED8[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED9[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_SET; /**< Crystal Configuration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_SET; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_SET; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + uint32_t RESERVED12[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_SET; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_SET; /**< BUFOUT Control Register */ + uint32_t RESERVED13[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED15[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED17[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_CLR; /**< Crystal Configuration Register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_CLR; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_CLR; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + uint32_t RESERVED21[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_CLR; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_CLR; /**< BUFOUT Control Register */ + uint32_t RESERVED22[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED24[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED25[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED26[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_TGL; /**< Crystal Configuration Register */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_TGL; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_TGL; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + uint32_t RESERVED30[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_TGL; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_TGL; /**< BUFOUT Control Register */ + uint32_t RESERVED31[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED33[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED34[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ } HFXO_TypeDef; /** @} End of group EFR32SG28_HFXO */ @@ -143,658 +141,658 @@ typedef struct *****************************************************************************/ /* Bit fields for HFXO IPVERSION */ -#define _HFXO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for HFXO_IPVERSION */ -#define _HFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFXO_IPVERSION */ -#define _HFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFXO_IPVERSION */ -#define _HFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFXO_IPVERSION */ -#define _HFXO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_IPVERSION */ -#define HFXO_IPVERSION_IPVERSION_DEFAULT (_HFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_IPVERSION */ +#define HFXO_IPVERSION_IPVERSION_DEFAULT (_HFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IPVERSION */ /* Bit fields for HFXO XTALCFG */ -#define _HFXO_XTALCFG_RESETVALUE 0x0BB00820UL /**< Default value for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_MASK 0x0FFFFFFFUL /**< Mask for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT 0 /**< Shift value for HFXO_COREBIASSTARTUPI */ -#define _HFXO_XTALCFG_COREBIASSTARTUPI_MASK 0x3FUL /**< Bit mask for HFXO_COREBIASSTARTUPI */ -#define _HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT 6 /**< Shift value for HFXO_COREBIASSTARTUP */ -#define _HFXO_XTALCFG_COREBIASSTARTUP_MASK 0xFC0UL /**< Bit mask for HFXO_COREBIASSTARTUP */ -#define _HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT 12 /**< Shift value for HFXO_CTUNEXISTARTUP */ -#define _HFXO_XTALCFG_CTUNEXISTARTUP_MASK 0xF000UL /**< Bit mask for HFXO_CTUNEXISTARTUP */ -#define _HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT 16 /**< Shift value for HFXO_CTUNEXOSTARTUP */ -#define _HFXO_XTALCFG_CTUNEXOSTARTUP_MASK 0xF0000UL /**< Bit mask for HFXO_CTUNEXOSTARTUP */ -#define _HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTEADY */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTEADY */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4US 0x00000000UL /**< Mode T4US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T16US 0x00000001UL /**< Mode T16US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T83US 0x00000003UL /**< Mode T83US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T125US 0x00000004UL /**< Mode T125US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T166US 0x00000005UL /**< Mode T166US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T208US 0x00000006UL /**< Mode T208US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T250US 0x00000007UL /**< Mode T250US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T333US 0x00000008UL /**< Mode T333US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T416US 0x00000009UL /**< Mode T416US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T500US 0x0000000AUL /**< Mode T500US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T666US 0x0000000BUL /**< Mode T666US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US 0x0000000DUL /**< Mode T1666US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US 0x0000000EUL /**< Mode T2500US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US 0x0000000FUL /**< Mode T4166US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT (_HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T4US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4US << 20) /**< Shifted mode T4US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T16US (_HFXO_XTALCFG_TIMEOUTSTEADY_T16US << 20) /**< Shifted mode T16US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T41US (_HFXO_XTALCFG_TIMEOUTSTEADY_T41US << 20) /**< Shifted mode T41US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T83US (_HFXO_XTALCFG_TIMEOUTSTEADY_T83US << 20) /**< Shifted mode T83US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T125US (_HFXO_XTALCFG_TIMEOUTSTEADY_T125US << 20) /**< Shifted mode T125US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T166US << 20) /**< Shifted mode T166US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T208US (_HFXO_XTALCFG_TIMEOUTSTEADY_T208US << 20) /**< Shifted mode T208US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T250US (_HFXO_XTALCFG_TIMEOUTSTEADY_T250US << 20) /**< Shifted mode T250US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T333US (_HFXO_XTALCFG_TIMEOUTSTEADY_T333US << 20) /**< Shifted mode T333US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T416US (_HFXO_XTALCFG_TIMEOUTSTEADY_T416US << 20) /**< Shifted mode T416US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T500US << 20) /**< Shifted mode T500US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T666US << 20) /**< Shifted mode T666US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T833US (_HFXO_XTALCFG_TIMEOUTSTEADY_T833US << 20) /**< Shifted mode T833US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T1666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T1666US << 20) /**< Shifted mode T1666US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T2500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T2500US << 20) /**< Shifted mode T2500US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T4166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4166US << 20) /**< Shifted mode T4166US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT 24 /**< Shift value for HFXO_TIMEOUTCBLSB */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_MASK 0xF000000UL /**< Bit mask for HFXO_TIMEOUTCBLSB */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T8US 0x00000000UL /**< Mode T8US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T20US 0x00000001UL /**< Mode T20US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T62US 0x00000003UL /**< Mode T62US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T83US 0x00000004UL /**< Mode T83US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T104US 0x00000005UL /**< Mode T104US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T125US 0x00000006UL /**< Mode T125US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T166US 0x00000007UL /**< Mode T166US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T208US 0x00000008UL /**< Mode T208US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T250US 0x00000009UL /**< Mode T250US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T333US 0x0000000AUL /**< Mode T333US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T416US 0x0000000BUL /**< Mode T416US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US 0x0000000DUL /**< Mode T1250US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US 0x0000000EUL /**< Mode T2083US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US 0x0000000FUL /**< Mode T3750US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT (_HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T8US (_HFXO_XTALCFG_TIMEOUTCBLSB_T8US << 24) /**< Shifted mode T8US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T20US (_HFXO_XTALCFG_TIMEOUTCBLSB_T20US << 24) /**< Shifted mode T20US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T41US (_HFXO_XTALCFG_TIMEOUTCBLSB_T41US << 24) /**< Shifted mode T41US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T62US (_HFXO_XTALCFG_TIMEOUTCBLSB_T62US << 24) /**< Shifted mode T62US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T83US (_HFXO_XTALCFG_TIMEOUTCBLSB_T83US << 24) /**< Shifted mode T83US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T104US (_HFXO_XTALCFG_TIMEOUTCBLSB_T104US << 24) /**< Shifted mode T104US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T125US (_HFXO_XTALCFG_TIMEOUTCBLSB_T125US << 24) /**< Shifted mode T125US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T166US (_HFXO_XTALCFG_TIMEOUTCBLSB_T166US << 24) /**< Shifted mode T166US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T208US (_HFXO_XTALCFG_TIMEOUTCBLSB_T208US << 24) /**< Shifted mode T208US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T250US << 24) /**< Shifted mode T250US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T333US (_HFXO_XTALCFG_TIMEOUTCBLSB_T333US << 24) /**< Shifted mode T333US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T416US (_HFXO_XTALCFG_TIMEOUTCBLSB_T416US << 24) /**< Shifted mode T416US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T833US (_HFXO_XTALCFG_TIMEOUTCBLSB_T833US << 24) /**< Shifted mode T833US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T1250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T1250US << 24) /**< Shifted mode T1250US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T2083US (_HFXO_XTALCFG_TIMEOUTCBLSB_T2083US << 24) /**< Shifted mode T2083US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T3750US (_HFXO_XTALCFG_TIMEOUTCBLSB_T3750US << 24) /**< Shifted mode T3750US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_RESETVALUE 0x0BB00820UL /**< Default value for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_MASK 0x0FFFFFFFUL /**< Mask for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT 0 /**< Shift value for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_MASK 0x3FUL /**< Bit mask for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT 6 /**< Shift value for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_MASK 0xFC0UL /**< Bit mask for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT 12 /**< Shift value for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_MASK 0xF000UL /**< Bit mask for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT 16 /**< Shift value for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_MASK 0xF0000UL /**< Bit mask for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4US 0x00000000UL /**< Mode T4US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T16US 0x00000001UL /**< Mode T16US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T83US 0x00000003UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T125US 0x00000004UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T166US 0x00000005UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T208US 0x00000006UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T250US 0x00000007UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T333US 0x00000008UL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T416US 0x00000009UL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T500US 0x0000000AUL /**< Mode T500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T666US 0x0000000BUL /**< Mode T666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US 0x0000000DUL /**< Mode T1666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US 0x0000000EUL /**< Mode T2500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US 0x0000000FUL /**< Mode T4166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT (_HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T4US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4US << 20) /**< Shifted mode T4US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T16US (_HFXO_XTALCFG_TIMEOUTSTEADY_T16US << 20) /**< Shifted mode T16US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T41US (_HFXO_XTALCFG_TIMEOUTSTEADY_T41US << 20) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T83US (_HFXO_XTALCFG_TIMEOUTSTEADY_T83US << 20) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T125US (_HFXO_XTALCFG_TIMEOUTSTEADY_T125US << 20) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T166US << 20) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T208US (_HFXO_XTALCFG_TIMEOUTSTEADY_T208US << 20) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T250US (_HFXO_XTALCFG_TIMEOUTSTEADY_T250US << 20) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T333US (_HFXO_XTALCFG_TIMEOUTSTEADY_T333US << 20) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T416US (_HFXO_XTALCFG_TIMEOUTSTEADY_T416US << 20) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T500US << 20) /**< Shifted mode T500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T666US << 20) /**< Shifted mode T666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T833US (_HFXO_XTALCFG_TIMEOUTSTEADY_T833US << 20) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T1666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T1666US << 20) /**< Shifted mode T1666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T2500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T2500US << 20) /**< Shifted mode T2500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T4166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4166US << 20) /**< Shifted mode T4166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT 24 /**< Shift value for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_MASK 0xF000000UL /**< Bit mask for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T8US 0x00000000UL /**< Mode T8US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T20US 0x00000001UL /**< Mode T20US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T62US 0x00000003UL /**< Mode T62US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T83US 0x00000004UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T104US 0x00000005UL /**< Mode T104US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T125US 0x00000006UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T166US 0x00000007UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T208US 0x00000008UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T250US 0x00000009UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T333US 0x0000000AUL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T416US 0x0000000BUL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US 0x0000000DUL /**< Mode T1250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US 0x0000000EUL /**< Mode T2083US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US 0x0000000FUL /**< Mode T3750US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT (_HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T8US (_HFXO_XTALCFG_TIMEOUTCBLSB_T8US << 24) /**< Shifted mode T8US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T20US (_HFXO_XTALCFG_TIMEOUTCBLSB_T20US << 24) /**< Shifted mode T20US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T41US (_HFXO_XTALCFG_TIMEOUTCBLSB_T41US << 24) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T62US (_HFXO_XTALCFG_TIMEOUTCBLSB_T62US << 24) /**< Shifted mode T62US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T83US (_HFXO_XTALCFG_TIMEOUTCBLSB_T83US << 24) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T104US (_HFXO_XTALCFG_TIMEOUTCBLSB_T104US << 24) /**< Shifted mode T104US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T125US (_HFXO_XTALCFG_TIMEOUTCBLSB_T125US << 24) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T166US (_HFXO_XTALCFG_TIMEOUTCBLSB_T166US << 24) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T208US (_HFXO_XTALCFG_TIMEOUTCBLSB_T208US << 24) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T250US << 24) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T333US (_HFXO_XTALCFG_TIMEOUTCBLSB_T333US << 24) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T416US (_HFXO_XTALCFG_TIMEOUTCBLSB_T416US << 24) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T833US (_HFXO_XTALCFG_TIMEOUTCBLSB_T833US << 24) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T1250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T1250US << 24) /**< Shifted mode T1250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T2083US (_HFXO_XTALCFG_TIMEOUTCBLSB_T2083US << 24) /**< Shifted mode T2083US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T3750US (_HFXO_XTALCFG_TIMEOUTCBLSB_T3750US << 24) /**< Shifted mode T3750US for HFXO_XTALCFG */ /* Bit fields for HFXO XTALCTRL */ -#define _HFXO_XTALCTRL_RESETVALUE 0x033C3C3CUL /**< Default value for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_MASK 0x8FFFFFFFUL /**< Mask for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREBIASANA_SHIFT 0 /**< Shift value for HFXO_COREBIASANA */ -#define _HFXO_XTALCTRL_COREBIASANA_MASK 0xFFUL /**< Bit mask for HFXO_COREBIASANA */ -#define _HFXO_XTALCTRL_COREBIASANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREBIASANA_DEFAULT (_HFXO_XTALCTRL_COREBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEXIANA_SHIFT 8 /**< Shift value for HFXO_CTUNEXIANA */ -#define _HFXO_XTALCTRL_CTUNEXIANA_MASK 0xFF00UL /**< Bit mask for HFXO_CTUNEXIANA */ -#define _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEXIANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEXOANA_SHIFT 16 /**< Shift value for HFXO_CTUNEXOANA */ -#define _HFXO_XTALCTRL_CTUNEXOANA_MASK 0xFF0000UL /**< Bit mask for HFXO_CTUNEXOANA */ -#define _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEXOANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT 24 /**< Shift value for HFXO_CTUNEFIXANA */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_MASK 0x3000000UL /**< Bit mask for HFXO_CTUNEFIXANA */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_XI 0x00000001UL /**< Mode XI for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_XO 0x00000002UL /**< Mode XO for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_BOTH 0x00000003UL /**< Mode BOTH for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT (_HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_NONE (_HFXO_XTALCTRL_CTUNEFIXANA_NONE << 24) /**< Shifted mode NONE for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_XI (_HFXO_XTALCTRL_CTUNEFIXANA_XI << 24) /**< Shifted mode XI for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_XO (_HFXO_XTALCTRL_CTUNEFIXANA_XO << 24) /**< Shifted mode XO for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_BOTH (_HFXO_XTALCTRL_CTUNEFIXANA_BOTH << 24) /**< Shifted mode BOTH for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_SHIFT 26 /**< Shift value for HFXO_COREDGENANA */ -#define _HFXO_XTALCTRL_COREDGENANA_MASK 0xC000000UL /**< Bit mask for HFXO_COREDGENANA */ -#define _HFXO_XTALCTRL_COREDGENANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_DGEN33 0x00000001UL /**< Mode DGEN33 for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_DGEN50 0x00000002UL /**< Mode DGEN50 for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_DGEN100 0x00000003UL /**< Mode DGEN100 for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_DEFAULT (_HFXO_XTALCTRL_COREDGENANA_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_NONE (_HFXO_XTALCTRL_COREDGENANA_NONE << 26) /**< Shifted mode NONE for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_DGEN33 (_HFXO_XTALCTRL_COREDGENANA_DGEN33 << 26) /**< Shifted mode DGEN33 for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_DGEN50 (_HFXO_XTALCTRL_COREDGENANA_DGEN50 << 26) /**< Shifted mode DGEN50 for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_DGEN100 (_HFXO_XTALCTRL_COREDGENANA_DGEN100 << 26) /**< Shifted mode DGEN100 for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_SKIPCOREBIASOPT (0x1UL << 31) /**< Skip Core Bias Optimization */ -#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_SHIFT 31 /**< Shift value for HFXO_SKIPCOREBIASOPT */ -#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK 0x80000000UL /**< Bit mask for HFXO_SKIPCOREBIASOPT */ -#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT (_HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_RESETVALUE 0x033C3C3CUL /**< Default value for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_MASK 0x8FFFFFFFUL /**< Mask for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREBIASANA_SHIFT 0 /**< Shift value for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_MASK 0xFFUL /**< Bit mask for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREBIASANA_DEFAULT (_HFXO_XTALCTRL_COREBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXIANA_SHIFT 8 /**< Shift value for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_MASK 0xFF00UL /**< Bit mask for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXIANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXOANA_SHIFT 16 /**< Shift value for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_MASK 0xFF0000UL /**< Bit mask for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXOANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT 24 /**< Shift value for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_MASK 0x3000000UL /**< Bit mask for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XI 0x00000001UL /**< Mode XI for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XO 0x00000002UL /**< Mode XO for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_BOTH 0x00000003UL /**< Mode BOTH for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT (_HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_NONE (_HFXO_XTALCTRL_CTUNEFIXANA_NONE << 24) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XI (_HFXO_XTALCTRL_CTUNEFIXANA_XI << 24) /**< Shifted mode XI for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XO (_HFXO_XTALCTRL_CTUNEFIXANA_XO << 24) /**< Shifted mode XO for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_BOTH (_HFXO_XTALCTRL_CTUNEFIXANA_BOTH << 24) /**< Shifted mode BOTH for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_SHIFT 26 /**< Shift value for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_MASK 0xC000000UL /**< Bit mask for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN33 0x00000001UL /**< Mode DGEN33 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN50 0x00000002UL /**< Mode DGEN50 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN100 0x00000003UL /**< Mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DEFAULT (_HFXO_XTALCTRL_COREDGENANA_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_NONE (_HFXO_XTALCTRL_COREDGENANA_NONE << 26) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN33 (_HFXO_XTALCTRL_COREDGENANA_DGEN33 << 26) /**< Shifted mode DGEN33 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN50 (_HFXO_XTALCTRL_COREDGENANA_DGEN50 << 26) /**< Shifted mode DGEN50 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN100 (_HFXO_XTALCTRL_COREDGENANA_DGEN100 << 26) /**< Shifted mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT (0x1UL << 31) /**< Skip Core Bias Optimization */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_SHIFT 31 /**< Shift value for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK 0x80000000UL /**< Bit mask for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT (_HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ /* Bit fields for HFXO XTALCTRL1 */ -#define _HFXO_XTALCTRL1_RESETVALUE 0x0000003CUL /**< Default value for HFXO_XTALCTRL1 */ -#define _HFXO_XTALCTRL1_MASK 0x000000FFUL /**< Mask for HFXO_XTALCTRL1 */ -#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_SHIFT 0 /**< Shift value for HFXO_CTUNEXIBUFOUTANA */ -#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_MASK 0xFFUL /**< Bit mask for HFXO_CTUNEXIBUFOUTANA */ -#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL1 */ -#define HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT (_HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL1 */ +#define _HFXO_XTALCTRL1_RESETVALUE 0x0000003CUL /**< Default value for HFXO_XTALCTRL1 */ +#define _HFXO_XTALCTRL1_MASK 0x000000FFUL /**< Mask for HFXO_XTALCTRL1 */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_SHIFT 0 /**< Shift value for HFXO_CTUNEXIBUFOUTANA */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_MASK 0xFFUL /**< Bit mask for HFXO_CTUNEXIBUFOUTANA */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL1 */ +#define HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT (_HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL1 */ /* Bit fields for HFXO CFG */ -#define _HFXO_CFG_RESETVALUE 0x10000000UL /**< Default value for HFXO_CFG */ -#define _HFXO_CFG_MASK 0xB000000FUL /**< Mask for HFXO_CFG */ -#define _HFXO_CFG_MODE_SHIFT 0 /**< Shift value for HFXO_MODE */ -#define _HFXO_CFG_MODE_MASK 0x3UL /**< Bit mask for HFXO_MODE */ -#define _HFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ -#define _HFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for HFXO_CFG */ -#define _HFXO_CFG_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for HFXO_CFG */ -#define _HFXO_CFG_MODE_EXTCLKPKDET 0x00000002UL /**< Mode EXTCLKPKDET for HFXO_CFG */ -#define HFXO_CFG_MODE_DEFAULT (_HFXO_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_MODE_XTAL (_HFXO_CFG_MODE_XTAL << 0) /**< Shifted mode XTAL for HFXO_CFG */ -#define HFXO_CFG_MODE_EXTCLK (_HFXO_CFG_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for HFXO_CFG */ -#define HFXO_CFG_MODE_EXTCLKPKDET (_HFXO_CFG_MODE_EXTCLKPKDET << 0) /**< Shifted mode EXTCLKPKDET for HFXO_CFG */ -#define HFXO_CFG_ENXIDCBIASANA (0x1UL << 2) /**< Enable XI Internal DC Bias */ -#define _HFXO_CFG_ENXIDCBIASANA_SHIFT 2 /**< Shift value for HFXO_ENXIDCBIASANA */ -#define _HFXO_CFG_ENXIDCBIASANA_MASK 0x4UL /**< Bit mask for HFXO_ENXIDCBIASANA */ -#define _HFXO_CFG_ENXIDCBIASANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_ENXIDCBIASANA_DEFAULT (_HFXO_CFG_ENXIDCBIASANA_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_SQBUFSCHTRGANA (0x1UL << 3) /**< Squaring Buffer Schmitt Trigger */ -#define _HFXO_CFG_SQBUFSCHTRGANA_SHIFT 3 /**< Shift value for HFXO_SQBUFSCHTRGANA */ -#define _HFXO_CFG_SQBUFSCHTRGANA_MASK 0x8UL /**< Bit mask for HFXO_SQBUFSCHTRGANA */ -#define _HFXO_CFG_SQBUFSCHTRGANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ -#define _HFXO_CFG_SQBUFSCHTRGANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CFG */ -#define _HFXO_CFG_SQBUFSCHTRGANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CFG */ -#define HFXO_CFG_SQBUFSCHTRGANA_DEFAULT (_HFXO_CFG_SQBUFSCHTRGANA_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_SQBUFSCHTRGANA_DISABLE (_HFXO_CFG_SQBUFSCHTRGANA_DISABLE << 3) /**< Shifted mode DISABLE for HFXO_CFG */ -#define HFXO_CFG_SQBUFSCHTRGANA_ENABLE (_HFXO_CFG_SQBUFSCHTRGANA_ENABLE << 3) /**< Shifted mode ENABLE for HFXO_CFG */ -#define HFXO_CFG_FORCELFTIMEOUT (0x1UL << 28) /**< Force Low Frequency Timeout */ -#define _HFXO_CFG_FORCELFTIMEOUT_SHIFT 28 /**< Shift value for HFXO_FORCELFTIMEOUT */ -#define _HFXO_CFG_FORCELFTIMEOUT_MASK 0x10000000UL /**< Bit mask for HFXO_FORCELFTIMEOUT */ -#define _HFXO_CFG_FORCELFTIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_FORCELFTIMEOUT_DEFAULT (_HFXO_CFG_FORCELFTIMEOUT_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_RESETVALUE 0x10000000UL /**< Default value for HFXO_CFG */ +#define _HFXO_CFG_MASK 0xB000000FUL /**< Mask for HFXO_CFG */ +#define _HFXO_CFG_MODE_SHIFT 0 /**< Shift value for HFXO_MODE */ +#define _HFXO_CFG_MODE_MASK 0x3UL /**< Bit mask for HFXO_MODE */ +#define _HFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for HFXO_CFG */ +#define _HFXO_CFG_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for HFXO_CFG */ +#define _HFXO_CFG_MODE_EXTCLKPKDET 0x00000002UL /**< Mode EXTCLKPKDET for HFXO_CFG */ +#define HFXO_CFG_MODE_DEFAULT (_HFXO_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_MODE_XTAL (_HFXO_CFG_MODE_XTAL << 0) /**< Shifted mode XTAL for HFXO_CFG */ +#define HFXO_CFG_MODE_EXTCLK (_HFXO_CFG_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for HFXO_CFG */ +#define HFXO_CFG_MODE_EXTCLKPKDET (_HFXO_CFG_MODE_EXTCLKPKDET << 0) /**< Shifted mode EXTCLKPKDET for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA (0x1UL << 2) /**< Enable XI Internal DC Bias */ +#define _HFXO_CFG_ENXIDCBIASANA_SHIFT 2 /**< Shift value for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_MASK 0x4UL /**< Bit mask for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA_DEFAULT (_HFXO_CFG_ENXIDCBIASANA_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA (0x1UL << 3) /**< Squaring Buffer Schmitt Trigger */ +#define _HFXO_CFG_SQBUFSCHTRGANA_SHIFT 3 /**< Shift value for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_MASK 0x8UL /**< Bit mask for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DEFAULT (_HFXO_CFG_SQBUFSCHTRGANA_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DISABLE (_HFXO_CFG_SQBUFSCHTRGANA_DISABLE << 3) /**< Shifted mode DISABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_ENABLE (_HFXO_CFG_SQBUFSCHTRGANA_ENABLE << 3) /**< Shifted mode ENABLE for HFXO_CFG */ +#define HFXO_CFG_FORCELFTIMEOUT (0x1UL << 28) /**< Force Low Frequency Timeout */ +#define _HFXO_CFG_FORCELFTIMEOUT_SHIFT 28 /**< Shift value for HFXO_FORCELFTIMEOUT */ +#define _HFXO_CFG_FORCELFTIMEOUT_MASK 0x10000000UL /**< Bit mask for HFXO_FORCELFTIMEOUT */ +#define _HFXO_CFG_FORCELFTIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_FORCELFTIMEOUT_DEFAULT (_HFXO_CFG_FORCELFTIMEOUT_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_CFG */ /* Bit fields for HFXO CTRL */ -#define _HFXO_CTRL_RESETVALUE 0x07000040UL /**< Default value for HFXO_CTRL */ -#define _HFXO_CTRL_MASK 0x8707FF7DUL /**< Mask for HFXO_CTRL */ -#define HFXO_CTRL_BUFOUTFREEZE (0x1UL << 0) /**< Freeze BUFOUT Controls */ -#define _HFXO_CTRL_BUFOUTFREEZE_SHIFT 0 /**< Shift value for HFXO_BUFOUTFREEZE */ -#define _HFXO_CTRL_BUFOUTFREEZE_MASK 0x1UL /**< Bit mask for HFXO_BUFOUTFREEZE */ -#define _HFXO_CTRL_BUFOUTFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_BUFOUTFREEZE_DEFAULT (_HFXO_CTRL_BUFOUTFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_KEEPWARM (0x1UL << 2) /**< Keep Warm */ -#define _HFXO_CTRL_KEEPWARM_SHIFT 2 /**< Shift value for HFXO_KEEPWARM */ -#define _HFXO_CTRL_KEEPWARM_MASK 0x4UL /**< Bit mask for HFXO_KEEPWARM */ -#define _HFXO_CTRL_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_KEEPWARM_DEFAULT (_HFXO_CTRL_KEEPWARM_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_EM23ONDEMAND (0x1UL << 3) /**< On-demand During EM23 */ -#define _HFXO_CTRL_EM23ONDEMAND_SHIFT 3 /**< Shift value for HFXO_EM23ONDEMAND */ -#define _HFXO_CTRL_EM23ONDEMAND_MASK 0x8UL /**< Bit mask for HFXO_EM23ONDEMAND */ -#define _HFXO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_EM23ONDEMAND_DEFAULT (_HFXO_CTRL_EM23ONDEMAND_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXI2GNDANA (0x1UL << 4) /**< Force XI Pin to Ground */ -#define _HFXO_CTRL_FORCEXI2GNDANA_SHIFT 4 /**< Shift value for HFXO_FORCEXI2GNDANA */ -#define _HFXO_CTRL_FORCEXI2GNDANA_MASK 0x10UL /**< Bit mask for HFXO_FORCEXI2GNDANA */ -#define _HFXO_CTRL_FORCEXI2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define _HFXO_CTRL_FORCEXI2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ -#define _HFXO_CTRL_FORCEXI2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXI2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXI2GNDANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXI2GNDANA_DISABLE (_HFXO_CTRL_FORCEXI2GNDANA_DISABLE << 4) /**< Shifted mode DISABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXI2GNDANA_ENABLE (_HFXO_CTRL_FORCEXI2GNDANA_ENABLE << 4) /**< Shifted mode ENABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXO2GNDANA (0x1UL << 5) /**< Force XO Pin to Ground */ -#define _HFXO_CTRL_FORCEXO2GNDANA_SHIFT 5 /**< Shift value for HFXO_FORCEXO2GNDANA */ -#define _HFXO_CTRL_FORCEXO2GNDANA_MASK 0x20UL /**< Bit mask for HFXO_FORCEXO2GNDANA */ -#define _HFXO_CTRL_FORCEXO2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define _HFXO_CTRL_FORCEXO2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ -#define _HFXO_CTRL_FORCEXO2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXO2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXO2GNDANA_DEFAULT << 5) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXO2GNDANA_DISABLE (_HFXO_CTRL_FORCEXO2GNDANA_DISABLE << 5) /**< Shifted mode DISABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXO2GNDANA_ENABLE (_HFXO_CTRL_FORCEXO2GNDANA_ENABLE << 5) /**< Shifted mode ENABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCECTUNEMAX (0x1UL << 6) /**< Force Tuning Cap to Max Value */ -#define _HFXO_CTRL_FORCECTUNEMAX_SHIFT 6 /**< Shift value for HFXO_FORCECTUNEMAX */ -#define _HFXO_CTRL_FORCECTUNEMAX_MASK 0x40UL /**< Bit mask for HFXO_FORCECTUNEMAX */ -#define _HFXO_CTRL_FORCECTUNEMAX_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCECTUNEMAX_DEFAULT (_HFXO_CTRL_FORCECTUNEMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_SHIFT 8 /**< Shift value for HFXO_PRSSTATUSSEL0 */ -#define _HFXO_CTRL_PRSSTATUSSEL0_MASK 0xF00UL /**< Bit mask for HFXO_PRSSTATUSSEL0 */ -#define _HFXO_CTRL_PRSSTATUSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL0_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_DISABLED (_HFXO_CTRL_PRSSTATUSSEL0_DISABLED << 8) /**< Shifted mode DISABLED for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_ENS (_HFXO_CTRL_PRSSTATUSSEL0_ENS << 8) /**< Shifted mode ENS for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY << 8) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_RDY (_HFXO_CTRL_PRSSTATUSSEL0_RDY << 8) /**< Shifted mode RDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL0_PRSRDY << 8) /**< Shifted mode PRSRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY << 8) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_HWREQ (_HFXO_CTRL_PRSSTATUSSEL0_HWREQ << 8) /**< Shifted mode HWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ << 8) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ << 8) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_SHIFT 12 /**< Shift value for HFXO_PRSSTATUSSEL1 */ -#define _HFXO_CTRL_PRSSTATUSSEL1_MASK 0xF000UL /**< Bit mask for HFXO_PRSSTATUSSEL1 */ -#define _HFXO_CTRL_PRSSTATUSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL1_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_DISABLED (_HFXO_CTRL_PRSSTATUSSEL1_DISABLED << 12) /**< Shifted mode DISABLED for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_ENS (_HFXO_CTRL_PRSSTATUSSEL1_ENS << 12) /**< Shifted mode ENS for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY << 12) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_RDY (_HFXO_CTRL_PRSSTATUSSEL1_RDY << 12) /**< Shifted mode RDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL1_PRSRDY << 12) /**< Shifted mode PRSRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY << 12) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_HWREQ (_HFXO_CTRL_PRSSTATUSSEL1_HWREQ << 12) /**< Shifted mode HWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ << 12) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ << 12) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ -#define HFXO_CTRL_FORCEEN (0x1UL << 16) /**< Force Digital Clock Request */ -#define _HFXO_CTRL_FORCEEN_SHIFT 16 /**< Shift value for HFXO_FORCEEN */ -#define _HFXO_CTRL_FORCEEN_MASK 0x10000UL /**< Bit mask for HFXO_FORCEEN */ -#define _HFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEEN_DEFAULT (_HFXO_CTRL_FORCEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEENPRS (0x1UL << 17) /**< Force PRS Oscillator Request */ -#define _HFXO_CTRL_FORCEENPRS_SHIFT 17 /**< Shift value for HFXO_FORCEENPRS */ -#define _HFXO_CTRL_FORCEENPRS_MASK 0x20000UL /**< Bit mask for HFXO_FORCEENPRS */ -#define _HFXO_CTRL_FORCEENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEENPRS_DEFAULT (_HFXO_CTRL_FORCEENPRS_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEENBUFOUT (0x1UL << 18) /**< Force BUFOUT Request */ -#define _HFXO_CTRL_FORCEENBUFOUT_SHIFT 18 /**< Shift value for HFXO_FORCEENBUFOUT */ -#define _HFXO_CTRL_FORCEENBUFOUT_MASK 0x40000UL /**< Bit mask for HFXO_FORCEENBUFOUT */ -#define _HFXO_CTRL_FORCEENBUFOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEENBUFOUT_DEFAULT (_HFXO_CTRL_FORCEENBUFOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMAND (0x1UL << 24) /**< Disable On-demand For Digital Clock */ -#define _HFXO_CTRL_DISONDEMAND_SHIFT 24 /**< Shift value for HFXO_DISONDEMAND */ -#define _HFXO_CTRL_DISONDEMAND_MASK 0x1000000UL /**< Bit mask for HFXO_DISONDEMAND */ -#define _HFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMAND_DEFAULT (_HFXO_CTRL_DISONDEMAND_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMANDPRS (0x1UL << 25) /**< Disable On-demand For PRS */ -#define _HFXO_CTRL_DISONDEMANDPRS_SHIFT 25 /**< Shift value for HFXO_DISONDEMANDPRS */ -#define _HFXO_CTRL_DISONDEMANDPRS_MASK 0x2000000UL /**< Bit mask for HFXO_DISONDEMANDPRS */ -#define _HFXO_CTRL_DISONDEMANDPRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMANDPRS_DEFAULT (_HFXO_CTRL_DISONDEMANDPRS_DEFAULT << 25) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMANDBUFOUT (0x1UL << 26) /**< Disable On-demand For BUFOUT */ -#define _HFXO_CTRL_DISONDEMANDBUFOUT_SHIFT 26 /**< Shift value for HFXO_DISONDEMANDBUFOUT */ -#define _HFXO_CTRL_DISONDEMANDBUFOUT_MASK 0x4000000UL /**< Bit mask for HFXO_DISONDEMANDBUFOUT */ -#define _HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT (_HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_RESETVALUE 0x07000040UL /**< Default value for HFXO_CTRL */ +#define _HFXO_CTRL_MASK 0x8707FF7DUL /**< Mask for HFXO_CTRL */ +#define HFXO_CTRL_BUFOUTFREEZE (0x1UL << 0) /**< Freeze BUFOUT Controls */ +#define _HFXO_CTRL_BUFOUTFREEZE_SHIFT 0 /**< Shift value for HFXO_BUFOUTFREEZE */ +#define _HFXO_CTRL_BUFOUTFREEZE_MASK 0x1UL /**< Bit mask for HFXO_BUFOUTFREEZE */ +#define _HFXO_CTRL_BUFOUTFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_BUFOUTFREEZE_DEFAULT (_HFXO_CTRL_BUFOUTFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM (0x1UL << 2) /**< Keep Warm */ +#define _HFXO_CTRL_KEEPWARM_SHIFT 2 /**< Shift value for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_MASK 0x4UL /**< Bit mask for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM_DEFAULT (_HFXO_CTRL_KEEPWARM_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_EM23ONDEMAND (0x1UL << 3) /**< On-demand During EM23 */ +#define _HFXO_CTRL_EM23ONDEMAND_SHIFT 3 /**< Shift value for HFXO_EM23ONDEMAND */ +#define _HFXO_CTRL_EM23ONDEMAND_MASK 0x8UL /**< Bit mask for HFXO_EM23ONDEMAND */ +#define _HFXO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_EM23ONDEMAND_DEFAULT (_HFXO_CTRL_EM23ONDEMAND_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA (0x1UL << 4) /**< Force XI Pin to Ground */ +#define _HFXO_CTRL_FORCEXI2GNDANA_SHIFT 4 /**< Shift value for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_MASK 0x10UL /**< Bit mask for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXI2GNDANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DISABLE (_HFXO_CTRL_FORCEXI2GNDANA_DISABLE << 4) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_ENABLE (_HFXO_CTRL_FORCEXI2GNDANA_ENABLE << 4) /**< Shifted mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA (0x1UL << 5) /**< Force XO Pin to Ground */ +#define _HFXO_CTRL_FORCEXO2GNDANA_SHIFT 5 /**< Shift value for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_MASK 0x20UL /**< Bit mask for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXO2GNDANA_DEFAULT << 5) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DISABLE (_HFXO_CTRL_FORCEXO2GNDANA_DISABLE << 5) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_ENABLE (_HFXO_CTRL_FORCEXO2GNDANA_ENABLE << 5) /**< Shifted mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCECTUNEMAX (0x1UL << 6) /**< Force Tuning Cap to Max Value */ +#define _HFXO_CTRL_FORCECTUNEMAX_SHIFT 6 /**< Shift value for HFXO_FORCECTUNEMAX */ +#define _HFXO_CTRL_FORCECTUNEMAX_MASK 0x40UL /**< Bit mask for HFXO_FORCECTUNEMAX */ +#define _HFXO_CTRL_FORCECTUNEMAX_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCECTUNEMAX_DEFAULT (_HFXO_CTRL_FORCECTUNEMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_SHIFT 8 /**< Shift value for HFXO_PRSSTATUSSEL0 */ +#define _HFXO_CTRL_PRSSTATUSSEL0_MASK 0xF00UL /**< Bit mask for HFXO_PRSSTATUSSEL0 */ +#define _HFXO_CTRL_PRSSTATUSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL0_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_DISABLED (_HFXO_CTRL_PRSSTATUSSEL0_DISABLED << 8) /**< Shifted mode DISABLED for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_ENS (_HFXO_CTRL_PRSSTATUSSEL0_ENS << 8) /**< Shifted mode ENS for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY << 8) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_RDY (_HFXO_CTRL_PRSSTATUSSEL0_RDY << 8) /**< Shifted mode RDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL0_PRSRDY << 8) /**< Shifted mode PRSRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY << 8) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_HWREQ (_HFXO_CTRL_PRSSTATUSSEL0_HWREQ << 8) /**< Shifted mode HWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ << 8) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ << 8) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_SHIFT 12 /**< Shift value for HFXO_PRSSTATUSSEL1 */ +#define _HFXO_CTRL_PRSSTATUSSEL1_MASK 0xF000UL /**< Bit mask for HFXO_PRSSTATUSSEL1 */ +#define _HFXO_CTRL_PRSSTATUSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL1_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_DISABLED (_HFXO_CTRL_PRSSTATUSSEL1_DISABLED << 12) /**< Shifted mode DISABLED for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_ENS (_HFXO_CTRL_PRSSTATUSSEL1_ENS << 12) /**< Shifted mode ENS for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY << 12) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_RDY (_HFXO_CTRL_PRSSTATUSSEL1_RDY << 12) /**< Shifted mode RDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL1_PRSRDY << 12) /**< Shifted mode PRSRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY << 12) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_HWREQ (_HFXO_CTRL_PRSSTATUSSEL1_HWREQ << 12) /**< Shifted mode HWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ << 12) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ << 12) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN (0x1UL << 16) /**< Force Digital Clock Request */ +#define _HFXO_CTRL_FORCEEN_SHIFT 16 /**< Shift value for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_MASK 0x10000UL /**< Bit mask for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN_DEFAULT (_HFXO_CTRL_FORCEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENPRS (0x1UL << 17) /**< Force PRS Oscillator Request */ +#define _HFXO_CTRL_FORCEENPRS_SHIFT 17 /**< Shift value for HFXO_FORCEENPRS */ +#define _HFXO_CTRL_FORCEENPRS_MASK 0x20000UL /**< Bit mask for HFXO_FORCEENPRS */ +#define _HFXO_CTRL_FORCEENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENPRS_DEFAULT (_HFXO_CTRL_FORCEENPRS_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENBUFOUT (0x1UL << 18) /**< Force BUFOUT Request */ +#define _HFXO_CTRL_FORCEENBUFOUT_SHIFT 18 /**< Shift value for HFXO_FORCEENBUFOUT */ +#define _HFXO_CTRL_FORCEENBUFOUT_MASK 0x40000UL /**< Bit mask for HFXO_FORCEENBUFOUT */ +#define _HFXO_CTRL_FORCEENBUFOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENBUFOUT_DEFAULT (_HFXO_CTRL_FORCEENBUFOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND (0x1UL << 24) /**< Disable On-demand For Digital Clock */ +#define _HFXO_CTRL_DISONDEMAND_SHIFT 24 /**< Shift value for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_MASK 0x1000000UL /**< Bit mask for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND_DEFAULT (_HFXO_CTRL_DISONDEMAND_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDPRS (0x1UL << 25) /**< Disable On-demand For PRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_SHIFT 25 /**< Shift value for HFXO_DISONDEMANDPRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_MASK 0x2000000UL /**< Bit mask for HFXO_DISONDEMANDPRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDPRS_DEFAULT (_HFXO_CTRL_DISONDEMANDPRS_DEFAULT << 25) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDBUFOUT (0x1UL << 26) /**< Disable On-demand For BUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_SHIFT 26 /**< Shift value for HFXO_DISONDEMANDBUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_MASK 0x4000000UL /**< Bit mask for HFXO_DISONDEMANDBUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT (_HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_CTRL */ /* Bit fields for HFXO BUFOUTTRIM */ -#define _HFXO_BUFOUTTRIM_RESETVALUE 0x00000008UL /**< Default value for HFXO_BUFOUTTRIM */ -#define _HFXO_BUFOUTTRIM_MASK 0x0000000FUL /**< Mask for HFXO_BUFOUTTRIM */ -#define _HFXO_BUFOUTTRIM_VTRTRIMANA_SHIFT 0 /**< Shift value for HFXO_VTRTRIMANA */ -#define _HFXO_BUFOUTTRIM_VTRTRIMANA_MASK 0xFUL /**< Bit mask for HFXO_VTRTRIMANA */ -#define _HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFXO_BUFOUTTRIM */ -#define HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT (_HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_RESETVALUE 0x00000008UL /**< Default value for HFXO_BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_MASK 0x0000000FUL /**< Mask for HFXO_BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_SHIFT 0 /**< Shift value for HFXO_VTRTRIMANA */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_MASK 0xFUL /**< Bit mask for HFXO_VTRTRIMANA */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFXO_BUFOUTTRIM */ +#define HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT (_HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTTRIM */ /* Bit fields for HFXO BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_RESETVALUE 0x00643C15UL /**< Default value for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_MASK 0xC0FFFFFFUL /**< Mask for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_XOUTBIASANA_SHIFT 0 /**< Shift value for HFXO_XOUTBIASANA */ -#define _HFXO_BUFOUTCTRL_XOUTBIASANA_MASK 0xFUL /**< Bit mask for HFXO_XOUTBIASANA */ -#define _HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT 0x00000005UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_XOUTCFANA_SHIFT 4 /**< Shift value for HFXO_XOUTCFANA */ -#define _HFXO_BUFOUTCTRL_XOUTCFANA_MASK 0xF0UL /**< Bit mask for HFXO_XOUTCFANA */ -#define _HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_XOUTGMANA_SHIFT 8 /**< Shift value for HFXO_XOUTGMANA */ -#define _HFXO_BUFOUTCTRL_XOUTGMANA_MASK 0xF00UL /**< Bit mask for HFXO_XOUTGMANA */ -#define _HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT 0x0000000CUL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_SHIFT 12 /**< Shift value for HFXO_PEAKDETTHRESANA */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_MASK 0xF000UL /**< Bit mask for HFXO_PEAKDETTHRESANA */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV 0x00000000UL /**< Mode V105MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV 0x00000001UL /**< Mode V132MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV 0x00000002UL /**< Mode V157MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV 0x00000003UL /**< Mode V184MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV 0x00000004UL /**< Mode V210MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV 0x00000005UL /**< Mode V236MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV 0x00000006UL /**< Mode V262MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV 0x00000007UL /**< Mode V289MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV 0x00000008UL /**< Mode V315MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV 0x00000009UL /**< Mode V341MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV 0x0000000AUL /**< Mode V367MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV 0x0000000BUL /**< Mode V394MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV 0x0000000CUL /**< Mode V420MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV 0x0000000DUL /**< Mode V446MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV 0x0000000EUL /**< Mode V472MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV 0x0000000FUL /**< Mode V499MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV << 12) /**< Shifted mode V105MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV << 12) /**< Shifted mode V132MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV << 12) /**< Shifted mode V157MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV << 12) /**< Shifted mode V184MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV << 12) /**< Shifted mode V210MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV << 12) /**< Shifted mode V236MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV << 12) /**< Shifted mode V262MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV << 12) /**< Shifted mode V289MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV << 12) /**< Shifted mode V315MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV << 12) /**< Shifted mode V341MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV << 12) /**< Shifted mode V367MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV << 12) /**< Shifted mode V394MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV << 12) /**< Shifted mode V420MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV << 12) /**< Shifted mode V446MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV << 12) /**< Shifted mode V472MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV << 12) /**< Shifted mode V499MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_SHIFT 16 /**< Shift value for HFXO_TIMEOUTCTUNE */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_MASK 0xF0000UL /**< Bit mask for HFXO_TIMEOUTCTUNE */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US 0x00000000UL /**< Mode T2US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US 0x00000001UL /**< Mode T5US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US 0x00000002UL /**< Mode T10US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US 0x00000003UL /**< Mode T16US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US 0x00000004UL /**< Mode T21US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US 0x00000005UL /**< Mode T26US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US 0x00000006UL /**< Mode T31US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US 0x00000007UL /**< Mode T42US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US 0x00000008UL /**< Mode T52US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US 0x00000009UL /**< Mode T63US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US 0x0000000AUL /**< Mode T83US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US 0x0000000BUL /**< Mode T104US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US 0x0000000CUL /**< Mode T208US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US 0x0000000DUL /**< Mode T313US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US 0x0000000EUL /**< Mode T521US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US 0x0000000FUL /**< Mode T938US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US << 16) /**< Shifted mode T2US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US << 16) /**< Shifted mode T5US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US << 16) /**< Shifted mode T10US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US << 16) /**< Shifted mode T16US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US << 16) /**< Shifted mode T21US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US << 16) /**< Shifted mode T26US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US << 16) /**< Shifted mode T31US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US << 16) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US << 16) /**< Shifted mode T52US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US << 16) /**< Shifted mode T63US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US << 16) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US << 16) /**< Shifted mode T104US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US << 16) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US << 16) /**< Shifted mode T313US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US << 16) /**< Shifted mode T521US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US << 16) /**< Shifted mode T938US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTARTUP */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTARTUP */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT 0x00000006UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US 0x00000000UL /**< Mode T42US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US 0x00000001UL /**< Mode T83US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US 0x00000002UL /**< Mode T108US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US 0x00000003UL /**< Mode T133US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US 0x00000004UL /**< Mode T158US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US 0x00000005UL /**< Mode T183US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US 0x00000006UL /**< Mode T208US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US 0x00000007UL /**< Mode T233US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US 0x00000008UL /**< Mode T258US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US 0x00000009UL /**< Mode T283US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US 0x0000000AUL /**< Mode T333US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US 0x0000000BUL /**< Mode T375US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US 0x0000000CUL /**< Mode T417US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US 0x0000000DUL /**< Mode T458US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US 0x0000000EUL /**< Mode T500US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US 0x0000000FUL /**< Mode T667US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US << 20) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US << 20) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US << 20) /**< Shifted mode T108US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US << 20) /**< Shifted mode T133US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US << 20) /**< Shifted mode T158US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US << 20) /**< Shifted mode T183US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US << 20) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US << 20) /**< Shifted mode T233US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US << 20) /**< Shifted mode T258US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US << 20) /**< Shifted mode T283US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US << 20) /**< Shifted mode T333US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US << 20) /**< Shifted mode T375US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US << 20) /**< Shifted mode T417US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US << 20) /**< Shifted mode T458US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US << 20) /**< Shifted mode T500US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US << 20) /**< Shifted mode T667US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY (0x1UL << 31) /**< Minimum Startup Delay */ -#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_SHIFT 31 /**< Shift value for HFXO_MINIMUMSTARTUPDELAY */ -#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_MASK 0x80000000UL /**< Bit mask for HFXO_MINIMUMSTARTUPDELAY */ -#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT (_HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_RESETVALUE 0x00643C15UL /**< Default value for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_MASK 0xC0FFFFFFUL /**< Mask for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_SHIFT 0 /**< Shift value for HFXO_XOUTBIASANA */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_MASK 0xFUL /**< Bit mask for HFXO_XOUTBIASANA */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT 0x00000005UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_SHIFT 4 /**< Shift value for HFXO_XOUTCFANA */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_MASK 0xF0UL /**< Bit mask for HFXO_XOUTCFANA */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_SHIFT 8 /**< Shift value for HFXO_XOUTGMANA */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_MASK 0xF00UL /**< Bit mask for HFXO_XOUTGMANA */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT 0x0000000CUL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_SHIFT 12 /**< Shift value for HFXO_PEAKDETTHRESANA */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_MASK 0xF000UL /**< Bit mask for HFXO_PEAKDETTHRESANA */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV 0x00000000UL /**< Mode V105MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV 0x00000001UL /**< Mode V132MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV 0x00000002UL /**< Mode V157MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV 0x00000003UL /**< Mode V184MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV 0x00000004UL /**< Mode V210MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV 0x00000005UL /**< Mode V236MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV 0x00000006UL /**< Mode V262MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV 0x00000007UL /**< Mode V289MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV 0x00000008UL /**< Mode V315MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV 0x00000009UL /**< Mode V341MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV 0x0000000AUL /**< Mode V367MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV 0x0000000BUL /**< Mode V394MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV 0x0000000CUL /**< Mode V420MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV 0x0000000DUL /**< Mode V446MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV 0x0000000EUL /**< Mode V472MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV 0x0000000FUL /**< Mode V499MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV << 12) /**< Shifted mode V105MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV << 12) /**< Shifted mode V132MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV << 12) /**< Shifted mode V157MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV << 12) /**< Shifted mode V184MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV << 12) /**< Shifted mode V210MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV << 12) /**< Shifted mode V236MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV << 12) /**< Shifted mode V262MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV << 12) /**< Shifted mode V289MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV << 12) /**< Shifted mode V315MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV << 12) /**< Shifted mode V341MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV << 12) /**< Shifted mode V367MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV << 12) /**< Shifted mode V394MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV << 12) /**< Shifted mode V420MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV << 12) /**< Shifted mode V446MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV << 12) /**< Shifted mode V472MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV << 12) /**< Shifted mode V499MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_SHIFT 16 /**< Shift value for HFXO_TIMEOUTCTUNE */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_MASK 0xF0000UL /**< Bit mask for HFXO_TIMEOUTCTUNE */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US 0x00000000UL /**< Mode T2US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US 0x00000001UL /**< Mode T5US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US 0x00000002UL /**< Mode T10US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US 0x00000003UL /**< Mode T16US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US 0x00000004UL /**< Mode T21US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US 0x00000005UL /**< Mode T26US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US 0x00000006UL /**< Mode T31US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US 0x00000007UL /**< Mode T42US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US 0x00000008UL /**< Mode T52US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US 0x00000009UL /**< Mode T63US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US 0x0000000AUL /**< Mode T83US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US 0x0000000BUL /**< Mode T104US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US 0x0000000CUL /**< Mode T208US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US 0x0000000DUL /**< Mode T313US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US 0x0000000EUL /**< Mode T521US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US 0x0000000FUL /**< Mode T938US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US << 16) /**< Shifted mode T2US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US << 16) /**< Shifted mode T5US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US << 16) /**< Shifted mode T10US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US << 16) /**< Shifted mode T16US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US << 16) /**< Shifted mode T21US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US << 16) /**< Shifted mode T26US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US << 16) /**< Shifted mode T31US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US << 16) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US << 16) /**< Shifted mode T52US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US << 16) /**< Shifted mode T63US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US << 16) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US << 16) /**< Shifted mode T104US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US << 16) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US << 16) /**< Shifted mode T313US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US << 16) /**< Shifted mode T521US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US << 16) /**< Shifted mode T938US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTARTUP */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTARTUP */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT 0x00000006UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US 0x00000000UL /**< Mode T42US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US 0x00000001UL /**< Mode T83US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US 0x00000002UL /**< Mode T108US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US 0x00000003UL /**< Mode T133US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US 0x00000004UL /**< Mode T158US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US 0x00000005UL /**< Mode T183US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US 0x00000006UL /**< Mode T208US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US 0x00000007UL /**< Mode T233US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US 0x00000008UL /**< Mode T258US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US 0x00000009UL /**< Mode T283US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US 0x0000000AUL /**< Mode T333US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US 0x0000000BUL /**< Mode T375US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US 0x0000000CUL /**< Mode T417US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US 0x0000000DUL /**< Mode T458US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US 0x0000000EUL /**< Mode T500US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US 0x0000000FUL /**< Mode T667US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US << 20) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US << 20) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US << 20) /**< Shifted mode T108US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US << 20) /**< Shifted mode T133US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US << 20) /**< Shifted mode T158US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US << 20) /**< Shifted mode T183US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US << 20) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US << 20) /**< Shifted mode T233US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US << 20) /**< Shifted mode T258US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US << 20) /**< Shifted mode T283US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US << 20) /**< Shifted mode T333US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US << 20) /**< Shifted mode T375US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US << 20) /**< Shifted mode T417US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US << 20) /**< Shifted mode T458US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US << 20) /**< Shifted mode T500US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US << 20) /**< Shifted mode T667US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY (0x1UL << 31) /**< Minimum Startup Delay */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_SHIFT 31 /**< Shift value for HFXO_MINIMUMSTARTUPDELAY */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_MASK 0x80000000UL /**< Bit mask for HFXO_MINIMUMSTARTUPDELAY */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT (_HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ /* Bit fields for HFXO CMD */ -#define _HFXO_CMD_RESETVALUE 0x00000000UL /**< Default value for HFXO_CMD */ -#define _HFXO_CMD_MASK 0x00000001UL /**< Mask for HFXO_CMD */ -#define HFXO_CMD_COREBIASOPT (0x1UL << 0) /**< Core Bias Optimizaton */ -#define _HFXO_CMD_COREBIASOPT_SHIFT 0 /**< Shift value for HFXO_COREBIASOPT */ -#define _HFXO_CMD_COREBIASOPT_MASK 0x1UL /**< Bit mask for HFXO_COREBIASOPT */ -#define _HFXO_CMD_COREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ -#define HFXO_CMD_COREBIASOPT_DEFAULT (_HFXO_CMD_COREBIASOPT_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CMD */ +#define _HFXO_CMD_RESETVALUE 0x00000000UL /**< Default value for HFXO_CMD */ +#define _HFXO_CMD_MASK 0x00000001UL /**< Mask for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT (0x1UL << 0) /**< Core Bias Optimizaton */ +#define _HFXO_CMD_COREBIASOPT_SHIFT 0 /**< Shift value for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_MASK 0x1UL /**< Bit mask for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT_DEFAULT (_HFXO_CMD_COREBIASOPT_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CMD */ /* Bit fields for HFXO STATUS */ -#define _HFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFXO_STATUS */ -#define _HFXO_STATUS_MASK 0xC03F800FUL /**< Mask for HFXO_STATUS */ -#define HFXO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ -#define _HFXO_STATUS_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ -#define _HFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ -#define _HFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_RDY_DEFAULT (_HFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready */ -#define _HFXO_STATUS_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ -#define _HFXO_STATUS_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ -#define _HFXO_STATUS_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_COREBIASOPTRDY_DEFAULT (_HFXO_STATUS_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_PRSRDY (0x1UL << 2) /**< PRS Ready Status */ -#define _HFXO_STATUS_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ -#define _HFXO_STATUS_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ -#define _HFXO_STATUS_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_PRSRDY_DEFAULT (_HFXO_STATUS_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Status */ -#define _HFXO_STATUS_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ -#define _HFXO_STATUS_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ -#define _HFXO_STATUS_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTRDY_DEFAULT (_HFXO_STATUS_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT Frozen */ -#define _HFXO_STATUS_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ -#define _HFXO_STATUS_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ -#define _HFXO_STATUS_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTFROZEN_DEFAULT (_HFXO_STATUS_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ -#define _HFXO_STATUS_ENS_SHIFT 16 /**< Shift value for HFXO_ENS */ -#define _HFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFXO_ENS */ -#define _HFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_ENS_DEFAULT (_HFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_HWREQ (0x1UL << 17) /**< Oscillator Requested by Digital Clock */ -#define _HFXO_STATUS_HWREQ_SHIFT 17 /**< Shift value for HFXO_HWREQ */ -#define _HFXO_STATUS_HWREQ_MASK 0x20000UL /**< Bit mask for HFXO_HWREQ */ -#define _HFXO_STATUS_HWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_HWREQ_DEFAULT (_HFXO_STATUS_HWREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_ISWARM (0x1UL << 19) /**< Oscillator Is Kept Warm */ -#define _HFXO_STATUS_ISWARM_SHIFT 19 /**< Shift value for HFXO_ISWARM */ -#define _HFXO_STATUS_ISWARM_MASK 0x80000UL /**< Bit mask for HFXO_ISWARM */ -#define _HFXO_STATUS_ISWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_ISWARM_DEFAULT (_HFXO_STATUS_ISWARM_DEFAULT << 19) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_PRSHWREQ (0x1UL << 20) /**< Oscillator Requested by PRS Request */ -#define _HFXO_STATUS_PRSHWREQ_SHIFT 20 /**< Shift value for HFXO_PRSHWREQ */ -#define _HFXO_STATUS_PRSHWREQ_MASK 0x100000UL /**< Bit mask for HFXO_PRSHWREQ */ -#define _HFXO_STATUS_PRSHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_PRSHWREQ_DEFAULT (_HFXO_STATUS_PRSHWREQ_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTHWREQ (0x1UL << 21) /**< Oscillator Requested by BUFOUT Request */ -#define _HFXO_STATUS_BUFOUTHWREQ_SHIFT 21 /**< Shift value for HFXO_BUFOUTHWREQ */ -#define _HFXO_STATUS_BUFOUTHWREQ_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTHWREQ */ -#define _HFXO_STATUS_BUFOUTHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTHWREQ_DEFAULT (_HFXO_STATUS_BUFOUTHWREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_SYNCBUSY (0x1UL << 30) /**< Sync Busy */ -#define _HFXO_STATUS_SYNCBUSY_SHIFT 30 /**< Shift value for HFXO_SYNCBUSY */ -#define _HFXO_STATUS_SYNCBUSY_MASK 0x40000000UL /**< Bit mask for HFXO_SYNCBUSY */ -#define _HFXO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_SYNCBUSY_DEFAULT (_HFXO_STATUS_SYNCBUSY_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ -#define _HFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFXO_LOCK */ -#define _HFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFXO_LOCK */ -#define _HFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define _HFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ -#define _HFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ -#define HFXO_STATUS_LOCK_DEFAULT (_HFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_LOCK_UNLOCKED (_HFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFXO_STATUS */ -#define HFXO_STATUS_LOCK_LOCKED (_HFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFXO_STATUS */ +#define _HFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFXO_STATUS */ +#define _HFXO_STATUS_MASK 0xC03F800FUL /**< Mask for HFXO_STATUS */ +#define HFXO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _HFXO_STATUS_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_RDY_DEFAULT (_HFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready */ +#define _HFXO_STATUS_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY_DEFAULT (_HFXO_STATUS_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSRDY (0x1UL << 2) /**< PRS Ready Status */ +#define _HFXO_STATUS_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_STATUS_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_STATUS_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSRDY_DEFAULT (_HFXO_STATUS_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Status */ +#define _HFXO_STATUS_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_STATUS_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_STATUS_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTRDY_DEFAULT (_HFXO_STATUS_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT Frozen */ +#define _HFXO_STATUS_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_STATUS_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_STATUS_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTFROZEN_DEFAULT (_HFXO_STATUS_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _HFXO_STATUS_ENS_SHIFT 16 /**< Shift value for HFXO_ENS */ +#define _HFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFXO_ENS */ +#define _HFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS_DEFAULT (_HFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ (0x1UL << 17) /**< Oscillator Requested by Digital Clock */ +#define _HFXO_STATUS_HWREQ_SHIFT 17 /**< Shift value for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_MASK 0x20000UL /**< Bit mask for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ_DEFAULT (_HFXO_STATUS_HWREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM (0x1UL << 19) /**< Oscillator Is Kept Warm */ +#define _HFXO_STATUS_ISWARM_SHIFT 19 /**< Shift value for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_MASK 0x80000UL /**< Bit mask for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM_DEFAULT (_HFXO_STATUS_ISWARM_DEFAULT << 19) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSHWREQ (0x1UL << 20) /**< Oscillator Requested by PRS Request */ +#define _HFXO_STATUS_PRSHWREQ_SHIFT 20 /**< Shift value for HFXO_PRSHWREQ */ +#define _HFXO_STATUS_PRSHWREQ_MASK 0x100000UL /**< Bit mask for HFXO_PRSHWREQ */ +#define _HFXO_STATUS_PRSHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSHWREQ_DEFAULT (_HFXO_STATUS_PRSHWREQ_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTHWREQ (0x1UL << 21) /**< Oscillator Requested by BUFOUT Request */ +#define _HFXO_STATUS_BUFOUTHWREQ_SHIFT 21 /**< Shift value for HFXO_BUFOUTHWREQ */ +#define _HFXO_STATUS_BUFOUTHWREQ_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTHWREQ */ +#define _HFXO_STATUS_BUFOUTHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTHWREQ_DEFAULT (_HFXO_STATUS_BUFOUTHWREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_SYNCBUSY (0x1UL << 30) /**< Sync Busy */ +#define _HFXO_STATUS_SYNCBUSY_SHIFT 30 /**< Shift value for HFXO_SYNCBUSY */ +#define _HFXO_STATUS_SYNCBUSY_MASK 0x40000000UL /**< Bit mask for HFXO_SYNCBUSY */ +#define _HFXO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_SYNCBUSY_DEFAULT (_HFXO_STATUS_SYNCBUSY_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _HFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_DEFAULT (_HFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_UNLOCKED (_HFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_LOCKED (_HFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFXO_STATUS */ /* Bit fields for HFXO IF */ -#define _HFXO_IF_RESETVALUE 0x00000000UL /**< Default value for HFXO_IF */ -#define _HFXO_IF_MASK 0xF830800FUL /**< Mask for HFXO_IF */ -#define HFXO_IF_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ -#define _HFXO_IF_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ -#define _HFXO_IF_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ -#define _HFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_RDY_DEFAULT (_HFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ -#define _HFXO_IF_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ -#define _HFXO_IF_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ -#define _HFXO_IF_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_COREBIASOPTRDY_DEFAULT (_HFXO_IF_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ -#define _HFXO_IF_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ -#define _HFXO_IF_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ -#define _HFXO_IF_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_PRSRDY_DEFAULT (_HFXO_IF_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ -#define _HFXO_IF_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ -#define _HFXO_IF_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ -#define _HFXO_IF_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTRDY_DEFAULT (_HFXO_IF_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ -#define _HFXO_IF_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ -#define _HFXO_IF_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ -#define _HFXO_IF_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTFROZEN_DEFAULT (_HFXO_IF_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ -#define _HFXO_IF_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ -#define _HFXO_IF_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ -#define _HFXO_IF_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_PRSERR_DEFAULT (_HFXO_IF_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ -#define _HFXO_IF_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ -#define _HFXO_IF_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ -#define _HFXO_IF_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTERR_DEFAULT (_HFXO_IF_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ -#define _HFXO_IF_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ -#define _HFXO_IF_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ -#define _HFXO_IF_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTFREEZEERR_DEFAULT (_HFXO_IF_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ -#define _HFXO_IF_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ -#define _HFXO_IF_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ -#define _HFXO_IF_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTDNSERR_DEFAULT (_HFXO_IF_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ -#define _HFXO_IF_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ -#define _HFXO_IF_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ -#define _HFXO_IF_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_DNSERR_DEFAULT (_HFXO_IF_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ -#define _HFXO_IF_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ -#define _HFXO_IF_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ -#define _HFXO_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_LFTIMEOUTERR_DEFAULT (_HFXO_IF_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ -#define _HFXO_IF_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ -#define _HFXO_IF_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ -#define _HFXO_IF_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_COREBIASOPTERR_DEFAULT (_HFXO_IF_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IF */ +#define _HFXO_IF_RESETVALUE 0x00000000UL /**< Default value for HFXO_IF */ +#define _HFXO_IF_MASK 0xF830800FUL /**< Mask for HFXO_IF */ +#define HFXO_IF_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ +#define _HFXO_IF_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IF_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_RDY_DEFAULT (_HFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IF_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY_DEFAULT (_HFXO_IF_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ +#define _HFXO_IF_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_IF_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_IF_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSRDY_DEFAULT (_HFXO_IF_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ +#define _HFXO_IF_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_IF_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_IF_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTRDY_DEFAULT (_HFXO_IF_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ +#define _HFXO_IF_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_IF_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_IF_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFROZEN_DEFAULT (_HFXO_IF_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ +#define _HFXO_IF_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ +#define _HFXO_IF_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ +#define _HFXO_IF_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSERR_DEFAULT (_HFXO_IF_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ +#define _HFXO_IF_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ +#define _HFXO_IF_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ +#define _HFXO_IF_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTERR_DEFAULT (_HFXO_IF_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ +#define _HFXO_IF_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IF_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IF_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFREEZEERR_DEFAULT (_HFXO_IF_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ +#define _HFXO_IF_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ +#define _HFXO_IF_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ +#define _HFXO_IF_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTDNSERR_DEFAULT (_HFXO_IF_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IF_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR_DEFAULT (_HFXO_IF_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ +#define _HFXO_IF_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ +#define _HFXO_IF_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ +#define _HFXO_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_LFTIMEOUTERR_DEFAULT (_HFXO_IF_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IF_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR_DEFAULT (_HFXO_IF_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IF */ /* Bit fields for HFXO IEN */ -#define _HFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFXO_IEN */ -#define _HFXO_IEN_MASK 0xF830800FUL /**< Mask for HFXO_IEN */ -#define HFXO_IEN_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ -#define _HFXO_IEN_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ -#define _HFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ -#define _HFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_RDY_DEFAULT (_HFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ -#define _HFXO_IEN_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ -#define _HFXO_IEN_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ -#define _HFXO_IEN_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_COREBIASOPTRDY_DEFAULT (_HFXO_IEN_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ -#define _HFXO_IEN_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ -#define _HFXO_IEN_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ -#define _HFXO_IEN_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_PRSRDY_DEFAULT (_HFXO_IEN_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ -#define _HFXO_IEN_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ -#define _HFXO_IEN_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ -#define _HFXO_IEN_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTRDY_DEFAULT (_HFXO_IEN_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ -#define _HFXO_IEN_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ -#define _HFXO_IEN_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ -#define _HFXO_IEN_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTFROZEN_DEFAULT (_HFXO_IEN_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ -#define _HFXO_IEN_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ -#define _HFXO_IEN_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ -#define _HFXO_IEN_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_PRSERR_DEFAULT (_HFXO_IEN_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ -#define _HFXO_IEN_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ -#define _HFXO_IEN_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ -#define _HFXO_IEN_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTERR_DEFAULT (_HFXO_IEN_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ -#define _HFXO_IEN_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ -#define _HFXO_IEN_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ -#define _HFXO_IEN_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTFREEZEERR_DEFAULT (_HFXO_IEN_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ -#define _HFXO_IEN_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ -#define _HFXO_IEN_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ -#define _HFXO_IEN_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTDNSERR_DEFAULT (_HFXO_IEN_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ -#define _HFXO_IEN_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ -#define _HFXO_IEN_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ -#define _HFXO_IEN_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_DNSERR_DEFAULT (_HFXO_IEN_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ -#define _HFXO_IEN_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ -#define _HFXO_IEN_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ -#define _HFXO_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_LFTIMEOUTERR_DEFAULT (_HFXO_IEN_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ -#define _HFXO_IEN_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ -#define _HFXO_IEN_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ -#define _HFXO_IEN_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_COREBIASOPTERR_DEFAULT (_HFXO_IEN_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define _HFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFXO_IEN */ +#define _HFXO_IEN_MASK 0xF830800FUL /**< Mask for HFXO_IEN */ +#define HFXO_IEN_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ +#define _HFXO_IEN_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_RDY_DEFAULT (_HFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IEN_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY_DEFAULT (_HFXO_IEN_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ +#define _HFXO_IEN_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_IEN_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_IEN_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSRDY_DEFAULT (_HFXO_IEN_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ +#define _HFXO_IEN_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_IEN_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_IEN_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTRDY_DEFAULT (_HFXO_IEN_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ +#define _HFXO_IEN_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_IEN_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_IEN_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFROZEN_DEFAULT (_HFXO_IEN_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ +#define _HFXO_IEN_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ +#define _HFXO_IEN_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ +#define _HFXO_IEN_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSERR_DEFAULT (_HFXO_IEN_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ +#define _HFXO_IEN_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ +#define _HFXO_IEN_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ +#define _HFXO_IEN_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTERR_DEFAULT (_HFXO_IEN_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ +#define _HFXO_IEN_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IEN_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IEN_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFREEZEERR_DEFAULT (_HFXO_IEN_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ +#define _HFXO_IEN_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ +#define _HFXO_IEN_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ +#define _HFXO_IEN_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTDNSERR_DEFAULT (_HFXO_IEN_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IEN_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR_DEFAULT (_HFXO_IEN_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ +#define _HFXO_IEN_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ +#define _HFXO_IEN_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ +#define _HFXO_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_LFTIMEOUTERR_DEFAULT (_HFXO_IEN_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IEN_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR_DEFAULT (_HFXO_IEN_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IEN */ /* Bit fields for HFXO LOCK */ -#define _HFXO_LOCK_RESETVALUE 0x0000580EUL /**< Default value for HFXO_LOCK */ -#define _HFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFXO_LOCK */ -#define _HFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFXO_LOCKKEY */ -#define _HFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFXO_LOCKKEY */ -#define _HFXO_LOCK_LOCKKEY_DEFAULT 0x0000580EUL /**< Mode DEFAULT for HFXO_LOCK */ -#define _HFXO_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for HFXO_LOCK */ -#define HFXO_LOCK_LOCKKEY_DEFAULT (_HFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_LOCK */ -#define HFXO_LOCK_LOCKKEY_UNLOCK (_HFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFXO_LOCK */ +#define _HFXO_LOCK_RESETVALUE 0x0000580EUL /**< Default value for HFXO_LOCK */ +#define _HFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_DEFAULT 0x0000580EUL /**< Mode DEFAULT for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_DEFAULT (_HFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_UNLOCK (_HFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFXO_LOCK */ /** @} End of group EFR32SG28_HFXO_BitFields */ /** @} End of group EFR32SG28_HFXO */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_i2c.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_i2c.h index 706dbc30ba..f22820c604 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_i2c.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_i2c.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_I2C_H #define EFR32SG28_I2C_H - #define I2C_HAS_SET_CLEAR /**************************************************************************//** @@ -43,79 +42,78 @@ *****************************************************************************/ /** I2C Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP VERSION Register */ - __IOM uint32_t EN; /**< Enable Register */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATE; /**< State Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t CLKDIV; /**< Clock Division Register */ - __IOM uint32_t SADDR; /**< Follower Address Register */ - __IOM uint32_t SADDRMASK; /**< Follower Address Mask Register */ - __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ - __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ - __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ - __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ - __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ - __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED0[1007U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP VERSION Register */ - __IOM uint32_t EN_SET; /**< Enable Register */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATE_SET; /**< State Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t CLKDIV_SET; /**< Clock Division Register */ - __IOM uint32_t SADDR_SET; /**< Follower Address Register */ - __IOM uint32_t SADDRMASK_SET; /**< Follower Address Mask Register */ - __IM uint32_t RXDATA_SET; /**< Receive Buffer Data Register */ - __IM uint32_t RXDOUBLE_SET; /**< Receive Buffer Double Data Register */ - __IM uint32_t RXDATAP_SET; /**< Receive Buffer Data Peek Register */ - __IM uint32_t RXDOUBLEP_SET; /**< Receive Buffer Double Data Peek Register */ - __IOM uint32_t TXDATA_SET; /**< Transmit Buffer Data Register */ - __IOM uint32_t TXDOUBLE_SET; /**< Transmit Buffer Double Data Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED1[1007U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP VERSION Register */ - __IOM uint32_t EN_CLR; /**< Enable Register */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATE_CLR; /**< State Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t CLKDIV_CLR; /**< Clock Division Register */ - __IOM uint32_t SADDR_CLR; /**< Follower Address Register */ - __IOM uint32_t SADDRMASK_CLR; /**< Follower Address Mask Register */ - __IM uint32_t RXDATA_CLR; /**< Receive Buffer Data Register */ - __IM uint32_t RXDOUBLE_CLR; /**< Receive Buffer Double Data Register */ - __IM uint32_t RXDATAP_CLR; /**< Receive Buffer Data Peek Register */ - __IM uint32_t RXDOUBLEP_CLR; /**< Receive Buffer Double Data Peek Register */ - __IOM uint32_t TXDATA_CLR; /**< Transmit Buffer Data Register */ - __IOM uint32_t TXDOUBLE_CLR; /**< Transmit Buffer Double Data Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED2[1007U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP VERSION Register */ - __IOM uint32_t EN_TGL; /**< Enable Register */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATE_TGL; /**< State Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t CLKDIV_TGL; /**< Clock Division Register */ - __IOM uint32_t SADDR_TGL; /**< Follower Address Register */ - __IOM uint32_t SADDRMASK_TGL; /**< Follower Address Mask Register */ - __IM uint32_t RXDATA_TGL; /**< Receive Buffer Data Register */ - __IM uint32_t RXDOUBLE_TGL; /**< Receive Buffer Double Data Register */ - __IM uint32_t RXDATAP_TGL; /**< Receive Buffer Data Peek Register */ - __IM uint32_t RXDOUBLEP_TGL; /**< Receive Buffer Double Data Peek Register */ - __IOM uint32_t TXDATA_TGL; /**< Transmit Buffer Data Register */ - __IOM uint32_t TXDOUBLE_TGL; /**< Transmit Buffer Double Data Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP VERSION Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATE; /**< State Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Division Register */ + __IOM uint32_t SADDR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATE_SET; /**< State Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Division Register */ + __IOM uint32_t SADDR_SET; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_SET; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_SET; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_SET; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_SET; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_SET; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_SET; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATE_CLR; /**< State Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Division Register */ + __IOM uint32_t SADDR_CLR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_CLR; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_CLR; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_CLR; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_CLR; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_CLR; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATE_TGL; /**< State Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Division Register */ + __IOM uint32_t SADDR_TGL; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_TGL; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_TGL; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_TGL; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_TGL; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_TGL; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ } I2C_TypeDef; /** @} End of group EFR32SG28_I2C */ @@ -127,617 +125,617 @@ typedef struct *****************************************************************************/ /* Bit fields for I2C IPVERSION */ -#define _I2C_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for I2C_IPVERSION */ -#define _I2C_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for I2C_IPVERSION */ -#define _I2C_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for I2C_IPVERSION */ -#define _I2C_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for I2C_IPVERSION */ -#define _I2C_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IPVERSION */ -#define I2C_IPVERSION_IPVERSION_DEFAULT (_I2C_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IPVERSION */ +#define _I2C_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for I2C_IPVERSION */ +#define _I2C_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IPVERSION */ +#define I2C_IPVERSION_IPVERSION_DEFAULT (_I2C_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IPVERSION */ /* Bit fields for I2C EN */ -#define _I2C_EN_RESETVALUE 0x00000000UL /**< Default value for I2C_EN */ -#define _I2C_EN_MASK 0x00000001UL /**< Mask for I2C_EN */ -#define I2C_EN_EN (0x1UL << 0) /**< module enable */ -#define _I2C_EN_EN_SHIFT 0 /**< Shift value for I2C_EN */ -#define _I2C_EN_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ -#define _I2C_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_EN */ -#define _I2C_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_EN */ -#define _I2C_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_EN */ -#define I2C_EN_EN_DEFAULT (_I2C_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_EN */ -#define I2C_EN_EN_DISABLE (_I2C_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for I2C_EN */ -#define I2C_EN_EN_ENABLE (_I2C_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for I2C_EN */ +#define _I2C_EN_RESETVALUE 0x00000000UL /**< Default value for I2C_EN */ +#define _I2C_EN_MASK 0x00000001UL /**< Mask for I2C_EN */ +#define I2C_EN_EN (0x1UL << 0) /**< module enable */ +#define _I2C_EN_EN_SHIFT 0 /**< Shift value for I2C_EN */ +#define _I2C_EN_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ +#define _I2C_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_EN */ +#define _I2C_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_EN */ +#define _I2C_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_EN */ +#define I2C_EN_EN_DEFAULT (_I2C_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_EN */ +#define I2C_EN_EN_DISABLE (_I2C_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for I2C_EN */ +#define I2C_EN_EN_ENABLE (_I2C_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for I2C_EN */ /* Bit fields for I2C CTRL */ -#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ -#define _I2C_CTRL_MASK 0x0037B3FFUL /**< Mask for I2C_CTRL */ -#define I2C_CTRL_CORERST (0x1UL << 0) /**< Soft Reset the internal state registers */ -#define _I2C_CTRL_CORERST_SHIFT 0 /**< Shift value for I2C_CORERST */ -#define _I2C_CTRL_CORERST_MASK 0x1UL /**< Bit mask for I2C_CORERST */ -#define _I2C_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_CORERST_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_CORERST_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_CORERST_DEFAULT (_I2C_CTRL_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_CORERST_DISABLE (_I2C_CTRL_CORERST_DISABLE << 0) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_CORERST_ENABLE (_I2C_CTRL_CORERST_ENABLE << 0) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Follower */ -#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ -#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ -#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_SLAVE_DISABLE (_I2C_CTRL_SLAVE_DISABLE << 1) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_SLAVE_ENABLE (_I2C_CTRL_SLAVE_ENABLE << 1) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ -#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ -#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ -#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_AUTOACK_DISABLE (_I2C_CTRL_AUTOACK_DISABLE << 2) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOACK_ENABLE (_I2C_CTRL_AUTOACK_ENABLE << 2) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ -#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ -#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ -#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_AUTOSE_DISABLE (_I2C_CTRL_AUTOSE_DISABLE << 3) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSE_ENABLE (_I2C_CTRL_AUTOSE_ENABLE << 3) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ -#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ -#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ -#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_AUTOSN_DISABLE (_I2C_CTRL_AUTOSN_DISABLE << 4) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSN_ENABLE (_I2C_CTRL_AUTOSN_ENABLE << 4) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ -#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ -#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ -#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_ARBDIS_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_ARBDIS_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_ARBDIS_DISABLE (_I2C_CTRL_ARBDIS_DISABLE << 5) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_ARBDIS_ENABLE (_I2C_CTRL_ARBDIS_ENABLE << 5) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ -#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ -#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ -#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_GCAMEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_GCAMEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_GCAMEN_DISABLE (_I2C_CTRL_GCAMEN_DISABLE << 6) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_GCAMEN_ENABLE (_I2C_CTRL_GCAMEN_ENABLE << 6) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ -#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ -#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ -#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ -#define _I2C_CTRL_TXBIL_HALF_FULL 0x00000001UL /**< Mode HALF_FULL for I2C_CTRL */ -#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ -#define I2C_CTRL_TXBIL_HALF_FULL (_I2C_CTRL_TXBIL_HALF_FULL << 7) /**< Shifted mode HALF_FULL for I2C_CTRL */ -#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ -#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ -#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ -#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ -#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ -#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ -#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ -#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ -#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ -#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ -#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ -#define _I2C_CTRL_BITO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ -#define _I2C_CTRL_BITO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ -#define _I2C_CTRL_BITO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ -#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ -#define I2C_CTRL_BITO_I2C40PCC (_I2C_CTRL_BITO_I2C40PCC << 12) /**< Shifted mode I2C40PCC for I2C_CTRL */ -#define I2C_CTRL_BITO_I2C80PCC (_I2C_CTRL_BITO_I2C80PCC << 12) /**< Shifted mode I2C80PCC for I2C_CTRL */ -#define I2C_CTRL_BITO_I2C160PCC (_I2C_CTRL_BITO_I2C160PCC << 12) /**< Shifted mode I2C160PCC for I2C_CTRL */ -#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ -#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ -#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ -#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_GIBITO_DISABLE (_I2C_CTRL_GIBITO_DISABLE << 15) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_GIBITO_ENABLE (_I2C_CTRL_GIBITO_ENABLE << 15) /**< Shifted mode ENABLE for I2C_CTRL */ -#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ -#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ -#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C320PCC 0x00000004UL /**< Mode I2C320PCC for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C1024PCC 0x00000005UL /**< Mode I2C1024PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C40PCC (_I2C_CTRL_CLTO_I2C40PCC << 16) /**< Shifted mode I2C40PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C80PCC (_I2C_CTRL_CLTO_I2C80PCC << 16) /**< Shifted mode I2C80PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C160PCC (_I2C_CTRL_CLTO_I2C160PCC << 16) /**< Shifted mode I2C160PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C320PCC (_I2C_CTRL_CLTO_I2C320PCC << 16) /**< Shifted mode I2C320PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C1024PCC (_I2C_CTRL_CLTO_I2C1024PCC << 16) /**< Shifted mode I2C1024PCC for I2C_CTRL */ -#define I2C_CTRL_SCLMONEN (0x1UL << 20) /**< SCL Monitor Enable */ -#define _I2C_CTRL_SCLMONEN_SHIFT 20 /**< Shift value for I2C_SCLMONEN */ -#define _I2C_CTRL_SCLMONEN_MASK 0x100000UL /**< Bit mask for I2C_SCLMONEN */ -#define _I2C_CTRL_SCLMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_SCLMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_SCLMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SCLMONEN_DEFAULT (_I2C_CTRL_SCLMONEN_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_SCLMONEN_DISABLE (_I2C_CTRL_SCLMONEN_DISABLE << 20) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_SCLMONEN_ENABLE (_I2C_CTRL_SCLMONEN_ENABLE << 20) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SDAMONEN (0x1UL << 21) /**< SDA Monitor Enable */ -#define _I2C_CTRL_SDAMONEN_SHIFT 21 /**< Shift value for I2C_SDAMONEN */ -#define _I2C_CTRL_SDAMONEN_MASK 0x200000UL /**< Bit mask for I2C_SDAMONEN */ -#define _I2C_CTRL_SDAMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_SDAMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_SDAMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SDAMONEN_DEFAULT (_I2C_CTRL_SDAMONEN_DEFAULT << 21) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_SDAMONEN_DISABLE (_I2C_CTRL_SDAMONEN_DISABLE << 21) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_SDAMONEN_ENABLE (_I2C_CTRL_SDAMONEN_ENABLE << 21) /**< Shifted mode ENABLE for I2C_CTRL */ +#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ +#define _I2C_CTRL_MASK 0x0037B3FFUL /**< Mask for I2C_CTRL */ +#define I2C_CTRL_CORERST (0x1UL << 0) /**< Soft Reset the internal state registers */ +#define _I2C_CTRL_CORERST_SHIFT 0 /**< Shift value for I2C_CORERST */ +#define _I2C_CTRL_CORERST_MASK 0x1UL /**< Bit mask for I2C_CORERST */ +#define _I2C_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CORERST_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_CORERST_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_DEFAULT (_I2C_CTRL_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CORERST_DISABLE (_I2C_CTRL_CORERST_DISABLE << 0) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_ENABLE (_I2C_CTRL_CORERST_ENABLE << 0) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Follower */ +#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DISABLE (_I2C_CTRL_SLAVE_DISABLE << 1) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_ENABLE (_I2C_CTRL_SLAVE_ENABLE << 1) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ +#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DISABLE (_I2C_CTRL_AUTOACK_DISABLE << 2) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_ENABLE (_I2C_CTRL_AUTOACK_ENABLE << 2) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ +#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DISABLE (_I2C_CTRL_AUTOSE_DISABLE << 3) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_ENABLE (_I2C_CTRL_AUTOSE_ENABLE << 3) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ +#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DISABLE (_I2C_CTRL_AUTOSN_DISABLE << 4) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_ENABLE (_I2C_CTRL_AUTOSN_ENABLE << 4) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ +#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DISABLE (_I2C_CTRL_ARBDIS_DISABLE << 5) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_ENABLE (_I2C_CTRL_ARBDIS_ENABLE << 5) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ +#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DISABLE (_I2C_CTRL_GCAMEN_DISABLE << 6) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_ENABLE (_I2C_CTRL_GCAMEN_ENABLE << 6) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ +#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_HALF_FULL 0x00000001UL /**< Mode HALF_FULL for I2C_CTRL */ +#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ +#define I2C_CTRL_TXBIL_HALF_FULL (_I2C_CTRL_TXBIL_HALF_FULL << 7) /**< Shifted mode HALF_FULL for I2C_CTRL */ +#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ +#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ +#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ +#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ +#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ +#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ +#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ +#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ +#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ +#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ +#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C40PCC (_I2C_CTRL_BITO_I2C40PCC << 12) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C80PCC (_I2C_CTRL_BITO_I2C80PCC << 12) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C160PCC (_I2C_CTRL_BITO_I2C160PCC << 12) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ +#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DISABLE (_I2C_CTRL_GIBITO_DISABLE << 15) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_ENABLE (_I2C_CTRL_GIBITO_ENABLE << 15) /**< Shifted mode ENABLE for I2C_CTRL */ +#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ +#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C320PCC 0x00000004UL /**< Mode I2C320PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C1024PCC 0x00000005UL /**< Mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C40PCC (_I2C_CTRL_CLTO_I2C40PCC << 16) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C80PCC (_I2C_CTRL_CLTO_I2C80PCC << 16) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C160PCC (_I2C_CTRL_CLTO_I2C160PCC << 16) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C320PCC (_I2C_CTRL_CLTO_I2C320PCC << 16) /**< Shifted mode I2C320PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C1024PCC (_I2C_CTRL_CLTO_I2C1024PCC << 16) /**< Shifted mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN (0x1UL << 20) /**< SCL Monitor Enable */ +#define _I2C_CTRL_SCLMONEN_SHIFT 20 /**< Shift value for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_MASK 0x100000UL /**< Bit mask for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DEFAULT (_I2C_CTRL_SCLMONEN_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DISABLE (_I2C_CTRL_SCLMONEN_DISABLE << 20) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_ENABLE (_I2C_CTRL_SCLMONEN_ENABLE << 20) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN (0x1UL << 21) /**< SDA Monitor Enable */ +#define _I2C_CTRL_SDAMONEN_SHIFT 21 /**< Shift value for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_MASK 0x200000UL /**< Bit mask for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DEFAULT (_I2C_CTRL_SDAMONEN_DEFAULT << 21) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DISABLE (_I2C_CTRL_SDAMONEN_DISABLE << 21) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_ENABLE (_I2C_CTRL_SDAMONEN_ENABLE << 21) /**< Shifted mode ENABLE for I2C_CTRL */ /* Bit fields for I2C CMD */ -#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ -#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ -#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ -#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ -#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ -#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ -#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ -#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ -#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ -#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ -#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ -#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ -#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ -#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ -#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ -#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ -#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ -#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ -#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ -#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ -#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ -#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ -#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ -#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ -#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ -#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ -#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ +#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ +#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ +#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ +#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ +#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ +#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ +#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ +#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ +#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ +#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ +#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ +#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ +#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ +#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ +#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ +#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ +#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ +#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ +#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ +#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ /* Bit fields for I2C STATE */ -#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ -#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ -#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ -#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ -#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ -#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_MASTER (0x1UL << 1) /**< Leader */ -#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ -#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ -#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ -#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ -#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ -#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ -#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ -#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ -#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ -#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ -#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ -#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ -#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ -#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ -#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ -#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ -#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ -#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ -#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ -#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ -#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ -#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ -#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ -#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ -#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ -#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ -#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ -#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ +#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ +#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ +#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ +#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ +#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ +#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER (0x1UL << 1) /**< Leader */ +#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ +#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ +#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ +#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ +#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ +#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ +#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ +#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ +#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ +#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ +#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ +#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ +#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ +#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ +#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ +#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ +#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ +#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ +#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ +#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ +#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ +#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ +#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ /* Bit fields for I2C STATUS */ -#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ -#define _I2C_STATUS_MASK 0x00000FFFUL /**< Mask for I2C_STATUS */ -#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ -#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ -#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ -#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ -#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ -#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ -#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ -#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ -#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ -#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ -#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ -#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ -#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ -#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ -#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ -#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ -#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ -#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ -#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ -#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ -#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ -#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ -#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ -#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ -#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ -#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ -#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ -#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ -#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ -#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ -#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define _I2C_STATUS_TXBUFCNT_SHIFT 10 /**< Shift value for I2C_TXBUFCNT */ -#define _I2C_STATUS_TXBUFCNT_MASK 0xC00UL /**< Bit mask for I2C_TXBUFCNT */ -#define _I2C_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXBUFCNT_DEFAULT (_I2C_STATUS_TXBUFCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ +#define _I2C_STATUS_MASK 0x00000FFFUL /**< Mask for I2C_STATUS */ +#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ +#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ +#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ +#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ +#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ +#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ +#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ +#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ +#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ +#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ +#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ +#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ +#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ +#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ +#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ +#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ +#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ +#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ +#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ +#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ +#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ +#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ +#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ +#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ +#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_TXBUFCNT_SHIFT 10 /**< Shift value for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_MASK 0xC00UL /**< Bit mask for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBUFCNT_DEFAULT (_I2C_STATUS_TXBUFCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_STATUS */ /* Bit fields for I2C CLKDIV */ -#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ -#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ -#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ -#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ -#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ -#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ +#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ +#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ +#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ +#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ +#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ +#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ /* Bit fields for I2C SADDR */ -#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ -#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ -#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ -#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ -#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ -#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ +#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ +#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ +#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ +#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ +#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ +#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ /* Bit fields for I2C SADDRMASK */ -#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ -#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ -#define _I2C_SADDRMASK_SADDRMASK_SHIFT 1 /**< Shift value for I2C_SADDRMASK */ -#define _I2C_SADDRMASK_SADDRMASK_MASK 0xFEUL /**< Bit mask for I2C_SADDRMASK */ -#define _I2C_SADDRMASK_SADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ -#define I2C_SADDRMASK_SADDRMASK_DEFAULT (_I2C_SADDRMASK_SADDRMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_SHIFT 1 /**< Shift value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_MASK 0xFEUL /**< Bit mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ +#define I2C_SADDRMASK_SADDRMASK_DEFAULT (_I2C_SADDRMASK_SADDRMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ /* Bit fields for I2C RXDATA */ -#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ -#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ -#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ -#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ -#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ -#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ +#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ +#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ +#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ /* Bit fields for I2C RXDOUBLE */ -#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ -#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ -#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ -#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ -#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ -#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ -#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ -#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ -#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ -#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ /* Bit fields for I2C RXDATAP */ -#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ -#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ -#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ -#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ -#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ -#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ +#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ +#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ +#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ /* Bit fields for I2C RXDOUBLEP */ -#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ -#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ -#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ -#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ -#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ -#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ -#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ -#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ -#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ -#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ /* Bit fields for I2C TXDATA */ -#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ -#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ -#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ -#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ -#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ -#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ +#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ +#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ +#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ /* Bit fields for I2C TXDOUBLE */ -#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ -#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ -#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ -#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ -#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ -#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ -#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ -#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ -#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ -#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ /* Bit fields for I2C IF */ -#define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */ -#define _I2C_IF_MASK 0x001FFFFFUL /**< Mask for I2C_IF */ -#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ -#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ -#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ -#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ -#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ -#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ -#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ -#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ -#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ -#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ -#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ -#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ -#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ -#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ -#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ -#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ -#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ -#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ -#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ -#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ -#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ -#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ -#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ -#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ -#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ -#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ -#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ -#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ -#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ -#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ -#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ -#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ -#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ -#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ -#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ -#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ -#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ -#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ -#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ -#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ -#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ -#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ -#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ -#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ -#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ -#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ -#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ -#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ -#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ -#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ -#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ -#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ -#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ -#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ -#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ -#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ -#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ -#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ -#define _I2C_IF_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ -#define _I2C_IF_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ -#define _I2C_IF_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_SCLERR_DEFAULT (_I2C_IF_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ -#define _I2C_IF_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ -#define _I2C_IF_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ -#define _I2C_IF_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_SDAERR_DEFAULT (_I2C_IF_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IF */ +#define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */ +#define _I2C_IF_MASK 0x001FFFFFUL /**< Mask for I2C_IF */ +#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IF_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IF_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IF_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR_DEFAULT (_I2C_IF_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IF_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IF_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IF_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR_DEFAULT (_I2C_IF_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IF */ /* Bit fields for I2C IEN */ -#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ -#define _I2C_IEN_MASK 0x001FFFFFUL /**< Mask for I2C_IEN */ -#define I2C_IEN_START (0x1UL << 0) /**< START condition Interrupt Flag */ -#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ -#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ -#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ -#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ -#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ -#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ -#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ -#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ -#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ -#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ -#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ -#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ -#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ -#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ -#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ -#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ -#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ -#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ -#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ -#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ -#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ -#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ -#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ -#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ -#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ -#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ -#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ -#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ -#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ -#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ -#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ -#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ -#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ -#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ -#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ -#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ -#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ -#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ -#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ -#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ -#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ -#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ -#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ -#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ -#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ -#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ -#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ -#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ -#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ -#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ -#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ -#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ -#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ -#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ -#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ -#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ -#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ -#define _I2C_IEN_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ -#define _I2C_IEN_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ -#define _I2C_IEN_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SCLERR_DEFAULT (_I2C_IEN_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ -#define _I2C_IEN_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ -#define _I2C_IEN_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ -#define _I2C_IEN_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SDAERR_DEFAULT (_I2C_IEN_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IEN */ +#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ +#define _I2C_IEN_MASK 0x001FFFFFUL /**< Mask for I2C_IEN */ +#define I2C_IEN_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IEN_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR_DEFAULT (_I2C_IEN_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IEN_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR_DEFAULT (_I2C_IEN_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IEN */ /** @} End of group EFR32SG28_I2C_BitFields */ /** @} End of group EFR32SG28_I2C */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_iadc.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_iadc.h index 5d8e8a25d7..309776479e 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_iadc.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_iadc.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_IADC_H #define EFR32SG28_IADC_H - #define IADC_HAS_SET_CLEAR /**************************************************************************//** @@ -43,152 +42,147 @@ *****************************************************************************/ /** IADC CFG Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t CFG; /**< Configuration */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t SCALE; /**< Scaling */ - __IOM uint32_t SCHED; /**< Scheduling */ +typedef struct { + __IOM uint32_t CFG; /**< Configuration */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t SCALE; /**< Scaling */ + __IOM uint32_t SCHED; /**< Scheduling */ } IADC_CFG_TypeDef; - /** IADC SCANTABLE Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t SCAN; /**< SCAN Entry */ +typedef struct { + __IOM uint32_t SCAN; /**< SCAN Entry */ } IADC_SCANTABLE_TypeDef; - /** IADC Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< Enable */ - __IOM uint32_t CTRL; /**< Control */ - __IOM uint32_t CMD; /**< Command */ - __IOM uint32_t TIMER; /**< Timer */ - __IM uint32_t STATUS; /**< Status */ - __IOM uint32_t MASKREQ; /**< Mask Request */ - __IM uint32_t STMASK; /**< Scan Table Mask */ - __IOM uint32_t CMPTHR; /**< Digital Window Comparator Threshold */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - __IOM uint32_t TRIGGER; /**< Trigger */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - uint32_t RESERVED1[5U]; /**< Reserved for future use */ - IADC_CFG_TypeDef CFG[2U]; /**< CFG */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IOM uint32_t SINGLEFIFOCFG; /**< Single FIFO Configuration */ - __IM uint32_t SINGLEFIFODATA; /**< Single FIFO DATA */ - __IM uint32_t SINGLEFIFOSTAT; /**< Single FIFO Status */ - __IM uint32_t SINGLEDATA; /**< Single Data */ - __IOM uint32_t SCANFIFOCFG; /**< Scan FIFO Configuration */ - __IM uint32_t SCANFIFODATA; /**< Scan FIFO Read Data */ - __IM uint32_t SCANFIFOSTAT; /**< Scan FIFO Status */ - __IM uint32_t SCANDATA; /**< Scan Data */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IOM uint32_t SINGLE; /**< Single Queue Port Selection */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - IADC_SCANTABLE_TypeDef SCANTABLE[16U]; /**< SCANTABLE */ - uint32_t RESERVED6[4U]; /**< Reserved for future use */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - uint32_t RESERVED8[963U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< Enable */ - __IOM uint32_t CTRL_SET; /**< Control */ - __IOM uint32_t CMD_SET; /**< Command */ - __IOM uint32_t TIMER_SET; /**< Timer */ - __IM uint32_t STATUS_SET; /**< Status */ - __IOM uint32_t MASKREQ_SET; /**< Mask Request */ - __IM uint32_t STMASK_SET; /**< Scan Table Mask */ - __IOM uint32_t CMPTHR_SET; /**< Digital Window Comparator Threshold */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - __IOM uint32_t TRIGGER_SET; /**< Trigger */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - uint32_t RESERVED10[5U]; /**< Reserved for future use */ - IADC_CFG_TypeDef CFG_SET[2U]; /**< CFG */ - uint32_t RESERVED11[2U]; /**< Reserved for future use */ - __IOM uint32_t SINGLEFIFOCFG_SET; /**< Single FIFO Configuration */ - __IM uint32_t SINGLEFIFODATA_SET; /**< Single FIFO DATA */ - __IM uint32_t SINGLEFIFOSTAT_SET; /**< Single FIFO Status */ - __IM uint32_t SINGLEDATA_SET; /**< Single Data */ - __IOM uint32_t SCANFIFOCFG_SET; /**< Scan FIFO Configuration */ - __IM uint32_t SCANFIFODATA_SET; /**< Scan FIFO Read Data */ - __IM uint32_t SCANFIFOSTAT_SET; /**< Scan FIFO Status */ - __IM uint32_t SCANDATA_SET; /**< Scan Data */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - uint32_t RESERVED13[1U]; /**< Reserved for future use */ - __IOM uint32_t SINGLE_SET; /**< Single Queue Port Selection */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - IADC_SCANTABLE_TypeDef SCANTABLE_SET[16U];/**< SCANTABLE */ - uint32_t RESERVED15[4U]; /**< Reserved for future use */ - uint32_t RESERVED16[1U]; /**< Reserved for future use */ - uint32_t RESERVED17[963U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< Enable */ - __IOM uint32_t CTRL_CLR; /**< Control */ - __IOM uint32_t CMD_CLR; /**< Command */ - __IOM uint32_t TIMER_CLR; /**< Timer */ - __IM uint32_t STATUS_CLR; /**< Status */ - __IOM uint32_t MASKREQ_CLR; /**< Mask Request */ - __IM uint32_t STMASK_CLR; /**< Scan Table Mask */ - __IOM uint32_t CMPTHR_CLR; /**< Digital Window Comparator Threshold */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - __IOM uint32_t TRIGGER_CLR; /**< Trigger */ - uint32_t RESERVED18[1U]; /**< Reserved for future use */ - uint32_t RESERVED19[5U]; /**< Reserved for future use */ - IADC_CFG_TypeDef CFG_CLR[2U]; /**< CFG */ - uint32_t RESERVED20[2U]; /**< Reserved for future use */ - __IOM uint32_t SINGLEFIFOCFG_CLR; /**< Single FIFO Configuration */ - __IM uint32_t SINGLEFIFODATA_CLR; /**< Single FIFO DATA */ - __IM uint32_t SINGLEFIFOSTAT_CLR; /**< Single FIFO Status */ - __IM uint32_t SINGLEDATA_CLR; /**< Single Data */ - __IOM uint32_t SCANFIFOCFG_CLR; /**< Scan FIFO Configuration */ - __IM uint32_t SCANFIFODATA_CLR; /**< Scan FIFO Read Data */ - __IM uint32_t SCANFIFOSTAT_CLR; /**< Scan FIFO Status */ - __IM uint32_t SCANDATA_CLR; /**< Scan Data */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - uint32_t RESERVED22[1U]; /**< Reserved for future use */ - __IOM uint32_t SINGLE_CLR; /**< Single Queue Port Selection */ - uint32_t RESERVED23[1U]; /**< Reserved for future use */ - IADC_SCANTABLE_TypeDef SCANTABLE_CLR[16U];/**< SCANTABLE */ - uint32_t RESERVED24[4U]; /**< Reserved for future use */ - uint32_t RESERVED25[1U]; /**< Reserved for future use */ - uint32_t RESERVED26[963U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< Enable */ - __IOM uint32_t CTRL_TGL; /**< Control */ - __IOM uint32_t CMD_TGL; /**< Command */ - __IOM uint32_t TIMER_TGL; /**< Timer */ - __IM uint32_t STATUS_TGL; /**< Status */ - __IOM uint32_t MASKREQ_TGL; /**< Mask Request */ - __IM uint32_t STMASK_TGL; /**< Scan Table Mask */ - __IOM uint32_t CMPTHR_TGL; /**< Digital Window Comparator Threshold */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - __IOM uint32_t TRIGGER_TGL; /**< Trigger */ - uint32_t RESERVED27[1U]; /**< Reserved for future use */ - uint32_t RESERVED28[5U]; /**< Reserved for future use */ - IADC_CFG_TypeDef CFG_TGL[2U]; /**< CFG */ - uint32_t RESERVED29[2U]; /**< Reserved for future use */ - __IOM uint32_t SINGLEFIFOCFG_TGL; /**< Single FIFO Configuration */ - __IM uint32_t SINGLEFIFODATA_TGL; /**< Single FIFO DATA */ - __IM uint32_t SINGLEFIFOSTAT_TGL; /**< Single FIFO Status */ - __IM uint32_t SINGLEDATA_TGL; /**< Single Data */ - __IOM uint32_t SCANFIFOCFG_TGL; /**< Scan FIFO Configuration */ - __IM uint32_t SCANFIFODATA_TGL; /**< Scan FIFO Read Data */ - __IM uint32_t SCANFIFOSTAT_TGL; /**< Scan FIFO Status */ - __IM uint32_t SCANDATA_TGL; /**< Scan Data */ - uint32_t RESERVED30[1U]; /**< Reserved for future use */ - uint32_t RESERVED31[1U]; /**< Reserved for future use */ - __IOM uint32_t SINGLE_TGL; /**< Single Queue Port Selection */ - uint32_t RESERVED32[1U]; /**< Reserved for future use */ - IADC_SCANTABLE_TypeDef SCANTABLE_TGL[16U];/**< SCANTABLE */ - uint32_t RESERVED33[4U]; /**< Reserved for future use */ - uint32_t RESERVED34[1U]; /**< Reserved for future use */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CTRL; /**< Control */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t TIMER; /**< Timer */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t MASKREQ; /**< Mask Request */ + __IM uint32_t STMASK; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER; /**< Trigger */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG[2U]; /**< CFG */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA; /**< Scan Data */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE; /**< Single Queue Port Selection */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE[16U]; /**< SCANTABLE */ + uint32_t RESERVED6[4U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CTRL_SET; /**< Control */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t TIMER_SET; /**< Timer */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t MASKREQ_SET; /**< Mask Request */ + __IM uint32_t STMASK_SET; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_SET; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_SET; /**< Trigger */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_SET[2U]; /**< CFG */ + uint32_t RESERVED11[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_SET; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_SET; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_SET; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_SET; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_SET; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_SET; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_SET; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_SET; /**< Scan Data */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_SET; /**< Single Queue Port Selection */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_SET[16U]; /**< SCANTABLE */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CTRL_CLR; /**< Control */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t TIMER_CLR; /**< Timer */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t MASKREQ_CLR; /**< Mask Request */ + __IM uint32_t STMASK_CLR; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_CLR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_CLR; /**< Trigger */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_CLR[2U]; /**< CFG */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_CLR; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_CLR; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_CLR; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_CLR; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_CLR; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_CLR; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_CLR; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_CLR; /**< Scan Data */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_CLR; /**< Single Queue Port Selection */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_CLR[16U]; /**< SCANTABLE */ + uint32_t RESERVED24[4U]; /**< Reserved for future use */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + uint32_t RESERVED26[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CTRL_TGL; /**< Control */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t TIMER_TGL; /**< Timer */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t MASKREQ_TGL; /**< Mask Request */ + __IM uint32_t STMASK_TGL; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_TGL; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_TGL; /**< Trigger */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_TGL[2U]; /**< CFG */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_TGL; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_TGL; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_TGL; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_TGL; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_TGL; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_TGL; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_TGL; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_TGL; /**< Scan Data */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + uint32_t RESERVED31[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_TGL; /**< Single Queue Port Selection */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_TGL[16U]; /**< SCANTABLE */ + uint32_t RESERVED33[4U]; /**< Reserved for future use */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ } IADC_TypeDef; /** @} End of group EFR32SG28_IADC */ @@ -200,856 +194,856 @@ typedef struct *****************************************************************************/ /* Bit fields for IADC IPVERSION */ -#define _IADC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for IADC_IPVERSION */ -#define _IADC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for IADC_IPVERSION */ -#define _IADC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for IADC_IPVERSION */ -#define _IADC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_IPVERSION */ -#define _IADC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_IPVERSION */ -#define IADC_IPVERSION_IPVERSION_DEFAULT (_IADC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IPVERSION */ +#define _IADC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for IADC_IPVERSION */ +#define _IADC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_IPVERSION */ +#define IADC_IPVERSION_IPVERSION_DEFAULT (_IADC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IPVERSION */ /* Bit fields for IADC EN */ -#define _IADC_EN_RESETVALUE 0x00000000UL /**< Default value for IADC_EN */ -#define _IADC_EN_MASK 0x00000003UL /**< Mask for IADC_EN */ -#define IADC_EN_EN (0x1UL << 0) /**< Enable IADC Module */ -#define _IADC_EN_EN_SHIFT 0 /**< Shift value for IADC_EN */ -#define _IADC_EN_EN_MASK 0x1UL /**< Bit mask for IADC_EN */ -#define _IADC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ -#define _IADC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for IADC_EN */ -#define _IADC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for IADC_EN */ -#define IADC_EN_EN_DEFAULT (_IADC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_EN */ -#define IADC_EN_EN_DISABLE (_IADC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for IADC_EN */ -#define IADC_EN_EN_ENABLE (_IADC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for IADC_EN */ -#define IADC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _IADC_EN_DISABLING_SHIFT 1 /**< Shift value for IADC_DISABLING */ -#define _IADC_EN_DISABLING_MASK 0x2UL /**< Bit mask for IADC_DISABLING */ -#define _IADC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ -#define IADC_EN_DISABLING_DEFAULT (_IADC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_EN */ +#define _IADC_EN_RESETVALUE 0x00000000UL /**< Default value for IADC_EN */ +#define _IADC_EN_MASK 0x00000003UL /**< Mask for IADC_EN */ +#define IADC_EN_EN (0x1UL << 0) /**< Enable IADC Module */ +#define _IADC_EN_EN_SHIFT 0 /**< Shift value for IADC_EN */ +#define _IADC_EN_EN_MASK 0x1UL /**< Bit mask for IADC_EN */ +#define _IADC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ +#define _IADC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for IADC_EN */ +#define _IADC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for IADC_EN */ +#define IADC_EN_EN_DEFAULT (_IADC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_EN */ +#define IADC_EN_EN_DISABLE (_IADC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for IADC_EN */ +#define IADC_EN_EN_ENABLE (_IADC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for IADC_EN */ +#define IADC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _IADC_EN_DISABLING_SHIFT 1 /**< Shift value for IADC_DISABLING */ +#define _IADC_EN_DISABLING_MASK 0x2UL /**< Bit mask for IADC_DISABLING */ +#define _IADC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ +#define IADC_EN_DISABLING_DEFAULT (_IADC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_EN */ /* Bit fields for IADC CTRL */ -#define _IADC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IADC_CTRL */ -#define _IADC_CTRL_MASK 0x707F003FUL /**< Mask for IADC_CTRL */ -#define IADC_CTRL_EM23WUCONVERT (0x1UL << 0) /**< EM23 Wakeup on Conversion */ -#define _IADC_CTRL_EM23WUCONVERT_SHIFT 0 /**< Shift value for IADC_EM23WUCONVERT */ -#define _IADC_CTRL_EM23WUCONVERT_MASK 0x1UL /**< Bit mask for IADC_EM23WUCONVERT */ -#define _IADC_CTRL_EM23WUCONVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_EM23WUCONVERT_WUDVL 0x00000000UL /**< Mode WUDVL for IADC_CTRL */ -#define _IADC_CTRL_EM23WUCONVERT_WUCONVERT 0x00000001UL /**< Mode WUCONVERT for IADC_CTRL */ -#define IADC_CTRL_EM23WUCONVERT_DEFAULT (_IADC_CTRL_EM23WUCONVERT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_EM23WUCONVERT_WUDVL (_IADC_CTRL_EM23WUCONVERT_WUDVL << 0) /**< Shifted mode WUDVL for IADC_CTRL */ -#define IADC_CTRL_EM23WUCONVERT_WUCONVERT (_IADC_CTRL_EM23WUCONVERT_WUCONVERT << 0) /**< Shifted mode WUCONVERT for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND0 (0x1UL << 1) /**< ADC_CLK Suspend - PRS0 */ -#define _IADC_CTRL_ADCCLKSUSPEND0_SHIFT 1 /**< Shift value for IADC_ADCCLKSUSPEND0 */ -#define _IADC_CTRL_ADCCLKSUSPEND0_MASK 0x2UL /**< Bit mask for IADC_ADCCLKSUSPEND0 */ -#define _IADC_CTRL_ADCCLKSUSPEND0_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ -#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND0_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND0_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS << 1) /**< Shifted mode PRSWUDIS for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN << 1) /**< Shifted mode PRSWUEN for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND1 (0x1UL << 2) /**< ADC_CLK Suspend - PRS1 */ -#define _IADC_CTRL_ADCCLKSUSPEND1_SHIFT 2 /**< Shift value for IADC_ADCCLKSUSPEND1 */ -#define _IADC_CTRL_ADCCLKSUSPEND1_MASK 0x4UL /**< Bit mask for IADC_ADCCLKSUSPEND1 */ -#define _IADC_CTRL_ADCCLKSUSPEND1_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ -#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND1_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND1_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS << 2) /**< Shifted mode PRSWUDIS for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN << 2) /**< Shifted mode PRSWUEN for IADC_CTRL */ -#define IADC_CTRL_DBGHALT (0x1UL << 3) /**< Debug Halt */ -#define _IADC_CTRL_DBGHALT_SHIFT 3 /**< Shift value for IADC_DBGHALT */ -#define _IADC_CTRL_DBGHALT_MASK 0x8UL /**< Bit mask for IADC_DBGHALT */ -#define _IADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ -#define _IADC_CTRL_DBGHALT_HALT 0x00000001UL /**< Mode HALT for IADC_CTRL */ -#define IADC_CTRL_DBGHALT_DEFAULT (_IADC_CTRL_DBGHALT_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_DBGHALT_NORMAL (_IADC_CTRL_DBGHALT_NORMAL << 3) /**< Shifted mode NORMAL for IADC_CTRL */ -#define IADC_CTRL_DBGHALT_HALT (_IADC_CTRL_DBGHALT_HALT << 3) /**< Shifted mode HALT for IADC_CTRL */ -#define _IADC_CTRL_WARMUPMODE_SHIFT 4 /**< Shift value for IADC_WARMUPMODE */ -#define _IADC_CTRL_WARMUPMODE_MASK 0x30UL /**< Bit mask for IADC_WARMUPMODE */ -#define _IADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ -#define _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for IADC_CTRL */ -#define _IADC_CTRL_WARMUPMODE_KEEPWARM 0x00000002UL /**< Mode KEEPWARM for IADC_CTRL */ -#define IADC_CTRL_WARMUPMODE_DEFAULT (_IADC_CTRL_WARMUPMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_WARMUPMODE_NORMAL (_IADC_CTRL_WARMUPMODE_NORMAL << 4) /**< Shifted mode NORMAL for IADC_CTRL */ -#define IADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_IADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 4) /**< Shifted mode KEEPINSTANDBY for IADC_CTRL */ -#define IADC_CTRL_WARMUPMODE_KEEPWARM (_IADC_CTRL_WARMUPMODE_KEEPWARM << 4) /**< Shifted mode KEEPWARM for IADC_CTRL */ -#define _IADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for IADC_TIMEBASE */ -#define _IADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for IADC_TIMEBASE */ -#define _IADC_CTRL_TIMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_TIMEBASE_DEFAULT (_IADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_SHIFT 28 /**< Shift value for IADC_HSCLKRATE */ -#define _IADC_CTRL_HSCLKRATE_MASK 0x70000000UL /**< Bit mask for IADC_HSCLKRATE */ -#define _IADC_CTRL_HSCLKRATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_DIV1 0x00000000UL /**< Mode DIV1 for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_DIV2 0x00000001UL /**< Mode DIV2 for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_DIV3 0x00000002UL /**< Mode DIV3 for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_DIV4 0x00000003UL /**< Mode DIV4 for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DEFAULT (_IADC_CTRL_HSCLKRATE_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DIV1 (_IADC_CTRL_HSCLKRATE_DIV1 << 28) /**< Shifted mode DIV1 for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DIV2 (_IADC_CTRL_HSCLKRATE_DIV2 << 28) /**< Shifted mode DIV2 for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DIV3 (_IADC_CTRL_HSCLKRATE_DIV3 << 28) /**< Shifted mode DIV3 for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DIV4 (_IADC_CTRL_HSCLKRATE_DIV4 << 28) /**< Shifted mode DIV4 for IADC_CTRL */ +#define _IADC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IADC_CTRL */ +#define _IADC_CTRL_MASK 0x707F003FUL /**< Mask for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT (0x1UL << 0) /**< EM23 Wakeup on Conversion */ +#define _IADC_CTRL_EM23WUCONVERT_SHIFT 0 /**< Shift value for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_MASK 0x1UL /**< Bit mask for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUDVL 0x00000000UL /**< Mode WUDVL for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUCONVERT 0x00000001UL /**< Mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_DEFAULT (_IADC_CTRL_EM23WUCONVERT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUDVL (_IADC_CTRL_EM23WUCONVERT_WUDVL << 0) /**< Shifted mode WUDVL for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUCONVERT (_IADC_CTRL_EM23WUCONVERT_WUCONVERT << 0) /**< Shifted mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0 (0x1UL << 1) /**< ADC_CLK Suspend - PRS0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_SHIFT 1 /**< Shift value for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_MASK 0x2UL /**< Bit mask for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND0_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS << 1) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN << 1) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1 (0x1UL << 2) /**< ADC_CLK Suspend - PRS1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_SHIFT 2 /**< Shift value for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_MASK 0x4UL /**< Bit mask for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND1_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS << 2) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN << 2) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_DBGHALT (0x1UL << 3) /**< Debug Halt */ +#define _IADC_CTRL_DBGHALT_SHIFT 3 /**< Shift value for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_MASK 0x8UL /**< Bit mask for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_HALT 0x00000001UL /**< Mode HALT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_DEFAULT (_IADC_CTRL_DBGHALT_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_NORMAL (_IADC_CTRL_DBGHALT_NORMAL << 3) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_HALT (_IADC_CTRL_DBGHALT_HALT << 3) /**< Shifted mode HALT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_SHIFT 4 /**< Shift value for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_MASK 0x30UL /**< Bit mask for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPWARM 0x00000002UL /**< Mode KEEPWARM for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_DEFAULT (_IADC_CTRL_WARMUPMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_NORMAL (_IADC_CTRL_WARMUPMODE_NORMAL << 4) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_IADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 4) /**< Shifted mode KEEPINSTANDBY for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPWARM (_IADC_CTRL_WARMUPMODE_KEEPWARM << 4) /**< Shifted mode KEEPWARM for IADC_CTRL */ +#define _IADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_TIMEBASE_DEFAULT (_IADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_SHIFT 28 /**< Shift value for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_MASK 0x70000000UL /**< Bit mask for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV1 0x00000000UL /**< Mode DIV1 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV2 0x00000001UL /**< Mode DIV2 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV3 0x00000002UL /**< Mode DIV3 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV4 0x00000003UL /**< Mode DIV4 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DEFAULT (_IADC_CTRL_HSCLKRATE_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV1 (_IADC_CTRL_HSCLKRATE_DIV1 << 28) /**< Shifted mode DIV1 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV2 (_IADC_CTRL_HSCLKRATE_DIV2 << 28) /**< Shifted mode DIV2 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV3 (_IADC_CTRL_HSCLKRATE_DIV3 << 28) /**< Shifted mode DIV3 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV4 (_IADC_CTRL_HSCLKRATE_DIV4 << 28) /**< Shifted mode DIV4 for IADC_CTRL */ /* Bit fields for IADC CMD */ -#define _IADC_CMD_RESETVALUE 0x00000000UL /**< Default value for IADC_CMD */ -#define _IADC_CMD_MASK 0x0303001BUL /**< Mask for IADC_CMD */ -#define IADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Queue Start */ -#define _IADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for IADC_SINGLESTART */ -#define _IADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for IADC_SINGLESTART */ -#define _IADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLESTART_DEFAULT (_IADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Queue Stop */ -#define _IADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for IADC_SINGLESTOP */ -#define _IADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for IADC_SINGLESTOP */ -#define _IADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLESTOP_DEFAULT (_IADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANSTART (0x1UL << 3) /**< Scan Queue Start */ -#define _IADC_CMD_SCANSTART_SHIFT 3 /**< Shift value for IADC_SCANSTART */ -#define _IADC_CMD_SCANSTART_MASK 0x8UL /**< Bit mask for IADC_SCANSTART */ -#define _IADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANSTART_DEFAULT (_IADC_CMD_SCANSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANSTOP (0x1UL << 4) /**< Scan Queue Stop */ -#define _IADC_CMD_SCANSTOP_SHIFT 4 /**< Shift value for IADC_SCANSTOP */ -#define _IADC_CMD_SCANSTOP_MASK 0x10UL /**< Bit mask for IADC_SCANSTOP */ -#define _IADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANSTOP_DEFAULT (_IADC_CMD_SCANSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_TIMEREN (0x1UL << 16) /**< Timer Enable */ -#define _IADC_CMD_TIMEREN_SHIFT 16 /**< Shift value for IADC_TIMEREN */ -#define _IADC_CMD_TIMEREN_MASK 0x10000UL /**< Bit mask for IADC_TIMEREN */ -#define _IADC_CMD_TIMEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_TIMEREN_DEFAULT (_IADC_CMD_TIMEREN_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_TIMERDIS (0x1UL << 17) /**< Timer Disable */ -#define _IADC_CMD_TIMERDIS_SHIFT 17 /**< Shift value for IADC_TIMERDIS */ -#define _IADC_CMD_TIMERDIS_MASK 0x20000UL /**< Bit mask for IADC_TIMERDIS */ -#define _IADC_CMD_TIMERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_TIMERDIS_DEFAULT (_IADC_CMD_TIMERDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLEFIFOFLUSH (0x1UL << 24) /**< Flush the Single FIFO */ -#define _IADC_CMD_SINGLEFIFOFLUSH_SHIFT 24 /**< Shift value for IADC_SINGLEFIFOFLUSH */ -#define _IADC_CMD_SINGLEFIFOFLUSH_MASK 0x1000000UL /**< Bit mask for IADC_SINGLEFIFOFLUSH */ -#define _IADC_CMD_SINGLEFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLEFIFOFLUSH_DEFAULT (_IADC_CMD_SINGLEFIFOFLUSH_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANFIFOFLUSH (0x1UL << 25) /**< Flush the Scan FIFO */ -#define _IADC_CMD_SCANFIFOFLUSH_SHIFT 25 /**< Shift value for IADC_SCANFIFOFLUSH */ -#define _IADC_CMD_SCANFIFOFLUSH_MASK 0x2000000UL /**< Bit mask for IADC_SCANFIFOFLUSH */ -#define _IADC_CMD_SCANFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANFIFOFLUSH_DEFAULT (_IADC_CMD_SCANFIFOFLUSH_DEFAULT << 25) /**< Shifted mode DEFAULT for IADC_CMD */ +#define _IADC_CMD_RESETVALUE 0x00000000UL /**< Default value for IADC_CMD */ +#define _IADC_CMD_MASK 0x0303001BUL /**< Mask for IADC_CMD */ +#define IADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Queue Start */ +#define _IADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTART_DEFAULT (_IADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Queue Stop */ +#define _IADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP_DEFAULT (_IADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART (0x1UL << 3) /**< Scan Queue Start */ +#define _IADC_CMD_SCANSTART_SHIFT 3 /**< Shift value for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_MASK 0x8UL /**< Bit mask for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART_DEFAULT (_IADC_CMD_SCANSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP (0x1UL << 4) /**< Scan Queue Stop */ +#define _IADC_CMD_SCANSTOP_SHIFT 4 /**< Shift value for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_MASK 0x10UL /**< Bit mask for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP_DEFAULT (_IADC_CMD_SCANSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN (0x1UL << 16) /**< Timer Enable */ +#define _IADC_CMD_TIMEREN_SHIFT 16 /**< Shift value for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_MASK 0x10000UL /**< Bit mask for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN_DEFAULT (_IADC_CMD_TIMEREN_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS (0x1UL << 17) /**< Timer Disable */ +#define _IADC_CMD_TIMERDIS_SHIFT 17 /**< Shift value for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_MASK 0x20000UL /**< Bit mask for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS_DEFAULT (_IADC_CMD_TIMERDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH (0x1UL << 24) /**< Flush the Single FIFO */ +#define _IADC_CMD_SINGLEFIFOFLUSH_SHIFT 24 /**< Shift value for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_MASK 0x1000000UL /**< Bit mask for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH_DEFAULT (_IADC_CMD_SINGLEFIFOFLUSH_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH (0x1UL << 25) /**< Flush the Scan FIFO */ +#define _IADC_CMD_SCANFIFOFLUSH_SHIFT 25 /**< Shift value for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_MASK 0x2000000UL /**< Bit mask for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH_DEFAULT (_IADC_CMD_SCANFIFOFLUSH_DEFAULT << 25) /**< Shifted mode DEFAULT for IADC_CMD */ /* Bit fields for IADC TIMER */ -#define _IADC_TIMER_RESETVALUE 0x00000000UL /**< Default value for IADC_TIMER */ -#define _IADC_TIMER_MASK 0x0000FFFFUL /**< Mask for IADC_TIMER */ -#define _IADC_TIMER_TIMER_SHIFT 0 /**< Shift value for IADC_TIMER */ -#define _IADC_TIMER_TIMER_MASK 0xFFFFUL /**< Bit mask for IADC_TIMER */ -#define _IADC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TIMER */ -#define IADC_TIMER_TIMER_DEFAULT (_IADC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TIMER */ +#define _IADC_TIMER_RESETVALUE 0x00000000UL /**< Default value for IADC_TIMER */ +#define _IADC_TIMER_MASK 0x0000FFFFUL /**< Mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_SHIFT 0 /**< Shift value for IADC_TIMER */ +#define _IADC_TIMER_TIMER_MASK 0xFFFFUL /**< Bit mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TIMER */ +#define IADC_TIMER_TIMER_DEFAULT (_IADC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TIMER */ /* Bit fields for IADC STATUS */ -#define _IADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IADC_STATUS */ -#define _IADC_STATUS_MASK 0x4131CF5BUL /**< Mask for IADC_STATUS */ -#define IADC_STATUS_SINGLEQEN (0x1UL << 0) /**< Single Queue Enabled */ -#define _IADC_STATUS_SINGLEQEN_SHIFT 0 /**< Shift value for IADC_SINGLEQEN */ -#define _IADC_STATUS_SINGLEQEN_MASK 0x1UL /**< Bit mask for IADC_SINGLEQEN */ -#define _IADC_STATUS_SINGLEQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEQEN_DEFAULT (_IADC_STATUS_SINGLEQEN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEQUEUEPENDING (0x1UL << 1) /**< Single Queue Pending */ -#define _IADC_STATUS_SINGLEQUEUEPENDING_SHIFT 1 /**< Shift value for IADC_SINGLEQUEUEPENDING */ -#define _IADC_STATUS_SINGLEQUEUEPENDING_MASK 0x2UL /**< Bit mask for IADC_SINGLEQUEUEPENDING */ -#define _IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT (_IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANQEN (0x1UL << 3) /**< Scan Queued Enabled */ -#define _IADC_STATUS_SCANQEN_SHIFT 3 /**< Shift value for IADC_SCANQEN */ -#define _IADC_STATUS_SCANQEN_MASK 0x8UL /**< Bit mask for IADC_SCANQEN */ -#define _IADC_STATUS_SCANQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANQEN_DEFAULT (_IADC_STATUS_SCANQEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANQUEUEPENDING (0x1UL << 4) /**< Scan Queue Pending */ -#define _IADC_STATUS_SCANQUEUEPENDING_SHIFT 4 /**< Shift value for IADC_SCANQUEUEPENDING */ -#define _IADC_STATUS_SCANQUEUEPENDING_MASK 0x10UL /**< Bit mask for IADC_SCANQUEUEPENDING */ -#define _IADC_STATUS_SCANQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANQUEUEPENDING_DEFAULT (_IADC_STATUS_SCANQUEUEPENDING_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_CONVERTING (0x1UL << 6) /**< Converting */ -#define _IADC_STATUS_CONVERTING_SHIFT 6 /**< Shift value for IADC_CONVERTING */ -#define _IADC_STATUS_CONVERTING_MASK 0x40UL /**< Bit mask for IADC_CONVERTING */ -#define _IADC_STATUS_CONVERTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_CONVERTING_DEFAULT (_IADC_STATUS_CONVERTING_DEFAULT << 6) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEFIFODV (0x1UL << 8) /**< SINGLEFIFO Data Valid */ -#define _IADC_STATUS_SINGLEFIFODV_SHIFT 8 /**< Shift value for IADC_SINGLEFIFODV */ -#define _IADC_STATUS_SINGLEFIFODV_MASK 0x100UL /**< Bit mask for IADC_SINGLEFIFODV */ -#define _IADC_STATUS_SINGLEFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEFIFODV_DEFAULT (_IADC_STATUS_SINGLEFIFODV_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANFIFODV (0x1UL << 9) /**< SCANFIFO Data Valid */ -#define _IADC_STATUS_SCANFIFODV_SHIFT 9 /**< Shift value for IADC_SCANFIFODV */ -#define _IADC_STATUS_SCANFIFODV_MASK 0x200UL /**< Bit mask for IADC_SCANFIFODV */ -#define _IADC_STATUS_SCANFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANFIFODV_DEFAULT (_IADC_STATUS_SCANFIFODV_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEFIFOFLUSHING (0x1UL << 14) /**< The Single FIFO is flushing */ -#define _IADC_STATUS_SINGLEFIFOFLUSHING_SHIFT 14 /**< Shift value for IADC_SINGLEFIFOFLUSHING */ -#define _IADC_STATUS_SINGLEFIFOFLUSHING_MASK 0x4000UL /**< Bit mask for IADC_SINGLEFIFOFLUSHING */ -#define _IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT (_IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT << 14) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANFIFOFLUSHING (0x1UL << 15) /**< The Scan FIFO is flushing */ -#define _IADC_STATUS_SCANFIFOFLUSHING_SHIFT 15 /**< Shift value for IADC_SCANFIFOFLUSHING */ -#define _IADC_STATUS_SCANFIFOFLUSHING_MASK 0x8000UL /**< Bit mask for IADC_SCANFIFOFLUSHING */ -#define _IADC_STATUS_SCANFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANFIFOFLUSHING_DEFAULT (_IADC_STATUS_SCANFIFOFLUSHING_DEFAULT << 15) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_TIMERACTIVE (0x1UL << 16) /**< Timer Active */ -#define _IADC_STATUS_TIMERACTIVE_SHIFT 16 /**< Shift value for IADC_TIMERACTIVE */ -#define _IADC_STATUS_TIMERACTIVE_MASK 0x10000UL /**< Bit mask for IADC_TIMERACTIVE */ -#define _IADC_STATUS_TIMERACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_TIMERACTIVE_DEFAULT (_IADC_STATUS_TIMERACTIVE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEWRITEPENDING (0x1UL << 20) /**< SINGLE write pending */ -#define _IADC_STATUS_SINGLEWRITEPENDING_SHIFT 20 /**< Shift value for IADC_SINGLEWRITEPENDING */ -#define _IADC_STATUS_SINGLEWRITEPENDING_MASK 0x100000UL /**< Bit mask for IADC_SINGLEWRITEPENDING */ -#define _IADC_STATUS_SINGLEWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEWRITEPENDING_DEFAULT (_IADC_STATUS_SINGLEWRITEPENDING_DEFAULT << 20) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_MASKREQWRITEPENDING (0x1UL << 21) /**< MASKREQ write pending */ -#define _IADC_STATUS_MASKREQWRITEPENDING_SHIFT 21 /**< Shift value for IADC_MASKREQWRITEPENDING */ -#define _IADC_STATUS_MASKREQWRITEPENDING_MASK 0x200000UL /**< Bit mask for IADC_MASKREQWRITEPENDING */ -#define _IADC_STATUS_MASKREQWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_MASKREQWRITEPENDING_DEFAULT (_IADC_STATUS_MASKREQWRITEPENDING_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SYNCBUSY (0x1UL << 24) /**< SYNCBUSY */ -#define _IADC_STATUS_SYNCBUSY_SHIFT 24 /**< Shift value for IADC_SYNCBUSY */ -#define _IADC_STATUS_SYNCBUSY_MASK 0x1000000UL /**< Bit mask for IADC_SYNCBUSY */ -#define _IADC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SYNCBUSY_DEFAULT (_IADC_STATUS_SYNCBUSY_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_ADCWARM (0x1UL << 30) /**< ADCWARM */ -#define _IADC_STATUS_ADCWARM_SHIFT 30 /**< Shift value for IADC_ADCWARM */ -#define _IADC_STATUS_ADCWARM_MASK 0x40000000UL /**< Bit mask for IADC_ADCWARM */ -#define _IADC_STATUS_ADCWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_ADCWARM_DEFAULT (_IADC_STATUS_ADCWARM_DEFAULT << 30) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define _IADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IADC_STATUS */ +#define _IADC_STATUS_MASK 0x4131CF5BUL /**< Mask for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN (0x1UL << 0) /**< Single Queue Enabled */ +#define _IADC_STATUS_SINGLEQEN_SHIFT 0 /**< Shift value for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_MASK 0x1UL /**< Bit mask for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN_DEFAULT (_IADC_STATUS_SINGLEQEN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING (0x1UL << 1) /**< Single Queue Pending */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_SHIFT 1 /**< Shift value for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_MASK 0x2UL /**< Bit mask for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT (_IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN (0x1UL << 3) /**< Scan Queued Enabled */ +#define _IADC_STATUS_SCANQEN_SHIFT 3 /**< Shift value for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_MASK 0x8UL /**< Bit mask for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN_DEFAULT (_IADC_STATUS_SCANQEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING (0x1UL << 4) /**< Scan Queue Pending */ +#define _IADC_STATUS_SCANQUEUEPENDING_SHIFT 4 /**< Shift value for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_MASK 0x10UL /**< Bit mask for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING_DEFAULT (_IADC_STATUS_SCANQUEUEPENDING_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING (0x1UL << 6) /**< Converting */ +#define _IADC_STATUS_CONVERTING_SHIFT 6 /**< Shift value for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_MASK 0x40UL /**< Bit mask for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING_DEFAULT (_IADC_STATUS_CONVERTING_DEFAULT << 6) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV (0x1UL << 8) /**< SINGLEFIFO Data Valid */ +#define _IADC_STATUS_SINGLEFIFODV_SHIFT 8 /**< Shift value for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_MASK 0x100UL /**< Bit mask for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV_DEFAULT (_IADC_STATUS_SINGLEFIFODV_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV (0x1UL << 9) /**< SCANFIFO Data Valid */ +#define _IADC_STATUS_SCANFIFODV_SHIFT 9 /**< Shift value for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_MASK 0x200UL /**< Bit mask for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV_DEFAULT (_IADC_STATUS_SCANFIFODV_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING (0x1UL << 14) /**< The Single FIFO is flushing */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_SHIFT 14 /**< Shift value for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_MASK 0x4000UL /**< Bit mask for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT (_IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT << 14) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING (0x1UL << 15) /**< The Scan FIFO is flushing */ +#define _IADC_STATUS_SCANFIFOFLUSHING_SHIFT 15 /**< Shift value for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_MASK 0x8000UL /**< Bit mask for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING_DEFAULT (_IADC_STATUS_SCANFIFOFLUSHING_DEFAULT << 15) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE (0x1UL << 16) /**< Timer Active */ +#define _IADC_STATUS_TIMERACTIVE_SHIFT 16 /**< Shift value for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_MASK 0x10000UL /**< Bit mask for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE_DEFAULT (_IADC_STATUS_TIMERACTIVE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING (0x1UL << 20) /**< SINGLE write pending */ +#define _IADC_STATUS_SINGLEWRITEPENDING_SHIFT 20 /**< Shift value for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_MASK 0x100000UL /**< Bit mask for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING_DEFAULT (_IADC_STATUS_SINGLEWRITEPENDING_DEFAULT << 20) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING (0x1UL << 21) /**< MASKREQ write pending */ +#define _IADC_STATUS_MASKREQWRITEPENDING_SHIFT 21 /**< Shift value for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_MASK 0x200000UL /**< Bit mask for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING_DEFAULT (_IADC_STATUS_MASKREQWRITEPENDING_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY (0x1UL << 24) /**< SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_SHIFT 24 /**< Shift value for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_MASK 0x1000000UL /**< Bit mask for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY_DEFAULT (_IADC_STATUS_SYNCBUSY_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM (0x1UL << 30) /**< ADCWARM */ +#define _IADC_STATUS_ADCWARM_SHIFT 30 /**< Shift value for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_MASK 0x40000000UL /**< Bit mask for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM_DEFAULT (_IADC_STATUS_ADCWARM_DEFAULT << 30) /**< Shifted mode DEFAULT for IADC_STATUS */ /* Bit fields for IADC MASKREQ */ -#define _IADC_MASKREQ_RESETVALUE 0x00000000UL /**< Default value for IADC_MASKREQ */ -#define _IADC_MASKREQ_MASK 0x0000FFFFUL /**< Mask for IADC_MASKREQ */ -#define _IADC_MASKREQ_MASKREQ_SHIFT 0 /**< Shift value for IADC_MASKREQ */ -#define _IADC_MASKREQ_MASKREQ_MASK 0xFFFFUL /**< Bit mask for IADC_MASKREQ */ -#define _IADC_MASKREQ_MASKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_MASKREQ */ -#define IADC_MASKREQ_MASKREQ_DEFAULT (_IADC_MASKREQ_MASKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_MASKREQ */ +#define _IADC_MASKREQ_RESETVALUE 0x00000000UL /**< Default value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASK 0x0000FFFFUL /**< Mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_SHIFT 0 /**< Shift value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_MASK 0xFFFFUL /**< Bit mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_MASKREQ */ +#define IADC_MASKREQ_MASKREQ_DEFAULT (_IADC_MASKREQ_MASKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_MASKREQ */ /* Bit fields for IADC STMASK */ -#define _IADC_STMASK_RESETVALUE 0x00000000UL /**< Default value for IADC_STMASK */ -#define _IADC_STMASK_MASK 0x0000FFFFUL /**< Mask for IADC_STMASK */ -#define _IADC_STMASK_STMASK_SHIFT 0 /**< Shift value for IADC_STMASK */ -#define _IADC_STMASK_STMASK_MASK 0xFFFFUL /**< Bit mask for IADC_STMASK */ -#define _IADC_STMASK_STMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STMASK */ -#define IADC_STMASK_STMASK_DEFAULT (_IADC_STMASK_STMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STMASK */ +#define _IADC_STMASK_RESETVALUE 0x00000000UL /**< Default value for IADC_STMASK */ +#define _IADC_STMASK_MASK 0x0000FFFFUL /**< Mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_SHIFT 0 /**< Shift value for IADC_STMASK */ +#define _IADC_STMASK_STMASK_MASK 0xFFFFUL /**< Bit mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STMASK */ +#define IADC_STMASK_STMASK_DEFAULT (_IADC_STMASK_STMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STMASK */ /* Bit fields for IADC CMPTHR */ -#define _IADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for IADC_CMPTHR */ -#define _IADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for IADC_CMPTHR */ -#define _IADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for IADC_ADLT */ -#define _IADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for IADC_ADLT */ -#define _IADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ -#define IADC_CMPTHR_ADLT_DEFAULT (_IADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMPTHR */ -#define _IADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for IADC_ADGT */ -#define _IADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for IADC_ADGT */ -#define _IADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ -#define IADC_CMPTHR_ADGT_DEFAULT (_IADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMPTHR */ +#define _IADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for IADC_CMPTHR */ +#define _IADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADLT_DEFAULT (_IADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADGT_DEFAULT (_IADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMPTHR */ /* Bit fields for IADC IF */ -#define _IADC_IF_RESETVALUE 0x00000000UL /**< Default value for IADC_IF */ -#define _IADC_IF_MASK 0x800F338FUL /**< Mask for IADC_IF */ -#define IADC_IF_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level */ -#define _IADC_IF_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ -#define _IADC_IF_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ -#define _IADC_IF_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFODVL_DEFAULT (_IADC_IF_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level */ -#define _IADC_IF_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ -#define _IADC_IF_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ -#define _IADC_IF_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFODVL_DEFAULT (_IADC_IF_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare */ -#define _IADC_IF_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ -#define _IADC_IF_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ -#define _IADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLECMP_DEFAULT (_IADC_IF_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare */ -#define _IADC_IF_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ -#define _IADC_IF_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ -#define _IADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANCMP_DEFAULT (_IADC_IF_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done */ -#define _IADC_IF_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ -#define _IADC_IF_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ -#define _IADC_IF_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANENTRYDONE_DEFAULT (_IADC_IF_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done */ -#define _IADC_IF_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ -#define _IADC_IF_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ -#define _IADC_IF_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANTABLEDONE_DEFAULT (_IADC_IF_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done */ -#define _IADC_IF_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ -#define _IADC_IF_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ -#define _IADC_IF_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEDONE_DEFAULT (_IADC_IF_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_POLARITYERR (0x1UL << 12) /**< Polarity Error */ -#define _IADC_IF_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ -#define _IADC_IF_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ -#define _IADC_IF_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_POLARITYERR_DEFAULT (_IADC_IF_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error */ -#define _IADC_IF_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ -#define _IADC_IF_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ -#define _IADC_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_PORTALLOCERR_DEFAULT (_IADC_IF_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow */ -#define _IADC_IF_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ -#define _IADC_IF_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ -#define _IADC_IF_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFOOF_DEFAULT (_IADC_IF_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow */ -#define _IADC_IF_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ -#define _IADC_IF_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ -#define _IADC_IF_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFOOF_DEFAULT (_IADC_IF_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow */ -#define _IADC_IF_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ -#define _IADC_IF_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ -#define _IADC_IF_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFOUF_DEFAULT (_IADC_IF_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow */ -#define _IADC_IF_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ -#define _IADC_IF_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ -#define _IADC_IF_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFOUF_DEFAULT (_IADC_IF_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error */ -#define _IADC_IF_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ -#define _IADC_IF_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ -#define _IADC_IF_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_EM23ABORTERROR_DEFAULT (_IADC_IF_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IF */ +#define _IADC_IF_RESETVALUE 0x00000000UL /**< Default value for IADC_IF */ +#define _IADC_IF_MASK 0x800F338FUL /**< Mask for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level */ +#define _IADC_IF_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL_DEFAULT (_IADC_IF_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level */ +#define _IADC_IF_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL_DEFAULT (_IADC_IF_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare */ +#define _IADC_IF_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP_DEFAULT (_IADC_IF_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare */ +#define _IADC_IF_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP_DEFAULT (_IADC_IF_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done */ +#define _IADC_IF_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE_DEFAULT (_IADC_IF_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done */ +#define _IADC_IF_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE_DEFAULT (_IADC_IF_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done */ +#define _IADC_IF_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE_DEFAULT (_IADC_IF_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR (0x1UL << 12) /**< Polarity Error */ +#define _IADC_IF_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR_DEFAULT (_IADC_IF_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error */ +#define _IADC_IF_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR_DEFAULT (_IADC_IF_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow */ +#define _IADC_IF_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF_DEFAULT (_IADC_IF_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow */ +#define _IADC_IF_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF_DEFAULT (_IADC_IF_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow */ +#define _IADC_IF_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF_DEFAULT (_IADC_IF_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow */ +#define _IADC_IF_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF_DEFAULT (_IADC_IF_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error */ +#define _IADC_IF_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR_DEFAULT (_IADC_IF_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IF */ /* Bit fields for IADC IEN */ -#define _IADC_IEN_RESETVALUE 0x00000000UL /**< Default value for IADC_IEN */ -#define _IADC_IEN_MASK 0x800F338FUL /**< Mask for IADC_IEN */ -#define IADC_IEN_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level Enable */ -#define _IADC_IEN_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ -#define _IADC_IEN_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ -#define _IADC_IEN_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFODVL_DEFAULT (_IADC_IEN_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level Enable */ -#define _IADC_IEN_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ -#define _IADC_IEN_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ -#define _IADC_IEN_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFODVL_DEFAULT (_IADC_IEN_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare Enable */ -#define _IADC_IEN_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ -#define _IADC_IEN_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ -#define _IADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLECMP_DEFAULT (_IADC_IEN_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare Enable */ -#define _IADC_IEN_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ -#define _IADC_IEN_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ -#define _IADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANCMP_DEFAULT (_IADC_IEN_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done Enable */ -#define _IADC_IEN_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ -#define _IADC_IEN_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ -#define _IADC_IEN_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANENTRYDONE_DEFAULT (_IADC_IEN_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done Enable */ -#define _IADC_IEN_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ -#define _IADC_IEN_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ -#define _IADC_IEN_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANTABLEDONE_DEFAULT (_IADC_IEN_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done Enable */ -#define _IADC_IEN_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ -#define _IADC_IEN_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ -#define _IADC_IEN_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEDONE_DEFAULT (_IADC_IEN_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_POLARITYERR (0x1UL << 12) /**< Polarity Error Enable */ -#define _IADC_IEN_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ -#define _IADC_IEN_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ -#define _IADC_IEN_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_POLARITYERR_DEFAULT (_IADC_IEN_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error Enable */ -#define _IADC_IEN_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ -#define _IADC_IEN_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ -#define _IADC_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_PORTALLOCERR_DEFAULT (_IADC_IEN_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow Enable */ -#define _IADC_IEN_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ -#define _IADC_IEN_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ -#define _IADC_IEN_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFOOF_DEFAULT (_IADC_IEN_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow Enable */ -#define _IADC_IEN_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ -#define _IADC_IEN_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ -#define _IADC_IEN_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFOOF_DEFAULT (_IADC_IEN_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow Enable */ -#define _IADC_IEN_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ -#define _IADC_IEN_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ -#define _IADC_IEN_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFOUF_DEFAULT (_IADC_IEN_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow Enable */ -#define _IADC_IEN_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ -#define _IADC_IEN_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ -#define _IADC_IEN_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFOUF_DEFAULT (_IADC_IEN_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error Enable */ -#define _IADC_IEN_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ -#define _IADC_IEN_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ -#define _IADC_IEN_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_EM23ABORTERROR_DEFAULT (_IADC_IEN_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IEN */ +#define _IADC_IEN_RESETVALUE 0x00000000UL /**< Default value for IADC_IEN */ +#define _IADC_IEN_MASK 0x800F338FUL /**< Mask for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level Enable */ +#define _IADC_IEN_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL_DEFAULT (_IADC_IEN_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level Enable */ +#define _IADC_IEN_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL_DEFAULT (_IADC_IEN_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare Enable */ +#define _IADC_IEN_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP_DEFAULT (_IADC_IEN_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare Enable */ +#define _IADC_IEN_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP_DEFAULT (_IADC_IEN_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done Enable */ +#define _IADC_IEN_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE_DEFAULT (_IADC_IEN_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done Enable */ +#define _IADC_IEN_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE_DEFAULT (_IADC_IEN_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done Enable */ +#define _IADC_IEN_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE_DEFAULT (_IADC_IEN_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR (0x1UL << 12) /**< Polarity Error Enable */ +#define _IADC_IEN_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR_DEFAULT (_IADC_IEN_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error Enable */ +#define _IADC_IEN_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR_DEFAULT (_IADC_IEN_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow Enable */ +#define _IADC_IEN_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF_DEFAULT (_IADC_IEN_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow Enable */ +#define _IADC_IEN_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF_DEFAULT (_IADC_IEN_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow Enable */ +#define _IADC_IEN_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF_DEFAULT (_IADC_IEN_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow Enable */ +#define _IADC_IEN_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF_DEFAULT (_IADC_IEN_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error Enable */ +#define _IADC_IEN_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR_DEFAULT (_IADC_IEN_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IEN */ /* Bit fields for IADC TRIGGER */ -#define _IADC_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for IADC_TRIGGER */ -#define _IADC_TRIGGER_MASK 0x00011717UL /**< Mask for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_SHIFT 0 /**< Shift value for IADC_SCANTRIGSEL */ -#define _IADC_TRIGGER_SCANTRIGSEL_MASK 0x7UL /**< Bit mask for IADC_SCANTRIGSEL */ -#define _IADC_TRIGGER_SCANTRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_LESENSE 0x00000005UL /**< Mode LESENSE for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_DEFAULT (_IADC_TRIGGER_SCANTRIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE (_IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE << 0) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_TIMER (_IADC_TRIGGER_SCANTRIGSEL_TIMER << 0) /**< Shifted mode TIMER for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP << 0) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_PRSPOS (_IADC_TRIGGER_SCANTRIGSEL_PRSPOS << 0) /**< Shifted mode PRSPOS for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_PRSNEG (_IADC_TRIGGER_SCANTRIGSEL_PRSNEG << 0) /**< Shifted mode PRSNEG for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_LESENSE (_IADC_TRIGGER_SCANTRIGSEL_LESENSE << 0) /**< Shifted mode LESENSE for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGACTION (0x1UL << 4) /**< Scan Trigger Action */ -#define _IADC_TRIGGER_SCANTRIGACTION_SHIFT 4 /**< Shift value for IADC_SCANTRIGACTION */ -#define _IADC_TRIGGER_SCANTRIGACTION_MASK 0x10UL /**< Bit mask for IADC_SCANTRIGACTION */ -#define _IADC_TRIGGER_SCANTRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGACTION_DEFAULT (_IADC_TRIGGER_SCANTRIGACTION_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGACTION_ONCE (_IADC_TRIGGER_SCANTRIGACTION_ONCE << 4) /**< Shifted mode ONCE for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS (_IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS << 4) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_SHIFT 8 /**< Shift value for IADC_SINGLETRIGSEL */ -#define _IADC_TRIGGER_SINGLETRIGSEL_MASK 0x700UL /**< Bit mask for IADC_SINGLETRIGSEL */ -#define _IADC_TRIGGER_SINGLETRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_DEFAULT (_IADC_TRIGGER_SINGLETRIGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE (_IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE << 8) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_TIMER (_IADC_TRIGGER_SINGLETRIGSEL_TIMER << 8) /**< Shifted mode TIMER for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP << 8) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_PRSPOS (_IADC_TRIGGER_SINGLETRIGSEL_PRSPOS << 8) /**< Shifted mode PRSPOS for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_PRSNEG (_IADC_TRIGGER_SINGLETRIGSEL_PRSNEG << 8) /**< Shifted mode PRSNEG for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGACTION (0x1UL << 12) /**< Single Trigger Action */ -#define _IADC_TRIGGER_SINGLETRIGACTION_SHIFT 12 /**< Shift value for IADC_SINGLETRIGACTION */ -#define _IADC_TRIGGER_SINGLETRIGACTION_MASK 0x1000UL /**< Bit mask for IADC_SINGLETRIGACTION */ -#define _IADC_TRIGGER_SINGLETRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGACTION_DEFAULT (_IADC_TRIGGER_SINGLETRIGACTION_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGACTION_ONCE (_IADC_TRIGGER_SINGLETRIGACTION_ONCE << 12) /**< Shifted mode ONCE for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS (_IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS << 12) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETAILGATE (0x1UL << 16) /**< Single Tailgate Enable */ -#define _IADC_TRIGGER_SINGLETAILGATE_SHIFT 16 /**< Shift value for IADC_SINGLETAILGATE */ -#define _IADC_TRIGGER_SINGLETAILGATE_MASK 0x10000UL /**< Bit mask for IADC_SINGLETAILGATE */ -#define _IADC_TRIGGER_SINGLETAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF 0x00000000UL /**< Mode TAILGATEOFF for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEON 0x00000001UL /**< Mode TAILGATEON for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETAILGATE_DEFAULT (_IADC_TRIGGER_SINGLETAILGATE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF << 16) /**< Shifted mode TAILGATEOFF for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEON (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEON << 16) /**< Shifted mode TAILGATEON for IADC_TRIGGER */ +#define _IADC_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for IADC_TRIGGER */ +#define _IADC_TRIGGER_MASK 0x00011717UL /**< Mask for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_SHIFT 0 /**< Shift value for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_MASK 0x7UL /**< Bit mask for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_LESENSE 0x00000005UL /**< Mode LESENSE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_DEFAULT (_IADC_TRIGGER_SCANTRIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE (_IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE << 0) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_TIMER (_IADC_TRIGGER_SCANTRIGSEL_TIMER << 0) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP << 0) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSPOS (_IADC_TRIGGER_SCANTRIGSEL_PRSPOS << 0) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSNEG (_IADC_TRIGGER_SCANTRIGSEL_PRSNEG << 0) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_LESENSE (_IADC_TRIGGER_SCANTRIGSEL_LESENSE << 0) /**< Shifted mode LESENSE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION (0x1UL << 4) /**< Scan Trigger Action */ +#define _IADC_TRIGGER_SCANTRIGACTION_SHIFT 4 /**< Shift value for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_MASK 0x10UL /**< Bit mask for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_DEFAULT (_IADC_TRIGGER_SCANTRIGACTION_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_ONCE (_IADC_TRIGGER_SCANTRIGACTION_ONCE << 4) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS (_IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS << 4) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_SHIFT 8 /**< Shift value for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_MASK 0x700UL /**< Bit mask for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_DEFAULT (_IADC_TRIGGER_SINGLETRIGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE (_IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE << 8) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_TIMER (_IADC_TRIGGER_SINGLETRIGSEL_TIMER << 8) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP << 8) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSPOS (_IADC_TRIGGER_SINGLETRIGSEL_PRSPOS << 8) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSNEG (_IADC_TRIGGER_SINGLETRIGSEL_PRSNEG << 8) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION (0x1UL << 12) /**< Single Trigger Action */ +#define _IADC_TRIGGER_SINGLETRIGACTION_SHIFT 12 /**< Shift value for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_MASK 0x1000UL /**< Bit mask for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_DEFAULT (_IADC_TRIGGER_SINGLETRIGACTION_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_ONCE (_IADC_TRIGGER_SINGLETRIGACTION_ONCE << 12) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS (_IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS << 12) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE (0x1UL << 16) /**< Single Tailgate Enable */ +#define _IADC_TRIGGER_SINGLETAILGATE_SHIFT 16 /**< Shift value for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_MASK 0x10000UL /**< Bit mask for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF 0x00000000UL /**< Mode TAILGATEOFF for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEON 0x00000001UL /**< Mode TAILGATEON for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_DEFAULT (_IADC_TRIGGER_SINGLETAILGATE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF << 16) /**< Shifted mode TAILGATEOFF for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEON (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEON << 16) /**< Shifted mode TAILGATEON for IADC_TRIGGER */ /* Bit fields for IADC CFG */ -#define _IADC_CFG_RESETVALUE 0x00002060UL /**< Default value for IADC_CFG */ -#define _IADC_CFG_MASK 0x30E770FFUL /**< Mask for IADC_CFG */ -#define _IADC_CFG_ADCMODE_SHIFT 0 /**< Shift value for IADC_ADCMODE */ -#define _IADC_CFG_ADCMODE_MASK 0x3UL /**< Bit mask for IADC_ADCMODE */ -#define _IADC_CFG_ADCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_ADCMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CFG */ -#define IADC_CFG_ADCMODE_DEFAULT (_IADC_CFG_ADCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_ADCMODE_NORMAL (_IADC_CFG_ADCMODE_NORMAL << 0) /**< Shifted mode NORMAL for IADC_CFG */ -#define _IADC_CFG_OSRHS_SHIFT 2 /**< Shift value for IADC_OSRHS */ -#define _IADC_CFG_OSRHS_MASK 0x1CUL /**< Bit mask for IADC_OSRHS */ -#define _IADC_CFG_OSRHS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD2 0x00000000UL /**< Mode HISPD2 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD4 0x00000001UL /**< Mode HISPD4 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD8 0x00000002UL /**< Mode HISPD8 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD16 0x00000003UL /**< Mode HISPD16 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD32 0x00000004UL /**< Mode HISPD32 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD64 0x00000005UL /**< Mode HISPD64 for IADC_CFG */ -#define IADC_CFG_OSRHS_DEFAULT (_IADC_CFG_OSRHS_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD2 (_IADC_CFG_OSRHS_HISPD2 << 2) /**< Shifted mode HISPD2 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD4 (_IADC_CFG_OSRHS_HISPD4 << 2) /**< Shifted mode HISPD4 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD8 (_IADC_CFG_OSRHS_HISPD8 << 2) /**< Shifted mode HISPD8 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD16 (_IADC_CFG_OSRHS_HISPD16 << 2) /**< Shifted mode HISPD16 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD32 (_IADC_CFG_OSRHS_HISPD32 << 2) /**< Shifted mode HISPD32 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD64 (_IADC_CFG_OSRHS_HISPD64 << 2) /**< Shifted mode HISPD64 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_SHIFT 12 /**< Shift value for IADC_ANALOGGAIN */ -#define _IADC_CFG_ANALOGGAIN_MASK 0x7000UL /**< Bit mask for IADC_ANALOGGAIN */ -#define _IADC_CFG_ANALOGGAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN0P5 0x00000001UL /**< Mode ANAGAIN0P5 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN1 0x00000002UL /**< Mode ANAGAIN1 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN2 0x00000003UL /**< Mode ANAGAIN2 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN3 0x00000004UL /**< Mode ANAGAIN3 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN4 0x00000005UL /**< Mode ANAGAIN4 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_DEFAULT (_IADC_CFG_ANALOGGAIN_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN0P5 (_IADC_CFG_ANALOGGAIN_ANAGAIN0P5 << 12) /**< Shifted mode ANAGAIN0P5 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN1 (_IADC_CFG_ANALOGGAIN_ANAGAIN1 << 12) /**< Shifted mode ANAGAIN1 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN2 (_IADC_CFG_ANALOGGAIN_ANAGAIN2 << 12) /**< Shifted mode ANAGAIN2 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN3 (_IADC_CFG_ANALOGGAIN_ANAGAIN3 << 12) /**< Shifted mode ANAGAIN3 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN4 (_IADC_CFG_ANALOGGAIN_ANAGAIN4 << 12) /**< Shifted mode ANAGAIN4 for IADC_CFG */ -#define _IADC_CFG_REFSEL_SHIFT 16 /**< Shift value for IADC_REFSEL */ -#define _IADC_CFG_REFSEL_MASK 0x70000UL /**< Bit mask for IADC_REFSEL */ -#define _IADC_CFG_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_REFSEL_VBGR 0x00000000UL /**< Mode VBGR for IADC_CFG */ -#define _IADC_CFG_REFSEL_VREF 0x00000001UL /**< Mode VREF for IADC_CFG */ -#define _IADC_CFG_REFSEL_VDDX 0x00000003UL /**< Mode VDDX for IADC_CFG */ -#define _IADC_CFG_REFSEL_VDDX0P8BUF 0x00000004UL /**< Mode VDDX0P8BUF for IADC_CFG */ -#define IADC_CFG_REFSEL_DEFAULT (_IADC_CFG_REFSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_REFSEL_VBGR (_IADC_CFG_REFSEL_VBGR << 16) /**< Shifted mode VBGR for IADC_CFG */ -#define IADC_CFG_REFSEL_VREF (_IADC_CFG_REFSEL_VREF << 16) /**< Shifted mode VREF for IADC_CFG */ -#define IADC_CFG_REFSEL_VDDX (_IADC_CFG_REFSEL_VDDX << 16) /**< Shifted mode VDDX for IADC_CFG */ -#define IADC_CFG_REFSEL_VDDX0P8BUF (_IADC_CFG_REFSEL_VDDX0P8BUF << 16) /**< Shifted mode VDDX0P8BUF for IADC_CFG */ -#define _IADC_CFG_DIGAVG_SHIFT 21 /**< Shift value for IADC_DIGAVG */ -#define _IADC_CFG_DIGAVG_MASK 0xE00000UL /**< Bit mask for IADC_DIGAVG */ -#define _IADC_CFG_DIGAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG1 0x00000000UL /**< Mode AVG1 for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG2 0x00000001UL /**< Mode AVG2 for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG4 0x00000002UL /**< Mode AVG4 for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG8 0x00000003UL /**< Mode AVG8 for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG16 0x00000004UL /**< Mode AVG16 for IADC_CFG */ -#define IADC_CFG_DIGAVG_DEFAULT (_IADC_CFG_DIGAVG_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG1 (_IADC_CFG_DIGAVG_AVG1 << 21) /**< Shifted mode AVG1 for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG2 (_IADC_CFG_DIGAVG_AVG2 << 21) /**< Shifted mode AVG2 for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG4 (_IADC_CFG_DIGAVG_AVG4 << 21) /**< Shifted mode AVG4 for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG8 (_IADC_CFG_DIGAVG_AVG8 << 21) /**< Shifted mode AVG8 for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG16 (_IADC_CFG_DIGAVG_AVG16 << 21) /**< Shifted mode AVG16 for IADC_CFG */ -#define _IADC_CFG_TWOSCOMPL_SHIFT 28 /**< Shift value for IADC_TWOSCOMPL */ -#define _IADC_CFG_TWOSCOMPL_MASK 0x30000000UL /**< Bit mask for IADC_TWOSCOMPL */ -#define _IADC_CFG_TWOSCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_TWOSCOMPL_AUTO 0x00000000UL /**< Mode AUTO for IADC_CFG */ -#define _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR 0x00000001UL /**< Mode FORCEUNIPOLAR for IADC_CFG */ -#define _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR 0x00000002UL /**< Mode FORCEBIPOLAR for IADC_CFG */ -#define IADC_CFG_TWOSCOMPL_DEFAULT (_IADC_CFG_TWOSCOMPL_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_TWOSCOMPL_AUTO (_IADC_CFG_TWOSCOMPL_AUTO << 28) /**< Shifted mode AUTO for IADC_CFG */ -#define IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR << 28) /**< Shifted mode FORCEUNIPOLAR for IADC_CFG */ -#define IADC_CFG_TWOSCOMPL_FORCEBIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEBIPOLAR << 28) /**< Shifted mode FORCEBIPOLAR for IADC_CFG */ +#define _IADC_CFG_RESETVALUE 0x00002060UL /**< Default value for IADC_CFG */ +#define _IADC_CFG_MASK 0x30E770FFUL /**< Mask for IADC_CFG */ +#define _IADC_CFG_ADCMODE_SHIFT 0 /**< Shift value for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_MASK 0x3UL /**< Bit mask for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ADCMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CFG */ +#define IADC_CFG_ADCMODE_DEFAULT (_IADC_CFG_ADCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ADCMODE_NORMAL (_IADC_CFG_ADCMODE_NORMAL << 0) /**< Shifted mode NORMAL for IADC_CFG */ +#define _IADC_CFG_OSRHS_SHIFT 2 /**< Shift value for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_MASK 0x1CUL /**< Bit mask for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD2 0x00000000UL /**< Mode HISPD2 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD4 0x00000001UL /**< Mode HISPD4 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD8 0x00000002UL /**< Mode HISPD8 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD16 0x00000003UL /**< Mode HISPD16 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD32 0x00000004UL /**< Mode HISPD32 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD64 0x00000005UL /**< Mode HISPD64 for IADC_CFG */ +#define IADC_CFG_OSRHS_DEFAULT (_IADC_CFG_OSRHS_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD2 (_IADC_CFG_OSRHS_HISPD2 << 2) /**< Shifted mode HISPD2 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD4 (_IADC_CFG_OSRHS_HISPD4 << 2) /**< Shifted mode HISPD4 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD8 (_IADC_CFG_OSRHS_HISPD8 << 2) /**< Shifted mode HISPD8 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD16 (_IADC_CFG_OSRHS_HISPD16 << 2) /**< Shifted mode HISPD16 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD32 (_IADC_CFG_OSRHS_HISPD32 << 2) /**< Shifted mode HISPD32 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD64 (_IADC_CFG_OSRHS_HISPD64 << 2) /**< Shifted mode HISPD64 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_SHIFT 12 /**< Shift value for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_MASK 0x7000UL /**< Bit mask for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN0P5 0x00000001UL /**< Mode ANAGAIN0P5 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN1 0x00000002UL /**< Mode ANAGAIN1 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN2 0x00000003UL /**< Mode ANAGAIN2 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN3 0x00000004UL /**< Mode ANAGAIN3 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN4 0x00000005UL /**< Mode ANAGAIN4 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_DEFAULT (_IADC_CFG_ANALOGGAIN_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN0P5 (_IADC_CFG_ANALOGGAIN_ANAGAIN0P5 << 12) /**< Shifted mode ANAGAIN0P5 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN1 (_IADC_CFG_ANALOGGAIN_ANAGAIN1 << 12) /**< Shifted mode ANAGAIN1 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN2 (_IADC_CFG_ANALOGGAIN_ANAGAIN2 << 12) /**< Shifted mode ANAGAIN2 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN3 (_IADC_CFG_ANALOGGAIN_ANAGAIN3 << 12) /**< Shifted mode ANAGAIN3 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN4 (_IADC_CFG_ANALOGGAIN_ANAGAIN4 << 12) /**< Shifted mode ANAGAIN4 for IADC_CFG */ +#define _IADC_CFG_REFSEL_SHIFT 16 /**< Shift value for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_MASK 0x70000UL /**< Bit mask for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_REFSEL_VBGR 0x00000000UL /**< Mode VBGR for IADC_CFG */ +#define _IADC_CFG_REFSEL_VREF 0x00000001UL /**< Mode VREF for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX 0x00000003UL /**< Mode VDDX for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX0P8BUF 0x00000004UL /**< Mode VDDX0P8BUF for IADC_CFG */ +#define IADC_CFG_REFSEL_DEFAULT (_IADC_CFG_REFSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_REFSEL_VBGR (_IADC_CFG_REFSEL_VBGR << 16) /**< Shifted mode VBGR for IADC_CFG */ +#define IADC_CFG_REFSEL_VREF (_IADC_CFG_REFSEL_VREF << 16) /**< Shifted mode VREF for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX (_IADC_CFG_REFSEL_VDDX << 16) /**< Shifted mode VDDX for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX0P8BUF (_IADC_CFG_REFSEL_VDDX0P8BUF << 16) /**< Shifted mode VDDX0P8BUF for IADC_CFG */ +#define _IADC_CFG_DIGAVG_SHIFT 21 /**< Shift value for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_MASK 0xE00000UL /**< Bit mask for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG1 0x00000000UL /**< Mode AVG1 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG2 0x00000001UL /**< Mode AVG2 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG4 0x00000002UL /**< Mode AVG4 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG8 0x00000003UL /**< Mode AVG8 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG16 0x00000004UL /**< Mode AVG16 for IADC_CFG */ +#define IADC_CFG_DIGAVG_DEFAULT (_IADC_CFG_DIGAVG_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG1 (_IADC_CFG_DIGAVG_AVG1 << 21) /**< Shifted mode AVG1 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG2 (_IADC_CFG_DIGAVG_AVG2 << 21) /**< Shifted mode AVG2 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG4 (_IADC_CFG_DIGAVG_AVG4 << 21) /**< Shifted mode AVG4 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG8 (_IADC_CFG_DIGAVG_AVG8 << 21) /**< Shifted mode AVG8 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG16 (_IADC_CFG_DIGAVG_AVG16 << 21) /**< Shifted mode AVG16 for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_SHIFT 28 /**< Shift value for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_MASK 0x30000000UL /**< Bit mask for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_AUTO 0x00000000UL /**< Mode AUTO for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR 0x00000001UL /**< Mode FORCEUNIPOLAR for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR 0x00000002UL /**< Mode FORCEBIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_DEFAULT (_IADC_CFG_TWOSCOMPL_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_AUTO (_IADC_CFG_TWOSCOMPL_AUTO << 28) /**< Shifted mode AUTO for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR << 28) /**< Shifted mode FORCEUNIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEBIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEBIPOLAR << 28) /**< Shifted mode FORCEBIPOLAR for IADC_CFG */ /* Bit fields for IADC SCALE */ -#define _IADC_SCALE_RESETVALUE 0x8002C000UL /**< Default value for IADC_SCALE */ -#define _IADC_SCALE_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCALE */ -#define _IADC_SCALE_OFFSET_SHIFT 0 /**< Shift value for IADC_OFFSET */ -#define _IADC_SCALE_OFFSET_MASK 0x3FFFFUL /**< Bit mask for IADC_OFFSET */ -#define _IADC_SCALE_OFFSET_DEFAULT 0x0002C000UL /**< Mode DEFAULT for IADC_SCALE */ -#define IADC_SCALE_OFFSET_DEFAULT (_IADC_SCALE_OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCALE */ -#define _IADC_SCALE_GAIN13LSB_SHIFT 18 /**< Shift value for IADC_GAIN13LSB */ -#define _IADC_SCALE_GAIN13LSB_MASK 0x7FFC0000UL /**< Bit mask for IADC_GAIN13LSB */ -#define _IADC_SCALE_GAIN13LSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCALE */ -#define IADC_SCALE_GAIN13LSB_DEFAULT (_IADC_SCALE_GAIN13LSB_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_SCALE */ -#define IADC_SCALE_GAIN3MSB (0x1UL << 31) /**< Gain 3 MSBs */ -#define _IADC_SCALE_GAIN3MSB_SHIFT 31 /**< Shift value for IADC_GAIN3MSB */ -#define _IADC_SCALE_GAIN3MSB_MASK 0x80000000UL /**< Bit mask for IADC_GAIN3MSB */ -#define _IADC_SCALE_GAIN3MSB_DEFAULT 0x00000001UL /**< Mode DEFAULT for IADC_SCALE */ -#define _IADC_SCALE_GAIN3MSB_GAIN011 0x00000000UL /**< Mode GAIN011 for IADC_SCALE */ -#define _IADC_SCALE_GAIN3MSB_GAIN100 0x00000001UL /**< Mode GAIN100 for IADC_SCALE */ -#define IADC_SCALE_GAIN3MSB_DEFAULT (_IADC_SCALE_GAIN3MSB_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_SCALE */ -#define IADC_SCALE_GAIN3MSB_GAIN011 (_IADC_SCALE_GAIN3MSB_GAIN011 << 31) /**< Shifted mode GAIN011 for IADC_SCALE */ -#define IADC_SCALE_GAIN3MSB_GAIN100 (_IADC_SCALE_GAIN3MSB_GAIN100 << 31) /**< Shifted mode GAIN100 for IADC_SCALE */ +#define _IADC_SCALE_RESETVALUE 0x8002C000UL /**< Default value for IADC_SCALE */ +#define _IADC_SCALE_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCALE */ +#define _IADC_SCALE_OFFSET_SHIFT 0 /**< Shift value for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_MASK 0x3FFFFUL /**< Bit mask for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_DEFAULT 0x0002C000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_OFFSET_DEFAULT (_IADC_SCALE_OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN13LSB_SHIFT 18 /**< Shift value for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_MASK 0x7FFC0000UL /**< Bit mask for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN13LSB_DEFAULT (_IADC_SCALE_GAIN13LSB_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB (0x1UL << 31) /**< Gain 3 MSBs */ +#define _IADC_SCALE_GAIN3MSB_SHIFT 31 /**< Shift value for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_MASK 0x80000000UL /**< Bit mask for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_DEFAULT 0x00000001UL /**< Mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN011 0x00000000UL /**< Mode GAIN011 for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN100 0x00000001UL /**< Mode GAIN100 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_DEFAULT (_IADC_SCALE_GAIN3MSB_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN011 (_IADC_SCALE_GAIN3MSB_GAIN011 << 31) /**< Shifted mode GAIN011 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN100 (_IADC_SCALE_GAIN3MSB_GAIN100 << 31) /**< Shifted mode GAIN100 for IADC_SCALE */ /* Bit fields for IADC SCHED */ -#define _IADC_SCHED_RESETVALUE 0x00000000UL /**< Default value for IADC_SCHED */ -#define _IADC_SCHED_MASK 0x000003FFUL /**< Mask for IADC_SCHED */ -#define _IADC_SCHED_PRESCALE_SHIFT 0 /**< Shift value for IADC_PRESCALE */ -#define _IADC_SCHED_PRESCALE_MASK 0x3FFUL /**< Bit mask for IADC_PRESCALE */ -#define _IADC_SCHED_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCHED */ -#define IADC_SCHED_PRESCALE_DEFAULT (_IADC_SCHED_PRESCALE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCHED */ +#define _IADC_SCHED_RESETVALUE 0x00000000UL /**< Default value for IADC_SCHED */ +#define _IADC_SCHED_MASK 0x000003FFUL /**< Mask for IADC_SCHED */ +#define _IADC_SCHED_PRESCALE_SHIFT 0 /**< Shift value for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_MASK 0x3FFUL /**< Bit mask for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCHED */ +#define IADC_SCHED_PRESCALE_DEFAULT (_IADC_SCHED_PRESCALE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCHED */ /* Bit fields for IADC SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ -#define _IADC_SINGLEFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ -#define _IADC_SINGLEFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ -#define _IADC_SINGLEFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_SHOWID_DEFAULT (_IADC_SINGLEFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ -#define _IADC_SINGLEFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ -#define _IADC_SINGLEFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_DEFAULT (_IADC_SINGLEFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID1 (_IADC_SINGLEFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID2 (_IADC_SINGLEFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID3 (_IADC_SINGLEFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID4 (_IADC_SINGLEFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID5 (_IADC_SINGLEFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID6 (_IADC_SINGLEFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID7 (_IADC_SINGLEFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID8 (_IADC_SINGLEFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE (0x1UL << 8) /**< Single FIFO DMA wakeup. */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSINGLE */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSINGLE */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SINGLEFIFOCFG*/ -#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID_DEFAULT (_IADC_SINGLEFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_DEFAULT (_IADC_SINGLEFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID1 (_IADC_SINGLEFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID2 (_IADC_SINGLEFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID3 (_IADC_SINGLEFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID4 (_IADC_SINGLEFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID5 (_IADC_SINGLEFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID6 (_IADC_SINGLEFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID7 (_IADC_SINGLEFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID8 (_IADC_SINGLEFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE (0x1UL << 8) /**< Single FIFO DMA wakeup. */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SINGLEFIFOCFG*/ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SINGLEFIFOCFG */ /* Bit fields for IADC SINGLEFIFODATA */ -#define _IADC_SINGLEFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFODATA */ -#define _IADC_SINGLEFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEFIFODATA */ -#define _IADC_SINGLEFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ -#define _IADC_SINGLEFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ -#define _IADC_SINGLEFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFODATA */ -#define IADC_SINGLEFIFODATA_DATA_DEFAULT (_IADC_SINGLEFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFODATA*/ +#define _IADC_SINGLEFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFODATA */ +#define IADC_SINGLEFIFODATA_DATA_DEFAULT (_IADC_SINGLEFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFODATA*/ /* Bit fields for IADC SINGLEFIFOSTAT */ -#define _IADC_SINGLEFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFOSTAT */ -#define _IADC_SINGLEFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SINGLEFIFOSTAT */ -#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ -#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ -#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOSTAT */ -#define IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOSTAT*/ +#define _IADC_SINGLEFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOSTAT */ +#define IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOSTAT*/ /* Bit fields for IADC SINGLEDATA */ -#define _IADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEDATA */ -#define _IADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEDATA */ -#define _IADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ -#define _IADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ -#define _IADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEDATA */ -#define IADC_SINGLEDATA_DATA_DEFAULT (_IADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEDATA */ +#define IADC_SINGLEDATA_DATA_DEFAULT (_IADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEDATA */ /* Bit fields for IADC SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ -#define _IADC_SCANFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ -#define _IADC_SCANFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ -#define _IADC_SCANFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_SHOWID_DEFAULT (_IADC_SCANFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ -#define _IADC_SCANFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ -#define _IADC_SCANFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_DEFAULT (_IADC_SCANFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID1 (_IADC_SCANFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID2 (_IADC_SCANFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID3 (_IADC_SCANFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID4 (_IADC_SCANFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID5 (_IADC_SCANFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID6 (_IADC_SCANFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID7 (_IADC_SCANFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID8 (_IADC_SCANFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN (0x1UL << 8) /**< Scan FIFO DMA Wakeup */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSCAN */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSCAN */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SCANFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID_DEFAULT (_IADC_SCANFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_DEFAULT (_IADC_SCANFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID1 (_IADC_SCANFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID2 (_IADC_SCANFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID3 (_IADC_SCANFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID4 (_IADC_SCANFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID5 (_IADC_SCANFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID6 (_IADC_SCANFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID7 (_IADC_SCANFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID8 (_IADC_SCANFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN (0x1UL << 8) /**< Scan FIFO DMA Wakeup */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SCANFIFOCFG */ /* Bit fields for IADC SCANFIFODATA */ -#define _IADC_SCANFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFODATA */ -#define _IADC_SCANFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANFIFODATA */ -#define _IADC_SCANFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ -#define _IADC_SCANFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ -#define _IADC_SCANFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFODATA */ -#define IADC_SCANFIFODATA_DATA_DEFAULT (_IADC_SCANFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFODATA */ +#define IADC_SCANFIFODATA_DATA_DEFAULT (_IADC_SCANFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFODATA */ /* Bit fields for IADC SCANFIFOSTAT */ -#define _IADC_SCANFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFOSTAT */ -#define _IADC_SCANFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SCANFIFOSTAT */ -#define _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ -#define _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ -#define _IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOSTAT */ -#define IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOSTAT */ +#define IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOSTAT */ /* Bit fields for IADC SCANDATA */ -#define _IADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANDATA */ -#define _IADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANDATA */ -#define _IADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ -#define _IADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ -#define _IADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANDATA */ -#define IADC_SCANDATA_DATA_DEFAULT (_IADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANDATA */ +#define _IADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANDATA */ +#define _IADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANDATA */ +#define _IADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANDATA */ +#define IADC_SCANDATA_DATA_DEFAULT (_IADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANDATA */ /* Bit fields for IADC SINGLE */ -#define _IADC_SINGLE_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLE */ -#define _IADC_SINGLE_MASK 0x0003FFFFUL /**< Mask for IADC_SINGLE */ -#define _IADC_SINGLE_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ -#define _IADC_SINGLE_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ -#define _IADC_SINGLE_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_PINNEG_DEFAULT (_IADC_SINGLE_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ -#define _IADC_SINGLE_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ -#define _IADC_SINGLE_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PADANA1 0x00000004UL /**< Mode PADANA1 for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PADANA3 0x00000005UL /**< Mode PADANA3 for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_DEFAULT (_IADC_SINGLE_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_GND (_IADC_SINGLE_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_DAC1 (_IADC_SINGLE_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PADANA1 (_IADC_SINGLE_PORTNEG_PADANA1 << 4) /**< Shifted mode PADANA1 for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PADANA3 (_IADC_SINGLE_PORTNEG_PADANA3 << 4) /**< Shifted mode PADANA3 for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PORTA (_IADC_SINGLE_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PORTB (_IADC_SINGLE_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PORTC (_IADC_SINGLE_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PORTD (_IADC_SINGLE_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SINGLE */ -#define _IADC_SINGLE_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ -#define _IADC_SINGLE_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ -#define _IADC_SINGLE_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_PINPOS_DEFAULT (_IADC_SINGLE_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ -#define _IADC_SINGLE_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ -#define _IADC_SINGLE_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PADANA0 0x00000004UL /**< Mode PADANA0 for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PADANA2 0x00000005UL /**< Mode PADANA2 for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_DEFAULT (_IADC_SINGLE_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_GND (_IADC_SINGLE_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_SUPPLY (_IADC_SINGLE_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_DAC0 (_IADC_SINGLE_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PADANA0 (_IADC_SINGLE_PORTPOS_PADANA0 << 12) /**< Shifted mode PADANA0 for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PADANA2 (_IADC_SINGLE_PORTPOS_PADANA2 << 12) /**< Shifted mode PADANA2 for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PORTA (_IADC_SINGLE_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PORTB (_IADC_SINGLE_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PORTC (_IADC_SINGLE_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PORTD (_IADC_SINGLE_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SINGLE */ -#define IADC_SINGLE_CFG (0x1UL << 16) /**< Configuration Group Select */ -#define _IADC_SINGLE_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ -#define _IADC_SINGLE_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ -#define _IADC_SINGLE_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SINGLE */ -#define _IADC_SINGLE_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SINGLE */ -#define IADC_SINGLE_CFG_DEFAULT (_IADC_SINGLE_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_CFG_CONFIG0 (_IADC_SINGLE_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SINGLE */ -#define IADC_SINGLE_CFG_CONFIG1 (_IADC_SINGLE_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SINGLE */ -#define IADC_SINGLE_CMP (0x1UL << 17) /**< Comparison Enable */ -#define _IADC_SINGLE_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ -#define _IADC_SINGLE_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ -#define _IADC_SINGLE_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_CMP_DEFAULT (_IADC_SINGLE_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLE */ +#define _IADC_SINGLE_MASK 0x0003FFFFUL /**< Mask for IADC_SINGLE */ +#define _IADC_SINGLE_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINNEG_DEFAULT (_IADC_SINGLE_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PADANA1 0x00000004UL /**< Mode PADANA1 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PADANA3 0x00000005UL /**< Mode PADANA3 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_DEFAULT (_IADC_SINGLE_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_GND (_IADC_SINGLE_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_DAC1 (_IADC_SINGLE_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PADANA1 (_IADC_SINGLE_PORTNEG_PADANA1 << 4) /**< Shifted mode PADANA1 for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PADANA3 (_IADC_SINGLE_PORTNEG_PADANA3 << 4) /**< Shifted mode PADANA3 for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTA (_IADC_SINGLE_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTB (_IADC_SINGLE_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTC (_IADC_SINGLE_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTD (_IADC_SINGLE_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SINGLE */ +#define _IADC_SINGLE_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINPOS_DEFAULT (_IADC_SINGLE_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PADANA0 0x00000004UL /**< Mode PADANA0 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PADANA2 0x00000005UL /**< Mode PADANA2 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_DEFAULT (_IADC_SINGLE_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_GND (_IADC_SINGLE_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_SUPPLY (_IADC_SINGLE_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_DAC0 (_IADC_SINGLE_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PADANA0 (_IADC_SINGLE_PORTPOS_PADANA0 << 12) /**< Shifted mode PADANA0 for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PADANA2 (_IADC_SINGLE_PORTPOS_PADANA2 << 12) /**< Shifted mode PADANA2 for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTA (_IADC_SINGLE_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTB (_IADC_SINGLE_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTC (_IADC_SINGLE_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTD (_IADC_SINGLE_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SINGLE_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SINGLE_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SINGLE_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_DEFAULT (_IADC_SINGLE_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG0 (_IADC_SINGLE_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG1 (_IADC_SINGLE_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SINGLE_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SINGLE_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SINGLE_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CMP_DEFAULT (_IADC_SINGLE_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SINGLE */ /* Bit fields for IADC SCAN */ -#define _IADC_SCAN_RESETVALUE 0x00000000UL /**< Default value for IADC_SCAN */ -#define _IADC_SCAN_MASK 0x0003FFFFUL /**< Mask for IADC_SCAN */ -#define _IADC_SCAN_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ -#define _IADC_SCAN_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ -#define _IADC_SCAN_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_PINNEG_DEFAULT (_IADC_SCAN_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ -#define _IADC_SCAN_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ -#define _IADC_SCAN_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PADANA1 0x00000004UL /**< Mode PADANA1 for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PADANA3 0x00000005UL /**< Mode PADANA3 for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_DEFAULT (_IADC_SCAN_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_GND (_IADC_SCAN_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_DAC1 (_IADC_SCAN_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PADANA1 (_IADC_SCAN_PORTNEG_PADANA1 << 4) /**< Shifted mode PADANA1 for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PADANA3 (_IADC_SCAN_PORTNEG_PADANA3 << 4) /**< Shifted mode PADANA3 for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PORTA (_IADC_SCAN_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PORTB (_IADC_SCAN_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PORTC (_IADC_SCAN_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PORTD (_IADC_SCAN_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SCAN */ -#define _IADC_SCAN_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ -#define _IADC_SCAN_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ -#define _IADC_SCAN_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_PINPOS_DEFAULT (_IADC_SCAN_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ -#define _IADC_SCAN_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ -#define _IADC_SCAN_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PADANA0 0x00000004UL /**< Mode PADANA0 for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PADANA2 0x00000005UL /**< Mode PADANA2 for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_DEFAULT (_IADC_SCAN_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_GND (_IADC_SCAN_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_SUPPLY (_IADC_SCAN_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_DAC0 (_IADC_SCAN_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PADANA0 (_IADC_SCAN_PORTPOS_PADANA0 << 12) /**< Shifted mode PADANA0 for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PADANA2 (_IADC_SCAN_PORTPOS_PADANA2 << 12) /**< Shifted mode PADANA2 for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PORTA (_IADC_SCAN_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PORTB (_IADC_SCAN_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PORTC (_IADC_SCAN_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PORTD (_IADC_SCAN_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SCAN */ -#define IADC_SCAN_CFG (0x1UL << 16) /**< Configuration Group Select */ -#define _IADC_SCAN_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ -#define _IADC_SCAN_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ -#define _IADC_SCAN_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SCAN */ -#define _IADC_SCAN_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SCAN */ -#define IADC_SCAN_CFG_DEFAULT (_IADC_SCAN_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_CFG_CONFIG0 (_IADC_SCAN_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SCAN */ -#define IADC_SCAN_CFG_CONFIG1 (_IADC_SCAN_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SCAN */ -#define IADC_SCAN_CMP (0x1UL << 17) /**< Comparison Enable */ -#define _IADC_SCAN_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ -#define _IADC_SCAN_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ -#define _IADC_SCAN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_CMP_DEFAULT (_IADC_SCAN_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_RESETVALUE 0x00000000UL /**< Default value for IADC_SCAN */ +#define _IADC_SCAN_MASK 0x0003FFFFUL /**< Mask for IADC_SCAN */ +#define _IADC_SCAN_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINNEG_DEFAULT (_IADC_SCAN_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PADANA1 0x00000004UL /**< Mode PADANA1 for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PADANA3 0x00000005UL /**< Mode PADANA3 for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_DEFAULT (_IADC_SCAN_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_GND (_IADC_SCAN_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_DAC1 (_IADC_SCAN_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PADANA1 (_IADC_SCAN_PORTNEG_PADANA1 << 4) /**< Shifted mode PADANA1 for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PADANA3 (_IADC_SCAN_PORTNEG_PADANA3 << 4) /**< Shifted mode PADANA3 for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTA (_IADC_SCAN_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTB (_IADC_SCAN_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTC (_IADC_SCAN_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTD (_IADC_SCAN_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SCAN */ +#define _IADC_SCAN_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINPOS_DEFAULT (_IADC_SCAN_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PADANA0 0x00000004UL /**< Mode PADANA0 for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PADANA2 0x00000005UL /**< Mode PADANA2 for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_DEFAULT (_IADC_SCAN_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_GND (_IADC_SCAN_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_SUPPLY (_IADC_SCAN_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_DAC0 (_IADC_SCAN_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PADANA0 (_IADC_SCAN_PORTPOS_PADANA0 << 12) /**< Shifted mode PADANA0 for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PADANA2 (_IADC_SCAN_PORTPOS_PADANA2 << 12) /**< Shifted mode PADANA2 for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTA (_IADC_SCAN_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTB (_IADC_SCAN_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTC (_IADC_SCAN_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTD (_IADC_SCAN_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SCAN */ +#define IADC_SCAN_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SCAN_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SCAN_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SCAN_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CFG_DEFAULT (_IADC_SCAN_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG0 (_IADC_SCAN_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG1 (_IADC_SCAN_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SCAN_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SCAN_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SCAN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CMP_DEFAULT (_IADC_SCAN_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SCAN */ /** @} End of group EFR32SG28_IADC_BitFields */ /** @} End of group EFR32SG28_IADC */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_icache.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_icache.h index db219e202c..cc9063c46d 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_icache.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_icache.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_ICACHE_H #define EFR32SG28_ICACHE_H - #define ICACHE_HAS_SET_CLEAR /**************************************************************************//** @@ -43,51 +42,50 @@ *****************************************************************************/ /** ICACHE Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP Version */ - __IOM uint32_t CTRL; /**< Control Register */ - __IM uint32_t PCHITS; /**< Performance Counter Hits */ - __IM uint32_t PCMISSES; /**< Performance Counter Misses */ - __IM uint32_t PCAHITS; /**< Performance Counter Advanced Hits */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IOM uint32_t LPMODE; /**< Low Power Mode */ - __IOM uint32_t IF; /**< Interrupt Flag */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED0[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IM uint32_t PCHITS_SET; /**< Performance Counter Hits */ - __IM uint32_t PCMISSES_SET; /**< Performance Counter Misses */ - __IM uint32_t PCAHITS_SET; /**< Performance Counter Advanced Hits */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IOM uint32_t LPMODE_SET; /**< Low Power Mode */ - __IOM uint32_t IF_SET; /**< Interrupt Flag */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IM uint32_t PCHITS_CLR; /**< Performance Counter Hits */ - __IM uint32_t PCMISSES_CLR; /**< Performance Counter Misses */ - __IM uint32_t PCAHITS_CLR; /**< Performance Counter Advanced Hits */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IOM uint32_t LPMODE_CLR; /**< Low Power Mode */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - uint32_t RESERVED2[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IM uint32_t PCHITS_TGL; /**< Performance Counter Hits */ - __IM uint32_t PCMISSES_TGL; /**< Performance Counter Misses */ - __IM uint32_t PCAHITS_TGL; /**< Performance Counter Advanced Hits */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IOM uint32_t LPMODE_TGL; /**< Low Power Mode */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t PCHITS; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t LPMODE; /**< Low Power Mode */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED0[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IM uint32_t PCHITS_SET; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_SET; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_SET; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t LPMODE_SET; /**< Low Power Mode */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IM uint32_t PCHITS_CLR; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_CLR; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_CLR; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t LPMODE_CLR; /**< Low Power Mode */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED2[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IM uint32_t PCHITS_TGL; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_TGL; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_TGL; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t LPMODE_TGL; /**< Low Power Mode */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ } ICACHE_TypeDef; /** @} End of group EFR32SG28_ICACHE */ @@ -99,149 +97,149 @@ typedef struct *****************************************************************************/ /* Bit fields for ICACHE IPVERSION */ -#define _ICACHE_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IPVERSION */ -#define _ICACHE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_IPVERSION */ -#define _ICACHE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ICACHE_IPVERSION */ -#define _ICACHE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_IPVERSION */ -#define _ICACHE_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IPVERSION */ -#define ICACHE_IPVERSION_IPVERSION_DEFAULT (_ICACHE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IPVERSION */ +#define ICACHE_IPVERSION_IPVERSION_DEFAULT (_ICACHE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IPVERSION */ /* Bit fields for ICACHE CTRL */ -#define _ICACHE_CTRL_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CTRL */ -#define _ICACHE_CTRL_MASK 0x00000007UL /**< Mask for ICACHE_CTRL */ -#define ICACHE_CTRL_CACHEDIS (0x1UL << 0) /**< Cache Disable */ -#define _ICACHE_CTRL_CACHEDIS_SHIFT 0 /**< Shift value for ICACHE_CACHEDIS */ -#define _ICACHE_CTRL_CACHEDIS_MASK 0x1UL /**< Bit mask for ICACHE_CACHEDIS */ -#define _ICACHE_CTRL_CACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_CACHEDIS_DEFAULT (_ICACHE_CTRL_CACHEDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_USEMPU (0x1UL << 1) /**< Use MPU */ -#define _ICACHE_CTRL_USEMPU_SHIFT 1 /**< Shift value for ICACHE_USEMPU */ -#define _ICACHE_CTRL_USEMPU_MASK 0x2UL /**< Bit mask for ICACHE_USEMPU */ -#define _ICACHE_CTRL_USEMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_USEMPU_DEFAULT (_ICACHE_CTRL_USEMPU_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_AUTOFLUSHDIS (0x1UL << 2) /**< Automatic Flushing Disable */ -#define _ICACHE_CTRL_AUTOFLUSHDIS_SHIFT 2 /**< Shift value for ICACHE_AUTOFLUSHDIS */ -#define _ICACHE_CTRL_AUTOFLUSHDIS_MASK 0x4UL /**< Bit mask for ICACHE_AUTOFLUSHDIS */ -#define _ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT (_ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define _ICACHE_CTRL_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CTRL */ +#define _ICACHE_CTRL_MASK 0x00000007UL /**< Mask for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS (0x1UL << 0) /**< Cache Disable */ +#define _ICACHE_CTRL_CACHEDIS_SHIFT 0 /**< Shift value for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_MASK 0x1UL /**< Bit mask for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS_DEFAULT (_ICACHE_CTRL_CACHEDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU (0x1UL << 1) /**< Use MPU */ +#define _ICACHE_CTRL_USEMPU_SHIFT 1 /**< Shift value for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_MASK 0x2UL /**< Bit mask for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU_DEFAULT (_ICACHE_CTRL_USEMPU_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS (0x1UL << 2) /**< Automatic Flushing Disable */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_SHIFT 2 /**< Shift value for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_MASK 0x4UL /**< Bit mask for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT (_ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CTRL */ /* Bit fields for ICACHE PCHITS */ -#define _ICACHE_PCHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCHITS */ -#define _ICACHE_PCHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCHITS */ -#define _ICACHE_PCHITS_PCHITS_SHIFT 0 /**< Shift value for ICACHE_PCHITS */ -#define _ICACHE_PCHITS_PCHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCHITS */ -#define _ICACHE_PCHITS_PCHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCHITS */ -#define ICACHE_PCHITS_PCHITS_DEFAULT (_ICACHE_PCHITS_PCHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_SHIFT 0 /**< Shift value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCHITS */ +#define ICACHE_PCHITS_PCHITS_DEFAULT (_ICACHE_PCHITS_PCHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCHITS */ /* Bit fields for ICACHE PCMISSES */ -#define _ICACHE_PCMISSES_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCMISSES */ -#define _ICACHE_PCMISSES_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCMISSES */ -#define _ICACHE_PCMISSES_PCMISSES_SHIFT 0 /**< Shift value for ICACHE_PCMISSES */ -#define _ICACHE_PCMISSES_PCMISSES_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCMISSES */ -#define _ICACHE_PCMISSES_PCMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCMISSES */ -#define ICACHE_PCMISSES_PCMISSES_DEFAULT (_ICACHE_PCMISSES_PCMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_SHIFT 0 /**< Shift value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCMISSES */ +#define ICACHE_PCMISSES_PCMISSES_DEFAULT (_ICACHE_PCMISSES_PCMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCMISSES */ /* Bit fields for ICACHE PCAHITS */ -#define _ICACHE_PCAHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCAHITS */ -#define _ICACHE_PCAHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCAHITS */ -#define _ICACHE_PCAHITS_PCAHITS_SHIFT 0 /**< Shift value for ICACHE_PCAHITS */ -#define _ICACHE_PCAHITS_PCAHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCAHITS */ -#define _ICACHE_PCAHITS_PCAHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCAHITS */ -#define ICACHE_PCAHITS_PCAHITS_DEFAULT (_ICACHE_PCAHITS_PCAHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_SHIFT 0 /**< Shift value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCAHITS */ +#define ICACHE_PCAHITS_PCAHITS_DEFAULT (_ICACHE_PCAHITS_PCAHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCAHITS */ /* Bit fields for ICACHE STATUS */ -#define _ICACHE_STATUS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_STATUS */ -#define _ICACHE_STATUS_MASK 0x00000001UL /**< Mask for ICACHE_STATUS */ -#define ICACHE_STATUS_PCRUNNING (0x1UL << 0) /**< PC Running */ -#define _ICACHE_STATUS_PCRUNNING_SHIFT 0 /**< Shift value for ICACHE_PCRUNNING */ -#define _ICACHE_STATUS_PCRUNNING_MASK 0x1UL /**< Bit mask for ICACHE_PCRUNNING */ -#define _ICACHE_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_STATUS */ -#define ICACHE_STATUS_PCRUNNING_DEFAULT (_ICACHE_STATUS_PCRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_STATUS */ +#define _ICACHE_STATUS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_STATUS */ +#define _ICACHE_STATUS_MASK 0x00000001UL /**< Mask for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING (0x1UL << 0) /**< PC Running */ +#define _ICACHE_STATUS_PCRUNNING_SHIFT 0 /**< Shift value for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_MASK 0x1UL /**< Bit mask for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING_DEFAULT (_ICACHE_STATUS_PCRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_STATUS */ /* Bit fields for ICACHE CMD */ -#define _ICACHE_CMD_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CMD */ -#define _ICACHE_CMD_MASK 0x00000007UL /**< Mask for ICACHE_CMD */ -#define ICACHE_CMD_FLUSH (0x1UL << 0) /**< Flush */ -#define _ICACHE_CMD_FLUSH_SHIFT 0 /**< Shift value for ICACHE_FLUSH */ -#define _ICACHE_CMD_FLUSH_MASK 0x1UL /**< Bit mask for ICACHE_FLUSH */ -#define _ICACHE_CMD_FLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_FLUSH_DEFAULT (_ICACHE_CMD_FLUSH_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ -#define _ICACHE_CMD_STARTPC_SHIFT 1 /**< Shift value for ICACHE_STARTPC */ -#define _ICACHE_CMD_STARTPC_MASK 0x2UL /**< Bit mask for ICACHE_STARTPC */ -#define _ICACHE_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_STARTPC_DEFAULT (_ICACHE_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ -#define _ICACHE_CMD_STOPPC_SHIFT 2 /**< Shift value for ICACHE_STOPPC */ -#define _ICACHE_CMD_STOPPC_MASK 0x4UL /**< Bit mask for ICACHE_STOPPC */ -#define _ICACHE_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_STOPPC_DEFAULT (_ICACHE_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define _ICACHE_CMD_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CMD */ +#define _ICACHE_CMD_MASK 0x00000007UL /**< Mask for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH (0x1UL << 0) /**< Flush */ +#define _ICACHE_CMD_FLUSH_SHIFT 0 /**< Shift value for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_MASK 0x1UL /**< Bit mask for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH_DEFAULT (_ICACHE_CMD_FLUSH_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _ICACHE_CMD_STARTPC_SHIFT 1 /**< Shift value for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_MASK 0x2UL /**< Bit mask for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC_DEFAULT (_ICACHE_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _ICACHE_CMD_STOPPC_SHIFT 2 /**< Shift value for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_MASK 0x4UL /**< Bit mask for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC_DEFAULT (_ICACHE_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CMD */ /* Bit fields for ICACHE LPMODE */ -#define _ICACHE_LPMODE_RESETVALUE 0x00000023UL /**< Default value for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_MASK 0x000000F3UL /**< Mask for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_LPLEVEL_SHIFT 0 /**< Shift value for ICACHE_LPLEVEL */ -#define _ICACHE_LPMODE_LPLEVEL_MASK 0x3UL /**< Bit mask for ICACHE_LPLEVEL */ -#define _ICACHE_LPMODE_LPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_LPLEVEL_BASIC 0x00000000UL /**< Mode BASIC for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_LPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_LPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for ICACHE_LPMODE */ -#define ICACHE_LPMODE_LPLEVEL_DEFAULT (_ICACHE_LPMODE_LPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ -#define ICACHE_LPMODE_LPLEVEL_BASIC (_ICACHE_LPMODE_LPLEVEL_BASIC << 0) /**< Shifted mode BASIC for ICACHE_LPMODE */ -#define ICACHE_LPMODE_LPLEVEL_ADVANCED (_ICACHE_LPMODE_LPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for ICACHE_LPMODE */ -#define ICACHE_LPMODE_LPLEVEL_MINACTIVITY (_ICACHE_LPMODE_LPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_NESTFACTOR_SHIFT 4 /**< Shift value for ICACHE_NESTFACTOR */ -#define _ICACHE_LPMODE_NESTFACTOR_MASK 0xF0UL /**< Bit mask for ICACHE_NESTFACTOR */ -#define _ICACHE_LPMODE_NESTFACTOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for ICACHE_LPMODE */ -#define ICACHE_LPMODE_NESTFACTOR_DEFAULT (_ICACHE_LPMODE_NESTFACTOR_DEFAULT << 4) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_RESETVALUE 0x00000023UL /**< Default value for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_MASK 0x000000F3UL /**< Mask for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_SHIFT 0 /**< Shift value for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_MASK 0x3UL /**< Bit mask for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_BASIC 0x00000000UL /**< Mode BASIC for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_DEFAULT (_ICACHE_LPMODE_LPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_BASIC (_ICACHE_LPMODE_LPLEVEL_BASIC << 0) /**< Shifted mode BASIC for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_ADVANCED (_ICACHE_LPMODE_LPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_MINACTIVITY (_ICACHE_LPMODE_LPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_NESTFACTOR_SHIFT 4 /**< Shift value for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_MASK 0xF0UL /**< Bit mask for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_NESTFACTOR_DEFAULT (_ICACHE_LPMODE_NESTFACTOR_DEFAULT << 4) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ /* Bit fields for ICACHE IF */ -#define _ICACHE_IF_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IF */ -#define _ICACHE_IF_MASK 0x00000107UL /**< Mask for ICACHE_IF */ -#define ICACHE_IF_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Flag */ -#define _ICACHE_IF_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ -#define _ICACHE_IF_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ -#define _ICACHE_IF_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_HITOF_DEFAULT (_ICACHE_IF_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Flag */ -#define _ICACHE_IF_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ -#define _ICACHE_IF_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ -#define _ICACHE_IF_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_MISSOF_DEFAULT (_ICACHE_IF_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Flag */ -#define _ICACHE_IF_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ -#define _ICACHE_IF_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ -#define _ICACHE_IF_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_AHITOF_DEFAULT (_ICACHE_IF_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Flag */ -#define _ICACHE_IF_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ -#define _ICACHE_IF_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ -#define _ICACHE_IF_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_RAMERROR_DEFAULT (_ICACHE_IF_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define _ICACHE_IF_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IF */ +#define _ICACHE_IF_MASK 0x00000107UL /**< Mask for ICACHE_IF */ +#define ICACHE_IF_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_HITOF_DEFAULT (_ICACHE_IF_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Flag */ +#define _ICACHE_IF_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF_DEFAULT (_ICACHE_IF_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF_DEFAULT (_ICACHE_IF_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Flag */ +#define _ICACHE_IF_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR_DEFAULT (_ICACHE_IF_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IF */ /* Bit fields for ICACHE IEN */ -#define _ICACHE_IEN_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IEN */ -#define _ICACHE_IEN_MASK 0x00000107UL /**< Mask for ICACHE_IEN */ -#define ICACHE_IEN_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Enable */ -#define _ICACHE_IEN_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ -#define _ICACHE_IEN_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ -#define _ICACHE_IEN_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_HITOF_DEFAULT (_ICACHE_IEN_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Enable */ -#define _ICACHE_IEN_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ -#define _ICACHE_IEN_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ -#define _ICACHE_IEN_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_MISSOF_DEFAULT (_ICACHE_IEN_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Enable */ -#define _ICACHE_IEN_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ -#define _ICACHE_IEN_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ -#define _ICACHE_IEN_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_AHITOF_DEFAULT (_ICACHE_IEN_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Enable */ -#define _ICACHE_IEN_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ -#define _ICACHE_IEN_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ -#define _ICACHE_IEN_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_RAMERROR_DEFAULT (_ICACHE_IEN_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define _ICACHE_IEN_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IEN */ +#define _ICACHE_IEN_MASK 0x00000107UL /**< Mask for ICACHE_IEN */ +#define ICACHE_IEN_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_HITOF_DEFAULT (_ICACHE_IEN_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Enable */ +#define _ICACHE_IEN_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF_DEFAULT (_ICACHE_IEN_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF_DEFAULT (_ICACHE_IEN_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Enable */ +#define _ICACHE_IEN_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR_DEFAULT (_ICACHE_IEN_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IEN */ /** @} End of group EFR32SG28_ICACHE_BitFields */ /** @} End of group EFR32SG28_ICACHE */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_keyscan.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_keyscan.h index 16fa528237..d91735131f 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_keyscan.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_KEYSCAN_H #define EFR32SG28_KEYSCAN_H - #define KEYSCAN_HAS_SET_CLEAR /**************************************************************************//** @@ -43,47 +42,46 @@ *****************************************************************************/ /** KEYSCAN Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< Enable */ - __IOM uint32_t SWRST; /**< Software Reset */ - __IOM uint32_t CFG; /**< Config */ - __IOM uint32_t CMD; /**< Command */ - __IOM uint32_t DELAY; /**< Delay */ - __IM uint32_t STATUS; /**< Status */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enables */ - uint32_t RESERVED0[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< Enable */ - __IOM uint32_t SWRST_SET; /**< Software Reset */ - __IOM uint32_t CFG_SET; /**< Config */ - __IOM uint32_t CMD_SET; /**< Command */ - __IOM uint32_t DELAY_SET; /**< Delay */ - __IM uint32_t STATUS_SET; /**< Status */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enables */ - uint32_t RESERVED1[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< Enable */ - __IOM uint32_t SWRST_CLR; /**< Software Reset */ - __IOM uint32_t CFG_CLR; /**< Config */ - __IOM uint32_t CMD_CLR; /**< Command */ - __IOM uint32_t DELAY_CLR; /**< Delay */ - __IM uint32_t STATUS_CLR; /**< Status */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ - uint32_t RESERVED2[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< Enable */ - __IOM uint32_t SWRST_TGL; /**< Software Reset */ - __IOM uint32_t CFG_TGL; /**< Config */ - __IOM uint32_t CMD_TGL; /**< Command */ - __IOM uint32_t DELAY_TGL; /**< Delay */ - __IM uint32_t STATUS_TGL; /**< Status */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t SWRST; /**< Software Reset */ + __IOM uint32_t CFG; /**< Config */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t DELAY; /**< Delay */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + uint32_t RESERVED0[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset */ + __IOM uint32_t CFG_SET; /**< Config */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t DELAY_SET; /**< Delay */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + uint32_t RESERVED1[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset */ + __IOM uint32_t CFG_CLR; /**< Config */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t DELAY_CLR; /**< Delay */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset */ + __IOM uint32_t CFG_TGL; /**< Config */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t DELAY_TGL; /**< Delay */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ } KEYSCAN_TypeDef; /** @} End of group EFR32SG28_KEYSCAN */ @@ -95,11 +93,11 @@ typedef struct *****************************************************************************/ /* Bit fields for KEYSCAN IPVERSION */ -#define _KEYSCAN_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for KEYSCAN_IPVERSION */ -#define _KEYSCAN_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for KEYSCAN_IPVERSION */ -#define _KEYSCAN_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for KEYSCAN_IPVERSION */ -#define _KEYSCAN_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for KEYSCAN_IPVERSION */ -#define _KEYSCAN_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_IPVERSION */ #define KEYSCAN_IPVERSION_IPVERSION_DEFAULT (_KEYSCAN_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IPVERSION */ /* Bit fields for KEYSCAN EN */ @@ -135,164 +133,164 @@ typedef struct #define KEYSCAN_SWRST_RESETTING_DEFAULT (_KEYSCAN_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_SWRST */ /* Bit fields for KEYSCAN CFG */ -#define _KEYSCAN_CFG_RESETVALUE 0x2501387FUL /**< Default value for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_MASK 0x7753FFFFUL /**< Mask for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_CLKDIV_SHIFT 0 /**< Shift value for KEYSCAN_CLKDIV */ -#define _KEYSCAN_CFG_CLKDIV_MASK 0x3FFFFUL /**< Bit mask for KEYSCAN_CLKDIV */ -#define _KEYSCAN_CFG_CLKDIV_DEFAULT 0x0001387FUL /**< Mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_CLKDIV_DEFAULT (_KEYSCAN_CFG_CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_SINGLEPRESS (0x1UL << 20) /**< Single Press */ -#define _KEYSCAN_CFG_SINGLEPRESS_SHIFT 20 /**< Shift value for KEYSCAN_SINGLEPRESS */ -#define _KEYSCAN_CFG_SINGLEPRESS_MASK 0x100000UL /**< Bit mask for KEYSCAN_SINGLEPRESS */ -#define _KEYSCAN_CFG_SINGLEPRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS 0x00000000UL /**< Mode MULTIPRESS for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS 0x00000001UL /**< Mode SINGLEPRESS for KEYSCAN_CFG */ -#define KEYSCAN_CFG_SINGLEPRESS_DEFAULT (_KEYSCAN_CFG_SINGLEPRESS_DEFAULT << 20) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS (_KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS << 20) /**< Shifted mode MULTIPRESS for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_RESETVALUE 0x2501387FUL /**< Default value for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_MASK 0x7753FFFFUL /**< Mask for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_CLKDIV_SHIFT 0 /**< Shift value for KEYSCAN_CLKDIV */ +#define _KEYSCAN_CFG_CLKDIV_MASK 0x3FFFFUL /**< Bit mask for KEYSCAN_CLKDIV */ +#define _KEYSCAN_CFG_CLKDIV_DEFAULT 0x0001387FUL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_CLKDIV_DEFAULT (_KEYSCAN_CFG_CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS (0x1UL << 20) /**< Single Press */ +#define _KEYSCAN_CFG_SINGLEPRESS_SHIFT 20 /**< Shift value for KEYSCAN_SINGLEPRESS */ +#define _KEYSCAN_CFG_SINGLEPRESS_MASK 0x100000UL /**< Bit mask for KEYSCAN_SINGLEPRESS */ +#define _KEYSCAN_CFG_SINGLEPRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS 0x00000000UL /**< Mode MULTIPRESS for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS 0x00000001UL /**< Mode SINGLEPRESS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS_DEFAULT (_KEYSCAN_CFG_SINGLEPRESS_DEFAULT << 20) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS (_KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS << 20) /**< Shifted mode MULTIPRESS for KEYSCAN_CFG */ #define KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS (_KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS << 20) /**< Shifted mode SINGLEPRESS for KEYSCAN_CFG */ -#define KEYSCAN_CFG_AUTOSTART (0x1UL << 22) /**< Automatically Start */ -#define _KEYSCAN_CFG_AUTOSTART_SHIFT 22 /**< Shift value for KEYSCAN_AUTOSTART */ -#define _KEYSCAN_CFG_AUTOSTART_MASK 0x400000UL /**< Bit mask for KEYSCAN_AUTOSTART */ -#define _KEYSCAN_CFG_AUTOSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS 0x00000000UL /**< Mode AUTOSTARTDIS for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN 0x00000001UL /**< Mode AUTOSTARTEN for KEYSCAN_CFG */ -#define KEYSCAN_CFG_AUTOSTART_DEFAULT (_KEYSCAN_CFG_AUTOSTART_DEFAULT << 22) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS << 22) /**< Shifted mode AUTOSTARTDIS for KEYSCAN_CFG */ -#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN << 22) /**< Shifted mode AUTOSTARTEN for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_SHIFT 24 /**< Shift value for KEYSCAN_NUMROWS */ -#define _KEYSCAN_CFG_NUMROWS_MASK 0x7000000UL /**< Bit mask for KEYSCAN_NUMROWS */ -#define _KEYSCAN_CFG_NUMROWS_DEFAULT 0x00000005UL /**< Mode DEFAULT for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_RSV1 0x00000000UL /**< Mode RSV1 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_RSV2 0x00000001UL /**< Mode RSV2 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_ROW3 0x00000002UL /**< Mode ROW3 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_ROW4 0x00000003UL /**< Mode ROW4 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_ROW5 0x00000004UL /**< Mode ROW5 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_ROW6 0x00000005UL /**< Mode ROW6 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_DEFAULT (_KEYSCAN_CFG_NUMROWS_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_RSV1 (_KEYSCAN_CFG_NUMROWS_RSV1 << 24) /**< Shifted mode RSV1 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_RSV2 (_KEYSCAN_CFG_NUMROWS_RSV2 << 24) /**< Shifted mode RSV2 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_ROW3 (_KEYSCAN_CFG_NUMROWS_ROW3 << 24) /**< Shifted mode ROW3 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_ROW4 (_KEYSCAN_CFG_NUMROWS_ROW4 << 24) /**< Shifted mode ROW4 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_ROW5 (_KEYSCAN_CFG_NUMROWS_ROW5 << 24) /**< Shifted mode ROW5 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_ROW6 (_KEYSCAN_CFG_NUMROWS_ROW6 << 24) /**< Shifted mode ROW6 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMCOLS_SHIFT 28 /**< Shift value for KEYSCAN_NUMCOLS */ -#define _KEYSCAN_CFG_NUMCOLS_MASK 0x70000000UL /**< Bit mask for KEYSCAN_NUMCOLS */ -#define _KEYSCAN_CFG_NUMCOLS_DEFAULT 0x00000002UL /**< Mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMCOLS_DEFAULT (_KEYSCAN_CFG_NUMCOLS_DEFAULT << 28) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART (0x1UL << 22) /**< Automatically Start */ +#define _KEYSCAN_CFG_AUTOSTART_SHIFT 22 /**< Shift value for KEYSCAN_AUTOSTART */ +#define _KEYSCAN_CFG_AUTOSTART_MASK 0x400000UL /**< Bit mask for KEYSCAN_AUTOSTART */ +#define _KEYSCAN_CFG_AUTOSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS 0x00000000UL /**< Mode AUTOSTARTDIS for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN 0x00000001UL /**< Mode AUTOSTARTEN for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_DEFAULT (_KEYSCAN_CFG_AUTOSTART_DEFAULT << 22) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS << 22) /**< Shifted mode AUTOSTARTDIS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN << 22) /**< Shifted mode AUTOSTARTEN for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_SHIFT 24 /**< Shift value for KEYSCAN_NUMROWS */ +#define _KEYSCAN_CFG_NUMROWS_MASK 0x7000000UL /**< Bit mask for KEYSCAN_NUMROWS */ +#define _KEYSCAN_CFG_NUMROWS_DEFAULT 0x00000005UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_RSV1 0x00000000UL /**< Mode RSV1 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_RSV2 0x00000001UL /**< Mode RSV2 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW3 0x00000002UL /**< Mode ROW3 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW4 0x00000003UL /**< Mode ROW4 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW5 0x00000004UL /**< Mode ROW5 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW6 0x00000005UL /**< Mode ROW6 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_DEFAULT (_KEYSCAN_CFG_NUMROWS_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_RSV1 (_KEYSCAN_CFG_NUMROWS_RSV1 << 24) /**< Shifted mode RSV1 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_RSV2 (_KEYSCAN_CFG_NUMROWS_RSV2 << 24) /**< Shifted mode RSV2 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW3 (_KEYSCAN_CFG_NUMROWS_ROW3 << 24) /**< Shifted mode ROW3 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW4 (_KEYSCAN_CFG_NUMROWS_ROW4 << 24) /**< Shifted mode ROW4 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW5 (_KEYSCAN_CFG_NUMROWS_ROW5 << 24) /**< Shifted mode ROW5 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW6 (_KEYSCAN_CFG_NUMROWS_ROW6 << 24) /**< Shifted mode ROW6 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMCOLS_SHIFT 28 /**< Shift value for KEYSCAN_NUMCOLS */ +#define _KEYSCAN_CFG_NUMCOLS_MASK 0x70000000UL /**< Bit mask for KEYSCAN_NUMCOLS */ +#define _KEYSCAN_CFG_NUMCOLS_DEFAULT 0x00000002UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMCOLS_DEFAULT (_KEYSCAN_CFG_NUMCOLS_DEFAULT << 28) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ /* Bit fields for KEYSCAN CMD */ -#define _KEYSCAN_CMD_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_CMD */ -#define _KEYSCAN_CMD_MASK 0x00000003UL /**< Mask for KEYSCAN_CMD */ -#define KEYSCAN_CMD_KEYSCANSTART (0x1UL << 0) /**< Keyscan Start */ -#define _KEYSCAN_CMD_KEYSCANSTART_SHIFT 0 /**< Shift value for KEYSCAN_KEYSCANSTART */ -#define _KEYSCAN_CMD_KEYSCANSTART_MASK 0x1UL /**< Bit mask for KEYSCAN_KEYSCANSTART */ -#define _KEYSCAN_CMD_KEYSCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ +#define _KEYSCAN_CMD_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_CMD */ +#define _KEYSCAN_CMD_MASK 0x00000003UL /**< Mask for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTART (0x1UL << 0) /**< Keyscan Start */ +#define _KEYSCAN_CMD_KEYSCANSTART_SHIFT 0 /**< Shift value for KEYSCAN_KEYSCANSTART */ +#define _KEYSCAN_CMD_KEYSCANSTART_MASK 0x1UL /**< Bit mask for KEYSCAN_KEYSCANSTART */ +#define _KEYSCAN_CMD_KEYSCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ #define KEYSCAN_CMD_KEYSCANSTART_DEFAULT (_KEYSCAN_CMD_KEYSCANSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CMD */ -#define KEYSCAN_CMD_KEYSCANSTOP (0x1UL << 1) /**< Keyscan Stop */ -#define _KEYSCAN_CMD_KEYSCANSTOP_SHIFT 1 /**< Shift value for KEYSCAN_KEYSCANSTOP */ -#define _KEYSCAN_CMD_KEYSCANSTOP_MASK 0x2UL /**< Bit mask for KEYSCAN_KEYSCANSTOP */ -#define _KEYSCAN_CMD_KEYSCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ -#define KEYSCAN_CMD_KEYSCANSTOP_DEFAULT (_KEYSCAN_CMD_KEYSCANSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTOP (0x1UL << 1) /**< Keyscan Stop */ +#define _KEYSCAN_CMD_KEYSCANSTOP_SHIFT 1 /**< Shift value for KEYSCAN_KEYSCANSTOP */ +#define _KEYSCAN_CMD_KEYSCANSTOP_MASK 0x2UL /**< Bit mask for KEYSCAN_KEYSCANSTOP */ +#define _KEYSCAN_CMD_KEYSCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTOP_DEFAULT (_KEYSCAN_CMD_KEYSCANSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_CMD */ /* Bit fields for KEYSCAN DELAY */ -#define _KEYSCAN_DELAY_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_MASK 0x0F0F0F00UL /**< Mask for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SHIFT 8 /**< Shift value for KEYSCAN_SCANDLY */ -#define _KEYSCAN_DELAY_SCANDLY_MASK 0xF00UL /**< Bit mask for KEYSCAN_SCANDLY */ -#define _KEYSCAN_DELAY_SCANDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY2 0x00000000UL /**< Mode SCANDLY2 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY4 0x00000001UL /**< Mode SCANDLY4 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY6 0x00000002UL /**< Mode SCANDLY6 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY8 0x00000003UL /**< Mode SCANDLY8 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY10 0x00000004UL /**< Mode SCANDLY10 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY12 0x00000005UL /**< Mode SCANDLY12 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY14 0x00000006UL /**< Mode SCANDLY14 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY16 0x00000007UL /**< Mode SCANDLY16 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY18 0x00000008UL /**< Mode SCANDLY18 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY20 0x00000009UL /**< Mode SCANDLY20 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY22 0x0000000AUL /**< Mode SCANDLY22 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY24 0x0000000BUL /**< Mode SCANDLY24 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY26 0x0000000CUL /**< Mode SCANDLY26 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY28 0x0000000DUL /**< Mode SCANDLY28 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY30 0x0000000EUL /**< Mode SCANDLY30 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY32 0x0000000FUL /**< Mode SCANDLY32 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_DEFAULT (_KEYSCAN_DELAY_SCANDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY2 (_KEYSCAN_DELAY_SCANDLY_SCANDLY2 << 8) /**< Shifted mode SCANDLY2 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY4 (_KEYSCAN_DELAY_SCANDLY_SCANDLY4 << 8) /**< Shifted mode SCANDLY4 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY6 (_KEYSCAN_DELAY_SCANDLY_SCANDLY6 << 8) /**< Shifted mode SCANDLY6 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY8 (_KEYSCAN_DELAY_SCANDLY_SCANDLY8 << 8) /**< Shifted mode SCANDLY8 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY10 (_KEYSCAN_DELAY_SCANDLY_SCANDLY10 << 8) /**< Shifted mode SCANDLY10 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY12 (_KEYSCAN_DELAY_SCANDLY_SCANDLY12 << 8) /**< Shifted mode SCANDLY12 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY14 (_KEYSCAN_DELAY_SCANDLY_SCANDLY14 << 8) /**< Shifted mode SCANDLY14 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY16 (_KEYSCAN_DELAY_SCANDLY_SCANDLY16 << 8) /**< Shifted mode SCANDLY16 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY18 (_KEYSCAN_DELAY_SCANDLY_SCANDLY18 << 8) /**< Shifted mode SCANDLY18 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY20 (_KEYSCAN_DELAY_SCANDLY_SCANDLY20 << 8) /**< Shifted mode SCANDLY20 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY22 (_KEYSCAN_DELAY_SCANDLY_SCANDLY22 << 8) /**< Shifted mode SCANDLY22 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY24 (_KEYSCAN_DELAY_SCANDLY_SCANDLY24 << 8) /**< Shifted mode SCANDLY24 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY26 (_KEYSCAN_DELAY_SCANDLY_SCANDLY26 << 8) /**< Shifted mode SCANDLY26 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY28 (_KEYSCAN_DELAY_SCANDLY_SCANDLY28 << 8) /**< Shifted mode SCANDLY28 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY30 (_KEYSCAN_DELAY_SCANDLY_SCANDLY30 << 8) /**< Shifted mode SCANDLY30 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY32 (_KEYSCAN_DELAY_SCANDLY_SCANDLY32 << 8) /**< Shifted mode SCANDLY32 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_SHIFT 16 /**< Shift value for KEYSCAN_DEBDLY */ -#define _KEYSCAN_DELAY_DEBDLY_MASK 0xF0000UL /**< Bit mask for KEYSCAN_DEBDLY */ -#define _KEYSCAN_DELAY_DEBDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY2 0x00000000UL /**< Mode DEBDLY2 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY4 0x00000001UL /**< Mode DEBDLY4 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY6 0x00000002UL /**< Mode DEBDLY6 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY8 0x00000003UL /**< Mode DEBDLY8 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY10 0x00000004UL /**< Mode DEBDLY10 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY12 0x00000005UL /**< Mode DEBDLY12 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY14 0x00000006UL /**< Mode DEBDLY14 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY16 0x00000007UL /**< Mode DEBDLY16 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY18 0x00000008UL /**< Mode DEBDLY18 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY20 0x00000009UL /**< Mode DEBDLY20 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY22 0x0000000AUL /**< Mode DEBDLY22 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY24 0x0000000BUL /**< Mode DEBDLY24 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY26 0x0000000CUL /**< Mode DEBDLY26 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY28 0x0000000DUL /**< Mode DEBDLY28 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY30 0x0000000EUL /**< Mode DEBDLY30 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY32 0x0000000FUL /**< Mode DEBDLY32 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEFAULT (_KEYSCAN_DELAY_DEBDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY2 (_KEYSCAN_DELAY_DEBDLY_DEBDLY2 << 16) /**< Shifted mode DEBDLY2 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY4 (_KEYSCAN_DELAY_DEBDLY_DEBDLY4 << 16) /**< Shifted mode DEBDLY4 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY6 (_KEYSCAN_DELAY_DEBDLY_DEBDLY6 << 16) /**< Shifted mode DEBDLY6 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY8 (_KEYSCAN_DELAY_DEBDLY_DEBDLY8 << 16) /**< Shifted mode DEBDLY8 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY10 (_KEYSCAN_DELAY_DEBDLY_DEBDLY10 << 16) /**< Shifted mode DEBDLY10 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY12 (_KEYSCAN_DELAY_DEBDLY_DEBDLY12 << 16) /**< Shifted mode DEBDLY12 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY14 (_KEYSCAN_DELAY_DEBDLY_DEBDLY14 << 16) /**< Shifted mode DEBDLY14 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY16 (_KEYSCAN_DELAY_DEBDLY_DEBDLY16 << 16) /**< Shifted mode DEBDLY16 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY18 (_KEYSCAN_DELAY_DEBDLY_DEBDLY18 << 16) /**< Shifted mode DEBDLY18 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY20 (_KEYSCAN_DELAY_DEBDLY_DEBDLY20 << 16) /**< Shifted mode DEBDLY20 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY22 (_KEYSCAN_DELAY_DEBDLY_DEBDLY22 << 16) /**< Shifted mode DEBDLY22 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY24 (_KEYSCAN_DELAY_DEBDLY_DEBDLY24 << 16) /**< Shifted mode DEBDLY24 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY26 (_KEYSCAN_DELAY_DEBDLY_DEBDLY26 << 16) /**< Shifted mode DEBDLY26 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY28 (_KEYSCAN_DELAY_DEBDLY_DEBDLY28 << 16) /**< Shifted mode DEBDLY28 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY30 (_KEYSCAN_DELAY_DEBDLY_DEBDLY30 << 16) /**< Shifted mode DEBDLY30 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY32 (_KEYSCAN_DELAY_DEBDLY_DEBDLY32 << 16) /**< Shifted mode DEBDLY32 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_SHIFT 24 /**< Shift value for KEYSCAN_STABDLY */ -#define _KEYSCAN_DELAY_STABDLY_MASK 0xF000000UL /**< Bit mask for KEYSCAN_STABDLY */ -#define _KEYSCAN_DELAY_STABDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY2 0x00000000UL /**< Mode STABDLY2 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY4 0x00000001UL /**< Mode STABDLY4 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY6 0x00000002UL /**< Mode STABDLY6 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY8 0x00000003UL /**< Mode STABDLY8 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY10 0x00000004UL /**< Mode STABDLY10 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY12 0x00000005UL /**< Mode STABDLY12 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY14 0x00000006UL /**< Mode STABDLY14 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY16 0x00000007UL /**< Mode STABDLY16 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY18 0x00000008UL /**< Mode STABDLY18 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY20 0x00000009UL /**< Mode STABDLY20 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY22 0x0000000AUL /**< Mode STABDLY22 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY24 0x0000000BUL /**< Mode STABDLY24 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY26 0x0000000CUL /**< Mode STABDLY26 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY28 0x0000000DUL /**< Mode STABDLY28 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY30 0x0000000EUL /**< Mode STABDLY30 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY32 0x0000000FUL /**< Mode STABDLY32 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_DEFAULT (_KEYSCAN_DELAY_STABDLY_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY2 (_KEYSCAN_DELAY_STABDLY_STABDLY2 << 24) /**< Shifted mode STABDLY2 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY4 (_KEYSCAN_DELAY_STABDLY_STABDLY4 << 24) /**< Shifted mode STABDLY4 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY6 (_KEYSCAN_DELAY_STABDLY_STABDLY6 << 24) /**< Shifted mode STABDLY6 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY8 (_KEYSCAN_DELAY_STABDLY_STABDLY8 << 24) /**< Shifted mode STABDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_MASK 0x0F0F0F00UL /**< Mask for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SHIFT 8 /**< Shift value for KEYSCAN_SCANDLY */ +#define _KEYSCAN_DELAY_SCANDLY_MASK 0xF00UL /**< Bit mask for KEYSCAN_SCANDLY */ +#define _KEYSCAN_DELAY_SCANDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY2 0x00000000UL /**< Mode SCANDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY4 0x00000001UL /**< Mode SCANDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY6 0x00000002UL /**< Mode SCANDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY8 0x00000003UL /**< Mode SCANDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY10 0x00000004UL /**< Mode SCANDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY12 0x00000005UL /**< Mode SCANDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY14 0x00000006UL /**< Mode SCANDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY16 0x00000007UL /**< Mode SCANDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY18 0x00000008UL /**< Mode SCANDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY20 0x00000009UL /**< Mode SCANDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY22 0x0000000AUL /**< Mode SCANDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY24 0x0000000BUL /**< Mode SCANDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY26 0x0000000CUL /**< Mode SCANDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY28 0x0000000DUL /**< Mode SCANDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY30 0x0000000EUL /**< Mode SCANDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY32 0x0000000FUL /**< Mode SCANDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_DEFAULT (_KEYSCAN_DELAY_SCANDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY2 (_KEYSCAN_DELAY_SCANDLY_SCANDLY2 << 8) /**< Shifted mode SCANDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY4 (_KEYSCAN_DELAY_SCANDLY_SCANDLY4 << 8) /**< Shifted mode SCANDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY6 (_KEYSCAN_DELAY_SCANDLY_SCANDLY6 << 8) /**< Shifted mode SCANDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY8 (_KEYSCAN_DELAY_SCANDLY_SCANDLY8 << 8) /**< Shifted mode SCANDLY8 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY10 (_KEYSCAN_DELAY_SCANDLY_SCANDLY10 << 8) /**< Shifted mode SCANDLY10 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY12 (_KEYSCAN_DELAY_SCANDLY_SCANDLY12 << 8) /**< Shifted mode SCANDLY12 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY14 (_KEYSCAN_DELAY_SCANDLY_SCANDLY14 << 8) /**< Shifted mode SCANDLY14 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY16 (_KEYSCAN_DELAY_SCANDLY_SCANDLY16 << 8) /**< Shifted mode SCANDLY16 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY18 (_KEYSCAN_DELAY_SCANDLY_SCANDLY18 << 8) /**< Shifted mode SCANDLY18 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY20 (_KEYSCAN_DELAY_SCANDLY_SCANDLY20 << 8) /**< Shifted mode SCANDLY20 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY22 (_KEYSCAN_DELAY_SCANDLY_SCANDLY22 << 8) /**< Shifted mode SCANDLY22 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY24 (_KEYSCAN_DELAY_SCANDLY_SCANDLY24 << 8) /**< Shifted mode SCANDLY24 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY26 (_KEYSCAN_DELAY_SCANDLY_SCANDLY26 << 8) /**< Shifted mode SCANDLY26 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY28 (_KEYSCAN_DELAY_SCANDLY_SCANDLY28 << 8) /**< Shifted mode SCANDLY28 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY30 (_KEYSCAN_DELAY_SCANDLY_SCANDLY30 << 8) /**< Shifted mode SCANDLY30 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY32 (_KEYSCAN_DELAY_SCANDLY_SCANDLY32 << 8) /**< Shifted mode SCANDLY32 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_SHIFT 16 /**< Shift value for KEYSCAN_DEBDLY */ +#define _KEYSCAN_DELAY_DEBDLY_MASK 0xF0000UL /**< Bit mask for KEYSCAN_DEBDLY */ +#define _KEYSCAN_DELAY_DEBDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY2 0x00000000UL /**< Mode DEBDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY4 0x00000001UL /**< Mode DEBDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY6 0x00000002UL /**< Mode DEBDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY8 0x00000003UL /**< Mode DEBDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY10 0x00000004UL /**< Mode DEBDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY12 0x00000005UL /**< Mode DEBDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY14 0x00000006UL /**< Mode DEBDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY16 0x00000007UL /**< Mode DEBDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY18 0x00000008UL /**< Mode DEBDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY20 0x00000009UL /**< Mode DEBDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY22 0x0000000AUL /**< Mode DEBDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY24 0x0000000BUL /**< Mode DEBDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY26 0x0000000CUL /**< Mode DEBDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY28 0x0000000DUL /**< Mode DEBDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY30 0x0000000EUL /**< Mode DEBDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY32 0x0000000FUL /**< Mode DEBDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEFAULT (_KEYSCAN_DELAY_DEBDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY2 (_KEYSCAN_DELAY_DEBDLY_DEBDLY2 << 16) /**< Shifted mode DEBDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY4 (_KEYSCAN_DELAY_DEBDLY_DEBDLY4 << 16) /**< Shifted mode DEBDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY6 (_KEYSCAN_DELAY_DEBDLY_DEBDLY6 << 16) /**< Shifted mode DEBDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY8 (_KEYSCAN_DELAY_DEBDLY_DEBDLY8 << 16) /**< Shifted mode DEBDLY8 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY10 (_KEYSCAN_DELAY_DEBDLY_DEBDLY10 << 16) /**< Shifted mode DEBDLY10 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY12 (_KEYSCAN_DELAY_DEBDLY_DEBDLY12 << 16) /**< Shifted mode DEBDLY12 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY14 (_KEYSCAN_DELAY_DEBDLY_DEBDLY14 << 16) /**< Shifted mode DEBDLY14 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY16 (_KEYSCAN_DELAY_DEBDLY_DEBDLY16 << 16) /**< Shifted mode DEBDLY16 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY18 (_KEYSCAN_DELAY_DEBDLY_DEBDLY18 << 16) /**< Shifted mode DEBDLY18 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY20 (_KEYSCAN_DELAY_DEBDLY_DEBDLY20 << 16) /**< Shifted mode DEBDLY20 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY22 (_KEYSCAN_DELAY_DEBDLY_DEBDLY22 << 16) /**< Shifted mode DEBDLY22 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY24 (_KEYSCAN_DELAY_DEBDLY_DEBDLY24 << 16) /**< Shifted mode DEBDLY24 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY26 (_KEYSCAN_DELAY_DEBDLY_DEBDLY26 << 16) /**< Shifted mode DEBDLY26 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY28 (_KEYSCAN_DELAY_DEBDLY_DEBDLY28 << 16) /**< Shifted mode DEBDLY28 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY30 (_KEYSCAN_DELAY_DEBDLY_DEBDLY30 << 16) /**< Shifted mode DEBDLY30 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY32 (_KEYSCAN_DELAY_DEBDLY_DEBDLY32 << 16) /**< Shifted mode DEBDLY32 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_SHIFT 24 /**< Shift value for KEYSCAN_STABDLY */ +#define _KEYSCAN_DELAY_STABDLY_MASK 0xF000000UL /**< Bit mask for KEYSCAN_STABDLY */ +#define _KEYSCAN_DELAY_STABDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY2 0x00000000UL /**< Mode STABDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY4 0x00000001UL /**< Mode STABDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY6 0x00000002UL /**< Mode STABDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY8 0x00000003UL /**< Mode STABDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY10 0x00000004UL /**< Mode STABDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY12 0x00000005UL /**< Mode STABDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY14 0x00000006UL /**< Mode STABDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY16 0x00000007UL /**< Mode STABDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY18 0x00000008UL /**< Mode STABDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY20 0x00000009UL /**< Mode STABDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY22 0x0000000AUL /**< Mode STABDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY24 0x0000000BUL /**< Mode STABDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY26 0x0000000CUL /**< Mode STABDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY28 0x0000000DUL /**< Mode STABDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY30 0x0000000EUL /**< Mode STABDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY32 0x0000000FUL /**< Mode STABDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_DEFAULT (_KEYSCAN_DELAY_STABDLY_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY2 (_KEYSCAN_DELAY_STABDLY_STABDLY2 << 24) /**< Shifted mode STABDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY4 (_KEYSCAN_DELAY_STABDLY_STABDLY4 << 24) /**< Shifted mode STABDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY6 (_KEYSCAN_DELAY_STABDLY_STABDLY6 << 24) /**< Shifted mode STABDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY8 (_KEYSCAN_DELAY_STABDLY_STABDLY8 << 24) /**< Shifted mode STABDLY8 for KEYSCAN_DELAY */ #define KEYSCAN_DELAY_STABDLY_STABDLY10 (_KEYSCAN_DELAY_STABDLY_STABDLY10 << 24) /**< Shifted mode STABDLY10 for KEYSCAN_DELAY */ #define KEYSCAN_DELAY_STABDLY_STABDLY12 (_KEYSCAN_DELAY_STABDLY_STABDLY12 << 24) /**< Shifted mode STABDLY12 for KEYSCAN_DELAY */ #define KEYSCAN_DELAY_STABDLY_STABDLY14 (_KEYSCAN_DELAY_STABDLY_STABDLY14 << 24) /**< Shifted mode STABDLY14 for KEYSCAN_DELAY */ @@ -307,30 +305,30 @@ typedef struct #define KEYSCAN_DELAY_STABDLY_STABDLY32 (_KEYSCAN_DELAY_STABDLY_STABDLY32 << 24) /**< Shifted mode STABDLY32 for KEYSCAN_DELAY */ /* Bit fields for KEYSCAN STATUS */ -#define _KEYSCAN_STATUS_RESETVALUE 0x40000000UL /**< Default value for KEYSCAN_STATUS */ -#define _KEYSCAN_STATUS_MASK 0xC701003FUL /**< Mask for KEYSCAN_STATUS */ -#define _KEYSCAN_STATUS_ROW_SHIFT 0 /**< Shift value for KEYSCAN_ROW */ -#define _KEYSCAN_STATUS_ROW_MASK 0x3FUL /**< Bit mask for KEYSCAN_ROW */ -#define _KEYSCAN_STATUS_ROW_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_ROW_DEFAULT (_KEYSCAN_STATUS_ROW_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_RUNNING (0x1UL << 16) /**< Running */ -#define _KEYSCAN_STATUS_RUNNING_SHIFT 16 /**< Shift value for KEYSCAN_RUNNING */ -#define _KEYSCAN_STATUS_RUNNING_MASK 0x10000UL /**< Bit mask for KEYSCAN_RUNNING */ -#define _KEYSCAN_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_RUNNING_DEFAULT (_KEYSCAN_STATUS_RUNNING_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ -#define _KEYSCAN_STATUS_COL_SHIFT 24 /**< Shift value for KEYSCAN_COL */ -#define _KEYSCAN_STATUS_COL_MASK 0x7000000UL /**< Bit mask for KEYSCAN_COL */ -#define _KEYSCAN_STATUS_COL_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_COL_DEFAULT (_KEYSCAN_STATUS_COL_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_NOKEY (0x1UL << 30) /**< No Key pressed status */ -#define _KEYSCAN_STATUS_NOKEY_SHIFT 30 /**< Shift value for KEYSCAN_NOKEY */ -#define _KEYSCAN_STATUS_NOKEY_MASK 0x40000000UL /**< Bit mask for KEYSCAN_NOKEY */ -#define _KEYSCAN_STATUS_NOKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_NOKEY_DEFAULT (_KEYSCAN_STATUS_NOKEY_DEFAULT << 30) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy */ -#define _KEYSCAN_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for KEYSCAN_SYNCBUSY */ -#define _KEYSCAN_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for KEYSCAN_SYNCBUSY */ -#define _KEYSCAN_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_RESETVALUE 0x40000000UL /**< Default value for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_MASK 0xC701003FUL /**< Mask for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_ROW_SHIFT 0 /**< Shift value for KEYSCAN_ROW */ +#define _KEYSCAN_STATUS_ROW_MASK 0x3FUL /**< Bit mask for KEYSCAN_ROW */ +#define _KEYSCAN_STATUS_ROW_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_ROW_DEFAULT (_KEYSCAN_STATUS_ROW_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_RUNNING (0x1UL << 16) /**< Running */ +#define _KEYSCAN_STATUS_RUNNING_SHIFT 16 /**< Shift value for KEYSCAN_RUNNING */ +#define _KEYSCAN_STATUS_RUNNING_MASK 0x10000UL /**< Bit mask for KEYSCAN_RUNNING */ +#define _KEYSCAN_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_RUNNING_DEFAULT (_KEYSCAN_STATUS_RUNNING_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_COL_SHIFT 24 /**< Shift value for KEYSCAN_COL */ +#define _KEYSCAN_STATUS_COL_MASK 0x7000000UL /**< Bit mask for KEYSCAN_COL */ +#define _KEYSCAN_STATUS_COL_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_COL_DEFAULT (_KEYSCAN_STATUS_COL_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_NOKEY (0x1UL << 30) /**< No Key pressed status */ +#define _KEYSCAN_STATUS_NOKEY_SHIFT 30 /**< Shift value for KEYSCAN_NOKEY */ +#define _KEYSCAN_STATUS_NOKEY_MASK 0x40000000UL /**< Bit mask for KEYSCAN_NOKEY */ +#define _KEYSCAN_STATUS_NOKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_NOKEY_DEFAULT (_KEYSCAN_STATUS_NOKEY_DEFAULT << 30) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy */ +#define _KEYSCAN_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for KEYSCAN_SYNCBUSY */ +#define _KEYSCAN_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for KEYSCAN_SYNCBUSY */ +#define _KEYSCAN_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ #define KEYSCAN_STATUS_SYNCBUSY_DEFAULT (_KEYSCAN_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ /* Bit fields for KEYSCAN IF */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lcd.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lcd.h index 7255127a71..fdbf3908ce 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lcd.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lcd.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_LCD_H #define EFR32SG28_LCD_H - #define LCD_HAS_SET_CLEAR /**************************************************************************//** @@ -43,151 +42,150 @@ *****************************************************************************/ /** LCD Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< Enable */ - __IOM uint32_t SWRST; /**< Software Reset */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command register */ - __IOM uint32_t DISPCTRL; /**< Display Control Register */ - __IOM uint32_t BACFG; /**< Blink and Animation Config Register */ - __IOM uint32_t BACTRL; /**< Blink and Animation Control Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t AREGA; /**< Animation Register A */ - __IOM uint32_t AREGB; /**< Animation Register B */ - __IOM uint32_t IF; /**< Interrupt Enable Register */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - __IOM uint32_t BIASCTRL; /**< Analog BIAS Control */ - __IOM uint32_t DISPCTRLX; /**< Display Control Extended */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD0; /**< Segment Data Register 0 */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD1; /**< Segment Data Register 1 */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD2; /**< Segment Data Register 2 */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD3; /**< Segment Data Register 3 */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD4; /**< Segment Data Register 4 */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD5; /**< Segment Data Register 5 */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD6; /**< Segment Data Register 6 */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD7; /**< Segment Data Register 7 */ - uint32_t RESERVED8[17U]; /**< Reserved for future use */ - __IOM uint32_t UPDATECTRL; /**< Update Control */ - uint32_t RESERVED9[11U]; /**< Reserved for future use */ - __IOM uint32_t FRAMERATE; /**< Frame Rate */ - uint32_t RESERVED10[963U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< Enable */ - __IOM uint32_t SWRST_SET; /**< Software Reset */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command register */ - __IOM uint32_t DISPCTRL_SET; /**< Display Control Register */ - __IOM uint32_t BACFG_SET; /**< Blink and Animation Config Register */ - __IOM uint32_t BACTRL_SET; /**< Blink and Animation Control Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t AREGA_SET; /**< Animation Register A */ - __IOM uint32_t AREGB_SET; /**< Animation Register B */ - __IOM uint32_t IF_SET; /**< Interrupt Enable Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - __IOM uint32_t BIASCTRL_SET; /**< Analog BIAS Control */ - __IOM uint32_t DISPCTRLX_SET; /**< Display Control Extended */ - uint32_t RESERVED11[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD0_SET; /**< Segment Data Register 0 */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD1_SET; /**< Segment Data Register 1 */ - uint32_t RESERVED13[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD2_SET; /**< Segment Data Register 2 */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD3_SET; /**< Segment Data Register 3 */ - uint32_t RESERVED15[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD4_SET; /**< Segment Data Register 4 */ - uint32_t RESERVED16[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD5_SET; /**< Segment Data Register 5 */ - uint32_t RESERVED17[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD6_SET; /**< Segment Data Register 6 */ - uint32_t RESERVED18[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD7_SET; /**< Segment Data Register 7 */ - uint32_t RESERVED19[17U]; /**< Reserved for future use */ - __IOM uint32_t UPDATECTRL_SET; /**< Update Control */ - uint32_t RESERVED20[11U]; /**< Reserved for future use */ - __IOM uint32_t FRAMERATE_SET; /**< Frame Rate */ - uint32_t RESERVED21[963U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< Enable */ - __IOM uint32_t SWRST_CLR; /**< Software Reset */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command register */ - __IOM uint32_t DISPCTRL_CLR; /**< Display Control Register */ - __IOM uint32_t BACFG_CLR; /**< Blink and Animation Config Register */ - __IOM uint32_t BACTRL_CLR; /**< Blink and Animation Control Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t AREGA_CLR; /**< Animation Register A */ - __IOM uint32_t AREGB_CLR; /**< Animation Register B */ - __IOM uint32_t IF_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - __IOM uint32_t BIASCTRL_CLR; /**< Analog BIAS Control */ - __IOM uint32_t DISPCTRLX_CLR; /**< Display Control Extended */ - uint32_t RESERVED22[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD0_CLR; /**< Segment Data Register 0 */ - uint32_t RESERVED23[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD1_CLR; /**< Segment Data Register 1 */ - uint32_t RESERVED24[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD2_CLR; /**< Segment Data Register 2 */ - uint32_t RESERVED25[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD3_CLR; /**< Segment Data Register 3 */ - uint32_t RESERVED26[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD4_CLR; /**< Segment Data Register 4 */ - uint32_t RESERVED27[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD5_CLR; /**< Segment Data Register 5 */ - uint32_t RESERVED28[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD6_CLR; /**< Segment Data Register 6 */ - uint32_t RESERVED29[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD7_CLR; /**< Segment Data Register 7 */ - uint32_t RESERVED30[17U]; /**< Reserved for future use */ - __IOM uint32_t UPDATECTRL_CLR; /**< Update Control */ - uint32_t RESERVED31[11U]; /**< Reserved for future use */ - __IOM uint32_t FRAMERATE_CLR; /**< Frame Rate */ - uint32_t RESERVED32[963U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< Enable */ - __IOM uint32_t SWRST_TGL; /**< Software Reset */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command register */ - __IOM uint32_t DISPCTRL_TGL; /**< Display Control Register */ - __IOM uint32_t BACFG_TGL; /**< Blink and Animation Config Register */ - __IOM uint32_t BACTRL_TGL; /**< Blink and Animation Control Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t AREGA_TGL; /**< Animation Register A */ - __IOM uint32_t AREGB_TGL; /**< Animation Register B */ - __IOM uint32_t IF_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - __IOM uint32_t BIASCTRL_TGL; /**< Analog BIAS Control */ - __IOM uint32_t DISPCTRLX_TGL; /**< Display Control Extended */ - uint32_t RESERVED33[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD0_TGL; /**< Segment Data Register 0 */ - uint32_t RESERVED34[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD1_TGL; /**< Segment Data Register 1 */ - uint32_t RESERVED35[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD2_TGL; /**< Segment Data Register 2 */ - uint32_t RESERVED36[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD3_TGL; /**< Segment Data Register 3 */ - uint32_t RESERVED37[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD4_TGL; /**< Segment Data Register 4 */ - uint32_t RESERVED38[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD5_TGL; /**< Segment Data Register 5 */ - uint32_t RESERVED39[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD6_TGL; /**< Segment Data Register 6 */ - uint32_t RESERVED40[1U]; /**< Reserved for future use */ - __IOM uint32_t SEGD7_TGL; /**< Segment Data Register 7 */ - uint32_t RESERVED41[17U]; /**< Reserved for future use */ - __IOM uint32_t UPDATECTRL_TGL; /**< Update Control */ - uint32_t RESERVED42[11U]; /**< Reserved for future use */ - __IOM uint32_t FRAMERATE_TGL; /**< Frame Rate */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t SWRST; /**< Software Reset */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command register */ + __IOM uint32_t DISPCTRL; /**< Display Control Register */ + __IOM uint32_t BACFG; /**< Blink and Animation Config Register */ + __IOM uint32_t BACTRL; /**< Blink and Animation Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t AREGA; /**< Animation Register A */ + __IOM uint32_t AREGB; /**< Animation Register B */ + __IOM uint32_t IF; /**< Interrupt Enable Register */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IOM uint32_t BIASCTRL; /**< Analog BIAS Control */ + __IOM uint32_t DISPCTRLX; /**< Display Control Extended */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD0; /**< Segment Data Register 0 */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD1; /**< Segment Data Register 1 */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD2; /**< Segment Data Register 2 */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD3; /**< Segment Data Register 3 */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD4; /**< Segment Data Register 4 */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD5; /**< Segment Data Register 5 */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD6; /**< Segment Data Register 6 */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD7; /**< Segment Data Register 7 */ + uint32_t RESERVED8[17U]; /**< Reserved for future use */ + __IOM uint32_t UPDATECTRL; /**< Update Control */ + uint32_t RESERVED9[11U]; /**< Reserved for future use */ + __IOM uint32_t FRAMERATE; /**< Frame Rate */ + uint32_t RESERVED10[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command register */ + __IOM uint32_t DISPCTRL_SET; /**< Display Control Register */ + __IOM uint32_t BACFG_SET; /**< Blink and Animation Config Register */ + __IOM uint32_t BACTRL_SET; /**< Blink and Animation Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t AREGA_SET; /**< Animation Register A */ + __IOM uint32_t AREGB_SET; /**< Animation Register B */ + __IOM uint32_t IF_SET; /**< Interrupt Enable Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IOM uint32_t BIASCTRL_SET; /**< Analog BIAS Control */ + __IOM uint32_t DISPCTRLX_SET; /**< Display Control Extended */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD0_SET; /**< Segment Data Register 0 */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD1_SET; /**< Segment Data Register 1 */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD2_SET; /**< Segment Data Register 2 */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD3_SET; /**< Segment Data Register 3 */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD4_SET; /**< Segment Data Register 4 */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD5_SET; /**< Segment Data Register 5 */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD6_SET; /**< Segment Data Register 6 */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD7_SET; /**< Segment Data Register 7 */ + uint32_t RESERVED19[17U]; /**< Reserved for future use */ + __IOM uint32_t UPDATECTRL_SET; /**< Update Control */ + uint32_t RESERVED20[11U]; /**< Reserved for future use */ + __IOM uint32_t FRAMERATE_SET; /**< Frame Rate */ + uint32_t RESERVED21[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command register */ + __IOM uint32_t DISPCTRL_CLR; /**< Display Control Register */ + __IOM uint32_t BACFG_CLR; /**< Blink and Animation Config Register */ + __IOM uint32_t BACTRL_CLR; /**< Blink and Animation Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t AREGA_CLR; /**< Animation Register A */ + __IOM uint32_t AREGB_CLR; /**< Animation Register B */ + __IOM uint32_t IF_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IOM uint32_t BIASCTRL_CLR; /**< Analog BIAS Control */ + __IOM uint32_t DISPCTRLX_CLR; /**< Display Control Extended */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD0_CLR; /**< Segment Data Register 0 */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD1_CLR; /**< Segment Data Register 1 */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD2_CLR; /**< Segment Data Register 2 */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD3_CLR; /**< Segment Data Register 3 */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD4_CLR; /**< Segment Data Register 4 */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD5_CLR; /**< Segment Data Register 5 */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD6_CLR; /**< Segment Data Register 6 */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD7_CLR; /**< Segment Data Register 7 */ + uint32_t RESERVED30[17U]; /**< Reserved for future use */ + __IOM uint32_t UPDATECTRL_CLR; /**< Update Control */ + uint32_t RESERVED31[11U]; /**< Reserved for future use */ + __IOM uint32_t FRAMERATE_CLR; /**< Frame Rate */ + uint32_t RESERVED32[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command register */ + __IOM uint32_t DISPCTRL_TGL; /**< Display Control Register */ + __IOM uint32_t BACFG_TGL; /**< Blink and Animation Config Register */ + __IOM uint32_t BACTRL_TGL; /**< Blink and Animation Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t AREGA_TGL; /**< Animation Register A */ + __IOM uint32_t AREGB_TGL; /**< Animation Register B */ + __IOM uint32_t IF_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IOM uint32_t BIASCTRL_TGL; /**< Analog BIAS Control */ + __IOM uint32_t DISPCTRLX_TGL; /**< Display Control Extended */ + uint32_t RESERVED33[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD0_TGL; /**< Segment Data Register 0 */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD1_TGL; /**< Segment Data Register 1 */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD2_TGL; /**< Segment Data Register 2 */ + uint32_t RESERVED36[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD3_TGL; /**< Segment Data Register 3 */ + uint32_t RESERVED37[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD4_TGL; /**< Segment Data Register 4 */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD5_TGL; /**< Segment Data Register 5 */ + uint32_t RESERVED39[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD6_TGL; /**< Segment Data Register 6 */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD7_TGL; /**< Segment Data Register 7 */ + uint32_t RESERVED41[17U]; /**< Reserved for future use */ + __IOM uint32_t UPDATECTRL_TGL; /**< Update Control */ + uint32_t RESERVED42[11U]; /**< Reserved for future use */ + __IOM uint32_t FRAMERATE_TGL; /**< Frame Rate */ } LCD_TypeDef; /** @} End of group EFR32SG28_LCD */ @@ -199,509 +197,509 @@ typedef struct *****************************************************************************/ /* Bit fields for LCD IPVERSION */ -#define _LCD_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for LCD_IPVERSION */ -#define _LCD_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LCD_IPVERSION */ -#define _LCD_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LCD_IPVERSION */ -#define _LCD_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_IPVERSION */ -#define _LCD_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for LCD_IPVERSION */ -#define LCD_IPVERSION_IPVERSION_DEFAULT (_LCD_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IPVERSION */ +#define _LCD_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for LCD_IPVERSION */ +#define _LCD_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LCD_IPVERSION */ +#define _LCD_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LCD_IPVERSION */ +#define _LCD_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_IPVERSION */ +#define _LCD_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for LCD_IPVERSION */ +#define LCD_IPVERSION_IPVERSION_DEFAULT (_LCD_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IPVERSION */ /* Bit fields for LCD EN */ -#define _LCD_EN_RESETVALUE 0x00000000UL /**< Default value for LCD_EN */ -#define _LCD_EN_MASK 0x00000003UL /**< Mask for LCD_EN */ -#define LCD_EN_EN (0x1UL << 0) /**< Enable */ -#define _LCD_EN_EN_SHIFT 0 /**< Shift value for LCD_EN */ -#define _LCD_EN_EN_MASK 0x1UL /**< Bit mask for LCD_EN */ -#define _LCD_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_EN */ -#define _LCD_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_EN */ -#define _LCD_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_EN */ -#define LCD_EN_EN_DEFAULT (_LCD_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_EN */ -#define LCD_EN_EN_DISABLE (_LCD_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for LCD_EN */ -#define LCD_EN_EN_ENABLE (_LCD_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for LCD_EN */ -#define LCD_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _LCD_EN_DISABLING_SHIFT 1 /**< Shift value for LCD_DISABLING */ -#define _LCD_EN_DISABLING_MASK 0x2UL /**< Bit mask for LCD_DISABLING */ -#define _LCD_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_EN */ -#define LCD_EN_DISABLING_DEFAULT (_LCD_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_EN */ +#define _LCD_EN_RESETVALUE 0x00000000UL /**< Default value for LCD_EN */ +#define _LCD_EN_MASK 0x00000003UL /**< Mask for LCD_EN */ +#define LCD_EN_EN (0x1UL << 0) /**< Enable */ +#define _LCD_EN_EN_SHIFT 0 /**< Shift value for LCD_EN */ +#define _LCD_EN_EN_MASK 0x1UL /**< Bit mask for LCD_EN */ +#define _LCD_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_EN */ +#define _LCD_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_EN */ +#define _LCD_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_EN */ +#define LCD_EN_EN_DEFAULT (_LCD_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_EN */ +#define LCD_EN_EN_DISABLE (_LCD_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for LCD_EN */ +#define LCD_EN_EN_ENABLE (_LCD_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for LCD_EN */ +#define LCD_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _LCD_EN_DISABLING_SHIFT 1 /**< Shift value for LCD_DISABLING */ +#define _LCD_EN_DISABLING_MASK 0x2UL /**< Bit mask for LCD_DISABLING */ +#define _LCD_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_EN */ +#define LCD_EN_DISABLING_DEFAULT (_LCD_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_EN */ /* Bit fields for LCD SWRST */ -#define _LCD_SWRST_RESETVALUE 0x00000000UL /**< Default value for LCD_SWRST */ -#define _LCD_SWRST_MASK 0x00000003UL /**< Mask for LCD_SWRST */ -#define LCD_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ -#define _LCD_SWRST_SWRST_SHIFT 0 /**< Shift value for LCD_SWRST */ -#define _LCD_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LCD_SWRST */ -#define _LCD_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SWRST */ -#define LCD_SWRST_SWRST_DEFAULT (_LCD_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SWRST */ -#define LCD_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ -#define _LCD_SWRST_RESETTING_SHIFT 1 /**< Shift value for LCD_RESETTING */ -#define _LCD_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LCD_RESETTING */ -#define _LCD_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SWRST */ -#define LCD_SWRST_RESETTING_DEFAULT (_LCD_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_SWRST */ +#define _LCD_SWRST_RESETVALUE 0x00000000UL /**< Default value for LCD_SWRST */ +#define _LCD_SWRST_MASK 0x00000003UL /**< Mask for LCD_SWRST */ +#define LCD_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _LCD_SWRST_SWRST_SHIFT 0 /**< Shift value for LCD_SWRST */ +#define _LCD_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LCD_SWRST */ +#define _LCD_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SWRST */ +#define LCD_SWRST_SWRST_DEFAULT (_LCD_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SWRST */ +#define LCD_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _LCD_SWRST_RESETTING_SHIFT 1 /**< Shift value for LCD_RESETTING */ +#define _LCD_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LCD_RESETTING */ +#define _LCD_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SWRST */ +#define LCD_SWRST_RESETTING_DEFAULT (_LCD_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_SWRST */ /* Bit fields for LCD CTRL */ -#define _LCD_CTRL_RESETVALUE 0x00100000UL /**< Default value for LCD_CTRL */ -#define _LCD_CTRL_MASK 0x7F1D0006UL /**< Mask for LCD_CTRL */ -#define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */ -#define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */ -#define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ -#define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */ -#define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000001UL /**< Mode FRAMESTART for LCD_CTRL */ -#define _LCD_CTRL_UDCTRL_FCEVENT 0x00000002UL /**< Mode FCEVENT for LCD_CTRL */ -#define _LCD_CTRL_UDCTRL_DISPLAYEVENT 0x00000003UL /**< Mode DISPLAYEVENT for LCD_CTRL */ -#define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CTRL */ -#define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) /**< Shifted mode REGULAR for LCD_CTRL */ -#define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */ -#define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) /**< Shifted mode FCEVENT for LCD_CTRL */ -#define LCD_CTRL_UDCTRL_DISPLAYEVENT (_LCD_CTRL_UDCTRL_DISPLAYEVENT << 1) /**< Shifted mode DISPLAYEVENT for LCD_CTRL */ -#define LCD_CTRL_DSC (0x1UL << 16) /**< Direct Segment Control */ -#define _LCD_CTRL_DSC_SHIFT 16 /**< Shift value for LCD_DSC */ -#define _LCD_CTRL_DSC_MASK 0x10000UL /**< Bit mask for LCD_DSC */ -#define _LCD_CTRL_DSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ -#define _LCD_CTRL_DSC_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_CTRL */ -#define _LCD_CTRL_DSC_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_CTRL */ -#define LCD_CTRL_DSC_DEFAULT (_LCD_CTRL_DSC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_CTRL */ -#define LCD_CTRL_DSC_DISABLE (_LCD_CTRL_DSC_DISABLE << 16) /**< Shifted mode DISABLE for LCD_CTRL */ -#define LCD_CTRL_DSC_ENABLE (_LCD_CTRL_DSC_ENABLE << 16) /**< Shifted mode ENABLE for LCD_CTRL */ -#define _LCD_CTRL_WARMUPDLY_SHIFT 18 /**< Shift value for LCD_WARMUPDLY */ -#define _LCD_CTRL_WARMUPDLY_MASK 0x1C0000UL /**< Bit mask for LCD_WARMUPDLY */ -#define _LCD_CTRL_WARMUPDLY_DEFAULT 0x00000004UL /**< Mode DEFAULT for LCD_CTRL */ -#define _LCD_CTRL_WARMUPDLY_WARMUP1 0x00000000UL /**< Mode WARMUP1 for LCD_CTRL */ -#define _LCD_CTRL_WARMUPDLY_WARMUP31 0x00000001UL /**< Mode WARMUP31 for LCD_CTRL */ -#define _LCD_CTRL_WARMUPDLY_WARMUP63 0x00000002UL /**< Mode WARMUP63 for LCD_CTRL */ -#define _LCD_CTRL_WARMUPDLY_WARMUP125 0x00000003UL /**< Mode WARMUP125 for LCD_CTRL */ -#define _LCD_CTRL_WARMUPDLY_WARMUP250 0x00000004UL /**< Mode WARMUP250 for LCD_CTRL */ -#define _LCD_CTRL_WARMUPDLY_WARMUP500 0x00000005UL /**< Mode WARMUP500 for LCD_CTRL */ -#define _LCD_CTRL_WARMUPDLY_WARMUP1000 0x00000006UL /**< Mode WARMUP1000 for LCD_CTRL */ -#define _LCD_CTRL_WARMUPDLY_WARMUP2000 0x00000007UL /**< Mode WARMUP2000 for LCD_CTRL */ -#define LCD_CTRL_WARMUPDLY_DEFAULT (_LCD_CTRL_WARMUPDLY_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_CTRL */ -#define LCD_CTRL_WARMUPDLY_WARMUP1 (_LCD_CTRL_WARMUPDLY_WARMUP1 << 18) /**< Shifted mode WARMUP1 for LCD_CTRL */ -#define LCD_CTRL_WARMUPDLY_WARMUP31 (_LCD_CTRL_WARMUPDLY_WARMUP31 << 18) /**< Shifted mode WARMUP31 for LCD_CTRL */ -#define LCD_CTRL_WARMUPDLY_WARMUP63 (_LCD_CTRL_WARMUPDLY_WARMUP63 << 18) /**< Shifted mode WARMUP63 for LCD_CTRL */ -#define LCD_CTRL_WARMUPDLY_WARMUP125 (_LCD_CTRL_WARMUPDLY_WARMUP125 << 18) /**< Shifted mode WARMUP125 for LCD_CTRL */ -#define LCD_CTRL_WARMUPDLY_WARMUP250 (_LCD_CTRL_WARMUPDLY_WARMUP250 << 18) /**< Shifted mode WARMUP250 for LCD_CTRL */ -#define LCD_CTRL_WARMUPDLY_WARMUP500 (_LCD_CTRL_WARMUPDLY_WARMUP500 << 18) /**< Shifted mode WARMUP500 for LCD_CTRL */ -#define LCD_CTRL_WARMUPDLY_WARMUP1000 (_LCD_CTRL_WARMUPDLY_WARMUP1000 << 18) /**< Shifted mode WARMUP1000 for LCD_CTRL */ -#define LCD_CTRL_WARMUPDLY_WARMUP2000 (_LCD_CTRL_WARMUPDLY_WARMUP2000 << 18) /**< Shifted mode WARMUP2000 for LCD_CTRL */ -#define _LCD_CTRL_PRESCALE_SHIFT 24 /**< Shift value for LCD_PRESCALE */ -#define _LCD_CTRL_PRESCALE_MASK 0x7F000000UL /**< Bit mask for LCD_PRESCALE */ -#define _LCD_CTRL_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ -#define LCD_CTRL_PRESCALE_DEFAULT (_LCD_CTRL_PRESCALE_DEFAULT << 24) /**< Shifted mode DEFAULT for LCD_CTRL */ +#define _LCD_CTRL_RESETVALUE 0x00100000UL /**< Default value for LCD_CTRL */ +#define _LCD_CTRL_MASK 0x7F1D0006UL /**< Mask for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */ +#define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */ +#define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000001UL /**< Mode FRAMESTART for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_FCEVENT 0x00000002UL /**< Mode FCEVENT for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_DISPLAYEVENT 0x00000003UL /**< Mode DISPLAYEVENT for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) /**< Shifted mode REGULAR for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) /**< Shifted mode FCEVENT for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_DISPLAYEVENT (_LCD_CTRL_UDCTRL_DISPLAYEVENT << 1) /**< Shifted mode DISPLAYEVENT for LCD_CTRL */ +#define LCD_CTRL_DSC (0x1UL << 16) /**< Direct Segment Control */ +#define _LCD_CTRL_DSC_SHIFT 16 /**< Shift value for LCD_DSC */ +#define _LCD_CTRL_DSC_MASK 0x10000UL /**< Bit mask for LCD_DSC */ +#define _LCD_CTRL_DSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ +#define _LCD_CTRL_DSC_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_CTRL */ +#define _LCD_CTRL_DSC_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_CTRL */ +#define LCD_CTRL_DSC_DEFAULT (_LCD_CTRL_DSC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_DSC_DISABLE (_LCD_CTRL_DSC_DISABLE << 16) /**< Shifted mode DISABLE for LCD_CTRL */ +#define LCD_CTRL_DSC_ENABLE (_LCD_CTRL_DSC_ENABLE << 16) /**< Shifted mode ENABLE for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_SHIFT 18 /**< Shift value for LCD_WARMUPDLY */ +#define _LCD_CTRL_WARMUPDLY_MASK 0x1C0000UL /**< Bit mask for LCD_WARMUPDLY */ +#define _LCD_CTRL_WARMUPDLY_DEFAULT 0x00000004UL /**< Mode DEFAULT for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP1 0x00000000UL /**< Mode WARMUP1 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP31 0x00000001UL /**< Mode WARMUP31 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP63 0x00000002UL /**< Mode WARMUP63 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP125 0x00000003UL /**< Mode WARMUP125 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP250 0x00000004UL /**< Mode WARMUP250 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP500 0x00000005UL /**< Mode WARMUP500 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP1000 0x00000006UL /**< Mode WARMUP1000 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP2000 0x00000007UL /**< Mode WARMUP2000 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_DEFAULT (_LCD_CTRL_WARMUPDLY_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP1 (_LCD_CTRL_WARMUPDLY_WARMUP1 << 18) /**< Shifted mode WARMUP1 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP31 (_LCD_CTRL_WARMUPDLY_WARMUP31 << 18) /**< Shifted mode WARMUP31 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP63 (_LCD_CTRL_WARMUPDLY_WARMUP63 << 18) /**< Shifted mode WARMUP63 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP125 (_LCD_CTRL_WARMUPDLY_WARMUP125 << 18) /**< Shifted mode WARMUP125 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP250 (_LCD_CTRL_WARMUPDLY_WARMUP250 << 18) /**< Shifted mode WARMUP250 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP500 (_LCD_CTRL_WARMUPDLY_WARMUP500 << 18) /**< Shifted mode WARMUP500 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP1000 (_LCD_CTRL_WARMUPDLY_WARMUP1000 << 18) /**< Shifted mode WARMUP1000 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP2000 (_LCD_CTRL_WARMUPDLY_WARMUP2000 << 18) /**< Shifted mode WARMUP2000 for LCD_CTRL */ +#define _LCD_CTRL_PRESCALE_SHIFT 24 /**< Shift value for LCD_PRESCALE */ +#define _LCD_CTRL_PRESCALE_MASK 0x7F000000UL /**< Bit mask for LCD_PRESCALE */ +#define _LCD_CTRL_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_PRESCALE_DEFAULT (_LCD_CTRL_PRESCALE_DEFAULT << 24) /**< Shifted mode DEFAULT for LCD_CTRL */ /* Bit fields for LCD CMD */ -#define _LCD_CMD_RESETVALUE 0x00000000UL /**< Default value for LCD_CMD */ -#define _LCD_CMD_MASK 0x00000003UL /**< Mask for LCD_CMD */ -#define LCD_CMD_LOAD (0x1UL << 0) /**< Load command */ -#define _LCD_CMD_LOAD_SHIFT 0 /**< Shift value for LCD_LOAD */ -#define _LCD_CMD_LOAD_MASK 0x1UL /**< Bit mask for LCD_LOAD */ -#define _LCD_CMD_LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CMD */ -#define LCD_CMD_LOAD_DEFAULT (_LCD_CMD_LOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_CMD */ -#define LCD_CMD_CLEAR (0x1UL << 1) /**< Clear command */ -#define _LCD_CMD_CLEAR_SHIFT 1 /**< Shift value for LCD_CLEAR */ -#define _LCD_CMD_CLEAR_MASK 0x2UL /**< Bit mask for LCD_CLEAR */ -#define _LCD_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CMD */ -#define LCD_CMD_CLEAR_DEFAULT (_LCD_CMD_CLEAR_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CMD */ +#define _LCD_CMD_RESETVALUE 0x00000000UL /**< Default value for LCD_CMD */ +#define _LCD_CMD_MASK 0x00000003UL /**< Mask for LCD_CMD */ +#define LCD_CMD_LOAD (0x1UL << 0) /**< Load command */ +#define _LCD_CMD_LOAD_SHIFT 0 /**< Shift value for LCD_LOAD */ +#define _LCD_CMD_LOAD_MASK 0x1UL /**< Bit mask for LCD_LOAD */ +#define _LCD_CMD_LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CMD */ +#define LCD_CMD_LOAD_DEFAULT (_LCD_CMD_LOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_CMD */ +#define LCD_CMD_CLEAR (0x1UL << 1) /**< Clear command */ +#define _LCD_CMD_CLEAR_SHIFT 1 /**< Shift value for LCD_CLEAR */ +#define _LCD_CMD_CLEAR_MASK 0x2UL /**< Bit mask for LCD_CLEAR */ +#define _LCD_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CMD */ +#define LCD_CMD_CLEAR_DEFAULT (_LCD_CMD_CLEAR_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CMD */ /* Bit fields for LCD DISPCTRL */ -#define _LCD_DISPCTRL_RESETVALUE 0x00100000UL /**< Default value for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_MASK 0x03700017UL /**< Mask for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */ -#define _LCD_DISPCTRL_MUX_MASK 0x7UL /**< Bit mask for LCD_MUX */ -#define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_MUX_SEXTAPLEX 0x00000005UL /**< Mode SEXTAPLEX for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_MUX_OCTAPLEX 0x00000007UL /**< Mode OCTAPLEX for LCD_DISPCTRL */ -#define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ -#define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */ -#define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */ -#define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */ -#define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */ -#define LCD_DISPCTRL_MUX_SEXTAPLEX (_LCD_DISPCTRL_MUX_SEXTAPLEX << 0) /**< Shifted mode SEXTAPLEX for LCD_DISPCTRL */ -#define LCD_DISPCTRL_MUX_OCTAPLEX (_LCD_DISPCTRL_MUX_OCTAPLEX << 0) /**< Shifted mode OCTAPLEX for LCD_DISPCTRL */ -#define LCD_DISPCTRL_WAVE (0x1UL << 4) /**< Waveform Selection */ -#define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */ -#define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */ -#define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_WAVE_TYPEB 0x00000000UL /**< Mode TYPEB for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_WAVE_TYPEA 0x00000001UL /**< Mode TYPEA for LCD_DISPCTRL */ -#define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ -#define LCD_DISPCTRL_WAVE_TYPEB (_LCD_DISPCTRL_WAVE_TYPEB << 4) /**< Shifted mode TYPEB for LCD_DISPCTRL */ -#define LCD_DISPCTRL_WAVE_TYPEA (_LCD_DISPCTRL_WAVE_TYPEA << 4) /**< Shifted mode TYPEA for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_CHGRDST_SHIFT 20 /**< Shift value for LCD_CHGRDST */ -#define _LCD_DISPCTRL_CHGRDST_MASK 0x700000UL /**< Bit mask for LCD_CHGRDST */ -#define _LCD_DISPCTRL_CHGRDST_DEFAULT 0x00000001UL /**< Mode DEFAULT for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_CHGRDST_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_CHGRDST_ONE 0x00000001UL /**< Mode ONE for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_CHGRDST_TWO 0x00000002UL /**< Mode TWO for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_CHGRDST_THREE 0x00000003UL /**< Mode THREE for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_CHGRDST_FOUR 0x00000004UL /**< Mode FOUR for LCD_DISPCTRL */ -#define LCD_DISPCTRL_CHGRDST_DEFAULT (_LCD_DISPCTRL_CHGRDST_DEFAULT << 20) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ -#define LCD_DISPCTRL_CHGRDST_DISABLE (_LCD_DISPCTRL_CHGRDST_DISABLE << 20) /**< Shifted mode DISABLE for LCD_DISPCTRL */ -#define LCD_DISPCTRL_CHGRDST_ONE (_LCD_DISPCTRL_CHGRDST_ONE << 20) /**< Shifted mode ONE for LCD_DISPCTRL */ -#define LCD_DISPCTRL_CHGRDST_TWO (_LCD_DISPCTRL_CHGRDST_TWO << 20) /**< Shifted mode TWO for LCD_DISPCTRL */ -#define LCD_DISPCTRL_CHGRDST_THREE (_LCD_DISPCTRL_CHGRDST_THREE << 20) /**< Shifted mode THREE for LCD_DISPCTRL */ -#define LCD_DISPCTRL_CHGRDST_FOUR (_LCD_DISPCTRL_CHGRDST_FOUR << 20) /**< Shifted mode FOUR for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_BIAS_SHIFT 24 /**< Shift value for LCD_BIAS */ -#define _LCD_DISPCTRL_BIAS_MASK 0x3000000UL /**< Bit mask for LCD_BIAS */ -#define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */ -#define _LCD_DISPCTRL_BIAS_ONEFOURTH 0x00000003UL /**< Mode ONEFOURTH for LCD_DISPCTRL */ -#define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 24) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ -#define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 24) /**< Shifted mode STATIC for LCD_DISPCTRL */ -#define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 24) /**< Shifted mode ONEHALF for LCD_DISPCTRL */ -#define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 24) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */ -#define LCD_DISPCTRL_BIAS_ONEFOURTH (_LCD_DISPCTRL_BIAS_ONEFOURTH << 24) /**< Shifted mode ONEFOURTH for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_RESETVALUE 0x00100000UL /**< Default value for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MASK 0x03700017UL /**< Mask for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */ +#define _LCD_DISPCTRL_MUX_MASK 0x7UL /**< Bit mask for LCD_MUX */ +#define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_SEXTAPLEX 0x00000005UL /**< Mode SEXTAPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_OCTAPLEX 0x00000007UL /**< Mode OCTAPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_SEXTAPLEX (_LCD_DISPCTRL_MUX_SEXTAPLEX << 0) /**< Shifted mode SEXTAPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_OCTAPLEX (_LCD_DISPCTRL_MUX_OCTAPLEX << 0) /**< Shifted mode OCTAPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE (0x1UL << 4) /**< Waveform Selection */ +#define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */ +#define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */ +#define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_WAVE_TYPEB 0x00000000UL /**< Mode TYPEB for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_WAVE_TYPEA 0x00000001UL /**< Mode TYPEA for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE_TYPEB (_LCD_DISPCTRL_WAVE_TYPEB << 4) /**< Shifted mode TYPEB for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE_TYPEA (_LCD_DISPCTRL_WAVE_TYPEA << 4) /**< Shifted mode TYPEA for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_SHIFT 20 /**< Shift value for LCD_CHGRDST */ +#define _LCD_DISPCTRL_CHGRDST_MASK 0x700000UL /**< Bit mask for LCD_CHGRDST */ +#define _LCD_DISPCTRL_CHGRDST_DEFAULT 0x00000001UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_ONE 0x00000001UL /**< Mode ONE for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_TWO 0x00000002UL /**< Mode TWO for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_THREE 0x00000003UL /**< Mode THREE for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_FOUR 0x00000004UL /**< Mode FOUR for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_DEFAULT (_LCD_DISPCTRL_CHGRDST_DEFAULT << 20) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_DISABLE (_LCD_DISPCTRL_CHGRDST_DISABLE << 20) /**< Shifted mode DISABLE for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_ONE (_LCD_DISPCTRL_CHGRDST_ONE << 20) /**< Shifted mode ONE for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_TWO (_LCD_DISPCTRL_CHGRDST_TWO << 20) /**< Shifted mode TWO for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_THREE (_LCD_DISPCTRL_CHGRDST_THREE << 20) /**< Shifted mode THREE for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_FOUR (_LCD_DISPCTRL_CHGRDST_FOUR << 20) /**< Shifted mode FOUR for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_SHIFT 24 /**< Shift value for LCD_BIAS */ +#define _LCD_DISPCTRL_BIAS_MASK 0x3000000UL /**< Bit mask for LCD_BIAS */ +#define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_ONEFOURTH 0x00000003UL /**< Mode ONEFOURTH for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 24) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 24) /**< Shifted mode STATIC for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 24) /**< Shifted mode ONEHALF for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 24) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_ONEFOURTH (_LCD_DISPCTRL_BIAS_ONEFOURTH << 24) /**< Shifted mode ONEFOURTH for LCD_DISPCTRL */ /* Bit fields for LCD BACFG */ -#define _LCD_BACFG_RESETVALUE 0x00000007UL /**< Default value for LCD_BACFG */ -#define _LCD_BACFG_MASK 0x00FF0007UL /**< Mask for LCD_BACFG */ -#define _LCD_BACFG_ASTATETOP_SHIFT 0 /**< Shift value for LCD_ASTATETOP */ -#define _LCD_BACFG_ASTATETOP_MASK 0x7UL /**< Bit mask for LCD_ASTATETOP */ -#define _LCD_BACFG_ASTATETOP_DEFAULT 0x00000007UL /**< Mode DEFAULT for LCD_BACFG */ -#define LCD_BACFG_ASTATETOP_DEFAULT (_LCD_BACFG_ASTATETOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACFG */ -#define _LCD_BACFG_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */ -#define _LCD_BACFG_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */ -#define _LCD_BACFG_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACFG */ -#define _LCD_BACFG_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACFG */ -#define _LCD_BACFG_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACFG */ -#define _LCD_BACFG_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACFG */ -#define _LCD_BACFG_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACFG */ -#define LCD_BACFG_FCPRESC_DEFAULT (_LCD_BACFG_FCPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BACFG */ -#define LCD_BACFG_FCPRESC_DIV1 (_LCD_BACFG_FCPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LCD_BACFG */ -#define LCD_BACFG_FCPRESC_DIV2 (_LCD_BACFG_FCPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LCD_BACFG */ -#define LCD_BACFG_FCPRESC_DIV4 (_LCD_BACFG_FCPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LCD_BACFG */ -#define LCD_BACFG_FCPRESC_DIV8 (_LCD_BACFG_FCPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LCD_BACFG */ -#define _LCD_BACFG_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */ -#define _LCD_BACFG_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */ -#define _LCD_BACFG_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACFG */ -#define LCD_BACFG_FCTOP_DEFAULT (_LCD_BACFG_FCTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_BACFG */ +#define _LCD_BACFG_RESETVALUE 0x00000007UL /**< Default value for LCD_BACFG */ +#define _LCD_BACFG_MASK 0x00FF0007UL /**< Mask for LCD_BACFG */ +#define _LCD_BACFG_ASTATETOP_SHIFT 0 /**< Shift value for LCD_ASTATETOP */ +#define _LCD_BACFG_ASTATETOP_MASK 0x7UL /**< Bit mask for LCD_ASTATETOP */ +#define _LCD_BACFG_ASTATETOP_DEFAULT 0x00000007UL /**< Mode DEFAULT for LCD_BACFG */ +#define LCD_BACFG_ASTATETOP_DEFAULT (_LCD_BACFG_ASTATETOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACFG */ +#define _LCD_BACFG_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */ +#define _LCD_BACFG_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */ +#define _LCD_BACFG_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACFG */ +#define _LCD_BACFG_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACFG */ +#define _LCD_BACFG_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACFG */ +#define _LCD_BACFG_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACFG */ +#define _LCD_BACFG_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACFG */ +#define LCD_BACFG_FCPRESC_DEFAULT (_LCD_BACFG_FCPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BACFG */ +#define LCD_BACFG_FCPRESC_DIV1 (_LCD_BACFG_FCPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LCD_BACFG */ +#define LCD_BACFG_FCPRESC_DIV2 (_LCD_BACFG_FCPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LCD_BACFG */ +#define LCD_BACFG_FCPRESC_DIV4 (_LCD_BACFG_FCPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LCD_BACFG */ +#define LCD_BACFG_FCPRESC_DIV8 (_LCD_BACFG_FCPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LCD_BACFG */ +#define _LCD_BACFG_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */ +#define _LCD_BACFG_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */ +#define _LCD_BACFG_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACFG */ +#define LCD_BACFG_FCTOP_DEFAULT (_LCD_BACFG_FCTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_BACFG */ /* Bit fields for LCD BACTRL */ -#define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */ -#define _LCD_BACTRL_MASK 0x100003FFUL /**< Mask for LCD_BACTRL */ -#define LCD_BACTRL_BLINKEN (0x1UL << 0) /**< Blink Enable */ -#define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */ -#define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */ -#define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ -#define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */ -#define LCD_BACTRL_BLANK (0x1UL << 1) /**< Blank Display */ -#define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */ -#define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */ -#define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ -#define _LCD_BACTRL_BLANK_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_BACTRL */ -#define _LCD_BACTRL_BLANK_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_BACTRL */ -#define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */ -#define LCD_BACTRL_BLANK_DISABLE (_LCD_BACTRL_BLANK_DISABLE << 1) /**< Shifted mode DISABLE for LCD_BACTRL */ -#define LCD_BACTRL_BLANK_ENABLE (_LCD_BACTRL_BLANK_ENABLE << 1) /**< Shifted mode ENABLE for LCD_BACTRL */ -#define LCD_BACTRL_AEN (0x1UL << 2) /**< Animation Enable */ -#define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */ -#define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */ -#define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ -#define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */ -#define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */ -#define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */ -#define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ -#define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ -#define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ -#define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ -#define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */ -#define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */ -#define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ -#define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ -#define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */ -#define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */ -#define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ -#define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ -#define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ -#define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ -#define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */ -#define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */ -#define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ -#define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ -#define LCD_BACTRL_ALOGSEL (0x1UL << 7) /**< Animate Logic Function Select */ -#define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */ -#define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */ -#define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ -#define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */ -#define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */ -#define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */ -#define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) /**< Shifted mode AND for LCD_BACTRL */ -#define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) /**< Shifted mode OR for LCD_BACTRL */ -#define LCD_BACTRL_FCEN (0x1UL << 8) /**< Frame Counter Enable */ -#define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */ -#define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */ -#define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ -#define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */ -#define LCD_BACTRL_DISPLAYCNTEN (0x1UL << 9) /**< Display Counter Enable */ -#define _LCD_BACTRL_DISPLAYCNTEN_SHIFT 9 /**< Shift value for LCD_DISPLAYCNTEN */ -#define _LCD_BACTRL_DISPLAYCNTEN_MASK 0x200UL /**< Bit mask for LCD_DISPLAYCNTEN */ -#define _LCD_BACTRL_DISPLAYCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ -#define _LCD_BACTRL_DISPLAYCNTEN_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_BACTRL */ -#define _LCD_BACTRL_DISPLAYCNTEN_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_BACTRL */ -#define LCD_BACTRL_DISPLAYCNTEN_DEFAULT (_LCD_BACTRL_DISPLAYCNTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LCD_BACTRL */ -#define LCD_BACTRL_DISPLAYCNTEN_DISABLE (_LCD_BACTRL_DISPLAYCNTEN_DISABLE << 9) /**< Shifted mode DISABLE for LCD_BACTRL */ -#define LCD_BACTRL_DISPLAYCNTEN_ENABLE (_LCD_BACTRL_DISPLAYCNTEN_ENABLE << 9) /**< Shifted mode ENABLE for LCD_BACTRL */ -#define LCD_BACTRL_ALOC (0x1UL << 28) /**< Animation Location */ -#define _LCD_BACTRL_ALOC_SHIFT 28 /**< Shift value for LCD_ALOC */ -#define _LCD_BACTRL_ALOC_MASK 0x10000000UL /**< Bit mask for LCD_ALOC */ -#define _LCD_BACTRL_ALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ -#define _LCD_BACTRL_ALOC_SEG0TO7 0x00000000UL /**< Mode SEG0TO7 for LCD_BACTRL */ -#define _LCD_BACTRL_ALOC_SEG8TO15 0x00000001UL /**< Mode SEG8TO15 for LCD_BACTRL */ -#define LCD_BACTRL_ALOC_DEFAULT (_LCD_BACTRL_ALOC_DEFAULT << 28) /**< Shifted mode DEFAULT for LCD_BACTRL */ -#define LCD_BACTRL_ALOC_SEG0TO7 (_LCD_BACTRL_ALOC_SEG0TO7 << 28) /**< Shifted mode SEG0TO7 for LCD_BACTRL */ -#define LCD_BACTRL_ALOC_SEG8TO15 (_LCD_BACTRL_ALOC_SEG8TO15 << 28) /**< Shifted mode SEG8TO15 for LCD_BACTRL */ +#define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */ +#define _LCD_BACTRL_MASK 0x100003FFUL /**< Mask for LCD_BACTRL */ +#define LCD_BACTRL_BLINKEN (0x1UL << 0) /**< Blink Enable */ +#define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */ +#define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */ +#define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_BLANK (0x1UL << 1) /**< Blank Display */ +#define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */ +#define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */ +#define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_BLANK_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_BACTRL */ +#define _LCD_BACTRL_BLANK_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_BACTRL */ +#define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_BLANK_DISABLE (_LCD_BACTRL_BLANK_DISABLE << 1) /**< Shifted mode DISABLE for LCD_BACTRL */ +#define LCD_BACTRL_BLANK_ENABLE (_LCD_BACTRL_BLANK_ENABLE << 1) /**< Shifted mode ENABLE for LCD_BACTRL */ +#define LCD_BACTRL_AEN (0x1UL << 2) /**< Animation Enable */ +#define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */ +#define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */ +#define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */ +#define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */ +#define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */ +#define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */ +#define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL (0x1UL << 7) /**< Animate Logic Function Select */ +#define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */ +#define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */ +#define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */ +#define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) /**< Shifted mode AND for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) /**< Shifted mode OR for LCD_BACTRL */ +#define LCD_BACTRL_FCEN (0x1UL << 8) /**< Frame Counter Enable */ +#define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */ +#define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */ +#define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_DISPLAYCNTEN (0x1UL << 9) /**< Display Counter Enable */ +#define _LCD_BACTRL_DISPLAYCNTEN_SHIFT 9 /**< Shift value for LCD_DISPLAYCNTEN */ +#define _LCD_BACTRL_DISPLAYCNTEN_MASK 0x200UL /**< Bit mask for LCD_DISPLAYCNTEN */ +#define _LCD_BACTRL_DISPLAYCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_DISPLAYCNTEN_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_BACTRL */ +#define _LCD_BACTRL_DISPLAYCNTEN_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_BACTRL */ +#define LCD_BACTRL_DISPLAYCNTEN_DEFAULT (_LCD_BACTRL_DISPLAYCNTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_DISPLAYCNTEN_DISABLE (_LCD_BACTRL_DISPLAYCNTEN_DISABLE << 9) /**< Shifted mode DISABLE for LCD_BACTRL */ +#define LCD_BACTRL_DISPLAYCNTEN_ENABLE (_LCD_BACTRL_DISPLAYCNTEN_ENABLE << 9) /**< Shifted mode ENABLE for LCD_BACTRL */ +#define LCD_BACTRL_ALOC (0x1UL << 28) /**< Animation Location */ +#define _LCD_BACTRL_ALOC_SHIFT 28 /**< Shift value for LCD_ALOC */ +#define _LCD_BACTRL_ALOC_MASK 0x10000000UL /**< Bit mask for LCD_ALOC */ +#define _LCD_BACTRL_ALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_ALOC_SEG0TO7 0x00000000UL /**< Mode SEG0TO7 for LCD_BACTRL */ +#define _LCD_BACTRL_ALOC_SEG8TO15 0x00000001UL /**< Mode SEG8TO15 for LCD_BACTRL */ +#define LCD_BACTRL_ALOC_DEFAULT (_LCD_BACTRL_ALOC_DEFAULT << 28) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_ALOC_SEG0TO7 (_LCD_BACTRL_ALOC_SEG0TO7 << 28) /**< Shifted mode SEG0TO7 for LCD_BACTRL */ +#define LCD_BACTRL_ALOC_SEG8TO15 (_LCD_BACTRL_ALOC_SEG8TO15 << 28) /**< Shifted mode SEG8TO15 for LCD_BACTRL */ /* Bit fields for LCD STATUS */ -#define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */ -#define _LCD_STATUS_MASK 0x0000090FUL /**< Mask for LCD_STATUS */ -#define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */ -#define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */ -#define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ -#define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_STATUS */ -#define LCD_STATUS_BLINK (0x1UL << 8) /**< Blink State */ -#define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */ -#define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */ -#define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ -#define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_STATUS */ -#define LCD_STATUS_LOADBUSY (0x1UL << 11) /**< Load Synchronization is busy */ -#define _LCD_STATUS_LOADBUSY_SHIFT 11 /**< Shift value for LCD_LOADBUSY */ -#define _LCD_STATUS_LOADBUSY_MASK 0x800UL /**< Bit mask for LCD_LOADBUSY */ -#define _LCD_STATUS_LOADBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ -#define LCD_STATUS_LOADBUSY_DEFAULT (_LCD_STATUS_LOADBUSY_DEFAULT << 11) /**< Shifted mode DEFAULT for LCD_STATUS */ +#define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */ +#define _LCD_STATUS_MASK 0x0000090FUL /**< Mask for LCD_STATUS */ +#define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */ +#define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */ +#define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_BLINK (0x1UL << 8) /**< Blink State */ +#define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */ +#define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */ +#define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_LOADBUSY (0x1UL << 11) /**< Load Synchronization is busy */ +#define _LCD_STATUS_LOADBUSY_SHIFT 11 /**< Shift value for LCD_LOADBUSY */ +#define _LCD_STATUS_LOADBUSY_MASK 0x800UL /**< Bit mask for LCD_LOADBUSY */ +#define _LCD_STATUS_LOADBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_LOADBUSY_DEFAULT (_LCD_STATUS_LOADBUSY_DEFAULT << 11) /**< Shifted mode DEFAULT for LCD_STATUS */ /* Bit fields for LCD AREGA */ -#define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */ -#define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */ -#define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */ -#define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */ -#define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */ -#define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGA */ +#define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */ +#define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */ +#define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */ +#define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */ +#define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */ +#define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGA */ /* Bit fields for LCD AREGB */ -#define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */ -#define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */ -#define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */ -#define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */ -#define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */ -#define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGB */ +#define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */ +#define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */ +#define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */ +#define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */ +#define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */ +#define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGB */ /* Bit fields for LCD IF */ -#define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */ -#define _LCD_IF_MASK 0x00000007UL /**< Mask for LCD_IF */ -#define LCD_IF_FC (0x1UL << 0) /**< Frame Counter */ -#define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */ -#define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ -#define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */ -#define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IF */ -#define LCD_IF_DISPLAY (0x1UL << 1) /**< Display Update Event */ -#define _LCD_IF_DISPLAY_SHIFT 1 /**< Shift value for LCD_DISPLAY */ -#define _LCD_IF_DISPLAY_MASK 0x2UL /**< Bit mask for LCD_DISPLAY */ -#define _LCD_IF_DISPLAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */ -#define LCD_IF_DISPLAY_DEFAULT (_LCD_IF_DISPLAY_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_IF */ -#define LCD_IF_SYNCBUSYDONE (0x1UL << 2) /**< Synchronization is Done */ -#define _LCD_IF_SYNCBUSYDONE_SHIFT 2 /**< Shift value for LCD_SYNCBUSYDONE */ -#define _LCD_IF_SYNCBUSYDONE_MASK 0x4UL /**< Bit mask for LCD_SYNCBUSYDONE */ -#define _LCD_IF_SYNCBUSYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */ -#define LCD_IF_SYNCBUSYDONE_DEFAULT (_LCD_IF_SYNCBUSYDONE_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_IF */ +#define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */ +#define _LCD_IF_MASK 0x00000007UL /**< Mask for LCD_IF */ +#define LCD_IF_FC (0x1UL << 0) /**< Frame Counter */ +#define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */ +#define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ +#define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */ +#define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IF */ +#define LCD_IF_DISPLAY (0x1UL << 1) /**< Display Update Event */ +#define _LCD_IF_DISPLAY_SHIFT 1 /**< Shift value for LCD_DISPLAY */ +#define _LCD_IF_DISPLAY_MASK 0x2UL /**< Bit mask for LCD_DISPLAY */ +#define _LCD_IF_DISPLAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */ +#define LCD_IF_DISPLAY_DEFAULT (_LCD_IF_DISPLAY_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_IF */ +#define LCD_IF_SYNCBUSYDONE (0x1UL << 2) /**< Synchronization is Done */ +#define _LCD_IF_SYNCBUSYDONE_SHIFT 2 /**< Shift value for LCD_SYNCBUSYDONE */ +#define _LCD_IF_SYNCBUSYDONE_MASK 0x4UL /**< Bit mask for LCD_SYNCBUSYDONE */ +#define _LCD_IF_SYNCBUSYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */ +#define LCD_IF_SYNCBUSYDONE_DEFAULT (_LCD_IF_SYNCBUSYDONE_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_IF */ /* Bit fields for LCD IEN */ -#define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */ -#define _LCD_IEN_MASK 0x00000007UL /**< Mask for LCD_IEN */ -#define LCD_IEN_FC (0x1UL << 0) /**< Frame Counter */ -#define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */ -#define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ -#define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */ -#define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IEN */ -#define LCD_IEN_DISPLAY (0x1UL << 1) /**< Display Update Event */ -#define _LCD_IEN_DISPLAY_SHIFT 1 /**< Shift value for LCD_DISPLAY */ -#define _LCD_IEN_DISPLAY_MASK 0x2UL /**< Bit mask for LCD_DISPLAY */ -#define _LCD_IEN_DISPLAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */ -#define LCD_IEN_DISPLAY_DEFAULT (_LCD_IEN_DISPLAY_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_IEN */ -#define LCD_IEN_SYNCBUSYDONE (0x1UL << 2) /**< Sync Busy Done */ -#define _LCD_IEN_SYNCBUSYDONE_SHIFT 2 /**< Shift value for LCD_SYNCBUSYDONE */ -#define _LCD_IEN_SYNCBUSYDONE_MASK 0x4UL /**< Bit mask for LCD_SYNCBUSYDONE */ -#define _LCD_IEN_SYNCBUSYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */ -#define LCD_IEN_SYNCBUSYDONE_DEFAULT (_LCD_IEN_SYNCBUSYDONE_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_IEN */ +#define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */ +#define _LCD_IEN_MASK 0x00000007UL /**< Mask for LCD_IEN */ +#define LCD_IEN_FC (0x1UL << 0) /**< Frame Counter */ +#define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */ +#define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ +#define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */ +#define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IEN */ +#define LCD_IEN_DISPLAY (0x1UL << 1) /**< Display Update Event */ +#define _LCD_IEN_DISPLAY_SHIFT 1 /**< Shift value for LCD_DISPLAY */ +#define _LCD_IEN_DISPLAY_MASK 0x2UL /**< Bit mask for LCD_DISPLAY */ +#define _LCD_IEN_DISPLAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */ +#define LCD_IEN_DISPLAY_DEFAULT (_LCD_IEN_DISPLAY_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_IEN */ +#define LCD_IEN_SYNCBUSYDONE (0x1UL << 2) /**< Sync Busy Done */ +#define _LCD_IEN_SYNCBUSYDONE_SHIFT 2 /**< Shift value for LCD_SYNCBUSYDONE */ +#define _LCD_IEN_SYNCBUSYDONE_MASK 0x4UL /**< Bit mask for LCD_SYNCBUSYDONE */ +#define _LCD_IEN_SYNCBUSYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */ +#define LCD_IEN_SYNCBUSYDONE_DEFAULT (_LCD_IEN_SYNCBUSYDONE_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_IEN */ /* Bit fields for LCD BIASCTRL */ -#define _LCD_BIASCTRL_RESETVALUE 0x001F0000UL /**< Default value for LCD_BIASCTRL */ -#define _LCD_BIASCTRL_MASK 0xC45F137FUL /**< Mask for LCD_BIASCTRL */ -#define _LCD_BIASCTRL_RESISTOR_SHIFT 0 /**< Shift value for LCD_RESISTOR */ -#define _LCD_BIASCTRL_RESISTOR_MASK 0xFUL /**< Bit mask for LCD_RESISTOR */ -#define _LCD_BIASCTRL_RESISTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ -#define LCD_BIASCTRL_RESISTOR_DEFAULT (_LCD_BIASCTRL_RESISTOR_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ -#define _LCD_BIASCTRL_BUFDRV_SHIFT 4 /**< Shift value for LCD_BUFDRV */ -#define _LCD_BIASCTRL_BUFDRV_MASK 0x70UL /**< Bit mask for LCD_BUFDRV */ -#define _LCD_BIASCTRL_BUFDRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ -#define LCD_BIASCTRL_BUFDRV_DEFAULT (_LCD_BIASCTRL_BUFDRV_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ -#define _LCD_BIASCTRL_BUFBIAS_SHIFT 8 /**< Shift value for LCD_BUFBIAS */ -#define _LCD_BIASCTRL_BUFBIAS_MASK 0x300UL /**< Bit mask for LCD_BUFBIAS */ -#define _LCD_BIASCTRL_BUFBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ -#define LCD_BIASCTRL_BUFBIAS_DEFAULT (_LCD_BIASCTRL_BUFBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ -#define LCD_BIASCTRL_MODE (0x1UL << 12) /**< Mode Setting */ -#define _LCD_BIASCTRL_MODE_SHIFT 12 /**< Shift value for LCD_MODE */ -#define _LCD_BIASCTRL_MODE_MASK 0x1000UL /**< Bit mask for LCD_MODE */ -#define _LCD_BIASCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ -#define _LCD_BIASCTRL_MODE_STEPDOWN 0x00000000UL /**< Mode STEPDOWN for LCD_BIASCTRL */ -#define _LCD_BIASCTRL_MODE_CHARGEPUMP 0x00000001UL /**< Mode CHARGEPUMP for LCD_BIASCTRL */ -#define LCD_BIASCTRL_MODE_DEFAULT (_LCD_BIASCTRL_MODE_DEFAULT << 12) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ -#define LCD_BIASCTRL_MODE_STEPDOWN (_LCD_BIASCTRL_MODE_STEPDOWN << 12) /**< Shifted mode STEPDOWN for LCD_BIASCTRL */ -#define LCD_BIASCTRL_MODE_CHARGEPUMP (_LCD_BIASCTRL_MODE_CHARGEPUMP << 12) /**< Shifted mode CHARGEPUMP for LCD_BIASCTRL */ -#define _LCD_BIASCTRL_VLCD_SHIFT 16 /**< Shift value for LCD_VLCD */ -#define _LCD_BIASCTRL_VLCD_MASK 0x1F0000UL /**< Bit mask for LCD_VLCD */ -#define _LCD_BIASCTRL_VLCD_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LCD_BIASCTRL */ -#define LCD_BIASCTRL_VLCD_DEFAULT (_LCD_BIASCTRL_VLCD_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ -#define LCD_BIASCTRL_VDDXSEL (0x1UL << 22) /**< VDDX select */ -#define _LCD_BIASCTRL_VDDXSEL_SHIFT 22 /**< Shift value for LCD_VDDXSEL */ -#define _LCD_BIASCTRL_VDDXSEL_MASK 0x400000UL /**< Bit mask for LCD_VDDXSEL */ -#define _LCD_BIASCTRL_VDDXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ -#define _LCD_BIASCTRL_VDDXSEL_DVDD 0x00000000UL /**< Mode DVDD for LCD_BIASCTRL */ -#define _LCD_BIASCTRL_VDDXSEL_AVDD 0x00000001UL /**< Mode AVDD for LCD_BIASCTRL */ -#define LCD_BIASCTRL_VDDXSEL_DEFAULT (_LCD_BIASCTRL_VDDXSEL_DEFAULT << 22) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ -#define LCD_BIASCTRL_VDDXSEL_DVDD (_LCD_BIASCTRL_VDDXSEL_DVDD << 22) /**< Shifted mode DVDD for LCD_BIASCTRL */ -#define LCD_BIASCTRL_VDDXSEL_AVDD (_LCD_BIASCTRL_VDDXSEL_AVDD << 22) /**< Shifted mode AVDD for LCD_BIASCTRL */ -#define LCD_BIASCTRL_LCDGATE (0x1UL << 26) /**< LCD Gate */ -#define _LCD_BIASCTRL_LCDGATE_SHIFT 26 /**< Shift value for LCD_LCDGATE */ -#define _LCD_BIASCTRL_LCDGATE_MASK 0x4000000UL /**< Bit mask for LCD_LCDGATE */ -#define _LCD_BIASCTRL_LCDGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ -#define _LCD_BIASCTRL_LCDGATE_UNGATE 0x00000000UL /**< Mode UNGATE for LCD_BIASCTRL */ -#define _LCD_BIASCTRL_LCDGATE_GATE 0x00000001UL /**< Mode GATE for LCD_BIASCTRL */ -#define LCD_BIASCTRL_LCDGATE_DEFAULT (_LCD_BIASCTRL_LCDGATE_DEFAULT << 26) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ -#define LCD_BIASCTRL_LCDGATE_UNGATE (_LCD_BIASCTRL_LCDGATE_UNGATE << 26) /**< Shifted mode UNGATE for LCD_BIASCTRL */ -#define LCD_BIASCTRL_LCDGATE_GATE (_LCD_BIASCTRL_LCDGATE_GATE << 26) /**< Shifted mode GATE for LCD_BIASCTRL */ -#define _LCD_BIASCTRL_DMAMODE_SHIFT 30 /**< Shift value for LCD_DMAMODE */ -#define _LCD_BIASCTRL_DMAMODE_MASK 0xC0000000UL /**< Bit mask for LCD_DMAMODE */ -#define _LCD_BIASCTRL_DMAMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ -#define _LCD_BIASCTRL_DMAMODE_DMADISABLE 0x00000000UL /**< Mode DMADISABLE for LCD_BIASCTRL */ -#define _LCD_BIASCTRL_DMAMODE_DMAFC 0x00000001UL /**< Mode DMAFC for LCD_BIASCTRL */ -#define _LCD_BIASCTRL_DMAMODE_DMADISPLAY 0x00000002UL /**< Mode DMADISPLAY for LCD_BIASCTRL */ -#define LCD_BIASCTRL_DMAMODE_DEFAULT (_LCD_BIASCTRL_DMAMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ -#define LCD_BIASCTRL_DMAMODE_DMADISABLE (_LCD_BIASCTRL_DMAMODE_DMADISABLE << 30) /**< Shifted mode DMADISABLE for LCD_BIASCTRL */ -#define LCD_BIASCTRL_DMAMODE_DMAFC (_LCD_BIASCTRL_DMAMODE_DMAFC << 30) /**< Shifted mode DMAFC for LCD_BIASCTRL */ -#define LCD_BIASCTRL_DMAMODE_DMADISPLAY (_LCD_BIASCTRL_DMAMODE_DMADISPLAY << 30) /**< Shifted mode DMADISPLAY for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_RESETVALUE 0x001F0000UL /**< Default value for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_MASK 0xC45F137FUL /**< Mask for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_RESISTOR_SHIFT 0 /**< Shift value for LCD_RESISTOR */ +#define _LCD_BIASCTRL_RESISTOR_MASK 0xFUL /**< Bit mask for LCD_RESISTOR */ +#define _LCD_BIASCTRL_RESISTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_RESISTOR_DEFAULT (_LCD_BIASCTRL_RESISTOR_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_BUFDRV_SHIFT 4 /**< Shift value for LCD_BUFDRV */ +#define _LCD_BIASCTRL_BUFDRV_MASK 0x70UL /**< Bit mask for LCD_BUFDRV */ +#define _LCD_BIASCTRL_BUFDRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_BUFDRV_DEFAULT (_LCD_BIASCTRL_BUFDRV_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_BUFBIAS_SHIFT 8 /**< Shift value for LCD_BUFBIAS */ +#define _LCD_BIASCTRL_BUFBIAS_MASK 0x300UL /**< Bit mask for LCD_BUFBIAS */ +#define _LCD_BIASCTRL_BUFBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_BUFBIAS_DEFAULT (_LCD_BIASCTRL_BUFBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_MODE (0x1UL << 12) /**< Mode Setting */ +#define _LCD_BIASCTRL_MODE_SHIFT 12 /**< Shift value for LCD_MODE */ +#define _LCD_BIASCTRL_MODE_MASK 0x1000UL /**< Bit mask for LCD_MODE */ +#define _LCD_BIASCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_MODE_STEPDOWN 0x00000000UL /**< Mode STEPDOWN for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_MODE_CHARGEPUMP 0x00000001UL /**< Mode CHARGEPUMP for LCD_BIASCTRL */ +#define LCD_BIASCTRL_MODE_DEFAULT (_LCD_BIASCTRL_MODE_DEFAULT << 12) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_MODE_STEPDOWN (_LCD_BIASCTRL_MODE_STEPDOWN << 12) /**< Shifted mode STEPDOWN for LCD_BIASCTRL */ +#define LCD_BIASCTRL_MODE_CHARGEPUMP (_LCD_BIASCTRL_MODE_CHARGEPUMP << 12) /**< Shifted mode CHARGEPUMP for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_VLCD_SHIFT 16 /**< Shift value for LCD_VLCD */ +#define _LCD_BIASCTRL_VLCD_MASK 0x1F0000UL /**< Bit mask for LCD_VLCD */ +#define _LCD_BIASCTRL_VLCD_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_VLCD_DEFAULT (_LCD_BIASCTRL_VLCD_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_VDDXSEL (0x1UL << 22) /**< VDDX select */ +#define _LCD_BIASCTRL_VDDXSEL_SHIFT 22 /**< Shift value for LCD_VDDXSEL */ +#define _LCD_BIASCTRL_VDDXSEL_MASK 0x400000UL /**< Bit mask for LCD_VDDXSEL */ +#define _LCD_BIASCTRL_VDDXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_VDDXSEL_DVDD 0x00000000UL /**< Mode DVDD for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_VDDXSEL_AVDD 0x00000001UL /**< Mode AVDD for LCD_BIASCTRL */ +#define LCD_BIASCTRL_VDDXSEL_DEFAULT (_LCD_BIASCTRL_VDDXSEL_DEFAULT << 22) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_VDDXSEL_DVDD (_LCD_BIASCTRL_VDDXSEL_DVDD << 22) /**< Shifted mode DVDD for LCD_BIASCTRL */ +#define LCD_BIASCTRL_VDDXSEL_AVDD (_LCD_BIASCTRL_VDDXSEL_AVDD << 22) /**< Shifted mode AVDD for LCD_BIASCTRL */ +#define LCD_BIASCTRL_LCDGATE (0x1UL << 26) /**< LCD Gate */ +#define _LCD_BIASCTRL_LCDGATE_SHIFT 26 /**< Shift value for LCD_LCDGATE */ +#define _LCD_BIASCTRL_LCDGATE_MASK 0x4000000UL /**< Bit mask for LCD_LCDGATE */ +#define _LCD_BIASCTRL_LCDGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_LCDGATE_UNGATE 0x00000000UL /**< Mode UNGATE for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_LCDGATE_GATE 0x00000001UL /**< Mode GATE for LCD_BIASCTRL */ +#define LCD_BIASCTRL_LCDGATE_DEFAULT (_LCD_BIASCTRL_LCDGATE_DEFAULT << 26) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_LCDGATE_UNGATE (_LCD_BIASCTRL_LCDGATE_UNGATE << 26) /**< Shifted mode UNGATE for LCD_BIASCTRL */ +#define LCD_BIASCTRL_LCDGATE_GATE (_LCD_BIASCTRL_LCDGATE_GATE << 26) /**< Shifted mode GATE for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_DMAMODE_SHIFT 30 /**< Shift value for LCD_DMAMODE */ +#define _LCD_BIASCTRL_DMAMODE_MASK 0xC0000000UL /**< Bit mask for LCD_DMAMODE */ +#define _LCD_BIASCTRL_DMAMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_DMAMODE_DMADISABLE 0x00000000UL /**< Mode DMADISABLE for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_DMAMODE_DMAFC 0x00000001UL /**< Mode DMAFC for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_DMAMODE_DMADISPLAY 0x00000002UL /**< Mode DMADISPLAY for LCD_BIASCTRL */ +#define LCD_BIASCTRL_DMAMODE_DEFAULT (_LCD_BIASCTRL_DMAMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_DMAMODE_DMADISABLE (_LCD_BIASCTRL_DMAMODE_DMADISABLE << 30) /**< Shifted mode DMADISABLE for LCD_BIASCTRL */ +#define LCD_BIASCTRL_DMAMODE_DMAFC (_LCD_BIASCTRL_DMAMODE_DMAFC << 30) /**< Shifted mode DMAFC for LCD_BIASCTRL */ +#define LCD_BIASCTRL_DMAMODE_DMADISPLAY (_LCD_BIASCTRL_DMAMODE_DMADISPLAY << 30) /**< Shifted mode DMADISPLAY for LCD_BIASCTRL */ /* Bit fields for LCD DISPCTRLX */ -#define _LCD_DISPCTRLX_RESETVALUE 0x00000000UL /**< Default value for LCD_DISPCTRLX */ -#define _LCD_DISPCTRLX_MASK 0x000003FFUL /**< Mask for LCD_DISPCTRLX */ -#define _LCD_DISPCTRLX_DISPLAYDIV_SHIFT 0 /**< Shift value for LCD_DISPLAYDIV */ -#define _LCD_DISPCTRLX_DISPLAYDIV_MASK 0x3FFUL /**< Bit mask for LCD_DISPLAYDIV */ -#define _LCD_DISPCTRLX_DISPLAYDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRLX */ -#define LCD_DISPCTRLX_DISPLAYDIV_DEFAULT (_LCD_DISPCTRLX_DISPLAYDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRLX */ +#define _LCD_DISPCTRLX_RESETVALUE 0x00000000UL /**< Default value for LCD_DISPCTRLX */ +#define _LCD_DISPCTRLX_MASK 0x000003FFUL /**< Mask for LCD_DISPCTRLX */ +#define _LCD_DISPCTRLX_DISPLAYDIV_SHIFT 0 /**< Shift value for LCD_DISPLAYDIV */ +#define _LCD_DISPCTRLX_DISPLAYDIV_MASK 0x3FFUL /**< Bit mask for LCD_DISPLAYDIV */ +#define _LCD_DISPCTRLX_DISPLAYDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRLX */ +#define LCD_DISPCTRLX_DISPLAYDIV_DEFAULT (_LCD_DISPCTRLX_DISPLAYDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRLX */ /* Bit fields for LCD SEGD0 */ -#define _LCD_SEGD0_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0 */ -#define _LCD_SEGD0_MASK 0x0FFFFFFFUL /**< Mask for LCD_SEGD0 */ -#define _LCD_SEGD0_SEGD0_SHIFT 0 /**< Shift value for LCD_SEGD0 */ -#define _LCD_SEGD0_SEGD0_MASK 0xFFFFFFFUL /**< Bit mask for LCD_SEGD0 */ -#define _LCD_SEGD0_SEGD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0 */ -#define LCD_SEGD0_SEGD0_DEFAULT (_LCD_SEGD0_SEGD0_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0 */ +#define _LCD_SEGD0_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0 */ +#define _LCD_SEGD0_MASK 0x0FFFFFFFUL /**< Mask for LCD_SEGD0 */ +#define _LCD_SEGD0_SEGD0_SHIFT 0 /**< Shift value for LCD_SEGD0 */ +#define _LCD_SEGD0_SEGD0_MASK 0xFFFFFFFUL /**< Bit mask for LCD_SEGD0 */ +#define _LCD_SEGD0_SEGD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0 */ +#define LCD_SEGD0_SEGD0_DEFAULT (_LCD_SEGD0_SEGD0_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0 */ /* Bit fields for LCD SEGD1 */ -#define _LCD_SEGD1_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1 */ -#define _LCD_SEGD1_MASK 0x0FFFFFFFUL /**< Mask for LCD_SEGD1 */ -#define _LCD_SEGD1_SEGD1_SHIFT 0 /**< Shift value for LCD_SEGD1 */ -#define _LCD_SEGD1_SEGD1_MASK 0xFFFFFFFUL /**< Bit mask for LCD_SEGD1 */ -#define _LCD_SEGD1_SEGD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1 */ -#define LCD_SEGD1_SEGD1_DEFAULT (_LCD_SEGD1_SEGD1_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1 */ +#define _LCD_SEGD1_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1 */ +#define _LCD_SEGD1_MASK 0x0FFFFFFFUL /**< Mask for LCD_SEGD1 */ +#define _LCD_SEGD1_SEGD1_SHIFT 0 /**< Shift value for LCD_SEGD1 */ +#define _LCD_SEGD1_SEGD1_MASK 0xFFFFFFFUL /**< Bit mask for LCD_SEGD1 */ +#define _LCD_SEGD1_SEGD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1 */ +#define LCD_SEGD1_SEGD1_DEFAULT (_LCD_SEGD1_SEGD1_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1 */ /* Bit fields for LCD SEGD2 */ -#define _LCD_SEGD2_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2 */ -#define _LCD_SEGD2_MASK 0x0FFFFFFFUL /**< Mask for LCD_SEGD2 */ -#define _LCD_SEGD2_SEGD2_SHIFT 0 /**< Shift value for LCD_SEGD2 */ -#define _LCD_SEGD2_SEGD2_MASK 0xFFFFFFFUL /**< Bit mask for LCD_SEGD2 */ -#define _LCD_SEGD2_SEGD2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2 */ -#define LCD_SEGD2_SEGD2_DEFAULT (_LCD_SEGD2_SEGD2_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2 */ +#define _LCD_SEGD2_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2 */ +#define _LCD_SEGD2_MASK 0x0FFFFFFFUL /**< Mask for LCD_SEGD2 */ +#define _LCD_SEGD2_SEGD2_SHIFT 0 /**< Shift value for LCD_SEGD2 */ +#define _LCD_SEGD2_SEGD2_MASK 0xFFFFFFFUL /**< Bit mask for LCD_SEGD2 */ +#define _LCD_SEGD2_SEGD2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2 */ +#define LCD_SEGD2_SEGD2_DEFAULT (_LCD_SEGD2_SEGD2_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2 */ /* Bit fields for LCD SEGD3 */ -#define _LCD_SEGD3_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3 */ -#define _LCD_SEGD3_MASK 0x0FFFFFFFUL /**< Mask for LCD_SEGD3 */ -#define _LCD_SEGD3_SEGD3_SHIFT 0 /**< Shift value for LCD_SEGD3 */ -#define _LCD_SEGD3_SEGD3_MASK 0xFFFFFFFUL /**< Bit mask for LCD_SEGD3 */ -#define _LCD_SEGD3_SEGD3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3 */ -#define LCD_SEGD3_SEGD3_DEFAULT (_LCD_SEGD3_SEGD3_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3 */ +#define _LCD_SEGD3_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3 */ +#define _LCD_SEGD3_MASK 0x0FFFFFFFUL /**< Mask for LCD_SEGD3 */ +#define _LCD_SEGD3_SEGD3_SHIFT 0 /**< Shift value for LCD_SEGD3 */ +#define _LCD_SEGD3_SEGD3_MASK 0xFFFFFFFUL /**< Bit mask for LCD_SEGD3 */ +#define _LCD_SEGD3_SEGD3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3 */ +#define LCD_SEGD3_SEGD3_DEFAULT (_LCD_SEGD3_SEGD3_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3 */ /* Bit fields for LCD SEGD4 */ -#define _LCD_SEGD4_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4 */ -#define _LCD_SEGD4_MASK 0x0FFFFFFFUL /**< Mask for LCD_SEGD4 */ -#define _LCD_SEGD4_SEGD4_SHIFT 0 /**< Shift value for LCD_SEGD4 */ -#define _LCD_SEGD4_SEGD4_MASK 0xFFFFFFFUL /**< Bit mask for LCD_SEGD4 */ -#define _LCD_SEGD4_SEGD4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4 */ -#define LCD_SEGD4_SEGD4_DEFAULT (_LCD_SEGD4_SEGD4_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4 */ +#define _LCD_SEGD4_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4 */ +#define _LCD_SEGD4_MASK 0x0FFFFFFFUL /**< Mask for LCD_SEGD4 */ +#define _LCD_SEGD4_SEGD4_SHIFT 0 /**< Shift value for LCD_SEGD4 */ +#define _LCD_SEGD4_SEGD4_MASK 0xFFFFFFFUL /**< Bit mask for LCD_SEGD4 */ +#define _LCD_SEGD4_SEGD4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4 */ +#define LCD_SEGD4_SEGD4_DEFAULT (_LCD_SEGD4_SEGD4_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4 */ /* Bit fields for LCD SEGD5 */ -#define _LCD_SEGD5_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5 */ -#define _LCD_SEGD5_MASK 0x0FFFFFFFUL /**< Mask for LCD_SEGD5 */ -#define _LCD_SEGD5_SEGD5_SHIFT 0 /**< Shift value for LCD_SEGD5 */ -#define _LCD_SEGD5_SEGD5_MASK 0xFFFFFFFUL /**< Bit mask for LCD_SEGD5 */ -#define _LCD_SEGD5_SEGD5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5 */ -#define LCD_SEGD5_SEGD5_DEFAULT (_LCD_SEGD5_SEGD5_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5 */ +#define _LCD_SEGD5_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5 */ +#define _LCD_SEGD5_MASK 0x0FFFFFFFUL /**< Mask for LCD_SEGD5 */ +#define _LCD_SEGD5_SEGD5_SHIFT 0 /**< Shift value for LCD_SEGD5 */ +#define _LCD_SEGD5_SEGD5_MASK 0xFFFFFFFUL /**< Bit mask for LCD_SEGD5 */ +#define _LCD_SEGD5_SEGD5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5 */ +#define LCD_SEGD5_SEGD5_DEFAULT (_LCD_SEGD5_SEGD5_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5 */ /* Bit fields for LCD SEGD6 */ -#define _LCD_SEGD6_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6 */ -#define _LCD_SEGD6_MASK 0x0FFFFFFFUL /**< Mask for LCD_SEGD6 */ -#define _LCD_SEGD6_SEGD6_SHIFT 0 /**< Shift value for LCD_SEGD6 */ -#define _LCD_SEGD6_SEGD6_MASK 0xFFFFFFFUL /**< Bit mask for LCD_SEGD6 */ -#define _LCD_SEGD6_SEGD6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6 */ -#define LCD_SEGD6_SEGD6_DEFAULT (_LCD_SEGD6_SEGD6_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6 */ +#define _LCD_SEGD6_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6 */ +#define _LCD_SEGD6_MASK 0x0FFFFFFFUL /**< Mask for LCD_SEGD6 */ +#define _LCD_SEGD6_SEGD6_SHIFT 0 /**< Shift value for LCD_SEGD6 */ +#define _LCD_SEGD6_SEGD6_MASK 0xFFFFFFFUL /**< Bit mask for LCD_SEGD6 */ +#define _LCD_SEGD6_SEGD6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6 */ +#define LCD_SEGD6_SEGD6_DEFAULT (_LCD_SEGD6_SEGD6_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6 */ /* Bit fields for LCD SEGD7 */ -#define _LCD_SEGD7_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7 */ -#define _LCD_SEGD7_MASK 0x0FFFFFFFUL /**< Mask for LCD_SEGD7 */ -#define _LCD_SEGD7_SEGD7_SHIFT 0 /**< Shift value for LCD_SEGD7 */ -#define _LCD_SEGD7_SEGD7_MASK 0xFFFFFFFUL /**< Bit mask for LCD_SEGD7 */ -#define _LCD_SEGD7_SEGD7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7 */ -#define LCD_SEGD7_SEGD7_DEFAULT (_LCD_SEGD7_SEGD7_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7 */ +#define _LCD_SEGD7_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7 */ +#define _LCD_SEGD7_MASK 0x0FFFFFFFUL /**< Mask for LCD_SEGD7 */ +#define _LCD_SEGD7_SEGD7_SHIFT 0 /**< Shift value for LCD_SEGD7 */ +#define _LCD_SEGD7_SEGD7_MASK 0xFFFFFFFUL /**< Bit mask for LCD_SEGD7 */ +#define _LCD_SEGD7_SEGD7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7 */ +#define LCD_SEGD7_SEGD7_DEFAULT (_LCD_SEGD7_SEGD7_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7 */ /* Bit fields for LCD UPDATECTRL */ -#define _LCD_UPDATECTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_UPDATECTRL */ -#define _LCD_UPDATECTRL_MASK 0x0001E100UL /**< Mask for LCD_UPDATECTRL */ -#define LCD_UPDATECTRL_AUTOLOAD (0x1UL << 8) /**< Auto Load */ -#define _LCD_UPDATECTRL_AUTOLOAD_SHIFT 8 /**< Shift value for LCD_AUTOLOAD */ -#define _LCD_UPDATECTRL_AUTOLOAD_MASK 0x100UL /**< Bit mask for LCD_AUTOLOAD */ -#define _LCD_UPDATECTRL_AUTOLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_UPDATECTRL */ -#define _LCD_UPDATECTRL_AUTOLOAD_MANUAL 0x00000000UL /**< Mode MANUAL for LCD_UPDATECTRL */ -#define _LCD_UPDATECTRL_AUTOLOAD_AUTO 0x00000001UL /**< Mode AUTO for LCD_UPDATECTRL */ -#define LCD_UPDATECTRL_AUTOLOAD_DEFAULT (_LCD_UPDATECTRL_AUTOLOAD_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_UPDATECTRL */ -#define LCD_UPDATECTRL_AUTOLOAD_MANUAL (_LCD_UPDATECTRL_AUTOLOAD_MANUAL << 8) /**< Shifted mode MANUAL for LCD_UPDATECTRL */ -#define LCD_UPDATECTRL_AUTOLOAD_AUTO (_LCD_UPDATECTRL_AUTOLOAD_AUTO << 8) /**< Shifted mode AUTO for LCD_UPDATECTRL */ -#define _LCD_UPDATECTRL_LOADADDR_SHIFT 13 /**< Shift value for LCD_LOADADDR */ -#define _LCD_UPDATECTRL_LOADADDR_MASK 0x1E000UL /**< Bit mask for LCD_LOADADDR */ -#define _LCD_UPDATECTRL_LOADADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_UPDATECTRL */ -#define _LCD_UPDATECTRL_LOADADDR_BACTRLWR 0x00000000UL /**< Mode BACTRLWR for LCD_UPDATECTRL */ -#define _LCD_UPDATECTRL_LOADADDR_AREGAWR 0x00000001UL /**< Mode AREGAWR for LCD_UPDATECTRL */ -#define _LCD_UPDATECTRL_LOADADDR_AREGBWR 0x00000002UL /**< Mode AREGBWR for LCD_UPDATECTRL */ -#define _LCD_UPDATECTRL_LOADADDR_SEGD0WR 0x00000003UL /**< Mode SEGD0WR for LCD_UPDATECTRL */ -#define _LCD_UPDATECTRL_LOADADDR_SEGD1WR 0x00000004UL /**< Mode SEGD1WR for LCD_UPDATECTRL */ -#define _LCD_UPDATECTRL_LOADADDR_SEGD2WR 0x00000005UL /**< Mode SEGD2WR for LCD_UPDATECTRL */ -#define _LCD_UPDATECTRL_LOADADDR_SEGD3WR 0x00000006UL /**< Mode SEGD3WR for LCD_UPDATECTRL */ -#define _LCD_UPDATECTRL_LOADADDR_SEGD4WR 0x00000007UL /**< Mode SEGD4WR for LCD_UPDATECTRL */ -#define _LCD_UPDATECTRL_LOADADDR_SEGD5WR 0x00000008UL /**< Mode SEGD5WR for LCD_UPDATECTRL */ -#define _LCD_UPDATECTRL_LOADADDR_SEGD6WR 0x00000009UL /**< Mode SEGD6WR for LCD_UPDATECTRL */ -#define _LCD_UPDATECTRL_LOADADDR_SEGD7WR 0x0000000AUL /**< Mode SEGD7WR for LCD_UPDATECTRL */ -#define LCD_UPDATECTRL_LOADADDR_DEFAULT (_LCD_UPDATECTRL_LOADADDR_DEFAULT << 13) /**< Shifted mode DEFAULT for LCD_UPDATECTRL */ -#define LCD_UPDATECTRL_LOADADDR_BACTRLWR (_LCD_UPDATECTRL_LOADADDR_BACTRLWR << 13) /**< Shifted mode BACTRLWR for LCD_UPDATECTRL */ -#define LCD_UPDATECTRL_LOADADDR_AREGAWR (_LCD_UPDATECTRL_LOADADDR_AREGAWR << 13) /**< Shifted mode AREGAWR for LCD_UPDATECTRL */ -#define LCD_UPDATECTRL_LOADADDR_AREGBWR (_LCD_UPDATECTRL_LOADADDR_AREGBWR << 13) /**< Shifted mode AREGBWR for LCD_UPDATECTRL */ -#define LCD_UPDATECTRL_LOADADDR_SEGD0WR (_LCD_UPDATECTRL_LOADADDR_SEGD0WR << 13) /**< Shifted mode SEGD0WR for LCD_UPDATECTRL */ -#define LCD_UPDATECTRL_LOADADDR_SEGD1WR (_LCD_UPDATECTRL_LOADADDR_SEGD1WR << 13) /**< Shifted mode SEGD1WR for LCD_UPDATECTRL */ -#define LCD_UPDATECTRL_LOADADDR_SEGD2WR (_LCD_UPDATECTRL_LOADADDR_SEGD2WR << 13) /**< Shifted mode SEGD2WR for LCD_UPDATECTRL */ -#define LCD_UPDATECTRL_LOADADDR_SEGD3WR (_LCD_UPDATECTRL_LOADADDR_SEGD3WR << 13) /**< Shifted mode SEGD3WR for LCD_UPDATECTRL */ -#define LCD_UPDATECTRL_LOADADDR_SEGD4WR (_LCD_UPDATECTRL_LOADADDR_SEGD4WR << 13) /**< Shifted mode SEGD4WR for LCD_UPDATECTRL */ -#define LCD_UPDATECTRL_LOADADDR_SEGD5WR (_LCD_UPDATECTRL_LOADADDR_SEGD5WR << 13) /**< Shifted mode SEGD5WR for LCD_UPDATECTRL */ -#define LCD_UPDATECTRL_LOADADDR_SEGD6WR (_LCD_UPDATECTRL_LOADADDR_SEGD6WR << 13) /**< Shifted mode SEGD6WR for LCD_UPDATECTRL */ -#define LCD_UPDATECTRL_LOADADDR_SEGD7WR (_LCD_UPDATECTRL_LOADADDR_SEGD7WR << 13) /**< Shifted mode SEGD7WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_MASK 0x0001E100UL /**< Mask for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_AUTOLOAD (0x1UL << 8) /**< Auto Load */ +#define _LCD_UPDATECTRL_AUTOLOAD_SHIFT 8 /**< Shift value for LCD_AUTOLOAD */ +#define _LCD_UPDATECTRL_AUTOLOAD_MASK 0x100UL /**< Bit mask for LCD_AUTOLOAD */ +#define _LCD_UPDATECTRL_AUTOLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_AUTOLOAD_MANUAL 0x00000000UL /**< Mode MANUAL for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_AUTOLOAD_AUTO 0x00000001UL /**< Mode AUTO for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_AUTOLOAD_DEFAULT (_LCD_UPDATECTRL_AUTOLOAD_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_AUTOLOAD_MANUAL (_LCD_UPDATECTRL_AUTOLOAD_MANUAL << 8) /**< Shifted mode MANUAL for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_AUTOLOAD_AUTO (_LCD_UPDATECTRL_AUTOLOAD_AUTO << 8) /**< Shifted mode AUTO for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SHIFT 13 /**< Shift value for LCD_LOADADDR */ +#define _LCD_UPDATECTRL_LOADADDR_MASK 0x1E000UL /**< Bit mask for LCD_LOADADDR */ +#define _LCD_UPDATECTRL_LOADADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_BACTRLWR 0x00000000UL /**< Mode BACTRLWR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_AREGAWR 0x00000001UL /**< Mode AREGAWR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_AREGBWR 0x00000002UL /**< Mode AREGBWR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD0WR 0x00000003UL /**< Mode SEGD0WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD1WR 0x00000004UL /**< Mode SEGD1WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD2WR 0x00000005UL /**< Mode SEGD2WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD3WR 0x00000006UL /**< Mode SEGD3WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD4WR 0x00000007UL /**< Mode SEGD4WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD5WR 0x00000008UL /**< Mode SEGD5WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD6WR 0x00000009UL /**< Mode SEGD6WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD7WR 0x0000000AUL /**< Mode SEGD7WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_DEFAULT (_LCD_UPDATECTRL_LOADADDR_DEFAULT << 13) /**< Shifted mode DEFAULT for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_BACTRLWR (_LCD_UPDATECTRL_LOADADDR_BACTRLWR << 13) /**< Shifted mode BACTRLWR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_AREGAWR (_LCD_UPDATECTRL_LOADADDR_AREGAWR << 13) /**< Shifted mode AREGAWR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_AREGBWR (_LCD_UPDATECTRL_LOADADDR_AREGBWR << 13) /**< Shifted mode AREGBWR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD0WR (_LCD_UPDATECTRL_LOADADDR_SEGD0WR << 13) /**< Shifted mode SEGD0WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD1WR (_LCD_UPDATECTRL_LOADADDR_SEGD1WR << 13) /**< Shifted mode SEGD1WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD2WR (_LCD_UPDATECTRL_LOADADDR_SEGD2WR << 13) /**< Shifted mode SEGD2WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD3WR (_LCD_UPDATECTRL_LOADADDR_SEGD3WR << 13) /**< Shifted mode SEGD3WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD4WR (_LCD_UPDATECTRL_LOADADDR_SEGD4WR << 13) /**< Shifted mode SEGD4WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD5WR (_LCD_UPDATECTRL_LOADADDR_SEGD5WR << 13) /**< Shifted mode SEGD5WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD6WR (_LCD_UPDATECTRL_LOADADDR_SEGD6WR << 13) /**< Shifted mode SEGD6WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD7WR (_LCD_UPDATECTRL_LOADADDR_SEGD7WR << 13) /**< Shifted mode SEGD7WR for LCD_UPDATECTRL */ /* Bit fields for LCD FRAMERATE */ -#define _LCD_FRAMERATE_RESETVALUE 0x00000000UL /**< Default value for LCD_FRAMERATE */ -#define _LCD_FRAMERATE_MASK 0x000001FFUL /**< Mask for LCD_FRAMERATE */ -#define _LCD_FRAMERATE_FRDIV_SHIFT 0 /**< Shift value for LCD_FRDIV */ -#define _LCD_FRAMERATE_FRDIV_MASK 0x1FFUL /**< Bit mask for LCD_FRDIV */ -#define _LCD_FRAMERATE_FRDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FRAMERATE */ -#define LCD_FRAMERATE_FRDIV_DEFAULT (_LCD_FRAMERATE_FRDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FRAMERATE */ +#define _LCD_FRAMERATE_RESETVALUE 0x00000000UL /**< Default value for LCD_FRAMERATE */ +#define _LCD_FRAMERATE_MASK 0x000001FFUL /**< Mask for LCD_FRAMERATE */ +#define _LCD_FRAMERATE_FRDIV_SHIFT 0 /**< Shift value for LCD_FRDIV */ +#define _LCD_FRAMERATE_FRDIV_MASK 0x1FFUL /**< Bit mask for LCD_FRDIV */ +#define _LCD_FRAMERATE_FRDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FRAMERATE */ +#define LCD_FRAMERATE_FRDIV_DEFAULT (_LCD_FRAMERATE_FRDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FRAMERATE */ /** @} End of group EFR32SG28_LCD_BitFields */ /** @} End of group EFR32SG28_LCD */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lcdrf.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lcdrf.h index 2136c629d8..39941e6539 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lcdrf.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lcdrf.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_LCDRF_H #define EFR32SG28_LCDRF_H - #define LCDRF_HAS_SET_CLEAR /**************************************************************************//** @@ -43,15 +42,14 @@ *****************************************************************************/ /** LCDRF Register Declaration. */ -typedef struct -{ - __IOM uint32_t RFIMLCDCTRL; /**< RF Interference Mitigation LCD Control */ - uint32_t RESERVED0[1023U]; /**< Reserved for future use */ - __IOM uint32_t RFIMLCDCTRL_SET; /**< RF Interference Mitigation LCD Control */ - uint32_t RESERVED1[1023U]; /**< Reserved for future use */ - __IOM uint32_t RFIMLCDCTRL_CLR; /**< RF Interference Mitigation LCD Control */ - uint32_t RESERVED2[1023U]; /**< Reserved for future use */ - __IOM uint32_t RFIMLCDCTRL_TGL; /**< RF Interference Mitigation LCD Control */ +typedef struct { + __IOM uint32_t RFIMLCDCTRL; /**< RF Interference Mitigation LCD Control */ + uint32_t RESERVED0[1023U]; /**< Reserved for future use */ + __IOM uint32_t RFIMLCDCTRL_SET; /**< RF Interference Mitigation LCD Control */ + uint32_t RESERVED1[1023U]; /**< Reserved for future use */ + __IOM uint32_t RFIMLCDCTRL_CLR; /**< RF Interference Mitigation LCD Control */ + uint32_t RESERVED2[1023U]; /**< Reserved for future use */ + __IOM uint32_t RFIMLCDCTRL_TGL; /**< RF Interference Mitigation LCD Control */ } LCDRF_TypeDef; /** @} End of group EFR32SG28_LCDRF */ @@ -63,41 +61,41 @@ typedef struct *****************************************************************************/ /* Bit fields for LCDRF RFIMLCDCTRL */ -#define _LCDRF_RFIMLCDCTRL_RESETVALUE 0x00000000UL /**< Default value for LCDRF_RFIMLCDCTRL */ -#define _LCDRF_RFIMLCDCTRL_MASK 0x0000001FUL /**< Mask for LCDRF_RFIMLCDCTRL */ -#define LCDRF_RFIMLCDCTRL_LCDCPXOEN (0x1UL << 0) /**< LCD Charge Pump XO Clock Enable */ -#define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_SHIFT 0 /**< Shift value for LCDRF_LCDCPXOEN */ -#define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_MASK 0x1UL /**< Bit mask for LCDRF_LCDCPXOEN */ -#define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ -#define LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ -#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL (0x1UL << 1) /**< LCD Charge Pump XO Select */ -#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_SHIFT 1 /**< Shift value for LCDRF_LCDCPXOSEL */ -#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_MASK 0x2UL /**< Bit mask for LCDRF_LCDCPXOSEL */ -#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ -#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO 0x00000000UL /**< Mode INTRCO for LCDRF_RFIMLCDCTRL */ -#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV 0x00000001UL /**< Mode HFXODIV for LCDRF_RFIMLCDCTRL */ -#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ -#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO << 1) /**< Shifted mode INTRCO for LCDRF_RFIMLCDCTRL */ -#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV << 1) /**< Shifted mode HFXODIV for LCDRF_RFIMLCDCTRL */ -#define LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN (0x1UL << 2) /**< LCD Charge Pump XO Retime Enable */ -#define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_SHIFT 2 /**< Shift value for LCDRF_LCDCPXORETIMEEN */ -#define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_MASK 0x4UL /**< Bit mask for LCDRF_LCDCPXORETIMEEN */ -#define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ -#define LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ -#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE (0x1UL << 3) /**< LCD Low Noise */ -#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SHIFT 3 /**< Shift value for LCDRF_LCDLOWNOISE */ -#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_MASK 0x8UL /**< Bit mask for LCDRF_LCDLOWNOISE */ -#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ -#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL 0x00000000UL /**< Mode NORMAL for LCDRF_RFIMLCDCTRL */ -#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW 0x00000001UL /**< Mode SLOW for LCDRF_RFIMLCDCTRL */ -#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT << 3) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ -#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL << 3) /**< Shifted mode NORMAL for LCDRF_RFIMLCDCTRL */ -#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW << 3) /**< Shifted mode SLOW for LCDRF_RFIMLCDCTRL */ -#define LCDRF_RFIMLCDCTRL_LCDCMPDOUT (0x1UL << 4) /**< LCD Comparator Dout */ -#define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_SHIFT 4 /**< Shift value for LCDRF_LCDCMPDOUT */ -#define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_MASK 0x10UL /**< Bit mask for LCDRF_LCDCMPDOUT */ -#define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ -#define LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_RESETVALUE 0x00000000UL /**< Default value for LCDRF_RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_MASK 0x0000001FUL /**< Mask for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOEN (0x1UL << 0) /**< LCD Charge Pump XO Clock Enable */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_SHIFT 0 /**< Shift value for LCDRF_LCDCPXOEN */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_MASK 0x1UL /**< Bit mask for LCDRF_LCDCPXOEN */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL (0x1UL << 1) /**< LCD Charge Pump XO Select */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_SHIFT 1 /**< Shift value for LCDRF_LCDCPXOSEL */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_MASK 0x2UL /**< Bit mask for LCDRF_LCDCPXOSEL */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO 0x00000000UL /**< Mode INTRCO for LCDRF_RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV 0x00000001UL /**< Mode HFXODIV for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO << 1) /**< Shifted mode INTRCO for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV << 1) /**< Shifted mode HFXODIV for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN (0x1UL << 2) /**< LCD Charge Pump XO Retime Enable */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_SHIFT 2 /**< Shift value for LCDRF_LCDCPXORETIMEEN */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_MASK 0x4UL /**< Bit mask for LCDRF_LCDCPXORETIMEEN */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE (0x1UL << 3) /**< LCD Low Noise */ +#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SHIFT 3 /**< Shift value for LCDRF_LCDLOWNOISE */ +#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_MASK 0x8UL /**< Bit mask for LCDRF_LCDLOWNOISE */ +#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL 0x00000000UL /**< Mode NORMAL for LCDRF_RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW 0x00000001UL /**< Mode SLOW for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT << 3) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL << 3) /**< Shifted mode NORMAL for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW << 3) /**< Shifted mode SLOW for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCMPDOUT (0x1UL << 4) /**< LCD Comparator Dout */ +#define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_SHIFT 4 /**< Shift value for LCDRF_LCDCMPDOUT */ +#define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_MASK 0x10UL /**< Bit mask for LCDRF_LCDCMPDOUT */ +#define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ /** @} End of group EFR32SG28_LCDRF_BitFields */ /** @} End of group EFR32SG28_LCDRF */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldma.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldma.h index e33456ace3..b0c4ae0834 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldma.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldma.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_LDMA_H #define EFR32SG28_LDMA_H - #define LDMA_HAS_SET_CLEAR /**************************************************************************//** @@ -43,117 +42,114 @@ *****************************************************************************/ /** LDMA CH Register Group Declaration. */ -typedef struct -{ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t CFG; /**< Channel Configuration Register */ - __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ - __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ - __IOM uint32_t SRC; /**< Channel Descriptor Source Address */ - __IOM uint32_t DST; /**< Channel Descriptor Destination Address */ - __IOM uint32_t LINK; /**< Channel Descriptor Link Address */ - uint32_t RESERVED1[5U]; /**< Reserved for future use */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG; /**< Channel Configuration Register */ + __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ + __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ + __IOM uint32_t SRC; /**< Channel Descriptor Source Address */ + __IOM uint32_t DST; /**< Channel Descriptor Destination Address */ + __IOM uint32_t LINK; /**< Channel Descriptor Link Address */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ } LDMA_CH_TypeDef; - /** LDMA Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< DMA Channel Request Clear Register */ - __IOM uint32_t EN; /**< DMA module enable disable Register */ - __IOM uint32_t CTRL; /**< DMA Control Register */ - __IM uint32_t STATUS; /**< DMA Status Register */ - __IOM uint32_t SYNCSWSET; /**< DMA Sync Trig Sw Set Register */ - __IOM uint32_t SYNCSWCLR; /**< DMA Sync Trig Sw Clear register */ - __IOM uint32_t SYNCHWEN; /**< DMA Sync HW trigger enable register */ - __IOM uint32_t SYNCHWSEL; /**< DMA Sync HW trigger selection register */ - __IM uint32_t SYNCSTATUS; /**< DMA Sync Trigger Status Register */ - __IOM uint32_t CHEN; /**< DMA Channel Enable Register */ - __IOM uint32_t CHDIS; /**< DMA Channel Disable Register */ - __IM uint32_t CHSTATUS; /**< DMA Channel Status Register */ - __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ - __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register */ - __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ - __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request */ - __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ - __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ - __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ - __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED0[906U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< DMA Channel Request Clear Register */ - __IOM uint32_t EN_SET; /**< DMA module enable disable Register */ - __IOM uint32_t CTRL_SET; /**< DMA Control Register */ - __IM uint32_t STATUS_SET; /**< DMA Status Register */ - __IOM uint32_t SYNCSWSET_SET; /**< DMA Sync Trig Sw Set Register */ - __IOM uint32_t SYNCSWCLR_SET; /**< DMA Sync Trig Sw Clear register */ - __IOM uint32_t SYNCHWEN_SET; /**< DMA Sync HW trigger enable register */ - __IOM uint32_t SYNCHWSEL_SET; /**< DMA Sync HW trigger selection register */ - __IM uint32_t SYNCSTATUS_SET; /**< DMA Sync Trigger Status Register */ - __IOM uint32_t CHEN_SET; /**< DMA Channel Enable Register */ - __IOM uint32_t CHDIS_SET; /**< DMA Channel Disable Register */ - __IM uint32_t CHSTATUS_SET; /**< DMA Channel Status Register */ - __IM uint32_t CHBUSY_SET; /**< DMA Channel Busy Register */ - __IOM uint32_t CHDONE_SET; /**< DMA Channel Linking Done Register */ - __IOM uint32_t DBGHALT_SET; /**< DMA Channel Debug Halt Register */ - __IOM uint32_t SWREQ_SET; /**< DMA Channel Software Transfer Request */ - __IOM uint32_t REQDIS_SET; /**< DMA Channel Request Disable Register */ - __IM uint32_t REQPEND_SET; /**< DMA Channel Requests Pending Register */ - __IOM uint32_t LINKLOAD_SET; /**< DMA Channel Link Load Register */ - __IOM uint32_t REQCLEAR_SET; /**< DMA Channel Request Clear Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - LDMA_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED1[906U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< DMA Channel Request Clear Register */ - __IOM uint32_t EN_CLR; /**< DMA module enable disable Register */ - __IOM uint32_t CTRL_CLR; /**< DMA Control Register */ - __IM uint32_t STATUS_CLR; /**< DMA Status Register */ - __IOM uint32_t SYNCSWSET_CLR; /**< DMA Sync Trig Sw Set Register */ - __IOM uint32_t SYNCSWCLR_CLR; /**< DMA Sync Trig Sw Clear register */ - __IOM uint32_t SYNCHWEN_CLR; /**< DMA Sync HW trigger enable register */ - __IOM uint32_t SYNCHWSEL_CLR; /**< DMA Sync HW trigger selection register */ - __IM uint32_t SYNCSTATUS_CLR; /**< DMA Sync Trigger Status Register */ - __IOM uint32_t CHEN_CLR; /**< DMA Channel Enable Register */ - __IOM uint32_t CHDIS_CLR; /**< DMA Channel Disable Register */ - __IM uint32_t CHSTATUS_CLR; /**< DMA Channel Status Register */ - __IM uint32_t CHBUSY_CLR; /**< DMA Channel Busy Register */ - __IOM uint32_t CHDONE_CLR; /**< DMA Channel Linking Done Register */ - __IOM uint32_t DBGHALT_CLR; /**< DMA Channel Debug Halt Register */ - __IOM uint32_t SWREQ_CLR; /**< DMA Channel Software Transfer Request */ - __IOM uint32_t REQDIS_CLR; /**< DMA Channel Request Disable Register */ - __IM uint32_t REQPEND_CLR; /**< DMA Channel Requests Pending Register */ - __IOM uint32_t LINKLOAD_CLR; /**< DMA Channel Link Load Register */ - __IOM uint32_t REQCLEAR_CLR; /**< DMA Channel Request Clear Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - LDMA_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED2[906U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< DMA Channel Request Clear Register */ - __IOM uint32_t EN_TGL; /**< DMA module enable disable Register */ - __IOM uint32_t CTRL_TGL; /**< DMA Control Register */ - __IM uint32_t STATUS_TGL; /**< DMA Status Register */ - __IOM uint32_t SYNCSWSET_TGL; /**< DMA Sync Trig Sw Set Register */ - __IOM uint32_t SYNCSWCLR_TGL; /**< DMA Sync Trig Sw Clear register */ - __IOM uint32_t SYNCHWEN_TGL; /**< DMA Sync HW trigger enable register */ - __IOM uint32_t SYNCHWSEL_TGL; /**< DMA Sync HW trigger selection register */ - __IM uint32_t SYNCSTATUS_TGL; /**< DMA Sync Trigger Status Register */ - __IOM uint32_t CHEN_TGL; /**< DMA Channel Enable Register */ - __IOM uint32_t CHDIS_TGL; /**< DMA Channel Disable Register */ - __IM uint32_t CHSTATUS_TGL; /**< DMA Channel Status Register */ - __IM uint32_t CHBUSY_TGL; /**< DMA Channel Busy Register */ - __IOM uint32_t CHDONE_TGL; /**< DMA Channel Linking Done Register */ - __IOM uint32_t DBGHALT_TGL; /**< DMA Channel Debug Halt Register */ - __IOM uint32_t SWREQ_TGL; /**< DMA Channel Software Transfer Request */ - __IOM uint32_t REQDIS_TGL; /**< DMA Channel Request Disable Register */ - __IM uint32_t REQPEND_TGL; /**< DMA Channel Requests Pending Register */ - __IOM uint32_t LINKLOAD_TGL; /**< DMA Channel Link Load Register */ - __IOM uint32_t REQCLEAR_TGL; /**< DMA Channel Request Clear Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - LDMA_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +typedef struct { + __IM uint32_t IPVERSION; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL; /**< DMA Control Register */ + __IM uint32_t STATUS; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN_SET; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_SET; /**< DMA Control Register */ + __IM uint32_t STATUS_SET; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_SET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_SET; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_SET; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_SET; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_SET; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_SET; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_SET; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_SET; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_SET; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_SET; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_SET; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_SET; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_SET; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_SET; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_SET; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_SET; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN_CLR; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_CLR; /**< DMA Control Register */ + __IM uint32_t STATUS_CLR; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_CLR; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_CLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_CLR; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_CLR; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_CLR; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_CLR; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_CLR; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_CLR; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_CLR; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_CLR; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_CLR; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_CLR; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_CLR; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_CLR; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_CLR; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_CLR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN_TGL; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_TGL; /**< DMA Control Register */ + __IM uint32_t STATUS_TGL; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_TGL; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_TGL; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_TGL; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_TGL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_TGL; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_TGL; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_TGL; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_TGL; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_TGL; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_TGL; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_TGL; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_TGL; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_TGL; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_TGL; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_TGL; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_TGL; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ } LDMA_TypeDef; /** @} End of group EFR32SG28_LDMA */ @@ -165,11 +161,11 @@ typedef struct *****************************************************************************/ /* Bit fields for LDMA IPVERSION */ -#define _LDMA_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LDMA_IPVERSION */ -#define _LDMA_IPVERSION_MASK 0x000000FFUL /**< Mask for LDMA_IPVERSION */ -#define _LDMA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMA_IPVERSION */ -#define _LDMA_IPVERSION_IPVERSION_MASK 0xFFUL /**< Bit mask for LDMA_IPVERSION */ -#define _LDMA_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_MASK 0x000000FFUL /**< Mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_MASK 0xFFUL /**< Bit mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IPVERSION */ #define LDMA_IPVERSION_IPVERSION_DEFAULT (_LDMA_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IPVERSION */ /* Bit fields for LDMA EN */ @@ -225,59 +221,59 @@ typedef struct #define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ /* Bit fields for LDMA SYNCSWSET */ -#define _LDMA_SYNCSWSET_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWSET */ -#define _LDMA_SYNCSWSET_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWSET */ -#define _LDMA_SYNCSWSET_SYNCSWSET_SHIFT 0 /**< Shift value for LDMA_SYNCSWSET */ -#define _LDMA_SYNCSWSET_SYNCSWSET_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWSET */ -#define _LDMA_SYNCSWSET_SYNCSWSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_SHIFT 0 /**< Shift value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWSET */ #define LDMA_SYNCSWSET_SYNCSWSET_DEFAULT (_LDMA_SYNCSWSET_SYNCSWSET_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWSET */ /* Bit fields for LDMA SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_SYNCSWCLR_SHIFT 0 /**< Shift value for LDMA_SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_SYNCSWCLR_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_SHIFT 0 /**< Shift value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWCLR */ #define LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT (_LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWCLR */ /* Bit fields for LDMA SYNCHWEN */ -#define _LDMA_SYNCHWEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWEN */ -#define _LDMA_SYNCHWEN_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWEN */ -#define _LDMA_SYNCHWEN_SYNCSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCSETEN */ -#define _LDMA_SYNCHWEN_SYNCSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEN */ -#define _LDMA_SYNCHWEN_SYNCSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ -#define LDMA_SYNCHWEN_SYNCSETEN_DEFAULT (_LDMA_SYNCHWEN_SYNCSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ -#define _LDMA_SYNCHWEN_SYNCCLREN_SHIFT 16 /**< Shift value for LDMA_SYNCCLREN */ -#define _LDMA_SYNCHWEN_SYNCCLREN_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREN */ -#define _LDMA_SYNCHWEN_SYNCCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define LDMA_SYNCHWEN_SYNCSETEN_DEFAULT (_LDMA_SYNCHWEN_SYNCSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_SHIFT 16 /**< Shift value for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ #define LDMA_SYNCHWEN_SYNCCLREN_DEFAULT (_LDMA_SYNCHWEN_SYNCCLREN_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ /* Bit fields for LDMA SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_SHIFT 0 /**< Shift value for LDMA_SYNCSETEDGE */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEDGE */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCSETEDGE_RISE (_LDMA_SYNCHWSEL_SYNCSETEDGE_RISE << 0) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCSETEDGE_FALL (_LDMA_SYNCHWSEL_SYNCSETEDGE_FALL << 0) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_SHIFT 16 /**< Shift value for LDMA_SYNCCLREDGE */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREDGE */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_SHIFT 0 /**< Shift value for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_RISE (_LDMA_SYNCHWSEL_SYNCSETEDGE_RISE << 0) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_FALL (_LDMA_SYNCHWSEL_SYNCSETEDGE_FALL << 0) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_SHIFT 16 /**< Shift value for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ #define LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCCLREDGE_RISE (_LDMA_SYNCHWSEL_SYNCCLREDGE_RISE << 16) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCCLREDGE_FALL (_LDMA_SYNCHWSEL_SYNCCLREDGE_FALL << 16) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_RISE (_LDMA_SYNCHWSEL_SYNCCLREDGE_RISE << 16) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_FALL (_LDMA_SYNCHWSEL_SYNCCLREDGE_FALL << 16) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ /* Bit fields for LDMA SYNCSTATUS */ -#define _LDMA_SYNCSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSTATUS */ -#define _LDMA_SYNCSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSTATUS */ -#define _LDMA_SYNCSTATUS_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ -#define _LDMA_SYNCSTATUS_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ -#define _LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSTATUS */ #define LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT (_LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSTATUS */ /* Bit fields for LDMA CHEN */ @@ -467,36 +463,36 @@ typedef struct #define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ /* Bit fields for LDMA CH_CFG */ -#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ -#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ -#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ -#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ -#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ -#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ -#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ +#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ #define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ #define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ -#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ -#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ -#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ +#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ #define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ #define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ @@ -509,140 +505,140 @@ typedef struct #define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ /* Bit fields for LDMA CH_CTRL */ -#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ -#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ -#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ #define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ -#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ -#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ -#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ -#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ -#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ -#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ -#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ -#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ -#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ -#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DONEIEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set En */ -#define _LDMA_CH_CTRL_DONEIEN_SHIFT 20 /**< Shift value for LDMA_DONEIEN */ -#define _LDMA_CH_CTRL_DONEIEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIEN */ -#define _LDMA_CH_CTRL_DONEIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DONEIEN_DEFAULT (_LDMA_CH_CTRL_DONEIEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ -#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ -#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ -#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ -#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ -#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ -#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ -#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ -#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ -#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ -#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ -#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ -#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ -#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ -#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ -#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ -#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ -#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ -#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ -#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ -#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ -#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ +#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ +#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set En */ +#define _LDMA_CH_CTRL_DONEIEN_SHIFT 20 /**< Shift value for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN_DEFAULT (_LDMA_CH_CTRL_DONEIEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ +#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ +#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ +#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ +#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ +#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ /* Bit fields for LDMA CH_SRC */ #define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldmaxbar.h index 2ce4d6312d..0174609bb5 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldmaxbar.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_LDMAXBAR_H #define EFR32SG28_LDMAXBAR_H - #define LDMAXBAR_HAS_SET_CLEAR /**************************************************************************//** @@ -43,26 +42,23 @@ *****************************************************************************/ /** LDMAXBAR CH Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Reg... */ +typedef struct { + __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Reg... */ } LDMAXBAR_CH_TypeDef; - /** LDMAXBAR Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP veersion ID */ - LDMAXBAR_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED0[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP veersion ID */ - LDMAXBAR_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED1[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP veersion ID */ - LDMAXBAR_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED2[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP veersion ID */ - LDMAXBAR_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ } LDMAXBAR_TypeDef; /** @} End of group EFR32SG28_LDMAXBAR */ @@ -74,24 +70,24 @@ typedef struct *****************************************************************************/ /* Bit fields for LDMAXBAR IPVERSION */ -#define _LDMAXBAR_IPVERSION_RESETVALUE 0x00000006UL /**< Default value for LDMAXBAR_IPVERSION */ -#define _LDMAXBAR_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LDMAXBAR_IPVERSION */ -#define _LDMAXBAR_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMAXBAR_IPVERSION */ -#define _LDMAXBAR_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LDMAXBAR_IPVERSION */ -#define _LDMAXBAR_IPVERSION_IPVERSION_DEFAULT 0x00000006UL /**< Mode DEFAULT for LDMAXBAR_IPVERSION */ -#define LDMAXBAR_IPVERSION_IPVERSION_DEFAULT (_LDMAXBAR_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_RESETVALUE 0x00000006UL /**< Default value for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_DEFAULT 0x00000006UL /**< Mode DEFAULT for LDMAXBAR_IPVERSION */ +#define LDMAXBAR_IPVERSION_IPVERSION_DEFAULT (_LDMAXBAR_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_IPVERSION */ /* Bit fields for LDMAXBAR CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMAXBAR_SIGSEL */ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMAXBAR_SIGSEL */ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMAXBAR_SOURCESEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMAXBAR_SOURCESEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ /** @} End of group EFR32SG28_LDMAXBAR_BitFields */ /** @} End of group EFR32SG28_LDMAXBAR */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldmaxbar_defines.h index 2de7b767dc..782243e461 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ldmaxbar_defines.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -31,169 +31,135 @@ #define EFR32SG28_LDMAXBAR_DEFINES_H // Module source selection indices -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL/**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 0x00000002UL/**< Mode TIMER0 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 0x00000003UL/**< Mode TIMER1 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 0x00000004UL/**< Mode USART0 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 0x00000005UL/**< Mode I2C0 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 0x00000006UL/**< Mode I2C1 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 0x0000000aUL/**< Mode IADC0 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MSC 0x0000000bUL/**< Mode MSC for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 0x0000000cUL/**< Mode TIMER2 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 0x0000000dUL/**< Mode TIMER3 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 0x0000000eUL/**< Mode TIMER4 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 0x0000000fUL/**< Mode VDAC0 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 0x00000010UL/**< Mode EUSART0 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 0x00000011UL/**< Mode EUSART1 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2 0x00000012UL/**< Mode EUSART2 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE 0x00000013UL/**< Mode LESENSE for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LCD 0x00000014UL/**< Mode LCD for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 0x00000002UL /**< Mode TIMER0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 0x00000003UL /**< Mode TIMER1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 0x00000004UL /**< Mode USART0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 0x00000005UL /**< Mode I2C0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 0x00000006UL /**< Mode I2C1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 0x0000000aUL /**< Mode IADC0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MSC 0x0000000bUL /**< Mode MSC for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 0x0000000cUL /**< Mode TIMER2 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 0x0000000dUL /**< Mode TIMER3 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 0x0000000eUL /**< Mode TIMER4 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 0x0000000fUL /**< Mode VDAC0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 0x00000010UL /**< Mode EUSART0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 0x00000011UL /**< Mode EUSART1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2 0x00000012UL /**< Mode EUSART2 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE 0x00000013UL /**< Mode LESENSE for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LCD 0x00000014UL /**< Mode LCD for LDMAXBAR_CH_REQSEL */ // Shifted source selection indices -#define LDMAXBAR_CH_REQSEL_SOURCESEL_NONE (_LDMAXBAR_CH_REQSEL_SOURCESEL_NONE << 16) -#define LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR (_LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR << 16)/**< Shifted Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 << 16)/**< Shifted Mode TIMER0 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 << 16)/**< Shifted Mode TIMER1 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 << 16)/**< Shifted Mode USART0 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 << 16)/**< Shifted Mode I2C0 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 << 16)/**< Shifted Mode I2C1 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 << 16)/**< Shifted Mode IADC0 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_MSC (_LDMAXBAR_CH_REQSEL_SOURCESEL_MSC << 16)/**< Shifted Mode MSC for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 << 16)/**< Shifted Mode TIMER2 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 << 16)/**< Shifted Mode TIMER3 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 << 16)/**< Shifted Mode TIMER4 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 << 16)/**< Shifted Mode VDAC0 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 << 16)/**< Shifted Mode EUSART0 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 << 16)/**< Shifted Mode EUSART1 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2 << 16)/**< Shifted Mode EUSART2 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE (_LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE << 16)/**< Shifted Mode LESENSE for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_LCD (_LDMAXBAR_CH_REQSEL_SOURCESEL_LCD << 16)/**< Shifted Mode LCD for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_NONE (_LDMAXBAR_CH_REQSEL_SOURCESEL_NONE << 16) +#define LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR (_LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR << 16) /**< Shifted Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted Mode TIMER0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted Mode TIMER1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted Mode USART0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted Mode I2C0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted Mode I2C1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 << 16) /**< Shifted Mode IADC0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_MSC (_LDMAXBAR_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted Mode MSC for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 << 16) /**< Shifted Mode TIMER2 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 << 16) /**< Shifted Mode TIMER3 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 << 16) /**< Shifted Mode TIMER4 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted Mode VDAC0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 << 16) /**< Shifted Mode EUSART0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 << 16) /**< Shifted Mode EUSART1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2 << 16) /**< Shifted Mode EUSART2 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE (_LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE << 16) /**< Shifted Mode LESENSE for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_LCD (_LDMAXBAR_CH_REQSEL_SOURCESEL_LCD << 16) /**< Shifted Mode LCD for LDMAXBAR_CH_REQSEL */ // Module signal selection indices -#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 0x00000000UL /** Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 0x00000001UL /** Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ - -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000000UL /** Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000001UL /** Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000002UL /** Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000003UL /** Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ - -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000000UL /** Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000001UL /** Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000002UL /** Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000003UL /** Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ - -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /** Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT 0x00000001UL /** Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL 0x00000002UL /** Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT 0x00000003UL /** Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000004UL /** Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ - -#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /** Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /** Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ - -#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /** Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /** Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ - -#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN 0x00000000UL /** Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE 0x00000001UL /** Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ - -#define _LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /** Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ - -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000000UL /** Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000001UL /** Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000002UL /** Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000003UL /** Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ - -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000000UL /** Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000001UL /** Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000002UL /** Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000003UL /** Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ - -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000000UL /** Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000001UL /** Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000002UL /** Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000003UL /** Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ - -#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ 0x00000000UL /** Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ 0x00000001UL /** Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ - -#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL 0x00000000UL /** Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL 0x00000001UL /** Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ - -#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL 0x00000000UL /** Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL 0x00000001UL /** Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ - -#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL 0x00000000UL /** Mode EUSART2RXFL for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL 0x00000001UL /** Mode EUSART2TXFL for LDMAXBAR_CH_REQSEL**/ - -#define _LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO 0x00000000UL /** Mode LESENSEFIFO for LDMAXBAR_CH_REQSEL**/ - -#define _LDMAXBAR_CH_REQSEL_SIGSEL_LCD 0x00000000UL /** Mode LCD for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 0x00000000UL /** Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 0x00000001UL /** Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000000UL /** Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000001UL /** Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000002UL /** Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000003UL /** Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000000UL /** Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000001UL /** Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000002UL /** Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000003UL /** Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /** Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT 0x00000001UL /** Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL 0x00000002UL /** Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT 0x00000003UL /** Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000004UL /** Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /** Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /** Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /** Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /** Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN 0x00000000UL /** Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE 0x00000001UL /** Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /** Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000000UL /** Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000001UL /** Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000002UL /** Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000003UL /** Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000000UL /** Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000001UL /** Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000002UL /** Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000003UL /** Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000000UL /** Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000001UL /** Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000002UL /** Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000003UL /** Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ 0x00000000UL /** Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ 0x00000001UL /** Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL 0x00000000UL /** Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL 0x00000001UL /** Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL 0x00000000UL /** Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL 0x00000001UL /** Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL 0x00000000UL /** Mode EUSART2RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL 0x00000001UL /** Mode EUSART2TXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO 0x00000000UL /** Mode LESENSEFIFO for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LCD 0x00000000UL /** Mode LCD for LDMAXBAR_CH_REQSEL**/ // Shifted Module signal selection indices -#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 << 0)/** Shifted Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 << 0)/** Shifted Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ - -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 << 0)/** Shifted Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 << 0)/** Shifted Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 << 0)/** Shifted Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF << 0)/** Shifted Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ - -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 << 0)/** Shifted Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 << 0)/** Shifted Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 << 0)/** Shifted Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF << 0)/** Shifted Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ - -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV << 0)/** Shifted Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT << 0)/** Shifted Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL << 0)/** Shifted Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT << 0)/** Shifted Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0)/** Shifted Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ - -#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0)/** Shifted Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL << 0)/** Shifted Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ - -#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0)/** Shifted Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL << 0)/** Shifted Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ - -#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN << 0)/** Shifted Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE << 0)/** Shifted Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ - -#define LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA (_LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA << 0)/** Shifted Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ - -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 << 0)/** Shifted Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 << 0)/** Shifted Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 << 0)/** Shifted Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF << 0)/** Shifted Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ - -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 << 0)/** Shifted Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0)/** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0)/** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0)/** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ - -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 << 0)/** Shifted Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0)/** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0)/** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0)/** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ - -#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ << 0)/** Shifted Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ << 0)/** Shifted Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ - -#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL << 0)/** Shifted Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL << 0)/** Shifted Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ - -#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL << 0)/** Shifted Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL << 0)/** Shifted Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ - -#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL << 0)/** Shifted Mode EUSART2RXFL for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL << 0)/** Shifted Mode EUSART2TXFL for LDMAXBAR_CH_REQSEL**/ - -#define LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO (_LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO << 0)/** Shifted Mode LESENSEFIFO for LDMAXBAR_CH_REQSEL**/ - -#define LDMAXBAR_CH_REQSEL_SIGSEL_LCD (_LDMAXBAR_CH_REQSEL_SIGSEL_LCD << 0)/** Shifted Mode LCD for LDMAXBAR_CH_REQSEL**/ - - +#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 << 0) /** Shifted Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 << 0) /** Shifted Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /** Shifted Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /** Shifted Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /** Shifted Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /** Shifted Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /** Shifted Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /** Shifted Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /** Shifted Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /** Shifted Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /** Shifted Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT << 0) /** Shifted Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL << 0) /** Shifted Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT << 0) /** Shifted Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /** Shifted Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /** Shifted Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /** Shifted Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /** Shifted Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /** Shifted Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN << 0) /** Shifted Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE << 0) /** Shifted Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA (_LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA << 0) /** Shifted Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 << 0) /** Shifted Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 << 0) /** Shifted Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 << 0) /** Shifted Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF << 0) /** Shifted Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 << 0) /** Shifted Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 << 0) /** Shifted Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ << 0) /** Shifted Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ << 0) /** Shifted Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL << 0) /** Shifted Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL << 0) /** Shifted Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL << 0) /** Shifted Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL << 0) /** Shifted Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL << 0) /** Shifted Mode EUSART2RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL << 0) /** Shifted Mode EUSART2TXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO (_LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO << 0) /** Shifted Mode LESENSEFIFO for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_LCD (_LDMAXBAR_CH_REQSEL_SIGSEL_LCD << 0) /** Shifted Mode LCD for LDMAXBAR_CH_REQSEL**/ #endif // EFR32SG28_LDMAXBAR_DEFINES_H diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lesense.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lesense.h index f4d25d2cc5..2c79a80240 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lesense.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lesense.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_LESENSE_H #define EFR32SG28_LESENSE_H - #define LESENSE_HAS_SET_CLEAR /**************************************************************************//** @@ -43,136 +42,131 @@ *****************************************************************************/ /** LESENSE CH Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t TIMING; /**< Scan configuration */ - __IOM uint32_t INTERACT; /**< Scan configuration */ - __IOM uint32_t EVALCFG; /**< Scan configuration */ - __IOM uint32_t EVALTHRES; /**< Scan confguration */ +typedef struct { + __IOM uint32_t TIMING; /**< Scan configuration */ + __IOM uint32_t INTERACT; /**< Scan configuration */ + __IOM uint32_t EVALCFG; /**< Scan configuration */ + __IOM uint32_t EVALTHRES; /**< Scan confguration */ } LESENSE_CH_TypeDef; - /** LESENSE ST Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t ARC; /**< State transition Arc */ +typedef struct { + __IOM uint32_t ARC; /**< State transition Arc */ } LESENSE_ST_TypeDef; - /** LESENSE Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< Enable */ - __IOM uint32_t SWRST; /**< Software Reset Register */ - __IOM uint32_t CFG; /**< Configuration */ - __IOM uint32_t TIMCTRL; /**< Timing Control */ - __IOM uint32_t PERCTRL; /**< Peripheral Control */ - __IOM uint32_t DECCTRL; /**< Decoder control */ - __IOM uint32_t EVALCTRL; /**< LESENSE evaluation */ - __IOM uint32_t PRSCTRL; /**< PRS control */ - __IOM uint32_t CMD; /**< Command */ - __IOM uint32_t CHEN; /**< Channel enable */ - __IM uint32_t SCANRES; /**< Scan result */ - __IM uint32_t STATUS; /**< Status */ - __IM uint32_t RESCOUNT; /**< Result FIFO Count */ - __IM uint32_t RESFIFO; /**< Result Fifo */ - __IM uint32_t CURCH; /**< Current channel index */ - __IM uint32_t DECSTATE; /**< Current decoder state */ - __IM uint32_t SENSORSTATE; /**< Sensor State */ - __IOM uint32_t IDLECONF; /**< IDLE Configuration */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t SYNCBUSY; /**< Synchronization */ - uint32_t RESERVED1[3U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enables */ - uint32_t RESERVED2[38U]; /**< Reserved for future use */ - LESENSE_CH_TypeDef CH[16U]; /**< Channels */ - LESENSE_ST_TypeDef ST[64U]; /**< Decoding FSM Arcs */ - uint32_t RESERVED3[832U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< Enable */ - __IOM uint32_t SWRST_SET; /**< Software Reset Register */ - __IOM uint32_t CFG_SET; /**< Configuration */ - __IOM uint32_t TIMCTRL_SET; /**< Timing Control */ - __IOM uint32_t PERCTRL_SET; /**< Peripheral Control */ - __IOM uint32_t DECCTRL_SET; /**< Decoder control */ - __IOM uint32_t EVALCTRL_SET; /**< LESENSE evaluation */ - __IOM uint32_t PRSCTRL_SET; /**< PRS control */ - __IOM uint32_t CMD_SET; /**< Command */ - __IOM uint32_t CHEN_SET; /**< Channel enable */ - __IM uint32_t SCANRES_SET; /**< Scan result */ - __IM uint32_t STATUS_SET; /**< Status */ - __IM uint32_t RESCOUNT_SET; /**< Result FIFO Count */ - __IM uint32_t RESFIFO_SET; /**< Result Fifo */ - __IM uint32_t CURCH_SET; /**< Current channel index */ - __IM uint32_t DECSTATE_SET; /**< Current decoder state */ - __IM uint32_t SENSORSTATE_SET; /**< Sensor State */ - __IOM uint32_t IDLECONF_SET; /**< IDLE Configuration */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization */ - uint32_t RESERVED5[3U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enables */ - uint32_t RESERVED6[38U]; /**< Reserved for future use */ - LESENSE_CH_TypeDef CH_SET[16U]; /**< Channels */ - LESENSE_ST_TypeDef ST_SET[64U]; /**< Decoding FSM Arcs */ - uint32_t RESERVED7[832U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< Enable */ - __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ - __IOM uint32_t CFG_CLR; /**< Configuration */ - __IOM uint32_t TIMCTRL_CLR; /**< Timing Control */ - __IOM uint32_t PERCTRL_CLR; /**< Peripheral Control */ - __IOM uint32_t DECCTRL_CLR; /**< Decoder control */ - __IOM uint32_t EVALCTRL_CLR; /**< LESENSE evaluation */ - __IOM uint32_t PRSCTRL_CLR; /**< PRS control */ - __IOM uint32_t CMD_CLR; /**< Command */ - __IOM uint32_t CHEN_CLR; /**< Channel enable */ - __IM uint32_t SCANRES_CLR; /**< Scan result */ - __IM uint32_t STATUS_CLR; /**< Status */ - __IM uint32_t RESCOUNT_CLR; /**< Result FIFO Count */ - __IM uint32_t RESFIFO_CLR; /**< Result Fifo */ - __IM uint32_t CURCH_CLR; /**< Current channel index */ - __IM uint32_t DECSTATE_CLR; /**< Current decoder state */ - __IM uint32_t SENSORSTATE_CLR; /**< Sensor State */ - __IOM uint32_t IDLECONF_CLR; /**< IDLE Configuration */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization */ - uint32_t RESERVED9[3U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ - uint32_t RESERVED10[38U]; /**< Reserved for future use */ - LESENSE_CH_TypeDef CH_CLR[16U]; /**< Channels */ - LESENSE_ST_TypeDef ST_CLR[64U]; /**< Decoding FSM Arcs */ - uint32_t RESERVED11[832U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< Enable */ - __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ - __IOM uint32_t CFG_TGL; /**< Configuration */ - __IOM uint32_t TIMCTRL_TGL; /**< Timing Control */ - __IOM uint32_t PERCTRL_TGL; /**< Peripheral Control */ - __IOM uint32_t DECCTRL_TGL; /**< Decoder control */ - __IOM uint32_t EVALCTRL_TGL; /**< LESENSE evaluation */ - __IOM uint32_t PRSCTRL_TGL; /**< PRS control */ - __IOM uint32_t CMD_TGL; /**< Command */ - __IOM uint32_t CHEN_TGL; /**< Channel enable */ - __IM uint32_t SCANRES_TGL; /**< Scan result */ - __IM uint32_t STATUS_TGL; /**< Status */ - __IM uint32_t RESCOUNT_TGL; /**< Result FIFO Count */ - __IM uint32_t RESFIFO_TGL; /**< Result Fifo */ - __IM uint32_t CURCH_TGL; /**< Current channel index */ - __IM uint32_t DECSTATE_TGL; /**< Current decoder state */ - __IM uint32_t SENSORSTATE_TGL; /**< Sensor State */ - __IOM uint32_t IDLECONF_TGL; /**< IDLE Configuration */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization */ - uint32_t RESERVED13[3U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ - uint32_t RESERVED14[38U]; /**< Reserved for future use */ - LESENSE_CH_TypeDef CH_TGL[16U]; /**< Channels */ - LESENSE_ST_TypeDef ST_TGL[64U]; /**< Decoding FSM Arcs */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Configuration */ + __IOM uint32_t TIMCTRL; /**< Timing Control */ + __IOM uint32_t PERCTRL; /**< Peripheral Control */ + __IOM uint32_t DECCTRL; /**< Decoder control */ + __IOM uint32_t EVALCTRL; /**< LESENSE evaluation */ + __IOM uint32_t PRSCTRL; /**< PRS control */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t CHEN; /**< Channel enable */ + __IM uint32_t SCANRES; /**< Scan result */ + __IM uint32_t STATUS; /**< Status */ + __IM uint32_t RESCOUNT; /**< Result FIFO Count */ + __IM uint32_t RESFIFO; /**< Result Fifo */ + __IM uint32_t CURCH; /**< Current channel index */ + __IM uint32_t DECSTATE; /**< Current decoder state */ + __IM uint32_t SENSORSTATE; /**< Sensor State */ + __IOM uint32_t IDLECONF; /**< IDLE Configuration */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY; /**< Synchronization */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + uint32_t RESERVED2[38U]; /**< Reserved for future use */ + LESENSE_CH_TypeDef CH[16U]; /**< Channels */ + LESENSE_ST_TypeDef ST[64U]; /**< Decoding FSM Arcs */ + uint32_t RESERVED3[832U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Configuration */ + __IOM uint32_t TIMCTRL_SET; /**< Timing Control */ + __IOM uint32_t PERCTRL_SET; /**< Peripheral Control */ + __IOM uint32_t DECCTRL_SET; /**< Decoder control */ + __IOM uint32_t EVALCTRL_SET; /**< LESENSE evaluation */ + __IOM uint32_t PRSCTRL_SET; /**< PRS control */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t CHEN_SET; /**< Channel enable */ + __IM uint32_t SCANRES_SET; /**< Scan result */ + __IM uint32_t STATUS_SET; /**< Status */ + __IM uint32_t RESCOUNT_SET; /**< Result FIFO Count */ + __IM uint32_t RESFIFO_SET; /**< Result Fifo */ + __IM uint32_t CURCH_SET; /**< Current channel index */ + __IM uint32_t DECSTATE_SET; /**< Current decoder state */ + __IM uint32_t SENSORSTATE_SET; /**< Sensor State */ + __IOM uint32_t IDLECONF_SET; /**< IDLE Configuration */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization */ + uint32_t RESERVED5[3U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + uint32_t RESERVED6[38U]; /**< Reserved for future use */ + LESENSE_CH_TypeDef CH_SET[16U]; /**< Channels */ + LESENSE_ST_TypeDef ST_SET[64U]; /**< Decoding FSM Arcs */ + uint32_t RESERVED7[832U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Configuration */ + __IOM uint32_t TIMCTRL_CLR; /**< Timing Control */ + __IOM uint32_t PERCTRL_CLR; /**< Peripheral Control */ + __IOM uint32_t DECCTRL_CLR; /**< Decoder control */ + __IOM uint32_t EVALCTRL_CLR; /**< LESENSE evaluation */ + __IOM uint32_t PRSCTRL_CLR; /**< PRS control */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t CHEN_CLR; /**< Channel enable */ + __IM uint32_t SCANRES_CLR; /**< Scan result */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IM uint32_t RESCOUNT_CLR; /**< Result FIFO Count */ + __IM uint32_t RESFIFO_CLR; /**< Result Fifo */ + __IM uint32_t CURCH_CLR; /**< Current channel index */ + __IM uint32_t DECSTATE_CLR; /**< Current decoder state */ + __IM uint32_t SENSORSTATE_CLR; /**< Sensor State */ + __IOM uint32_t IDLECONF_CLR; /**< IDLE Configuration */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization */ + uint32_t RESERVED9[3U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + uint32_t RESERVED10[38U]; /**< Reserved for future use */ + LESENSE_CH_TypeDef CH_CLR[16U]; /**< Channels */ + LESENSE_ST_TypeDef ST_CLR[64U]; /**< Decoding FSM Arcs */ + uint32_t RESERVED11[832U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Configuration */ + __IOM uint32_t TIMCTRL_TGL; /**< Timing Control */ + __IOM uint32_t PERCTRL_TGL; /**< Peripheral Control */ + __IOM uint32_t DECCTRL_TGL; /**< Decoder control */ + __IOM uint32_t EVALCTRL_TGL; /**< LESENSE evaluation */ + __IOM uint32_t PRSCTRL_TGL; /**< PRS control */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t CHEN_TGL; /**< Channel enable */ + __IM uint32_t SCANRES_TGL; /**< Scan result */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IM uint32_t RESCOUNT_TGL; /**< Result FIFO Count */ + __IM uint32_t RESFIFO_TGL; /**< Result Fifo */ + __IM uint32_t CURCH_TGL; /**< Current channel index */ + __IM uint32_t DECSTATE_TGL; /**< Current decoder state */ + __IM uint32_t SENSORSTATE_TGL; /**< Sensor State */ + __IOM uint32_t IDLECONF_TGL; /**< IDLE Configuration */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization */ + uint32_t RESERVED13[3U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ + uint32_t RESERVED14[38U]; /**< Reserved for future use */ + LESENSE_CH_TypeDef CH_TGL[16U]; /**< Channels */ + LESENSE_ST_TypeDef ST_TGL[64U]; /**< Decoding FSM Arcs */ } LESENSE_TypeDef; /** @} End of group EFR32SG28_LESENSE */ @@ -184,1042 +178,1042 @@ typedef struct *****************************************************************************/ /* Bit fields for LESENSE IPVERSION */ -#define _LESENSE_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LESENSE_IPVERSION */ -#define _LESENSE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_IPVERSION */ -#define _LESENSE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LESENSE_IPVERSION */ -#define _LESENSE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LESENSE_IPVERSION */ -#define _LESENSE_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LESENSE_IPVERSION */ -#define LESENSE_IPVERSION_IPVERSION_DEFAULT (_LESENSE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IPVERSION */ +#define _LESENSE_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LESENSE_IPVERSION */ +#define _LESENSE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_IPVERSION */ +#define _LESENSE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LESENSE_IPVERSION */ +#define _LESENSE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LESENSE_IPVERSION */ +#define _LESENSE_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LESENSE_IPVERSION */ +#define LESENSE_IPVERSION_IPVERSION_DEFAULT (_LESENSE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IPVERSION */ /* Bit fields for LESENSE EN */ -#define _LESENSE_EN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_EN */ -#define _LESENSE_EN_MASK 0x00000003UL /**< Mask for LESENSE_EN */ -#define LESENSE_EN_EN (0x1UL << 0) /**< Enable */ -#define _LESENSE_EN_EN_SHIFT 0 /**< Shift value for LESENSE_EN */ -#define _LESENSE_EN_EN_MASK 0x1UL /**< Bit mask for LESENSE_EN */ -#define _LESENSE_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EN */ -#define _LESENSE_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_EN */ -#define _LESENSE_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for LESENSE_EN */ -#define LESENSE_EN_EN_DEFAULT (_LESENSE_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_EN */ -#define LESENSE_EN_EN_DISABLE (_LESENSE_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_EN */ -#define LESENSE_EN_EN_ENABLE (_LESENSE_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for LESENSE_EN */ -#define LESENSE_EN_DISABLING (0x1UL << 1) /**< Disabling */ -#define _LESENSE_EN_DISABLING_SHIFT 1 /**< Shift value for LESENSE_DISABLING */ -#define _LESENSE_EN_DISABLING_MASK 0x2UL /**< Bit mask for LESENSE_DISABLING */ -#define _LESENSE_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EN */ -#define LESENSE_EN_DISABLING_DEFAULT (_LESENSE_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_EN */ +#define _LESENSE_EN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_EN */ +#define _LESENSE_EN_MASK 0x00000003UL /**< Mask for LESENSE_EN */ +#define LESENSE_EN_EN (0x1UL << 0) /**< Enable */ +#define _LESENSE_EN_EN_SHIFT 0 /**< Shift value for LESENSE_EN */ +#define _LESENSE_EN_EN_MASK 0x1UL /**< Bit mask for LESENSE_EN */ +#define _LESENSE_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EN */ +#define _LESENSE_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_EN */ +#define _LESENSE_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for LESENSE_EN */ +#define LESENSE_EN_EN_DEFAULT (_LESENSE_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_EN */ +#define LESENSE_EN_EN_DISABLE (_LESENSE_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_EN */ +#define LESENSE_EN_EN_ENABLE (_LESENSE_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for LESENSE_EN */ +#define LESENSE_EN_DISABLING (0x1UL << 1) /**< Disabling */ +#define _LESENSE_EN_DISABLING_SHIFT 1 /**< Shift value for LESENSE_DISABLING */ +#define _LESENSE_EN_DISABLING_MASK 0x2UL /**< Bit mask for LESENSE_DISABLING */ +#define _LESENSE_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EN */ +#define LESENSE_EN_DISABLING_DEFAULT (_LESENSE_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_EN */ /* Bit fields for LESENSE SWRST */ -#define _LESENSE_SWRST_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SWRST */ -#define _LESENSE_SWRST_MASK 0x00000003UL /**< Mask for LESENSE_SWRST */ -#define LESENSE_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ -#define _LESENSE_SWRST_SWRST_SHIFT 0 /**< Shift value for LESENSE_SWRST */ -#define _LESENSE_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LESENSE_SWRST */ -#define _LESENSE_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SWRST */ -#define LESENSE_SWRST_SWRST_DEFAULT (_LESENSE_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SWRST */ -#define LESENSE_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ -#define _LESENSE_SWRST_RESETTING_SHIFT 1 /**< Shift value for LESENSE_RESETTING */ -#define _LESENSE_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LESENSE_RESETTING */ -#define _LESENSE_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SWRST */ -#define LESENSE_SWRST_RESETTING_DEFAULT (_LESENSE_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_SWRST */ +#define _LESENSE_SWRST_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SWRST */ +#define _LESENSE_SWRST_MASK 0x00000003UL /**< Mask for LESENSE_SWRST */ +#define LESENSE_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _LESENSE_SWRST_SWRST_SHIFT 0 /**< Shift value for LESENSE_SWRST */ +#define _LESENSE_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LESENSE_SWRST */ +#define _LESENSE_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SWRST */ +#define LESENSE_SWRST_SWRST_DEFAULT (_LESENSE_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SWRST */ +#define LESENSE_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _LESENSE_SWRST_RESETTING_SHIFT 1 /**< Shift value for LESENSE_RESETTING */ +#define _LESENSE_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LESENSE_RESETTING */ +#define _LESENSE_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SWRST */ +#define LESENSE_SWRST_RESETTING_DEFAULT (_LESENSE_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_SWRST */ /* Bit fields for LESENSE CFG */ -#define _LESENSE_CFG_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CFG */ -#define _LESENSE_CFG_MASK 0x00020FEFUL /**< Mask for LESENSE_CFG */ -#define _LESENSE_CFG_SCANMODE_SHIFT 0 /**< Shift value for LESENSE_SCANMODE */ -#define _LESENSE_CFG_SCANMODE_MASK 0x3UL /**< Bit mask for LESENSE_SCANMODE */ -#define _LESENSE_CFG_SCANMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ -#define _LESENSE_CFG_SCANMODE_PERIODIC 0x00000000UL /**< Mode PERIODIC for LESENSE_CFG */ -#define _LESENSE_CFG_SCANMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LESENSE_CFG */ -#define _LESENSE_CFG_SCANMODE_PRS 0x00000002UL /**< Mode PRS for LESENSE_CFG */ -#define LESENSE_CFG_SCANMODE_DEFAULT (_LESENSE_CFG_SCANMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_SCANMODE_PERIODIC (_LESENSE_CFG_SCANMODE_PERIODIC << 0) /**< Shifted mode PERIODIC for LESENSE_CFG */ -#define LESENSE_CFG_SCANMODE_ONESHOT (_LESENSE_CFG_SCANMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LESENSE_CFG */ -#define LESENSE_CFG_SCANMODE_PRS (_LESENSE_CFG_SCANMODE_PRS << 0) /**< Shifted mode PRS for LESENSE_CFG */ -#define _LESENSE_CFG_SCANCONF_SHIFT 2 /**< Shift value for LESENSE_SCANCONF */ -#define _LESENSE_CFG_SCANCONF_MASK 0xCUL /**< Bit mask for LESENSE_SCANCONF */ -#define _LESENSE_CFG_SCANCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ -#define _LESENSE_CFG_SCANCONF_DIRMAP 0x00000000UL /**< Mode DIRMAP for LESENSE_CFG */ -#define _LESENSE_CFG_SCANCONF_INVMAP 0x00000001UL /**< Mode INVMAP for LESENSE_CFG */ -#define _LESENSE_CFG_SCANCONF_TOGGLE 0x00000002UL /**< Mode TOGGLE for LESENSE_CFG */ -#define _LESENSE_CFG_SCANCONF_DECDEF 0x00000003UL /**< Mode DECDEF for LESENSE_CFG */ -#define LESENSE_CFG_SCANCONF_DEFAULT (_LESENSE_CFG_SCANCONF_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_SCANCONF_DIRMAP (_LESENSE_CFG_SCANCONF_DIRMAP << 2) /**< Shifted mode DIRMAP for LESENSE_CFG */ -#define LESENSE_CFG_SCANCONF_INVMAP (_LESENSE_CFG_SCANCONF_INVMAP << 2) /**< Shifted mode INVMAP for LESENSE_CFG */ -#define LESENSE_CFG_SCANCONF_TOGGLE (_LESENSE_CFG_SCANCONF_TOGGLE << 2) /**< Shifted mode TOGGLE for LESENSE_CFG */ -#define LESENSE_CFG_SCANCONF_DECDEF (_LESENSE_CFG_SCANCONF_DECDEF << 2) /**< Shifted mode DECDEF for LESENSE_CFG */ -#define LESENSE_CFG_DUALSAMPLE (0x1UL << 5) /**< Enable dual sample mode */ -#define _LESENSE_CFG_DUALSAMPLE_SHIFT 5 /**< Shift value for LESENSE_DUALSAMPLE */ -#define _LESENSE_CFG_DUALSAMPLE_MASK 0x20UL /**< Bit mask for LESENSE_DUALSAMPLE */ -#define _LESENSE_CFG_DUALSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_DUALSAMPLE_DEFAULT (_LESENSE_CFG_DUALSAMPLE_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_STRSCANRES (0x1UL << 6) /**< Enable storing of SCANRES */ -#define _LESENSE_CFG_STRSCANRES_SHIFT 6 /**< Shift value for LESENSE_STRSCANRES */ -#define _LESENSE_CFG_STRSCANRES_MASK 0x40UL /**< Bit mask for LESENSE_STRSCANRES */ -#define _LESENSE_CFG_STRSCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_STRSCANRES_DEFAULT (_LESENSE_CFG_STRSCANRES_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_DMAWU (0x1UL << 7) /**< DMA wake-up from EM2 */ -#define _LESENSE_CFG_DMAWU_SHIFT 7 /**< Shift value for LESENSE_DMAWU */ -#define _LESENSE_CFG_DMAWU_MASK 0x80UL /**< Bit mask for LESENSE_DMAWU */ -#define _LESENSE_CFG_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ -#define _LESENSE_CFG_DMAWU_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CFG */ -#define _LESENSE_CFG_DMAWU_ENABLE 0x00000001UL /**< Mode ENABLE for LESENSE_CFG */ -#define LESENSE_CFG_DMAWU_DEFAULT (_LESENSE_CFG_DMAWU_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_DMAWU_DISABLE (_LESENSE_CFG_DMAWU_DISABLE << 7) /**< Shifted mode DISABLE for LESENSE_CFG */ -#define LESENSE_CFG_DMAWU_ENABLE (_LESENSE_CFG_DMAWU_ENABLE << 7) /**< Shifted mode ENABLE for LESENSE_CFG */ -#define _LESENSE_CFG_RESFIDL_SHIFT 8 /**< Shift value for LESENSE_RESFIDL */ -#define _LESENSE_CFG_RESFIDL_MASK 0xF00UL /**< Bit mask for LESENSE_RESFIDL */ -#define _LESENSE_CFG_RESFIDL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_RESFIDL_DEFAULT (_LESENSE_CFG_RESFIDL_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_DEBUGRUN (0x1UL << 17) /**< Debug Mode Run Enable */ -#define _LESENSE_CFG_DEBUGRUN_SHIFT 17 /**< Shift value for LESENSE_DEBUGRUN */ -#define _LESENSE_CFG_DEBUGRUN_MASK 0x20000UL /**< Bit mask for LESENSE_DEBUGRUN */ -#define _LESENSE_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ -#define _LESENSE_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for LESENSE_CFG */ -#define _LESENSE_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for LESENSE_CFG */ -#define LESENSE_CFG_DEBUGRUN_DEFAULT (_LESENSE_CFG_DEBUGRUN_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CFG */ -#define LESENSE_CFG_DEBUGRUN_X0 (_LESENSE_CFG_DEBUGRUN_X0 << 17) /**< Shifted mode X0 for LESENSE_CFG */ -#define LESENSE_CFG_DEBUGRUN_X1 (_LESENSE_CFG_DEBUGRUN_X1 << 17) /**< Shifted mode X1 for LESENSE_CFG */ +#define _LESENSE_CFG_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CFG */ +#define _LESENSE_CFG_MASK 0x00020FEFUL /**< Mask for LESENSE_CFG */ +#define _LESENSE_CFG_SCANMODE_SHIFT 0 /**< Shift value for LESENSE_SCANMODE */ +#define _LESENSE_CFG_SCANMODE_MASK 0x3UL /**< Bit mask for LESENSE_SCANMODE */ +#define _LESENSE_CFG_SCANMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define _LESENSE_CFG_SCANMODE_PERIODIC 0x00000000UL /**< Mode PERIODIC for LESENSE_CFG */ +#define _LESENSE_CFG_SCANMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LESENSE_CFG */ +#define _LESENSE_CFG_SCANMODE_PRS 0x00000002UL /**< Mode PRS for LESENSE_CFG */ +#define LESENSE_CFG_SCANMODE_DEFAULT (_LESENSE_CFG_SCANMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_SCANMODE_PERIODIC (_LESENSE_CFG_SCANMODE_PERIODIC << 0) /**< Shifted mode PERIODIC for LESENSE_CFG */ +#define LESENSE_CFG_SCANMODE_ONESHOT (_LESENSE_CFG_SCANMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LESENSE_CFG */ +#define LESENSE_CFG_SCANMODE_PRS (_LESENSE_CFG_SCANMODE_PRS << 0) /**< Shifted mode PRS for LESENSE_CFG */ +#define _LESENSE_CFG_SCANCONF_SHIFT 2 /**< Shift value for LESENSE_SCANCONF */ +#define _LESENSE_CFG_SCANCONF_MASK 0xCUL /**< Bit mask for LESENSE_SCANCONF */ +#define _LESENSE_CFG_SCANCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define _LESENSE_CFG_SCANCONF_DIRMAP 0x00000000UL /**< Mode DIRMAP for LESENSE_CFG */ +#define _LESENSE_CFG_SCANCONF_INVMAP 0x00000001UL /**< Mode INVMAP for LESENSE_CFG */ +#define _LESENSE_CFG_SCANCONF_TOGGLE 0x00000002UL /**< Mode TOGGLE for LESENSE_CFG */ +#define _LESENSE_CFG_SCANCONF_DECDEF 0x00000003UL /**< Mode DECDEF for LESENSE_CFG */ +#define LESENSE_CFG_SCANCONF_DEFAULT (_LESENSE_CFG_SCANCONF_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_SCANCONF_DIRMAP (_LESENSE_CFG_SCANCONF_DIRMAP << 2) /**< Shifted mode DIRMAP for LESENSE_CFG */ +#define LESENSE_CFG_SCANCONF_INVMAP (_LESENSE_CFG_SCANCONF_INVMAP << 2) /**< Shifted mode INVMAP for LESENSE_CFG */ +#define LESENSE_CFG_SCANCONF_TOGGLE (_LESENSE_CFG_SCANCONF_TOGGLE << 2) /**< Shifted mode TOGGLE for LESENSE_CFG */ +#define LESENSE_CFG_SCANCONF_DECDEF (_LESENSE_CFG_SCANCONF_DECDEF << 2) /**< Shifted mode DECDEF for LESENSE_CFG */ +#define LESENSE_CFG_DUALSAMPLE (0x1UL << 5) /**< Enable dual sample mode */ +#define _LESENSE_CFG_DUALSAMPLE_SHIFT 5 /**< Shift value for LESENSE_DUALSAMPLE */ +#define _LESENSE_CFG_DUALSAMPLE_MASK 0x20UL /**< Bit mask for LESENSE_DUALSAMPLE */ +#define _LESENSE_CFG_DUALSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_DUALSAMPLE_DEFAULT (_LESENSE_CFG_DUALSAMPLE_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_STRSCANRES (0x1UL << 6) /**< Enable storing of SCANRES */ +#define _LESENSE_CFG_STRSCANRES_SHIFT 6 /**< Shift value for LESENSE_STRSCANRES */ +#define _LESENSE_CFG_STRSCANRES_MASK 0x40UL /**< Bit mask for LESENSE_STRSCANRES */ +#define _LESENSE_CFG_STRSCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_STRSCANRES_DEFAULT (_LESENSE_CFG_STRSCANRES_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_DMAWU (0x1UL << 7) /**< DMA wake-up from EM2 */ +#define _LESENSE_CFG_DMAWU_SHIFT 7 /**< Shift value for LESENSE_DMAWU */ +#define _LESENSE_CFG_DMAWU_MASK 0x80UL /**< Bit mask for LESENSE_DMAWU */ +#define _LESENSE_CFG_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define _LESENSE_CFG_DMAWU_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CFG */ +#define _LESENSE_CFG_DMAWU_ENABLE 0x00000001UL /**< Mode ENABLE for LESENSE_CFG */ +#define LESENSE_CFG_DMAWU_DEFAULT (_LESENSE_CFG_DMAWU_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_DMAWU_DISABLE (_LESENSE_CFG_DMAWU_DISABLE << 7) /**< Shifted mode DISABLE for LESENSE_CFG */ +#define LESENSE_CFG_DMAWU_ENABLE (_LESENSE_CFG_DMAWU_ENABLE << 7) /**< Shifted mode ENABLE for LESENSE_CFG */ +#define _LESENSE_CFG_RESFIDL_SHIFT 8 /**< Shift value for LESENSE_RESFIDL */ +#define _LESENSE_CFG_RESFIDL_MASK 0xF00UL /**< Bit mask for LESENSE_RESFIDL */ +#define _LESENSE_CFG_RESFIDL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_RESFIDL_DEFAULT (_LESENSE_CFG_RESFIDL_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_DEBUGRUN (0x1UL << 17) /**< Debug Mode Run Enable */ +#define _LESENSE_CFG_DEBUGRUN_SHIFT 17 /**< Shift value for LESENSE_DEBUGRUN */ +#define _LESENSE_CFG_DEBUGRUN_MASK 0x20000UL /**< Bit mask for LESENSE_DEBUGRUN */ +#define _LESENSE_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define _LESENSE_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for LESENSE_CFG */ +#define _LESENSE_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for LESENSE_CFG */ +#define LESENSE_CFG_DEBUGRUN_DEFAULT (_LESENSE_CFG_DEBUGRUN_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_DEBUGRUN_X0 (_LESENSE_CFG_DEBUGRUN_X0 << 17) /**< Shifted mode X0 for LESENSE_CFG */ +#define LESENSE_CFG_DEBUGRUN_X1 (_LESENSE_CFG_DEBUGRUN_X1 << 17) /**< Shifted mode X1 for LESENSE_CFG */ /* Bit fields for LESENSE TIMCTRL */ -#define _LESENSE_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_MASK 0x10CFF773UL /**< Mask for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_AUXPRESC_SHIFT 0 /**< Shift value for LESENSE_AUXPRESC */ -#define _LESENSE_TIMCTRL_AUXPRESC_MASK 0x3UL /**< Bit mask for LESENSE_AUXPRESC */ -#define _LESENSE_TIMCTRL_AUXPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_AUXPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_AUXPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_AUXPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_AUXPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXPRESC_DEFAULT (_LESENSE_TIMCTRL_AUXPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXPRESC_DIV1 (_LESENSE_TIMCTRL_AUXPRESC_DIV1 << 0) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXPRESC_DIV2 (_LESENSE_TIMCTRL_AUXPRESC_DIV2 << 0) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXPRESC_DIV4 (_LESENSE_TIMCTRL_AUXPRESC_DIV4 << 0) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXPRESC_DIV8 (_LESENSE_TIMCTRL_AUXPRESC_DIV8 << 0) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_SHIFT 4 /**< Shift value for LESENSE_LFPRESC */ -#define _LESENSE_TIMCTRL_LFPRESC_MASK 0x70UL /**< Bit mask for LESENSE_LFPRESC */ -#define _LESENSE_TIMCTRL_LFPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_LFPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DEFAULT (_LESENSE_TIMCTRL_LFPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DIV1 (_LESENSE_TIMCTRL_LFPRESC_DIV1 << 4) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DIV2 (_LESENSE_TIMCTRL_LFPRESC_DIV2 << 4) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DIV4 (_LESENSE_TIMCTRL_LFPRESC_DIV4 << 4) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DIV8 (_LESENSE_TIMCTRL_LFPRESC_DIV8 << 4) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DIV16 (_LESENSE_TIMCTRL_LFPRESC_DIV16 << 4) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DIV32 (_LESENSE_TIMCTRL_LFPRESC_DIV32 << 4) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DIV64 (_LESENSE_TIMCTRL_LFPRESC_DIV64 << 4) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_LFPRESC_DIV128 (_LESENSE_TIMCTRL_LFPRESC_DIV128 << 4) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_SHIFT 8 /**< Shift value for LESENSE_PCPRESC */ -#define _LESENSE_TIMCTRL_PCPRESC_MASK 0x700UL /**< Bit mask for LESENSE_PCPRESC */ -#define _LESENSE_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DEFAULT (_LESENSE_TIMCTRL_PCPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DIV1 (_LESENSE_TIMCTRL_PCPRESC_DIV1 << 8) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DIV2 (_LESENSE_TIMCTRL_PCPRESC_DIV2 << 8) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DIV4 (_LESENSE_TIMCTRL_PCPRESC_DIV4 << 8) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DIV8 (_LESENSE_TIMCTRL_PCPRESC_DIV8 << 8) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DIV16 (_LESENSE_TIMCTRL_PCPRESC_DIV16 << 8) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DIV32 (_LESENSE_TIMCTRL_PCPRESC_DIV32 << 8) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DIV64 (_LESENSE_TIMCTRL_PCPRESC_DIV64 << 8) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCPRESC_DIV128 (_LESENSE_TIMCTRL_PCPRESC_DIV128 << 8) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_PCTOP_SHIFT 12 /**< Shift value for LESENSE_PCTOP */ -#define _LESENSE_TIMCTRL_PCTOP_MASK 0xFF000UL /**< Bit mask for LESENSE_PCTOP */ -#define _LESENSE_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_PCTOP_DEFAULT (_LESENSE_TIMCTRL_PCTOP_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_STARTDLY_SHIFT 22 /**< Shift value for LESENSE_STARTDLY */ -#define _LESENSE_TIMCTRL_STARTDLY_MASK 0xC00000UL /**< Bit mask for LESENSE_STARTDLY */ -#define _LESENSE_TIMCTRL_STARTDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_STARTDLY_DEFAULT (_LESENSE_TIMCTRL_STARTDLY_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXSTARTUP (0x1UL << 28) /**< AUX startup config */ -#define _LESENSE_TIMCTRL_AUXSTARTUP_SHIFT 28 /**< Shift value for LESENSE_AUXSTARTUP */ -#define _LESENSE_TIMCTRL_AUXSTARTUP_MASK 0x10000000UL /**< Bit mask for LESENSE_AUXSTARTUP */ -#define _LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND 0x00000000UL /**< Mode PREDEMAND for LESENSE_TIMCTRL */ -#define _LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND 0x00000001UL /**< Mode ONDEMAND for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT (_LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND << 28) /**< Shifted mode PREDEMAND for LESENSE_TIMCTRL */ -#define LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND << 28) /**< Shifted mode ONDEMAND for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_MASK 0x10CFF773UL /**< Mask for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_SHIFT 0 /**< Shift value for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_MASK 0x3UL /**< Bit mask for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DEFAULT (_LESENSE_TIMCTRL_AUXPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV1 (_LESENSE_TIMCTRL_AUXPRESC_DIV1 << 0) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV2 (_LESENSE_TIMCTRL_AUXPRESC_DIV2 << 0) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV4 (_LESENSE_TIMCTRL_AUXPRESC_DIV4 << 0) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV8 (_LESENSE_TIMCTRL_AUXPRESC_DIV8 << 0) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_SHIFT 4 /**< Shift value for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_MASK 0x70UL /**< Bit mask for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DEFAULT (_LESENSE_TIMCTRL_LFPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV1 (_LESENSE_TIMCTRL_LFPRESC_DIV1 << 4) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV2 (_LESENSE_TIMCTRL_LFPRESC_DIV2 << 4) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV4 (_LESENSE_TIMCTRL_LFPRESC_DIV4 << 4) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV8 (_LESENSE_TIMCTRL_LFPRESC_DIV8 << 4) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV16 (_LESENSE_TIMCTRL_LFPRESC_DIV16 << 4) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV32 (_LESENSE_TIMCTRL_LFPRESC_DIV32 << 4) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV64 (_LESENSE_TIMCTRL_LFPRESC_DIV64 << 4) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV128 (_LESENSE_TIMCTRL_LFPRESC_DIV128 << 4) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_SHIFT 8 /**< Shift value for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_MASK 0x700UL /**< Bit mask for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DEFAULT (_LESENSE_TIMCTRL_PCPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV1 (_LESENSE_TIMCTRL_PCPRESC_DIV1 << 8) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV2 (_LESENSE_TIMCTRL_PCPRESC_DIV2 << 8) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV4 (_LESENSE_TIMCTRL_PCPRESC_DIV4 << 8) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV8 (_LESENSE_TIMCTRL_PCPRESC_DIV8 << 8) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV16 (_LESENSE_TIMCTRL_PCPRESC_DIV16 << 8) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV32 (_LESENSE_TIMCTRL_PCPRESC_DIV32 << 8) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV64 (_LESENSE_TIMCTRL_PCPRESC_DIV64 << 8) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV128 (_LESENSE_TIMCTRL_PCPRESC_DIV128 << 8) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCTOP_SHIFT 12 /**< Shift value for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_MASK 0xFF000UL /**< Bit mask for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCTOP_DEFAULT (_LESENSE_TIMCTRL_PCTOP_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_STARTDLY_SHIFT 22 /**< Shift value for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_MASK 0xC00000UL /**< Bit mask for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_STARTDLY_DEFAULT (_LESENSE_TIMCTRL_STARTDLY_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP (0x1UL << 28) /**< AUX startup config */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_SHIFT 28 /**< Shift value for LESENSE_AUXSTARTUP */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_MASK 0x10000000UL /**< Bit mask for LESENSE_AUXSTARTUP */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND 0x00000000UL /**< Mode PREDEMAND for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND 0x00000001UL /**< Mode ONDEMAND for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT (_LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND << 28) /**< Shifted mode PREDEMAND for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND << 28) /**< Shifted mode ONDEMAND for LESENSE_TIMCTRL */ /* Bit fields for LESENSE PERCTRL */ -#define _LESENSE_PERCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_MASK 0x03500144UL /**< Mask for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACCH0DATA (0x1UL << 2) /**< DAC CH0 data selection. */ -#define _LESENSE_PERCTRL_DACCH0DATA_SHIFT 2 /**< Shift value for LESENSE_DACCH0DATA */ -#define _LESENSE_PERCTRL_DACCH0DATA_MASK 0x4UL /**< Bit mask for LESENSE_DACCH0DATA */ -#define _LESENSE_PERCTRL_DACCH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_DACCH0DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_DACCH0DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACCH0DATA_DEFAULT (_LESENSE_PERCTRL_DACCH0DATA_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACCH0DATA_DACDATA (_LESENSE_PERCTRL_DACCH0DATA_DACDATA << 2) /**< Shifted mode DACDATA for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACCH0DATA_THRES (_LESENSE_PERCTRL_DACCH0DATA_THRES << 2) /**< Shifted mode THRES for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACSTARTUP (0x1UL << 6) /**< DAC startup configuration */ -#define _LESENSE_PERCTRL_DACSTARTUP_SHIFT 6 /**< Shift value for LESENSE_DACSTARTUP */ -#define _LESENSE_PERCTRL_DACSTARTUP_MASK 0x40UL /**< Bit mask for LESENSE_DACSTARTUP */ -#define _LESENSE_PERCTRL_DACSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE 0x00000000UL /**< Mode FULLCYCLE for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE 0x00000001UL /**< Mode HALFCYCLE for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACSTARTUP_DEFAULT (_LESENSE_PERCTRL_DACSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE (_LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE << 6) /**< Shifted mode FULLCYCLE for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE (_LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE << 6) /**< Shifted mode HALFCYCLE for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACCONVTRIG (0x1UL << 8) /**< DAC conversion trigger configuration */ -#define _LESENSE_PERCTRL_DACCONVTRIG_SHIFT 8 /**< Shift value for LESENSE_DACCONVTRIG */ -#define _LESENSE_PERCTRL_DACCONVTRIG_MASK 0x100UL /**< Bit mask for LESENSE_DACCONVTRIG */ -#define _LESENSE_PERCTRL_DACCONVTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART 0x00000000UL /**< Mode CHANNELSTART for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_DACCONVTRIG_SCANSTART 0x00000001UL /**< Mode SCANSTART for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACCONVTRIG_DEFAULT (_LESENSE_PERCTRL_DACCONVTRIG_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART (_LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART << 8) /**< Shifted mode CHANNELSTART for LESENSE_PERCTRL*/ -#define LESENSE_PERCTRL_DACCONVTRIG_SCANSTART (_LESENSE_PERCTRL_DACCONVTRIG_SCANSTART << 8) /**< Shifted mode SCANSTART for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP0MODE (0x1UL << 20) /**< ACMP0 mode */ -#define _LESENSE_PERCTRL_ACMP0MODE_SHIFT 20 /**< Shift value for LESENSE_ACMP0MODE */ -#define _LESENSE_PERCTRL_ACMP0MODE_MASK 0x100000UL /**< Bit mask for LESENSE_ACMP0MODE */ -#define _LESENSE_PERCTRL_ACMP0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_ACMP0MODE_MUX 0x00000000UL /**< Mode MUX for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_ACMP0MODE_MUXTHRES 0x00000001UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP0MODE_DEFAULT (_LESENSE_PERCTRL_ACMP0MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP0MODE_MUX (_LESENSE_PERCTRL_ACMP0MODE_MUX << 20) /**< Shifted mode MUX for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP0MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP0MODE_MUXTHRES << 20) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP1MODE (0x1UL << 22) /**< ACMP1 mode */ -#define _LESENSE_PERCTRL_ACMP1MODE_SHIFT 22 /**< Shift value for LESENSE_ACMP1MODE */ -#define _LESENSE_PERCTRL_ACMP1MODE_MASK 0x400000UL /**< Bit mask for LESENSE_ACMP1MODE */ -#define _LESENSE_PERCTRL_ACMP1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_ACMP1MODE_MUX 0x00000000UL /**< Mode MUX for LESENSE_PERCTRL */ -#define _LESENSE_PERCTRL_ACMP1MODE_MUXTHRES 0x00000001UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP1MODE_DEFAULT (_LESENSE_PERCTRL_ACMP1MODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP1MODE_MUX (_LESENSE_PERCTRL_ACMP1MODE_MUX << 22) /**< Shifted mode MUX for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP1MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP1MODE_MUXTHRES << 22) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP0INV (0x1UL << 24) /**< Invert analog comparator 0 output */ -#define _LESENSE_PERCTRL_ACMP0INV_SHIFT 24 /**< Shift value for LESENSE_ACMP0INV */ -#define _LESENSE_PERCTRL_ACMP0INV_MASK 0x1000000UL /**< Bit mask for LESENSE_ACMP0INV */ -#define _LESENSE_PERCTRL_ACMP0INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP0INV_DEFAULT (_LESENSE_PERCTRL_ACMP0INV_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP1INV (0x1UL << 25) /**< Invert analog comparator 1 output */ -#define _LESENSE_PERCTRL_ACMP1INV_SHIFT 25 /**< Shift value for LESENSE_ACMP1INV */ -#define _LESENSE_PERCTRL_ACMP1INV_MASK 0x2000000UL /**< Bit mask for LESENSE_ACMP1INV */ -#define _LESENSE_PERCTRL_ACMP1INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ -#define LESENSE_PERCTRL_ACMP1INV_DEFAULT (_LESENSE_PERCTRL_ACMP1INV_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_MASK 0x03500144UL /**< Mask for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA (0x1UL << 2) /**< DAC CH0 data selection. */ +#define _LESENSE_PERCTRL_DACCH0DATA_SHIFT 2 /**< Shift value for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_MASK 0x4UL /**< Bit mask for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DEFAULT (_LESENSE_PERCTRL_DACCH0DATA_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DACDATA (_LESENSE_PERCTRL_DACCH0DATA_DACDATA << 2) /**< Shifted mode DACDATA for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_THRES (_LESENSE_PERCTRL_DACCH0DATA_THRES << 2) /**< Shifted mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP (0x1UL << 6) /**< DAC startup configuration */ +#define _LESENSE_PERCTRL_DACSTARTUP_SHIFT 6 /**< Shift value for LESENSE_DACSTARTUP */ +#define _LESENSE_PERCTRL_DACSTARTUP_MASK 0x40UL /**< Bit mask for LESENSE_DACSTARTUP */ +#define _LESENSE_PERCTRL_DACSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE 0x00000000UL /**< Mode FULLCYCLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE 0x00000001UL /**< Mode HALFCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_DEFAULT (_LESENSE_PERCTRL_DACSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE (_LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE << 6) /**< Shifted mode FULLCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE (_LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE << 6) /**< Shifted mode HALFCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG (0x1UL << 8) /**< DAC conversion trigger configuration */ +#define _LESENSE_PERCTRL_DACCONVTRIG_SHIFT 8 /**< Shift value for LESENSE_DACCONVTRIG */ +#define _LESENSE_PERCTRL_DACCONVTRIG_MASK 0x100UL /**< Bit mask for LESENSE_DACCONVTRIG */ +#define _LESENSE_PERCTRL_DACCONVTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART 0x00000000UL /**< Mode CHANNELSTART for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCONVTRIG_SCANSTART 0x00000001UL /**< Mode SCANSTART for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_DEFAULT (_LESENSE_PERCTRL_DACCONVTRIG_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART (_LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART << 8) /**< Shifted mode CHANNELSTART for LESENSE_PERCTRL*/ +#define LESENSE_PERCTRL_DACCONVTRIG_SCANSTART (_LESENSE_PERCTRL_DACCONVTRIG_SCANSTART << 8) /**< Shifted mode SCANSTART for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE (0x1UL << 20) /**< ACMP0 mode */ +#define _LESENSE_PERCTRL_ACMP0MODE_SHIFT 20 /**< Shift value for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_MASK 0x100000UL /**< Bit mask for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUX 0x00000000UL /**< Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUXTHRES 0x00000001UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_DEFAULT (_LESENSE_PERCTRL_ACMP0MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUX (_LESENSE_PERCTRL_ACMP0MODE_MUX << 20) /**< Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP0MODE_MUXTHRES << 20) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE (0x1UL << 22) /**< ACMP1 mode */ +#define _LESENSE_PERCTRL_ACMP1MODE_SHIFT 22 /**< Shift value for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_MASK 0x400000UL /**< Bit mask for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUX 0x00000000UL /**< Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUXTHRES 0x00000001UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_DEFAULT (_LESENSE_PERCTRL_ACMP1MODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUX (_LESENSE_PERCTRL_ACMP1MODE_MUX << 22) /**< Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP1MODE_MUXTHRES << 22) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0INV (0x1UL << 24) /**< Invert analog comparator 0 output */ +#define _LESENSE_PERCTRL_ACMP0INV_SHIFT 24 /**< Shift value for LESENSE_ACMP0INV */ +#define _LESENSE_PERCTRL_ACMP0INV_MASK 0x1000000UL /**< Bit mask for LESENSE_ACMP0INV */ +#define _LESENSE_PERCTRL_ACMP0INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0INV_DEFAULT (_LESENSE_PERCTRL_ACMP0INV_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1INV (0x1UL << 25) /**< Invert analog comparator 1 output */ +#define _LESENSE_PERCTRL_ACMP1INV_SHIFT 25 /**< Shift value for LESENSE_ACMP1INV */ +#define _LESENSE_PERCTRL_ACMP1INV_MASK 0x2000000UL /**< Bit mask for LESENSE_ACMP1INV */ +#define _LESENSE_PERCTRL_ACMP1INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1INV_DEFAULT (_LESENSE_PERCTRL_ACMP1INV_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ /* Bit fields for LESENSE DECCTRL */ -#define _LESENSE_DECCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECCTRL */ -#define _LESENSE_DECCTRL_MASK 0x000000FDUL /**< Mask for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_DECDIS (0x1UL << 0) /**< Disable the decoder */ -#define _LESENSE_DECCTRL_DECDIS_SHIFT 0 /**< Shift value for LESENSE_DECDIS */ -#define _LESENSE_DECCTRL_DECDIS_MASK 0x1UL /**< Bit mask for LESENSE_DECDIS */ -#define _LESENSE_DECCTRL_DECDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_DECDIS_DEFAULT (_LESENSE_DECCTRL_DECDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_INTMAP (0x1UL << 2) /**< Enable decoder to channel interrupt map */ -#define _LESENSE_DECCTRL_INTMAP_SHIFT 2 /**< Shift value for LESENSE_INTMAP */ -#define _LESENSE_DECCTRL_INTMAP_MASK 0x4UL /**< Bit mask for LESENSE_INTMAP */ -#define _LESENSE_DECCTRL_INTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_INTMAP_DEFAULT (_LESENSE_DECCTRL_INTMAP_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_HYSTPRS0 (0x1UL << 3) /**< Enable decoder hysteresis on PRS0 output */ -#define _LESENSE_DECCTRL_HYSTPRS0_SHIFT 3 /**< Shift value for LESENSE_HYSTPRS0 */ -#define _LESENSE_DECCTRL_HYSTPRS0_MASK 0x8UL /**< Bit mask for LESENSE_HYSTPRS0 */ -#define _LESENSE_DECCTRL_HYSTPRS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_HYSTPRS0_DEFAULT (_LESENSE_DECCTRL_HYSTPRS0_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_HYSTPRS1 (0x1UL << 4) /**< Enable decoder hysteresis on PRS1 output */ -#define _LESENSE_DECCTRL_HYSTPRS1_SHIFT 4 /**< Shift value for LESENSE_HYSTPRS1 */ -#define _LESENSE_DECCTRL_HYSTPRS1_MASK 0x10UL /**< Bit mask for LESENSE_HYSTPRS1 */ -#define _LESENSE_DECCTRL_HYSTPRS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_HYSTPRS1_DEFAULT (_LESENSE_DECCTRL_HYSTPRS1_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_HYSTPRS2 (0x1UL << 5) /**< Enable decoder hysteresis on PRS2 output */ -#define _LESENSE_DECCTRL_HYSTPRS2_SHIFT 5 /**< Shift value for LESENSE_HYSTPRS2 */ -#define _LESENSE_DECCTRL_HYSTPRS2_MASK 0x20UL /**< Bit mask for LESENSE_HYSTPRS2 */ -#define _LESENSE_DECCTRL_HYSTPRS2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_HYSTPRS2_DEFAULT (_LESENSE_DECCTRL_HYSTPRS2_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_HYSTIRQ (0x1UL << 6) /**< Enable decoder hysteresis on interrupt r */ -#define _LESENSE_DECCTRL_HYSTIRQ_SHIFT 6 /**< Shift value for LESENSE_HYSTIRQ */ -#define _LESENSE_DECCTRL_HYSTIRQ_MASK 0x40UL /**< Bit mask for LESENSE_HYSTIRQ */ -#define _LESENSE_DECCTRL_HYSTIRQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_HYSTIRQ_DEFAULT (_LESENSE_DECCTRL_HYSTIRQ_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_PRSCNT (0x1UL << 7) /**< Enable count mode on decoder PRS channel */ -#define _LESENSE_DECCTRL_PRSCNT_SHIFT 7 /**< Shift value for LESENSE_PRSCNT */ -#define _LESENSE_DECCTRL_PRSCNT_MASK 0x80UL /**< Bit mask for LESENSE_PRSCNT */ -#define _LESENSE_DECCTRL_PRSCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ -#define LESENSE_DECCTRL_PRSCNT_DEFAULT (_LESENSE_DECCTRL_PRSCNT_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_MASK 0x000000FDUL /**< Mask for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_DECDIS (0x1UL << 0) /**< Disable the decoder */ +#define _LESENSE_DECCTRL_DECDIS_SHIFT 0 /**< Shift value for LESENSE_DECDIS */ +#define _LESENSE_DECCTRL_DECDIS_MASK 0x1UL /**< Bit mask for LESENSE_DECDIS */ +#define _LESENSE_DECCTRL_DECDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_DECDIS_DEFAULT (_LESENSE_DECCTRL_DECDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP (0x1UL << 2) /**< Enable decoder to channel interrupt map */ +#define _LESENSE_DECCTRL_INTMAP_SHIFT 2 /**< Shift value for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_MASK 0x4UL /**< Bit mask for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP_DEFAULT (_LESENSE_DECCTRL_INTMAP_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0 (0x1UL << 3) /**< Enable decoder hysteresis on PRS0 output */ +#define _LESENSE_DECCTRL_HYSTPRS0_SHIFT 3 /**< Shift value for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_MASK 0x8UL /**< Bit mask for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0_DEFAULT (_LESENSE_DECCTRL_HYSTPRS0_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1 (0x1UL << 4) /**< Enable decoder hysteresis on PRS1 output */ +#define _LESENSE_DECCTRL_HYSTPRS1_SHIFT 4 /**< Shift value for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_MASK 0x10UL /**< Bit mask for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1_DEFAULT (_LESENSE_DECCTRL_HYSTPRS1_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2 (0x1UL << 5) /**< Enable decoder hysteresis on PRS2 output */ +#define _LESENSE_DECCTRL_HYSTPRS2_SHIFT 5 /**< Shift value for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_MASK 0x20UL /**< Bit mask for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2_DEFAULT (_LESENSE_DECCTRL_HYSTPRS2_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ (0x1UL << 6) /**< Enable decoder hysteresis on interrupt r */ +#define _LESENSE_DECCTRL_HYSTIRQ_SHIFT 6 /**< Shift value for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_MASK 0x40UL /**< Bit mask for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ_DEFAULT (_LESENSE_DECCTRL_HYSTIRQ_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT (0x1UL << 7) /**< Enable count mode on decoder PRS channel */ +#define _LESENSE_DECCTRL_PRSCNT_SHIFT 7 /**< Shift value for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_MASK 0x80UL /**< Bit mask for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT_DEFAULT (_LESENSE_DECCTRL_PRSCNT_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ /* Bit fields for LESENSE EVALCTRL */ -#define _LESENSE_EVALCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_EVALCTRL */ -#define _LESENSE_EVALCTRL_MASK 0x0000FFFFUL /**< Mask for LESENSE_EVALCTRL */ -#define _LESENSE_EVALCTRL_WINSIZE_SHIFT 0 /**< Shift value for LESENSE_WINSIZE */ -#define _LESENSE_EVALCTRL_WINSIZE_MASK 0xFFFFUL /**< Bit mask for LESENSE_WINSIZE */ -#define _LESENSE_EVALCTRL_WINSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EVALCTRL */ -#define LESENSE_EVALCTRL_WINSIZE_DEFAULT (_LESENSE_EVALCTRL_WINSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_MASK 0x0000FFFFUL /**< Mask for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_WINSIZE_SHIFT 0 /**< Shift value for LESENSE_WINSIZE */ +#define _LESENSE_EVALCTRL_WINSIZE_MASK 0xFFFFUL /**< Bit mask for LESENSE_WINSIZE */ +#define _LESENSE_EVALCTRL_WINSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EVALCTRL */ +#define LESENSE_EVALCTRL_WINSIZE_DEFAULT (_LESENSE_EVALCTRL_WINSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_EVALCTRL */ /* Bit fields for LESENSE PRSCTRL */ -#define _LESENSE_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PRSCTRL */ -#define _LESENSE_PRSCTRL_MASK 0x00011F1FUL /**< Mask for LESENSE_PRSCTRL */ -#define _LESENSE_PRSCTRL_DECCMPVAL_SHIFT 0 /**< Shift value for LESENSE_DECCMPVAL */ -#define _LESENSE_PRSCTRL_DECCMPVAL_MASK 0x1FUL /**< Bit mask for LESENSE_DECCMPVAL */ -#define _LESENSE_PRSCTRL_DECCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ -#define LESENSE_PRSCTRL_DECCMPVAL_DEFAULT (_LESENSE_PRSCTRL_DECCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ -#define _LESENSE_PRSCTRL_DECCMPMASK_SHIFT 8 /**< Shift value for LESENSE_DECCMPMASK */ -#define _LESENSE_PRSCTRL_DECCMPMASK_MASK 0x1F00UL /**< Bit mask for LESENSE_DECCMPMASK */ -#define _LESENSE_PRSCTRL_DECCMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ -#define LESENSE_PRSCTRL_DECCMPMASK_DEFAULT (_LESENSE_PRSCTRL_DECCMPMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ -#define LESENSE_PRSCTRL_DECCMPEN (0x1UL << 16) /**< Enable PRS output DECCMP */ -#define _LESENSE_PRSCTRL_DECCMPEN_SHIFT 16 /**< Shift value for LESENSE_DECCMPEN */ -#define _LESENSE_PRSCTRL_DECCMPEN_MASK 0x10000UL /**< Bit mask for LESENSE_DECCMPEN */ -#define _LESENSE_PRSCTRL_DECCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ -#define LESENSE_PRSCTRL_DECCMPEN_DEFAULT (_LESENSE_PRSCTRL_DECCMPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_MASK 0x00011F1FUL /**< Mask for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_SHIFT 0 /**< Shift value for LESENSE_DECCMPVAL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_MASK 0x1FUL /**< Bit mask for LESENSE_DECCMPVAL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPVAL_DEFAULT (_LESENSE_PRSCTRL_DECCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_DECCMPMASK_SHIFT 8 /**< Shift value for LESENSE_DECCMPMASK */ +#define _LESENSE_PRSCTRL_DECCMPMASK_MASK 0x1F00UL /**< Bit mask for LESENSE_DECCMPMASK */ +#define _LESENSE_PRSCTRL_DECCMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPMASK_DEFAULT (_LESENSE_PRSCTRL_DECCMPMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPEN (0x1UL << 16) /**< Enable PRS output DECCMP */ +#define _LESENSE_PRSCTRL_DECCMPEN_SHIFT 16 /**< Shift value for LESENSE_DECCMPEN */ +#define _LESENSE_PRSCTRL_DECCMPEN_MASK 0x10000UL /**< Bit mask for LESENSE_DECCMPEN */ +#define _LESENSE_PRSCTRL_DECCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPEN_DEFAULT (_LESENSE_PRSCTRL_DECCMPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ /* Bit fields for LESENSE CMD */ -#define _LESENSE_CMD_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CMD */ -#define _LESENSE_CMD_MASK 0x0000000FUL /**< Mask for LESENSE_CMD */ -#define LESENSE_CMD_START (0x1UL << 0) /**< Start scanning of sensors. */ -#define _LESENSE_CMD_START_SHIFT 0 /**< Shift value for LESENSE_START */ -#define _LESENSE_CMD_START_MASK 0x1UL /**< Bit mask for LESENSE_START */ -#define _LESENSE_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ -#define LESENSE_CMD_START_DEFAULT (_LESENSE_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CMD */ -#define LESENSE_CMD_STOP (0x1UL << 1) /**< Stop scanning of sensors */ -#define _LESENSE_CMD_STOP_SHIFT 1 /**< Shift value for LESENSE_STOP */ -#define _LESENSE_CMD_STOP_MASK 0x2UL /**< Bit mask for LESENSE_STOP */ -#define _LESENSE_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ -#define LESENSE_CMD_STOP_DEFAULT (_LESENSE_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_CMD */ -#define LESENSE_CMD_DECODE (0x1UL << 2) /**< Start decoder */ -#define _LESENSE_CMD_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */ -#define _LESENSE_CMD_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */ -#define _LESENSE_CMD_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ -#define LESENSE_CMD_DECODE_DEFAULT (_LESENSE_CMD_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CMD */ -#define LESENSE_CMD_CLEARBUF (0x1UL << 3) /**< Clear result buffer */ -#define _LESENSE_CMD_CLEARBUF_SHIFT 3 /**< Shift value for LESENSE_CLEARBUF */ -#define _LESENSE_CMD_CLEARBUF_MASK 0x8UL /**< Bit mask for LESENSE_CLEARBUF */ -#define _LESENSE_CMD_CLEARBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ -#define LESENSE_CMD_CLEARBUF_DEFAULT (_LESENSE_CMD_CLEARBUF_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define _LESENSE_CMD_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CMD */ +#define _LESENSE_CMD_MASK 0x0000000FUL /**< Mask for LESENSE_CMD */ +#define LESENSE_CMD_START (0x1UL << 0) /**< Start scanning of sensors. */ +#define _LESENSE_CMD_START_SHIFT 0 /**< Shift value for LESENSE_START */ +#define _LESENSE_CMD_START_MASK 0x1UL /**< Bit mask for LESENSE_START */ +#define _LESENSE_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_START_DEFAULT (_LESENSE_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP (0x1UL << 1) /**< Stop scanning of sensors */ +#define _LESENSE_CMD_STOP_SHIFT 1 /**< Shift value for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_MASK 0x2UL /**< Bit mask for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP_DEFAULT (_LESENSE_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE (0x1UL << 2) /**< Start decoder */ +#define _LESENSE_CMD_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE_DEFAULT (_LESENSE_CMD_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF (0x1UL << 3) /**< Clear result buffer */ +#define _LESENSE_CMD_CLEARBUF_SHIFT 3 /**< Shift value for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_MASK 0x8UL /**< Bit mask for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF_DEFAULT (_LESENSE_CMD_CLEARBUF_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_CMD */ /* Bit fields for LESENSE CHEN */ -#define _LESENSE_CHEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CHEN */ -#define _LESENSE_CHEN_MASK 0x0000FFFFUL /**< Mask for LESENSE_CHEN */ -#define _LESENSE_CHEN_CHEN_SHIFT 0 /**< Shift value for LESENSE_CHEN */ -#define _LESENSE_CHEN_CHEN_MASK 0xFFFFUL /**< Bit mask for LESENSE_CHEN */ -#define _LESENSE_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CHEN */ -#define LESENSE_CHEN_CHEN_DEFAULT (_LESENSE_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CHEN */ +#define _LESENSE_CHEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CHEN */ +#define _LESENSE_CHEN_MASK 0x0000FFFFUL /**< Mask for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_SHIFT 0 /**< Shift value for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_MASK 0xFFFFUL /**< Bit mask for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CHEN */ +#define LESENSE_CHEN_CHEN_DEFAULT (_LESENSE_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CHEN */ /* Bit fields for LESENSE SCANRES */ -#define _LESENSE_SCANRES_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SCANRES */ -#define _LESENSE_SCANRES_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_SCANRES */ -#define _LESENSE_SCANRES_SCANRES_SHIFT 0 /**< Shift value for LESENSE_SCANRES */ -#define _LESENSE_SCANRES_SCANRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_SCANRES */ -#define _LESENSE_SCANRES_SCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ -#define LESENSE_SCANRES_SCANRES_DEFAULT (_LESENSE_SCANRES_SCANRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ -#define _LESENSE_SCANRES_STEPDIR_SHIFT 16 /**< Shift value for LESENSE_STEPDIR */ -#define _LESENSE_SCANRES_STEPDIR_MASK 0xFFFF0000UL /**< Bit mask for LESENSE_STEPDIR */ -#define _LESENSE_SCANRES_STEPDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ -#define LESENSE_SCANRES_STEPDIR_DEFAULT (_LESENSE_SCANRES_STEPDIR_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_SHIFT 0 /**< Shift value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ +#define LESENSE_SCANRES_SCANRES_DEFAULT (_LESENSE_SCANRES_SCANRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_STEPDIR_SHIFT 16 /**< Shift value for LESENSE_STEPDIR */ +#define _LESENSE_SCANRES_STEPDIR_MASK 0xFFFF0000UL /**< Bit mask for LESENSE_STEPDIR */ +#define _LESENSE_SCANRES_STEPDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ +#define LESENSE_SCANRES_STEPDIR_DEFAULT (_LESENSE_SCANRES_STEPDIR_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ /* Bit fields for LESENSE STATUS */ -#define _LESENSE_STATUS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_STATUS */ -#define _LESENSE_STATUS_MASK 0x0000007BUL /**< Mask for LESENSE_STATUS */ -#define LESENSE_STATUS_RESFIFOV (0x1UL << 0) /**< Result fifo valid */ -#define _LESENSE_STATUS_RESFIFOV_SHIFT 0 /**< Shift value for LESENSE_RESFIFOV */ -#define _LESENSE_STATUS_RESFIFOV_MASK 0x1UL /**< Bit mask for LESENSE_RESFIFOV */ -#define _LESENSE_STATUS_RESFIFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_RESFIFOV_DEFAULT (_LESENSE_STATUS_RESFIFOV_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_RESFIFOFULL (0x1UL << 1) /**< Result fifo full */ -#define _LESENSE_STATUS_RESFIFOFULL_SHIFT 1 /**< Shift value for LESENSE_RESFIFOFULL */ -#define _LESENSE_STATUS_RESFIFOFULL_MASK 0x2UL /**< Bit mask for LESENSE_RESFIFOFULL */ -#define _LESENSE_STATUS_RESFIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_RESFIFOFULL_DEFAULT (_LESENSE_STATUS_RESFIFOFULL_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_SCANACTIVE (0x1UL << 3) /**< LESENSE scan active */ -#define _LESENSE_STATUS_SCANACTIVE_SHIFT 3 /**< Shift value for LESENSE_SCANACTIVE */ -#define _LESENSE_STATUS_SCANACTIVE_MASK 0x8UL /**< Bit mask for LESENSE_SCANACTIVE */ -#define _LESENSE_STATUS_SCANACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_SCANACTIVE_DEFAULT (_LESENSE_STATUS_SCANACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_RUNNING (0x1UL << 4) /**< LESENSE periodic counter running */ -#define _LESENSE_STATUS_RUNNING_SHIFT 4 /**< Shift value for LESENSE_RUNNING */ -#define _LESENSE_STATUS_RUNNING_MASK 0x10UL /**< Bit mask for LESENSE_RUNNING */ -#define _LESENSE_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_RUNNING_DEFAULT (_LESENSE_STATUS_RUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_READBUSY (0x1UL << 5) /**< FIFO Read Busy */ -#define _LESENSE_STATUS_READBUSY_SHIFT 5 /**< Shift value for LESENSE_READBUSY */ -#define _LESENSE_STATUS_READBUSY_MASK 0x20UL /**< Bit mask for LESENSE_READBUSY */ -#define _LESENSE_STATUS_READBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_READBUSY_DEFAULT (_LESENSE_STATUS_READBUSY_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_FLUSHING (0x1UL << 6) /**< FIFO Flushing */ -#define _LESENSE_STATUS_FLUSHING_SHIFT 6 /**< Shift value for LESENSE_FLUSHING */ -#define _LESENSE_STATUS_FLUSHING_MASK 0x40UL /**< Bit mask for LESENSE_FLUSHING */ -#define _LESENSE_STATUS_FLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ -#define LESENSE_STATUS_FLUSHING_DEFAULT (_LESENSE_STATUS_FLUSHING_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define _LESENSE_STATUS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_STATUS */ +#define _LESENSE_STATUS_MASK 0x0000007BUL /**< Mask for LESENSE_STATUS */ +#define LESENSE_STATUS_RESFIFOV (0x1UL << 0) /**< Result fifo valid */ +#define _LESENSE_STATUS_RESFIFOV_SHIFT 0 /**< Shift value for LESENSE_RESFIFOV */ +#define _LESENSE_STATUS_RESFIFOV_MASK 0x1UL /**< Bit mask for LESENSE_RESFIFOV */ +#define _LESENSE_STATUS_RESFIFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RESFIFOV_DEFAULT (_LESENSE_STATUS_RESFIFOV_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RESFIFOFULL (0x1UL << 1) /**< Result fifo full */ +#define _LESENSE_STATUS_RESFIFOFULL_SHIFT 1 /**< Shift value for LESENSE_RESFIFOFULL */ +#define _LESENSE_STATUS_RESFIFOFULL_MASK 0x2UL /**< Bit mask for LESENSE_RESFIFOFULL */ +#define _LESENSE_STATUS_RESFIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RESFIFOFULL_DEFAULT (_LESENSE_STATUS_RESFIFOFULL_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE (0x1UL << 3) /**< LESENSE scan active */ +#define _LESENSE_STATUS_SCANACTIVE_SHIFT 3 /**< Shift value for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_MASK 0x8UL /**< Bit mask for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE_DEFAULT (_LESENSE_STATUS_SCANACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING (0x1UL << 4) /**< LESENSE periodic counter running */ +#define _LESENSE_STATUS_RUNNING_SHIFT 4 /**< Shift value for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_MASK 0x10UL /**< Bit mask for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING_DEFAULT (_LESENSE_STATUS_RUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_READBUSY (0x1UL << 5) /**< FIFO Read Busy */ +#define _LESENSE_STATUS_READBUSY_SHIFT 5 /**< Shift value for LESENSE_READBUSY */ +#define _LESENSE_STATUS_READBUSY_MASK 0x20UL /**< Bit mask for LESENSE_READBUSY */ +#define _LESENSE_STATUS_READBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_READBUSY_DEFAULT (_LESENSE_STATUS_READBUSY_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_FLUSHING (0x1UL << 6) /**< FIFO Flushing */ +#define _LESENSE_STATUS_FLUSHING_SHIFT 6 /**< Shift value for LESENSE_FLUSHING */ +#define _LESENSE_STATUS_FLUSHING_MASK 0x40UL /**< Bit mask for LESENSE_FLUSHING */ +#define _LESENSE_STATUS_FLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_FLUSHING_DEFAULT (_LESENSE_STATUS_FLUSHING_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_STATUS */ /* Bit fields for LESENSE RESCOUNT */ -#define _LESENSE_RESCOUNT_RESETVALUE 0x00000000UL /**< Default value for LESENSE_RESCOUNT */ -#define _LESENSE_RESCOUNT_MASK 0x0000001FUL /**< Mask for LESENSE_RESCOUNT */ -#define _LESENSE_RESCOUNT_COUNT_SHIFT 0 /**< Shift value for LESENSE_COUNT */ -#define _LESENSE_RESCOUNT_COUNT_MASK 0x1FUL /**< Bit mask for LESENSE_COUNT */ -#define _LESENSE_RESCOUNT_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_RESCOUNT */ -#define LESENSE_RESCOUNT_COUNT_DEFAULT (_LESENSE_RESCOUNT_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_RESCOUNT */ +#define _LESENSE_RESCOUNT_RESETVALUE 0x00000000UL /**< Default value for LESENSE_RESCOUNT */ +#define _LESENSE_RESCOUNT_MASK 0x0000001FUL /**< Mask for LESENSE_RESCOUNT */ +#define _LESENSE_RESCOUNT_COUNT_SHIFT 0 /**< Shift value for LESENSE_COUNT */ +#define _LESENSE_RESCOUNT_COUNT_MASK 0x1FUL /**< Bit mask for LESENSE_COUNT */ +#define _LESENSE_RESCOUNT_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_RESCOUNT */ +#define LESENSE_RESCOUNT_COUNT_DEFAULT (_LESENSE_RESCOUNT_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_RESCOUNT */ /* Bit fields for LESENSE RESFIFO */ -#define _LESENSE_RESFIFO_RESETVALUE 0x00000000UL /**< Default value for LESENSE_RESFIFO */ -#define _LESENSE_RESFIFO_MASK 0x000FFFFFUL /**< Mask for LESENSE_RESFIFO */ -#define _LESENSE_RESFIFO_BUFDATASRC_SHIFT 0 /**< Shift value for LESENSE_BUFDATASRC */ -#define _LESENSE_RESFIFO_BUFDATASRC_MASK 0xFFFFFUL /**< Bit mask for LESENSE_BUFDATASRC */ -#define _LESENSE_RESFIFO_BUFDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_RESFIFO */ -#define LESENSE_RESFIFO_BUFDATASRC_DEFAULT (_LESENSE_RESFIFO_BUFDATASRC_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_RESFIFO */ +#define _LESENSE_RESFIFO_RESETVALUE 0x00000000UL /**< Default value for LESENSE_RESFIFO */ +#define _LESENSE_RESFIFO_MASK 0x000FFFFFUL /**< Mask for LESENSE_RESFIFO */ +#define _LESENSE_RESFIFO_BUFDATASRC_SHIFT 0 /**< Shift value for LESENSE_BUFDATASRC */ +#define _LESENSE_RESFIFO_BUFDATASRC_MASK 0xFFFFFUL /**< Bit mask for LESENSE_BUFDATASRC */ +#define _LESENSE_RESFIFO_BUFDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_RESFIFO */ +#define LESENSE_RESFIFO_BUFDATASRC_DEFAULT (_LESENSE_RESFIFO_BUFDATASRC_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_RESFIFO */ /* Bit fields for LESENSE CURCH */ -#define _LESENSE_CURCH_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CURCH */ -#define _LESENSE_CURCH_MASK 0x0000000FUL /**< Mask for LESENSE_CURCH */ -#define _LESENSE_CURCH_CURCH_SHIFT 0 /**< Shift value for LESENSE_CURCH */ -#define _LESENSE_CURCH_CURCH_MASK 0xFUL /**< Bit mask for LESENSE_CURCH */ -#define _LESENSE_CURCH_CURCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CURCH */ -#define LESENSE_CURCH_CURCH_DEFAULT (_LESENSE_CURCH_CURCH_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CURCH */ +#define _LESENSE_CURCH_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CURCH */ +#define _LESENSE_CURCH_MASK 0x0000000FUL /**< Mask for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_SHIFT 0 /**< Shift value for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_MASK 0xFUL /**< Bit mask for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CURCH */ +#define LESENSE_CURCH_CURCH_DEFAULT (_LESENSE_CURCH_CURCH_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CURCH */ /* Bit fields for LESENSE DECSTATE */ -#define _LESENSE_DECSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECSTATE */ -#define _LESENSE_DECSTATE_MASK 0x0000001FUL /**< Mask for LESENSE_DECSTATE */ -#define _LESENSE_DECSTATE_DECSTATE_SHIFT 0 /**< Shift value for LESENSE_DECSTATE */ -#define _LESENSE_DECSTATE_DECSTATE_MASK 0x1FUL /**< Bit mask for LESENSE_DECSTATE */ -#define _LESENSE_DECSTATE_DECSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECSTATE */ -#define LESENSE_DECSTATE_DECSTATE_DEFAULT (_LESENSE_DECSTATE_DECSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_MASK 0x0000001FUL /**< Mask for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_SHIFT 0 /**< Shift value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_MASK 0x1FUL /**< Bit mask for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECSTATE */ +#define LESENSE_DECSTATE_DECSTATE_DEFAULT (_LESENSE_DECSTATE_DECSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECSTATE */ /* Bit fields for LESENSE SENSORSTATE */ -#define _LESENSE_SENSORSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SENSORSTATE */ -#define _LESENSE_SENSORSTATE_MASK 0x0000000FUL /**< Mask for LESENSE_SENSORSTATE */ -#define _LESENSE_SENSORSTATE_SENSORSTATE_SHIFT 0 /**< Shift value for LESENSE_SENSORSTATE */ -#define _LESENSE_SENSORSTATE_SENSORSTATE_MASK 0xFUL /**< Bit mask for LESENSE_SENSORSTATE */ -#define _LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SENSORSTATE */ -#define LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT (_LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SENSORSTATE*/ +#define _LESENSE_SENSORSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_MASK 0x0000000FUL /**< Mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_SHIFT 0 /**< Shift value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_MASK 0xFUL /**< Bit mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SENSORSTATE */ +#define LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT (_LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SENSORSTATE*/ /* Bit fields for LESENSE IDLECONF */ -#define _LESENSE_IDLECONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE0_SHIFT 0 /**< Shift value for LESENSE_CHIDLE0 */ -#define _LESENSE_IDLECONF_CHIDLE0_MASK 0x3UL /**< Bit mask for LESENSE_CHIDLE0 */ -#define _LESENSE_IDLECONF_CHIDLE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE0_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE0_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE0_DEFAULT (_LESENSE_IDLECONF_CHIDLE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE0_DISABLE (_LESENSE_IDLECONF_CHIDLE0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE0_HIGH (_LESENSE_IDLECONF_CHIDLE0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE0_LOW (_LESENSE_IDLECONF_CHIDLE0_LOW << 0) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE0_DAC (_LESENSE_IDLECONF_CHIDLE0_DAC << 0) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE1_SHIFT 2 /**< Shift value for LESENSE_CHIDLE1 */ -#define _LESENSE_IDLECONF_CHIDLE1_MASK 0xCUL /**< Bit mask for LESENSE_CHIDLE1 */ -#define _LESENSE_IDLECONF_CHIDLE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE1_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE1_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE1_DEFAULT (_LESENSE_IDLECONF_CHIDLE1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE1_DISABLE (_LESENSE_IDLECONF_CHIDLE1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE1_HIGH (_LESENSE_IDLECONF_CHIDLE1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE1_LOW (_LESENSE_IDLECONF_CHIDLE1_LOW << 2) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE1_DAC (_LESENSE_IDLECONF_CHIDLE1_DAC << 2) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE2_SHIFT 4 /**< Shift value for LESENSE_CHIDLE2 */ -#define _LESENSE_IDLECONF_CHIDLE2_MASK 0x30UL /**< Bit mask for LESENSE_CHIDLE2 */ -#define _LESENSE_IDLECONF_CHIDLE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE2_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE2_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE2_DEFAULT (_LESENSE_IDLECONF_CHIDLE2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE2_DISABLE (_LESENSE_IDLECONF_CHIDLE2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE2_HIGH (_LESENSE_IDLECONF_CHIDLE2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE2_LOW (_LESENSE_IDLECONF_CHIDLE2_LOW << 4) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE2_DAC (_LESENSE_IDLECONF_CHIDLE2_DAC << 4) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE3_SHIFT 6 /**< Shift value for LESENSE_CHIDLE3 */ -#define _LESENSE_IDLECONF_CHIDLE3_MASK 0xC0UL /**< Bit mask for LESENSE_CHIDLE3 */ -#define _LESENSE_IDLECONF_CHIDLE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE3_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE3_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE3_DEFAULT (_LESENSE_IDLECONF_CHIDLE3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE3_DISABLE (_LESENSE_IDLECONF_CHIDLE3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE3_HIGH (_LESENSE_IDLECONF_CHIDLE3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE3_LOW (_LESENSE_IDLECONF_CHIDLE3_LOW << 6) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE3_DAC (_LESENSE_IDLECONF_CHIDLE3_DAC << 6) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE4_SHIFT 8 /**< Shift value for LESENSE_CHIDLE4 */ -#define _LESENSE_IDLECONF_CHIDLE4_MASK 0x300UL /**< Bit mask for LESENSE_CHIDLE4 */ -#define _LESENSE_IDLECONF_CHIDLE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE4_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE4_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE4_DEFAULT (_LESENSE_IDLECONF_CHIDLE4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE4_DISABLE (_LESENSE_IDLECONF_CHIDLE4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE4_HIGH (_LESENSE_IDLECONF_CHIDLE4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE4_LOW (_LESENSE_IDLECONF_CHIDLE4_LOW << 8) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE4_DAC (_LESENSE_IDLECONF_CHIDLE4_DAC << 8) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE5_SHIFT 10 /**< Shift value for LESENSE_CHIDLE5 */ -#define _LESENSE_IDLECONF_CHIDLE5_MASK 0xC00UL /**< Bit mask for LESENSE_CHIDLE5 */ -#define _LESENSE_IDLECONF_CHIDLE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE5_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE5_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE5_DEFAULT (_LESENSE_IDLECONF_CHIDLE5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE5_DISABLE (_LESENSE_IDLECONF_CHIDLE5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE5_HIGH (_LESENSE_IDLECONF_CHIDLE5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE5_LOW (_LESENSE_IDLECONF_CHIDLE5_LOW << 10) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE5_DAC (_LESENSE_IDLECONF_CHIDLE5_DAC << 10) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE6_SHIFT 12 /**< Shift value for LESENSE_CHIDLE6 */ -#define _LESENSE_IDLECONF_CHIDLE6_MASK 0x3000UL /**< Bit mask for LESENSE_CHIDLE6 */ -#define _LESENSE_IDLECONF_CHIDLE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE6_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE6_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE6_DEFAULT (_LESENSE_IDLECONF_CHIDLE6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE6_DISABLE (_LESENSE_IDLECONF_CHIDLE6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE6_HIGH (_LESENSE_IDLECONF_CHIDLE6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE6_LOW (_LESENSE_IDLECONF_CHIDLE6_LOW << 12) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE6_DAC (_LESENSE_IDLECONF_CHIDLE6_DAC << 12) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE7_SHIFT 14 /**< Shift value for LESENSE_CHIDLE7 */ -#define _LESENSE_IDLECONF_CHIDLE7_MASK 0xC000UL /**< Bit mask for LESENSE_CHIDLE7 */ -#define _LESENSE_IDLECONF_CHIDLE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE7_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE7_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE7_DEFAULT (_LESENSE_IDLECONF_CHIDLE7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE7_DISABLE (_LESENSE_IDLECONF_CHIDLE7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE7_HIGH (_LESENSE_IDLECONF_CHIDLE7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE7_LOW (_LESENSE_IDLECONF_CHIDLE7_LOW << 14) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE7_DAC (_LESENSE_IDLECONF_CHIDLE7_DAC << 14) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE8_SHIFT 16 /**< Shift value for LESENSE_CHIDLE8 */ -#define _LESENSE_IDLECONF_CHIDLE8_MASK 0x30000UL /**< Bit mask for LESENSE_CHIDLE8 */ -#define _LESENSE_IDLECONF_CHIDLE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE8_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE8_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE8_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE8_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE8_DEFAULT (_LESENSE_IDLECONF_CHIDLE8_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE8_DISABLE (_LESENSE_IDLECONF_CHIDLE8_DISABLE << 16) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE8_HIGH (_LESENSE_IDLECONF_CHIDLE8_HIGH << 16) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE8_LOW (_LESENSE_IDLECONF_CHIDLE8_LOW << 16) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE8_DAC (_LESENSE_IDLECONF_CHIDLE8_DAC << 16) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE9_SHIFT 18 /**< Shift value for LESENSE_CHIDLE9 */ -#define _LESENSE_IDLECONF_CHIDLE9_MASK 0xC0000UL /**< Bit mask for LESENSE_CHIDLE9 */ -#define _LESENSE_IDLECONF_CHIDLE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE9_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE9_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE9_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE9_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE9_DEFAULT (_LESENSE_IDLECONF_CHIDLE9_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE9_DISABLE (_LESENSE_IDLECONF_CHIDLE9_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE9_HIGH (_LESENSE_IDLECONF_CHIDLE9_HIGH << 18) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE9_LOW (_LESENSE_IDLECONF_CHIDLE9_LOW << 18) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE9_DAC (_LESENSE_IDLECONF_CHIDLE9_DAC << 18) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE10_SHIFT 20 /**< Shift value for LESENSE_CHIDLE10 */ -#define _LESENSE_IDLECONF_CHIDLE10_MASK 0x300000UL /**< Bit mask for LESENSE_CHIDLE10 */ -#define _LESENSE_IDLECONF_CHIDLE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE10_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE10_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE10_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE10_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE10_DEFAULT (_LESENSE_IDLECONF_CHIDLE10_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE10_DISABLE (_LESENSE_IDLECONF_CHIDLE10_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE10_HIGH (_LESENSE_IDLECONF_CHIDLE10_HIGH << 20) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE10_LOW (_LESENSE_IDLECONF_CHIDLE10_LOW << 20) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE10_DAC (_LESENSE_IDLECONF_CHIDLE10_DAC << 20) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE11_SHIFT 22 /**< Shift value for LESENSE_CHIDLE11 */ -#define _LESENSE_IDLECONF_CHIDLE11_MASK 0xC00000UL /**< Bit mask for LESENSE_CHIDLE11 */ -#define _LESENSE_IDLECONF_CHIDLE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE11_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE11_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE11_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE11_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE11_DEFAULT (_LESENSE_IDLECONF_CHIDLE11_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE11_DISABLE (_LESENSE_IDLECONF_CHIDLE11_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE11_HIGH (_LESENSE_IDLECONF_CHIDLE11_HIGH << 22) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE11_LOW (_LESENSE_IDLECONF_CHIDLE11_LOW << 22) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE11_DAC (_LESENSE_IDLECONF_CHIDLE11_DAC << 22) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE12_SHIFT 24 /**< Shift value for LESENSE_CHIDLE12 */ -#define _LESENSE_IDLECONF_CHIDLE12_MASK 0x3000000UL /**< Bit mask for LESENSE_CHIDLE12 */ -#define _LESENSE_IDLECONF_CHIDLE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE12_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE12_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE12_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE12_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE12_DEFAULT (_LESENSE_IDLECONF_CHIDLE12_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE12_DISABLE (_LESENSE_IDLECONF_CHIDLE12_DISABLE << 24) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE12_HIGH (_LESENSE_IDLECONF_CHIDLE12_HIGH << 24) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE12_LOW (_LESENSE_IDLECONF_CHIDLE12_LOW << 24) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE12_DAC (_LESENSE_IDLECONF_CHIDLE12_DAC << 24) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE13_SHIFT 26 /**< Shift value for LESENSE_CHIDLE13 */ -#define _LESENSE_IDLECONF_CHIDLE13_MASK 0xC000000UL /**< Bit mask for LESENSE_CHIDLE13 */ -#define _LESENSE_IDLECONF_CHIDLE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE13_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE13_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE13_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE13_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE13_DEFAULT (_LESENSE_IDLECONF_CHIDLE13_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE13_DISABLE (_LESENSE_IDLECONF_CHIDLE13_DISABLE << 26) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE13_HIGH (_LESENSE_IDLECONF_CHIDLE13_HIGH << 26) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE13_LOW (_LESENSE_IDLECONF_CHIDLE13_LOW << 26) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE13_DAC (_LESENSE_IDLECONF_CHIDLE13_DAC << 26) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE14_SHIFT 28 /**< Shift value for LESENSE_CHIDLE14 */ -#define _LESENSE_IDLECONF_CHIDLE14_MASK 0x30000000UL /**< Bit mask for LESENSE_CHIDLE14 */ -#define _LESENSE_IDLECONF_CHIDLE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE14_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE14_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE14_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE14_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE14_DEFAULT (_LESENSE_IDLECONF_CHIDLE14_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE14_DISABLE (_LESENSE_IDLECONF_CHIDLE14_DISABLE << 28) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE14_HIGH (_LESENSE_IDLECONF_CHIDLE14_HIGH << 28) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE14_LOW (_LESENSE_IDLECONF_CHIDLE14_LOW << 28) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE14_DAC (_LESENSE_IDLECONF_CHIDLE14_DAC << 28) /**< Shifted mode DAC for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE15_SHIFT 30 /**< Shift value for LESENSE_CHIDLE15 */ -#define _LESENSE_IDLECONF_CHIDLE15_MASK 0xC0000000UL /**< Bit mask for LESENSE_CHIDLE15 */ -#define _LESENSE_IDLECONF_CHIDLE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE15_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE15_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE15_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ -#define _LESENSE_IDLECONF_CHIDLE15_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE15_DEFAULT (_LESENSE_IDLECONF_CHIDLE15_DEFAULT << 30) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE15_DISABLE (_LESENSE_IDLECONF_CHIDLE15_DISABLE << 30) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE15_HIGH (_LESENSE_IDLECONF_CHIDLE15_HIGH << 30) /**< Shifted mode HIGH for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE15_LOW (_LESENSE_IDLECONF_CHIDLE15_LOW << 30) /**< Shifted mode LOW for LESENSE_IDLECONF */ -#define LESENSE_IDLECONF_CHIDLE15_DAC (_LESENSE_IDLECONF_CHIDLE15_DAC << 30) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE0_SHIFT 0 /**< Shift value for LESENSE_CHIDLE0 */ +#define _LESENSE_IDLECONF_CHIDLE0_MASK 0x3UL /**< Bit mask for LESENSE_CHIDLE0 */ +#define _LESENSE_IDLECONF_CHIDLE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE0_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE0_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE0_DEFAULT (_LESENSE_IDLECONF_CHIDLE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE0_DISABLE (_LESENSE_IDLECONF_CHIDLE0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE0_HIGH (_LESENSE_IDLECONF_CHIDLE0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE0_LOW (_LESENSE_IDLECONF_CHIDLE0_LOW << 0) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE0_DAC (_LESENSE_IDLECONF_CHIDLE0_DAC << 0) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE1_SHIFT 2 /**< Shift value for LESENSE_CHIDLE1 */ +#define _LESENSE_IDLECONF_CHIDLE1_MASK 0xCUL /**< Bit mask for LESENSE_CHIDLE1 */ +#define _LESENSE_IDLECONF_CHIDLE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE1_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE1_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE1_DEFAULT (_LESENSE_IDLECONF_CHIDLE1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE1_DISABLE (_LESENSE_IDLECONF_CHIDLE1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE1_HIGH (_LESENSE_IDLECONF_CHIDLE1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE1_LOW (_LESENSE_IDLECONF_CHIDLE1_LOW << 2) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE1_DAC (_LESENSE_IDLECONF_CHIDLE1_DAC << 2) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE2_SHIFT 4 /**< Shift value for LESENSE_CHIDLE2 */ +#define _LESENSE_IDLECONF_CHIDLE2_MASK 0x30UL /**< Bit mask for LESENSE_CHIDLE2 */ +#define _LESENSE_IDLECONF_CHIDLE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE2_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE2_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE2_DEFAULT (_LESENSE_IDLECONF_CHIDLE2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE2_DISABLE (_LESENSE_IDLECONF_CHIDLE2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE2_HIGH (_LESENSE_IDLECONF_CHIDLE2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE2_LOW (_LESENSE_IDLECONF_CHIDLE2_LOW << 4) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE2_DAC (_LESENSE_IDLECONF_CHIDLE2_DAC << 4) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE3_SHIFT 6 /**< Shift value for LESENSE_CHIDLE3 */ +#define _LESENSE_IDLECONF_CHIDLE3_MASK 0xC0UL /**< Bit mask for LESENSE_CHIDLE3 */ +#define _LESENSE_IDLECONF_CHIDLE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE3_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE3_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE3_DEFAULT (_LESENSE_IDLECONF_CHIDLE3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE3_DISABLE (_LESENSE_IDLECONF_CHIDLE3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE3_HIGH (_LESENSE_IDLECONF_CHIDLE3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE3_LOW (_LESENSE_IDLECONF_CHIDLE3_LOW << 6) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE3_DAC (_LESENSE_IDLECONF_CHIDLE3_DAC << 6) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE4_SHIFT 8 /**< Shift value for LESENSE_CHIDLE4 */ +#define _LESENSE_IDLECONF_CHIDLE4_MASK 0x300UL /**< Bit mask for LESENSE_CHIDLE4 */ +#define _LESENSE_IDLECONF_CHIDLE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE4_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE4_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE4_DEFAULT (_LESENSE_IDLECONF_CHIDLE4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE4_DISABLE (_LESENSE_IDLECONF_CHIDLE4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE4_HIGH (_LESENSE_IDLECONF_CHIDLE4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE4_LOW (_LESENSE_IDLECONF_CHIDLE4_LOW << 8) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE4_DAC (_LESENSE_IDLECONF_CHIDLE4_DAC << 8) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE5_SHIFT 10 /**< Shift value for LESENSE_CHIDLE5 */ +#define _LESENSE_IDLECONF_CHIDLE5_MASK 0xC00UL /**< Bit mask for LESENSE_CHIDLE5 */ +#define _LESENSE_IDLECONF_CHIDLE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE5_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE5_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE5_DEFAULT (_LESENSE_IDLECONF_CHIDLE5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE5_DISABLE (_LESENSE_IDLECONF_CHIDLE5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE5_HIGH (_LESENSE_IDLECONF_CHIDLE5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE5_LOW (_LESENSE_IDLECONF_CHIDLE5_LOW << 10) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE5_DAC (_LESENSE_IDLECONF_CHIDLE5_DAC << 10) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE6_SHIFT 12 /**< Shift value for LESENSE_CHIDLE6 */ +#define _LESENSE_IDLECONF_CHIDLE6_MASK 0x3000UL /**< Bit mask for LESENSE_CHIDLE6 */ +#define _LESENSE_IDLECONF_CHIDLE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE6_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE6_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE6_DEFAULT (_LESENSE_IDLECONF_CHIDLE6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE6_DISABLE (_LESENSE_IDLECONF_CHIDLE6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE6_HIGH (_LESENSE_IDLECONF_CHIDLE6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE6_LOW (_LESENSE_IDLECONF_CHIDLE6_LOW << 12) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE6_DAC (_LESENSE_IDLECONF_CHIDLE6_DAC << 12) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE7_SHIFT 14 /**< Shift value for LESENSE_CHIDLE7 */ +#define _LESENSE_IDLECONF_CHIDLE7_MASK 0xC000UL /**< Bit mask for LESENSE_CHIDLE7 */ +#define _LESENSE_IDLECONF_CHIDLE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE7_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE7_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE7_DEFAULT (_LESENSE_IDLECONF_CHIDLE7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE7_DISABLE (_LESENSE_IDLECONF_CHIDLE7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE7_HIGH (_LESENSE_IDLECONF_CHIDLE7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE7_LOW (_LESENSE_IDLECONF_CHIDLE7_LOW << 14) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE7_DAC (_LESENSE_IDLECONF_CHIDLE7_DAC << 14) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE8_SHIFT 16 /**< Shift value for LESENSE_CHIDLE8 */ +#define _LESENSE_IDLECONF_CHIDLE8_MASK 0x30000UL /**< Bit mask for LESENSE_CHIDLE8 */ +#define _LESENSE_IDLECONF_CHIDLE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE8_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE8_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE8_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE8_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE8_DEFAULT (_LESENSE_IDLECONF_CHIDLE8_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE8_DISABLE (_LESENSE_IDLECONF_CHIDLE8_DISABLE << 16) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE8_HIGH (_LESENSE_IDLECONF_CHIDLE8_HIGH << 16) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE8_LOW (_LESENSE_IDLECONF_CHIDLE8_LOW << 16) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE8_DAC (_LESENSE_IDLECONF_CHIDLE8_DAC << 16) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE9_SHIFT 18 /**< Shift value for LESENSE_CHIDLE9 */ +#define _LESENSE_IDLECONF_CHIDLE9_MASK 0xC0000UL /**< Bit mask for LESENSE_CHIDLE9 */ +#define _LESENSE_IDLECONF_CHIDLE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE9_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE9_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE9_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE9_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE9_DEFAULT (_LESENSE_IDLECONF_CHIDLE9_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE9_DISABLE (_LESENSE_IDLECONF_CHIDLE9_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE9_HIGH (_LESENSE_IDLECONF_CHIDLE9_HIGH << 18) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE9_LOW (_LESENSE_IDLECONF_CHIDLE9_LOW << 18) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE9_DAC (_LESENSE_IDLECONF_CHIDLE9_DAC << 18) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE10_SHIFT 20 /**< Shift value for LESENSE_CHIDLE10 */ +#define _LESENSE_IDLECONF_CHIDLE10_MASK 0x300000UL /**< Bit mask for LESENSE_CHIDLE10 */ +#define _LESENSE_IDLECONF_CHIDLE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE10_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE10_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE10_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE10_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE10_DEFAULT (_LESENSE_IDLECONF_CHIDLE10_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE10_DISABLE (_LESENSE_IDLECONF_CHIDLE10_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE10_HIGH (_LESENSE_IDLECONF_CHIDLE10_HIGH << 20) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE10_LOW (_LESENSE_IDLECONF_CHIDLE10_LOW << 20) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE10_DAC (_LESENSE_IDLECONF_CHIDLE10_DAC << 20) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE11_SHIFT 22 /**< Shift value for LESENSE_CHIDLE11 */ +#define _LESENSE_IDLECONF_CHIDLE11_MASK 0xC00000UL /**< Bit mask for LESENSE_CHIDLE11 */ +#define _LESENSE_IDLECONF_CHIDLE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE11_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE11_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE11_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE11_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE11_DEFAULT (_LESENSE_IDLECONF_CHIDLE11_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE11_DISABLE (_LESENSE_IDLECONF_CHIDLE11_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE11_HIGH (_LESENSE_IDLECONF_CHIDLE11_HIGH << 22) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE11_LOW (_LESENSE_IDLECONF_CHIDLE11_LOW << 22) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE11_DAC (_LESENSE_IDLECONF_CHIDLE11_DAC << 22) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE12_SHIFT 24 /**< Shift value for LESENSE_CHIDLE12 */ +#define _LESENSE_IDLECONF_CHIDLE12_MASK 0x3000000UL /**< Bit mask for LESENSE_CHIDLE12 */ +#define _LESENSE_IDLECONF_CHIDLE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE12_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE12_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE12_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE12_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE12_DEFAULT (_LESENSE_IDLECONF_CHIDLE12_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE12_DISABLE (_LESENSE_IDLECONF_CHIDLE12_DISABLE << 24) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE12_HIGH (_LESENSE_IDLECONF_CHIDLE12_HIGH << 24) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE12_LOW (_LESENSE_IDLECONF_CHIDLE12_LOW << 24) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE12_DAC (_LESENSE_IDLECONF_CHIDLE12_DAC << 24) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE13_SHIFT 26 /**< Shift value for LESENSE_CHIDLE13 */ +#define _LESENSE_IDLECONF_CHIDLE13_MASK 0xC000000UL /**< Bit mask for LESENSE_CHIDLE13 */ +#define _LESENSE_IDLECONF_CHIDLE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE13_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE13_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE13_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE13_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE13_DEFAULT (_LESENSE_IDLECONF_CHIDLE13_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE13_DISABLE (_LESENSE_IDLECONF_CHIDLE13_DISABLE << 26) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE13_HIGH (_LESENSE_IDLECONF_CHIDLE13_HIGH << 26) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE13_LOW (_LESENSE_IDLECONF_CHIDLE13_LOW << 26) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE13_DAC (_LESENSE_IDLECONF_CHIDLE13_DAC << 26) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE14_SHIFT 28 /**< Shift value for LESENSE_CHIDLE14 */ +#define _LESENSE_IDLECONF_CHIDLE14_MASK 0x30000000UL /**< Bit mask for LESENSE_CHIDLE14 */ +#define _LESENSE_IDLECONF_CHIDLE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE14_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE14_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE14_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE14_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE14_DEFAULT (_LESENSE_IDLECONF_CHIDLE14_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE14_DISABLE (_LESENSE_IDLECONF_CHIDLE14_DISABLE << 28) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE14_HIGH (_LESENSE_IDLECONF_CHIDLE14_HIGH << 28) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE14_LOW (_LESENSE_IDLECONF_CHIDLE14_LOW << 28) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE14_DAC (_LESENSE_IDLECONF_CHIDLE14_DAC << 28) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE15_SHIFT 30 /**< Shift value for LESENSE_CHIDLE15 */ +#define _LESENSE_IDLECONF_CHIDLE15_MASK 0xC0000000UL /**< Bit mask for LESENSE_CHIDLE15 */ +#define _LESENSE_IDLECONF_CHIDLE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE15_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE15_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE15_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE15_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE15_DEFAULT (_LESENSE_IDLECONF_CHIDLE15_DEFAULT << 30) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE15_DISABLE (_LESENSE_IDLECONF_CHIDLE15_DISABLE << 30) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE15_HIGH (_LESENSE_IDLECONF_CHIDLE15_HIGH << 30) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE15_LOW (_LESENSE_IDLECONF_CHIDLE15_LOW << 30) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE15_DAC (_LESENSE_IDLECONF_CHIDLE15_DAC << 30) /**< Shifted mode DAC for LESENSE_IDLECONF */ /* Bit fields for LESENSE SYNCBUSY */ -#define _LESENSE_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SYNCBUSY */ -#define _LESENSE_SYNCBUSY_MASK 0x00000001UL /**< Mask for LESENSE_SYNCBUSY */ -#define LESENSE_SYNCBUSY_CMD (0x1UL << 0) /**< Command */ -#define _LESENSE_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for LESENSE_CMD */ -#define _LESENSE_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for LESENSE_CMD */ -#define _LESENSE_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SYNCBUSY */ -#define LESENSE_SYNCBUSY_CMD_DEFAULT (_LESENSE_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define _LESENSE_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SYNCBUSY */ +#define _LESENSE_SYNCBUSY_MASK 0x00000001UL /**< Mask for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD (0x1UL << 0) /**< Command */ +#define _LESENSE_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD_DEFAULT (_LESENSE_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SYNCBUSY */ /* Bit fields for LESENSE IF */ -#define _LESENSE_IF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IF */ -#define _LESENSE_IF_MASK 0x003FFFFFUL /**< Mask for LESENSE_IF */ -#define LESENSE_IF_CH0 (0x1UL << 0) /**< Channel */ -#define _LESENSE_IF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ -#define _LESENSE_IF_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ -#define _LESENSE_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH0_DEFAULT (_LESENSE_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH1 (0x1UL << 1) /**< Channel */ -#define _LESENSE_IF_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ -#define _LESENSE_IF_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ -#define _LESENSE_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH1_DEFAULT (_LESENSE_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH2 (0x1UL << 2) /**< Channel */ -#define _LESENSE_IF_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ -#define _LESENSE_IF_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ -#define _LESENSE_IF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH2_DEFAULT (_LESENSE_IF_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH3 (0x1UL << 3) /**< Channel */ -#define _LESENSE_IF_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ -#define _LESENSE_IF_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ -#define _LESENSE_IF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH3_DEFAULT (_LESENSE_IF_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH4 (0x1UL << 4) /**< Channel */ -#define _LESENSE_IF_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ -#define _LESENSE_IF_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ -#define _LESENSE_IF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH4_DEFAULT (_LESENSE_IF_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH5 (0x1UL << 5) /**< Channel */ -#define _LESENSE_IF_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ -#define _LESENSE_IF_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ -#define _LESENSE_IF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH5_DEFAULT (_LESENSE_IF_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH6 (0x1UL << 6) /**< Channel */ -#define _LESENSE_IF_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ -#define _LESENSE_IF_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ -#define _LESENSE_IF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH6_DEFAULT (_LESENSE_IF_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH7 (0x1UL << 7) /**< Channel */ -#define _LESENSE_IF_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ -#define _LESENSE_IF_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ -#define _LESENSE_IF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH7_DEFAULT (_LESENSE_IF_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH8 (0x1UL << 8) /**< Channel */ -#define _LESENSE_IF_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ -#define _LESENSE_IF_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ -#define _LESENSE_IF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH8_DEFAULT (_LESENSE_IF_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH9 (0x1UL << 9) /**< Channel */ -#define _LESENSE_IF_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ -#define _LESENSE_IF_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ -#define _LESENSE_IF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH9_DEFAULT (_LESENSE_IF_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH10 (0x1UL << 10) /**< Channel */ -#define _LESENSE_IF_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ -#define _LESENSE_IF_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ -#define _LESENSE_IF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH10_DEFAULT (_LESENSE_IF_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH11 (0x1UL << 11) /**< Channel */ -#define _LESENSE_IF_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ -#define _LESENSE_IF_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ -#define _LESENSE_IF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH11_DEFAULT (_LESENSE_IF_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH12 (0x1UL << 12) /**< Channel */ -#define _LESENSE_IF_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ -#define _LESENSE_IF_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ -#define _LESENSE_IF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH12_DEFAULT (_LESENSE_IF_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH13 (0x1UL << 13) /**< Channel */ -#define _LESENSE_IF_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ -#define _LESENSE_IF_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ -#define _LESENSE_IF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH13_DEFAULT (_LESENSE_IF_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH14 (0x1UL << 14) /**< Channel */ -#define _LESENSE_IF_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ -#define _LESENSE_IF_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ -#define _LESENSE_IF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH14_DEFAULT (_LESENSE_IF_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH15 (0x1UL << 15) /**< Channel */ -#define _LESENSE_IF_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ -#define _LESENSE_IF_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ -#define _LESENSE_IF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CH15_DEFAULT (_LESENSE_IF_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_SCANDONE (0x1UL << 16) /**< Scan Done */ -#define _LESENSE_IF_SCANDONE_SHIFT 16 /**< Shift value for LESENSE_SCANDONE */ -#define _LESENSE_IF_SCANDONE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANDONE */ -#define _LESENSE_IF_SCANDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_SCANDONE_DEFAULT (_LESENSE_IF_SCANDONE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_DEC (0x1UL << 17) /**< Decoder */ -#define _LESENSE_IF_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ -#define _LESENSE_IF_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ -#define _LESENSE_IF_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_DEC_DEFAULT (_LESENSE_IF_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_RESWL (0x1UL << 18) /**< Result Watermark Level */ -#define _LESENSE_IF_RESWL_SHIFT 18 /**< Shift value for LESENSE_RESWL */ -#define _LESENSE_IF_RESWL_MASK 0x40000UL /**< Bit mask for LESENSE_RESWL */ -#define _LESENSE_IF_RESWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_RESWL_DEFAULT (_LESENSE_IF_RESWL_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_RESOF (0x1UL << 19) /**< Result Overflow */ -#define _LESENSE_IF_RESOF_SHIFT 19 /**< Shift value for LESENSE_RESOF */ -#define _LESENSE_IF_RESOF_MASK 0x80000UL /**< Bit mask for LESENSE_RESOF */ -#define _LESENSE_IF_RESOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_RESOF_DEFAULT (_LESENSE_IF_RESOF_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CNTOF (0x1UL << 20) /**< Counter Overflow */ -#define _LESENSE_IF_CNTOF_SHIFT 20 /**< Shift value for LESENSE_CNTOF */ -#define _LESENSE_IF_CNTOF_MASK 0x100000UL /**< Bit mask for LESENSE_CNTOF */ -#define _LESENSE_IF_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_CNTOF_DEFAULT (_LESENSE_IF_CNTOF_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_RESUF (0x1UL << 21) /**< Result Underflow */ -#define _LESENSE_IF_RESUF_SHIFT 21 /**< Shift value for LESENSE_RESUF */ -#define _LESENSE_IF_RESUF_MASK 0x200000UL /**< Bit mask for LESENSE_RESUF */ -#define _LESENSE_IF_RESUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ -#define LESENSE_IF_RESUF_DEFAULT (_LESENSE_IF_RESUF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define _LESENSE_IF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IF */ +#define _LESENSE_IF_MASK 0x003FFFFFUL /**< Mask for LESENSE_IF */ +#define LESENSE_IF_CH0 (0x1UL << 0) /**< Channel */ +#define _LESENSE_IF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH0_DEFAULT (_LESENSE_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1 (0x1UL << 1) /**< Channel */ +#define _LESENSE_IF_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1_DEFAULT (_LESENSE_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2 (0x1UL << 2) /**< Channel */ +#define _LESENSE_IF_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2_DEFAULT (_LESENSE_IF_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3 (0x1UL << 3) /**< Channel */ +#define _LESENSE_IF_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3_DEFAULT (_LESENSE_IF_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4 (0x1UL << 4) /**< Channel */ +#define _LESENSE_IF_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4_DEFAULT (_LESENSE_IF_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5 (0x1UL << 5) /**< Channel */ +#define _LESENSE_IF_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5_DEFAULT (_LESENSE_IF_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6 (0x1UL << 6) /**< Channel */ +#define _LESENSE_IF_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6_DEFAULT (_LESENSE_IF_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7 (0x1UL << 7) /**< Channel */ +#define _LESENSE_IF_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7_DEFAULT (_LESENSE_IF_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8 (0x1UL << 8) /**< Channel */ +#define _LESENSE_IF_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8_DEFAULT (_LESENSE_IF_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9 (0x1UL << 9) /**< Channel */ +#define _LESENSE_IF_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9_DEFAULT (_LESENSE_IF_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10 (0x1UL << 10) /**< Channel */ +#define _LESENSE_IF_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10_DEFAULT (_LESENSE_IF_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11 (0x1UL << 11) /**< Channel */ +#define _LESENSE_IF_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11_DEFAULT (_LESENSE_IF_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12 (0x1UL << 12) /**< Channel */ +#define _LESENSE_IF_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12_DEFAULT (_LESENSE_IF_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13 (0x1UL << 13) /**< Channel */ +#define _LESENSE_IF_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13_DEFAULT (_LESENSE_IF_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14 (0x1UL << 14) /**< Channel */ +#define _LESENSE_IF_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14_DEFAULT (_LESENSE_IF_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15 (0x1UL << 15) /**< Channel */ +#define _LESENSE_IF_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15_DEFAULT (_LESENSE_IF_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANDONE (0x1UL << 16) /**< Scan Done */ +#define _LESENSE_IF_SCANDONE_SHIFT 16 /**< Shift value for LESENSE_SCANDONE */ +#define _LESENSE_IF_SCANDONE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANDONE */ +#define _LESENSE_IF_SCANDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANDONE_DEFAULT (_LESENSE_IF_SCANDONE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC (0x1UL << 17) /**< Decoder */ +#define _LESENSE_IF_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IF_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IF_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC_DEFAULT (_LESENSE_IF_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESWL (0x1UL << 18) /**< Result Watermark Level */ +#define _LESENSE_IF_RESWL_SHIFT 18 /**< Shift value for LESENSE_RESWL */ +#define _LESENSE_IF_RESWL_MASK 0x40000UL /**< Bit mask for LESENSE_RESWL */ +#define _LESENSE_IF_RESWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESWL_DEFAULT (_LESENSE_IF_RESWL_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESOF (0x1UL << 19) /**< Result Overflow */ +#define _LESENSE_IF_RESOF_SHIFT 19 /**< Shift value for LESENSE_RESOF */ +#define _LESENSE_IF_RESOF_MASK 0x80000UL /**< Bit mask for LESENSE_RESOF */ +#define _LESENSE_IF_RESOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESOF_DEFAULT (_LESENSE_IF_RESOF_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF (0x1UL << 20) /**< Counter Overflow */ +#define _LESENSE_IF_CNTOF_SHIFT 20 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_MASK 0x100000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF_DEFAULT (_LESENSE_IF_CNTOF_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESUF (0x1UL << 21) /**< Result Underflow */ +#define _LESENSE_IF_RESUF_SHIFT 21 /**< Shift value for LESENSE_RESUF */ +#define _LESENSE_IF_RESUF_MASK 0x200000UL /**< Bit mask for LESENSE_RESUF */ +#define _LESENSE_IF_RESUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESUF_DEFAULT (_LESENSE_IF_RESUF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IF */ /* Bit fields for LESENSE IEN */ -#define _LESENSE_IEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IEN */ -#define _LESENSE_IEN_MASK 0x003FFFFFUL /**< Mask for LESENSE_IEN */ -#define LESENSE_IEN_CH0 (0x1UL << 0) /**< Channel */ -#define _LESENSE_IEN_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ -#define _LESENSE_IEN_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ -#define _LESENSE_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH0_DEFAULT (_LESENSE_IEN_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH1 (0x1UL << 1) /**< Channel */ -#define _LESENSE_IEN_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ -#define _LESENSE_IEN_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ -#define _LESENSE_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH1_DEFAULT (_LESENSE_IEN_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH2 (0x1UL << 2) /**< Channel */ -#define _LESENSE_IEN_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ -#define _LESENSE_IEN_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ -#define _LESENSE_IEN_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH2_DEFAULT (_LESENSE_IEN_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH3 (0x1UL << 3) /**< Channel */ -#define _LESENSE_IEN_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ -#define _LESENSE_IEN_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ -#define _LESENSE_IEN_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH3_DEFAULT (_LESENSE_IEN_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH4 (0x1UL << 4) /**< Channel */ -#define _LESENSE_IEN_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ -#define _LESENSE_IEN_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ -#define _LESENSE_IEN_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH4_DEFAULT (_LESENSE_IEN_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH5 (0x1UL << 5) /**< Channel */ -#define _LESENSE_IEN_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ -#define _LESENSE_IEN_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ -#define _LESENSE_IEN_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH5_DEFAULT (_LESENSE_IEN_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH6 (0x1UL << 6) /**< Channel */ -#define _LESENSE_IEN_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ -#define _LESENSE_IEN_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ -#define _LESENSE_IEN_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH6_DEFAULT (_LESENSE_IEN_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH7 (0x1UL << 7) /**< Channel */ -#define _LESENSE_IEN_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ -#define _LESENSE_IEN_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ -#define _LESENSE_IEN_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH7_DEFAULT (_LESENSE_IEN_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH8 (0x1UL << 8) /**< Channel */ -#define _LESENSE_IEN_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ -#define _LESENSE_IEN_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ -#define _LESENSE_IEN_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH8_DEFAULT (_LESENSE_IEN_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH9 (0x1UL << 9) /**< Channel */ -#define _LESENSE_IEN_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ -#define _LESENSE_IEN_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ -#define _LESENSE_IEN_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH9_DEFAULT (_LESENSE_IEN_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH10 (0x1UL << 10) /**< Channel */ -#define _LESENSE_IEN_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ -#define _LESENSE_IEN_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ -#define _LESENSE_IEN_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH10_DEFAULT (_LESENSE_IEN_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH11 (0x1UL << 11) /**< Channel */ -#define _LESENSE_IEN_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ -#define _LESENSE_IEN_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ -#define _LESENSE_IEN_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH11_DEFAULT (_LESENSE_IEN_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH12 (0x1UL << 12) /**< Channel */ -#define _LESENSE_IEN_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ -#define _LESENSE_IEN_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ -#define _LESENSE_IEN_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH12_DEFAULT (_LESENSE_IEN_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH13 (0x1UL << 13) /**< Channel */ -#define _LESENSE_IEN_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ -#define _LESENSE_IEN_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ -#define _LESENSE_IEN_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH13_DEFAULT (_LESENSE_IEN_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH14 (0x1UL << 14) /**< Channel */ -#define _LESENSE_IEN_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ -#define _LESENSE_IEN_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ -#define _LESENSE_IEN_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH14_DEFAULT (_LESENSE_IEN_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH15 (0x1UL << 15) /**< Channel */ -#define _LESENSE_IEN_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ -#define _LESENSE_IEN_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ -#define _LESENSE_IEN_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CH15_DEFAULT (_LESENSE_IEN_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_SCANDONE (0x1UL << 16) /**< Scan Complete */ -#define _LESENSE_IEN_SCANDONE_SHIFT 16 /**< Shift value for LESENSE_SCANDONE */ -#define _LESENSE_IEN_SCANDONE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANDONE */ -#define _LESENSE_IEN_SCANDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_SCANDONE_DEFAULT (_LESENSE_IEN_SCANDONE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_DEC (0x1UL << 17) /**< Decoder */ -#define _LESENSE_IEN_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ -#define _LESENSE_IEN_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ -#define _LESENSE_IEN_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_DEC_DEFAULT (_LESENSE_IEN_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_RESWL (0x1UL << 18) /**< Result Watermark Level */ -#define _LESENSE_IEN_RESWL_SHIFT 18 /**< Shift value for LESENSE_RESWL */ -#define _LESENSE_IEN_RESWL_MASK 0x40000UL /**< Bit mask for LESENSE_RESWL */ -#define _LESENSE_IEN_RESWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_RESWL_DEFAULT (_LESENSE_IEN_RESWL_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_RESOF (0x1UL << 19) /**< Result Overflow */ -#define _LESENSE_IEN_RESOF_SHIFT 19 /**< Shift value for LESENSE_RESOF */ -#define _LESENSE_IEN_RESOF_MASK 0x80000UL /**< Bit mask for LESENSE_RESOF */ -#define _LESENSE_IEN_RESOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_RESOF_DEFAULT (_LESENSE_IEN_RESOF_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CNTOF (0x1UL << 20) /**< Counter Overflow */ -#define _LESENSE_IEN_CNTOF_SHIFT 20 /**< Shift value for LESENSE_CNTOF */ -#define _LESENSE_IEN_CNTOF_MASK 0x100000UL /**< Bit mask for LESENSE_CNTOF */ -#define _LESENSE_IEN_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_CNTOF_DEFAULT (_LESENSE_IEN_CNTOF_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_RESUF (0x1UL << 21) /**< Result Underflow */ -#define _LESENSE_IEN_RESUF_SHIFT 21 /**< Shift value for LESENSE_RESUF */ -#define _LESENSE_IEN_RESUF_MASK 0x200000UL /**< Bit mask for LESENSE_RESUF */ -#define _LESENSE_IEN_RESUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ -#define LESENSE_IEN_RESUF_DEFAULT (_LESENSE_IEN_RESUF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define _LESENSE_IEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IEN */ +#define _LESENSE_IEN_MASK 0x003FFFFFUL /**< Mask for LESENSE_IEN */ +#define LESENSE_IEN_CH0 (0x1UL << 0) /**< Channel */ +#define _LESENSE_IEN_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH0_DEFAULT (_LESENSE_IEN_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1 (0x1UL << 1) /**< Channel */ +#define _LESENSE_IEN_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1_DEFAULT (_LESENSE_IEN_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2 (0x1UL << 2) /**< Channel */ +#define _LESENSE_IEN_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2_DEFAULT (_LESENSE_IEN_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3 (0x1UL << 3) /**< Channel */ +#define _LESENSE_IEN_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3_DEFAULT (_LESENSE_IEN_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4 (0x1UL << 4) /**< Channel */ +#define _LESENSE_IEN_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4_DEFAULT (_LESENSE_IEN_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5 (0x1UL << 5) /**< Channel */ +#define _LESENSE_IEN_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5_DEFAULT (_LESENSE_IEN_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6 (0x1UL << 6) /**< Channel */ +#define _LESENSE_IEN_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6_DEFAULT (_LESENSE_IEN_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7 (0x1UL << 7) /**< Channel */ +#define _LESENSE_IEN_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7_DEFAULT (_LESENSE_IEN_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8 (0x1UL << 8) /**< Channel */ +#define _LESENSE_IEN_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8_DEFAULT (_LESENSE_IEN_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9 (0x1UL << 9) /**< Channel */ +#define _LESENSE_IEN_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9_DEFAULT (_LESENSE_IEN_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10 (0x1UL << 10) /**< Channel */ +#define _LESENSE_IEN_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10_DEFAULT (_LESENSE_IEN_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11 (0x1UL << 11) /**< Channel */ +#define _LESENSE_IEN_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11_DEFAULT (_LESENSE_IEN_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12 (0x1UL << 12) /**< Channel */ +#define _LESENSE_IEN_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12_DEFAULT (_LESENSE_IEN_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13 (0x1UL << 13) /**< Channel */ +#define _LESENSE_IEN_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13_DEFAULT (_LESENSE_IEN_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14 (0x1UL << 14) /**< Channel */ +#define _LESENSE_IEN_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14_DEFAULT (_LESENSE_IEN_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15 (0x1UL << 15) /**< Channel */ +#define _LESENSE_IEN_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15_DEFAULT (_LESENSE_IEN_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANDONE (0x1UL << 16) /**< Scan Complete */ +#define _LESENSE_IEN_SCANDONE_SHIFT 16 /**< Shift value for LESENSE_SCANDONE */ +#define _LESENSE_IEN_SCANDONE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANDONE */ +#define _LESENSE_IEN_SCANDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANDONE_DEFAULT (_LESENSE_IEN_SCANDONE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC (0x1UL << 17) /**< Decoder */ +#define _LESENSE_IEN_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC_DEFAULT (_LESENSE_IEN_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESWL (0x1UL << 18) /**< Result Watermark Level */ +#define _LESENSE_IEN_RESWL_SHIFT 18 /**< Shift value for LESENSE_RESWL */ +#define _LESENSE_IEN_RESWL_MASK 0x40000UL /**< Bit mask for LESENSE_RESWL */ +#define _LESENSE_IEN_RESWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESWL_DEFAULT (_LESENSE_IEN_RESWL_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESOF (0x1UL << 19) /**< Result Overflow */ +#define _LESENSE_IEN_RESOF_SHIFT 19 /**< Shift value for LESENSE_RESOF */ +#define _LESENSE_IEN_RESOF_MASK 0x80000UL /**< Bit mask for LESENSE_RESOF */ +#define _LESENSE_IEN_RESOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESOF_DEFAULT (_LESENSE_IEN_RESOF_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF (0x1UL << 20) /**< Counter Overflow */ +#define _LESENSE_IEN_CNTOF_SHIFT 20 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_MASK 0x100000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF_DEFAULT (_LESENSE_IEN_CNTOF_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESUF (0x1UL << 21) /**< Result Underflow */ +#define _LESENSE_IEN_RESUF_SHIFT 21 /**< Shift value for LESENSE_RESUF */ +#define _LESENSE_IEN_RESUF_MASK 0x200000UL /**< Bit mask for LESENSE_RESUF */ +#define _LESENSE_IEN_RESUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESUF_DEFAULT (_LESENSE_IEN_RESUF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IEN */ /* Bit fields for LESENSE CH_TIMING */ -#define _LESENSE_CH_TIMING_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_TIMING */ -#define _LESENSE_CH_TIMING_MASK 0x00FFFFFFUL /**< Mask for LESENSE_CH_TIMING */ -#define _LESENSE_CH_TIMING_EXTIME_SHIFT 0 /**< Shift value for LESENSE_EXTIME */ -#define _LESENSE_CH_TIMING_EXTIME_MASK 0x3FUL /**< Bit mask for LESENSE_EXTIME */ -#define _LESENSE_CH_TIMING_EXTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ -#define LESENSE_CH_TIMING_EXTIME_DEFAULT (_LESENSE_CH_TIMING_EXTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ -#define _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT 6 /**< Shift value for LESENSE_SAMPLEDLY */ -#define _LESENSE_CH_TIMING_SAMPLEDLY_MASK 0x3FC0UL /**< Bit mask for LESENSE_SAMPLEDLY */ -#define _LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ -#define LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT (_LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ -#define _LESENSE_CH_TIMING_MEASUREDLY_SHIFT 14 /**< Shift value for LESENSE_MEASUREDLY */ -#define _LESENSE_CH_TIMING_MEASUREDLY_MASK 0xFFC000UL /**< Bit mask for LESENSE_MEASUREDLY */ -#define _LESENSE_CH_TIMING_MEASUREDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ -#define LESENSE_CH_TIMING_MEASUREDLY_DEFAULT (_LESENSE_CH_TIMING_MEASUREDLY_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MASK 0x00FFFFFFUL /**< Mask for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_EXTIME_SHIFT 0 /**< Shift value for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_MASK 0x3FUL /**< Bit mask for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_EXTIME_DEFAULT (_LESENSE_CH_TIMING_EXTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT 6 /**< Shift value for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_MASK 0x3FC0UL /**< Bit mask for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT (_LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MEASUREDLY_SHIFT 14 /**< Shift value for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_MASK 0xFFC000UL /**< Bit mask for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_MEASUREDLY_DEFAULT (_LESENSE_CH_TIMING_MEASUREDLY_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ /* Bit fields for LESENSE CH_INTERACT */ -#define _LESENSE_CH_INTERACT_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_MASK 0x3FFF0FFFUL /**< Mask for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_THRES_SHIFT 0 /**< Shift value for LESENSE_THRES */ -#define _LESENSE_CH_INTERACT_THRES_MASK 0xFFFUL /**< Bit mask for LESENSE_THRES */ -#define _LESENSE_CH_INTERACT_THRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_THRES_DEFAULT (_LESENSE_CH_INTERACT_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ -#define _LESENSE_CH_INTERACT_EXMODE_SHIFT 16 /**< Shift value for LESENSE_EXMODE */ -#define _LESENSE_CH_INTERACT_EXMODE_MASK 0x30000UL /**< Bit mask for LESENSE_EXMODE */ -#define _LESENSE_CH_INTERACT_EXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_EXMODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_EXMODE_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_EXMODE_LOW 0x00000002UL /**< Mode LOW for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_EXMODE_DACOUT 0x00000003UL /**< Mode DACOUT for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_EXMODE_DEFAULT (_LESENSE_CH_INTERACT_EXMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_EXMODE_DISABLE (_LESENSE_CH_INTERACT_EXMODE_DISABLE << 16) /**< Shifted mode DISABLE for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_EXMODE_HIGH (_LESENSE_CH_INTERACT_EXMODE_HIGH << 16) /**< Shifted mode HIGH for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_EXMODE_LOW (_LESENSE_CH_INTERACT_EXMODE_LOW << 16) /**< Shifted mode LOW for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_EXMODE_DACOUT (_LESENSE_CH_INTERACT_EXMODE_DACOUT << 16) /**< Shifted mode DACOUT for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_ALTEX (0x1UL << 18) /**< Use alternative excite pin */ -#define _LESENSE_CH_INTERACT_ALTEX_SHIFT 18 /**< Shift value for LESENSE_ALTEX */ -#define _LESENSE_CH_INTERACT_ALTEX_MASK 0x40000UL /**< Bit mask for LESENSE_ALTEX */ -#define _LESENSE_CH_INTERACT_ALTEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_ALTEX_DEFAULT (_LESENSE_CH_INTERACT_ALTEX_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_SAMPLECLK (0x1UL << 19) /**< Select clock used for timing of sample d */ -#define _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT 19 /**< Shift value for LESENSE_SAMPLECLK */ -#define _LESENSE_CH_INTERACT_SAMPLECLK_MASK 0x80000UL /**< Bit mask for LESENSE_SAMPLECLK */ -#define _LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SAMPLECLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT (_LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_SAMPLECLK_LFACLK (_LESENSE_CH_INTERACT_SAMPLECLK_LFACLK << 19) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO (_LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO << 19) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_EXCLK (0x1UL << 20) /**< Select clock used for excitation timing */ -#define _LESENSE_CH_INTERACT_EXCLK_SHIFT 20 /**< Shift value for LESENSE_EXCLK */ -#define _LESENSE_CH_INTERACT_EXCLK_MASK 0x100000UL /**< Bit mask for LESENSE_EXCLK */ -#define _LESENSE_CH_INTERACT_EXCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_EXCLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_EXCLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_EXCLK_DEFAULT (_LESENSE_CH_INTERACT_EXCLK_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_EXCLK_LFACLK (_LESENSE_CH_INTERACT_EXCLK_LFACLK << 20) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_EXCLK_AUXHFRCO (_LESENSE_CH_INTERACT_EXCLK_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT*/ -#define _LESENSE_CH_INTERACT_SETIF_SHIFT 21 /**< Shift value for LESENSE_SETIF */ -#define _LESENSE_CH_INTERACT_SETIF_MASK 0xE00000UL /**< Bit mask for LESENSE_SETIF */ -#define _LESENSE_CH_INTERACT_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SETIF_NONE 0x00000000UL /**< Mode NONE for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SETIF_LEVEL 0x00000001UL /**< Mode LEVEL for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SETIF_POSEDGE 0x00000002UL /**< Mode POSEDGE for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SETIF_NEGEDGE 0x00000003UL /**< Mode NEGEDGE for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SETIF_BOTHEDGES 0x00000004UL /**< Mode BOTHEDGES for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_SETIF_DEFAULT (_LESENSE_CH_INTERACT_SETIF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_SETIF_NONE (_LESENSE_CH_INTERACT_SETIF_NONE << 21) /**< Shifted mode NONE for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_SETIF_LEVEL (_LESENSE_CH_INTERACT_SETIF_LEVEL << 21) /**< Shifted mode LEVEL for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_SETIF_POSEDGE (_LESENSE_CH_INTERACT_SETIF_POSEDGE << 21) /**< Shifted mode POSEDGE for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_SETIF_NEGEDGE (_LESENSE_CH_INTERACT_SETIF_NEGEDGE << 21) /**< Shifted mode NEGEDGE for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_SETIF_BOTHEDGES (_LESENSE_CH_INTERACT_SETIF_BOTHEDGES << 21) /**< Shifted mode BOTHEDGES for LESENSE_CH_INTERACT*/ -#define _LESENSE_CH_INTERACT_OFFSET_SHIFT 24 /**< Shift value for LESENSE_OFFSET */ -#define _LESENSE_CH_INTERACT_OFFSET_MASK 0xF000000UL /**< Bit mask for LESENSE_OFFSET */ -#define _LESENSE_CH_INTERACT_OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_OFFSET_DEFAULT (_LESENSE_CH_INTERACT_OFFSET_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ -#define _LESENSE_CH_INTERACT_SAMPLE_SHIFT 28 /**< Shift value for LESENSE_SAMPLE */ -#define _LESENSE_CH_INTERACT_SAMPLE_MASK 0x30000000UL /**< Bit mask for LESENSE_SAMPLE */ -#define _LESENSE_CH_INTERACT_SAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT 0x00000000UL /**< Mode ACMPCOUNT for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SAMPLE_ACMP 0x00000001UL /**< Mode ACMP for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SAMPLE_ADC 0x00000002UL /**< Mode ADC for LESENSE_CH_INTERACT */ -#define _LESENSE_CH_INTERACT_SAMPLE_ADCDIFF 0x00000003UL /**< Mode ADCDIFF for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_SAMPLE_DEFAULT (_LESENSE_CH_INTERACT_SAMPLE_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT (_LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT << 28) /**< Shifted mode ACMPCOUNT for LESENSE_CH_INTERACT*/ -#define LESENSE_CH_INTERACT_SAMPLE_ACMP (_LESENSE_CH_INTERACT_SAMPLE_ACMP << 28) /**< Shifted mode ACMP for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_SAMPLE_ADC (_LESENSE_CH_INTERACT_SAMPLE_ADC << 28) /**< Shifted mode ADC for LESENSE_CH_INTERACT */ -#define LESENSE_CH_INTERACT_SAMPLE_ADCDIFF (_LESENSE_CH_INTERACT_SAMPLE_ADCDIFF << 28) /**< Shifted mode ADCDIFF for LESENSE_CH_INTERACT*/ +#define _LESENSE_CH_INTERACT_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_MASK 0x3FFF0FFFUL /**< Mask for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_THRES_SHIFT 0 /**< Shift value for LESENSE_THRES */ +#define _LESENSE_CH_INTERACT_THRES_MASK 0xFFFUL /**< Bit mask for LESENSE_THRES */ +#define _LESENSE_CH_INTERACT_THRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_THRES_DEFAULT (_LESENSE_CH_INTERACT_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define _LESENSE_CH_INTERACT_EXMODE_SHIFT 16 /**< Shift value for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_MASK 0x30000UL /**< Bit mask for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_LOW 0x00000002UL /**< Mode LOW for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DACOUT 0x00000003UL /**< Mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DEFAULT (_LESENSE_CH_INTERACT_EXMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_EXMODE_DISABLE (_LESENSE_CH_INTERACT_EXMODE_DISABLE << 16) /**< Shifted mode DISABLE for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_EXMODE_HIGH (_LESENSE_CH_INTERACT_EXMODE_HIGH << 16) /**< Shifted mode HIGH for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_LOW (_LESENSE_CH_INTERACT_EXMODE_LOW << 16) /**< Shifted mode LOW for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DACOUT (_LESENSE_CH_INTERACT_EXMODE_DACOUT << 16) /**< Shifted mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX (0x1UL << 18) /**< Use alternative excite pin */ +#define _LESENSE_CH_INTERACT_ALTEX_SHIFT 18 /**< Shift value for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_MASK 0x40000UL /**< Bit mask for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX_DEFAULT (_LESENSE_CH_INTERACT_ALTEX_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SAMPLECLK (0x1UL << 19) /**< Select clock used for timing of sample d */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT 19 /**< Shift value for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_MASK 0x80000UL /**< Bit mask for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT (_LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SAMPLECLK_LFACLK (_LESENSE_CH_INTERACT_SAMPLECLK_LFACLK << 19) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO (_LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO << 19) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_EXCLK (0x1UL << 20) /**< Select clock used for excitation timing */ +#define _LESENSE_CH_INTERACT_EXCLK_SHIFT 20 /**< Shift value for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_MASK 0x100000UL /**< Bit mask for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_DEFAULT (_LESENSE_CH_INTERACT_EXCLK_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_EXCLK_LFACLK (_LESENSE_CH_INTERACT_EXCLK_LFACLK << 20) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_AUXHFRCO (_LESENSE_CH_INTERACT_EXCLK_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT*/ +#define _LESENSE_CH_INTERACT_SETIF_SHIFT 21 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_MASK 0xE00000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NONE 0x00000000UL /**< Mode NONE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_LEVEL 0x00000001UL /**< Mode LEVEL for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_POSEDGE 0x00000002UL /**< Mode POSEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NEGEDGE 0x00000003UL /**< Mode NEGEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_BOTHEDGES 0x00000004UL /**< Mode BOTHEDGES for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_DEFAULT (_LESENSE_CH_INTERACT_SETIF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SETIF_NONE (_LESENSE_CH_INTERACT_SETIF_NONE << 21) /**< Shifted mode NONE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_LEVEL (_LESENSE_CH_INTERACT_SETIF_LEVEL << 21) /**< Shifted mode LEVEL for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_POSEDGE (_LESENSE_CH_INTERACT_SETIF_POSEDGE << 21) /**< Shifted mode POSEDGE for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SETIF_NEGEDGE (_LESENSE_CH_INTERACT_SETIF_NEGEDGE << 21) /**< Shifted mode NEGEDGE for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SETIF_BOTHEDGES (_LESENSE_CH_INTERACT_SETIF_BOTHEDGES << 21) /**< Shifted mode BOTHEDGES for LESENSE_CH_INTERACT*/ +#define _LESENSE_CH_INTERACT_OFFSET_SHIFT 24 /**< Shift value for LESENSE_OFFSET */ +#define _LESENSE_CH_INTERACT_OFFSET_MASK 0xF000000UL /**< Bit mask for LESENSE_OFFSET */ +#define _LESENSE_CH_INTERACT_OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_OFFSET_DEFAULT (_LESENSE_CH_INTERACT_OFFSET_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define _LESENSE_CH_INTERACT_SAMPLE_SHIFT 28 /**< Shift value for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_MASK 0x30000000UL /**< Bit mask for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT 0x00000000UL /**< Mode ACMPCOUNT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ACMP 0x00000001UL /**< Mode ACMP for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ADC 0x00000002UL /**< Mode ADC for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ADCDIFF 0x00000003UL /**< Mode ADCDIFF for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_DEFAULT (_LESENSE_CH_INTERACT_SAMPLE_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT (_LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT << 28) /**< Shifted mode ACMPCOUNT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SAMPLE_ACMP (_LESENSE_CH_INTERACT_SAMPLE_ACMP << 28) /**< Shifted mode ACMP for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ADC (_LESENSE_CH_INTERACT_SAMPLE_ADC << 28) /**< Shifted mode ADC for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ADCDIFF (_LESENSE_CH_INTERACT_SAMPLE_ADCDIFF << 28) /**< Shifted mode ADCDIFF for LESENSE_CH_INTERACT*/ /* Bit fields for LESENSE CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_MASK 0x0000037CUL /**< Mask for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_DECODE (0x1UL << 2) /**< Send result to decoder */ -#define _LESENSE_CH_EVALCFG_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */ -#define _LESENSE_CH_EVALCFG_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */ -#define _LESENSE_CH_EVALCFG_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_DECODE_DEFAULT (_LESENSE_CH_EVALCFG_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_COMP (0x1UL << 3) /**< Select mode for threshold comparison */ -#define _LESENSE_CH_EVALCFG_COMP_SHIFT 3 /**< Shift value for LESENSE_COMP */ -#define _LESENSE_CH_EVALCFG_COMP_MASK 0x8UL /**< Bit mask for LESENSE_COMP */ -#define _LESENSE_CH_EVALCFG_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_COMP_LESS 0x00000000UL /**< Mode LESS for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_COMP_GE 0x00000001UL /**< Mode GE for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_COMP_DEFAULT (_LESENSE_CH_EVALCFG_COMP_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_COMP_LESS (_LESENSE_CH_EVALCFG_COMP_LESS << 3) /**< Shifted mode LESS for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_COMP_GE (_LESENSE_CH_EVALCFG_COMP_GE << 3) /**< Shifted mode GE for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_STRSAMPLE_SHIFT 4 /**< Shift value for LESENSE_STRSAMPLE */ -#define _LESENSE_CH_EVALCFG_STRSAMPLE_MASK 0x30UL /**< Bit mask for LESENSE_STRSAMPLE */ -#define _LESENSE_CH_EVALCFG_STRSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_STRSAMPLE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_STRSAMPLE_DATA 0x00000001UL /**< Mode DATA for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_STRSAMPLE_DATASRC 0x00000002UL /**< Mode DATASRC for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_STRSAMPLE_DEFAULT (_LESENSE_CH_EVALCFG_STRSAMPLE_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_STRSAMPLE_DISABLE (_LESENSE_CH_EVALCFG_STRSAMPLE_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_STRSAMPLE_DATA (_LESENSE_CH_EVALCFG_STRSAMPLE_DATA << 4) /**< Shifted mode DATA for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_STRSAMPLE_DATASRC (_LESENSE_CH_EVALCFG_STRSAMPLE_DATASRC << 4) /**< Shifted mode DATASRC for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_SCANRESINV (0x1UL << 6) /**< Enable inversion of result */ -#define _LESENSE_CH_EVALCFG_SCANRESINV_SHIFT 6 /**< Shift value for LESENSE_SCANRESINV */ -#define _LESENSE_CH_EVALCFG_SCANRESINV_MASK 0x40UL /**< Bit mask for LESENSE_SCANRESINV */ -#define _LESENSE_CH_EVALCFG_SCANRESINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_SCANRESINV_DEFAULT (_LESENSE_CH_EVALCFG_SCANRESINV_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_MODE_SHIFT 8 /**< Shift value for LESENSE_MODE */ -#define _LESENSE_CH_EVALCFG_MODE_MASK 0x300UL /**< Bit mask for LESENSE_MODE */ -#define _LESENSE_CH_EVALCFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_MODE_THRES 0x00000000UL /**< Mode THRES for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_MODE_SLIDINGWIN 0x00000001UL /**< Mode SLIDINGWIN for LESENSE_CH_EVALCFG */ -#define _LESENSE_CH_EVALCFG_MODE_STEPDET 0x00000002UL /**< Mode STEPDET for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_MODE_DEFAULT (_LESENSE_CH_EVALCFG_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_MODE_THRES (_LESENSE_CH_EVALCFG_MODE_THRES << 8) /**< Shifted mode THRES for LESENSE_CH_EVALCFG */ -#define LESENSE_CH_EVALCFG_MODE_SLIDINGWIN (_LESENSE_CH_EVALCFG_MODE_SLIDINGWIN << 8) /**< Shifted mode SLIDINGWIN for LESENSE_CH_EVALCFG*/ -#define LESENSE_CH_EVALCFG_MODE_STEPDET (_LESENSE_CH_EVALCFG_MODE_STEPDET << 8) /**< Shifted mode STEPDET for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_MASK 0x0000037CUL /**< Mask for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_DECODE (0x1UL << 2) /**< Send result to decoder */ +#define _LESENSE_CH_EVALCFG_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */ +#define _LESENSE_CH_EVALCFG_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */ +#define _LESENSE_CH_EVALCFG_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_DECODE_DEFAULT (_LESENSE_CH_EVALCFG_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_COMP (0x1UL << 3) /**< Select mode for threshold comparison */ +#define _LESENSE_CH_EVALCFG_COMP_SHIFT 3 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_CH_EVALCFG_COMP_MASK 0x8UL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_CH_EVALCFG_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_COMP_LESS 0x00000000UL /**< Mode LESS for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_COMP_GE 0x00000001UL /**< Mode GE for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_COMP_DEFAULT (_LESENSE_CH_EVALCFG_COMP_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_COMP_LESS (_LESENSE_CH_EVALCFG_COMP_LESS << 3) /**< Shifted mode LESS for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_COMP_GE (_LESENSE_CH_EVALCFG_COMP_GE << 3) /**< Shifted mode GE for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_SHIFT 4 /**< Shift value for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_MASK 0x30UL /**< Bit mask for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_DATA 0x00000001UL /**< Mode DATA for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_DATASRC 0x00000002UL /**< Mode DATASRC for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_STRSAMPLE_DEFAULT (_LESENSE_CH_EVALCFG_STRSAMPLE_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_STRSAMPLE_DISABLE (_LESENSE_CH_EVALCFG_STRSAMPLE_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_STRSAMPLE_DATA (_LESENSE_CH_EVALCFG_STRSAMPLE_DATA << 4) /**< Shifted mode DATA for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_STRSAMPLE_DATASRC (_LESENSE_CH_EVALCFG_STRSAMPLE_DATASRC << 4) /**< Shifted mode DATASRC for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_SCANRESINV (0x1UL << 6) /**< Enable inversion of result */ +#define _LESENSE_CH_EVALCFG_SCANRESINV_SHIFT 6 /**< Shift value for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVALCFG_SCANRESINV_MASK 0x40UL /**< Bit mask for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVALCFG_SCANRESINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_SCANRESINV_DEFAULT (_LESENSE_CH_EVALCFG_SCANRESINV_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_MODE_SHIFT 8 /**< Shift value for LESENSE_MODE */ +#define _LESENSE_CH_EVALCFG_MODE_MASK 0x300UL /**< Bit mask for LESENSE_MODE */ +#define _LESENSE_CH_EVALCFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_MODE_THRES 0x00000000UL /**< Mode THRES for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_MODE_SLIDINGWIN 0x00000001UL /**< Mode SLIDINGWIN for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_MODE_STEPDET 0x00000002UL /**< Mode STEPDET for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_MODE_DEFAULT (_LESENSE_CH_EVALCFG_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_MODE_THRES (_LESENSE_CH_EVALCFG_MODE_THRES << 8) /**< Shifted mode THRES for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_MODE_SLIDINGWIN (_LESENSE_CH_EVALCFG_MODE_SLIDINGWIN << 8) /**< Shifted mode SLIDINGWIN for LESENSE_CH_EVALCFG*/ +#define LESENSE_CH_EVALCFG_MODE_STEPDET (_LESENSE_CH_EVALCFG_MODE_STEPDET << 8) /**< Shifted mode STEPDET for LESENSE_CH_EVALCFG */ /* Bit fields for LESENSE CH_EVALTHRES */ -#define _LESENSE_CH_EVALTHRES_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_EVALTHRES */ -#define _LESENSE_CH_EVALTHRES_MASK 0x0000FFFFUL /**< Mask for LESENSE_CH_EVALTHRES */ -#define _LESENSE_CH_EVALTHRES_EVALTHRES_SHIFT 0 /**< Shift value for LESENSE_EVALTHRES */ -#define _LESENSE_CH_EVALTHRES_EVALTHRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_EVALTHRES */ -#define _LESENSE_CH_EVALTHRES_EVALTHRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALTHRES */ -#define LESENSE_CH_EVALTHRES_EVALTHRES_DEFAULT (_LESENSE_CH_EVALTHRES_EVALTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_EVALTHRES*/ +#define _LESENSE_CH_EVALTHRES_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_EVALTHRES */ +#define _LESENSE_CH_EVALTHRES_MASK 0x0000FFFFUL /**< Mask for LESENSE_CH_EVALTHRES */ +#define _LESENSE_CH_EVALTHRES_EVALTHRES_SHIFT 0 /**< Shift value for LESENSE_EVALTHRES */ +#define _LESENSE_CH_EVALTHRES_EVALTHRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_EVALTHRES */ +#define _LESENSE_CH_EVALTHRES_EVALTHRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALTHRES */ +#define LESENSE_CH_EVALTHRES_EVALTHRES_DEFAULT (_LESENSE_CH_EVALTHRES_EVALTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_EVALTHRES*/ /* Bit fields for LESENSE ST_ARC */ -#define _LESENSE_ST_ARC_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_MASK 0x003FFFFFUL /**< Mask for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_SCOMP_SHIFT 0 /**< Shift value for LESENSE_SCOMP */ -#define _LESENSE_ST_ARC_SCOMP_MASK 0xFUL /**< Bit mask for LESENSE_SCOMP */ -#define _LESENSE_ST_ARC_SCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_SCOMP_DEFAULT (_LESENSE_ST_ARC_SCOMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_SMASK_SHIFT 4 /**< Shift value for LESENSE_SMASK */ -#define _LESENSE_ST_ARC_SMASK_MASK 0xF0UL /**< Bit mask for LESENSE_SMASK */ -#define _LESENSE_ST_ARC_SMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_SMASK_DEFAULT (_LESENSE_ST_ARC_SMASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_CURSTATE_SHIFT 8 /**< Shift value for LESENSE_CURSTATE */ -#define _LESENSE_ST_ARC_CURSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_CURSTATE */ -#define _LESENSE_ST_ARC_CURSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_CURSTATE_DEFAULT (_LESENSE_ST_ARC_CURSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_SHIFT 13 /**< Shift value for LESENSE_PRSACT */ -#define _LESENSE_ST_ARC_PRSACT_MASK 0xE000UL /**< Bit mask for LESENSE_PRSACT */ -#define _LESENSE_ST_ARC_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_DEFAULT (_LESENSE_ST_ARC_PRSACT_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_NONE (_LESENSE_ST_ARC_PRSACT_NONE << 13) /**< Shifted mode NONE for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_PRS0 (_LESENSE_ST_ARC_PRSACT_PRS0 << 13) /**< Shifted mode PRS0 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_UP (_LESENSE_ST_ARC_PRSACT_UP << 13) /**< Shifted mode UP for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_PRS1 (_LESENSE_ST_ARC_PRSACT_PRS1 << 13) /**< Shifted mode PRS1 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_DOWN (_LESENSE_ST_ARC_PRSACT_DOWN << 13) /**< Shifted mode DOWN for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_PRS01 (_LESENSE_ST_ARC_PRSACT_PRS01 << 13) /**< Shifted mode PRS01 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_PRS2 (_LESENSE_ST_ARC_PRSACT_PRS2 << 13) /**< Shifted mode PRS2 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_PRS02 (_LESENSE_ST_ARC_PRSACT_PRS02 << 13) /**< Shifted mode PRS02 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_UPANDPRS2 (_LESENSE_ST_ARC_PRSACT_UPANDPRS2 << 13) /**< Shifted mode UPANDPRS2 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_PRS12 (_LESENSE_ST_ARC_PRSACT_PRS12 << 13) /**< Shifted mode PRS12 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_DOWNANDPRS2 (_LESENSE_ST_ARC_PRSACT_DOWNANDPRS2 << 13) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_PRSACT_PRS012 (_LESENSE_ST_ARC_PRSACT_PRS012 << 13) /**< Shifted mode PRS012 for LESENSE_ST_ARC */ -#define _LESENSE_ST_ARC_NEXTSTATE_SHIFT 16 /**< Shift value for LESENSE_NEXTSTATE */ -#define _LESENSE_ST_ARC_NEXTSTATE_MASK 0x1F0000UL /**< Bit mask for LESENSE_NEXTSTATE */ -#define _LESENSE_ST_ARC_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_NEXTSTATE_DEFAULT (_LESENSE_ST_ARC_NEXTSTATE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_SETIF (0x1UL << 21) /**< Set interrupt flag */ -#define _LESENSE_ST_ARC_SETIF_SHIFT 21 /**< Shift value for LESENSE_SETIF */ -#define _LESENSE_ST_ARC_SETIF_MASK 0x200000UL /**< Bit mask for LESENSE_SETIF */ -#define _LESENSE_ST_ARC_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ -#define LESENSE_ST_ARC_SETIF_DEFAULT (_LESENSE_ST_ARC_SETIF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_MASK 0x003FFFFFUL /**< Mask for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_SCOMP_SHIFT 0 /**< Shift value for LESENSE_SCOMP */ +#define _LESENSE_ST_ARC_SCOMP_MASK 0xFUL /**< Bit mask for LESENSE_SCOMP */ +#define _LESENSE_ST_ARC_SCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_SCOMP_DEFAULT (_LESENSE_ST_ARC_SCOMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_SMASK_SHIFT 4 /**< Shift value for LESENSE_SMASK */ +#define _LESENSE_ST_ARC_SMASK_MASK 0xF0UL /**< Bit mask for LESENSE_SMASK */ +#define _LESENSE_ST_ARC_SMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_SMASK_DEFAULT (_LESENSE_ST_ARC_SMASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_CURSTATE_SHIFT 8 /**< Shift value for LESENSE_CURSTATE */ +#define _LESENSE_ST_ARC_CURSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_CURSTATE */ +#define _LESENSE_ST_ARC_CURSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_CURSTATE_DEFAULT (_LESENSE_ST_ARC_CURSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_SHIFT 13 /**< Shift value for LESENSE_PRSACT */ +#define _LESENSE_ST_ARC_PRSACT_MASK 0xE000UL /**< Bit mask for LESENSE_PRSACT */ +#define _LESENSE_ST_ARC_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_DEFAULT (_LESENSE_ST_ARC_PRSACT_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_NONE (_LESENSE_ST_ARC_PRSACT_NONE << 13) /**< Shifted mode NONE for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS0 (_LESENSE_ST_ARC_PRSACT_PRS0 << 13) /**< Shifted mode PRS0 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_UP (_LESENSE_ST_ARC_PRSACT_UP << 13) /**< Shifted mode UP for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS1 (_LESENSE_ST_ARC_PRSACT_PRS1 << 13) /**< Shifted mode PRS1 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_DOWN (_LESENSE_ST_ARC_PRSACT_DOWN << 13) /**< Shifted mode DOWN for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS01 (_LESENSE_ST_ARC_PRSACT_PRS01 << 13) /**< Shifted mode PRS01 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS2 (_LESENSE_ST_ARC_PRSACT_PRS2 << 13) /**< Shifted mode PRS2 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS02 (_LESENSE_ST_ARC_PRSACT_PRS02 << 13) /**< Shifted mode PRS02 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_UPANDPRS2 (_LESENSE_ST_ARC_PRSACT_UPANDPRS2 << 13) /**< Shifted mode UPANDPRS2 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS12 (_LESENSE_ST_ARC_PRSACT_PRS12 << 13) /**< Shifted mode PRS12 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_DOWNANDPRS2 (_LESENSE_ST_ARC_PRSACT_DOWNANDPRS2 << 13) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS012 (_LESENSE_ST_ARC_PRSACT_PRS012 << 13) /**< Shifted mode PRS012 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_NEXTSTATE_SHIFT 16 /**< Shift value for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_ARC_NEXTSTATE_MASK 0x1F0000UL /**< Bit mask for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_ARC_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_NEXTSTATE_DEFAULT (_LESENSE_ST_ARC_NEXTSTATE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_SETIF (0x1UL << 21) /**< Set interrupt flag */ +#define _LESENSE_ST_ARC_SETIF_SHIFT 21 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_ST_ARC_SETIF_MASK 0x200000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_ST_ARC_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_SETIF_DEFAULT (_LESENSE_ST_ARC_SETIF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ /** @} End of group EFR32SG28_LESENSE_BitFields */ /** @} End of group EFR32SG28_LESENSE */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_letimer.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_letimer.h index 1cbbef3091..c4bfbe489c 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_letimer.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_letimer.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_LETIMER_H #define EFR32SG28_LETIMER_H - #define LETIMER_HAS_SET_CLEAR /**************************************************************************//** @@ -43,87 +42,86 @@ *****************************************************************************/ /** LETIMER Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version */ - __IOM uint32_t EN; /**< module en */ - __IOM uint32_t SWRST; /**< Software Reset Register */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t CNT; /**< Counter Value Register */ - __IOM uint32_t COMP0; /**< Compare Value Register 0 */ - __IOM uint32_t COMP1; /**< Compare Value Register 1 */ - __IOM uint32_t TOP; /**< Counter TOP Value Register */ - __IOM uint32_t TOPBUFF; /**< Buffered Counter TOP Value */ - __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ - __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - __IOM uint32_t PRSMODE; /**< PRS Input mode select Register */ - uint32_t RESERVED1[1003U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version */ - __IOM uint32_t EN_SET; /**< module en */ - __IOM uint32_t SWRST_SET; /**< Software Reset Register */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t CNT_SET; /**< Counter Value Register */ - __IOM uint32_t COMP0_SET; /**< Compare Value Register 0 */ - __IOM uint32_t COMP1_SET; /**< Compare Value Register 1 */ - __IOM uint32_t TOP_SET; /**< Counter TOP Value Register */ - __IOM uint32_t TOPBUFF_SET; /**< Buffered Counter TOP Value */ - __IOM uint32_t REP0_SET; /**< Repeat Counter Register 0 */ - __IOM uint32_t REP1_SET; /**< Repeat Counter Register 1 */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - uint32_t RESERVED2[3U]; /**< Reserved for future use */ - __IOM uint32_t PRSMODE_SET; /**< PRS Input mode select Register */ - uint32_t RESERVED3[1003U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version */ - __IOM uint32_t EN_CLR; /**< module en */ - __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t CNT_CLR; /**< Counter Value Register */ - __IOM uint32_t COMP0_CLR; /**< Compare Value Register 0 */ - __IOM uint32_t COMP1_CLR; /**< Compare Value Register 1 */ - __IOM uint32_t TOP_CLR; /**< Counter TOP Value Register */ - __IOM uint32_t TOPBUFF_CLR; /**< Buffered Counter TOP Value */ - __IOM uint32_t REP0_CLR; /**< Repeat Counter Register 0 */ - __IOM uint32_t REP1_CLR; /**< Repeat Counter Register 1 */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - uint32_t RESERVED4[3U]; /**< Reserved for future use */ - __IOM uint32_t PRSMODE_CLR; /**< PRS Input mode select Register */ - uint32_t RESERVED5[1003U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version */ - __IOM uint32_t EN_TGL; /**< module en */ - __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t CNT_TGL; /**< Counter Value Register */ - __IOM uint32_t COMP0_TGL; /**< Compare Value Register 0 */ - __IOM uint32_t COMP1_TGL; /**< Compare Value Register 1 */ - __IOM uint32_t TOP_TGL; /**< Counter TOP Value Register */ - __IOM uint32_t TOPBUFF_TGL; /**< Buffered Counter TOP Value */ - __IOM uint32_t REP0_TGL; /**< Repeat Counter Register 0 */ - __IOM uint32_t REP1_TGL; /**< Repeat Counter Register 1 */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - uint32_t RESERVED6[3U]; /**< Reserved for future use */ - __IOM uint32_t PRSMODE_TGL; /**< PRS Input mode select Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t EN; /**< module en */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t COMP0; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1; /**< Compare Value Register 1 */ + __IOM uint32_t TOP; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE; /**< PRS Input mode select Register */ + uint32_t RESERVED1[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t EN_SET; /**< module en */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t COMP0_SET; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_SET; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_SET; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_SET; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_SET; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_SET; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_SET; /**< PRS Input mode select Register */ + uint32_t RESERVED3[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t EN_CLR; /**< module en */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t COMP0_CLR; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_CLR; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_CLR; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_CLR; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_CLR; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_CLR; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_CLR; /**< PRS Input mode select Register */ + uint32_t RESERVED5[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t EN_TGL; /**< module en */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t COMP0_TGL; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_TGL; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_TGL; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_TGL; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_TGL; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_TGL; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_TGL; /**< PRS Input mode select Register */ } LETIMER_TypeDef; /** @} End of group EFR32SG28_LETIMER */ @@ -135,399 +133,399 @@ typedef struct *****************************************************************************/ /* Bit fields for LETIMER IPVERSION */ -#define _LETIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LETIMER_IPVERSION */ -#define _LETIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LETIMER_IPVERSION */ -#define _LETIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LETIMER_IPVERSION */ -#define _LETIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LETIMER_IPVERSION */ -#define _LETIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LETIMER_IPVERSION */ -#define LETIMER_IPVERSION_IPVERSION_DEFAULT (_LETIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LETIMER_IPVERSION */ +#define LETIMER_IPVERSION_IPVERSION_DEFAULT (_LETIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IPVERSION */ /* Bit fields for LETIMER EN */ -#define _LETIMER_EN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_EN */ -#define _LETIMER_EN_MASK 0x00000003UL /**< Mask for LETIMER_EN */ -#define LETIMER_EN_EN (0x1UL << 0) /**< module en */ -#define _LETIMER_EN_EN_SHIFT 0 /**< Shift value for LETIMER_EN */ -#define _LETIMER_EN_EN_MASK 0x1UL /**< Bit mask for LETIMER_EN */ -#define _LETIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ -#define LETIMER_EN_EN_DEFAULT (_LETIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_EN */ -#define LETIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _LETIMER_EN_DISABLING_SHIFT 1 /**< Shift value for LETIMER_DISABLING */ -#define _LETIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for LETIMER_DISABLING */ -#define _LETIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ -#define LETIMER_EN_DISABLING_DEFAULT (_LETIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_EN */ +#define _LETIMER_EN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_EN */ +#define _LETIMER_EN_MASK 0x00000003UL /**< Mask for LETIMER_EN */ +#define LETIMER_EN_EN (0x1UL << 0) /**< module en */ +#define _LETIMER_EN_EN_SHIFT 0 /**< Shift value for LETIMER_EN */ +#define _LETIMER_EN_EN_MASK 0x1UL /**< Bit mask for LETIMER_EN */ +#define _LETIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_EN_DEFAULT (_LETIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _LETIMER_EN_DISABLING_SHIFT 1 /**< Shift value for LETIMER_DISABLING */ +#define _LETIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for LETIMER_DISABLING */ +#define _LETIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_DISABLING_DEFAULT (_LETIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_EN */ /* Bit fields for LETIMER SWRST */ -#define _LETIMER_SWRST_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SWRST */ -#define _LETIMER_SWRST_MASK 0x00000003UL /**< Mask for LETIMER_SWRST */ -#define LETIMER_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ -#define _LETIMER_SWRST_SWRST_SHIFT 0 /**< Shift value for LETIMER_SWRST */ -#define _LETIMER_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LETIMER_SWRST */ -#define _LETIMER_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ -#define LETIMER_SWRST_SWRST_DEFAULT (_LETIMER_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SWRST */ -#define LETIMER_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ -#define _LETIMER_SWRST_RESETTING_SHIFT 1 /**< Shift value for LETIMER_RESETTING */ -#define _LETIMER_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LETIMER_RESETTING */ -#define _LETIMER_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ -#define LETIMER_SWRST_RESETTING_DEFAULT (_LETIMER_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SWRST */ +#define _LETIMER_SWRST_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SWRST */ +#define _LETIMER_SWRST_MASK 0x00000003UL /**< Mask for LETIMER_SWRST */ +#define LETIMER_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _LETIMER_SWRST_SWRST_SHIFT 0 /**< Shift value for LETIMER_SWRST */ +#define _LETIMER_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LETIMER_SWRST */ +#define _LETIMER_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_SWRST_DEFAULT (_LETIMER_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _LETIMER_SWRST_RESETTING_SHIFT 1 /**< Shift value for LETIMER_RESETTING */ +#define _LETIMER_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LETIMER_RESETTING */ +#define _LETIMER_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_RESETTING_DEFAULT (_LETIMER_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SWRST */ /* Bit fields for LETIMER CTRL */ -#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ -#define _LETIMER_CTRL_MASK 0x000F13FFUL /**< Mask for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ -#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ -#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ -#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ -#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ -#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ -#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ -#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ -#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ -#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ -#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ -#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ -#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ -#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ -#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ -#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ -#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_BUFTOP_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_BUFTOP_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_BUFTOP_DISABLE (_LETIMER_CTRL_BUFTOP_DISABLE << 8) /**< Shifted mode DISABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_BUFTOP_ENABLE (_LETIMER_CTRL_BUFTOP_ENABLE << 8) /**< Shifted mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTTOPEN (0x1UL << 9) /**< Compare Value 0 Is Top Value */ -#define _LETIMER_CTRL_CNTTOPEN_SHIFT 9 /**< Shift value for LETIMER_CNTTOPEN */ -#define _LETIMER_CTRL_CNTTOPEN_MASK 0x200UL /**< Bit mask for LETIMER_CNTTOPEN */ -#define _LETIMER_CTRL_CNTTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTTOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTTOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTTOPEN_DEFAULT (_LETIMER_CTRL_CNTTOPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTTOPEN_DISABLE (_LETIMER_CTRL_CNTTOPEN_DISABLE << 9) /**< Shifted mode DISABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTTOPEN_ENABLE (_LETIMER_CTRL_CNTTOPEN_ENABLE << 9) /**< Shifted mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ -#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ -#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ -#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUGRUN_DISABLE (_LETIMER_CTRL_DEBUGRUN_DISABLE << 12) /**< Shifted mode DISABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUGRUN_ENABLE (_LETIMER_CTRL_DEBUGRUN_ENABLE << 12) /**< Shifted mode ENABLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_SHIFT 16 /**< Shift value for LETIMER_CNTPRESC */ -#define _LETIMER_CTRL_CNTPRESC_MASK 0xF0000UL /**< Bit mask for LETIMER_CNTPRESC */ -#define _LETIMER_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DEFAULT (_LETIMER_CTRL_CNTPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV1 (_LETIMER_CTRL_CNTPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV2 (_LETIMER_CTRL_CNTPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV4 (_LETIMER_CTRL_CNTPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV8 (_LETIMER_CTRL_CNTPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV16 (_LETIMER_CTRL_CNTPRESC_DIV16 << 16) /**< Shifted mode DIV16 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV32 (_LETIMER_CTRL_CNTPRESC_DIV32 << 16) /**< Shifted mode DIV32 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV64 (_LETIMER_CTRL_CNTPRESC_DIV64 << 16) /**< Shifted mode DIV64 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV128 (_LETIMER_CTRL_CNTPRESC_DIV128 << 16) /**< Shifted mode DIV128 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV256 (_LETIMER_CTRL_CNTPRESC_DIV256 << 16) /**< Shifted mode DIV256 for LETIMER_CTRL */ +#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ +#define _LETIMER_CTRL_MASK 0x000F13FFUL /**< Mask for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ +#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ +#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ +#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DISABLE (_LETIMER_CTRL_BUFTOP_DISABLE << 8) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_ENABLE (_LETIMER_CTRL_BUFTOP_ENABLE << 8) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN (0x1UL << 9) /**< Compare Value 0 Is Top Value */ +#define _LETIMER_CTRL_CNTTOPEN_SHIFT 9 /**< Shift value for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_MASK 0x200UL /**< Bit mask for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DEFAULT (_LETIMER_CTRL_CNTTOPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DISABLE (_LETIMER_CTRL_CNTTOPEN_DISABLE << 9) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_ENABLE (_LETIMER_CTRL_CNTTOPEN_ENABLE << 9) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ +#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DISABLE (_LETIMER_CTRL_DEBUGRUN_DISABLE << 12) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_ENABLE (_LETIMER_CTRL_DEBUGRUN_ENABLE << 12) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_SHIFT 16 /**< Shift value for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_MASK 0xF0000UL /**< Bit mask for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DEFAULT (_LETIMER_CTRL_CNTPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV1 (_LETIMER_CTRL_CNTPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV2 (_LETIMER_CTRL_CNTPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV4 (_LETIMER_CTRL_CNTPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV8 (_LETIMER_CTRL_CNTPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV16 (_LETIMER_CTRL_CNTPRESC_DIV16 << 16) /**< Shifted mode DIV16 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV32 (_LETIMER_CTRL_CNTPRESC_DIV32 << 16) /**< Shifted mode DIV32 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV64 (_LETIMER_CTRL_CNTPRESC_DIV64 << 16) /**< Shifted mode DIV64 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV128 (_LETIMER_CTRL_CNTPRESC_DIV128 << 16) /**< Shifted mode DIV128 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV256 (_LETIMER_CTRL_CNTPRESC_DIV256 << 16) /**< Shifted mode DIV256 for LETIMER_CTRL */ /* Bit fields for LETIMER CMD */ -#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ -#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ -#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ -#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ -#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ -#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ -#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ -#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ -#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ -#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ -#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ -#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ -#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ -#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ -#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ -#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ -#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ -#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ +#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ +#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ +#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ +#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ +#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ +#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ +#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ +#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ /* Bit fields for LETIMER STATUS */ -#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ -#define _LETIMER_STATUS_MASK 0x00000003UL /**< Mask for LETIMER_STATUS */ -#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ -#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ -#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ -#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ -#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ -#define LETIMER_STATUS_LETIMERLOCKSTATUS (0x1UL << 1) /**< LETIMER Lock Status */ -#define _LETIMER_STATUS_LETIMERLOCKSTATUS_SHIFT 1 /**< Shift value for LETIMER_LETIMERLOCKSTATUS */ -#define _LETIMER_STATUS_LETIMERLOCKSTATUS_MASK 0x2UL /**< Bit mask for LETIMER_LETIMERLOCKSTATUS */ -#define _LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ -#define _LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LETIMER_STATUS */ -#define _LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for LETIMER_STATUS */ -#define LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT (_LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_STATUS */ -#define LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for LETIMER_STATUS */ -#define LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for LETIMER_STATUS */ +#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ +#define _LETIMER_STATUS_MASK 0x00000003UL /**< Mask for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ +#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS (0x1UL << 1) /**< LETIMER Lock Status */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_SHIFT 1 /**< Shift value for LETIMER_LETIMERLOCKSTATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_MASK 0x2UL /**< Bit mask for LETIMER_LETIMERLOCKSTATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LETIMER_STATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT (_LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for LETIMER_STATUS */ /* Bit fields for LETIMER CNT */ -#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ -#define _LETIMER_CNT_MASK 0x00FFFFFFUL /**< Mask for LETIMER_CNT */ -#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ -#define _LETIMER_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_CNT */ -#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ -#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ +#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ +#define _LETIMER_CNT_MASK 0x00FFFFFFUL /**< Mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ +#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ /* Bit fields for LETIMER COMP0 */ -#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ -#define _LETIMER_COMP0_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP0 */ -#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ -#define _LETIMER_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP0 */ -#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ -#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ +#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ +#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ /* Bit fields for LETIMER COMP1 */ -#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ -#define _LETIMER_COMP1_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP1 */ -#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ -#define _LETIMER_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP1 */ -#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ -#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ +#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ +#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ /* Bit fields for LETIMER TOP */ -#define _LETIMER_TOP_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOP */ -#define _LETIMER_TOP_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOP */ -#define _LETIMER_TOP_TOP_SHIFT 0 /**< Shift value for LETIMER_TOP */ -#define _LETIMER_TOP_TOP_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOP */ -#define _LETIMER_TOP_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOP */ -#define LETIMER_TOP_TOP_DEFAULT (_LETIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOP */ +#define _LETIMER_TOP_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOP */ +#define _LETIMER_TOP_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_SHIFT 0 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOP */ +#define LETIMER_TOP_TOP_DEFAULT (_LETIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOP */ /* Bit fields for LETIMER TOPBUFF */ -#define _LETIMER_TOPBUFF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOPBUFF */ -#define _LETIMER_TOPBUFF_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOPBUFF */ -#define _LETIMER_TOPBUFF_TOPBUFF_SHIFT 0 /**< Shift value for LETIMER_TOPBUFF */ -#define _LETIMER_TOPBUFF_TOPBUFF_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOPBUFF */ -#define _LETIMER_TOPBUFF_TOPBUFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOPBUFF */ -#define LETIMER_TOPBUFF_TOPBUFF_DEFAULT (_LETIMER_TOPBUFF_TOPBUFF_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_SHIFT 0 /**< Shift value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOPBUFF */ +#define LETIMER_TOPBUFF_TOPBUFF_DEFAULT (_LETIMER_TOPBUFF_TOPBUFF_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOPBUFF */ /* Bit fields for LETIMER REP0 */ -#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ -#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ -#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ -#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ -#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ -#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ +#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ +#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ +#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ /* Bit fields for LETIMER REP1 */ -#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ -#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ -#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ -#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ -#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ -#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ +#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ +#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ +#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ /* Bit fields for LETIMER IF */ -#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ -#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ -#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ -#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ -#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ -#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ -#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ -#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ -#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ -#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ -#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ -#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ -#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ -#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ -#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ -#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ -#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ -#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ +#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ +#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ +#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ +#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ +#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ /* Bit fields for LETIMER IEN */ -#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ -#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ -#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Enable */ -#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ -#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ -#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Enable */ -#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ -#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ -#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_UF (0x1UL << 2) /**< Underflow Interrupt Enable */ -#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ -#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ -#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Enable */ -#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ -#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ -#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Enable */ -#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ -#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ -#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ +#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ +#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Enable */ +#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Enable */ +#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF (0x1UL << 2) /**< Underflow Interrupt Enable */ +#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Enable */ +#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Enable */ +#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ /* Bit fields for LETIMER LOCK */ -#define _LETIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for LETIMER_LOCK */ -#define _LETIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for LETIMER_LOCK */ -#define _LETIMER_LOCK_LETIMERLOCKKEY_SHIFT 0 /**< Shift value for LETIMER_LETIMERLOCKKEY */ -#define _LETIMER_LOCK_LETIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for LETIMER_LETIMERLOCKKEY */ -#define _LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_LOCK */ -#define _LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK 0x0000CCFCUL /**< Mode UNLOCK for LETIMER_LOCK */ -#define LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT (_LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_LOCK */ -#define LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK (_LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LETIMER_LOCK */ +#define _LETIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for LETIMER_LOCK */ +#define _LETIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for LETIMER_LOCK */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_SHIFT 0 /**< Shift value for LETIMER_LETIMERLOCKKEY */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for LETIMER_LETIMERLOCKKEY */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_LOCK */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK 0x0000CCFCUL /**< Mode UNLOCK for LETIMER_LOCK */ +#define LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT (_LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_LOCK */ +#define LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK (_LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LETIMER_LOCK */ /* Bit fields for LETIMER SYNCBUSY */ -#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ -#define _LETIMER_SYNCBUSY_MASK 0x000003FDUL /**< Mask for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CNT (0x1UL << 0) /**< Sync busy for CNT */ -#define _LETIMER_SYNCBUSY_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ -#define _LETIMER_SYNCBUSY_CNT_MASK 0x1UL /**< Bit mask for LETIMER_CNT */ -#define _LETIMER_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CNT_DEFAULT (_LETIMER_SYNCBUSY_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_TOP (0x1UL << 2) /**< Sync busy for TOP */ -#define _LETIMER_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for LETIMER_TOP */ -#define _LETIMER_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for LETIMER_TOP */ -#define _LETIMER_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_TOP_DEFAULT (_LETIMER_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP0 (0x1UL << 3) /**< Sync busy for REP0 */ -#define _LETIMER_SYNCBUSY_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ -#define _LETIMER_SYNCBUSY_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ -#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP1 (0x1UL << 4) /**< Sync busy for REP1 */ -#define _LETIMER_SYNCBUSY_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ -#define _LETIMER_SYNCBUSY_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ -#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_START (0x1UL << 5) /**< Sync busy for START */ -#define _LETIMER_SYNCBUSY_START_SHIFT 5 /**< Shift value for LETIMER_START */ -#define _LETIMER_SYNCBUSY_START_MASK 0x20UL /**< Bit mask for LETIMER_START */ -#define _LETIMER_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_START_DEFAULT (_LETIMER_SYNCBUSY_START_DEFAULT << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_STOP (0x1UL << 6) /**< Sync busy for STOP */ -#define _LETIMER_SYNCBUSY_STOP_SHIFT 6 /**< Shift value for LETIMER_STOP */ -#define _LETIMER_SYNCBUSY_STOP_MASK 0x40UL /**< Bit mask for LETIMER_STOP */ -#define _LETIMER_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_STOP_DEFAULT (_LETIMER_SYNCBUSY_STOP_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CLEAR (0x1UL << 7) /**< Sync busy for CLEAR */ -#define _LETIMER_SYNCBUSY_CLEAR_SHIFT 7 /**< Shift value for LETIMER_CLEAR */ -#define _LETIMER_SYNCBUSY_CLEAR_MASK 0x80UL /**< Bit mask for LETIMER_CLEAR */ -#define _LETIMER_SYNCBUSY_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CLEAR_DEFAULT (_LETIMER_SYNCBUSY_CLEAR_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CTO0 (0x1UL << 8) /**< Sync busy for CTO0 */ -#define _LETIMER_SYNCBUSY_CTO0_SHIFT 8 /**< Shift value for LETIMER_CTO0 */ -#define _LETIMER_SYNCBUSY_CTO0_MASK 0x100UL /**< Bit mask for LETIMER_CTO0 */ -#define _LETIMER_SYNCBUSY_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CTO0_DEFAULT (_LETIMER_SYNCBUSY_CTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CTO1 (0x1UL << 9) /**< Sync busy for CTO1 */ -#define _LETIMER_SYNCBUSY_CTO1_SHIFT 9 /**< Shift value for LETIMER_CTO1 */ -#define _LETIMER_SYNCBUSY_CTO1_MASK 0x200UL /**< Bit mask for LETIMER_CTO1 */ -#define _LETIMER_SYNCBUSY_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CTO1_DEFAULT (_LETIMER_SYNCBUSY_CTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_MASK 0x000003FDUL /**< Mask for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT (0x1UL << 0) /**< Sync busy for CNT */ +#define _LETIMER_SYNCBUSY_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_MASK 0x1UL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT_DEFAULT (_LETIMER_SYNCBUSY_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP (0x1UL << 2) /**< Sync busy for TOP */ +#define _LETIMER_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP_DEFAULT (_LETIMER_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0 (0x1UL << 3) /**< Sync busy for REP0 */ +#define _LETIMER_SYNCBUSY_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1 (0x1UL << 4) /**< Sync busy for REP1 */ +#define _LETIMER_SYNCBUSY_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START (0x1UL << 5) /**< Sync busy for START */ +#define _LETIMER_SYNCBUSY_START_SHIFT 5 /**< Shift value for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_MASK 0x20UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START_DEFAULT (_LETIMER_SYNCBUSY_START_DEFAULT << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP (0x1UL << 6) /**< Sync busy for STOP */ +#define _LETIMER_SYNCBUSY_STOP_SHIFT 6 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_MASK 0x40UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP_DEFAULT (_LETIMER_SYNCBUSY_STOP_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR (0x1UL << 7) /**< Sync busy for CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_SHIFT 7 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_MASK 0x80UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR_DEFAULT (_LETIMER_SYNCBUSY_CLEAR_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0 (0x1UL << 8) /**< Sync busy for CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_SHIFT 8 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_MASK 0x100UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0_DEFAULT (_LETIMER_SYNCBUSY_CTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1 (0x1UL << 9) /**< Sync busy for CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_SHIFT 9 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_MASK 0x200UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1_DEFAULT (_LETIMER_SYNCBUSY_CTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ /* Bit fields for LETIMER PRSMODE */ -#define _LETIMER_PRSMODE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_MASK 0x0CCC0000UL /**< Mask for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_NONE (_LETIMER_PRSMODE_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_RISING (_LETIMER_PRSMODE_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_FALLING (_LETIMER_PRSMODE_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_BOTH (_LETIMER_PRSMODE_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_NONE (_LETIMER_PRSMODE_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_RISING (_LETIMER_PRSMODE_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_FALLING (_LETIMER_PRSMODE_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_BOTH (_LETIMER_PRSMODE_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT (_LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_NONE (_LETIMER_PRSMODE_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_RISING (_LETIMER_PRSMODE_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_FALLING (_LETIMER_PRSMODE_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_BOTH (_LETIMER_PRSMODE_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_MASK 0x0CCC0000UL /**< Mask for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_NONE (_LETIMER_PRSMODE_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_RISING (_LETIMER_PRSMODE_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_FALLING (_LETIMER_PRSMODE_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_BOTH (_LETIMER_PRSMODE_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_NONE (_LETIMER_PRSMODE_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_RISING (_LETIMER_PRSMODE_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_FALLING (_LETIMER_PRSMODE_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_BOTH (_LETIMER_PRSMODE_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT (_LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_NONE (_LETIMER_PRSMODE_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_RISING (_LETIMER_PRSMODE_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_FALLING (_LETIMER_PRSMODE_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_BOTH (_LETIMER_PRSMODE_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSMODE */ /** @} End of group EFR32SG28_LETIMER_BitFields */ /** @} End of group EFR32SG28_LETIMER */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lfrco.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lfrco.h index 5804ddf2b0..32dc2716c4 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lfrco.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_LFRCO_H #define EFR32SG28_LFRCO_H - #define LFRCO_HAS_SET_CLEAR /**************************************************************************//** @@ -43,47 +42,46 @@ *****************************************************************************/ /** LFRCO Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t CAL; /**< Calibration Register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - uint32_t RESERVED2[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t CAL_SET; /**< Calibration Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - uint32_t RESERVED5[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t CAL_CLR; /**< Calibration Register */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - uint32_t RESERVED8[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t CAL_TGL; /**< Calibration Register */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CAL; /**< Calibration Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CAL_SET; /**< Calibration Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED5[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CAL_CLR; /**< Calibration Register */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED8[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CAL_TGL; /**< Calibration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ } LFRCO_TypeDef; /** @} End of group EFR32SG28_LFRCO */ @@ -95,102 +93,102 @@ typedef struct *****************************************************************************/ /* Bit fields for LFRCO IPVERSION */ -#define _LFRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IPVERSION */ -#define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */ -#define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */ -#define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */ -#define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IPVERSION */ -#define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IPVERSION */ +#define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */ /* Bit fields for LFRCO STATUS */ -#define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */ -#define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */ -#define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ -#define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ -#define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ -#define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ -#define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */ -#define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */ -#define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ -#define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */ -#define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */ -#define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ -#define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */ -#define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */ -#define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */ -#define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */ +#define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */ +#define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */ /* Bit fields for LFRCO CAL */ -#define _LFRCO_CAL_RESETVALUE 0x000000A5UL /**< Default value for LFRCO_CAL */ -#define _LFRCO_CAL_MASK 0x000000FFUL /**< Mask for LFRCO_CAL */ -#define _LFRCO_CAL_FREQTRIM_SHIFT 0 /**< Shift value for LFRCO_FREQTRIM */ -#define _LFRCO_CAL_FREQTRIM_MASK 0xFFUL /**< Bit mask for LFRCO_FREQTRIM */ -#define _LFRCO_CAL_FREQTRIM_DEFAULT 0x000000A5UL /**< Mode DEFAULT for LFRCO_CAL */ -#define LFRCO_CAL_FREQTRIM_DEFAULT (_LFRCO_CAL_FREQTRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CAL */ +#define _LFRCO_CAL_RESETVALUE 0x000000A5UL /**< Default value for LFRCO_CAL */ +#define _LFRCO_CAL_MASK 0x000000FFUL /**< Mask for LFRCO_CAL */ +#define _LFRCO_CAL_FREQTRIM_SHIFT 0 /**< Shift value for LFRCO_FREQTRIM */ +#define _LFRCO_CAL_FREQTRIM_MASK 0xFFUL /**< Bit mask for LFRCO_FREQTRIM */ +#define _LFRCO_CAL_FREQTRIM_DEFAULT 0x000000A5UL /**< Mode DEFAULT for LFRCO_CAL */ +#define LFRCO_CAL_FREQTRIM_DEFAULT (_LFRCO_CAL_FREQTRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CAL */ /* Bit fields for LFRCO IF */ -#define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */ -#define _LFRCO_IF_MASK 0x00000007UL /**< Mask for LFRCO_IF */ -#define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ -#define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ -#define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ -#define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ -#define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ -#define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ -#define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ -#define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ -#define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ -#define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */ +#define _LFRCO_IF_MASK 0x00000007UL /**< Mask for LFRCO_IF */ +#define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ +#define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ +#define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */ /* Bit fields for LFRCO IEN */ -#define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */ -#define _LFRCO_IEN_MASK 0x00000007UL /**< Mask for LFRCO_IEN */ -#define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Interrupt Enable */ -#define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ -#define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ -#define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ -#define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ -#define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ -#define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ -#define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ -#define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ -#define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */ +#define _LFRCO_IEN_MASK 0x00000007UL /**< Mask for LFRCO_IEN */ +#define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Interrupt Enable */ +#define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ +#define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ +#define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */ /* Bit fields for LFRCO SYNCBUSY */ -#define _LFRCO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFRCO_SYNCBUSY */ -#define _LFRCO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFRCO_SYNCBUSY */ -#define LFRCO_SYNCBUSY_CAL (0x1UL << 0) /**< CAL Busy */ -#define _LFRCO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFRCO_CAL */ -#define _LFRCO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFRCO_CAL */ -#define _LFRCO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_SYNCBUSY */ -#define LFRCO_SYNCBUSY_CAL_DEFAULT (_LFRCO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_SYNCBUSY */ +#define _LFRCO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFRCO_SYNCBUSY */ +#define _LFRCO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFRCO_SYNCBUSY */ +#define LFRCO_SYNCBUSY_CAL (0x1UL << 0) /**< CAL Busy */ +#define _LFRCO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFRCO_CAL */ +#define _LFRCO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFRCO_CAL */ +#define _LFRCO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_SYNCBUSY */ +#define LFRCO_SYNCBUSY_CAL_DEFAULT (_LFRCO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_SYNCBUSY */ /* Bit fields for LFRCO LOCK */ -#define _LFRCO_LOCK_RESETVALUE 0x00002603UL /**< Default value for LFRCO_LOCK */ -#define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */ -#define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */ -#define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */ -#define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00002603UL /**< Mode DEFAULT for LFRCO_LOCK */ -#define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */ -#define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00002603UL /**< Mode UNLOCK for LFRCO_LOCK */ -#define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */ -#define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */ -#define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */ +#define _LFRCO_LOCK_RESETVALUE 0x00002603UL /**< Default value for LFRCO_LOCK */ +#define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00002603UL /**< Mode DEFAULT for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00002603UL /**< Mode UNLOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */ /** @} End of group EFR32SG28_LFRCO_BitFields */ /** @} End of group EFR32SG28_LFRCO */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lfxo.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lfxo.h index b99a39b13d..a8394270c8 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_lfxo.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_LFXO_H #define EFR32SG28_LFXO_H - #define LFXO_HAS_SET_CLEAR /**************************************************************************//** @@ -43,51 +42,50 @@ *****************************************************************************/ /** LFXO Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< LFXO IP version */ - __IOM uint32_t CTRL; /**< LFXO Control Register */ - __IOM uint32_t CFG; /**< LFXO Configuration Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< LFXO Status Register */ - __IOM uint32_t CAL; /**< LFXO Calibration Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY; /**< LFXO Sync Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< LFXO IP version */ - __IOM uint32_t CTRL_SET; /**< LFXO Control Register */ - __IOM uint32_t CFG_SET; /**< LFXO Configuration Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< LFXO Status Register */ - __IOM uint32_t CAL_SET; /**< LFXO Calibration Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_SET; /**< LFXO Sync Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - uint32_t RESERVED3[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< LFXO IP version */ - __IOM uint32_t CTRL_CLR; /**< LFXO Control Register */ - __IOM uint32_t CFG_CLR; /**< LFXO Configuration Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< LFXO Status Register */ - __IOM uint32_t CAL_CLR; /**< LFXO Calibration Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_CLR; /**< LFXO Sync Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - uint32_t RESERVED5[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< LFXO IP version */ - __IOM uint32_t CTRL_TGL; /**< LFXO Control Register */ - __IOM uint32_t CFG_TGL; /**< LFXO Configuration Register */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< LFXO Status Register */ - __IOM uint32_t CAL_TGL; /**< LFXO Calibration Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_TGL; /**< LFXO Sync Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< LFXO IP version */ + __IOM uint32_t CTRL; /**< LFXO Control Register */ + __IOM uint32_t CFG; /**< LFXO Configuration Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< LFXO Status Register */ + __IOM uint32_t CAL; /**< LFXO Calibration Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< LFXO IP version */ + __IOM uint32_t CTRL_SET; /**< LFXO Control Register */ + __IOM uint32_t CFG_SET; /**< LFXO Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< LFXO Status Register */ + __IOM uint32_t CAL_SET; /**< LFXO Calibration Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< LFXO IP version */ + __IOM uint32_t CTRL_CLR; /**< LFXO Control Register */ + __IOM uint32_t CFG_CLR; /**< LFXO Configuration Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< LFXO Status Register */ + __IOM uint32_t CAL_CLR; /**< LFXO Calibration Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< LFXO IP version */ + __IOM uint32_t CTRL_TGL; /**< LFXO Control Register */ + __IOM uint32_t CFG_TGL; /**< LFXO Configuration Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< LFXO Status Register */ + __IOM uint32_t CAL_TGL; /**< LFXO Calibration Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ } LFXO_TypeDef; /** @} End of group EFR32SG28_LFXO */ @@ -99,182 +97,182 @@ typedef struct *****************************************************************************/ /* Bit fields for LFXO IPVERSION */ -#define _LFXO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LFXO_IPVERSION */ -#define _LFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFXO_IPVERSION */ -#define _LFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFXO_IPVERSION */ -#define _LFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFXO_IPVERSION */ -#define _LFXO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_IPVERSION */ -#define LFXO_IPVERSION_IPVERSION_DEFAULT (_LFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_IPVERSION */ +#define LFXO_IPVERSION_IPVERSION_DEFAULT (_LFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IPVERSION */ /* Bit fields for LFXO CTRL */ -#define _LFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for LFXO_CTRL */ -#define _LFXO_CTRL_MASK 0x00000033UL /**< Mask for LFXO_CTRL */ -#define LFXO_CTRL_FORCEEN (0x1UL << 0) /**< LFXO Force Enable */ -#define _LFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFXO_FORCEEN */ -#define _LFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFXO_FORCEEN */ -#define _LFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FORCEEN_DEFAULT (_LFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< LFXO Disable On-demand requests */ -#define _LFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFXO_DISONDEMAND */ -#define _LFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFXO_DISONDEMAND */ -#define _LFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_DISONDEMAND_DEFAULT (_LFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FAILDETEN (0x1UL << 4) /**< LFXO Failure Detection Enable */ -#define _LFXO_CTRL_FAILDETEN_SHIFT 4 /**< Shift value for LFXO_FAILDETEN */ -#define _LFXO_CTRL_FAILDETEN_MASK 0x10UL /**< Bit mask for LFXO_FAILDETEN */ -#define _LFXO_CTRL_FAILDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FAILDETEN_DEFAULT (_LFXO_CTRL_FAILDETEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FAILDETEM4WUEN (0x1UL << 5) /**< LFXO Failure Detection EM4WU Enable */ -#define _LFXO_CTRL_FAILDETEM4WUEN_SHIFT 5 /**< Shift value for LFXO_FAILDETEM4WUEN */ -#define _LFXO_CTRL_FAILDETEM4WUEN_MASK 0x20UL /**< Bit mask for LFXO_FAILDETEM4WUEN */ -#define _LFXO_CTRL_FAILDETEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FAILDETEM4WUEN_DEFAULT (_LFXO_CTRL_FAILDETEM4WUEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define _LFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for LFXO_CTRL */ +#define _LFXO_CTRL_MASK 0x00000033UL /**< Mask for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN (0x1UL << 0) /**< LFXO Force Enable */ +#define _LFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN_DEFAULT (_LFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< LFXO Disable On-demand requests */ +#define _LFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND_DEFAULT (_LFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN (0x1UL << 4) /**< LFXO Failure Detection Enable */ +#define _LFXO_CTRL_FAILDETEN_SHIFT 4 /**< Shift value for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_MASK 0x10UL /**< Bit mask for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN_DEFAULT (_LFXO_CTRL_FAILDETEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN (0x1UL << 5) /**< LFXO Failure Detection EM4WU Enable */ +#define _LFXO_CTRL_FAILDETEM4WUEN_SHIFT 5 /**< Shift value for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_MASK 0x20UL /**< Bit mask for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN_DEFAULT (_LFXO_CTRL_FAILDETEM4WUEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LFXO_CTRL */ /* Bit fields for LFXO CFG */ -#define _LFXO_CFG_RESETVALUE 0x00000701UL /**< Default value for LFXO_CFG */ -#define _LFXO_CFG_MASK 0x00000733UL /**< Mask for LFXO_CFG */ -#define LFXO_CFG_AGC (0x1UL << 0) /**< LFXO AGC Enable */ -#define _LFXO_CFG_AGC_SHIFT 0 /**< Shift value for LFXO_AGC */ -#define _LFXO_CFG_AGC_MASK 0x1UL /**< Bit mask for LFXO_AGC */ -#define _LFXO_CFG_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_AGC_DEFAULT (_LFXO_CFG_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_HIGHAMPL (0x1UL << 1) /**< LFXO High Amplitude Enable */ -#define _LFXO_CFG_HIGHAMPL_SHIFT 1 /**< Shift value for LFXO_HIGHAMPL */ -#define _LFXO_CFG_HIGHAMPL_MASK 0x2UL /**< Bit mask for LFXO_HIGHAMPL */ -#define _LFXO_CFG_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_HIGHAMPL_DEFAULT (_LFXO_CFG_HIGHAMPL_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CFG */ -#define _LFXO_CFG_MODE_SHIFT 4 /**< Shift value for LFXO_MODE */ -#define _LFXO_CFG_MODE_MASK 0x30UL /**< Bit mask for LFXO_MODE */ -#define _LFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ -#define _LFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for LFXO_CFG */ -#define _LFXO_CFG_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for LFXO_CFG */ -#define _LFXO_CFG_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for LFXO_CFG */ -#define LFXO_CFG_MODE_DEFAULT (_LFXO_CFG_MODE_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_MODE_XTAL (_LFXO_CFG_MODE_XTAL << 4) /**< Shifted mode XTAL for LFXO_CFG */ -#define LFXO_CFG_MODE_BUFEXTCLK (_LFXO_CFG_MODE_BUFEXTCLK << 4) /**< Shifted mode BUFEXTCLK for LFXO_CFG */ -#define LFXO_CFG_MODE_DIGEXTCLK (_LFXO_CFG_MODE_DIGEXTCLK << 4) /**< Shifted mode DIGEXTCLK for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_SHIFT 8 /**< Shift value for LFXO_TIMEOUT */ -#define _LFXO_CFG_TIMEOUT_MASK 0x700UL /**< Bit mask for LFXO_TIMEOUT */ -#define _LFXO_CFG_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES2 0x00000000UL /**< Mode CYCLES2 for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES256 0x00000001UL /**< Mode CYCLES256 for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES1K 0x00000002UL /**< Mode CYCLES1K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES2K 0x00000003UL /**< Mode CYCLES2K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES4K 0x00000004UL /**< Mode CYCLES4K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES8K 0x00000005UL /**< Mode CYCLES8K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES16K 0x00000006UL /**< Mode CYCLES16K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES32K 0x00000007UL /**< Mode CYCLES32K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_DEFAULT (_LFXO_CFG_TIMEOUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES2 (_LFXO_CFG_TIMEOUT_CYCLES2 << 8) /**< Shifted mode CYCLES2 for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES256 (_LFXO_CFG_TIMEOUT_CYCLES256 << 8) /**< Shifted mode CYCLES256 for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES1K (_LFXO_CFG_TIMEOUT_CYCLES1K << 8) /**< Shifted mode CYCLES1K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES2K (_LFXO_CFG_TIMEOUT_CYCLES2K << 8) /**< Shifted mode CYCLES2K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES4K (_LFXO_CFG_TIMEOUT_CYCLES4K << 8) /**< Shifted mode CYCLES4K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES8K (_LFXO_CFG_TIMEOUT_CYCLES8K << 8) /**< Shifted mode CYCLES8K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES16K (_LFXO_CFG_TIMEOUT_CYCLES16K << 8) /**< Shifted mode CYCLES16K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES32K (_LFXO_CFG_TIMEOUT_CYCLES32K << 8) /**< Shifted mode CYCLES32K for LFXO_CFG */ +#define _LFXO_CFG_RESETVALUE 0x00000701UL /**< Default value for LFXO_CFG */ +#define _LFXO_CFG_MASK 0x00000733UL /**< Mask for LFXO_CFG */ +#define LFXO_CFG_AGC (0x1UL << 0) /**< LFXO AGC Enable */ +#define _LFXO_CFG_AGC_SHIFT 0 /**< Shift value for LFXO_AGC */ +#define _LFXO_CFG_AGC_MASK 0x1UL /**< Bit mask for LFXO_AGC */ +#define _LFXO_CFG_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_AGC_DEFAULT (_LFXO_CFG_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL (0x1UL << 1) /**< LFXO High Amplitude Enable */ +#define _LFXO_CFG_HIGHAMPL_SHIFT 1 /**< Shift value for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_MASK 0x2UL /**< Bit mask for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL_DEFAULT (_LFXO_CFG_HIGHAMPL_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_SHIFT 4 /**< Shift value for LFXO_MODE */ +#define _LFXO_CFG_MODE_MASK 0x30UL /**< Bit mask for LFXO_MODE */ +#define _LFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for LFXO_CFG */ +#define _LFXO_CFG_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DEFAULT (_LFXO_CFG_MODE_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_MODE_XTAL (_LFXO_CFG_MODE_XTAL << 4) /**< Shifted mode XTAL for LFXO_CFG */ +#define LFXO_CFG_MODE_BUFEXTCLK (_LFXO_CFG_MODE_BUFEXTCLK << 4) /**< Shifted mode BUFEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DIGEXTCLK (_LFXO_CFG_MODE_DIGEXTCLK << 4) /**< Shifted mode DIGEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_SHIFT 8 /**< Shift value for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_MASK 0x700UL /**< Bit mask for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2 0x00000000UL /**< Mode CYCLES2 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES256 0x00000001UL /**< Mode CYCLES256 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES1K 0x00000002UL /**< Mode CYCLES1K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2K 0x00000003UL /**< Mode CYCLES2K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES4K 0x00000004UL /**< Mode CYCLES4K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES8K 0x00000005UL /**< Mode CYCLES8K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES16K 0x00000006UL /**< Mode CYCLES16K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES32K 0x00000007UL /**< Mode CYCLES32K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_DEFAULT (_LFXO_CFG_TIMEOUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2 (_LFXO_CFG_TIMEOUT_CYCLES2 << 8) /**< Shifted mode CYCLES2 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES256 (_LFXO_CFG_TIMEOUT_CYCLES256 << 8) /**< Shifted mode CYCLES256 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES1K (_LFXO_CFG_TIMEOUT_CYCLES1K << 8) /**< Shifted mode CYCLES1K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2K (_LFXO_CFG_TIMEOUT_CYCLES2K << 8) /**< Shifted mode CYCLES2K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES4K (_LFXO_CFG_TIMEOUT_CYCLES4K << 8) /**< Shifted mode CYCLES4K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES8K (_LFXO_CFG_TIMEOUT_CYCLES8K << 8) /**< Shifted mode CYCLES8K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES16K (_LFXO_CFG_TIMEOUT_CYCLES16K << 8) /**< Shifted mode CYCLES16K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES32K (_LFXO_CFG_TIMEOUT_CYCLES32K << 8) /**< Shifted mode CYCLES32K for LFXO_CFG */ /* Bit fields for LFXO STATUS */ -#define _LFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFXO_STATUS */ -#define _LFXO_STATUS_MASK 0x80010001UL /**< Mask for LFXO_STATUS */ -#define LFXO_STATUS_RDY (0x1UL << 0) /**< LFXO Ready Status */ -#define _LFXO_STATUS_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ -#define _LFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ -#define _LFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_RDY_DEFAULT (_LFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_ENS (0x1UL << 16) /**< LFXO Enable Status */ -#define _LFXO_STATUS_ENS_SHIFT 16 /**< Shift value for LFXO_ENS */ -#define _LFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFXO_ENS */ -#define _LFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_ENS_DEFAULT (_LFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_LOCK (0x1UL << 31) /**< LFXO Locked Status */ -#define _LFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFXO_LOCK */ -#define _LFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFXO_LOCK */ -#define _LFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ -#define _LFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFXO_STATUS */ -#define _LFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFXO_STATUS */ -#define LFXO_STATUS_LOCK_DEFAULT (_LFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_LOCK_UNLOCKED (_LFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFXO_STATUS */ -#define LFXO_STATUS_LOCK_LOCKED (_LFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFXO_STATUS */ +#define _LFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFXO_STATUS */ +#define _LFXO_STATUS_MASK 0x80010001UL /**< Mask for LFXO_STATUS */ +#define LFXO_STATUS_RDY (0x1UL << 0) /**< LFXO Ready Status */ +#define _LFXO_STATUS_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_RDY_DEFAULT (_LFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS (0x1UL << 16) /**< LFXO Enable Status */ +#define _LFXO_STATUS_ENS_SHIFT 16 /**< Shift value for LFXO_ENS */ +#define _LFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFXO_ENS */ +#define _LFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS_DEFAULT (_LFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK (0x1UL << 31) /**< LFXO Locked Status */ +#define _LFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_DEFAULT (_LFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_UNLOCKED (_LFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_LOCKED (_LFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFXO_STATUS */ /* Bit fields for LFXO CAL */ -#define _LFXO_CAL_RESETVALUE 0x00000100UL /**< Default value for LFXO_CAL */ -#define _LFXO_CAL_MASK 0x0000037FUL /**< Mask for LFXO_CAL */ -#define _LFXO_CAL_CAPTUNE_SHIFT 0 /**< Shift value for LFXO_CAPTUNE */ -#define _LFXO_CAL_CAPTUNE_MASK 0x7FUL /**< Bit mask for LFXO_CAPTUNE */ -#define _LFXO_CAL_CAPTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CAL */ -#define LFXO_CAL_CAPTUNE_DEFAULT (_LFXO_CAL_CAPTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CAL */ -#define _LFXO_CAL_GAIN_SHIFT 8 /**< Shift value for LFXO_GAIN */ -#define _LFXO_CAL_GAIN_MASK 0x300UL /**< Bit mask for LFXO_GAIN */ -#define _LFXO_CAL_GAIN_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CAL */ -#define LFXO_CAL_GAIN_DEFAULT (_LFXO_CAL_GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CAL */ +#define _LFXO_CAL_RESETVALUE 0x00000100UL /**< Default value for LFXO_CAL */ +#define _LFXO_CAL_MASK 0x0000037FUL /**< Mask for LFXO_CAL */ +#define _LFXO_CAL_CAPTUNE_SHIFT 0 /**< Shift value for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_MASK 0x7FUL /**< Bit mask for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_CAPTUNE_DEFAULT (_LFXO_CAL_CAPTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CAL */ +#define _LFXO_CAL_GAIN_SHIFT 8 /**< Shift value for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_MASK 0x300UL /**< Bit mask for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_GAIN_DEFAULT (_LFXO_CAL_GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CAL */ /* Bit fields for LFXO IF */ -#define _LFXO_IF_RESETVALUE 0x00000000UL /**< Default value for LFXO_IF */ -#define _LFXO_IF_MASK 0x0000000FUL /**< Mask for LFXO_IF */ -#define LFXO_IF_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Flag */ -#define _LFXO_IF_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ -#define _LFXO_IF_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ -#define _LFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ -#define LFXO_IF_RDY_DEFAULT (_LFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IF */ -#define LFXO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ -#define _LFXO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ -#define _LFXO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ -#define _LFXO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ -#define LFXO_IF_POSEDGE_DEFAULT (_LFXO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IF */ -#define LFXO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ -#define _LFXO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ -#define _LFXO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ -#define _LFXO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ -#define LFXO_IF_NEGEDGE_DEFAULT (_LFXO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IF */ -#define LFXO_IF_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Flag */ -#define _LFXO_IF_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ -#define _LFXO_IF_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ -#define _LFXO_IF_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ -#define LFXO_IF_FAIL_DEFAULT (_LFXO_IF_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IF */ +#define _LFXO_IF_RESETVALUE 0x00000000UL /**< Default value for LFXO_IF */ +#define _LFXO_IF_MASK 0x0000000FUL /**< Mask for LFXO_IF */ +#define LFXO_IF_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Flag */ +#define _LFXO_IF_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IF_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_RDY_DEFAULT (_LFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ +#define _LFXO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE_DEFAULT (_LFXO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ +#define _LFXO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE_DEFAULT (_LFXO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Flag */ +#define _LFXO_IF_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IF_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IF_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL_DEFAULT (_LFXO_IF_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IF */ /* Bit fields for LFXO IEN */ -#define _LFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFXO_IEN */ -#define _LFXO_IEN_MASK 0x0000000FUL /**< Mask for LFXO_IEN */ -#define LFXO_IEN_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Enable */ -#define _LFXO_IEN_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ -#define _LFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ -#define _LFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_RDY_DEFAULT (_LFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ -#define _LFXO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ -#define _LFXO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ -#define _LFXO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_POSEDGE_DEFAULT (_LFXO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ -#define _LFXO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ -#define _LFXO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ -#define _LFXO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_NEGEDGE_DEFAULT (_LFXO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Enable */ -#define _LFXO_IEN_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ -#define _LFXO_IEN_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ -#define _LFXO_IEN_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_FAIL_DEFAULT (_LFXO_IEN_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define _LFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFXO_IEN */ +#define _LFXO_IEN_MASK 0x0000000FUL /**< Mask for LFXO_IEN */ +#define LFXO_IEN_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Enable */ +#define _LFXO_IEN_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_RDY_DEFAULT (_LFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ +#define _LFXO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE_DEFAULT (_LFXO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ +#define _LFXO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE_DEFAULT (_LFXO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Enable */ +#define _LFXO_IEN_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL_DEFAULT (_LFXO_IEN_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IEN */ /* Bit fields for LFXO SYNCBUSY */ -#define _LFXO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFXO_SYNCBUSY */ -#define _LFXO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFXO_SYNCBUSY */ -#define LFXO_SYNCBUSY_CAL (0x1UL << 0) /**< LFXO Synchronization status */ -#define _LFXO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFXO_CAL */ -#define _LFXO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFXO_CAL */ -#define _LFXO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_SYNCBUSY */ -#define LFXO_SYNCBUSY_CAL_DEFAULT (_LFXO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_SYNCBUSY */ +#define _LFXO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFXO_SYNCBUSY */ +#define _LFXO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL (0x1UL << 0) /**< LFXO Synchronization status */ +#define _LFXO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL_DEFAULT (_LFXO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_SYNCBUSY */ /* Bit fields for LFXO LOCK */ -#define _LFXO_LOCK_RESETVALUE 0x00001A20UL /**< Default value for LFXO_LOCK */ -#define _LFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFXO_LOCK */ -#define _LFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFXO_LOCKKEY */ -#define _LFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFXO_LOCKKEY */ -#define _LFXO_LOCK_LOCKKEY_DEFAULT 0x00001A20UL /**< Mode DEFAULT for LFXO_LOCK */ -#define _LFXO_LOCK_LOCKKEY_UNLOCK 0x00001A20UL /**< Mode UNLOCK for LFXO_LOCK */ -#define LFXO_LOCK_LOCKKEY_DEFAULT (_LFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_LOCK */ -#define LFXO_LOCK_LOCKKEY_UNLOCK (_LFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFXO_LOCK */ +#define _LFXO_LOCK_RESETVALUE 0x00001A20UL /**< Default value for LFXO_LOCK */ +#define _LFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_DEFAULT 0x00001A20UL /**< Mode DEFAULT for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_UNLOCK 0x00001A20UL /**< Mode UNLOCK for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_DEFAULT (_LFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_UNLOCK (_LFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFXO_LOCK */ /** @} End of group EFR32SG28_LFXO_BitFields */ /** @} End of group EFR32SG28_LFXO */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_mailbox.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_mailbox.h index ca3e7b9ccb..d9aac38741 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_mailbox.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_MAILBOX_H #define EFR32SG28_MAILBOX_H - #define MAILBOX_HAS_SET_CLEAR /**************************************************************************//** @@ -43,34 +42,31 @@ *****************************************************************************/ /** MAILBOX MSGPTRS Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t MSGPTR; /**< Message Pointer */ +typedef struct { + __IOM uint32_t MSGPTR; /**< Message Pointer */ } MAILBOX_MSGPTRS_TypeDef; - /** MAILBOX Register Declaration. */ -typedef struct -{ - MAILBOX_MSGPTRS_TypeDef MSGPTRS[4U]; /**< Message Pointers */ - uint32_t RESERVED0[12U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag register */ - __IOM uint32_t IEN; /**< Interrupt Enable register */ - uint32_t RESERVED1[1006U]; /**< Reserved for future use */ - MAILBOX_MSGPTRS_TypeDef MSGPTRS_SET[4U]; /**< Message Pointers */ - uint32_t RESERVED2[12U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable register */ - uint32_t RESERVED3[1006U]; /**< Reserved for future use */ - MAILBOX_MSGPTRS_TypeDef MSGPTRS_CLR[4U]; /**< Message Pointers */ - uint32_t RESERVED4[12U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable register */ - uint32_t RESERVED5[1006U]; /**< Reserved for future use */ - MAILBOX_MSGPTRS_TypeDef MSGPTRS_TGL[4U]; /**< Message Pointers */ - uint32_t RESERVED6[12U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable register */ +typedef struct { + MAILBOX_MSGPTRS_TypeDef MSGPTRS[4U]; /**< Message Pointers */ + uint32_t RESERVED0[12U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag register */ + __IOM uint32_t IEN; /**< Interrupt Enable register */ + uint32_t RESERVED1[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_SET[4U]; /**< Message Pointers */ + uint32_t RESERVED2[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable register */ + uint32_t RESERVED3[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_CLR[4U]; /**< Message Pointers */ + uint32_t RESERVED4[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable register */ + uint32_t RESERVED5[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_TGL[4U]; /**< Message Pointers */ + uint32_t RESERVED6[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable register */ } MAILBOX_TypeDef; /** @} End of group EFR32SG28_MAILBOX */ @@ -82,60 +78,60 @@ typedef struct *****************************************************************************/ /* Bit fields for MAILBOX MSGPTR */ -#define _MAILBOX_MSGPTR_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_MSGPTR */ -#define _MAILBOX_MSGPTR_MASK 0xFFFFFFFFUL /**< Mask for MAILBOX_MSGPTR */ -#define _MAILBOX_MSGPTR_PTR_SHIFT 0 /**< Shift value for MAILBOX_PTR */ -#define _MAILBOX_MSGPTR_PTR_MASK 0xFFFFFFFFUL /**< Bit mask for MAILBOX_PTR */ -#define _MAILBOX_MSGPTR_PTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_MSGPTR */ -#define MAILBOX_MSGPTR_PTR_DEFAULT (_MAILBOX_MSGPTR_PTR_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_MSGPTR */ +#define _MAILBOX_MSGPTR_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_MSGPTR */ +#define _MAILBOX_MSGPTR_MASK 0xFFFFFFFFUL /**< Mask for MAILBOX_MSGPTR */ +#define _MAILBOX_MSGPTR_PTR_SHIFT 0 /**< Shift value for MAILBOX_PTR */ +#define _MAILBOX_MSGPTR_PTR_MASK 0xFFFFFFFFUL /**< Bit mask for MAILBOX_PTR */ +#define _MAILBOX_MSGPTR_PTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_MSGPTR */ +#define MAILBOX_MSGPTR_PTR_DEFAULT (_MAILBOX_MSGPTR_PTR_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_MSGPTR */ /* Bit fields for MAILBOX IF */ -#define _MAILBOX_IF_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IF */ -#define _MAILBOX_IF_MASK 0x0000000FUL /**< Mask for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF0 (0x1UL << 0) /**< Mailbox Interupt Flag */ -#define _MAILBOX_IF_MBOXIF0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIF0 */ -#define _MAILBOX_IF_MBOXIF0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIF0 */ -#define _MAILBOX_IF_MBOXIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF0_DEFAULT (_MAILBOX_IF_MBOXIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF1 (0x1UL << 1) /**< Mailbox Interupt Flag */ -#define _MAILBOX_IF_MBOXIF1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIF1 */ -#define _MAILBOX_IF_MBOXIF1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIF1 */ -#define _MAILBOX_IF_MBOXIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF1_DEFAULT (_MAILBOX_IF_MBOXIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF2 (0x1UL << 2) /**< Mailbox Interupt Flag */ -#define _MAILBOX_IF_MBOXIF2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIF2 */ -#define _MAILBOX_IF_MBOXIF2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIF2 */ -#define _MAILBOX_IF_MBOXIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF2_DEFAULT (_MAILBOX_IF_MBOXIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF3 (0x1UL << 3) /**< Mailbox Interupt Flag */ -#define _MAILBOX_IF_MBOXIF3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIF3 */ -#define _MAILBOX_IF_MBOXIF3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIF3 */ -#define _MAILBOX_IF_MBOXIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF3_DEFAULT (_MAILBOX_IF_MBOXIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define _MAILBOX_IF_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IF */ +#define _MAILBOX_IF_MASK 0x0000000FUL /**< Mask for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF0 (0x1UL << 0) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIF0 */ +#define _MAILBOX_IF_MBOXIF0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIF0 */ +#define _MAILBOX_IF_MBOXIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF0_DEFAULT (_MAILBOX_IF_MBOXIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF1 (0x1UL << 1) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIF1 */ +#define _MAILBOX_IF_MBOXIF1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIF1 */ +#define _MAILBOX_IF_MBOXIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF1_DEFAULT (_MAILBOX_IF_MBOXIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF2 (0x1UL << 2) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIF2 */ +#define _MAILBOX_IF_MBOXIF2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIF2 */ +#define _MAILBOX_IF_MBOXIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF2_DEFAULT (_MAILBOX_IF_MBOXIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF3 (0x1UL << 3) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIF3 */ +#define _MAILBOX_IF_MBOXIF3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIF3 */ +#define _MAILBOX_IF_MBOXIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF3_DEFAULT (_MAILBOX_IF_MBOXIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IF */ /* Bit fields for MAILBOX IEN */ -#define _MAILBOX_IEN_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IEN */ -#define _MAILBOX_IEN_MASK 0x0000000FUL /**< Mask for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN0 (0x1UL << 0) /**< Mailbox Interrupt Enable */ -#define _MAILBOX_IEN_MBOXIEN0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIEN0 */ -#define _MAILBOX_IEN_MBOXIEN0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIEN0 */ -#define _MAILBOX_IEN_MBOXIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN0_DEFAULT (_MAILBOX_IEN_MBOXIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN1 (0x1UL << 1) /**< Mailbox Interrupt Enable */ -#define _MAILBOX_IEN_MBOXIEN1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIEN1 */ -#define _MAILBOX_IEN_MBOXIEN1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIEN1 */ -#define _MAILBOX_IEN_MBOXIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN1_DEFAULT (_MAILBOX_IEN_MBOXIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN2 (0x1UL << 2) /**< Mailbox Interrupt Enable */ -#define _MAILBOX_IEN_MBOXIEN2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIEN2 */ -#define _MAILBOX_IEN_MBOXIEN2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIEN2 */ -#define _MAILBOX_IEN_MBOXIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN2_DEFAULT (_MAILBOX_IEN_MBOXIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN3 (0x1UL << 3) /**< Mailbox Interrupt Enable */ -#define _MAILBOX_IEN_MBOXIEN3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIEN3 */ -#define _MAILBOX_IEN_MBOXIEN3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIEN3 */ -#define _MAILBOX_IEN_MBOXIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN3_DEFAULT (_MAILBOX_IEN_MBOXIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define _MAILBOX_IEN_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IEN */ +#define _MAILBOX_IEN_MASK 0x0000000FUL /**< Mask for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN0 (0x1UL << 0) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIEN0 */ +#define _MAILBOX_IEN_MBOXIEN0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIEN0 */ +#define _MAILBOX_IEN_MBOXIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN0_DEFAULT (_MAILBOX_IEN_MBOXIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN1 (0x1UL << 1) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIEN1 */ +#define _MAILBOX_IEN_MBOXIEN1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIEN1 */ +#define _MAILBOX_IEN_MBOXIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN1_DEFAULT (_MAILBOX_IEN_MBOXIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN2 (0x1UL << 2) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIEN2 */ +#define _MAILBOX_IEN_MBOXIEN2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIEN2 */ +#define _MAILBOX_IEN_MBOXIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN2_DEFAULT (_MAILBOX_IEN_MBOXIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN3 (0x1UL << 3) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIEN3 */ +#define _MAILBOX_IEN_MBOXIEN3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIEN3 */ +#define _MAILBOX_IEN_MBOXIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN3_DEFAULT (_MAILBOX_IEN_MBOXIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IEN */ /** @} End of group EFR32SG28_MAILBOX_BitFields */ /** @} End of group EFR32SG28_MAILBOX */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_mpahbram.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_mpahbram.h index 8d16ef0343..5f20f001b9 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_msc.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_msc.h index 160622a998..25ab620453 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_msc.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_msc.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_MSC_H #define EFR32SG28_MSC_H - #define MSC_HAS_SET_CLEAR /**************************************************************************//** @@ -43,131 +42,130 @@ *****************************************************************************/ /** MSC Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t READCTRL; /**< Read Control Register */ - __IOM uint32_t RDATACTRL; /**< Read Data Control Register */ - __IOM uint32_t WRITECTRL; /**< Write Control Register */ - __IOM uint32_t WRITECMD; /**< Write Command Register */ - __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ - __IOM uint32_t WDATA; /**< Write Data Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - __IM uint32_t USERDATASIZE; /**< User Data Region Size Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - __IOM uint32_t MISCLOCKWORD; /**< Mass erase and User data page lock word */ - uint32_t RESERVED1[3U]; /**< Reserved for future use */ - __IOM uint32_t PWRCTRL; /**< Power control register */ - uint32_t RESERVED2[51U]; /**< Reserved for future use */ - __IOM uint32_t PAGELOCK0; /**< Main space page 0-31 lock word */ - __IOM uint32_t PAGELOCK1; /**< Main space page 32-63 lock word */ - __IOM uint32_t PAGELOCK2; /**< Main space page 64-95 lock word */ - __IOM uint32_t PAGELOCK3; /**< Main space page 96-127 lock word */ - uint32_t RESERVED3[4U]; /**< Reserved for future use */ - uint32_t RESERVED4[4U]; /**< Reserved for future use */ - uint32_t RESERVED5[4U]; /**< Reserved for future use */ - uint32_t RESERVED6[4U]; /**< Reserved for future use */ - uint32_t RESERVED7[12U]; /**< Reserved for future use */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - uint32_t RESERVED9[8U]; /**< Reserved for future use */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - uint32_t RESERVED11[910U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t READCTRL_SET; /**< Read Control Register */ - __IOM uint32_t RDATACTRL_SET; /**< Read Data Control Register */ - __IOM uint32_t WRITECTRL_SET; /**< Write Control Register */ - __IOM uint32_t WRITECMD_SET; /**< Write Command Register */ - __IOM uint32_t ADDRB_SET; /**< Page Erase/Write Address Buffer */ - __IOM uint32_t WDATA_SET; /**< Write Data Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED12[3U]; /**< Reserved for future use */ - __IM uint32_t USERDATASIZE_SET; /**< User Data Region Size Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - __IOM uint32_t MISCLOCKWORD_SET; /**< Mass erase and User data page lock word */ - uint32_t RESERVED13[3U]; /**< Reserved for future use */ - __IOM uint32_t PWRCTRL_SET; /**< Power control register */ - uint32_t RESERVED14[51U]; /**< Reserved for future use */ - __IOM uint32_t PAGELOCK0_SET; /**< Main space page 0-31 lock word */ - __IOM uint32_t PAGELOCK1_SET; /**< Main space page 32-63 lock word */ - __IOM uint32_t PAGELOCK2_SET; /**< Main space page 64-95 lock word */ - __IOM uint32_t PAGELOCK3_SET; /**< Main space page 96-127 lock word */ - uint32_t RESERVED15[4U]; /**< Reserved for future use */ - uint32_t RESERVED16[4U]; /**< Reserved for future use */ - uint32_t RESERVED17[4U]; /**< Reserved for future use */ - uint32_t RESERVED18[4U]; /**< Reserved for future use */ - uint32_t RESERVED19[12U]; /**< Reserved for future use */ - uint32_t RESERVED20[1U]; /**< Reserved for future use */ - uint32_t RESERVED21[8U]; /**< Reserved for future use */ - uint32_t RESERVED22[1U]; /**< Reserved for future use */ - uint32_t RESERVED23[910U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t READCTRL_CLR; /**< Read Control Register */ - __IOM uint32_t RDATACTRL_CLR; /**< Read Data Control Register */ - __IOM uint32_t WRITECTRL_CLR; /**< Write Control Register */ - __IOM uint32_t WRITECMD_CLR; /**< Write Command Register */ - __IOM uint32_t ADDRB_CLR; /**< Page Erase/Write Address Buffer */ - __IOM uint32_t WDATA_CLR; /**< Write Data Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED24[3U]; /**< Reserved for future use */ - __IM uint32_t USERDATASIZE_CLR; /**< User Data Region Size Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - __IOM uint32_t MISCLOCKWORD_CLR; /**< Mass erase and User data page lock word */ - uint32_t RESERVED25[3U]; /**< Reserved for future use */ - __IOM uint32_t PWRCTRL_CLR; /**< Power control register */ - uint32_t RESERVED26[51U]; /**< Reserved for future use */ - __IOM uint32_t PAGELOCK0_CLR; /**< Main space page 0-31 lock word */ - __IOM uint32_t PAGELOCK1_CLR; /**< Main space page 32-63 lock word */ - __IOM uint32_t PAGELOCK2_CLR; /**< Main space page 64-95 lock word */ - __IOM uint32_t PAGELOCK3_CLR; /**< Main space page 96-127 lock word */ - uint32_t RESERVED27[4U]; /**< Reserved for future use */ - uint32_t RESERVED28[4U]; /**< Reserved for future use */ - uint32_t RESERVED29[4U]; /**< Reserved for future use */ - uint32_t RESERVED30[4U]; /**< Reserved for future use */ - uint32_t RESERVED31[12U]; /**< Reserved for future use */ - uint32_t RESERVED32[1U]; /**< Reserved for future use */ - uint32_t RESERVED33[8U]; /**< Reserved for future use */ - uint32_t RESERVED34[1U]; /**< Reserved for future use */ - uint32_t RESERVED35[910U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t READCTRL_TGL; /**< Read Control Register */ - __IOM uint32_t RDATACTRL_TGL; /**< Read Data Control Register */ - __IOM uint32_t WRITECTRL_TGL; /**< Write Control Register */ - __IOM uint32_t WRITECMD_TGL; /**< Write Command Register */ - __IOM uint32_t ADDRB_TGL; /**< Page Erase/Write Address Buffer */ - __IOM uint32_t WDATA_TGL; /**< Write Data Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED36[3U]; /**< Reserved for future use */ - __IM uint32_t USERDATASIZE_TGL; /**< User Data Region Size Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - __IOM uint32_t MISCLOCKWORD_TGL; /**< Mass erase and User data page lock word */ - uint32_t RESERVED37[3U]; /**< Reserved for future use */ - __IOM uint32_t PWRCTRL_TGL; /**< Power control register */ - uint32_t RESERVED38[51U]; /**< Reserved for future use */ - __IOM uint32_t PAGELOCK0_TGL; /**< Main space page 0-31 lock word */ - __IOM uint32_t PAGELOCK1_TGL; /**< Main space page 32-63 lock word */ - __IOM uint32_t PAGELOCK2_TGL; /**< Main space page 64-95 lock word */ - __IOM uint32_t PAGELOCK3_TGL; /**< Main space page 96-127 lock word */ - uint32_t RESERVED39[4U]; /**< Reserved for future use */ - uint32_t RESERVED40[4U]; /**< Reserved for future use */ - uint32_t RESERVED41[4U]; /**< Reserved for future use */ - uint32_t RESERVED42[4U]; /**< Reserved for future use */ - uint32_t RESERVED43[12U]; /**< Reserved for future use */ - uint32_t RESERVED44[1U]; /**< Reserved for future use */ - uint32_t RESERVED45[8U]; /**< Reserved for future use */ - uint32_t RESERVED46[1U]; /**< Reserved for future use */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t RDATACTRL; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE; /**< User Data Region Size Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD; /**< Mass erase and User data page lock word */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL; /**< Power control register */ + uint32_t RESERVED2[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3; /**< Main space page 96-127 lock word */ + uint32_t RESERVED3[4U]; /**< Reserved for future use */ + uint32_t RESERVED4[4U]; /**< Reserved for future use */ + uint32_t RESERVED5[4U]; /**< Reserved for future use */ + uint32_t RESERVED6[4U]; /**< Reserved for future use */ + uint32_t RESERVED7[12U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[8U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t READCTRL_SET; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_SET; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_SET; /**< Write Control Register */ + __IOM uint32_t WRITECMD_SET; /**< Write Command Register */ + __IOM uint32_t ADDRB_SET; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_SET; /**< Write Data Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED12[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_SET; /**< User Data Region Size Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_SET; /**< Mass erase and User data page lock word */ + uint32_t RESERVED13[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_SET; /**< Power control register */ + uint32_t RESERVED14[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_SET; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_SET; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_SET; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_SET; /**< Main space page 96-127 lock word */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + uint32_t RESERVED16[4U]; /**< Reserved for future use */ + uint32_t RESERVED17[4U]; /**< Reserved for future use */ + uint32_t RESERVED18[4U]; /**< Reserved for future use */ + uint32_t RESERVED19[12U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[8U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t READCTRL_CLR; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_CLR; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_CLR; /**< Write Control Register */ + __IOM uint32_t WRITECMD_CLR; /**< Write Command Register */ + __IOM uint32_t ADDRB_CLR; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_CLR; /**< Write Data Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED24[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_CLR; /**< User Data Region Size Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_CLR; /**< Mass erase and User data page lock word */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_CLR; /**< Power control register */ + uint32_t RESERVED26[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_CLR; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_CLR; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_CLR; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_CLR; /**< Main space page 96-127 lock word */ + uint32_t RESERVED27[4U]; /**< Reserved for future use */ + uint32_t RESERVED28[4U]; /**< Reserved for future use */ + uint32_t RESERVED29[4U]; /**< Reserved for future use */ + uint32_t RESERVED30[4U]; /**< Reserved for future use */ + uint32_t RESERVED31[12U]; /**< Reserved for future use */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + uint32_t RESERVED33[8U]; /**< Reserved for future use */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ + uint32_t RESERVED35[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t READCTRL_TGL; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_TGL; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_TGL; /**< Write Control Register */ + __IOM uint32_t WRITECMD_TGL; /**< Write Command Register */ + __IOM uint32_t ADDRB_TGL; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_TGL; /**< Write Data Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED36[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_TGL; /**< User Data Region Size Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_TGL; /**< Mass erase and User data page lock word */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_TGL; /**< Power control register */ + uint32_t RESERVED38[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_TGL; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_TGL; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_TGL; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_TGL; /**< Main space page 96-127 lock word */ + uint32_t RESERVED39[4U]; /**< Reserved for future use */ + uint32_t RESERVED40[4U]; /**< Reserved for future use */ + uint32_t RESERVED41[4U]; /**< Reserved for future use */ + uint32_t RESERVED42[4U]; /**< Reserved for future use */ + uint32_t RESERVED43[12U]; /**< Reserved for future use */ + uint32_t RESERVED44[1U]; /**< Reserved for future use */ + uint32_t RESERVED45[8U]; /**< Reserved for future use */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ } MSC_TypeDef; /** @} End of group EFR32SG28_MSC */ @@ -179,343 +177,343 @@ typedef struct *****************************************************************************/ /* Bit fields for MSC IPVERSION */ -#define _MSC_IPVERSION_RESETVALUE 0x00000007UL /**< Default value for MSC_IPVERSION */ -#define _MSC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MSC_IPVERSION */ -#define _MSC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MSC_IPVERSION */ -#define _MSC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_IPVERSION */ -#define _MSC_IPVERSION_IPVERSION_DEFAULT 0x00000007UL /**< Mode DEFAULT for MSC_IPVERSION */ -#define MSC_IPVERSION_IPVERSION_DEFAULT (_MSC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IPVERSION */ +#define _MSC_IPVERSION_RESETVALUE 0x00000007UL /**< Default value for MSC_IPVERSION */ +#define _MSC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_DEFAULT 0x00000007UL /**< Mode DEFAULT for MSC_IPVERSION */ +#define MSC_IPVERSION_IPVERSION_DEFAULT (_MSC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IPVERSION */ /* Bit fields for MSC READCTRL */ -#define _MSC_READCTRL_RESETVALUE 0x00200000UL /**< Default value for MSC_READCTRL */ -#define _MSC_READCTRL_MASK 0x00300000UL /**< Mask for MSC_READCTRL */ -#define _MSC_READCTRL_MODE_SHIFT 20 /**< Shift value for MSC_MODE */ -#define _MSC_READCTRL_MODE_MASK 0x300000UL /**< Bit mask for MSC_MODE */ -#define _MSC_READCTRL_MODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MSC_READCTRL */ -#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ -#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ -#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ -#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ -#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_READCTRL */ -#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 20) /**< Shifted mode WS0 for MSC_READCTRL */ -#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 20) /**< Shifted mode WS1 for MSC_READCTRL */ -#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 20) /**< Shifted mode WS2 for MSC_READCTRL */ -#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 20) /**< Shifted mode WS3 for MSC_READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x00200000UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x00300000UL /**< Mask for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 20 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x300000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 20) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 20) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 20) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 20) /**< Shifted mode WS3 for MSC_READCTRL */ /* Bit fields for MSC RDATACTRL */ -#define _MSC_RDATACTRL_RESETVALUE 0x00001000UL /**< Default value for MSC_RDATACTRL */ -#define _MSC_RDATACTRL_MASK 0x00001002UL /**< Mask for MSC_RDATACTRL */ -#define MSC_RDATACTRL_AFDIS (0x1UL << 1) /**< Automatic Invalidate Disable */ -#define _MSC_RDATACTRL_AFDIS_SHIFT 1 /**< Shift value for MSC_AFDIS */ -#define _MSC_RDATACTRL_AFDIS_MASK 0x2UL /**< Bit mask for MSC_AFDIS */ -#define _MSC_RDATACTRL_AFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RDATACTRL */ -#define MSC_RDATACTRL_AFDIS_DEFAULT (_MSC_RDATACTRL_AFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ -#define MSC_RDATACTRL_DOUTBUFEN (0x1UL << 12) /**< Flash dout pipeline buffer enable */ -#define _MSC_RDATACTRL_DOUTBUFEN_SHIFT 12 /**< Shift value for MSC_DOUTBUFEN */ -#define _MSC_RDATACTRL_DOUTBUFEN_MASK 0x1000UL /**< Bit mask for MSC_DOUTBUFEN */ -#define _MSC_RDATACTRL_DOUTBUFEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_RDATACTRL */ -#define MSC_RDATACTRL_DOUTBUFEN_DEFAULT (_MSC_RDATACTRL_DOUTBUFEN_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ +#define _MSC_RDATACTRL_RESETVALUE 0x00001000UL /**< Default value for MSC_RDATACTRL */ +#define _MSC_RDATACTRL_MASK 0x00001002UL /**< Mask for MSC_RDATACTRL */ +#define MSC_RDATACTRL_AFDIS (0x1UL << 1) /**< Automatic Invalidate Disable */ +#define _MSC_RDATACTRL_AFDIS_SHIFT 1 /**< Shift value for MSC_AFDIS */ +#define _MSC_RDATACTRL_AFDIS_MASK 0x2UL /**< Bit mask for MSC_AFDIS */ +#define _MSC_RDATACTRL_AFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_AFDIS_DEFAULT (_MSC_RDATACTRL_AFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_DOUTBUFEN (0x1UL << 12) /**< Flash dout pipeline buffer enable */ +#define _MSC_RDATACTRL_DOUTBUFEN_SHIFT 12 /**< Shift value for MSC_DOUTBUFEN */ +#define _MSC_RDATACTRL_DOUTBUFEN_MASK 0x1000UL /**< Bit mask for MSC_DOUTBUFEN */ +#define _MSC_RDATACTRL_DOUTBUFEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_DOUTBUFEN_DEFAULT (_MSC_RDATACTRL_DOUTBUFEN_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ /* Bit fields for MSC WRITECTRL */ -#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ -#define _MSC_WRITECTRL_MASK 0x03FF000BUL /**< Mask for MSC_WRITECTRL */ -#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ -#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ -#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ -#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ -#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ -#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ -#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ -#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ -#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ -#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ -#define MSC_WRITECTRL_LPWRITE (0x1UL << 3) /**< Low-Power Write */ -#define _MSC_WRITECTRL_LPWRITE_SHIFT 3 /**< Shift value for MSC_LPWRITE */ -#define _MSC_WRITECTRL_LPWRITE_MASK 0x8UL /**< Bit mask for MSC_LPWRITE */ -#define _MSC_WRITECTRL_LPWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ -#define MSC_WRITECTRL_LPWRITE_DEFAULT (_MSC_WRITECTRL_LPWRITE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ -#define _MSC_WRITECTRL_RANGECOUNT_SHIFT 16 /**< Shift value for MSC_RANGECOUNT */ -#define _MSC_WRITECTRL_RANGECOUNT_MASK 0x3FF0000UL /**< Bit mask for MSC_RANGECOUNT */ -#define _MSC_WRITECTRL_RANGECOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ -#define MSC_WRITECTRL_RANGECOUNT_DEFAULT (_MSC_WRITECTRL_RANGECOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x03FF000BUL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_LPWRITE (0x1UL << 3) /**< Low-Power Write */ +#define _MSC_WRITECTRL_LPWRITE_SHIFT 3 /**< Shift value for MSC_LPWRITE */ +#define _MSC_WRITECTRL_LPWRITE_MASK 0x8UL /**< Bit mask for MSC_LPWRITE */ +#define _MSC_WRITECTRL_LPWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_LPWRITE_DEFAULT (_MSC_WRITECTRL_LPWRITE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_RANGECOUNT_SHIFT 16 /**< Shift value for MSC_RANGECOUNT */ +#define _MSC_WRITECTRL_RANGECOUNT_MASK 0x3FF0000UL /**< Bit mask for MSC_RANGECOUNT */ +#define _MSC_WRITECTRL_RANGECOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RANGECOUNT_DEFAULT (_MSC_WRITECTRL_RANGECOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ /* Bit fields for MSC WRITECMD */ -#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ -#define _MSC_WRITECMD_MASK 0x00001136UL /**< Mask for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ -#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ -#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ -#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ -#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ -#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ -#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASERANGE (0x1UL << 4) /**< Erase range of pages */ -#define _MSC_WRITECMD_ERASERANGE_SHIFT 4 /**< Shift value for MSC_ERASERANGE */ -#define _MSC_WRITECMD_ERASERANGE_MASK 0x10UL /**< Bit mask for MSC_ERASERANGE */ -#define _MSC_WRITECMD_ERASERANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASERANGE_DEFAULT (_MSC_WRITECMD_ERASERANGE_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ -#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ -#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ -#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ -#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ -#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ -#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ -#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ -#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ -#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x00001136UL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASERANGE (0x1UL << 4) /**< Erase range of pages */ +#define _MSC_WRITECMD_ERASERANGE_SHIFT 4 /**< Shift value for MSC_ERASERANGE */ +#define _MSC_WRITECMD_ERASERANGE_MASK 0x10UL /**< Bit mask for MSC_ERASERANGE */ +#define _MSC_WRITECMD_ERASERANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASERANGE_DEFAULT (_MSC_WRITECMD_ERASERANGE_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ /* Bit fields for MSC ADDRB */ -#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ -#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ -#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ -#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ -#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ -#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ /* Bit fields for MSC WDATA */ -#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ -#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ -#define _MSC_WDATA_DATAW_SHIFT 0 /**< Shift value for MSC_DATAW */ -#define _MSC_WDATA_DATAW_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_DATAW */ -#define _MSC_WDATA_DATAW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ -#define MSC_WDATA_DATAW_DEFAULT (_MSC_WDATA_DATAW_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_DATAW_SHIFT 0 /**< Shift value for MSC_DATAW */ +#define _MSC_WDATA_DATAW_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_DATAW */ +#define _MSC_WDATA_DATAW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_DATAW_DEFAULT (_MSC_WDATA_DATAW_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ /* Bit fields for MSC STATUS */ -#define _MSC_STATUS_RESETVALUE 0x08000008UL /**< Default value for MSC_STATUS */ -#define _MSC_STATUS_MASK 0xF90100FFUL /**< Mask for MSC_STATUS */ -#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ -#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ -#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ -#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ -#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ -#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ -#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ -#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ -#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ -#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ -#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ -#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ -#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_ERASEABORTED (0x1UL << 4) /**< Erase Operation Aborted */ -#define _MSC_STATUS_ERASEABORTED_SHIFT 4 /**< Shift value for MSC_ERASEABORTED */ -#define _MSC_STATUS_ERASEABORTED_MASK 0x10UL /**< Bit mask for MSC_ERASEABORTED */ -#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_PENDING (0x1UL << 5) /**< Write Command In Queue */ -#define _MSC_STATUS_PENDING_SHIFT 5 /**< Shift value for MSC_PENDING */ -#define _MSC_STATUS_PENDING_MASK 0x20UL /**< Bit mask for MSC_PENDING */ -#define _MSC_STATUS_PENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_PENDING_DEFAULT (_MSC_STATUS_PENDING_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_TIMEOUT (0x1UL << 6) /**< Write Command Timeout */ -#define _MSC_STATUS_TIMEOUT_SHIFT 6 /**< Shift value for MSC_TIMEOUT */ -#define _MSC_STATUS_TIMEOUT_MASK 0x40UL /**< Bit mask for MSC_TIMEOUT */ -#define _MSC_STATUS_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_TIMEOUT_DEFAULT (_MSC_STATUS_TIMEOUT_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_RANGEPARTIAL (0x1UL << 7) /**< EraseRange with skipped locked pages */ -#define _MSC_STATUS_RANGEPARTIAL_SHIFT 7 /**< Shift value for MSC_RANGEPARTIAL */ -#define _MSC_STATUS_RANGEPARTIAL_MASK 0x80UL /**< Bit mask for MSC_RANGEPARTIAL */ -#define _MSC_STATUS_RANGEPARTIAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_RANGEPARTIAL_DEFAULT (_MSC_STATUS_RANGEPARTIAL_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_REGLOCK (0x1UL << 16) /**< Register Lock Status */ -#define _MSC_STATUS_REGLOCK_SHIFT 16 /**< Shift value for MSC_REGLOCK */ -#define _MSC_STATUS_REGLOCK_MASK 0x10000UL /**< Bit mask for MSC_REGLOCK */ -#define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define _MSC_STATUS_REGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_STATUS */ -#define _MSC_STATUS_REGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_STATUS */ -#define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_REGLOCK_UNLOCKED (_MSC_STATUS_REGLOCK_UNLOCKED << 16) /**< Shifted mode UNLOCKED for MSC_STATUS */ -#define MSC_STATUS_REGLOCK_LOCKED (_MSC_STATUS_REGLOCK_LOCKED << 16) /**< Shifted mode LOCKED for MSC_STATUS */ -#define MSC_STATUS_PWRON (0x1UL << 24) /**< Flash Power On Status */ -#define _MSC_STATUS_PWRON_SHIFT 24 /**< Shift value for MSC_PWRON */ -#define _MSC_STATUS_PWRON_MASK 0x1000000UL /**< Bit mask for MSC_PWRON */ -#define _MSC_STATUS_PWRON_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_PWRON_DEFAULT (_MSC_STATUS_PWRON_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_WREADY (0x1UL << 27) /**< Flash Write Ready */ -#define _MSC_STATUS_WREADY_SHIFT 27 /**< Shift value for MSC_WREADY */ -#define _MSC_STATUS_WREADY_MASK 0x8000000UL /**< Bit mask for MSC_WREADY */ -#define _MSC_STATUS_WREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_WREADY_DEFAULT (_MSC_STATUS_WREADY_DEFAULT << 27) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ -#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ -#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_RESETVALUE 0x08000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xF90100FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 4) /**< Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 4 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x10UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PENDING (0x1UL << 5) /**< Write Command In Queue */ +#define _MSC_STATUS_PENDING_SHIFT 5 /**< Shift value for MSC_PENDING */ +#define _MSC_STATUS_PENDING_MASK 0x20UL /**< Bit mask for MSC_PENDING */ +#define _MSC_STATUS_PENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PENDING_DEFAULT (_MSC_STATUS_PENDING_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_TIMEOUT (0x1UL << 6) /**< Write Command Timeout */ +#define _MSC_STATUS_TIMEOUT_SHIFT 6 /**< Shift value for MSC_TIMEOUT */ +#define _MSC_STATUS_TIMEOUT_MASK 0x40UL /**< Bit mask for MSC_TIMEOUT */ +#define _MSC_STATUS_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_TIMEOUT_DEFAULT (_MSC_STATUS_TIMEOUT_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_RANGEPARTIAL (0x1UL << 7) /**< EraseRange with skipped locked pages */ +#define _MSC_STATUS_RANGEPARTIAL_SHIFT 7 /**< Shift value for MSC_RANGEPARTIAL */ +#define _MSC_STATUS_RANGEPARTIAL_MASK 0x80UL /**< Bit mask for MSC_RANGEPARTIAL */ +#define _MSC_STATUS_RANGEPARTIAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_RANGEPARTIAL_DEFAULT (_MSC_STATUS_RANGEPARTIAL_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_REGLOCK (0x1UL << 16) /**< Register Lock Status */ +#define _MSC_STATUS_REGLOCK_SHIFT 16 /**< Shift value for MSC_REGLOCK */ +#define _MSC_STATUS_REGLOCK_MASK 0x10000UL /**< Bit mask for MSC_REGLOCK */ +#define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_REGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_STATUS */ +#define _MSC_STATUS_REGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_UNLOCKED (_MSC_STATUS_REGLOCK_UNLOCKED << 16) /**< Shifted mode UNLOCKED for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_LOCKED (_MSC_STATUS_REGLOCK_LOCKED << 16) /**< Shifted mode LOCKED for MSC_STATUS */ +#define MSC_STATUS_PWRON (0x1UL << 24) /**< Flash Power On Status */ +#define _MSC_STATUS_PWRON_SHIFT 24 /**< Shift value for MSC_PWRON */ +#define _MSC_STATUS_PWRON_MASK 0x1000000UL /**< Bit mask for MSC_PWRON */ +#define _MSC_STATUS_PWRON_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRON_DEFAULT (_MSC_STATUS_PWRON_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WREADY (0x1UL << 27) /**< Flash Write Ready */ +#define _MSC_STATUS_WREADY_SHIFT 27 /**< Shift value for MSC_WREADY */ +#define _MSC_STATUS_WREADY_MASK 0x8000000UL /**< Bit mask for MSC_WREADY */ +#define _MSC_STATUS_WREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WREADY_DEFAULT (_MSC_STATUS_WREADY_DEFAULT << 27) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ /* Bit fields for MSC IF */ -#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ -#define _MSC_IF_MASK 0x00000307UL /**< Mask for MSC_IF */ -#define MSC_IF_ERASE (0x1UL << 0) /**< Host Erase Done Interrupt Read Flag */ -#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ -#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ -#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ -#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ -#define MSC_IF_WRITE (0x1UL << 1) /**< Host Write Done Interrupt Read Flag */ -#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ -#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ -#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ -#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ -#define MSC_IF_WDATAOV (0x1UL << 2) /**< Host write buffer overflow */ -#define _MSC_IF_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ -#define _MSC_IF_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ -#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ -#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ -#define MSC_IF_PWRUPF (0x1UL << 8) /**< Flash Power Up Sequence Complete Flag */ -#define _MSC_IF_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ -#define _MSC_IF_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ -#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ -#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ -#define MSC_IF_PWROFF (0x1UL << 9) /**< Flash Power Off Sequence Complete Flag */ -#define _MSC_IF_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ -#define _MSC_IF_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ -#define _MSC_IF_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ -#define MSC_IF_PWROFF_DEFAULT (_MSC_IF_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x00000307UL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Host Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Host Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 2) /**< Host write buffer overflow */ +#define _MSC_IF_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 8) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWROFF (0x1UL << 9) /**< Flash Power Off Sequence Complete Flag */ +#define _MSC_IF_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ +#define _MSC_IF_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_IF_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWROFF_DEFAULT (_MSC_IF_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IF */ /* Bit fields for MSC IEN */ -#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ -#define _MSC_IEN_MASK 0x00000307UL /**< Mask for MSC_IEN */ -#define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt enable */ -#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ -#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ -#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ -#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ -#define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt enable */ -#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ -#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ -#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ -#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ -#define MSC_IEN_WDATAOV (0x1UL << 2) /**< write data buffer overflow irq enable */ -#define _MSC_IEN_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ -#define _MSC_IEN_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ -#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ -#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ -#define MSC_IEN_PWRUPF (0x1UL << 8) /**< Flash Power Up Seq done irq enable */ -#define _MSC_IEN_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ -#define _MSC_IEN_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ -#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ -#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ -#define MSC_IEN_PWROFF (0x1UL << 9) /**< Flash Power Off Seq done irq enable */ -#define _MSC_IEN_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ -#define _MSC_IEN_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ -#define _MSC_IEN_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ -#define MSC_IEN_PWROFF_DEFAULT (_MSC_IEN_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x00000307UL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 2) /**< write data buffer overflow irq enable */ +#define _MSC_IEN_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 8) /**< Flash Power Up Seq done irq enable */ +#define _MSC_IEN_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWROFF (0x1UL << 9) /**< Flash Power Off Seq done irq enable */ +#define _MSC_IEN_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ +#define _MSC_IEN_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_IEN_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWROFF_DEFAULT (_MSC_IEN_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IEN */ /* Bit fields for MSC USERDATASIZE */ -#define _MSC_USERDATASIZE_RESETVALUE 0x00000004UL /**< Default value for MSC_USERDATASIZE */ -#define _MSC_USERDATASIZE_MASK 0x0000003FUL /**< Mask for MSC_USERDATASIZE */ -#define _MSC_USERDATASIZE_USERDATASIZE_SHIFT 0 /**< Shift value for MSC_USERDATASIZE */ -#define _MSC_USERDATASIZE_USERDATASIZE_MASK 0x3FUL /**< Bit mask for MSC_USERDATASIZE */ -#define _MSC_USERDATASIZE_USERDATASIZE_DEFAULT 0x00000004UL /**< Mode DEFAULT for MSC_USERDATASIZE */ -#define MSC_USERDATASIZE_USERDATASIZE_DEFAULT (_MSC_USERDATASIZE_USERDATASIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_RESETVALUE 0x00000004UL /**< Default value for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_MASK 0x0000003FUL /**< Mask for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_SHIFT 0 /**< Shift value for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_MASK 0x3FUL /**< Bit mask for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_DEFAULT 0x00000004UL /**< Mode DEFAULT for MSC_USERDATASIZE */ +#define MSC_USERDATASIZE_USERDATASIZE_DEFAULT (_MSC_USERDATASIZE_USERDATASIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_USERDATASIZE */ /* Bit fields for MSC CMD */ -#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ -#define _MSC_CMD_MASK 0x00000011UL /**< Mask for MSC_CMD */ -#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ -#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ -#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ -#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ -#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ -#define MSC_CMD_PWROFF (0x1UL << 4) /**< Flash power off/sleep command */ -#define _MSC_CMD_PWROFF_SHIFT 4 /**< Shift value for MSC_PWROFF */ -#define _MSC_CMD_PWROFF_MASK 0x10UL /**< Bit mask for MSC_PWROFF */ -#define _MSC_CMD_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ -#define MSC_CMD_PWROFF_DEFAULT (_MSC_CMD_PWROFF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000011UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWROFF (0x1UL << 4) /**< Flash power off/sleep command */ +#define _MSC_CMD_PWROFF_SHIFT 4 /**< Shift value for MSC_PWROFF */ +#define _MSC_CMD_PWROFF_MASK 0x10UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_CMD_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWROFF_DEFAULT (_MSC_CMD_PWROFF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CMD */ /* Bit fields for MSC LOCK */ -#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ -#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ -#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ -#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ -#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ -#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ -#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ -#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ -#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ -#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ /* Bit fields for MSC MISCLOCKWORD */ -#define _MSC_MISCLOCKWORD_RESETVALUE 0x00000011UL /**< Default value for MSC_MISCLOCKWORD */ -#define _MSC_MISCLOCKWORD_MASK 0x00000011UL /**< Mask for MSC_MISCLOCKWORD */ -#define MSC_MISCLOCKWORD_MELOCKBIT (0x1UL << 0) /**< Mass Erase Lock */ -#define _MSC_MISCLOCKWORD_MELOCKBIT_SHIFT 0 /**< Shift value for MSC_MELOCKBIT */ -#define _MSC_MISCLOCKWORD_MELOCKBIT_MASK 0x1UL /**< Bit mask for MSC_MELOCKBIT */ -#define _MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ -#define MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ -#define MSC_MISCLOCKWORD_UDLOCKBIT (0x1UL << 4) /**< User Data Lock */ -#define _MSC_MISCLOCKWORD_UDLOCKBIT_SHIFT 4 /**< Shift value for MSC_UDLOCKBIT */ -#define _MSC_MISCLOCKWORD_UDLOCKBIT_MASK 0x10UL /**< Bit mask for MSC_UDLOCKBIT */ -#define _MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ -#define MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ +#define _MSC_MISCLOCKWORD_RESETVALUE 0x00000011UL /**< Default value for MSC_MISCLOCKWORD */ +#define _MSC_MISCLOCKWORD_MASK 0x00000011UL /**< Mask for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_MELOCKBIT (0x1UL << 0) /**< Mass Erase Lock */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_SHIFT 0 /**< Shift value for MSC_MELOCKBIT */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_MASK 0x1UL /**< Bit mask for MSC_MELOCKBIT */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_UDLOCKBIT (0x1UL << 4) /**< User Data Lock */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_SHIFT 4 /**< Shift value for MSC_UDLOCKBIT */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_MASK 0x10UL /**< Bit mask for MSC_UDLOCKBIT */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ /* Bit fields for MSC PWRCTRL */ -#define _MSC_PWRCTRL_RESETVALUE 0x00100002UL /**< Default value for MSC_PWRCTRL */ -#define _MSC_PWRCTRL_MASK 0x00FF0013UL /**< Mask for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFONEM1ENTRY (0x1UL << 0) /**< Power down Flash macro when enter EM1 */ -#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_SHIFT 0 /**< Shift value for MSC_PWROFFONEM1ENTRY */ -#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_MASK 0x1UL /**< Bit mask for MSC_PWROFFONEM1ENTRY */ -#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFONEM1PENTRY (0x1UL << 1) /**< Power down Flash macro when enter EM1P */ -#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_SHIFT 1 /**< Shift value for MSC_PWROFFONEM1PENTRY */ -#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_MASK 0x2UL /**< Bit mask for MSC_PWROFFONEM1PENTRY */ -#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFENTRYAGAIN (0x1UL << 4) /**< POWER down flash again in EM1/EM1p */ -#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_SHIFT 4 /**< Shift value for MSC_PWROFFENTRYAGAIN */ -#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_MASK 0x10UL /**< Bit mask for MSC_PWROFFENTRYAGAIN */ -#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT (_MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ -#define _MSC_PWRCTRL_PWROFFDLY_SHIFT 16 /**< Shift value for MSC_PWROFFDLY */ -#define _MSC_PWRCTRL_PWROFFDLY_MASK 0xFF0000UL /**< Bit mask for MSC_PWROFFDLY */ -#define _MSC_PWRCTRL_PWROFFDLY_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFDLY_DEFAULT (_MSC_PWRCTRL_PWROFFDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define _MSC_PWRCTRL_RESETVALUE 0x00100002UL /**< Default value for MSC_PWRCTRL */ +#define _MSC_PWRCTRL_MASK 0x00FF0013UL /**< Mask for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1ENTRY (0x1UL << 0) /**< Power down Flash macro when enter EM1 */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_SHIFT 0 /**< Shift value for MSC_PWROFFONEM1ENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_MASK 0x1UL /**< Bit mask for MSC_PWROFFONEM1ENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1PENTRY (0x1UL << 1) /**< Power down Flash macro when enter EM1P */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_SHIFT 1 /**< Shift value for MSC_PWROFFONEM1PENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_MASK 0x2UL /**< Bit mask for MSC_PWROFFONEM1PENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFENTRYAGAIN (0x1UL << 4) /**< POWER down flash again in EM1/EM1p */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_SHIFT 4 /**< Shift value for MSC_PWROFFENTRYAGAIN */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_MASK 0x10UL /**< Bit mask for MSC_PWROFFENTRYAGAIN */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT (_MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define _MSC_PWRCTRL_PWROFFDLY_SHIFT 16 /**< Shift value for MSC_PWROFFDLY */ +#define _MSC_PWRCTRL_PWROFFDLY_MASK 0xFF0000UL /**< Bit mask for MSC_PWROFFDLY */ +#define _MSC_PWRCTRL_PWROFFDLY_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFDLY_DEFAULT (_MSC_PWRCTRL_PWROFFDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ /* Bit fields for MSC PAGELOCK0 */ -#define _MSC_PAGELOCK0_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK0 */ -#define _MSC_PAGELOCK0_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK0 */ -#define _MSC_PAGELOCK0_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ -#define _MSC_PAGELOCK0_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ -#define _MSC_PAGELOCK0_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK0 */ -#define MSC_PAGELOCK0_LOCKBIT_DEFAULT (_MSC_PAGELOCK0_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK0 */ +#define _MSC_PAGELOCK0_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK0 */ +#define _MSC_PAGELOCK0_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK0 */ +#define _MSC_PAGELOCK0_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK0_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK0_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK0 */ +#define MSC_PAGELOCK0_LOCKBIT_DEFAULT (_MSC_PAGELOCK0_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK0 */ /* Bit fields for MSC PAGELOCK1 */ -#define _MSC_PAGELOCK1_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK1 */ -#define _MSC_PAGELOCK1_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK1 */ -#define _MSC_PAGELOCK1_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ -#define _MSC_PAGELOCK1_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ -#define _MSC_PAGELOCK1_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK1 */ -#define MSC_PAGELOCK1_LOCKBIT_DEFAULT (_MSC_PAGELOCK1_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK1 */ +#define _MSC_PAGELOCK1_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK1 */ +#define _MSC_PAGELOCK1_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK1 */ +#define _MSC_PAGELOCK1_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK1_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK1_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK1 */ +#define MSC_PAGELOCK1_LOCKBIT_DEFAULT (_MSC_PAGELOCK1_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK1 */ /* Bit fields for MSC PAGELOCK2 */ -#define _MSC_PAGELOCK2_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK2 */ -#define _MSC_PAGELOCK2_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK2 */ -#define _MSC_PAGELOCK2_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ -#define _MSC_PAGELOCK2_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ -#define _MSC_PAGELOCK2_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK2 */ -#define MSC_PAGELOCK2_LOCKBIT_DEFAULT (_MSC_PAGELOCK2_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK2 */ +#define _MSC_PAGELOCK2_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK2 */ +#define _MSC_PAGELOCK2_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK2 */ +#define _MSC_PAGELOCK2_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK2_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK2_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK2 */ +#define MSC_PAGELOCK2_LOCKBIT_DEFAULT (_MSC_PAGELOCK2_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK2 */ /* Bit fields for MSC PAGELOCK3 */ -#define _MSC_PAGELOCK3_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK3 */ -#define _MSC_PAGELOCK3_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK3 */ -#define _MSC_PAGELOCK3_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ -#define _MSC_PAGELOCK3_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ -#define _MSC_PAGELOCK3_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK3 */ -#define MSC_PAGELOCK3_LOCKBIT_DEFAULT (_MSC_PAGELOCK3_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK3 */ +#define _MSC_PAGELOCK3_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK3 */ +#define _MSC_PAGELOCK3_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK3 */ +#define _MSC_PAGELOCK3_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK3_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK3_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK3 */ +#define MSC_PAGELOCK3_LOCKBIT_DEFAULT (_MSC_PAGELOCK3_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK3 */ /** @} End of group EFR32SG28_MSC_BitFields */ /** @} End of group EFR32SG28_MSC */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_pcnt.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_pcnt.h index 6945a63162..4e00accf93 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_pcnt.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_PCNT_H #define EFR32SG28_PCNT_H - #define PCNT_HAS_SET_CLEAR /**************************************************************************//** @@ -43,75 +42,74 @@ *****************************************************************************/ /** PCNT Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t EN; /**< Module Enable Register */ - __IOM uint32_t SWRST; /**< Software Reset Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IM uint32_t CNT; /**< Counter Value Register */ - __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */ - __IOM uint32_t TOP; /**< Top Value Register */ - __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ - __IOM uint32_t OVSCTRL; /**< Oversampling Control Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - uint32_t RESERVED0[1008U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t EN_SET; /**< Module Enable Register */ - __IOM uint32_t SWRST_SET; /**< Software Reset Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IM uint32_t CNT_SET; /**< Counter Value Register */ - __IM uint32_t AUXCNT_SET; /**< Auxiliary Counter Value Register */ - __IOM uint32_t TOP_SET; /**< Top Value Register */ - __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ - __IOM uint32_t OVSCTRL_SET; /**< Oversampling Control Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - uint32_t RESERVED1[1008U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t EN_CLR; /**< Module Enable Register */ - __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IM uint32_t CNT_CLR; /**< Counter Value Register */ - __IM uint32_t AUXCNT_CLR; /**< Auxiliary Counter Value Register */ - __IOM uint32_t TOP_CLR; /**< Top Value Register */ - __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ - __IOM uint32_t OVSCTRL_CLR; /**< Oversampling Control Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - uint32_t RESERVED2[1008U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t EN_TGL; /**< Module Enable Register */ - __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IM uint32_t CNT_TGL; /**< Counter Value Register */ - __IM uint32_t AUXCNT_TGL; /**< Auxiliary Counter Value Register */ - __IOM uint32_t TOP_TGL; /**< Top Value Register */ - __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ - __IOM uint32_t OVSCTRL_TGL; /**< Oversampling Control Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP; /**< Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED0[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t CNT_SET; /**< Counter Value Register */ + __IM uint32_t AUXCNT_SET; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_SET; /**< Top Value Register */ + __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_SET; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED1[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t CNT_CLR; /**< Counter Value Register */ + __IM uint32_t AUXCNT_CLR; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_CLR; /**< Top Value Register */ + __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_CLR; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED2[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t CNT_TGL; /**< Counter Value Register */ + __IM uint32_t AUXCNT_TGL; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_TGL; /**< Top Value Register */ + __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_TGL; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ } PCNT_TypeDef; /** @} End of group EFR32SG28_PCNT */ @@ -123,11 +121,11 @@ typedef struct *****************************************************************************/ /* Bit fields for PCNT IPVERSION */ -#define _PCNT_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for PCNT_IPVERSION */ -#define _PCNT_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PCNT_IPVERSION */ -#define _PCNT_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PCNT_IPVERSION */ -#define _PCNT_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PCNT_IPVERSION */ -#define _PCNT_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for PCNT_IPVERSION */ #define PCNT_IPVERSION_IPVERSION_DEFAULT (_PCNT_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IPVERSION */ /* Bit fields for PCNT EN */ @@ -299,41 +297,41 @@ typedef struct #define PCNT_CMD_STOPAUXCNT_DEFAULT (_PCNT_CMD_STOPAUXCNT_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_CMD */ /* Bit fields for PCNT STATUS */ -#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ -#define _PCNT_STATUS_MASK 0x0000001FUL /**< Mask for PCNT_STATUS */ -#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */ -#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ -#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ -#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ -#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ -#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ -#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */ -#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */ -#define PCNT_STATUS_TOPBV (0x1UL << 1) /**< TOP Buffer Valid */ -#define _PCNT_STATUS_TOPBV_SHIFT 1 /**< Shift value for PCNT_TOPBV */ -#define _PCNT_STATUS_TOPBV_MASK 0x2UL /**< Bit mask for PCNT_TOPBV */ -#define _PCNT_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_TOPBV_DEFAULT (_PCNT_STATUS_TOPBV_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_PCNTLOCKSTATUS (0x1UL << 2) /**< Lock Status */ -#define _PCNT_STATUS_PCNTLOCKSTATUS_SHIFT 2 /**< Shift value for PCNT_PCNTLOCKSTATUS */ -#define _PCNT_STATUS_PCNTLOCKSTATUS_MASK 0x4UL /**< Bit mask for PCNT_PCNTLOCKSTATUS */ -#define _PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ -#define _PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for PCNT_STATUS */ -#define _PCNT_STATUS_PCNTLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for PCNT_STATUS */ -#define PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT (_PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ +#define _PCNT_STATUS_MASK 0x0000001FUL /**< Mask for PCNT_STATUS */ +#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */ +#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ +#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ +#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_TOPBV (0x1UL << 1) /**< TOP Buffer Valid */ +#define _PCNT_STATUS_TOPBV_SHIFT 1 /**< Shift value for PCNT_TOPBV */ +#define _PCNT_STATUS_TOPBV_MASK 0x2UL /**< Bit mask for PCNT_TOPBV */ +#define _PCNT_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_TOPBV_DEFAULT (_PCNT_STATUS_TOPBV_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS (0x1UL << 2) /**< Lock Status */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_SHIFT 2 /**< Shift value for PCNT_PCNTLOCKSTATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_MASK 0x4UL /**< Bit mask for PCNT_PCNTLOCKSTATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for PCNT_STATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT (_PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_STATUS */ #define PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED << 2) /**< Shifted mode UNLOCKED for PCNT_STATUS */ -#define PCNT_STATUS_PCNTLOCKSTATUS_LOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_LOCKED << 2) /**< Shifted mode LOCKED for PCNT_STATUS */ -#define PCNT_STATUS_CNTRUNNING (0x1UL << 3) /**< Main Counter running status */ -#define _PCNT_STATUS_CNTRUNNING_SHIFT 3 /**< Shift value for PCNT_CNTRUNNING */ -#define _PCNT_STATUS_CNTRUNNING_MASK 0x8UL /**< Bit mask for PCNT_CNTRUNNING */ -#define _PCNT_STATUS_CNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_CNTRUNNING_DEFAULT (_PCNT_STATUS_CNTRUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_AUXCNTRUNNING (0x1UL << 4) /**< Aux Counter running status */ -#define _PCNT_STATUS_AUXCNTRUNNING_SHIFT 4 /**< Shift value for PCNT_AUXCNTRUNNING */ -#define _PCNT_STATUS_AUXCNTRUNNING_MASK 0x10UL /**< Bit mask for PCNT_AUXCNTRUNNING */ -#define _PCNT_STATUS_AUXCNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_AUXCNTRUNNING_DEFAULT (_PCNT_STATUS_AUXCNTRUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS_LOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_LOCKED << 2) /**< Shifted mode LOCKED for PCNT_STATUS */ +#define PCNT_STATUS_CNTRUNNING (0x1UL << 3) /**< Main Counter running status */ +#define _PCNT_STATUS_CNTRUNNING_SHIFT 3 /**< Shift value for PCNT_CNTRUNNING */ +#define _PCNT_STATUS_CNTRUNNING_MASK 0x8UL /**< Bit mask for PCNT_CNTRUNNING */ +#define _PCNT_STATUS_CNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_CNTRUNNING_DEFAULT (_PCNT_STATUS_CNTRUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_AUXCNTRUNNING (0x1UL << 4) /**< Aux Counter running status */ +#define _PCNT_STATUS_AUXCNTRUNNING_SHIFT 4 /**< Shift value for PCNT_AUXCNTRUNNING */ +#define _PCNT_STATUS_AUXCNTRUNNING_MASK 0x10UL /**< Bit mask for PCNT_AUXCNTRUNNING */ +#define _PCNT_STATUS_AUXCNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_AUXCNTRUNNING_DEFAULT (_PCNT_STATUS_AUXCNTRUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_STATUS */ /* Bit fields for PCNT IF */ #define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_pfmxpprf.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_pfmxpprf.h index 135084e655..1e7ffe2f61 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_pfmxpprf.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_pfmxpprf.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_PFMXPPRF_H #define EFR32SG28_PFMXPPRF_H - #define PFMXPPRF_HAS_SET_CLEAR /**************************************************************************//** @@ -43,31 +42,30 @@ *****************************************************************************/ /** PFMXPPRF Register Declaration. */ -typedef struct -{ - __IOM uint32_t RFIMDCDCCTRL0; /**< New Register */ - __IOM uint32_t RFIMDCDCCTRL1; /**< New Register */ - __IOM uint32_t RFIMDCDCCTRL2; /**< New Register */ - __IM uint32_t RFIMDCDCSTATUS; /**< New Register */ - __IOM uint32_t RPURATD0; /**< Root Access Type Descriptor Register */ - uint32_t RESERVED0[1019U]; /**< Reserved for future use */ - __IOM uint32_t RFIMDCDCCTRL0_SET; /**< New Register */ - __IOM uint32_t RFIMDCDCCTRL1_SET; /**< New Register */ - __IOM uint32_t RFIMDCDCCTRL2_SET; /**< New Register */ - __IM uint32_t RFIMDCDCSTATUS_SET; /**< New Register */ - __IOM uint32_t RPURATD0_SET; /**< Root Access Type Descriptor Register */ - uint32_t RESERVED1[1019U]; /**< Reserved for future use */ - __IOM uint32_t RFIMDCDCCTRL0_CLR; /**< New Register */ - __IOM uint32_t RFIMDCDCCTRL1_CLR; /**< New Register */ - __IOM uint32_t RFIMDCDCCTRL2_CLR; /**< New Register */ - __IM uint32_t RFIMDCDCSTATUS_CLR; /**< New Register */ - __IOM uint32_t RPURATD0_CLR; /**< Root Access Type Descriptor Register */ - uint32_t RESERVED2[1019U]; /**< Reserved for future use */ - __IOM uint32_t RFIMDCDCCTRL0_TGL; /**< New Register */ - __IOM uint32_t RFIMDCDCCTRL1_TGL; /**< New Register */ - __IOM uint32_t RFIMDCDCCTRL2_TGL; /**< New Register */ - __IM uint32_t RFIMDCDCSTATUS_TGL; /**< New Register */ - __IOM uint32_t RPURATD0_TGL; /**< Root Access Type Descriptor Register */ +typedef struct { + __IOM uint32_t RFIMDCDCCTRL0; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL1; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL2; /**< New Register */ + __IM uint32_t RFIMDCDCSTATUS; /**< New Register */ + __IOM uint32_t RPURATD0; /**< Root Access Type Descriptor Register */ + uint32_t RESERVED0[1019U]; /**< Reserved for future use */ + __IOM uint32_t RFIMDCDCCTRL0_SET; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL1_SET; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL2_SET; /**< New Register */ + __IM uint32_t RFIMDCDCSTATUS_SET; /**< New Register */ + __IOM uint32_t RPURATD0_SET; /**< Root Access Type Descriptor Register */ + uint32_t RESERVED1[1019U]; /**< Reserved for future use */ + __IOM uint32_t RFIMDCDCCTRL0_CLR; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL1_CLR; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL2_CLR; /**< New Register */ + __IM uint32_t RFIMDCDCSTATUS_CLR; /**< New Register */ + __IOM uint32_t RPURATD0_CLR; /**< Root Access Type Descriptor Register */ + uint32_t RESERVED2[1019U]; /**< Reserved for future use */ + __IOM uint32_t RFIMDCDCCTRL0_TGL; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL1_TGL; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL2_TGL; /**< New Register */ + __IM uint32_t RFIMDCDCSTATUS_TGL; /**< New Register */ + __IOM uint32_t RPURATD0_TGL; /**< Root Access Type Descriptor Register */ } PFMXPPRF_TypeDef; /** @} End of group EFR32SG28_PFMXPPRF */ @@ -79,136 +77,136 @@ typedef struct *****************************************************************************/ /* Bit fields for PFMXPPRF RFIMDCDCCTRL0 */ -#define _PFMXPPRF_RFIMDCDCCTRL0_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL0 */ -#define _PFMXPPRF_RFIMDCDCCTRL0_MASK 0x80000003UL /**< Mask for PFMXPPRF_RFIMDCDCCTRL0 */ -#define PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ (0x1UL << 0) /**< TX Max Req */ -#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_SHIFT 0 /**< Shift value for PFMXPPRF_TXMAXREQ */ -#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_MASK 0x1UL /**< Bit mask for PFMXPPRF_TXMAXREQ */ -#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0 */ -#define PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0*/ -#define PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ (0x1UL << 1) /**< RX PP Req */ -#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_SHIFT 1 /**< Shift value for PFMXPPRF_RXPPREQ */ -#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_MASK 0x2UL /**< Bit mask for PFMXPPRF_RXPPREQ */ -#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0 */ -#define PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0*/ +#define _PFMXPPRF_RFIMDCDCCTRL0_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL0 */ +#define _PFMXPPRF_RFIMDCDCCTRL0_MASK 0x80000003UL /**< Mask for PFMXPPRF_RFIMDCDCCTRL0 */ +#define PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ (0x1UL << 0) /**< TX Max Req */ +#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_SHIFT 0 /**< Shift value for PFMXPPRF_TXMAXREQ */ +#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_MASK 0x1UL /**< Bit mask for PFMXPPRF_TXMAXREQ */ +#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0 */ +#define PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0*/ +#define PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ (0x1UL << 1) /**< RX PP Req */ +#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_SHIFT 1 /**< Shift value for PFMXPPRF_RXPPREQ */ +#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_MASK 0x2UL /**< Bit mask for PFMXPPRF_RXPPREQ */ +#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0 */ +#define PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0*/ /* Bit fields for PFMXPPRF RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_RESETVALUE 0x00000014UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_MASK 0x0000003FUL /**< Mask for PFMXPPRF_RFIMDCDCCTRL1 */ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN (0x1UL << 0) /**< DCDC DIV Enable */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_SHIFT 0 /**< Shift value for PFMXPPRF_DCDCDIVEN */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_MASK 0x1UL /**< Bit mask for PFMXPPRF_DCDCDIVEN */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN (0x1UL << 1) /**< DCDC DIV Inverter Enable */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_SHIFT 1 /**< Shift value for PFMXPPRF_DCDCDIVINVEN */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_MASK 0x2UL /**< Bit mask for PFMXPPRF_DCDCDIVINVEN */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_SHIFT 2 /**< Shift value for PFMXPPRF_DCDCDIVRATIO */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_MASK 0x3CUL /**< Bit mask for PFMXPPRF_DCDCDIVRATIO */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT 0x00000005UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 0x00000000UL /**< Mode DIVRATIO8 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 0x00000001UL /**< Mode DIVRATIO9 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 0x00000002UL /**< Mode DIVRATIO10 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 0x00000003UL /**< Mode DIVRATIO11 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 0x00000004UL /**< Mode DIVRATIO12 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 0x00000005UL /**< Mode DIVRATIO13 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 0x00000006UL /**< Mode DIVRATIO14 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 0x00000007UL /**< Mode DIVRATIO15 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 0x00000008UL /**< Mode DIVRATIO16 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 0x00000009UL /**< Mode DIVRATIO17 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 0x0000000AUL /**< Mode DIVRATIO18 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 0x0000000BUL /**< Mode DIVRATIO19 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 0x0000000CUL /**< Mode DIVRATIO20 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 0x0000000DUL /**< Mode DIVRATIO21 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 0x0000000EUL /**< Mode DIVRATIO22 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 0x0000000FUL /**< Mode DIVRATIO23 for PFMXPPRF_RFIMDCDCCTRL1 */ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 << 2) /**< Shifted mode DIVRATIO8 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 << 2) /**< Shifted mode DIVRATIO9 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 << 2) /**< Shifted mode DIVRATIO10 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 << 2) /**< Shifted mode DIVRATIO11 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 << 2) /**< Shifted mode DIVRATIO12 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 << 2) /**< Shifted mode DIVRATIO13 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 << 2) /**< Shifted mode DIVRATIO14 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 << 2) /**< Shifted mode DIVRATIO15 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 << 2) /**< Shifted mode DIVRATIO16 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 << 2) /**< Shifted mode DIVRATIO17 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 << 2) /**< Shifted mode DIVRATIO18 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 << 2) /**< Shifted mode DIVRATIO19 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 << 2) /**< Shifted mode DIVRATIO20 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 << 2) /**< Shifted mode DIVRATIO21 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 << 2) /**< Shifted mode DIVRATIO22 for PFMXPPRF_RFIMDCDCCTRL1*/ -#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 << 2) /**< Shifted mode DIVRATIO23 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define _PFMXPPRF_RFIMDCDCCTRL1_RESETVALUE 0x00000014UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_MASK 0x0000003FUL /**< Mask for PFMXPPRF_RFIMDCDCCTRL1 */ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN (0x1UL << 0) /**< DCDC DIV Enable */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_SHIFT 0 /**< Shift value for PFMXPPRF_DCDCDIVEN */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_MASK 0x1UL /**< Bit mask for PFMXPPRF_DCDCDIVEN */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN (0x1UL << 1) /**< DCDC DIV Inverter Enable */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_SHIFT 1 /**< Shift value for PFMXPPRF_DCDCDIVINVEN */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_MASK 0x2UL /**< Bit mask for PFMXPPRF_DCDCDIVINVEN */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_SHIFT 2 /**< Shift value for PFMXPPRF_DCDCDIVRATIO */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_MASK 0x3CUL /**< Bit mask for PFMXPPRF_DCDCDIVRATIO */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT 0x00000005UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 0x00000000UL /**< Mode DIVRATIO8 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 0x00000001UL /**< Mode DIVRATIO9 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 0x00000002UL /**< Mode DIVRATIO10 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 0x00000003UL /**< Mode DIVRATIO11 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 0x00000004UL /**< Mode DIVRATIO12 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 0x00000005UL /**< Mode DIVRATIO13 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 0x00000006UL /**< Mode DIVRATIO14 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 0x00000007UL /**< Mode DIVRATIO15 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 0x00000008UL /**< Mode DIVRATIO16 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 0x00000009UL /**< Mode DIVRATIO17 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 0x0000000AUL /**< Mode DIVRATIO18 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 0x0000000BUL /**< Mode DIVRATIO19 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 0x0000000CUL /**< Mode DIVRATIO20 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 0x0000000DUL /**< Mode DIVRATIO21 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 0x0000000EUL /**< Mode DIVRATIO22 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 0x0000000FUL /**< Mode DIVRATIO23 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 << 2) /**< Shifted mode DIVRATIO8 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 << 2) /**< Shifted mode DIVRATIO9 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 << 2) /**< Shifted mode DIVRATIO10 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 << 2) /**< Shifted mode DIVRATIO11 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 << 2) /**< Shifted mode DIVRATIO12 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 << 2) /**< Shifted mode DIVRATIO13 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 << 2) /**< Shifted mode DIVRATIO14 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 << 2) /**< Shifted mode DIVRATIO15 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 << 2) /**< Shifted mode DIVRATIO16 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 << 2) /**< Shifted mode DIVRATIO17 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 << 2) /**< Shifted mode DIVRATIO18 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 << 2) /**< Shifted mode DIVRATIO19 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 << 2) /**< Shifted mode DIVRATIO20 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 << 2) /**< Shifted mode DIVRATIO21 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 << 2) /**< Shifted mode DIVRATIO22 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 << 2) /**< Shifted mode DIVRATIO23 for PFMXPPRF_RFIMDCDCCTRL1*/ /* Bit fields for PFMXPPRF RFIMDCDCCTRL2 */ -#define _PFMXPPRF_RFIMDCDCCTRL2_RESETVALUE 0x0AD0B4A0UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL2 */ -#define _PFMXPPRF_RFIMDCDCCTRL2_MASK 0x9FFFFFFFUL /**< Mask for PFMXPPRF_RFIMDCDCCTRL2 */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_SHIFT 0 /**< Shift value for PFMXPPRF_PPTMAX */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_MASK 0x1FFUL /**< Bit mask for PFMXPPRF_PPTMAX */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT 0x000000A0UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ -#define PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_SHIFT 9 /**< Shift value for PFMXPPRF_PPTMIN */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_MASK 0x3FE00UL /**< Bit mask for PFMXPPRF_PPTMIN */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT 0x0000005AUL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ -#define PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT << 9) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_SHIFT 18 /**< Shift value for PFMXPPRF_PPND */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_MASK 0x7FC0000UL /**< Bit mask for PFMXPPRF_PPND */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT 0x000000B4UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ -#define PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT << 18) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ -#define PFMXPPRF_RFIMDCDCCTRL2_PPCALEN (0x1UL << 27) /**< Pulse Pairing Calibration Loop Enable */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_SHIFT 27 /**< Shift value for PFMXPPRF_PPCALEN */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_MASK 0x8000000UL /**< Bit mask for PFMXPPRF_PPCALEN */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ -#define PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT << 27) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ -#define PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY (0x1UL << 28) /**< Pulse Pairing Sync Only */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_SHIFT 28 /**< Shift value for PFMXPPRF_PPSYNCONLY */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_MASK 0x10000000UL /**< Bit mask for PFMXPPRF_PPSYNCONLY */ -#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ -#define PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT << 28) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ +#define _PFMXPPRF_RFIMDCDCCTRL2_RESETVALUE 0x0AD0B4A0UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL2 */ +#define _PFMXPPRF_RFIMDCDCCTRL2_MASK 0x9FFFFFFFUL /**< Mask for PFMXPPRF_RFIMDCDCCTRL2 */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_SHIFT 0 /**< Shift value for PFMXPPRF_PPTMAX */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_MASK 0x1FFUL /**< Bit mask for PFMXPPRF_PPTMAX */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT 0x000000A0UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ +#define PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_SHIFT 9 /**< Shift value for PFMXPPRF_PPTMIN */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_MASK 0x3FE00UL /**< Bit mask for PFMXPPRF_PPTMIN */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT 0x0000005AUL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ +#define PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT << 9) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_SHIFT 18 /**< Shift value for PFMXPPRF_PPND */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_MASK 0x7FC0000UL /**< Bit mask for PFMXPPRF_PPND */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT 0x000000B4UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ +#define PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT << 18) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ +#define PFMXPPRF_RFIMDCDCCTRL2_PPCALEN (0x1UL << 27) /**< Pulse Pairing Calibration Loop Enable */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_SHIFT 27 /**< Shift value for PFMXPPRF_PPCALEN */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_MASK 0x8000000UL /**< Bit mask for PFMXPPRF_PPCALEN */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ +#define PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT << 27) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ +#define PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY (0x1UL << 28) /**< Pulse Pairing Sync Only */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_SHIFT 28 /**< Shift value for PFMXPPRF_PPSYNCONLY */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_MASK 0x10000000UL /**< Bit mask for PFMXPPRF_PPSYNCONLY */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ +#define PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT << 28) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ /* Bit fields for PFMXPPRF RFIMDCDCSTATUS */ -#define _PFMXPPRF_RFIMDCDCSTATUS_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RFIMDCDCSTATUS */ -#define _PFMXPPRF_RFIMDCDCSTATUS_MASK 0x0001FF07UL /**< Mask for PFMXPPRF_RFIMDCDCSTATUS */ -#define PFMXPPRF_RFIMDCDCSTATUS_DCDCEN (0x1UL << 0) /**< DCDC Enable Status */ -#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_SHIFT 0 /**< Shift value for PFMXPPRF_DCDCEN */ -#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_MASK 0x1UL /**< Bit mask for PFMXPPRF_DCDCEN */ -#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ -#define PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ -#define PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS (0x1UL << 1) /**< TX MAX Status */ -#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_SHIFT 1 /**< Shift value for PFMXPPRF_TXMAXSTATUS */ -#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_MASK 0x2UL /**< Bit mask for PFMXPPRF_TXMAXSTATUS */ -#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ -#define PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ -#define PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS (0x1UL << 2) /**< RX PP Status */ -#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_SHIFT 2 /**< Shift value for PFMXPPRF_RXPPSTATUS */ -#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_MASK 0x4UL /**< Bit mask for PFMXPPRF_RXPPSTATUS */ -#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ -#define PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ -#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_SHIFT 8 /**< Shift value for PFMXPPRF_WNO1 */ -#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_MASK 0x1FF00UL /**< Bit mask for PFMXPPRF_WNO1 */ -#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ -#define PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT << 8) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ +#define _PFMXPPRF_RFIMDCDCSTATUS_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RFIMDCDCSTATUS */ +#define _PFMXPPRF_RFIMDCDCSTATUS_MASK 0x0001FF07UL /**< Mask for PFMXPPRF_RFIMDCDCSTATUS */ +#define PFMXPPRF_RFIMDCDCSTATUS_DCDCEN (0x1UL << 0) /**< DCDC Enable Status */ +#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_SHIFT 0 /**< Shift value for PFMXPPRF_DCDCEN */ +#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_MASK 0x1UL /**< Bit mask for PFMXPPRF_DCDCEN */ +#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ +#define PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ +#define PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS (0x1UL << 1) /**< TX MAX Status */ +#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_SHIFT 1 /**< Shift value for PFMXPPRF_TXMAXSTATUS */ +#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_MASK 0x2UL /**< Bit mask for PFMXPPRF_TXMAXSTATUS */ +#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ +#define PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ +#define PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS (0x1UL << 2) /**< RX PP Status */ +#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_SHIFT 2 /**< Shift value for PFMXPPRF_RXPPSTATUS */ +#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_MASK 0x4UL /**< Bit mask for PFMXPPRF_RXPPSTATUS */ +#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ +#define PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ +#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_SHIFT 8 /**< Shift value for PFMXPPRF_WNO1 */ +#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_MASK 0x1FF00UL /**< Bit mask for PFMXPPRF_WNO1 */ +#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ +#define PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT << 8) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ /* Bit fields for PFMXPPRF RPURATD0 */ -#define _PFMXPPRF_RPURATD0_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RPURATD0 */ -#define _PFMXPPRF_RPURATD0_MASK 0x00000007UL /**< Mask for PFMXPPRF_RPURATD0 */ -#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0 (0x1UL << 0) /**< RFIMDCDCCTRL0 Protection Bit */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_SHIFT 0 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL0 */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_MASK 0x1UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL0 */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ -#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ -#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1 (0x1UL << 1) /**< RFIMDCDCCTRL1 Protection Bit */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_SHIFT 1 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL1 */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_MASK 0x2UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL1 */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ -#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ -#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2 (0x1UL << 2) /**< RFIMDCDCCTRL2 Protection Bit */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_SHIFT 2 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL2 */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_MASK 0x4UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL2 */ -#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ -#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ +#define _PFMXPPRF_RPURATD0_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RPURATD0 */ +#define _PFMXPPRF_RPURATD0_MASK 0x00000007UL /**< Mask for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0 (0x1UL << 0) /**< RFIMDCDCCTRL0 Protection Bit */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_SHIFT 0 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL0 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_MASK 0x1UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL0 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1 (0x1UL << 1) /**< RFIMDCDCCTRL1 Protection Bit */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_SHIFT 1 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL1 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_MASK 0x2UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL1 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2 (0x1UL << 2) /**< RFIMDCDCCTRL2 Protection Bit */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_SHIFT 2 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL2 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_MASK 0x4UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL2 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ /** @} End of group EFR32SG28_PFMXPPRF_BitFields */ /** @} End of group EFR32SG28_PFMXPPRF */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_prs.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_prs.h index 1b303f6151..715c98d5e6 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_prs.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_prs.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_PRS_H #define EFR32SG28_PRS_H - #define PRS_HAS_SET_CLEAR /**************************************************************************//** @@ -43,433 +42,428 @@ *****************************************************************************/ /** PRS ASYNC_CH Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t CTRL; /**< Async Channel Control Register */ +typedef struct { + __IOM uint32_t CTRL; /**< Async Channel Control Register */ } PRS_ASYNC_CH_TypeDef; - /** PRS SYNC_CH Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t CTRL; /**< Sync Channel Control Register */ +typedef struct { + __IOM uint32_t CTRL; /**< Sync Channel Control Register */ } PRS_SYNC_CH_TypeDef; - /** PRS Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< PRS IPVERSION */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t ASYNC_SWPULSE; /**< Software Pulse Register */ - __IOM uint32_t ASYNC_SWLEVEL; /**< Software Level Register */ - __IM uint32_t ASYNC_PEEK; /**< Async Channel Values */ - __IM uint32_t SYNC_PEEK; /**< Sync Channel Values */ - PRS_ASYNC_CH_TypeDef ASYNC_CH[12U]; /**< Async Channel registers */ - PRS_SYNC_CH_TypeDef SYNC_CH[4U]; /**< Sync Channel registers */ - __IOM uint32_t CONSUMER_CMU_CALDN; /**< CALDN consumer register */ - __IOM uint32_t CONSUMER_CMU_CALUP; /**< CALUP Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_CLK; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART0_RX; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_TRIGGER;/**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_CLK; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART1_RX; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_TRIGGER;/**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART2_CLK; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART2_RX; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART2_TRIGGER;/**< TRIGGER Consumer register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER;/**< SCAN consumer register */ - __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER;/**< SINGLE Consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0;/**< DMAREQ0 consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1;/**< DMAREQ1 Consumer register */ - uint32_t RESERVED2[4U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_LESENSE_START; /**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_CLEAR;/**< CLEAR consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_START;/**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_STOP; /**< STOP Consumer register */ - __IOM uint32_t CONSUMER_MODEM_DIN; /**< MODEM DIN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S0IN; /**< S0IN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S1IN; /**< S1IN Consumer register */ - uint32_t RESERVED3[11U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_RAC_CLR; /**< CLR consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN0; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN1; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN2; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN3; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_FORCETX; /**< FORCETX Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXDIS; /**< RXDIS Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXEN; /**< RXEN Consumer register */ - __IOM uint32_t CONSUMER_RAC_TXEN; /**< TXEN Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25;/**< TAMPERSRC25 consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26;/**< TAMPERSRC26 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27;/**< TAMPERSRC27 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28;/**< TAMPERSRC28 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29;/**< TAMPERSRC29 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30;/**< TAMPERSRC30 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31;/**< TAMPERSRC31 Consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN0; /**< IN0 consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN1; /**< IN1 Consumer register */ - __IOM uint32_t CONSUMER_HFXO0_OSCREQ; /**< OSCREQ consumer register */ - __IOM uint32_t CONSUMER_HFXO0_TIMEOUT; /**< TIMEOUT Consumer register */ - __IOM uint32_t CONSUMER_CORE_CTIIN0; /**< CTI0 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN1; /**< CTI1 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN2; /**< CTI2 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN3; /**< CTI3 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_M33RXEV; /**< M33 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC0; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC1; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC2; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTI; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS1; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS2; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC0; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC1; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC2; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTI; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS1; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS2; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC0; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC1; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC2; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTI; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS1; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS2; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC0; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC1; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC2; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTI; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS1; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS2; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC0; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC1; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC2; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTI; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS1; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS2; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_USART0_CLK; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_USART0_IR; /**< IR Consumer register */ - __IOM uint32_t CONSUMER_USART0_RX; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_USART0_TRIGGER;/**< TRIGGER Consumer register */ - uint32_t RESERVED4[3U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0;/**< ASYNCTRIG consumer register */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1;/**< ASYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0;/**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1;/**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC0; /**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC1; /**< SRC1 Consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC0; /**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC1; /**< SRC1 Consumer register */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - uint32_t RESERVED6[893U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< PRS IPVERSION */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - __IOM uint32_t ASYNC_SWPULSE_SET; /**< Software Pulse Register */ - __IOM uint32_t ASYNC_SWLEVEL_SET; /**< Software Level Register */ - __IM uint32_t ASYNC_PEEK_SET; /**< Async Channel Values */ - __IM uint32_t SYNC_PEEK_SET; /**< Sync Channel Values */ - PRS_ASYNC_CH_TypeDef ASYNC_CH_SET[12U]; /**< Async Channel registers */ - PRS_SYNC_CH_TypeDef SYNC_CH_SET[4U]; /**< Sync Channel registers */ - __IOM uint32_t CONSUMER_CMU_CALDN_SET; /**< CALDN consumer register */ - __IOM uint32_t CONSUMER_CMU_CALUP_SET; /**< CALUP Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_CLK_SET;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART0_RX_SET;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_TRIGGER_SET;/**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_CLK_SET;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART1_RX_SET;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_TRIGGER_SET;/**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART2_CLK_SET;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART2_RX_SET;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART2_TRIGGER_SET;/**< TRIGGER Consumer register */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_SET;/**< SCAN consumer register */ - __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_SET;/**< SINGLE Consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_SET;/**< DMAREQ0 consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_SET;/**< DMAREQ1 Consumer register */ - uint32_t RESERVED9[4U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_LESENSE_START_SET;/**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_CLEAR_SET;/**< CLEAR consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_START_SET;/**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_STOP_SET;/**< STOP Consumer register */ - __IOM uint32_t CONSUMER_MODEM_DIN_SET; /**< MODEM DIN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S0IN_SET;/**< S0IN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S1IN_SET;/**< S1IN Consumer register */ - uint32_t RESERVED10[11U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_RAC_CLR_SET; /**< CLR consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN0_SET;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN1_SET;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN2_SET;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN3_SET;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_FORCETX_SET;/**< FORCETX Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXDIS_SET; /**< RXDIS Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXEN_SET; /**< RXEN Consumer register */ - __IOM uint32_t CONSUMER_RAC_TXEN_SET; /**< TXEN Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_SET;/**< TAMPERSRC25 consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_SET;/**< TAMPERSRC26 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_SET;/**< TAMPERSRC27 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_SET;/**< TAMPERSRC28 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_SET;/**< TAMPERSRC29 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_SET;/**< TAMPERSRC30 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_SET;/**< TAMPERSRC31 Consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN0_SET;/**< IN0 consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN1_SET;/**< IN1 Consumer register */ - __IOM uint32_t CONSUMER_HFXO0_OSCREQ_SET;/**< OSCREQ consumer register */ - __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_SET;/**< TIMEOUT Consumer register */ - __IOM uint32_t CONSUMER_CORE_CTIIN0_SET;/**< CTI0 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN1_SET;/**< CTI1 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN2_SET;/**< CTI2 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN3_SET;/**< CTI3 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_M33RXEV_SET;/**< M33 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC0_SET;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC1_SET;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC2_SET;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTI_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS1_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS2_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC0_SET;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC1_SET;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC2_SET;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTI_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS1_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS2_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC0_SET;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC1_SET;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC2_SET;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTI_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS1_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS2_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC0_SET;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC1_SET;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC2_SET;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTI_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS1_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS2_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC0_SET;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC1_SET;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC2_SET;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTI_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS1_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS2_SET;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_USART0_CLK_SET;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_USART0_IR_SET; /**< IR Consumer register */ - __IOM uint32_t CONSUMER_USART0_RX_SET; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_USART0_TRIGGER_SET;/**< TRIGGER Consumer register */ - uint32_t RESERVED11[3U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_SET;/**< ASYNCTRIG consumer register */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_SET;/**< ASYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_SET;/**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_SET;/**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC0_SET;/**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC1_SET;/**< SRC1 Consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC0_SET;/**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC1_SET;/**< SRC1 Consumer register */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - uint32_t RESERVED13[893U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< PRS IPVERSION */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - __IOM uint32_t ASYNC_SWPULSE_CLR; /**< Software Pulse Register */ - __IOM uint32_t ASYNC_SWLEVEL_CLR; /**< Software Level Register */ - __IM uint32_t ASYNC_PEEK_CLR; /**< Async Channel Values */ - __IM uint32_t SYNC_PEEK_CLR; /**< Sync Channel Values */ - PRS_ASYNC_CH_TypeDef ASYNC_CH_CLR[12U]; /**< Async Channel registers */ - PRS_SYNC_CH_TypeDef SYNC_CH_CLR[4U]; /**< Sync Channel registers */ - __IOM uint32_t CONSUMER_CMU_CALDN_CLR; /**< CALDN consumer register */ - __IOM uint32_t CONSUMER_CMU_CALUP_CLR; /**< CALUP Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_CLK_CLR;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART0_RX_CLR;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_TRIGGER_CLR;/**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_CLK_CLR;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART1_RX_CLR;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_TRIGGER_CLR;/**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART2_CLK_CLR;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART2_RX_CLR;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART2_TRIGGER_CLR;/**< TRIGGER Consumer register */ - uint32_t RESERVED15[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_CLR;/**< SCAN consumer register */ - __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_CLR;/**< SINGLE Consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_CLR;/**< DMAREQ0 consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_CLR;/**< DMAREQ1 Consumer register */ - uint32_t RESERVED16[4U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_LESENSE_START_CLR;/**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_CLEAR_CLR;/**< CLEAR consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_START_CLR;/**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_STOP_CLR;/**< STOP Consumer register */ - __IOM uint32_t CONSUMER_MODEM_DIN_CLR; /**< MODEM DIN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S0IN_CLR;/**< S0IN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S1IN_CLR;/**< S1IN Consumer register */ - uint32_t RESERVED17[11U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_RAC_CLR_CLR; /**< CLR consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN0_CLR;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN1_CLR;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN2_CLR;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN3_CLR;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_FORCETX_CLR;/**< FORCETX Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXDIS_CLR; /**< RXDIS Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXEN_CLR; /**< RXEN Consumer register */ - __IOM uint32_t CONSUMER_RAC_TXEN_CLR; /**< TXEN Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_CLR;/**< TAMPERSRC25 consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_CLR;/**< TAMPERSRC26 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_CLR;/**< TAMPERSRC27 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_CLR;/**< TAMPERSRC28 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_CLR;/**< TAMPERSRC29 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_CLR;/**< TAMPERSRC30 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_CLR;/**< TAMPERSRC31 Consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN0_CLR;/**< IN0 consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN1_CLR;/**< IN1 Consumer register */ - __IOM uint32_t CONSUMER_HFXO0_OSCREQ_CLR;/**< OSCREQ consumer register */ - __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_CLR;/**< TIMEOUT Consumer register */ - __IOM uint32_t CONSUMER_CORE_CTIIN0_CLR;/**< CTI0 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN1_CLR;/**< CTI1 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN2_CLR;/**< CTI2 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN3_CLR;/**< CTI3 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_M33RXEV_CLR;/**< M33 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC0_CLR;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC1_CLR;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC2_CLR;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTI_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS1_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS2_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC0_CLR;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC1_CLR;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC2_CLR;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTI_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS1_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS2_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC0_CLR;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC1_CLR;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC2_CLR;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTI_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS1_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS2_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC0_CLR;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC1_CLR;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC2_CLR;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTI_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS1_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS2_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC0_CLR;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC1_CLR;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC2_CLR;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTI_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS1_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS2_CLR;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_USART0_CLK_CLR;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_USART0_IR_CLR; /**< IR Consumer register */ - __IOM uint32_t CONSUMER_USART0_RX_CLR; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_USART0_TRIGGER_CLR;/**< TRIGGER Consumer register */ - uint32_t RESERVED18[3U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_CLR;/**< ASYNCTRIG consumer register */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_CLR;/**< ASYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_CLR;/**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_CLR;/**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC0_CLR;/**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC1_CLR;/**< SRC1 Consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC0_CLR;/**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC1_CLR;/**< SRC1 Consumer register */ - uint32_t RESERVED19[1U]; /**< Reserved for future use */ - uint32_t RESERVED20[893U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< PRS IPVERSION */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - __IOM uint32_t ASYNC_SWPULSE_TGL; /**< Software Pulse Register */ - __IOM uint32_t ASYNC_SWLEVEL_TGL; /**< Software Level Register */ - __IM uint32_t ASYNC_PEEK_TGL; /**< Async Channel Values */ - __IM uint32_t SYNC_PEEK_TGL; /**< Sync Channel Values */ - PRS_ASYNC_CH_TypeDef ASYNC_CH_TGL[12U]; /**< Async Channel registers */ - PRS_SYNC_CH_TypeDef SYNC_CH_TGL[4U]; /**< Sync Channel registers */ - __IOM uint32_t CONSUMER_CMU_CALDN_TGL; /**< CALDN consumer register */ - __IOM uint32_t CONSUMER_CMU_CALUP_TGL; /**< CALUP Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_CLK_TGL;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART0_RX_TGL;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_TRIGGER_TGL;/**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_CLK_TGL;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART1_RX_TGL;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_TRIGGER_TGL;/**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART2_CLK_TGL;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART2_RX_TGL;/**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART2_TRIGGER_TGL;/**< TRIGGER Consumer register */ - uint32_t RESERVED22[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_TGL;/**< SCAN consumer register */ - __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_TGL;/**< SINGLE Consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_TGL;/**< DMAREQ0 consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_TGL;/**< DMAREQ1 Consumer register */ - uint32_t RESERVED23[4U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_LESENSE_START_TGL;/**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_CLEAR_TGL;/**< CLEAR consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_START_TGL;/**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_STOP_TGL;/**< STOP Consumer register */ - __IOM uint32_t CONSUMER_MODEM_DIN_TGL; /**< MODEM DIN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S0IN_TGL;/**< S0IN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S1IN_TGL;/**< S1IN Consumer register */ - uint32_t RESERVED24[11U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_RAC_CLR_TGL; /**< CLR consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN0_TGL;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN1_TGL;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN2_TGL;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN3_TGL;/**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_FORCETX_TGL;/**< FORCETX Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXDIS_TGL; /**< RXDIS Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXEN_TGL; /**< RXEN Consumer register */ - __IOM uint32_t CONSUMER_RAC_TXEN_TGL; /**< TXEN Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_TGL;/**< TAMPERSRC25 consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_TGL;/**< TAMPERSRC26 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_TGL;/**< TAMPERSRC27 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_TGL;/**< TAMPERSRC28 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_TGL;/**< TAMPERSRC29 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_TGL;/**< TAMPERSRC30 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_TGL;/**< TAMPERSRC31 Consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN0_TGL;/**< IN0 consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN1_TGL;/**< IN1 Consumer register */ - __IOM uint32_t CONSUMER_HFXO0_OSCREQ_TGL;/**< OSCREQ consumer register */ - __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_TGL;/**< TIMEOUT Consumer register */ - __IOM uint32_t CONSUMER_CORE_CTIIN0_TGL;/**< CTI0 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN1_TGL;/**< CTI1 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN2_TGL;/**< CTI2 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN3_TGL;/**< CTI3 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_M33RXEV_TGL;/**< M33 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC0_TGL;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC1_TGL;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC2_TGL;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTI_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS1_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS2_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC0_TGL;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC1_TGL;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC2_TGL;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTI_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS1_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS2_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC0_TGL;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC1_TGL;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC2_TGL;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTI_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS1_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS2_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC0_TGL;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC1_TGL;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC2_TGL;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTI_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS1_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS2_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC0_TGL;/**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC1_TGL;/**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC2_TGL;/**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTI_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS1_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS2_TGL;/**< DTI Consumer register */ - __IOM uint32_t CONSUMER_USART0_CLK_TGL;/**< CLK consumer register */ - __IOM uint32_t CONSUMER_USART0_IR_TGL; /**< IR Consumer register */ - __IOM uint32_t CONSUMER_USART0_RX_TGL; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_USART0_TRIGGER_TGL;/**< TRIGGER Consumer register */ - uint32_t RESERVED25[3U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_TGL;/**< ASYNCTRIG consumer register */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_TGL;/**< ASYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_TGL;/**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_TGL;/**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC0_TGL;/**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC1_TGL;/**< SRC1 Consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC0_TGL;/**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC1_TGL;/**< SRC1 Consumer register */ - uint32_t RESERVED26[1U]; /**< Reserved for future use */ +typedef struct { + __IM uint32_t IPVERSION; /**< PRS IPVERSION */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART2_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1; /**< DMAREQ1 Consumer register */ + uint32_t RESERVED2[4U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_LESENSE_START; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN; /**< MODEM DIN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN; /**< S1IN Consumer register */ + uint32_t RESERVED3[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1; /**< SRC1 Consumer register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + uint32_t RESERVED6[893U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< PRS IPVERSION */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_SET; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_SET; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_SET; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_SET; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_SET[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_SET[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_SET; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_SET; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_SET; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_SET; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART2_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_SET; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_SET; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_SET; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_SET; /**< DMAREQ1 Consumer register */ + uint32_t RESERVED9[4U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_LESENSE_START_SET; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_SET; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_SET; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_SET; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_SET; /**< MODEM DIN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_SET; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_SET; /**< S1IN Consumer register */ + uint32_t RESERVED10[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_SET; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_SET; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_SET; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_SET; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_SET; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_SET; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_SET; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_SET; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_SET; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_SET; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_SET; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_SET; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_SET; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_SET; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_SET; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_SET; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_SET; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_SET; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_SET; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_SET; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_SET; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_SET; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_SET; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_SET; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_SET; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_SET; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_SET; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_SET; /**< SRC1 Consumer register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[893U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< PRS IPVERSION */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_CLR; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_CLR; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_CLR; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_CLR; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_CLR[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_CLR[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_CLR; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_CLR; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_CLR; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART2_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_CLR; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_CLR; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_CLR; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_CLR; /**< DMAREQ1 Consumer register */ + uint32_t RESERVED16[4U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_LESENSE_START_CLR; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_CLR; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_CLR; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_CLR; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_CLR; /**< MODEM DIN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_CLR; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_CLR; /**< S1IN Consumer register */ + uint32_t RESERVED17[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_CLR; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_CLR; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_CLR; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_CLR; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_CLR; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_CLR; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_CLR; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_CLR; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_CLR; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_CLR; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_CLR; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_CLR; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_CLR; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_CLR; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_CLR; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_CLR; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_CLR; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_CLR; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_CLR; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_CLR; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_CLR; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_CLR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_CLR; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_CLR; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_CLR; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_CLR; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_CLR; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_CLR; /**< SRC1 Consumer register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + uint32_t RESERVED20[893U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< PRS IPVERSION */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_TGL; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_TGL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_TGL; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_TGL; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_TGL[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_TGL[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_TGL; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_TGL; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_TGL; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART2_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_TGL; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_TGL; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_TGL; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_TGL; /**< DMAREQ1 Consumer register */ + uint32_t RESERVED23[4U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_LESENSE_START_TGL; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_TGL; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_TGL; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_TGL; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_TGL; /**< MODEM DIN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_TGL; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_TGL; /**< S1IN Consumer register */ + uint32_t RESERVED24[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_TGL; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_TGL; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_TGL; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_TGL; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_TGL; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_TGL; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_TGL; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_TGL; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_TGL; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_TGL; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_TGL; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_TGL; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_TGL; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_TGL; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_TGL; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_TGL; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_TGL; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_TGL; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_TGL; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_TGL; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_TGL; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_TGL; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_TGL; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_TGL; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_TGL; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_TGL; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_TGL; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_TGL; /**< SRC1 Consumer register */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ } PRS_TypeDef; /** @} End of group EFR32SG28_PRS */ @@ -481,1076 +475,1076 @@ typedef struct *****************************************************************************/ /* Bit fields for PRS IPVERSION */ -#define _PRS_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for PRS_IPVERSION */ -#define _PRS_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PRS_IPVERSION */ -#define _PRS_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PRS_IPVERSION */ -#define _PRS_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PRS_IPVERSION */ -#define _PRS_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for PRS_IPVERSION */ -#define PRS_IPVERSION_IPVERSION_DEFAULT (_PRS_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_IPVERSION */ +#define _PRS_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for PRS_IPVERSION */ +#define _PRS_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for PRS_IPVERSION */ +#define PRS_IPVERSION_IPVERSION_DEFAULT (_PRS_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_IPVERSION */ /* Bit fields for PRS ASYNC_SWPULSE */ -#define _PRS_ASYNC_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWPULSE */ -#define _PRS_ASYNC_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ -#define _PRS_ASYNC_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ -#define _PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ -#define _PRS_ASYNC_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ -#define _PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ -#define _PRS_ASYNC_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ -#define _PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ -#define _PRS_ASYNC_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ -#define _PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ -#define _PRS_ASYNC_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ -#define _PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ -#define _PRS_ASYNC_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ -#define _PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ -#define _PRS_ASYNC_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ -#define _PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ -#define _PRS_ASYNC_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ -#define _PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ -#define _PRS_ASYNC_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ -#define _PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ -#define _PRS_ASYNC_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ -#define _PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ -#define _PRS_ASYNC_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ -#define _PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ -#define _PRS_ASYNC_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ -#define _PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ /* Bit fields for PRS ASYNC_SWLEVEL */ -#define _PRS_ASYNC_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWLEVEL */ -#define _PRS_ASYNC_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ /* Bit fields for PRS ASYNC_PEEK */ -#define _PRS_ASYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_PEEK */ -#define _PRS_ASYNC_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ -#define _PRS_ASYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ -#define _PRS_ASYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ -#define _PRS_ASYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH0VAL_DEFAULT (_PRS_ASYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ -#define _PRS_ASYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ -#define _PRS_ASYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ -#define _PRS_ASYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH1VAL_DEFAULT (_PRS_ASYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ -#define _PRS_ASYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ -#define _PRS_ASYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ -#define _PRS_ASYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH2VAL_DEFAULT (_PRS_ASYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ -#define _PRS_ASYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ -#define _PRS_ASYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ -#define _PRS_ASYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH3VAL_DEFAULT (_PRS_ASYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ -#define _PRS_ASYNC_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ -#define _PRS_ASYNC_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ -#define _PRS_ASYNC_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH4VAL_DEFAULT (_PRS_ASYNC_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ -#define _PRS_ASYNC_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ -#define _PRS_ASYNC_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ -#define _PRS_ASYNC_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH5VAL_DEFAULT (_PRS_ASYNC_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ -#define _PRS_ASYNC_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ -#define _PRS_ASYNC_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ -#define _PRS_ASYNC_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH6VAL_DEFAULT (_PRS_ASYNC_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ -#define _PRS_ASYNC_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ -#define _PRS_ASYNC_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ -#define _PRS_ASYNC_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH7VAL_DEFAULT (_PRS_ASYNC_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ -#define _PRS_ASYNC_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ -#define _PRS_ASYNC_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ -#define _PRS_ASYNC_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH8VAL_DEFAULT (_PRS_ASYNC_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ -#define _PRS_ASYNC_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ -#define _PRS_ASYNC_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ -#define _PRS_ASYNC_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH9VAL_DEFAULT (_PRS_ASYNC_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ -#define _PRS_ASYNC_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ -#define _PRS_ASYNC_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ -#define _PRS_ASYNC_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH10VAL_DEFAULT (_PRS_ASYNC_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ -#define _PRS_ASYNC_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ -#define _PRS_ASYNC_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ -#define _PRS_ASYNC_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH11VAL_DEFAULT (_PRS_ASYNC_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_ASYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL_DEFAULT (_PRS_ASYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_ASYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL_DEFAULT (_PRS_ASYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_ASYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL_DEFAULT (_PRS_ASYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_ASYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL_DEFAULT (_PRS_ASYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_ASYNC_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL_DEFAULT (_PRS_ASYNC_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_ASYNC_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL_DEFAULT (_PRS_ASYNC_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_ASYNC_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL_DEFAULT (_PRS_ASYNC_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_ASYNC_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL_DEFAULT (_PRS_ASYNC_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_ASYNC_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL_DEFAULT (_PRS_ASYNC_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_ASYNC_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL_DEFAULT (_PRS_ASYNC_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_ASYNC_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL_DEFAULT (_PRS_ASYNC_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_ASYNC_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL_DEFAULT (_PRS_ASYNC_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ /* Bit fields for PRS SYNC_PEEK */ -#define _PRS_SYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_PEEK */ -#define _PRS_SYNC_PEEK_MASK 0x0000000FUL /**< Mask for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel Value */ -#define _PRS_SYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ -#define _PRS_SYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ -#define _PRS_SYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH0VAL_DEFAULT (_PRS_SYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel Value */ -#define _PRS_SYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ -#define _PRS_SYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ -#define _PRS_SYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH1VAL_DEFAULT (_PRS_SYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel Value */ -#define _PRS_SYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ -#define _PRS_SYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ -#define _PRS_SYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH2VAL_DEFAULT (_PRS_SYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel Value */ -#define _PRS_SYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ -#define _PRS_SYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ -#define _PRS_SYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH3VAL_DEFAULT (_PRS_SYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define _PRS_SYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_PEEK */ +#define _PRS_SYNC_PEEK_MASK 0x0000000FUL /**< Mask for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL_DEFAULT (_PRS_SYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL_DEFAULT (_PRS_SYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL_DEFAULT (_PRS_SYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL_DEFAULT (_PRS_SYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ /* Bit fields for PRS ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_RESETVALUE 0x000C0000UL /**< Default value for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_MASK 0x0F0F7F07UL /**< Mask for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_SIGSEL_NONE (_PRS_ASYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT 16 /**< Shift value for PRS_FNSEL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_MASK 0xF0000UL /**< Bit mask for PRS_FNSEL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO 0x00000000UL /**< Mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B 0x00000001UL /**< Mode A_NOR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B 0x00000002UL /**< Mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A 0x00000003UL /**< Mode NOT_A for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B 0x00000004UL /**< Mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B 0x00000005UL /**< Mode NOT_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B 0x00000006UL /**< Mode A_XOR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B 0x00000007UL /**< Mode A_NAND_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B 0x00000008UL /**< Mode A_AND_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B 0x00000009UL /**< Mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_B 0x0000000AUL /**< Mode B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B 0x0000000BUL /**< Mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A 0x0000000CUL /**< Mode A for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B 0x0000000DUL /**< Mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B 0x0000000EUL /**< Mode A_OR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE 0x0000000FUL /**< Mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO << 16) /**< Shifted mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B << 16) /**< Shifted mode A_NOR_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B << 16) /**< Shifted mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A << 16) /**< Shifted mode NOT_A for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B << 16) /**< Shifted mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_B << 16) /**< Shifted mode NOT_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B << 16) /**< Shifted mode A_XOR_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B << 16) /**< Shifted mode A_NAND_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B << 16) /**< Shifted mode A_AND_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B << 16) /**< Shifted mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_B (_PRS_ASYNC_CH_CTRL_FNSEL_B << 16) /**< Shifted mode B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B << 16) /**< Shifted mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_A (_PRS_ASYNC_CH_CTRL_FNSEL_A << 16) /**< Shifted mode A for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B << 16) /**< Shifted mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B << 16) /**< Shifted mode A_OR_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE << 16) /**< Shifted mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL*/ -#define _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT 24 /**< Shift value for PRS_AUXSEL */ -#define _PRS_ASYNC_CH_CTRL_AUXSEL_MASK 0xF000000UL /**< Bit mask for PRS_AUXSEL */ -#define _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_RESETVALUE 0x000C0000UL /**< Default value for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_MASK 0x0F0F7F07UL /**< Mask for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_NONE (_PRS_ASYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT 16 /**< Shift value for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_MASK 0xF0000UL /**< Bit mask for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO 0x00000000UL /**< Mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B 0x00000001UL /**< Mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B 0x00000002UL /**< Mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A 0x00000003UL /**< Mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B 0x00000004UL /**< Mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B 0x00000005UL /**< Mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B 0x00000006UL /**< Mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B 0x00000007UL /**< Mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B 0x00000008UL /**< Mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B 0x00000009UL /**< Mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_B 0x0000000AUL /**< Mode B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B 0x0000000BUL /**< Mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A 0x0000000CUL /**< Mode A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B 0x0000000DUL /**< Mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B 0x0000000EUL /**< Mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE 0x0000000FUL /**< Mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO << 16) /**< Shifted mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B << 16) /**< Shifted mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B << 16) /**< Shifted mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A << 16) /**< Shifted mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B << 16) /**< Shifted mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_B << 16) /**< Shifted mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B << 16) /**< Shifted mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B << 16) /**< Shifted mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B << 16) /**< Shifted mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B << 16) /**< Shifted mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_B (_PRS_ASYNC_CH_CTRL_FNSEL_B << 16) /**< Shifted mode B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B << 16) /**< Shifted mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A (_PRS_ASYNC_CH_CTRL_FNSEL_A << 16) /**< Shifted mode A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B << 16) /**< Shifted mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B << 16) /**< Shifted mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE << 16) /**< Shifted mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL*/ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT 24 /**< Shift value for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_MASK 0xF000000UL /**< Bit mask for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ /* Bit fields for PRS SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_MASK 0x00007F07UL /**< Mask for PRS_SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ -#define _PRS_SYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ -#define _PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_SYNC_CH_CTRL */ -#define PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ -#define PRS_SYNC_CH_CTRL_SIGSEL_NONE (_PRS_SYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ -#define _PRS_SYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ -#define _PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ -#define PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_MASK 0x00007F07UL /**< Mask for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SIGSEL_NONE (_PRS_SYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ /* Bit fields for PRS CONSUMER_CMU_CALDN */ -#define _PRS_CONSUMER_CMU_CALDN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALDN */ -#define _PRS_CONSUMER_CMU_CALDN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALDN */ -#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALDN */ -#define PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALDN*/ +#define _PRS_CONSUMER_CMU_CALDN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALDN */ +#define PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALDN*/ /* Bit fields for PRS CONSUMER_CMU_CALUP */ -#define _PRS_CONSUMER_CMU_CALUP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALUP */ -#define _PRS_CONSUMER_CMU_CALUP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALUP */ -#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALUP */ -#define PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALUP*/ +#define _PRS_CONSUMER_CMU_CALUP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALUP */ +#define PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALUP*/ /* Bit fields for PRS CONSUMER_EUSART0_CLK */ -#define _PRS_CONSUMER_EUSART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_CLK */ -#define _PRS_CONSUMER_EUSART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_CLK */ -#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_CLK */ -#define PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_CLK*/ +#define _PRS_CONSUMER_EUSART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_CLK */ +#define PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_CLK*/ /* Bit fields for PRS CONSUMER_EUSART0_RX */ -#define _PRS_CONSUMER_EUSART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_RX */ -#define _PRS_CONSUMER_EUSART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_RX */ -#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_RX */ -#define PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_RX*/ +#define _PRS_CONSUMER_EUSART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_RX */ +#define PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_RX*/ /* Bit fields for PRS CONSUMER_EUSART0_TRIGGER */ -#define _PRS_CONSUMER_EUSART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_TRIGGER*/ -#define _PRS_CONSUMER_EUSART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_TRIGGER */ -#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ -#define PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define _PRS_CONSUMER_EUSART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define _PRS_CONSUMER_EUSART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_TRIGGER */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ /* Bit fields for PRS CONSUMER_EUSART1_CLK */ -#define _PRS_CONSUMER_EUSART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_CLK */ -#define _PRS_CONSUMER_EUSART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_CLK */ -#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_CLK */ -#define PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_CLK*/ +#define _PRS_CONSUMER_EUSART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_CLK */ +#define PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_CLK*/ /* Bit fields for PRS CONSUMER_EUSART1_RX */ -#define _PRS_CONSUMER_EUSART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_RX */ -#define _PRS_CONSUMER_EUSART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_RX */ -#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_RX */ -#define PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_RX*/ +#define _PRS_CONSUMER_EUSART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_RX */ +#define PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_RX*/ /* Bit fields for PRS CONSUMER_EUSART1_TRIGGER */ -#define _PRS_CONSUMER_EUSART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_TRIGGER*/ -#define _PRS_CONSUMER_EUSART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_TRIGGER */ -#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ -#define PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define _PRS_CONSUMER_EUSART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define _PRS_CONSUMER_EUSART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_TRIGGER */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ /* Bit fields for PRS CONSUMER_EUSART2_CLK */ -#define _PRS_CONSUMER_EUSART2_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_CLK */ -#define _PRS_CONSUMER_EUSART2_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_CLK */ -#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_CLK */ -#define PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_CLK*/ +#define _PRS_CONSUMER_EUSART2_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_CLK */ +#define _PRS_CONSUMER_EUSART2_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_CLK */ +#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_CLK */ +#define PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_CLK*/ /* Bit fields for PRS CONSUMER_EUSART2_RX */ -#define _PRS_CONSUMER_EUSART2_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_RX */ -#define _PRS_CONSUMER_EUSART2_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_RX */ -#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_RX */ -#define PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_RX*/ +#define _PRS_CONSUMER_EUSART2_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_RX */ +#define _PRS_CONSUMER_EUSART2_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_RX */ +#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_RX */ +#define PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_RX*/ /* Bit fields for PRS CONSUMER_EUSART2_TRIGGER */ -#define _PRS_CONSUMER_EUSART2_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_TRIGGER*/ -#define _PRS_CONSUMER_EUSART2_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_TRIGGER */ -#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_TRIGGER*/ -#define PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_TRIGGER*/ +#define _PRS_CONSUMER_EUSART2_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_TRIGGER*/ +#define _PRS_CONSUMER_EUSART2_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_TRIGGER */ +#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_TRIGGER*/ +#define PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_TRIGGER*/ /* Bit fields for PRS CONSUMER_IADC0_SCANTRIGGER */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SCANTRIGGER*/ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SCANTRIGGER */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ -#define PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ -#define PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SCANTRIGGER */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ /* Bit fields for PRS CONSUMER_IADC0_SINGLETRIGGER */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SINGLETRIGGER */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ -#define PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ -#define PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SINGLETRIGGER */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ /* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ0 */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ0 */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ -#define PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ0 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ /* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ1 */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ1 */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ -#define PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ1 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ /* Bit fields for PRS CONSUMER_LESENSE_START */ -#define _PRS_CONSUMER_LESENSE_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LESENSE_START*/ -#define _PRS_CONSUMER_LESENSE_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LESENSE_START */ -#define _PRS_CONSUMER_LESENSE_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LESENSE_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LESENSE_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LESENSE_START */ -#define PRS_CONSUMER_LESENSE_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LESENSE_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LESENSE_START*/ +#define _PRS_CONSUMER_LESENSE_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LESENSE_START*/ +#define _PRS_CONSUMER_LESENSE_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LESENSE_START */ +#define _PRS_CONSUMER_LESENSE_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LESENSE_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LESENSE_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LESENSE_START */ +#define PRS_CONSUMER_LESENSE_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LESENSE_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LESENSE_START*/ /* Bit fields for PRS CONSUMER_LETIMER0_CLEAR */ -#define _PRS_CONSUMER_LETIMER0_CLEAR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_CLEAR*/ -#define _PRS_CONSUMER_LETIMER0_CLEAR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_CLEAR */ -#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ -#define PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define _PRS_CONSUMER_LETIMER0_CLEAR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define _PRS_CONSUMER_LETIMER0_CLEAR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_CLEAR */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ /* Bit fields for PRS CONSUMER_LETIMER0_START */ -#define _PRS_CONSUMER_LETIMER0_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_START*/ -#define _PRS_CONSUMER_LETIMER0_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_START */ -#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ -#define PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ +#define _PRS_CONSUMER_LETIMER0_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_START*/ +#define _PRS_CONSUMER_LETIMER0_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_START */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ +#define PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ /* Bit fields for PRS CONSUMER_LETIMER0_STOP */ -#define _PRS_CONSUMER_LETIMER0_STOP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_STOP*/ -#define _PRS_CONSUMER_LETIMER0_STOP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_STOP */ -#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP */ -#define PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP*/ +#define _PRS_CONSUMER_LETIMER0_STOP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_STOP*/ +#define _PRS_CONSUMER_LETIMER0_STOP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_STOP */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP */ +#define PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP*/ /* Bit fields for PRS CONSUMER_MODEM_DIN */ -#define _PRS_CONSUMER_MODEM_DIN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_DIN */ -#define _PRS_CONSUMER_MODEM_DIN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_DIN */ -#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_DIN */ -#define PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_DIN*/ +#define _PRS_CONSUMER_MODEM_DIN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_DIN */ +#define PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_DIN*/ /* Bit fields for PRS CONSUMER_PCNT0_S0IN */ -#define _PRS_CONSUMER_PCNT0_S0IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S0IN */ -#define _PRS_CONSUMER_PCNT0_S0IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S0IN */ -#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN */ -#define PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN*/ +#define _PRS_CONSUMER_PCNT0_S0IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S0IN */ +#define _PRS_CONSUMER_PCNT0_S0IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S0IN */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN */ +#define PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN*/ /* Bit fields for PRS CONSUMER_PCNT0_S1IN */ -#define _PRS_CONSUMER_PCNT0_S1IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S1IN */ -#define _PRS_CONSUMER_PCNT0_S1IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S1IN */ -#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN */ -#define PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN*/ +#define _PRS_CONSUMER_PCNT0_S1IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S1IN */ +#define _PRS_CONSUMER_PCNT0_S1IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S1IN */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN */ +#define PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN*/ /* Bit fields for PRS CONSUMER_RAC_CLR */ -#define _PRS_CONSUMER_RAC_CLR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CLR */ -#define _PRS_CONSUMER_RAC_CLR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CLR */ -#define _PRS_CONSUMER_RAC_CLR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CLR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CLR */ -#define PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CLR*/ +#define _PRS_CONSUMER_RAC_CLR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CLR */ +#define PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CLR*/ /* Bit fields for PRS CONSUMER_RAC_CTIIN0 */ -#define _PRS_CONSUMER_RAC_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN0 */ -#define _PRS_CONSUMER_RAC_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN0 */ -#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0 */ -#define PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0*/ +#define _PRS_CONSUMER_RAC_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0 */ +#define PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0*/ /* Bit fields for PRS CONSUMER_RAC_CTIIN1 */ -#define _PRS_CONSUMER_RAC_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN1 */ -#define _PRS_CONSUMER_RAC_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN1 */ -#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1 */ -#define PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1*/ +#define _PRS_CONSUMER_RAC_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1 */ +#define PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1*/ /* Bit fields for PRS CONSUMER_RAC_CTIIN2 */ -#define _PRS_CONSUMER_RAC_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN2 */ -#define _PRS_CONSUMER_RAC_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN2 */ -#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2 */ -#define PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2*/ +#define _PRS_CONSUMER_RAC_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2 */ +#define PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2*/ /* Bit fields for PRS CONSUMER_RAC_CTIIN3 */ -#define _PRS_CONSUMER_RAC_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN3 */ -#define _PRS_CONSUMER_RAC_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN3 */ -#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3 */ -#define PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3*/ +#define _PRS_CONSUMER_RAC_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3 */ +#define PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3*/ /* Bit fields for PRS CONSUMER_RAC_FORCETX */ -#define _PRS_CONSUMER_RAC_FORCETX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_FORCETX */ -#define _PRS_CONSUMER_RAC_FORCETX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_FORCETX */ -#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_FORCETX */ -#define PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_FORCETX*/ +#define _PRS_CONSUMER_RAC_FORCETX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_FORCETX */ +#define PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_FORCETX*/ /* Bit fields for PRS CONSUMER_RAC_RXDIS */ -#define _PRS_CONSUMER_RAC_RXDIS_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXDIS */ -#define _PRS_CONSUMER_RAC_RXDIS_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXDIS */ -#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXDIS */ -#define PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXDIS*/ +#define _PRS_CONSUMER_RAC_RXDIS_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXDIS */ +#define PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXDIS*/ /* Bit fields for PRS CONSUMER_RAC_RXEN */ -#define _PRS_CONSUMER_RAC_RXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXEN */ -#define _PRS_CONSUMER_RAC_RXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXEN */ -#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXEN */ -#define PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXEN*/ +#define _PRS_CONSUMER_RAC_RXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXEN */ +#define PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXEN*/ /* Bit fields for PRS CONSUMER_RAC_TXEN */ -#define _PRS_CONSUMER_RAC_TXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_TXEN */ -#define _PRS_CONSUMER_RAC_TXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_TXEN */ -#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_TXEN */ -#define PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_TXEN*/ +#define _PRS_CONSUMER_RAC_TXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_TXEN */ +#define PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_TXEN*/ /* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC25 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC25 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC25 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ /* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC26 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC26 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC26 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ /* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC27 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC27 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC27 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ /* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC28 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC28 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC28 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ /* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC29 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC29 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC29 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ /* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC30 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC30 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC30 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ /* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC31 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC31 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC31 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ /* Bit fields for PRS CONSUMER_SYSRTC0_IN0 */ -#define _PRS_CONSUMER_SYSRTC0_IN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN0 */ -#define _PRS_CONSUMER_SYSRTC0_IN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN0 */ -#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0 */ -#define PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0*/ +#define _PRS_CONSUMER_SYSRTC0_IN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN0 */ +#define _PRS_CONSUMER_SYSRTC0_IN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN0 */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0 */ +#define PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0*/ /* Bit fields for PRS CONSUMER_SYSRTC0_IN1 */ -#define _PRS_CONSUMER_SYSRTC0_IN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN1 */ -#define _PRS_CONSUMER_SYSRTC0_IN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN1 */ -#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1 */ -#define PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1*/ +#define _PRS_CONSUMER_SYSRTC0_IN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN1 */ +#define _PRS_CONSUMER_SYSRTC0_IN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN1 */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1 */ +#define PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1*/ /* Bit fields for PRS CONSUMER_HFXO0_OSCREQ */ -#define _PRS_CONSUMER_HFXO0_OSCREQ_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_OSCREQ */ -#define _PRS_CONSUMER_HFXO0_OSCREQ_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_OSCREQ */ -#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ */ -#define PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ*/ +#define _PRS_CONSUMER_HFXO0_OSCREQ_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_OSCREQ */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_OSCREQ */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ */ +#define PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ*/ /* Bit fields for PRS CONSUMER_HFXO0_TIMEOUT */ -#define _PRS_CONSUMER_HFXO0_TIMEOUT_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_TIMEOUT*/ -#define _PRS_CONSUMER_HFXO0_TIMEOUT_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_TIMEOUT */ -#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT */ -#define PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT*/ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_TIMEOUT*/ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_TIMEOUT */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT */ +#define PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT*/ /* Bit fields for PRS CONSUMER_CORE_CTIIN0 */ -#define _PRS_CONSUMER_CORE_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN0 */ -#define _PRS_CONSUMER_CORE_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN0 */ -#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0 */ -#define PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0*/ +#define _PRS_CONSUMER_CORE_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0 */ +#define PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0*/ /* Bit fields for PRS CONSUMER_CORE_CTIIN1 */ -#define _PRS_CONSUMER_CORE_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN1 */ -#define _PRS_CONSUMER_CORE_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN1 */ -#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1 */ -#define PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1*/ +#define _PRS_CONSUMER_CORE_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1 */ +#define PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1*/ /* Bit fields for PRS CONSUMER_CORE_CTIIN2 */ -#define _PRS_CONSUMER_CORE_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN2 */ -#define _PRS_CONSUMER_CORE_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN2 */ -#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2 */ -#define PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2*/ +#define _PRS_CONSUMER_CORE_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2 */ +#define PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2*/ /* Bit fields for PRS CONSUMER_CORE_CTIIN3 */ -#define _PRS_CONSUMER_CORE_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN3 */ -#define _PRS_CONSUMER_CORE_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN3 */ -#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3 */ -#define PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3*/ +#define _PRS_CONSUMER_CORE_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3 */ +#define PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3*/ /* Bit fields for PRS CONSUMER_CORE_M33RXEV */ -#define _PRS_CONSUMER_CORE_M33RXEV_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_M33RXEV */ -#define _PRS_CONSUMER_CORE_M33RXEV_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_M33RXEV */ -#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV */ -#define PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV*/ +#define _PRS_CONSUMER_CORE_M33RXEV_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV */ +#define PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV*/ /* Bit fields for PRS CONSUMER_TIMER0_CC0 */ -#define _PRS_CONSUMER_TIMER0_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC0 */ -#define _PRS_CONSUMER_TIMER0_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC0 */ -#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ -#define PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ -#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ -#define PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ +#define _PRS_CONSUMER_TIMER0_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ /* Bit fields for PRS CONSUMER_TIMER0_CC1 */ -#define _PRS_CONSUMER_TIMER0_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC1 */ -#define _PRS_CONSUMER_TIMER0_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC1 */ -#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ -#define PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ -#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ -#define PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ +#define _PRS_CONSUMER_TIMER0_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ /* Bit fields for PRS CONSUMER_TIMER0_CC2 */ -#define _PRS_CONSUMER_TIMER0_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC2 */ -#define _PRS_CONSUMER_TIMER0_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC2 */ -#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ -#define PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ -#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ -#define PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ +#define _PRS_CONSUMER_TIMER0_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ /* Bit fields for PRS CONSUMER_TIMER0_DTI */ -#define _PRS_CONSUMER_TIMER0_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTI */ -#define _PRS_CONSUMER_TIMER0_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTI */ -#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTI */ -#define PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTI*/ +#define _PRS_CONSUMER_TIMER0_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTI */ +#define PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTI*/ /* Bit fields for PRS CONSUMER_TIMER0_DTIFS1 */ -#define _PRS_CONSUMER_TIMER0_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS1*/ -#define _PRS_CONSUMER_TIMER0_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS1 */ -#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1 */ -#define PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1*/ +#define _PRS_CONSUMER_TIMER0_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS1*/ +#define _PRS_CONSUMER_TIMER0_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1*/ /* Bit fields for PRS CONSUMER_TIMER0_DTIFS2 */ -#define _PRS_CONSUMER_TIMER0_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS2*/ -#define _PRS_CONSUMER_TIMER0_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS2 */ -#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2 */ -#define PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2*/ +#define _PRS_CONSUMER_TIMER0_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS2*/ +#define _PRS_CONSUMER_TIMER0_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2*/ /* Bit fields for PRS CONSUMER_TIMER1_CC0 */ -#define _PRS_CONSUMER_TIMER1_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC0 */ -#define _PRS_CONSUMER_TIMER1_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC0 */ -#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ -#define PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ -#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ -#define PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ +#define _PRS_CONSUMER_TIMER1_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ /* Bit fields for PRS CONSUMER_TIMER1_CC1 */ -#define _PRS_CONSUMER_TIMER1_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC1 */ -#define _PRS_CONSUMER_TIMER1_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC1 */ -#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ -#define PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ -#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ -#define PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ +#define _PRS_CONSUMER_TIMER1_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ /* Bit fields for PRS CONSUMER_TIMER1_CC2 */ -#define _PRS_CONSUMER_TIMER1_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC2 */ -#define _PRS_CONSUMER_TIMER1_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC2 */ -#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ -#define PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ -#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ -#define PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ +#define _PRS_CONSUMER_TIMER1_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ /* Bit fields for PRS CONSUMER_TIMER1_DTI */ -#define _PRS_CONSUMER_TIMER1_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTI */ -#define _PRS_CONSUMER_TIMER1_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTI */ -#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTI */ -#define PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTI*/ +#define _PRS_CONSUMER_TIMER1_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTI */ +#define PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTI*/ /* Bit fields for PRS CONSUMER_TIMER1_DTIFS1 */ -#define _PRS_CONSUMER_TIMER1_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS1*/ -#define _PRS_CONSUMER_TIMER1_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS1 */ -#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1 */ -#define PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1*/ +#define _PRS_CONSUMER_TIMER1_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS1*/ +#define _PRS_CONSUMER_TIMER1_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1*/ /* Bit fields for PRS CONSUMER_TIMER1_DTIFS2 */ -#define _PRS_CONSUMER_TIMER1_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS2*/ -#define _PRS_CONSUMER_TIMER1_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS2 */ -#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2 */ -#define PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2*/ +#define _PRS_CONSUMER_TIMER1_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS2*/ +#define _PRS_CONSUMER_TIMER1_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2*/ /* Bit fields for PRS CONSUMER_TIMER2_CC0 */ -#define _PRS_CONSUMER_TIMER2_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC0 */ -#define _PRS_CONSUMER_TIMER2_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC0 */ -#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ -#define PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ -#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ -#define PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ +#define _PRS_CONSUMER_TIMER2_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ /* Bit fields for PRS CONSUMER_TIMER2_CC1 */ -#define _PRS_CONSUMER_TIMER2_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC1 */ -#define _PRS_CONSUMER_TIMER2_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC1 */ -#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ -#define PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ -#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ -#define PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ +#define _PRS_CONSUMER_TIMER2_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ /* Bit fields for PRS CONSUMER_TIMER2_CC2 */ -#define _PRS_CONSUMER_TIMER2_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC2 */ -#define _PRS_CONSUMER_TIMER2_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC2 */ -#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ -#define PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ -#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ -#define PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ +#define _PRS_CONSUMER_TIMER2_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ /* Bit fields for PRS CONSUMER_TIMER2_DTI */ -#define _PRS_CONSUMER_TIMER2_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTI */ -#define _PRS_CONSUMER_TIMER2_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTI */ -#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTI */ -#define PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTI*/ +#define _PRS_CONSUMER_TIMER2_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTI */ +#define PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTI*/ /* Bit fields for PRS CONSUMER_TIMER2_DTIFS1 */ -#define _PRS_CONSUMER_TIMER2_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS1*/ -#define _PRS_CONSUMER_TIMER2_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS1 */ -#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1 */ -#define PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1*/ +#define _PRS_CONSUMER_TIMER2_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS1*/ +#define _PRS_CONSUMER_TIMER2_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1*/ /* Bit fields for PRS CONSUMER_TIMER2_DTIFS2 */ -#define _PRS_CONSUMER_TIMER2_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS2*/ -#define _PRS_CONSUMER_TIMER2_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS2 */ -#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2 */ -#define PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2*/ +#define _PRS_CONSUMER_TIMER2_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS2*/ +#define _PRS_CONSUMER_TIMER2_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2*/ /* Bit fields for PRS CONSUMER_TIMER3_CC0 */ -#define _PRS_CONSUMER_TIMER3_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC0 */ -#define _PRS_CONSUMER_TIMER3_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC0 */ -#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ -#define PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ -#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ -#define PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ +#define _PRS_CONSUMER_TIMER3_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ /* Bit fields for PRS CONSUMER_TIMER3_CC1 */ -#define _PRS_CONSUMER_TIMER3_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC1 */ -#define _PRS_CONSUMER_TIMER3_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC1 */ -#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ -#define PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ -#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ -#define PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ +#define _PRS_CONSUMER_TIMER3_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ /* Bit fields for PRS CONSUMER_TIMER3_CC2 */ -#define _PRS_CONSUMER_TIMER3_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC2 */ -#define _PRS_CONSUMER_TIMER3_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC2 */ -#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ -#define PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ -#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ -#define PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ +#define _PRS_CONSUMER_TIMER3_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ /* Bit fields for PRS CONSUMER_TIMER3_DTI */ -#define _PRS_CONSUMER_TIMER3_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTI */ -#define _PRS_CONSUMER_TIMER3_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTI */ -#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTI */ -#define PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTI*/ +#define _PRS_CONSUMER_TIMER3_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTI */ +#define PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTI*/ /* Bit fields for PRS CONSUMER_TIMER3_DTIFS1 */ -#define _PRS_CONSUMER_TIMER3_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS1*/ -#define _PRS_CONSUMER_TIMER3_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS1 */ -#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1 */ -#define PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1*/ +#define _PRS_CONSUMER_TIMER3_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS1*/ +#define _PRS_CONSUMER_TIMER3_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1*/ /* Bit fields for PRS CONSUMER_TIMER3_DTIFS2 */ -#define _PRS_CONSUMER_TIMER3_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS2*/ -#define _PRS_CONSUMER_TIMER3_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS2 */ -#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2 */ -#define PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2*/ +#define _PRS_CONSUMER_TIMER3_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS2*/ +#define _PRS_CONSUMER_TIMER3_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2*/ /* Bit fields for PRS CONSUMER_TIMER4_CC0 */ -#define _PRS_CONSUMER_TIMER4_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC0 */ -#define _PRS_CONSUMER_TIMER4_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC0 */ -#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ -#define PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ -#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ -#define PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ +#define _PRS_CONSUMER_TIMER4_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ /* Bit fields for PRS CONSUMER_TIMER4_CC1 */ -#define _PRS_CONSUMER_TIMER4_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC1 */ -#define _PRS_CONSUMER_TIMER4_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC1 */ -#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ -#define PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ -#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ -#define PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ +#define _PRS_CONSUMER_TIMER4_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ /* Bit fields for PRS CONSUMER_TIMER4_CC2 */ -#define _PRS_CONSUMER_TIMER4_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC2 */ -#define _PRS_CONSUMER_TIMER4_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC2 */ -#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ -#define PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ -#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ -#define PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ +#define _PRS_CONSUMER_TIMER4_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ /* Bit fields for PRS CONSUMER_TIMER4_DTI */ -#define _PRS_CONSUMER_TIMER4_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTI */ -#define _PRS_CONSUMER_TIMER4_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTI */ -#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTI */ -#define PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTI*/ +#define _PRS_CONSUMER_TIMER4_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTI */ +#define PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTI*/ /* Bit fields for PRS CONSUMER_TIMER4_DTIFS1 */ -#define _PRS_CONSUMER_TIMER4_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS1*/ -#define _PRS_CONSUMER_TIMER4_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS1 */ -#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1 */ -#define PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1*/ +#define _PRS_CONSUMER_TIMER4_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS1*/ +#define _PRS_CONSUMER_TIMER4_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1*/ /* Bit fields for PRS CONSUMER_TIMER4_DTIFS2 */ -#define _PRS_CONSUMER_TIMER4_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS2*/ -#define _PRS_CONSUMER_TIMER4_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS2 */ -#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2 */ -#define PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2*/ +#define _PRS_CONSUMER_TIMER4_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS2*/ +#define _PRS_CONSUMER_TIMER4_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2*/ /* Bit fields for PRS CONSUMER_USART0_CLK */ -#define _PRS_CONSUMER_USART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_CLK */ -#define _PRS_CONSUMER_USART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_CLK */ -#define _PRS_CONSUMER_USART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_CLK */ -#define PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_CLK*/ +#define _PRS_CONSUMER_USART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_CLK */ +#define PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_CLK*/ /* Bit fields for PRS CONSUMER_USART0_IR */ -#define _PRS_CONSUMER_USART0_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_IR */ -#define _PRS_CONSUMER_USART0_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_IR */ -#define _PRS_CONSUMER_USART0_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_IR */ -#define PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_IR*/ +#define _PRS_CONSUMER_USART0_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_IR */ +#define PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_IR*/ /* Bit fields for PRS CONSUMER_USART0_RX */ -#define _PRS_CONSUMER_USART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_RX */ -#define _PRS_CONSUMER_USART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_RX */ -#define _PRS_CONSUMER_USART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_RX */ -#define PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_RX*/ +#define _PRS_CONSUMER_USART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_RX */ +#define PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_RX*/ /* Bit fields for PRS CONSUMER_USART0_TRIGGER */ -#define _PRS_CONSUMER_USART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_TRIGGER*/ -#define _PRS_CONSUMER_USART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_TRIGGER */ -#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ -#define PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ +#define _PRS_CONSUMER_USART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_TRIGGER*/ +#define _PRS_CONSUMER_USART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_TRIGGER */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ +#define PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ /* Bit fields for PRS CONSUMER_VDAC0_ASYNCTRIGCH0 */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0 */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ -#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ /* Bit fields for PRS CONSUMER_VDAC0_ASYNCTRIGCH1 */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1 */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ -#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ /* Bit fields for PRS CONSUMER_VDAC0_SYNCTRIGCH0 */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH0 */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ -#define PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ /* Bit fields for PRS CONSUMER_VDAC0_SYNCTRIGCH1 */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH1 */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ -#define PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ /* Bit fields for PRS CONSUMER_WDOG0_SRC0 */ -#define _PRS_CONSUMER_WDOG0_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC0 */ -#define _PRS_CONSUMER_WDOG0_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC0 */ -#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0 */ -#define PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0*/ +#define _PRS_CONSUMER_WDOG0_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0 */ +#define PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0*/ /* Bit fields for PRS CONSUMER_WDOG0_SRC1 */ -#define _PRS_CONSUMER_WDOG0_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC1 */ -#define _PRS_CONSUMER_WDOG0_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC1 */ -#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1 */ -#define PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1*/ +#define _PRS_CONSUMER_WDOG0_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1 */ +#define PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1*/ /* Bit fields for PRS CONSUMER_WDOG1_SRC0 */ -#define _PRS_CONSUMER_WDOG1_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC0 */ -#define _PRS_CONSUMER_WDOG1_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC0 */ -#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0 */ -#define PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0*/ +#define _PRS_CONSUMER_WDOG1_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC0 */ +#define _PRS_CONSUMER_WDOG1_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC0 */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0 */ +#define PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0*/ /* Bit fields for PRS CONSUMER_WDOG1_SRC1 */ -#define _PRS_CONSUMER_WDOG1_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC1 */ -#define _PRS_CONSUMER_WDOG1_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC1 */ -#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1 */ -#define PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1*/ +#define _PRS_CONSUMER_WDOG1_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC1 */ +#define _PRS_CONSUMER_WDOG1_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC1 */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1 */ +#define PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1*/ /** @} End of group EFR32SG28_PRS_BitFields */ /** @} End of group EFR32SG28_PRS */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_prs_signals.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_prs_signals.h index 996b65f69d..39a5569b24 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_scratchpad.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_scratchpad.h index 893a804d45..386b2b4743 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_scratchpad.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_SCRATCHPAD_H #define EFR32SG28_SCRATCHPAD_H - #define SCRATCHPAD_HAS_SET_CLEAR /**************************************************************************//** @@ -43,19 +42,18 @@ *****************************************************************************/ /** SCRATCHPAD Register Declaration. */ -typedef struct -{ - __IOM uint32_t SREG0; /**< Scratchpad Register 0 */ - __IOM uint32_t SREG1; /**< Scratchpad Register 1 */ - uint32_t RESERVED0[1022U]; /**< Reserved for future use */ - __IOM uint32_t SREG0_SET; /**< Scratchpad Register 0 */ - __IOM uint32_t SREG1_SET; /**< Scratchpad Register 1 */ - uint32_t RESERVED1[1022U]; /**< Reserved for future use */ - __IOM uint32_t SREG0_CLR; /**< Scratchpad Register 0 */ - __IOM uint32_t SREG1_CLR; /**< Scratchpad Register 1 */ - uint32_t RESERVED2[1022U]; /**< Reserved for future use */ - __IOM uint32_t SREG0_TGL; /**< Scratchpad Register 0 */ - __IOM uint32_t SREG1_TGL; /**< Scratchpad Register 1 */ +typedef struct { + __IOM uint32_t SREG0; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1; /**< Scratchpad Register 1 */ + uint32_t RESERVED0[1022U]; /**< Reserved for future use */ + __IOM uint32_t SREG0_SET; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1_SET; /**< Scratchpad Register 1 */ + uint32_t RESERVED1[1022U]; /**< Reserved for future use */ + __IOM uint32_t SREG0_CLR; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1_CLR; /**< Scratchpad Register 1 */ + uint32_t RESERVED2[1022U]; /**< Reserved for future use */ + __IOM uint32_t SREG0_TGL; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1_TGL; /**< Scratchpad Register 1 */ } SCRATCHPAD_TypeDef; /** @} End of group EFR32SG28_SCRATCHPAD */ @@ -67,20 +65,20 @@ typedef struct *****************************************************************************/ /* Bit fields for SCRATCHPAD SREG0 */ -#define _SCRATCHPAD_SREG0_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG0 */ -#define _SCRATCHPAD_SREG0_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG0 */ -#define _SCRATCHPAD_SREG0_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */ -#define _SCRATCHPAD_SREG0_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */ -#define _SCRATCHPAD_SREG0_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG0 */ -#define SCRATCHPAD_SREG0_SCRATCH_DEFAULT (_SCRATCHPAD_SREG0_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG0 */ +#define _SCRATCHPAD_SREG0_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG0 */ +#define _SCRATCHPAD_SREG0_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG0 */ +#define _SCRATCHPAD_SREG0_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG0_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG0_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG0 */ +#define SCRATCHPAD_SREG0_SCRATCH_DEFAULT (_SCRATCHPAD_SREG0_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG0 */ /* Bit fields for SCRATCHPAD SREG1 */ -#define _SCRATCHPAD_SREG1_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG1 */ -#define _SCRATCHPAD_SREG1_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG1 */ -#define _SCRATCHPAD_SREG1_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */ -#define _SCRATCHPAD_SREG1_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */ -#define _SCRATCHPAD_SREG1_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG1 */ -#define SCRATCHPAD_SREG1_SCRATCH_DEFAULT (_SCRATCHPAD_SREG1_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG1 */ +#define _SCRATCHPAD_SREG1_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG1 */ +#define _SCRATCHPAD_SREG1_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG1 */ +#define _SCRATCHPAD_SREG1_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG1_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG1_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG1 */ +#define SCRATCHPAD_SREG1_SCRATCH_DEFAULT (_SCRATCHPAD_SREG1_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG1 */ /** @} End of group EFR32SG28_SCRATCHPAD_BitFields */ /** @} End of group EFR32SG28_SCRATCHPAD */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_semailbox.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_semailbox.h index d618bbad2a..956ca2a808 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_semailbox.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -41,17 +41,16 @@ *****************************************************************************/ /** SEMAILBOX_HOST Register Declaration. */ -typedef struct -{ - __IOM uint32_t FIFO; /**< ESECURE_MAILBOX_FIFO */ - uint32_t RESERVED0[15U]; /**< Reserved for future use */ - __IM uint32_t TX_STATUS; /**< ESECURE_MAILBOX_TXSTAT */ - __IM uint32_t RX_STATUS; /**< ESECURE_MAILBOX_RXSTAT */ - __IM uint32_t TX_PROT; /**< ESECURE_MAILBOX_TXPROTECT */ - __IM uint32_t RX_PROT; /**< ESECURE_MAILBOX_RXPROTECT */ - __IOM uint32_t TX_HEADER; /**< ESECURE_MAILBOX_TXHEADER */ - __IM uint32_t RX_HEADER; /**< ESECURE_MAILBOX_RXHEADER */ - __IOM uint32_t CONFIGURATION; /**< ESECURE_MAILBOX_CONFIG */ +typedef struct { + __IOM uint32_t FIFO; /**< ESECURE_MAILBOX_FIFO */ + uint32_t RESERVED0[15U]; /**< Reserved for future use */ + __IM uint32_t TX_STATUS; /**< ESECURE_MAILBOX_TXSTAT */ + __IM uint32_t RX_STATUS; /**< ESECURE_MAILBOX_RXSTAT */ + __IM uint32_t TX_PROT; /**< ESECURE_MAILBOX_TXPROTECT */ + __IM uint32_t RX_PROT; /**< ESECURE_MAILBOX_RXPROTECT */ + __IOM uint32_t TX_HEADER; /**< ESECURE_MAILBOX_TXHEADER */ + __IM uint32_t RX_HEADER; /**< ESECURE_MAILBOX_RXHEADER */ + __IOM uint32_t CONFIGURATION; /**< ESECURE_MAILBOX_CONFIG */ } SEMAILBOX_HOST_TypeDef; /** @} End of group EFR32SG28_SEMAILBOX_HOST */ @@ -63,147 +62,147 @@ typedef struct *****************************************************************************/ /* Bit fields for SEMAILBOX FIFO */ -#define _SEMAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_FIFO */ -#define _SEMAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_FIFO */ -#define _SEMAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ -#define _SEMAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ -#define _SEMAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_FIFO */ -#define SEMAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_FIFO */ +#define SEMAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_FIFO */ /* Bit fields for SEMAILBOX TX_STATUS */ -#define _SEMAILBOX_TX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_STATUS */ -#define _SEMAILBOX_TX_STATUS_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_TX_STATUS */ -#define _SEMAILBOX_TX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_TX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ -#define SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ -#define _SEMAILBOX_TX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_TX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ -#define SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ -#define SEMAILBOX_TX_STATUS_TXINT (0x1UL << 20) /**< TXINT */ -#define _SEMAILBOX_TX_STATUS_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ -#define _SEMAILBOX_TX_STATUS_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ -#define _SEMAILBOX_TX_STATUS_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ -#define SEMAILBOX_TX_STATUS_TXINT_DEFAULT (_SEMAILBOX_TX_STATUS_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ -#define SEMAILBOX_TX_STATUS_TXFULL (0x1UL << 21) /**< TXFULL */ -#define _SEMAILBOX_TX_STATUS_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ -#define _SEMAILBOX_TX_STATUS_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ -#define _SEMAILBOX_TX_STATUS_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ -#define SEMAILBOX_TX_STATUS_TXFULL_DEFAULT (_SEMAILBOX_TX_STATUS_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ -#define SEMAILBOX_TX_STATUS_TXERROR (0x1UL << 23) /**< TXERROR */ -#define _SEMAILBOX_TX_STATUS_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ -#define _SEMAILBOX_TX_STATUS_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ -#define _SEMAILBOX_TX_STATUS_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ -#define SEMAILBOX_TX_STATUS_TXERROR_DEFAULT (_SEMAILBOX_TX_STATUS_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define _SEMAILBOX_TX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define _SEMAILBOX_TX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_TX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXINT (0x1UL << 20) /**< TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXINT_DEFAULT (_SEMAILBOX_TX_STATUS_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXFULL (0x1UL << 21) /**< TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXFULL_DEFAULT (_SEMAILBOX_TX_STATUS_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXERROR (0x1UL << 23) /**< TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXERROR_DEFAULT (_SEMAILBOX_TX_STATUS_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ /* Bit fields for SEMAILBOX RX_STATUS */ -#define _SEMAILBOX_RX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_STATUS */ -#define _SEMAILBOX_RX_STATUS_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_RX_STATUS */ -#define _SEMAILBOX_RX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_RX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ -#define _SEMAILBOX_RX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_RX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ -#define SEMAILBOX_RX_STATUS_RXINT (0x1UL << 20) /**< RXINT */ -#define _SEMAILBOX_RX_STATUS_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ -#define _SEMAILBOX_RX_STATUS_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ -#define _SEMAILBOX_RX_STATUS_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_RXINT_DEFAULT (_SEMAILBOX_RX_STATUS_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ -#define SEMAILBOX_RX_STATUS_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ -#define _SEMAILBOX_RX_STATUS_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ -#define _SEMAILBOX_RX_STATUS_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ -#define _SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT (_SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ -#define SEMAILBOX_RX_STATUS_RXHDR (0x1UL << 22) /**< RXHDR */ -#define _SEMAILBOX_RX_STATUS_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ -#define _SEMAILBOX_RX_STATUS_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ -#define _SEMAILBOX_RX_STATUS_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_RXHDR_DEFAULT (_SEMAILBOX_RX_STATUS_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ -#define SEMAILBOX_RX_STATUS_RXERROR (0x1UL << 23) /**< RXERROR */ -#define _SEMAILBOX_RX_STATUS_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ -#define _SEMAILBOX_RX_STATUS_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ -#define _SEMAILBOX_RX_STATUS_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_RXERROR_DEFAULT (_SEMAILBOX_RX_STATUS_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define _SEMAILBOX_RX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define _SEMAILBOX_RX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_RX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXINT (0x1UL << 20) /**< RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXINT_DEFAULT (_SEMAILBOX_RX_STATUS_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT (_SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXHDR (0x1UL << 22) /**< RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXHDR_DEFAULT (_SEMAILBOX_RX_STATUS_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXERROR (0x1UL << 23) /**< RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXERROR_DEFAULT (_SEMAILBOX_RX_STATUS_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ /* Bit fields for SEMAILBOX TX_PROT */ -#define _SEMAILBOX_TX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_PROT */ -#define _SEMAILBOX_TX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ -#define _SEMAILBOX_TX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_TX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ -#define _SEMAILBOX_TX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_TX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ -#define _SEMAILBOX_TX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_TX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_TX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_TX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ -#define _SEMAILBOX_TX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ -#define _SEMAILBOX_TX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ -#define _SEMAILBOX_TX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_USER_DEFAULT (_SEMAILBOX_TX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_TX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_TX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_TX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_USER_DEFAULT (_SEMAILBOX_TX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ /* Bit fields for SEMAILBOX RX_PROT */ -#define _SEMAILBOX_RX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_PROT */ -#define _SEMAILBOX_RX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ -#define _SEMAILBOX_RX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_RX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ -#define _SEMAILBOX_RX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_RX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ -#define _SEMAILBOX_RX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_RX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_RX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_RX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ -#define _SEMAILBOX_RX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ -#define _SEMAILBOX_RX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ -#define _SEMAILBOX_RX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_USER_DEFAULT (_SEMAILBOX_RX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_RX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_RX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_RX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_USER_DEFAULT (_SEMAILBOX_RX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ /* Bit fields for SEMAILBOX TX_HEADER */ -#define _SEMAILBOX_TX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_HEADER */ -#define _SEMAILBOX_TX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_TX_HEADER */ -#define _SEMAILBOX_TX_HEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ -#define _SEMAILBOX_TX_HEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ -#define _SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_HEADER */ -#define SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT (_SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_HEADER*/ +#define _SEMAILBOX_TX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_HEADER */ +#define SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT (_SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_HEADER*/ /* Bit fields for SEMAILBOX RX_HEADER */ -#define _SEMAILBOX_RX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_HEADER */ -#define _SEMAILBOX_RX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_RX_HEADER */ -#define _SEMAILBOX_RX_HEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ -#define _SEMAILBOX_RX_HEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ -#define _SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_HEADER */ -#define SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT (_SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_HEADER*/ +#define _SEMAILBOX_RX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_HEADER */ +#define SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT (_SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_HEADER*/ /* Bit fields for SEMAILBOX CONFIGURATION */ -#define _SEMAILBOX_CONFIGURATION_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_CONFIGURATION */ -#define _SEMAILBOX_CONFIGURATION_MASK 0x00000003UL /**< Mask for SEMAILBOX_CONFIGURATION */ -#define SEMAILBOX_CONFIGURATION_TXINTEN (0x1UL << 0) /**< TXINTEN */ -#define _SEMAILBOX_CONFIGURATION_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ -#define _SEMAILBOX_CONFIGURATION_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ -#define _SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ -#define SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ -#define SEMAILBOX_CONFIGURATION_RXINTEN (0x1UL << 1) /**< RXINTEN */ -#define _SEMAILBOX_CONFIGURATION_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ -#define _SEMAILBOX_CONFIGURATION_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ -#define _SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ -#define SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ +#define _SEMAILBOX_CONFIGURATION_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_CONFIGURATION */ +#define _SEMAILBOX_CONFIGURATION_MASK 0x00000003UL /**< Mask for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_TXINTEN (0x1UL << 0) /**< TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ +#define SEMAILBOX_CONFIGURATION_RXINTEN (0x1UL << 1) /**< RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ /** @} End of group EFR32SG28_SEMAILBOX_HOST_BitFields */ /** @} End of group EFR32SG28_SEMAILBOX_HOST */ @@ -214,17 +213,16 @@ typedef struct *****************************************************************************/ /** SEMAILBOX_APBSE Register Declaration. */ -typedef struct -{ - __IOM uint32_t SE_ESECURE_MAILBOX_FIFO;/**< ESECURE_MAILBOX_FIFO */ - uint32_t RESERVED0[15U]; /**< Reserved for future use */ - __IM uint32_t SE_ESECURE_MAILBOX_TXSTAT;/**< ESECURE_MAILBOX_TXSTAT */ - __IM uint32_t SE_ESECURE_MAILBOX_RXSTAT;/**< ESECURE_MAILBOX_RXSTAT */ - __IM uint32_t SE_ESECURE_MAILBOX_TXPROTECT;/**< ESECURE_MAILBOX_TXPROTECT */ - __IM uint32_t SE_ESECURE_MAILBOX_RXPROTECT;/**< ESECURE_MAILBOX_RXPROTECT */ - __IOM uint32_t SE_ESECURE_MAILBOX_TXHEADER;/**< ESECURE_MAILBOX_TXHEADER */ - __IM uint32_t SE_ESECURE_MAILBOX_RXHEADER;/**< ESECURE_MAILBOX_RXHEADER */ - __IOM uint32_t SE_ESECURE_MAILBOX_CONFIG;/**< ESECURE_MAILBOX_CONFIG */ +typedef struct { + __IOM uint32_t SE_ESECURE_MAILBOX_FIFO; /**< ESECURE_MAILBOX_FIFO */ + uint32_t RESERVED0[15U]; /**< Reserved for future use */ + __IM uint32_t SE_ESECURE_MAILBOX_TXSTAT; /**< ESECURE_MAILBOX_TXSTAT */ + __IM uint32_t SE_ESECURE_MAILBOX_RXSTAT; /**< ESECURE_MAILBOX_RXSTAT */ + __IM uint32_t SE_ESECURE_MAILBOX_TXPROTECT; /**< ESECURE_MAILBOX_TXPROTECT */ + __IM uint32_t SE_ESECURE_MAILBOX_RXPROTECT; /**< ESECURE_MAILBOX_RXPROTECT */ + __IOM uint32_t SE_ESECURE_MAILBOX_TXHEADER; /**< ESECURE_MAILBOX_TXHEADER */ + __IM uint32_t SE_ESECURE_MAILBOX_RXHEADER; /**< ESECURE_MAILBOX_RXHEADER */ + __IOM uint32_t SE_ESECURE_MAILBOX_CONFIG; /**< ESECURE_MAILBOX_CONFIG */ } SEMAILBOX_APBSE_TypeDef; /** @} End of group EFR32SG28_SEMAILBOX_APBSE */ @@ -236,147 +234,147 @@ typedef struct *****************************************************************************/ /* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_FIFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ /* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXSTAT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT (0x1UL << 20) /**< TXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL (0x1UL << 21) /**< TXFULL */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR (0x1UL << 23) /**< TXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT (0x1UL << 20) /**< TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL (0x1UL << 21) /**< TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR (0x1UL << 23) /**< TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ /* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXSTAT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT (0x1UL << 20) /**< RXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR (0x1UL << 22) /**< RXHDR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR (0x1UL << 23) /**< RXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT (0x1UL << 20) /**< RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR (0x1UL << 22) /**< RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR (0x1UL << 23) /**< RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ /* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXPROTECT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ /* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXPROTECT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ /* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ /* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ /* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_CONFIG */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_MASK 0x00000003UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN (0x1UL << 0) /**< TXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN (0x1UL << 1) /**< RXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_MASK 0x00000003UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN (0x1UL << 0) /**< TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN (0x1UL << 1) /**< RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ /** @} End of group EFR32SG28_SEMAILBOX_APBSE_BitFields */ /** @} End of group EFR32SG28_SEMAILBOX_APBSE */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_smu.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_smu.h index 1fac4cafb0..26ed8b3a8f 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_smu.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_smu.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_SMU_H #define EFR32SG28_SMU_H - #define SMU_HAS_SET_CLEAR /**************************************************************************//** @@ -43,135 +42,134 @@ *****************************************************************************/ /** SMU Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP Version */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t LOCK; /**< Lock Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - __IOM uint32_t M33CTRL; /**< M33 Control Settings */ - uint32_t RESERVED1[7U]; /**< Reserved for future use */ - __IOM uint32_t PPUPATD0; /**< Privileged Access */ - __IOM uint32_t PPUPATD1; /**< Privileged Access */ - uint32_t RESERVED2[6U]; /**< Reserved for future use */ - __IOM uint32_t PPUSATD0; /**< Secure Access */ - __IOM uint32_t PPUSATD1; /**< Secure Access */ - uint32_t RESERVED3[54U]; /**< Reserved for future use */ - __IM uint32_t PPUFS; /**< Fault Status */ - uint32_t RESERVED4[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUPATD0; /**< Privileged Attribute */ - uint32_t RESERVED5[7U]; /**< Reserved for future use */ - __IOM uint32_t BMPUSATD0; /**< Secure Attribute */ - uint32_t RESERVED6[55U]; /**< Reserved for future use */ - __IM uint32_t BMPUFS; /**< Fault Status */ - __IM uint32_t BMPUFSADDR; /**< Fault Status Address */ - uint32_t RESERVED7[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAURTYPES0; /**< Region Types 0 */ - __IOM uint32_t ESAURTYPES1; /**< Region Types 1 */ - uint32_t RESERVED8[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB01; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB12; /**< Movable Region Boundary */ - uint32_t RESERVED9[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB45; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB56; /**< Movable Region Boundary */ - uint32_t RESERVED10[862U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t LOCK_SET; /**< Lock Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED11[3U]; /**< Reserved for future use */ - __IOM uint32_t M33CTRL_SET; /**< M33 Control Settings */ - uint32_t RESERVED12[7U]; /**< Reserved for future use */ - __IOM uint32_t PPUPATD0_SET; /**< Privileged Access */ - __IOM uint32_t PPUPATD1_SET; /**< Privileged Access */ - uint32_t RESERVED13[6U]; /**< Reserved for future use */ - __IOM uint32_t PPUSATD0_SET; /**< Secure Access */ - __IOM uint32_t PPUSATD1_SET; /**< Secure Access */ - uint32_t RESERVED14[54U]; /**< Reserved for future use */ - __IM uint32_t PPUFS_SET; /**< Fault Status */ - uint32_t RESERVED15[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUPATD0_SET; /**< Privileged Attribute */ - uint32_t RESERVED16[7U]; /**< Reserved for future use */ - __IOM uint32_t BMPUSATD0_SET; /**< Secure Attribute */ - uint32_t RESERVED17[55U]; /**< Reserved for future use */ - __IM uint32_t BMPUFS_SET; /**< Fault Status */ - __IM uint32_t BMPUFSADDR_SET; /**< Fault Status Address */ - uint32_t RESERVED18[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAURTYPES0_SET; /**< Region Types 0 */ - __IOM uint32_t ESAURTYPES1_SET; /**< Region Types 1 */ - uint32_t RESERVED19[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB01_SET; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB12_SET; /**< Movable Region Boundary */ - uint32_t RESERVED20[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB45_SET; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB56_SET; /**< Movable Region Boundary */ - uint32_t RESERVED21[862U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t LOCK_CLR; /**< Lock Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED22[3U]; /**< Reserved for future use */ - __IOM uint32_t M33CTRL_CLR; /**< M33 Control Settings */ - uint32_t RESERVED23[7U]; /**< Reserved for future use */ - __IOM uint32_t PPUPATD0_CLR; /**< Privileged Access */ - __IOM uint32_t PPUPATD1_CLR; /**< Privileged Access */ - uint32_t RESERVED24[6U]; /**< Reserved for future use */ - __IOM uint32_t PPUSATD0_CLR; /**< Secure Access */ - __IOM uint32_t PPUSATD1_CLR; /**< Secure Access */ - uint32_t RESERVED25[54U]; /**< Reserved for future use */ - __IM uint32_t PPUFS_CLR; /**< Fault Status */ - uint32_t RESERVED26[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUPATD0_CLR; /**< Privileged Attribute */ - uint32_t RESERVED27[7U]; /**< Reserved for future use */ - __IOM uint32_t BMPUSATD0_CLR; /**< Secure Attribute */ - uint32_t RESERVED28[55U]; /**< Reserved for future use */ - __IM uint32_t BMPUFS_CLR; /**< Fault Status */ - __IM uint32_t BMPUFSADDR_CLR; /**< Fault Status Address */ - uint32_t RESERVED29[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAURTYPES0_CLR; /**< Region Types 0 */ - __IOM uint32_t ESAURTYPES1_CLR; /**< Region Types 1 */ - uint32_t RESERVED30[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB01_CLR; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB12_CLR; /**< Movable Region Boundary */ - uint32_t RESERVED31[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB45_CLR; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB56_CLR; /**< Movable Region Boundary */ - uint32_t RESERVED32[862U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t LOCK_TGL; /**< Lock Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED33[3U]; /**< Reserved for future use */ - __IOM uint32_t M33CTRL_TGL; /**< M33 Control Settings */ - uint32_t RESERVED34[7U]; /**< Reserved for future use */ - __IOM uint32_t PPUPATD0_TGL; /**< Privileged Access */ - __IOM uint32_t PPUPATD1_TGL; /**< Privileged Access */ - uint32_t RESERVED35[6U]; /**< Reserved for future use */ - __IOM uint32_t PPUSATD0_TGL; /**< Secure Access */ - __IOM uint32_t PPUSATD1_TGL; /**< Secure Access */ - uint32_t RESERVED36[54U]; /**< Reserved for future use */ - __IM uint32_t PPUFS_TGL; /**< Fault Status */ - uint32_t RESERVED37[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUPATD0_TGL; /**< Privileged Attribute */ - uint32_t RESERVED38[7U]; /**< Reserved for future use */ - __IOM uint32_t BMPUSATD0_TGL; /**< Secure Attribute */ - uint32_t RESERVED39[55U]; /**< Reserved for future use */ - __IM uint32_t BMPUFS_TGL; /**< Fault Status */ - __IM uint32_t BMPUFSADDR_TGL; /**< Fault Status Address */ - uint32_t RESERVED40[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAURTYPES0_TGL; /**< Region Types 0 */ - __IOM uint32_t ESAURTYPES1_TGL; /**< Region Types 1 */ - uint32_t RESERVED41[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB01_TGL; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB12_TGL; /**< Movable Region Boundary */ - uint32_t RESERVED42[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB45_TGL; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB56_TGL; /**< Movable Region Boundary */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL; /**< M33 Control Settings */ + uint32_t RESERVED1[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0; /**< Privileged Access */ + __IOM uint32_t PPUPATD1; /**< Privileged Access */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0; /**< Secure Access */ + __IOM uint32_t PPUSATD1; /**< Secure Access */ + uint32_t RESERVED3[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS; /**< Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0; /**< Privileged Attribute */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0; /**< Secure Attribute */ + uint32_t RESERVED6[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS; /**< Fault Status */ + __IM uint32_t BMPUFSADDR; /**< Fault Status Address */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1; /**< Region Types 1 */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12; /**< Movable Region Boundary */ + uint32_t RESERVED9[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56; /**< Movable Region Boundary */ + uint32_t RESERVED10[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_SET; /**< M33 Control Settings */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_SET; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_SET; /**< Privileged Access */ + uint32_t RESERVED13[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_SET; /**< Secure Access */ + __IOM uint32_t PPUSATD1_SET; /**< Secure Access */ + uint32_t RESERVED14[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_SET; /**< Fault Status */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_SET; /**< Privileged Attribute */ + uint32_t RESERVED16[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_SET; /**< Secure Attribute */ + uint32_t RESERVED17[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_SET; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_SET; /**< Fault Status Address */ + uint32_t RESERVED18[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_SET; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_SET; /**< Region Types 1 */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_SET; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_SET; /**< Movable Region Boundary */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_SET; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_SET; /**< Movable Region Boundary */ + uint32_t RESERVED21[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_CLR; /**< M33 Control Settings */ + uint32_t RESERVED23[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_CLR; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_CLR; /**< Privileged Access */ + uint32_t RESERVED24[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_CLR; /**< Secure Access */ + __IOM uint32_t PPUSATD1_CLR; /**< Secure Access */ + uint32_t RESERVED25[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_CLR; /**< Fault Status */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_CLR; /**< Privileged Attribute */ + uint32_t RESERVED27[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_CLR; /**< Secure Attribute */ + uint32_t RESERVED28[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_CLR; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_CLR; /**< Fault Status Address */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_CLR; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_CLR; /**< Region Types 1 */ + uint32_t RESERVED30[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_CLR; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_CLR; /**< Movable Region Boundary */ + uint32_t RESERVED31[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_CLR; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_CLR; /**< Movable Region Boundary */ + uint32_t RESERVED32[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_TGL; /**< M33 Control Settings */ + uint32_t RESERVED34[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_TGL; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_TGL; /**< Privileged Access */ + uint32_t RESERVED35[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_TGL; /**< Secure Access */ + __IOM uint32_t PPUSATD1_TGL; /**< Secure Access */ + uint32_t RESERVED36[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_TGL; /**< Fault Status */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_TGL; /**< Privileged Attribute */ + uint32_t RESERVED38[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_TGL; /**< Secure Attribute */ + uint32_t RESERVED39[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_TGL; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_TGL; /**< Fault Status Address */ + uint32_t RESERVED40[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_TGL; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_TGL; /**< Region Types 1 */ + uint32_t RESERVED41[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_TGL; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_TGL; /**< Movable Region Boundary */ + uint32_t RESERVED42[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_TGL; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_TGL; /**< Movable Region Boundary */ } SMU_TypeDef; /** @} End of group EFR32SG28_SMU */ @@ -183,825 +181,825 @@ typedef struct *****************************************************************************/ /* Bit fields for SMU IPVERSION */ -#define _SMU_IPVERSION_RESETVALUE 0x00000006UL /**< Default value for SMU_IPVERSION */ -#define _SMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SMU_IPVERSION */ -#define _SMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SMU_IPVERSION */ -#define _SMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_IPVERSION */ -#define _SMU_IPVERSION_IPVERSION_DEFAULT 0x00000006UL /**< Mode DEFAULT for SMU_IPVERSION */ -#define SMU_IPVERSION_IPVERSION_DEFAULT (_SMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IPVERSION */ +#define _SMU_IPVERSION_RESETVALUE 0x00000006UL /**< Default value for SMU_IPVERSION */ +#define _SMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_DEFAULT 0x00000006UL /**< Mode DEFAULT for SMU_IPVERSION */ +#define SMU_IPVERSION_IPVERSION_DEFAULT (_SMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IPVERSION */ /* Bit fields for SMU STATUS */ -#define _SMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_STATUS */ -#define _SMU_STATUS_MASK 0x00000003UL /**< Mask for SMU_STATUS */ -#define SMU_STATUS_SMULOCK (0x1UL << 0) /**< SMU Lock */ -#define _SMU_STATUS_SMULOCK_SHIFT 0 /**< Shift value for SMU_SMULOCK */ -#define _SMU_STATUS_SMULOCK_MASK 0x1UL /**< Bit mask for SMU_SMULOCK */ -#define _SMU_STATUS_SMULOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ -#define _SMU_STATUS_SMULOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_STATUS */ -#define _SMU_STATUS_SMULOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_STATUS */ -#define SMU_STATUS_SMULOCK_DEFAULT (_SMU_STATUS_SMULOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_STATUS */ -#define SMU_STATUS_SMULOCK_UNLOCKED (_SMU_STATUS_SMULOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_STATUS */ -#define SMU_STATUS_SMULOCK_LOCKED (_SMU_STATUS_SMULOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_STATUS */ -#define SMU_STATUS_SMUPRGERR (0x1UL << 1) /**< SMU Programming Error */ -#define _SMU_STATUS_SMUPRGERR_SHIFT 1 /**< Shift value for SMU_SMUPRGERR */ -#define _SMU_STATUS_SMUPRGERR_MASK 0x2UL /**< Bit mask for SMU_SMUPRGERR */ -#define _SMU_STATUS_SMUPRGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ -#define SMU_STATUS_SMUPRGERR_DEFAULT (_SMU_STATUS_SMUPRGERR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_STATUS */ +#define _SMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_STATUS */ +#define _SMU_STATUS_MASK 0x00000003UL /**< Mask for SMU_STATUS */ +#define SMU_STATUS_SMULOCK (0x1UL << 0) /**< SMU Lock */ +#define _SMU_STATUS_SMULOCK_SHIFT 0 /**< Shift value for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_MASK 0x1UL /**< Bit mask for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_DEFAULT (_SMU_STATUS_SMULOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_UNLOCKED (_SMU_STATUS_SMULOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_LOCKED (_SMU_STATUS_SMULOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR (0x1UL << 1) /**< SMU Programming Error */ +#define _SMU_STATUS_SMUPRGERR_SHIFT 1 /**< Shift value for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_MASK 0x2UL /**< Bit mask for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR_DEFAULT (_SMU_STATUS_SMUPRGERR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_STATUS */ /* Bit fields for SMU LOCK */ -#define _SMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_LOCK */ -#define _SMU_LOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_LOCK */ -#define _SMU_LOCK_SMULOCKKEY_SHIFT 0 /**< Shift value for SMU_SMULOCKKEY */ -#define _SMU_LOCK_SMULOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMULOCKKEY */ -#define _SMU_LOCK_SMULOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_LOCK */ -#define _SMU_LOCK_SMULOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_LOCK */ -#define SMU_LOCK_SMULOCKKEY_DEFAULT (_SMU_LOCK_SMULOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_LOCK */ -#define SMU_LOCK_SMULOCKKEY_UNLOCK (_SMU_LOCK_SMULOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_LOCK */ +#define _SMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_LOCK */ +#define _SMU_LOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_SHIFT 0 /**< Shift value for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_DEFAULT (_SMU_LOCK_SMULOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_UNLOCK (_SMU_LOCK_SMULOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_LOCK */ /* Bit fields for SMU IF */ -#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ -#define _SMU_IF_MASK 0x00030005UL /**< Mask for SMU_IF */ -#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ -#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ -#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ -#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Flag */ -#define _SMU_IF_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ -#define _SMU_IF_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ -#define _SMU_IF_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUINST_DEFAULT (_SMU_IF_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Flag */ -#define _SMU_IF_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ -#define _SMU_IF_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ -#define _SMU_IF_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUSEC_DEFAULT (_SMU_IF_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IF */ -#define SMU_IF_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Flag */ -#define _SMU_IF_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ -#define _SMU_IF_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ -#define _SMU_IF_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ -#define SMU_IF_BMPUSEC_DEFAULT (_SMU_IF_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00030005UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Flag */ +#define _SMU_IF_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IF_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IF_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST_DEFAULT (_SMU_IF_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Flag */ +#define _SMU_IF_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC_DEFAULT (_SMU_IF_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Flag */ +#define _SMU_IF_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC_DEFAULT (_SMU_IF_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IF */ /* Bit fields for SMU IEN */ -#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ -#define _SMU_IEN_MASK 0x00030005UL /**< Mask for SMU_IEN */ -#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Enable */ -#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ -#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ -#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Enable */ -#define _SMU_IEN_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ -#define _SMU_IEN_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ -#define _SMU_IEN_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUINST_DEFAULT (_SMU_IEN_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Enable */ -#define _SMU_IEN_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ -#define _SMU_IEN_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ -#define _SMU_IEN_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUSEC_DEFAULT (_SMU_IEN_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IEN */ -#define SMU_IEN_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Enable */ -#define _SMU_IEN_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ -#define _SMU_IEN_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ -#define _SMU_IEN_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ -#define SMU_IEN_BMPUSEC_DEFAULT (_SMU_IEN_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00030005UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Enable */ +#define _SMU_IEN_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST_DEFAULT (_SMU_IEN_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Enable */ +#define _SMU_IEN_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC_DEFAULT (_SMU_IEN_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Enable */ +#define _SMU_IEN_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC_DEFAULT (_SMU_IEN_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IEN */ /* Bit fields for SMU M33CTRL */ -#define _SMU_M33CTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_M33CTRL */ -#define _SMU_M33CTRL_MASK 0x0000001FUL /**< Mask for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSVTAIRCR (0x1UL << 0) /**< New BitField */ -#define _SMU_M33CTRL_LOCKSVTAIRCR_SHIFT 0 /**< Shift value for SMU_LOCKSVTAIRCR */ -#define _SMU_M33CTRL_LOCKSVTAIRCR_MASK 0x1UL /**< Bit mask for SMU_LOCKSVTAIRCR */ -#define _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT (_SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKNSVTOR (0x1UL << 1) /**< New BitField */ -#define _SMU_M33CTRL_LOCKNSVTOR_SHIFT 1 /**< Shift value for SMU_LOCKNSVTOR */ -#define _SMU_M33CTRL_LOCKNSVTOR_MASK 0x2UL /**< Bit mask for SMU_LOCKNSVTOR */ -#define _SMU_M33CTRL_LOCKNSVTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKNSVTOR_DEFAULT (_SMU_M33CTRL_LOCKNSVTOR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSMPU (0x1UL << 2) /**< New BitField */ -#define _SMU_M33CTRL_LOCKSMPU_SHIFT 2 /**< Shift value for SMU_LOCKSMPU */ -#define _SMU_M33CTRL_LOCKSMPU_MASK 0x4UL /**< Bit mask for SMU_LOCKSMPU */ -#define _SMU_M33CTRL_LOCKSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSMPU_DEFAULT (_SMU_M33CTRL_LOCKSMPU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKNSMPU (0x1UL << 3) /**< New BitField */ -#define _SMU_M33CTRL_LOCKNSMPU_SHIFT 3 /**< Shift value for SMU_LOCKNSMPU */ -#define _SMU_M33CTRL_LOCKNSMPU_MASK 0x8UL /**< Bit mask for SMU_LOCKNSMPU */ -#define _SMU_M33CTRL_LOCKNSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKNSMPU_DEFAULT (_SMU_M33CTRL_LOCKNSMPU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSAU (0x1UL << 4) /**< New BitField */ -#define _SMU_M33CTRL_LOCKSAU_SHIFT 4 /**< Shift value for SMU_LOCKSAU */ -#define _SMU_M33CTRL_LOCKSAU_MASK 0x10UL /**< Bit mask for SMU_LOCKSAU */ -#define _SMU_M33CTRL_LOCKSAU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSAU_DEFAULT (_SMU_M33CTRL_LOCKSAU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define _SMU_M33CTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_M33CTRL */ +#define _SMU_M33CTRL_MASK 0x0000001FUL /**< Mask for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR (0x1UL << 0) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_SHIFT 0 /**< Shift value for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_MASK 0x1UL /**< Bit mask for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT (_SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR (0x1UL << 1) /**< New BitField */ +#define _SMU_M33CTRL_LOCKNSVTOR_SHIFT 1 /**< Shift value for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_MASK 0x2UL /**< Bit mask for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR_DEFAULT (_SMU_M33CTRL_LOCKNSVTOR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU (0x1UL << 2) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSMPU_SHIFT 2 /**< Shift value for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_MASK 0x4UL /**< Bit mask for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU_DEFAULT (_SMU_M33CTRL_LOCKSMPU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU (0x1UL << 3) /**< New BitField */ +#define _SMU_M33CTRL_LOCKNSMPU_SHIFT 3 /**< Shift value for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_MASK 0x8UL /**< Bit mask for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU_DEFAULT (_SMU_M33CTRL_LOCKNSMPU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU (0x1UL << 4) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSAU_SHIFT 4 /**< Shift value for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_MASK 0x10UL /**< Bit mask for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU_DEFAULT (_SMU_M33CTRL_LOCKSAU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_M33CTRL */ /* Bit fields for SMU PPUPATD0 */ -#define _SMU_PPUPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUPATD0 */ -#define _SMU_PPUPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ -#define _SMU_PPUPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ -#define _SMU_PPUPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ -#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ -#define _SMU_PPUPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ -#define _SMU_PPUPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ -#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */ -#define _SMU_PPUPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ -#define _SMU_PPUPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ -#define _SMU_PPUPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_HFRCO0_DEFAULT (_SMU_PPUPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */ -#define _SMU_PPUPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ -#define _SMU_PPUPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ -#define _SMU_PPUPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_FSRCO_DEFAULT (_SMU_PPUPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */ -#define _SMU_PPUPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ -#define _SMU_PPUPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ -#define _SMU_PPUPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_DPLL0_DEFAULT (_SMU_PPUPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */ -#define _SMU_PPUPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ -#define _SMU_PPUPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ -#define _SMU_PPUPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LFXO_DEFAULT (_SMU_PPUPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */ -#define _SMU_PPUPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ -#define _SMU_PPUPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ -#define _SMU_PPUPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LFRCO_DEFAULT (_SMU_PPUPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */ -#define _SMU_PPUPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ -#define _SMU_PPUPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ -#define _SMU_PPUPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_ULFRCO_DEFAULT (_SMU_PPUPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */ -#define _SMU_PPUPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ -#define _SMU_PPUPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ -#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */ -#define _SMU_PPUPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ -#define _SMU_PPUPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ -#define _SMU_PPUPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_ICACHE0_DEFAULT (_SMU_PPUPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */ -#define _SMU_PPUPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ -#define _SMU_PPUPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ -#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */ -#define _SMU_PPUPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ -#define _SMU_PPUPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ -#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */ -#define _SMU_PPUPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ -#define _SMU_PPUPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ -#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */ -#define _SMU_PPUPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ -#define _SMU_PPUPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ -#define _SMU_PPUPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LDMAXBAR_DEFAULT (_SMU_PPUPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */ -#define _SMU_PPUPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ -#define _SMU_PPUPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ -#define _SMU_PPUPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER0_DEFAULT (_SMU_PPUPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */ -#define _SMU_PPUPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ -#define _SMU_PPUPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ -#define _SMU_PPUPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER1_DEFAULT (_SMU_PPUPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */ -#define _SMU_PPUPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ -#define _SMU_PPUPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ -#define _SMU_PPUPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER2_DEFAULT (_SMU_PPUPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */ -#define _SMU_PPUPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ -#define _SMU_PPUPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ -#define _SMU_PPUPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER3_DEFAULT (_SMU_PPUPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */ -#define _SMU_PPUPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ -#define _SMU_PPUPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ -#define _SMU_PPUPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER4_DEFAULT (_SMU_PPUPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */ -#define _SMU_PPUPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ -#define _SMU_PPUPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ -#define _SMU_PPUPATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_USART0_DEFAULT (_SMU_PPUPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */ -#define _SMU_PPUPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ -#define _SMU_PPUPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ -#define _SMU_PPUPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_BURTC_DEFAULT (_SMU_PPUPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */ -#define _SMU_PPUPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ -#define _SMU_PPUPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ -#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */ -#define _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ -#define _SMU_PPUPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ -#define _SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */ -#define _SMU_PPUPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ -#define _SMU_PPUPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ -#define _SMU_PPUPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSCFG_DEFAULT (_SMU_PPUPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */ -#define _SMU_PPUPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ -#define _SMU_PPUPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ -#define _SMU_PPUPATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_BURAM_DEFAULT (_SMU_PPUPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */ -#define _SMU_PPUPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ -#define _SMU_PPUPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ -#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */ -#define _SMU_PPUPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ -#define _SMU_PPUPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ -#define _SMU_PPUPATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_DCDC_DEFAULT (_SMU_PPUPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */ -#define _SMU_PPUPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ -#define _SMU_PPUPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ -#define _SMU_PPUPATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */ -#define _SMU_PPUPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ -#define _SMU_PPUPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ -#define _SMU_PPUPATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EUSART1_DEFAULT (_SMU_PPUPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EUSART2 (0x1UL << 31) /**< EUSART2 Privileged Access */ -#define _SMU_PPUPATD0_EUSART2_SHIFT 31 /**< Shift value for SMU_EUSART2 */ -#define _SMU_PPUPATD0_EUSART2_MASK 0x80000000UL /**< Bit mask for SMU_EUSART2 */ -#define _SMU_PPUPATD0_EUSART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EUSART2_DEFAULT (_SMU_PPUPATD0_EUSART2_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0_DEFAULT (_SMU_PPUPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */ +#define _SMU_PPUPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO_DEFAULT (_SMU_PPUPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */ +#define _SMU_PPUPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0_DEFAULT (_SMU_PPUPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */ +#define _SMU_PPUPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO_DEFAULT (_SMU_PPUPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */ +#define _SMU_PPUPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO_DEFAULT (_SMU_PPUPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */ +#define _SMU_PPUPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO_DEFAULT (_SMU_PPUPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */ +#define _SMU_PPUPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0_DEFAULT (_SMU_PPUPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */ +#define _SMU_PPUPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */ +#define _SMU_PPUPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */ +#define _SMU_PPUPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR_DEFAULT (_SMU_PPUPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */ +#define _SMU_PPUPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0_DEFAULT (_SMU_PPUPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */ +#define _SMU_PPUPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1_DEFAULT (_SMU_PPUPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */ +#define _SMU_PPUPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2_DEFAULT (_SMU_PPUPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */ +#define _SMU_PPUPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3_DEFAULT (_SMU_PPUPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */ +#define _SMU_PPUPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4_DEFAULT (_SMU_PPUPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */ +#define _SMU_PPUPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART0_DEFAULT (_SMU_PPUPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */ +#define _SMU_PPUPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC_DEFAULT (_SMU_PPUPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */ +#define _SMU_PPUPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */ +#define _SMU_PPUPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG_DEFAULT (_SMU_PPUPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */ +#define _SMU_PPUPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUPATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURAM_DEFAULT (_SMU_PPUPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */ +#define _SMU_PPUPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUPATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DCDC_DEFAULT (_SMU_PPUPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */ +#define _SMU_PPUPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUPATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */ +#define _SMU_PPUPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUPATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EUSART1_DEFAULT (_SMU_PPUPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EUSART2 (0x1UL << 31) /**< EUSART2 Privileged Access */ +#define _SMU_PPUPATD0_EUSART2_SHIFT 31 /**< Shift value for SMU_EUSART2 */ +#define _SMU_PPUPATD0_EUSART2_MASK 0x80000000UL /**< Bit mask for SMU_EUSART2 */ +#define _SMU_PPUPATD0_EUSART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EUSART2_DEFAULT (_SMU_PPUPATD0_EUSART2_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ /* Bit fields for SMU PPUPATD1 */ -#define _SMU_PPUPATD1_RESETVALUE 0x03FFFFFFUL /**< Default value for SMU_PPUPATD1 */ -#define _SMU_PPUPATD1_MASK 0x03FFFFFFUL /**< Mask for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SYSRTC (0x1UL << 0) /**< SYSRTC Privileged Access */ -#define _SMU_PPUPATD1_SYSRTC_SHIFT 0 /**< Shift value for SMU_SYSRTC */ -#define _SMU_PPUPATD1_SYSRTC_MASK 0x1UL /**< Bit mask for SMU_SYSRTC */ -#define _SMU_PPUPATD1_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SYSRTC_DEFAULT (_SMU_PPUPATD1_SYSRTC_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LCD (0x1UL << 1) /**< LCD Privileged Access */ -#define _SMU_PPUPATD1_LCD_SHIFT 1 /**< Shift value for SMU_LCD */ -#define _SMU_PPUPATD1_LCD_MASK 0x2UL /**< Bit mask for SMU_LCD */ -#define _SMU_PPUPATD1_LCD_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LCD_DEFAULT (_SMU_PPUPATD1_LCD_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_KEYSCAN (0x1UL << 2) /**< KEYSCAN Privileged Access */ -#define _SMU_PPUPATD1_KEYSCAN_SHIFT 2 /**< Shift value for SMU_KEYSCAN */ -#define _SMU_PPUPATD1_KEYSCAN_MASK 0x4UL /**< Bit mask for SMU_KEYSCAN */ -#define _SMU_PPUPATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_KEYSCAN_DEFAULT (_SMU_PPUPATD1_KEYSCAN_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_DMEM (0x1UL << 3) /**< DMEM Privileged Access */ -#define _SMU_PPUPATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ -#define _SMU_PPUPATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ -#define _SMU_PPUPATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_DMEM_DEFAULT (_SMU_PPUPATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LCDRF (0x1UL << 4) /**< LCDRF Privileged Access */ -#define _SMU_PPUPATD1_LCDRF_SHIFT 4 /**< Shift value for SMU_LCDRF */ -#define _SMU_PPUPATD1_LCDRF_MASK 0x10UL /**< Bit mask for SMU_LCDRF */ -#define _SMU_PPUPATD1_LCDRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LCDRF_DEFAULT (_SMU_PPUPATD1_LCDRF_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_PFMXPPRF (0x1UL << 5) /**< PFMXPPRF Privileged Access */ -#define _SMU_PPUPATD1_PFMXPPRF_SHIFT 5 /**< Shift value for SMU_PFMXPPRF */ -#define _SMU_PPUPATD1_PFMXPPRF_MASK 0x20UL /**< Bit mask for SMU_PFMXPPRF */ -#define _SMU_PPUPATD1_PFMXPPRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_PFMXPPRF_DEFAULT (_SMU_PPUPATD1_PFMXPPRF_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_RADIOAES (0x1UL << 6) /**< RADIOAES Privileged Access */ -#define _SMU_PPUPATD1_RADIOAES_SHIFT 6 /**< Shift value for SMU_RADIOAES */ -#define _SMU_PPUPATD1_RADIOAES_MASK 0x40UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_PPUPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_RADIOAES_DEFAULT (_SMU_PPUPATD1_RADIOAES_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SMU (0x1UL << 7) /**< SMU Privileged Access */ -#define _SMU_PPUPATD1_SMU_SHIFT 7 /**< Shift value for SMU_SMU */ -#define _SMU_PPUPATD1_SMU_MASK 0x80UL /**< Bit mask for SMU_SMU */ -#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SMUCFGNS (0x1UL << 8) /**< SMUCFGNS Privileged Access */ -#define _SMU_PPUPATD1_SMUCFGNS_SHIFT 8 /**< Shift value for SMU_SMUCFGNS */ -#define _SMU_PPUPATD1_SMUCFGNS_MASK 0x100UL /**< Bit mask for SMU_SMUCFGNS */ -#define _SMU_PPUPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SMUCFGNS_DEFAULT (_SMU_PPUPATD1_SMUCFGNS_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LETIMER0 (0x1UL << 9) /**< LETIMER0 Privileged Access */ -#define _SMU_PPUPATD1_LETIMER0_SHIFT 9 /**< Shift value for SMU_LETIMER0 */ -#define _SMU_PPUPATD1_LETIMER0_MASK 0x200UL /**< Bit mask for SMU_LETIMER0 */ -#define _SMU_PPUPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LETIMER0_DEFAULT (_SMU_PPUPATD1_LETIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_IADC0 (0x1UL << 10) /**< IADC0 Privileged Access */ -#define _SMU_PPUPATD1_IADC0_SHIFT 10 /**< Shift value for SMU_IADC0 */ -#define _SMU_PPUPATD1_IADC0_MASK 0x400UL /**< Bit mask for SMU_IADC0 */ -#define _SMU_PPUPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_IADC0_DEFAULT (_SMU_PPUPATD1_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_ACMP0 (0x1UL << 11) /**< ACMP0 Privileged Access */ -#define _SMU_PPUPATD1_ACMP0_SHIFT 11 /**< Shift value for SMU_ACMP0 */ -#define _SMU_PPUPATD1_ACMP0_MASK 0x800UL /**< Bit mask for SMU_ACMP0 */ -#define _SMU_PPUPATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_ACMP0_DEFAULT (_SMU_PPUPATD1_ACMP0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_ACMP1 (0x1UL << 12) /**< ACMP1 Privileged Access */ -#define _SMU_PPUPATD1_ACMP1_SHIFT 12 /**< Shift value for SMU_ACMP1 */ -#define _SMU_PPUPATD1_ACMP1_MASK 0x1000UL /**< Bit mask for SMU_ACMP1 */ -#define _SMU_PPUPATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_ACMP1_DEFAULT (_SMU_PPUPATD1_ACMP1_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_AMUXCP0 (0x1UL << 13) /**< AMUXCP0 Privileged Access */ -#define _SMU_PPUPATD1_AMUXCP0_SHIFT 13 /**< Shift value for SMU_AMUXCP0 */ -#define _SMU_PPUPATD1_AMUXCP0_MASK 0x2000UL /**< Bit mask for SMU_AMUXCP0 */ -#define _SMU_PPUPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_AMUXCP0_DEFAULT (_SMU_PPUPATD1_AMUXCP0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_VDAC0 (0x1UL << 14) /**< VDAC0 Privileged Access */ -#define _SMU_PPUPATD1_VDAC0_SHIFT 14 /**< Shift value for SMU_VDAC0 */ -#define _SMU_PPUPATD1_VDAC0_MASK 0x4000UL /**< Bit mask for SMU_VDAC0 */ -#define _SMU_PPUPATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_VDAC0_DEFAULT (_SMU_PPUPATD1_VDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_PCNT (0x1UL << 15) /**< PCNT Privileged Access */ -#define _SMU_PPUPATD1_PCNT_SHIFT 15 /**< Shift value for SMU_PCNT */ -#define _SMU_PPUPATD1_PCNT_MASK 0x8000UL /**< Bit mask for SMU_PCNT */ -#define _SMU_PPUPATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_PCNT_DEFAULT (_SMU_PPUPATD1_PCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LESENSE (0x1UL << 16) /**< LESENSE Privileged Access */ -#define _SMU_PPUPATD1_LESENSE_SHIFT 16 /**< Shift value for SMU_LESENSE */ -#define _SMU_PPUPATD1_LESENSE_MASK 0x10000UL /**< Bit mask for SMU_LESENSE */ -#define _SMU_PPUPATD1_LESENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LESENSE_DEFAULT (_SMU_PPUPATD1_LESENSE_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_HFRCO1 (0x1UL << 17) /**< HFRCO1 Privileged Access */ -#define _SMU_PPUPATD1_HFRCO1_SHIFT 17 /**< Shift value for SMU_HFRCO1 */ -#define _SMU_PPUPATD1_HFRCO1_MASK 0x20000UL /**< Bit mask for SMU_HFRCO1 */ -#define _SMU_PPUPATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_HFRCO1_DEFAULT (_SMU_PPUPATD1_HFRCO1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_HFXO0 (0x1UL << 18) /**< HFXO0 Privileged Access */ -#define _SMU_PPUPATD1_HFXO0_SHIFT 18 /**< Shift value for SMU_HFXO0 */ -#define _SMU_PPUPATD1_HFXO0_MASK 0x40000UL /**< Bit mask for SMU_HFXO0 */ -#define _SMU_PPUPATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_HFXO0_DEFAULT (_SMU_PPUPATD1_HFXO0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_I2C0 (0x1UL << 19) /**< I2C0 Privileged Access */ -#define _SMU_PPUPATD1_I2C0_SHIFT 19 /**< Shift value for SMU_I2C0 */ -#define _SMU_PPUPATD1_I2C0_MASK 0x80000UL /**< Bit mask for SMU_I2C0 */ -#define _SMU_PPUPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_I2C0_DEFAULT (_SMU_PPUPATD1_I2C0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_WDOG0 (0x1UL << 20) /**< WDOG0 Privileged Access */ -#define _SMU_PPUPATD1_WDOG0_SHIFT 20 /**< Shift value for SMU_WDOG0 */ -#define _SMU_PPUPATD1_WDOG0_MASK 0x100000UL /**< Bit mask for SMU_WDOG0 */ -#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_WDOG1 (0x1UL << 21) /**< WDOG1 Privileged Access */ -#define _SMU_PPUPATD1_WDOG1_SHIFT 21 /**< Shift value for SMU_WDOG1 */ -#define _SMU_PPUPATD1_WDOG1_MASK 0x200000UL /**< Bit mask for SMU_WDOG1 */ -#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_EUSART0 (0x1UL << 22) /**< EUSART0 Privileged Access */ -#define _SMU_PPUPATD1_EUSART0_SHIFT 22 /**< Shift value for SMU_EUSART0 */ -#define _SMU_PPUPATD1_EUSART0_MASK 0x400000UL /**< Bit mask for SMU_EUSART0 */ -#define _SMU_PPUPATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_EUSART0_DEFAULT (_SMU_PPUPATD1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SEMAILBOX (0x1UL << 23) /**< SEMAILBOX Privileged Access */ -#define _SMU_PPUPATD1_SEMAILBOX_SHIFT 23 /**< Shift value for SMU_SEMAILBOX */ -#define _SMU_PPUPATD1_SEMAILBOX_MASK 0x800000UL /**< Bit mask for SMU_SEMAILBOX */ -#define _SMU_PPUPATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SEMAILBOX_DEFAULT (_SMU_PPUPATD1_SEMAILBOX_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_AHBRADIO (0x1UL << 25) /**< AHBRADIO Privileged Access */ -#define _SMU_PPUPATD1_AHBRADIO_SHIFT 25 /**< Shift value for SMU_AHBRADIO */ -#define _SMU_PPUPATD1_AHBRADIO_MASK 0x2000000UL /**< Bit mask for SMU_AHBRADIO */ -#define _SMU_PPUPATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_AHBRADIO_DEFAULT (_SMU_PPUPATD1_AHBRADIO_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x03FFFFFFUL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0x03FFFFFFUL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SYSRTC (0x1UL << 0) /**< SYSRTC Privileged Access */ +#define _SMU_PPUPATD1_SYSRTC_SHIFT 0 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUPATD1_SYSRTC_MASK 0x1UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUPATD1_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SYSRTC_DEFAULT (_SMU_PPUPATD1_SYSRTC_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LCD (0x1UL << 1) /**< LCD Privileged Access */ +#define _SMU_PPUPATD1_LCD_SHIFT 1 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD1_LCD_MASK 0x2UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD1_LCD_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LCD_DEFAULT (_SMU_PPUPATD1_LCD_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_KEYSCAN (0x1UL << 2) /**< KEYSCAN Privileged Access */ +#define _SMU_PPUPATD1_KEYSCAN_SHIFT 2 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUPATD1_KEYSCAN_MASK 0x4UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUPATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_KEYSCAN_DEFAULT (_SMU_PPUPATD1_KEYSCAN_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DMEM (0x1UL << 3) /**< DMEM Privileged Access */ +#define _SMU_PPUPATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUPATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUPATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DMEM_DEFAULT (_SMU_PPUPATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LCDRF (0x1UL << 4) /**< LCDRF Privileged Access */ +#define _SMU_PPUPATD1_LCDRF_SHIFT 4 /**< Shift value for SMU_LCDRF */ +#define _SMU_PPUPATD1_LCDRF_MASK 0x10UL /**< Bit mask for SMU_LCDRF */ +#define _SMU_PPUPATD1_LCDRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LCDRF_DEFAULT (_SMU_PPUPATD1_LCDRF_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PFMXPPRF (0x1UL << 5) /**< PFMXPPRF Privileged Access */ +#define _SMU_PPUPATD1_PFMXPPRF_SHIFT 5 /**< Shift value for SMU_PFMXPPRF */ +#define _SMU_PPUPATD1_PFMXPPRF_MASK 0x20UL /**< Bit mask for SMU_PFMXPPRF */ +#define _SMU_PPUPATD1_PFMXPPRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PFMXPPRF_DEFAULT (_SMU_PPUPATD1_PFMXPPRF_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES (0x1UL << 6) /**< RADIOAES Privileged Access */ +#define _SMU_PPUPATD1_RADIOAES_SHIFT 6 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_MASK 0x40UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES_DEFAULT (_SMU_PPUPATD1_RADIOAES_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 7) /**< SMU Privileged Access */ +#define _SMU_PPUPATD1_SMU_SHIFT 7 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x80UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS (0x1UL << 8) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUPATD1_SMUCFGNS_SHIFT 8 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_MASK 0x100UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS_DEFAULT (_SMU_PPUPATD1_SMUCFGNS_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0 (0x1UL << 9) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUPATD1_LETIMER0_SHIFT 9 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_MASK 0x200UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0_DEFAULT (_SMU_PPUPATD1_LETIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0 (0x1UL << 10) /**< IADC0 Privileged Access */ +#define _SMU_PPUPATD1_IADC0_SHIFT 10 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_MASK 0x400UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0_DEFAULT (_SMU_PPUPATD1_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP0 (0x1UL << 11) /**< ACMP0 Privileged Access */ +#define _SMU_PPUPATD1_ACMP0_SHIFT 11 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD1_ACMP0_MASK 0x800UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP0_DEFAULT (_SMU_PPUPATD1_ACMP0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP1 (0x1UL << 12) /**< ACMP1 Privileged Access */ +#define _SMU_PPUPATD1_ACMP1_SHIFT 12 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD1_ACMP1_MASK 0x1000UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP1_DEFAULT (_SMU_PPUPATD1_ACMP1_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0 (0x1UL << 13) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUPATD1_AMUXCP0_SHIFT 13 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_MASK 0x2000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0_DEFAULT (_SMU_PPUPATD1_AMUXCP0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC0 (0x1UL << 14) /**< VDAC0 Privileged Access */ +#define _SMU_PPUPATD1_VDAC0_SHIFT 14 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD1_VDAC0_MASK 0x4000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC0_DEFAULT (_SMU_PPUPATD1_VDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT (0x1UL << 15) /**< PCNT Privileged Access */ +#define _SMU_PPUPATD1_PCNT_SHIFT 15 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUPATD1_PCNT_MASK 0x8000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUPATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT_DEFAULT (_SMU_PPUPATD1_PCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LESENSE (0x1UL << 16) /**< LESENSE Privileged Access */ +#define _SMU_PPUPATD1_LESENSE_SHIFT 16 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD1_LESENSE_MASK 0x10000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD1_LESENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LESENSE_DEFAULT (_SMU_PPUPATD1_LESENSE_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFRCO1 (0x1UL << 17) /**< HFRCO1 Privileged Access */ +#define _SMU_PPUPATD1_HFRCO1_SHIFT 17 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUPATD1_HFRCO1_MASK 0x20000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUPATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFRCO1_DEFAULT (_SMU_PPUPATD1_HFRCO1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFXO0 (0x1UL << 18) /**< HFXO0 Privileged Access */ +#define _SMU_PPUPATD1_HFXO0_SHIFT 18 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUPATD1_HFXO0_MASK 0x40000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUPATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFXO0_DEFAULT (_SMU_PPUPATD1_HFXO0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0 (0x1UL << 19) /**< I2C0 Privileged Access */ +#define _SMU_PPUPATD1_I2C0_SHIFT 19 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_MASK 0x80000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0_DEFAULT (_SMU_PPUPATD1_I2C0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 20) /**< WDOG0 Privileged Access */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 20 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x100000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 21) /**< WDOG1 Privileged Access */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 21 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x200000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART0 (0x1UL << 22) /**< EUSART0 Privileged Access */ +#define _SMU_PPUPATD1_EUSART0_SHIFT 22 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUPATD1_EUSART0_MASK 0x400000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUPATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART0_DEFAULT (_SMU_PPUPATD1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SEMAILBOX (0x1UL << 23) /**< SEMAILBOX Privileged Access */ +#define _SMU_PPUPATD1_SEMAILBOX_SHIFT 23 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUPATD1_SEMAILBOX_MASK 0x800000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUPATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SEMAILBOX_DEFAULT (_SMU_PPUPATD1_SEMAILBOX_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AHBRADIO (0x1UL << 25) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUPATD1_AHBRADIO_SHIFT 25 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUPATD1_AHBRADIO_MASK 0x2000000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUPATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AHBRADIO_DEFAULT (_SMU_PPUPATD1_AHBRADIO_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ /* Bit fields for SMU PPUSATD0 */ -#define _SMU_PPUSATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUSATD0 */ -#define _SMU_PPUSATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EMU (0x1UL << 1) /**< EMU Secure Access */ -#define _SMU_PPUSATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ -#define _SMU_PPUSATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ -#define _SMU_PPUSATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EMU_DEFAULT (_SMU_PPUSATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_CMU (0x1UL << 2) /**< CMU Secure Access */ -#define _SMU_PPUSATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ -#define _SMU_PPUSATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ -#define _SMU_PPUSATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_CMU_DEFAULT (_SMU_PPUSATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Secure Access */ -#define _SMU_PPUSATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ -#define _SMU_PPUSATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ -#define _SMU_PPUSATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_HFRCO0_DEFAULT (_SMU_PPUSATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_FSRCO (0x1UL << 4) /**< FSRCO Secure Access */ -#define _SMU_PPUSATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ -#define _SMU_PPUSATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ -#define _SMU_PPUSATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_FSRCO_DEFAULT (_SMU_PPUSATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Secure Access */ -#define _SMU_PPUSATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ -#define _SMU_PPUSATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ -#define _SMU_PPUSATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_DPLL0_DEFAULT (_SMU_PPUSATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LFXO (0x1UL << 6) /**< LFXO Secure Access */ -#define _SMU_PPUSATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ -#define _SMU_PPUSATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ -#define _SMU_PPUSATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LFXO_DEFAULT (_SMU_PPUSATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LFRCO (0x1UL << 7) /**< LFRCO Secure Access */ -#define _SMU_PPUSATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ -#define _SMU_PPUSATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ -#define _SMU_PPUSATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LFRCO_DEFAULT (_SMU_PPUSATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Secure Access */ -#define _SMU_PPUSATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ -#define _SMU_PPUSATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ -#define _SMU_PPUSATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_ULFRCO_DEFAULT (_SMU_PPUSATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_MSC (0x1UL << 9) /**< MSC Secure Access */ -#define _SMU_PPUSATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ -#define _SMU_PPUSATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ -#define _SMU_PPUSATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_MSC_DEFAULT (_SMU_PPUSATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Secure Access */ -#define _SMU_PPUSATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ -#define _SMU_PPUSATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ -#define _SMU_PPUSATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_ICACHE0_DEFAULT (_SMU_PPUSATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_PRS (0x1UL << 11) /**< PRS Secure Access */ -#define _SMU_PPUSATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ -#define _SMU_PPUSATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ -#define _SMU_PPUSATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_PRS_DEFAULT (_SMU_PPUSATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_GPIO (0x1UL << 12) /**< GPIO Secure Access */ -#define _SMU_PPUSATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ -#define _SMU_PPUSATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ -#define _SMU_PPUSATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_GPIO_DEFAULT (_SMU_PPUSATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LDMA (0x1UL << 13) /**< LDMA Secure Access */ -#define _SMU_PPUSATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ -#define _SMU_PPUSATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ -#define _SMU_PPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LDMA_DEFAULT (_SMU_PPUSATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Secure Access */ -#define _SMU_PPUSATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ -#define _SMU_PPUSATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ -#define _SMU_PPUSATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LDMAXBAR_DEFAULT (_SMU_PPUSATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Secure Access */ -#define _SMU_PPUSATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ -#define _SMU_PPUSATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ -#define _SMU_PPUSATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER0_DEFAULT (_SMU_PPUSATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Secure Access */ -#define _SMU_PPUSATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ -#define _SMU_PPUSATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ -#define _SMU_PPUSATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER1_DEFAULT (_SMU_PPUSATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Secure Access */ -#define _SMU_PPUSATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ -#define _SMU_PPUSATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ -#define _SMU_PPUSATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER2_DEFAULT (_SMU_PPUSATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Secure Access */ -#define _SMU_PPUSATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ -#define _SMU_PPUSATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ -#define _SMU_PPUSATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER3_DEFAULT (_SMU_PPUSATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Secure Access */ -#define _SMU_PPUSATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ -#define _SMU_PPUSATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ -#define _SMU_PPUSATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER4_DEFAULT (_SMU_PPUSATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_USART0 (0x1UL << 20) /**< USART0 Secure Access */ -#define _SMU_PPUSATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ -#define _SMU_PPUSATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ -#define _SMU_PPUSATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_USART0_DEFAULT (_SMU_PPUSATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_BURTC (0x1UL << 21) /**< BURTC Secure Access */ -#define _SMU_PPUSATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ -#define _SMU_PPUSATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ -#define _SMU_PPUSATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_BURTC_DEFAULT (_SMU_PPUSATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_I2C1 (0x1UL << 22) /**< I2C1 Secure Access */ -#define _SMU_PPUSATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ -#define _SMU_PPUSATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ -#define _SMU_PPUSATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_I2C1_DEFAULT (_SMU_PPUSATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Secure Access */ -#define _SMU_PPUSATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ -#define _SMU_PPUSATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ -#define _SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Secure Access */ -#define _SMU_PPUSATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ -#define _SMU_PPUSATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ -#define _SMU_PPUSATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSCFG_DEFAULT (_SMU_PPUSATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_BURAM (0x1UL << 26) /**< BURAM Secure Access */ -#define _SMU_PPUSATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ -#define _SMU_PPUSATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ -#define _SMU_PPUSATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_BURAM_DEFAULT (_SMU_PPUSATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_GPCRC (0x1UL << 27) /**< GPCRC Secure Access */ -#define _SMU_PPUSATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ -#define _SMU_PPUSATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ -#define _SMU_PPUSATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_GPCRC_DEFAULT (_SMU_PPUSATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_DCDC (0x1UL << 28) /**< DCDC Secure Access */ -#define _SMU_PPUSATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ -#define _SMU_PPUSATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ -#define _SMU_PPUSATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_DCDC_DEFAULT (_SMU_PPUSATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Secure Access */ -#define _SMU_PPUSATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ -#define _SMU_PPUSATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ -#define _SMU_PPUSATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUSATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Secure Access */ -#define _SMU_PPUSATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ -#define _SMU_PPUSATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ -#define _SMU_PPUSATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EUSART1_DEFAULT (_SMU_PPUSATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EUSART2 (0x1UL << 31) /**< EUSART2 Secure Access */ -#define _SMU_PPUSATD0_EUSART2_SHIFT 31 /**< Shift value for SMU_EUSART2 */ -#define _SMU_PPUSATD0_EUSART2_MASK 0x80000000UL /**< Bit mask for SMU_EUSART2 */ -#define _SMU_PPUSATD0_EUSART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EUSART2_DEFAULT (_SMU_PPUSATD0_EUSART2_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define _SMU_PPUSATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUSATD0 */ +#define _SMU_PPUSATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU (0x1UL << 1) /**< EMU Secure Access */ +#define _SMU_PPUSATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU_DEFAULT (_SMU_PPUSATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU (0x1UL << 2) /**< CMU Secure Access */ +#define _SMU_PPUSATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU_DEFAULT (_SMU_PPUSATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Secure Access */ +#define _SMU_PPUSATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0_DEFAULT (_SMU_PPUSATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO (0x1UL << 4) /**< FSRCO Secure Access */ +#define _SMU_PPUSATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO_DEFAULT (_SMU_PPUSATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Secure Access */ +#define _SMU_PPUSATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0_DEFAULT (_SMU_PPUSATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO (0x1UL << 6) /**< LFXO Secure Access */ +#define _SMU_PPUSATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO_DEFAULT (_SMU_PPUSATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO (0x1UL << 7) /**< LFRCO Secure Access */ +#define _SMU_PPUSATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO_DEFAULT (_SMU_PPUSATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Secure Access */ +#define _SMU_PPUSATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO_DEFAULT (_SMU_PPUSATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC (0x1UL << 9) /**< MSC Secure Access */ +#define _SMU_PPUSATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC_DEFAULT (_SMU_PPUSATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Secure Access */ +#define _SMU_PPUSATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0_DEFAULT (_SMU_PPUSATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS (0x1UL << 11) /**< PRS Secure Access */ +#define _SMU_PPUSATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS_DEFAULT (_SMU_PPUSATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO (0x1UL << 12) /**< GPIO Secure Access */ +#define _SMU_PPUSATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO_DEFAULT (_SMU_PPUSATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA (0x1UL << 13) /**< LDMA Secure Access */ +#define _SMU_PPUSATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA_DEFAULT (_SMU_PPUSATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Secure Access */ +#define _SMU_PPUSATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR_DEFAULT (_SMU_PPUSATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Secure Access */ +#define _SMU_PPUSATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0_DEFAULT (_SMU_PPUSATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Secure Access */ +#define _SMU_PPUSATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1_DEFAULT (_SMU_PPUSATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Secure Access */ +#define _SMU_PPUSATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2_DEFAULT (_SMU_PPUSATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Secure Access */ +#define _SMU_PPUSATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3_DEFAULT (_SMU_PPUSATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Secure Access */ +#define _SMU_PPUSATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4_DEFAULT (_SMU_PPUSATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART0 (0x1UL << 20) /**< USART0 Secure Access */ +#define _SMU_PPUSATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUSATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUSATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART0_DEFAULT (_SMU_PPUSATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC (0x1UL << 21) /**< BURTC Secure Access */ +#define _SMU_PPUSATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC_DEFAULT (_SMU_PPUSATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_I2C1 (0x1UL << 22) /**< I2C1 Secure Access */ +#define _SMU_PPUSATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUSATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUSATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_I2C1_DEFAULT (_SMU_PPUSATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Secure Access */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Secure Access */ +#define _SMU_PPUSATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG_DEFAULT (_SMU_PPUSATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURAM (0x1UL << 26) /**< BURAM Secure Access */ +#define _SMU_PPUSATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUSATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUSATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURAM_DEFAULT (_SMU_PPUSATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPCRC (0x1UL << 27) /**< GPCRC Secure Access */ +#define _SMU_PPUSATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUSATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUSATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPCRC_DEFAULT (_SMU_PPUSATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DCDC (0x1UL << 28) /**< DCDC Secure Access */ +#define _SMU_PPUSATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUSATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUSATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DCDC_DEFAULT (_SMU_PPUSATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Secure Access */ +#define _SMU_PPUSATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUSATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUSATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUSATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Secure Access */ +#define _SMU_PPUSATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUSATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUSATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EUSART1_DEFAULT (_SMU_PPUSATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EUSART2 (0x1UL << 31) /**< EUSART2 Secure Access */ +#define _SMU_PPUSATD0_EUSART2_SHIFT 31 /**< Shift value for SMU_EUSART2 */ +#define _SMU_PPUSATD0_EUSART2_MASK 0x80000000UL /**< Bit mask for SMU_EUSART2 */ +#define _SMU_PPUSATD0_EUSART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EUSART2_DEFAULT (_SMU_PPUSATD0_EUSART2_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ /* Bit fields for SMU PPUSATD1 */ -#define _SMU_PPUSATD1_RESETVALUE 0x03FFFFFFUL /**< Default value for SMU_PPUSATD1 */ -#define _SMU_PPUSATD1_MASK 0x03FFFFFFUL /**< Mask for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SYSRTC (0x1UL << 0) /**< SYSRTC Secure Access */ -#define _SMU_PPUSATD1_SYSRTC_SHIFT 0 /**< Shift value for SMU_SYSRTC */ -#define _SMU_PPUSATD1_SYSRTC_MASK 0x1UL /**< Bit mask for SMU_SYSRTC */ -#define _SMU_PPUSATD1_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SYSRTC_DEFAULT (_SMU_PPUSATD1_SYSRTC_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LCD (0x1UL << 1) /**< LCD Secure Access */ -#define _SMU_PPUSATD1_LCD_SHIFT 1 /**< Shift value for SMU_LCD */ -#define _SMU_PPUSATD1_LCD_MASK 0x2UL /**< Bit mask for SMU_LCD */ -#define _SMU_PPUSATD1_LCD_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LCD_DEFAULT (_SMU_PPUSATD1_LCD_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_KEYSCAN (0x1UL << 2) /**< KEYSCAN Secure Access */ -#define _SMU_PPUSATD1_KEYSCAN_SHIFT 2 /**< Shift value for SMU_KEYSCAN */ -#define _SMU_PPUSATD1_KEYSCAN_MASK 0x4UL /**< Bit mask for SMU_KEYSCAN */ -#define _SMU_PPUSATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_KEYSCAN_DEFAULT (_SMU_PPUSATD1_KEYSCAN_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_DMEM (0x1UL << 3) /**< DMEM Secure Access */ -#define _SMU_PPUSATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ -#define _SMU_PPUSATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ -#define _SMU_PPUSATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_DMEM_DEFAULT (_SMU_PPUSATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LCDRF (0x1UL << 4) /**< LCDRF Secure Access */ -#define _SMU_PPUSATD1_LCDRF_SHIFT 4 /**< Shift value for SMU_LCDRF */ -#define _SMU_PPUSATD1_LCDRF_MASK 0x10UL /**< Bit mask for SMU_LCDRF */ -#define _SMU_PPUSATD1_LCDRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LCDRF_DEFAULT (_SMU_PPUSATD1_LCDRF_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_PFMXPPRF (0x1UL << 5) /**< PFMXPPRF Secure Access */ -#define _SMU_PPUSATD1_PFMXPPRF_SHIFT 5 /**< Shift value for SMU_PFMXPPRF */ -#define _SMU_PPUSATD1_PFMXPPRF_MASK 0x20UL /**< Bit mask for SMU_PFMXPPRF */ -#define _SMU_PPUSATD1_PFMXPPRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_PFMXPPRF_DEFAULT (_SMU_PPUSATD1_PFMXPPRF_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_RADIOAES (0x1UL << 6) /**< RADIOAES Secure Access */ -#define _SMU_PPUSATD1_RADIOAES_SHIFT 6 /**< Shift value for SMU_RADIOAES */ -#define _SMU_PPUSATD1_RADIOAES_MASK 0x40UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_PPUSATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_RADIOAES_DEFAULT (_SMU_PPUSATD1_RADIOAES_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SMU (0x1UL << 7) /**< SMU Secure Access */ -#define _SMU_PPUSATD1_SMU_SHIFT 7 /**< Shift value for SMU_SMU */ -#define _SMU_PPUSATD1_SMU_MASK 0x80UL /**< Bit mask for SMU_SMU */ -#define _SMU_PPUSATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SMU_DEFAULT (_SMU_PPUSATD1_SMU_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SMUCFGNS (0x1UL << 8) /**< SMUCFGNS Secure Access */ -#define _SMU_PPUSATD1_SMUCFGNS_SHIFT 8 /**< Shift value for SMU_SMUCFGNS */ -#define _SMU_PPUSATD1_SMUCFGNS_MASK 0x100UL /**< Bit mask for SMU_SMUCFGNS */ -#define _SMU_PPUSATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SMUCFGNS_DEFAULT (_SMU_PPUSATD1_SMUCFGNS_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LETIMER0 (0x1UL << 9) /**< LETIMER0 Secure Access */ -#define _SMU_PPUSATD1_LETIMER0_SHIFT 9 /**< Shift value for SMU_LETIMER0 */ -#define _SMU_PPUSATD1_LETIMER0_MASK 0x200UL /**< Bit mask for SMU_LETIMER0 */ -#define _SMU_PPUSATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LETIMER0_DEFAULT (_SMU_PPUSATD1_LETIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_IADC0 (0x1UL << 10) /**< IADC0 Secure Access */ -#define _SMU_PPUSATD1_IADC0_SHIFT 10 /**< Shift value for SMU_IADC0 */ -#define _SMU_PPUSATD1_IADC0_MASK 0x400UL /**< Bit mask for SMU_IADC0 */ -#define _SMU_PPUSATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_IADC0_DEFAULT (_SMU_PPUSATD1_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_ACMP0 (0x1UL << 11) /**< ACMP0 Secure Access */ -#define _SMU_PPUSATD1_ACMP0_SHIFT 11 /**< Shift value for SMU_ACMP0 */ -#define _SMU_PPUSATD1_ACMP0_MASK 0x800UL /**< Bit mask for SMU_ACMP0 */ -#define _SMU_PPUSATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_ACMP0_DEFAULT (_SMU_PPUSATD1_ACMP0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_ACMP1 (0x1UL << 12) /**< ACMP1 Secure Access */ -#define _SMU_PPUSATD1_ACMP1_SHIFT 12 /**< Shift value for SMU_ACMP1 */ -#define _SMU_PPUSATD1_ACMP1_MASK 0x1000UL /**< Bit mask for SMU_ACMP1 */ -#define _SMU_PPUSATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_ACMP1_DEFAULT (_SMU_PPUSATD1_ACMP1_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_AMUXCP0 (0x1UL << 13) /**< AMUXCP0 Secure Access */ -#define _SMU_PPUSATD1_AMUXCP0_SHIFT 13 /**< Shift value for SMU_AMUXCP0 */ -#define _SMU_PPUSATD1_AMUXCP0_MASK 0x2000UL /**< Bit mask for SMU_AMUXCP0 */ -#define _SMU_PPUSATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_AMUXCP0_DEFAULT (_SMU_PPUSATD1_AMUXCP0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_VDAC0 (0x1UL << 14) /**< VDAC0 Secure Access */ -#define _SMU_PPUSATD1_VDAC0_SHIFT 14 /**< Shift value for SMU_VDAC0 */ -#define _SMU_PPUSATD1_VDAC0_MASK 0x4000UL /**< Bit mask for SMU_VDAC0 */ -#define _SMU_PPUSATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_VDAC0_DEFAULT (_SMU_PPUSATD1_VDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_PCNT (0x1UL << 15) /**< PCNT Secure Access */ -#define _SMU_PPUSATD1_PCNT_SHIFT 15 /**< Shift value for SMU_PCNT */ -#define _SMU_PPUSATD1_PCNT_MASK 0x8000UL /**< Bit mask for SMU_PCNT */ -#define _SMU_PPUSATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_PCNT_DEFAULT (_SMU_PPUSATD1_PCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LESENSE (0x1UL << 16) /**< LESENSE Secure Access */ -#define _SMU_PPUSATD1_LESENSE_SHIFT 16 /**< Shift value for SMU_LESENSE */ -#define _SMU_PPUSATD1_LESENSE_MASK 0x10000UL /**< Bit mask for SMU_LESENSE */ -#define _SMU_PPUSATD1_LESENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LESENSE_DEFAULT (_SMU_PPUSATD1_LESENSE_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_HFRCO1 (0x1UL << 17) /**< HFRCO1 Secure Access */ -#define _SMU_PPUSATD1_HFRCO1_SHIFT 17 /**< Shift value for SMU_HFRCO1 */ -#define _SMU_PPUSATD1_HFRCO1_MASK 0x20000UL /**< Bit mask for SMU_HFRCO1 */ -#define _SMU_PPUSATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_HFRCO1_DEFAULT (_SMU_PPUSATD1_HFRCO1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_HFXO0 (0x1UL << 18) /**< HFXO0 Secure Access */ -#define _SMU_PPUSATD1_HFXO0_SHIFT 18 /**< Shift value for SMU_HFXO0 */ -#define _SMU_PPUSATD1_HFXO0_MASK 0x40000UL /**< Bit mask for SMU_HFXO0 */ -#define _SMU_PPUSATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_HFXO0_DEFAULT (_SMU_PPUSATD1_HFXO0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_I2C0 (0x1UL << 19) /**< I2C0 Secure Access */ -#define _SMU_PPUSATD1_I2C0_SHIFT 19 /**< Shift value for SMU_I2C0 */ -#define _SMU_PPUSATD1_I2C0_MASK 0x80000UL /**< Bit mask for SMU_I2C0 */ -#define _SMU_PPUSATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_I2C0_DEFAULT (_SMU_PPUSATD1_I2C0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_WDOG0 (0x1UL << 20) /**< WDOG0 Secure Access */ -#define _SMU_PPUSATD1_WDOG0_SHIFT 20 /**< Shift value for SMU_WDOG0 */ -#define _SMU_PPUSATD1_WDOG0_MASK 0x100000UL /**< Bit mask for SMU_WDOG0 */ -#define _SMU_PPUSATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_WDOG0_DEFAULT (_SMU_PPUSATD1_WDOG0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_WDOG1 (0x1UL << 21) /**< WDOG1 Secure Access */ -#define _SMU_PPUSATD1_WDOG1_SHIFT 21 /**< Shift value for SMU_WDOG1 */ -#define _SMU_PPUSATD1_WDOG1_MASK 0x200000UL /**< Bit mask for SMU_WDOG1 */ -#define _SMU_PPUSATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_WDOG1_DEFAULT (_SMU_PPUSATD1_WDOG1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_EUSART0 (0x1UL << 22) /**< EUSART0 Secure Access */ -#define _SMU_PPUSATD1_EUSART0_SHIFT 22 /**< Shift value for SMU_EUSART0 */ -#define _SMU_PPUSATD1_EUSART0_MASK 0x400000UL /**< Bit mask for SMU_EUSART0 */ -#define _SMU_PPUSATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_EUSART0_DEFAULT (_SMU_PPUSATD1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SEMAILBOX (0x1UL << 23) /**< SEMAILBOX Secure Access */ -#define _SMU_PPUSATD1_SEMAILBOX_SHIFT 23 /**< Shift value for SMU_SEMAILBOX */ -#define _SMU_PPUSATD1_SEMAILBOX_MASK 0x800000UL /**< Bit mask for SMU_SEMAILBOX */ -#define _SMU_PPUSATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SEMAILBOX_DEFAULT (_SMU_PPUSATD1_SEMAILBOX_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_AHBRADIO (0x1UL << 25) /**< AHBRADIO Secure Access */ -#define _SMU_PPUSATD1_AHBRADIO_SHIFT 25 /**< Shift value for SMU_AHBRADIO */ -#define _SMU_PPUSATD1_AHBRADIO_MASK 0x2000000UL /**< Bit mask for SMU_AHBRADIO */ -#define _SMU_PPUSATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_AHBRADIO_DEFAULT (_SMU_PPUSATD1_AHBRADIO_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define _SMU_PPUSATD1_RESETVALUE 0x03FFFFFFUL /**< Default value for SMU_PPUSATD1 */ +#define _SMU_PPUSATD1_MASK 0x03FFFFFFUL /**< Mask for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SYSRTC (0x1UL << 0) /**< SYSRTC Secure Access */ +#define _SMU_PPUSATD1_SYSRTC_SHIFT 0 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUSATD1_SYSRTC_MASK 0x1UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUSATD1_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SYSRTC_DEFAULT (_SMU_PPUSATD1_SYSRTC_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LCD (0x1UL << 1) /**< LCD Secure Access */ +#define _SMU_PPUSATD1_LCD_SHIFT 1 /**< Shift value for SMU_LCD */ +#define _SMU_PPUSATD1_LCD_MASK 0x2UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUSATD1_LCD_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LCD_DEFAULT (_SMU_PPUSATD1_LCD_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_KEYSCAN (0x1UL << 2) /**< KEYSCAN Secure Access */ +#define _SMU_PPUSATD1_KEYSCAN_SHIFT 2 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUSATD1_KEYSCAN_MASK 0x4UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUSATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_KEYSCAN_DEFAULT (_SMU_PPUSATD1_KEYSCAN_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DMEM (0x1UL << 3) /**< DMEM Secure Access */ +#define _SMU_PPUSATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUSATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUSATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DMEM_DEFAULT (_SMU_PPUSATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LCDRF (0x1UL << 4) /**< LCDRF Secure Access */ +#define _SMU_PPUSATD1_LCDRF_SHIFT 4 /**< Shift value for SMU_LCDRF */ +#define _SMU_PPUSATD1_LCDRF_MASK 0x10UL /**< Bit mask for SMU_LCDRF */ +#define _SMU_PPUSATD1_LCDRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LCDRF_DEFAULT (_SMU_PPUSATD1_LCDRF_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PFMXPPRF (0x1UL << 5) /**< PFMXPPRF Secure Access */ +#define _SMU_PPUSATD1_PFMXPPRF_SHIFT 5 /**< Shift value for SMU_PFMXPPRF */ +#define _SMU_PPUSATD1_PFMXPPRF_MASK 0x20UL /**< Bit mask for SMU_PFMXPPRF */ +#define _SMU_PPUSATD1_PFMXPPRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PFMXPPRF_DEFAULT (_SMU_PPUSATD1_PFMXPPRF_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES (0x1UL << 6) /**< RADIOAES Secure Access */ +#define _SMU_PPUSATD1_RADIOAES_SHIFT 6 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_MASK 0x40UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES_DEFAULT (_SMU_PPUSATD1_RADIOAES_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU (0x1UL << 7) /**< SMU Secure Access */ +#define _SMU_PPUSATD1_SMU_SHIFT 7 /**< Shift value for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_MASK 0x80UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU_DEFAULT (_SMU_PPUSATD1_SMU_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS (0x1UL << 8) /**< SMUCFGNS Secure Access */ +#define _SMU_PPUSATD1_SMUCFGNS_SHIFT 8 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_MASK 0x100UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS_DEFAULT (_SMU_PPUSATD1_SMUCFGNS_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0 (0x1UL << 9) /**< LETIMER0 Secure Access */ +#define _SMU_PPUSATD1_LETIMER0_SHIFT 9 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_MASK 0x200UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0_DEFAULT (_SMU_PPUSATD1_LETIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0 (0x1UL << 10) /**< IADC0 Secure Access */ +#define _SMU_PPUSATD1_IADC0_SHIFT 10 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_MASK 0x400UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0_DEFAULT (_SMU_PPUSATD1_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP0 (0x1UL << 11) /**< ACMP0 Secure Access */ +#define _SMU_PPUSATD1_ACMP0_SHIFT 11 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUSATD1_ACMP0_MASK 0x800UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUSATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP0_DEFAULT (_SMU_PPUSATD1_ACMP0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP1 (0x1UL << 12) /**< ACMP1 Secure Access */ +#define _SMU_PPUSATD1_ACMP1_SHIFT 12 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUSATD1_ACMP1_MASK 0x1000UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUSATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP1_DEFAULT (_SMU_PPUSATD1_ACMP1_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0 (0x1UL << 13) /**< AMUXCP0 Secure Access */ +#define _SMU_PPUSATD1_AMUXCP0_SHIFT 13 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_MASK 0x2000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0_DEFAULT (_SMU_PPUSATD1_AMUXCP0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC0 (0x1UL << 14) /**< VDAC0 Secure Access */ +#define _SMU_PPUSATD1_VDAC0_SHIFT 14 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUSATD1_VDAC0_MASK 0x4000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUSATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC0_DEFAULT (_SMU_PPUSATD1_VDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PCNT (0x1UL << 15) /**< PCNT Secure Access */ +#define _SMU_PPUSATD1_PCNT_SHIFT 15 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUSATD1_PCNT_MASK 0x8000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUSATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PCNT_DEFAULT (_SMU_PPUSATD1_PCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LESENSE (0x1UL << 16) /**< LESENSE Secure Access */ +#define _SMU_PPUSATD1_LESENSE_SHIFT 16 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUSATD1_LESENSE_MASK 0x10000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUSATD1_LESENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LESENSE_DEFAULT (_SMU_PPUSATD1_LESENSE_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFRCO1 (0x1UL << 17) /**< HFRCO1 Secure Access */ +#define _SMU_PPUSATD1_HFRCO1_SHIFT 17 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUSATD1_HFRCO1_MASK 0x20000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUSATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFRCO1_DEFAULT (_SMU_PPUSATD1_HFRCO1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFXO0 (0x1UL << 18) /**< HFXO0 Secure Access */ +#define _SMU_PPUSATD1_HFXO0_SHIFT 18 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUSATD1_HFXO0_MASK 0x40000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUSATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFXO0_DEFAULT (_SMU_PPUSATD1_HFXO0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0 (0x1UL << 19) /**< I2C0 Secure Access */ +#define _SMU_PPUSATD1_I2C0_SHIFT 19 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_MASK 0x80000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0_DEFAULT (_SMU_PPUSATD1_I2C0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0 (0x1UL << 20) /**< WDOG0 Secure Access */ +#define _SMU_PPUSATD1_WDOG0_SHIFT 20 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_MASK 0x100000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0_DEFAULT (_SMU_PPUSATD1_WDOG0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG1 (0x1UL << 21) /**< WDOG1 Secure Access */ +#define _SMU_PPUSATD1_WDOG1_SHIFT 21 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUSATD1_WDOG1_MASK 0x200000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUSATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG1_DEFAULT (_SMU_PPUSATD1_WDOG1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART0 (0x1UL << 22) /**< EUSART0 Secure Access */ +#define _SMU_PPUSATD1_EUSART0_SHIFT 22 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUSATD1_EUSART0_MASK 0x400000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUSATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART0_DEFAULT (_SMU_PPUSATD1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SEMAILBOX (0x1UL << 23) /**< SEMAILBOX Secure Access */ +#define _SMU_PPUSATD1_SEMAILBOX_SHIFT 23 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUSATD1_SEMAILBOX_MASK 0x800000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUSATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SEMAILBOX_DEFAULT (_SMU_PPUSATD1_SEMAILBOX_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AHBRADIO (0x1UL << 25) /**< AHBRADIO Secure Access */ +#define _SMU_PPUSATD1_AHBRADIO_SHIFT 25 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUSATD1_AHBRADIO_MASK 0x2000000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUSATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AHBRADIO_DEFAULT (_SMU_PPUSATD1_AHBRADIO_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ /* Bit fields for SMU PPUFS */ -#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ -#define _SMU_PPUFS_MASK 0x000000FFUL /**< Mask for SMU_PPUFS */ -#define _SMU_PPUFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ -#define _SMU_PPUFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ -#define _SMU_PPUFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ -#define SMU_PPUFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x000000FFUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ /* Bit fields for SMU BMPUPATD0 */ -#define _SMU_BMPUPATD0_RESETVALUE 0x000001FFUL /**< Default value for SMU_BMPUPATD0 */ -#define _SMU_BMPUPATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ -#define _SMU_BMPUPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ -#define _SMU_BMPUPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_BMPUPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOAES_DEFAULT (_SMU_BMPUPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */ -#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */ -#define _SMU_BMPUPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ -#define _SMU_BMPUPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ -#define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_LDMA_DEFAULT (_SMU_BMPUPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RFECA0 (0x1UL << 6) /**< RFECA0 privileged mode */ -#define _SMU_BMPUPATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ -#define _SMU_BMPUPATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ -#define _SMU_BMPUPATD0_RFECA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RFECA0_DEFAULT (_SMU_BMPUPATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RFECA1 (0x1UL << 7) /**< RFECA1 privileged mode */ -#define _SMU_BMPUPATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ -#define _SMU_BMPUPATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ -#define _SMU_BMPUPATD0_RFECA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RFECA1_DEFAULT (_SMU_BMPUPATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA privileged mode */ -#define _SMU_BMPUPATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ -#define _SMU_BMPUPATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ -#define _SMU_BMPUPATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUPATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define _SMU_BMPUPATD0_RESETVALUE 0x000001FFUL /**< Default value for SMU_BMPUPATD0 */ +#define _SMU_BMPUPATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ +#define _SMU_BMPUPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES_DEFAULT (_SMU_BMPUPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */ +#define _SMU_BMPUPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA_DEFAULT (_SMU_BMPUPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA0 (0x1UL << 6) /**< RFECA0 privileged mode */ +#define _SMU_BMPUPATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUPATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUPATD0_RFECA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA0_DEFAULT (_SMU_BMPUPATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA1 (0x1UL << 7) /**< RFECA1 privileged mode */ +#define _SMU_BMPUPATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUPATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUPATD0_RFECA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA1_DEFAULT (_SMU_BMPUPATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA privileged mode */ +#define _SMU_BMPUPATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUPATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUPATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUPATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ /* Bit fields for SMU BMPUSATD0 */ -#define _SMU_BMPUSATD0_RESETVALUE 0x000001FFUL /**< Default value for SMU_BMPUSATD0 */ -#define _SMU_BMPUSATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOAES (0x1UL << 0) /**< RADIOAES DMA secure mode */ -#define _SMU_BMPUSATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ -#define _SMU_BMPUSATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_BMPUSATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOAES_DEFAULT (_SMU_BMPUSATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager secure mode */ -#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_LDMA (0x1UL << 2) /**< MCU LDMA secure mode */ -#define _SMU_BMPUSATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ -#define _SMU_BMPUSATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ -#define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_LDMA_DEFAULT (_SMU_BMPUSATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RFECA0 (0x1UL << 6) /**< RFECA0 secure mode */ -#define _SMU_BMPUSATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ -#define _SMU_BMPUSATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ -#define _SMU_BMPUSATD0_RFECA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RFECA0_DEFAULT (_SMU_BMPUSATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RFECA1 (0x1UL << 7) /**< RFECA1 secure mode */ -#define _SMU_BMPUSATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ -#define _SMU_BMPUSATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ -#define _SMU_BMPUSATD0_RFECA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RFECA1_DEFAULT (_SMU_BMPUSATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA secure mode */ -#define _SMU_BMPUSATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ -#define _SMU_BMPUSATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ -#define _SMU_BMPUSATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_SEEXTDMA_DEFAULT (_SMU_BMPUSATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define _SMU_BMPUSATD0_RESETVALUE 0x000001FFUL /**< Default value for SMU_BMPUSATD0 */ +#define _SMU_BMPUSATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES (0x1UL << 0) /**< RADIOAES DMA secure mode */ +#define _SMU_BMPUSATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES_DEFAULT (_SMU_BMPUSATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager secure mode */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA (0x1UL << 2) /**< MCU LDMA secure mode */ +#define _SMU_BMPUSATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA_DEFAULT (_SMU_BMPUSATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA0 (0x1UL << 6) /**< RFECA0 secure mode */ +#define _SMU_BMPUSATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUSATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUSATD0_RFECA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA0_DEFAULT (_SMU_BMPUSATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA1 (0x1UL << 7) /**< RFECA1 secure mode */ +#define _SMU_BMPUSATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUSATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUSATD0_RFECA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA1_DEFAULT (_SMU_BMPUSATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA secure mode */ +#define _SMU_BMPUSATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUSATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUSATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_SEEXTDMA_DEFAULT (_SMU_BMPUSATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ /* Bit fields for SMU BMPUFS */ -#define _SMU_BMPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFS */ -#define _SMU_BMPUFS_MASK 0x000000FFUL /**< Mask for SMU_BMPUFS */ -#define _SMU_BMPUFS_BMPUFSMASTERID_SHIFT 0 /**< Shift value for SMU_BMPUFSMASTERID */ -#define _SMU_BMPUFS_BMPUFSMASTERID_MASK 0xFFUL /**< Bit mask for SMU_BMPUFSMASTERID */ -#define _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFS */ -#define SMU_BMPUFS_BMPUFSMASTERID_DEFAULT (_SMU_BMPUFS_BMPUFSMASTERID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFS */ +#define _SMU_BMPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFS */ +#define _SMU_BMPUFS_MASK 0x000000FFUL /**< Mask for SMU_BMPUFS */ +#define _SMU_BMPUFS_BMPUFSMASTERID_SHIFT 0 /**< Shift value for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_MASK 0xFFUL /**< Bit mask for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFS */ +#define SMU_BMPUFS_BMPUFSMASTERID_DEFAULT (_SMU_BMPUFS_BMPUFSMASTERID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFS */ /* Bit fields for SMU BMPUFSADDR */ -#define _SMU_BMPUFSADDR_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFSADDR */ -#define _SMU_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Mask for SMU_BMPUFSADDR */ -#define _SMU_BMPUFSADDR_BMPUFSADDR_SHIFT 0 /**< Shift value for SMU_BMPUFSADDR */ -#define _SMU_BMPUFSADDR_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_BMPUFSADDR */ -#define _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFSADDR */ -#define SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT (_SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_SHIFT 0 /**< Shift value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFSADDR */ +#define SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT (_SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFSADDR */ /* Bit fields for SMU ESAURTYPES0 */ -#define _SMU_ESAURTYPES0_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES0 */ -#define _SMU_ESAURTYPES0_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES0 */ -#define SMU_ESAURTYPES0_ESAUR3NS (0x1UL << 12) /**< Region 3 Non-Secure */ -#define _SMU_ESAURTYPES0_ESAUR3NS_SHIFT 12 /**< Shift value for SMU_ESAUR3NS */ -#define _SMU_ESAURTYPES0_ESAUR3NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR3NS */ -#define _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES0 */ -#define SMU_ESAURTYPES0_ESAUR3NS_DEFAULT (_SMU_ESAURTYPES0_ESAUR3NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS (0x1UL << 12) /**< Region 3 Non-Secure */ +#define _SMU_ESAURTYPES0_ESAUR3NS_SHIFT 12 /**< Shift value for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS_DEFAULT (_SMU_ESAURTYPES0_ESAUR3NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES0 */ /* Bit fields for SMU ESAURTYPES1 */ -#define _SMU_ESAURTYPES1_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES1 */ -#define _SMU_ESAURTYPES1_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES1 */ -#define SMU_ESAURTYPES1_ESAUR11NS (0x1UL << 12) /**< Region 11 Non-Secure */ -#define _SMU_ESAURTYPES1_ESAUR11NS_SHIFT 12 /**< Shift value for SMU_ESAUR11NS */ -#define _SMU_ESAURTYPES1_ESAUR11NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR11NS */ -#define _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES1 */ -#define SMU_ESAURTYPES1_ESAUR11NS_DEFAULT (_SMU_ESAURTYPES1_ESAUR11NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS (0x1UL << 12) /**< Region 11 Non-Secure */ +#define _SMU_ESAURTYPES1_ESAUR11NS_SHIFT 12 /**< Shift value for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS_DEFAULT (_SMU_ESAURTYPES1_ESAUR11NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES1 */ /* Bit fields for SMU ESAUMRB01 */ -#define _SMU_ESAUMRB01_RESETVALUE 0x0A000000UL /**< Default value for SMU_ESAUMRB01 */ -#define _SMU_ESAUMRB01_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB01 */ -#define _SMU_ESAUMRB01_ESAUMRB01_SHIFT 12 /**< Shift value for SMU_ESAUMRB01 */ -#define _SMU_ESAUMRB01_ESAUMRB01_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB01 */ -#define _SMU_ESAUMRB01_ESAUMRB01_DEFAULT 0x0000A000UL /**< Mode DEFAULT for SMU_ESAUMRB01 */ -#define SMU_ESAUMRB01_ESAUMRB01_DEFAULT (_SMU_ESAUMRB01_ESAUMRB01_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_RESETVALUE 0x0A000000UL /**< Default value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_SHIFT 12 /**< Shift value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_DEFAULT 0x0000A000UL /**< Mode DEFAULT for SMU_ESAUMRB01 */ +#define SMU_ESAUMRB01_ESAUMRB01_DEFAULT (_SMU_ESAUMRB01_ESAUMRB01_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB01 */ /* Bit fields for SMU ESAUMRB12 */ -#define _SMU_ESAUMRB12_RESETVALUE 0x0C000000UL /**< Default value for SMU_ESAUMRB12 */ -#define _SMU_ESAUMRB12_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB12 */ -#define _SMU_ESAUMRB12_ESAUMRB12_SHIFT 12 /**< Shift value for SMU_ESAUMRB12 */ -#define _SMU_ESAUMRB12_ESAUMRB12_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB12 */ -#define _SMU_ESAUMRB12_ESAUMRB12_DEFAULT 0x0000C000UL /**< Mode DEFAULT for SMU_ESAUMRB12 */ -#define SMU_ESAUMRB12_ESAUMRB12_DEFAULT (_SMU_ESAUMRB12_ESAUMRB12_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_RESETVALUE 0x0C000000UL /**< Default value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_SHIFT 12 /**< Shift value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_DEFAULT 0x0000C000UL /**< Mode DEFAULT for SMU_ESAUMRB12 */ +#define SMU_ESAUMRB12_ESAUMRB12_DEFAULT (_SMU_ESAUMRB12_ESAUMRB12_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB12 */ /* Bit fields for SMU ESAUMRB45 */ -#define _SMU_ESAUMRB45_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB45 */ -#define _SMU_ESAUMRB45_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB45 */ -#define _SMU_ESAUMRB45_ESAUMRB45_SHIFT 12 /**< Shift value for SMU_ESAUMRB45 */ -#define _SMU_ESAUMRB45_ESAUMRB45_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB45 */ -#define _SMU_ESAUMRB45_ESAUMRB45_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB45 */ -#define SMU_ESAUMRB45_ESAUMRB45_DEFAULT (_SMU_ESAUMRB45_ESAUMRB45_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_SHIFT 12 /**< Shift value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB45 */ +#define SMU_ESAUMRB45_ESAUMRB45_DEFAULT (_SMU_ESAUMRB45_ESAUMRB45_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB45 */ /* Bit fields for SMU ESAUMRB56 */ -#define _SMU_ESAUMRB56_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB56 */ -#define _SMU_ESAUMRB56_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB56 */ -#define _SMU_ESAUMRB56_ESAUMRB56_SHIFT 12 /**< Shift value for SMU_ESAUMRB56 */ -#define _SMU_ESAUMRB56_ESAUMRB56_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB56 */ -#define _SMU_ESAUMRB56_ESAUMRB56_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB56 */ -#define SMU_ESAUMRB56_ESAUMRB56_DEFAULT (_SMU_ESAUMRB56_ESAUMRB56_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_SHIFT 12 /**< Shift value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB56 */ +#define SMU_ESAUMRB56_ESAUMRB56_DEFAULT (_SMU_ESAUMRB56_ESAUMRB56_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB56 */ /** @} End of group EFR32SG28_SMU_BitFields */ /** @} End of group EFR32SG28_SMU */ @@ -1012,67 +1010,66 @@ typedef struct *****************************************************************************/ /** SMU_CFGNS Register Declaration. */ -typedef struct -{ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t NSSTATUS; /**< Status Register */ - __IOM uint32_t NSLOCK; /**< Lock Register */ - __IOM uint32_t NSIF; /**< Interrupt Flag Register */ - __IOM uint32_t NSIEN; /**< Interrupt Enable Register */ - uint32_t RESERVED1[3U]; /**< Reserved for future use */ - uint32_t RESERVED2[8U]; /**< Reserved for future use */ - __IOM uint32_t PPUNSPATD0; /**< Privileged Access */ - __IOM uint32_t PPUNSPATD1; /**< Privileged Access */ - uint32_t RESERVED3[62U]; /**< Reserved for future use */ - __IM uint32_t PPUNSFS; /**< Fault Status */ - uint32_t RESERVED4[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUNSPATD0; /**< Privileged Attribute */ - uint32_t RESERVED5[63U]; /**< Reserved for future use */ - uint32_t RESERVED6[876U]; /**< Reserved for future use */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - __IM uint32_t NSSTATUS_SET; /**< Status Register */ - __IOM uint32_t NSLOCK_SET; /**< Lock Register */ - __IOM uint32_t NSIF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t NSIEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED8[3U]; /**< Reserved for future use */ - uint32_t RESERVED9[8U]; /**< Reserved for future use */ - __IOM uint32_t PPUNSPATD0_SET; /**< Privileged Access */ - __IOM uint32_t PPUNSPATD1_SET; /**< Privileged Access */ - uint32_t RESERVED10[62U]; /**< Reserved for future use */ - __IM uint32_t PPUNSFS_SET; /**< Fault Status */ - uint32_t RESERVED11[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUNSPATD0_SET; /**< Privileged Attribute */ - uint32_t RESERVED12[63U]; /**< Reserved for future use */ - uint32_t RESERVED13[876U]; /**< Reserved for future use */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - __IM uint32_t NSSTATUS_CLR; /**< Status Register */ - __IOM uint32_t NSLOCK_CLR; /**< Lock Register */ - __IOM uint32_t NSIF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t NSIEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED15[3U]; /**< Reserved for future use */ - uint32_t RESERVED16[8U]; /**< Reserved for future use */ - __IOM uint32_t PPUNSPATD0_CLR; /**< Privileged Access */ - __IOM uint32_t PPUNSPATD1_CLR; /**< Privileged Access */ - uint32_t RESERVED17[62U]; /**< Reserved for future use */ - __IM uint32_t PPUNSFS_CLR; /**< Fault Status */ - uint32_t RESERVED18[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUNSPATD0_CLR; /**< Privileged Attribute */ - uint32_t RESERVED19[63U]; /**< Reserved for future use */ - uint32_t RESERVED20[876U]; /**< Reserved for future use */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - __IM uint32_t NSSTATUS_TGL; /**< Status Register */ - __IOM uint32_t NSLOCK_TGL; /**< Lock Register */ - __IOM uint32_t NSIF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t NSIEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED22[3U]; /**< Reserved for future use */ - uint32_t RESERVED23[8U]; /**< Reserved for future use */ - __IOM uint32_t PPUNSPATD0_TGL; /**< Privileged Access */ - __IOM uint32_t PPUNSPATD1_TGL; /**< Privileged Access */ - uint32_t RESERVED24[62U]; /**< Reserved for future use */ - __IM uint32_t PPUNSFS_TGL; /**< Fault Status */ - uint32_t RESERVED25[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUNSPATD0_TGL; /**< Privileged Attribute */ - uint32_t RESERVED26[63U]; /**< Reserved for future use */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS; /**< Status Register */ + __IOM uint32_t NSLOCK; /**< Lock Register */ + __IOM uint32_t NSIF; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN; /**< Interrupt Enable Register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1; /**< Privileged Access */ + uint32_t RESERVED3[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS; /**< Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0; /**< Privileged Attribute */ + uint32_t RESERVED5[63U]; /**< Reserved for future use */ + uint32_t RESERVED6[876U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_SET; /**< Status Register */ + __IOM uint32_t NSLOCK_SET; /**< Lock Register */ + __IOM uint32_t NSIF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED8[3U]; /**< Reserved for future use */ + uint32_t RESERVED9[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_SET; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_SET; /**< Privileged Access */ + uint32_t RESERVED10[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_SET; /**< Fault Status */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_SET; /**< Privileged Attribute */ + uint32_t RESERVED12[63U]; /**< Reserved for future use */ + uint32_t RESERVED13[876U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_CLR; /**< Status Register */ + __IOM uint32_t NSLOCK_CLR; /**< Lock Register */ + __IOM uint32_t NSIF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + uint32_t RESERVED16[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_CLR; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_CLR; /**< Privileged Access */ + uint32_t RESERVED17[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_CLR; /**< Fault Status */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_CLR; /**< Privileged Attribute */ + uint32_t RESERVED19[63U]; /**< Reserved for future use */ + uint32_t RESERVED20[876U]; /**< Reserved for future use */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_TGL; /**< Status Register */ + __IOM uint32_t NSLOCK_TGL; /**< Lock Register */ + __IOM uint32_t NSIF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + uint32_t RESERVED23[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_TGL; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_TGL; /**< Privileged Access */ + uint32_t RESERVED24[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_TGL; /**< Fault Status */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_TGL; /**< Privileged Attribute */ + uint32_t RESERVED26[63U]; /**< Reserved for future use */ } SMU_CFGNS_TypeDef; /** @} End of group EFR32SG28_SMU_CFGNS */ @@ -1084,385 +1081,385 @@ typedef struct *****************************************************************************/ /* Bit fields for SMU NSSTATUS */ -#define _SMU_NSSTATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_NSSTATUS */ -#define _SMU_NSSTATUS_MASK 0x00000001UL /**< Mask for SMU_NSSTATUS */ -#define SMU_NSSTATUS_SMUNSLOCK (0x1UL << 0) /**< SMUNS Lock */ -#define _SMU_NSSTATUS_SMUNSLOCK_SHIFT 0 /**< Shift value for SMU_SMUNSLOCK */ -#define _SMU_NSSTATUS_SMUNSLOCK_MASK 0x1UL /**< Bit mask for SMU_SMUNSLOCK */ -#define _SMU_NSSTATUS_SMUNSLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSSTATUS */ -#define _SMU_NSSTATUS_SMUNSLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_NSSTATUS */ -#define _SMU_NSSTATUS_SMUNSLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_NSSTATUS */ -#define SMU_NSSTATUS_SMUNSLOCK_DEFAULT (_SMU_NSSTATUS_SMUNSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSSTATUS */ -#define SMU_NSSTATUS_SMUNSLOCK_UNLOCKED (_SMU_NSSTATUS_SMUNSLOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_NSSTATUS */ -#define SMU_NSSTATUS_SMUNSLOCK_LOCKED (_SMU_NSSTATUS_SMUNSLOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_MASK 0x00000001UL /**< Mask for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK (0x1UL << 0) /**< SMUNS Lock */ +#define _SMU_NSSTATUS_SMUNSLOCK_SHIFT 0 /**< Shift value for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_MASK 0x1UL /**< Bit mask for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_DEFAULT (_SMU_NSSTATUS_SMUNSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_UNLOCKED (_SMU_NSSTATUS_SMUNSLOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_LOCKED (_SMU_NSSTATUS_SMUNSLOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_NSSTATUS */ /* Bit fields for SMU NSLOCK */ -#define _SMU_NSLOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_NSLOCK */ -#define _SMU_NSLOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_NSLOCK */ -#define _SMU_NSLOCK_SMUNSLOCKKEY_SHIFT 0 /**< Shift value for SMU_SMUNSLOCKKEY */ -#define _SMU_NSLOCK_SMUNSLOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMUNSLOCKKEY */ -#define _SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSLOCK */ -#define _SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_NSLOCK */ -#define SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT (_SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSLOCK */ -#define SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK (_SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_NSLOCK */ +#define _SMU_NSLOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_NSLOCK */ +#define _SMU_NSLOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_SHIFT 0 /**< Shift value for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT (_SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK (_SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_NSLOCK */ /* Bit fields for SMU NSIF */ -#define _SMU_NSIF_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIF */ -#define _SMU_NSIF_MASK 0x00000005UL /**< Mask for SMU_NSIF */ -#define SMU_NSIF_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Flag */ -#define _SMU_NSIF_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ -#define _SMU_NSIF_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ -#define _SMU_NSIF_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ -#define SMU_NSIF_PPUNSPRIV_DEFAULT (_SMU_NSIF_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIF */ -#define SMU_NSIF_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Flag */ -#define _SMU_NSIF_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ -#define _SMU_NSIF_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ -#define _SMU_NSIF_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ -#define SMU_NSIF_PPUNSINST_DEFAULT (_SMU_NSIF_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIF */ +#define _SMU_NSIF_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIF */ +#define _SMU_NSIF_MASK 0x00000005UL /**< Mask for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Flag */ +#define _SMU_NSIF_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV_DEFAULT (_SMU_NSIF_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Flag */ +#define _SMU_NSIF_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST_DEFAULT (_SMU_NSIF_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIF */ /* Bit fields for SMU NSIEN */ -#define _SMU_NSIEN_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIEN */ -#define _SMU_NSIEN_MASK 0x00000005UL /**< Mask for SMU_NSIEN */ -#define SMU_NSIEN_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Enable */ -#define _SMU_NSIEN_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ -#define _SMU_NSIEN_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ -#define _SMU_NSIEN_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ -#define SMU_NSIEN_PPUNSPRIV_DEFAULT (_SMU_NSIEN_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIEN */ -#define SMU_NSIEN_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Enable */ -#define _SMU_NSIEN_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ -#define _SMU_NSIEN_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ -#define _SMU_NSIEN_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ -#define SMU_NSIEN_PPUNSINST_DEFAULT (_SMU_NSIEN_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIEN */ +#define _SMU_NSIEN_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIEN */ +#define _SMU_NSIEN_MASK 0x00000005UL /**< Mask for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Enable */ +#define _SMU_NSIEN_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV_DEFAULT (_SMU_NSIEN_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Enable */ +#define _SMU_NSIEN_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST_DEFAULT (_SMU_NSIEN_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIEN */ /* Bit fields for SMU PPUNSPATD0 */ -#define _SMU_PPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD0 */ -#define _SMU_PPUNSPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SCRATCHPAD (0x1UL << 0) /**< SCRATCHPAD Privileged Access */ -#define _SMU_PPUNSPATD0_SCRATCHPAD_SHIFT 0 /**< Shift value for SMU_SCRATCHPAD */ -#define _SMU_PPUNSPATD0_SCRATCHPAD_MASK 0x1UL /**< Bit mask for SMU_SCRATCHPAD */ -#define _SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT (_SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ -#define _SMU_PPUNSPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ -#define _SMU_PPUNSPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ -#define _SMU_PPUNSPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EMU_DEFAULT (_SMU_PPUNSPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ -#define _SMU_PPUNSPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ -#define _SMU_PPUNSPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ -#define _SMU_PPUNSPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_CMU_DEFAULT (_SMU_PPUNSPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */ -#define _SMU_PPUNSPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ -#define _SMU_PPUNSPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ -#define _SMU_PPUNSPATD0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_HFRCO0_DEFAULT (_SMU_PPUNSPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */ -#define _SMU_PPUNSPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ -#define _SMU_PPUNSPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ -#define _SMU_PPUNSPATD0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_FSRCO_DEFAULT (_SMU_PPUNSPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */ -#define _SMU_PPUNSPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ -#define _SMU_PPUNSPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ -#define _SMU_PPUNSPATD0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_DPLL0_DEFAULT (_SMU_PPUNSPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */ -#define _SMU_PPUNSPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ -#define _SMU_PPUNSPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ -#define _SMU_PPUNSPATD0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LFXO_DEFAULT (_SMU_PPUNSPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */ -#define _SMU_PPUNSPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ -#define _SMU_PPUNSPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ -#define _SMU_PPUNSPATD0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LFRCO_DEFAULT (_SMU_PPUNSPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */ -#define _SMU_PPUNSPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ -#define _SMU_PPUNSPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ -#define _SMU_PPUNSPATD0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_ULFRCO_DEFAULT (_SMU_PPUNSPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */ -#define _SMU_PPUNSPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ -#define _SMU_PPUNSPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ -#define _SMU_PPUNSPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_MSC_DEFAULT (_SMU_PPUNSPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */ -#define _SMU_PPUNSPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ -#define _SMU_PPUNSPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ -#define _SMU_PPUNSPATD0_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_ICACHE0_DEFAULT (_SMU_PPUNSPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */ -#define _SMU_PPUNSPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ -#define _SMU_PPUNSPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ -#define _SMU_PPUNSPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_PRS_DEFAULT (_SMU_PPUNSPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */ -#define _SMU_PPUNSPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ -#define _SMU_PPUNSPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ -#define _SMU_PPUNSPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_GPIO_DEFAULT (_SMU_PPUNSPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */ -#define _SMU_PPUNSPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ -#define _SMU_PPUNSPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ -#define _SMU_PPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LDMA_DEFAULT (_SMU_PPUNSPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */ -#define _SMU_PPUNSPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ -#define _SMU_PPUNSPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ -#define _SMU_PPUNSPATD0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LDMAXBAR_DEFAULT (_SMU_PPUNSPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ -#define _SMU_PPUNSPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ -#define _SMU_PPUNSPATD0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER0_DEFAULT (_SMU_PPUNSPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ -#define _SMU_PPUNSPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ -#define _SMU_PPUNSPATD0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER1_DEFAULT (_SMU_PPUNSPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ -#define _SMU_PPUNSPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ -#define _SMU_PPUNSPATD0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER2_DEFAULT (_SMU_PPUNSPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ -#define _SMU_PPUNSPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ -#define _SMU_PPUNSPATD0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER3_DEFAULT (_SMU_PPUNSPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ -#define _SMU_PPUNSPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ -#define _SMU_PPUNSPATD0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER4_DEFAULT (_SMU_PPUNSPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */ -#define _SMU_PPUNSPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ -#define _SMU_PPUNSPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ -#define _SMU_PPUNSPATD0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_USART0_DEFAULT (_SMU_PPUNSPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */ -#define _SMU_PPUNSPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ -#define _SMU_PPUNSPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ -#define _SMU_PPUNSPATD0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_BURTC_DEFAULT (_SMU_PPUNSPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */ -#define _SMU_PPUNSPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ -#define _SMU_PPUNSPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ -#define _SMU_PPUNSPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_I2C1_DEFAULT (_SMU_PPUNSPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */ -#define _SMU_PPUNSPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ -#define _SMU_PPUNSPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ -#define _SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */ -#define _SMU_PPUNSPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ -#define _SMU_PPUNSPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ -#define _SMU_PPUNSPATD0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSCFG_DEFAULT (_SMU_PPUNSPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */ -#define _SMU_PPUNSPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ -#define _SMU_PPUNSPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ -#define _SMU_PPUNSPATD0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_BURAM_DEFAULT (_SMU_PPUNSPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */ -#define _SMU_PPUNSPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ -#define _SMU_PPUNSPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ -#define _SMU_PPUNSPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_GPCRC_DEFAULT (_SMU_PPUNSPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */ -#define _SMU_PPUNSPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ -#define _SMU_PPUNSPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ -#define _SMU_PPUNSPATD0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_DCDC_DEFAULT (_SMU_PPUNSPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */ -#define _SMU_PPUNSPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ -#define _SMU_PPUNSPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ -#define _SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */ -#define _SMU_PPUNSPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ -#define _SMU_PPUNSPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ -#define _SMU_PPUNSPATD0_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EUSART1_DEFAULT (_SMU_PPUNSPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EUSART2 (0x1UL << 31) /**< EUSART2 Privileged Access */ -#define _SMU_PPUNSPATD0_EUSART2_SHIFT 31 /**< Shift value for SMU_EUSART2 */ -#define _SMU_PPUNSPATD0_EUSART2_MASK 0x80000000UL /**< Bit mask for SMU_EUSART2 */ -#define _SMU_PPUNSPATD0_EUSART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EUSART2_DEFAULT (_SMU_PPUNSPATD0_EUSART2_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SCRATCHPAD (0x1UL << 0) /**< SCRATCHPAD Privileged Access */ +#define _SMU_PPUNSPATD0_SCRATCHPAD_SHIFT 0 /**< Shift value for SMU_SCRATCHPAD */ +#define _SMU_PPUNSPATD0_SCRATCHPAD_MASK 0x1UL /**< Bit mask for SMU_SCRATCHPAD */ +#define _SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT (_SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUNSPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU_DEFAULT (_SMU_PPUNSPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUNSPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU_DEFAULT (_SMU_PPUNSPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUNSPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0_DEFAULT (_SMU_PPUNSPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */ +#define _SMU_PPUNSPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO_DEFAULT (_SMU_PPUNSPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */ +#define _SMU_PPUNSPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0_DEFAULT (_SMU_PPUNSPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */ +#define _SMU_PPUNSPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO_DEFAULT (_SMU_PPUNSPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO_DEFAULT (_SMU_PPUNSPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO_DEFAULT (_SMU_PPUNSPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */ +#define _SMU_PPUNSPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC_DEFAULT (_SMU_PPUNSPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUNSPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0_DEFAULT (_SMU_PPUNSPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */ +#define _SMU_PPUNSPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS_DEFAULT (_SMU_PPUNSPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */ +#define _SMU_PPUNSPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO_DEFAULT (_SMU_PPUNSPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */ +#define _SMU_PPUNSPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA_DEFAULT (_SMU_PPUNSPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUNSPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR_DEFAULT (_SMU_PPUNSPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0_DEFAULT (_SMU_PPUNSPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1_DEFAULT (_SMU_PPUNSPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2_DEFAULT (_SMU_PPUNSPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3_DEFAULT (_SMU_PPUNSPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4_DEFAULT (_SMU_PPUNSPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */ +#define _SMU_PPUNSPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUNSPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUNSPATD0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART0_DEFAULT (_SMU_PPUNSPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */ +#define _SMU_PPUNSPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC_DEFAULT (_SMU_PPUNSPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */ +#define _SMU_PPUNSPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUNSPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUNSPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_I2C1_DEFAULT (_SMU_PPUNSPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG_DEFAULT (_SMU_PPUNSPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */ +#define _SMU_PPUNSPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUNSPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUNSPATD0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURAM_DEFAULT (_SMU_PPUNSPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */ +#define _SMU_PPUNSPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUNSPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUNSPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPCRC_DEFAULT (_SMU_PPUNSPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */ +#define _SMU_PPUNSPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUNSPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUNSPATD0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DCDC_DEFAULT (_SMU_PPUNSPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */ +#define _SMU_PPUNSPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUNSPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */ +#define _SMU_PPUNSPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUNSPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUNSPATD0_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EUSART1_DEFAULT (_SMU_PPUNSPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EUSART2 (0x1UL << 31) /**< EUSART2 Privileged Access */ +#define _SMU_PPUNSPATD0_EUSART2_SHIFT 31 /**< Shift value for SMU_EUSART2 */ +#define _SMU_PPUNSPATD0_EUSART2_MASK 0x80000000UL /**< Bit mask for SMU_EUSART2 */ +#define _SMU_PPUNSPATD0_EUSART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EUSART2_DEFAULT (_SMU_PPUNSPATD0_EUSART2_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ /* Bit fields for SMU PPUNSPATD1 */ -#define _SMU_PPUNSPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD1 */ -#define _SMU_PPUNSPATD1_MASK 0x03FFFFFFUL /**< Mask for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SYSRTC (0x1UL << 0) /**< SYSRTC Privileged Access */ -#define _SMU_PPUNSPATD1_SYSRTC_SHIFT 0 /**< Shift value for SMU_SYSRTC */ -#define _SMU_PPUNSPATD1_SYSRTC_MASK 0x1UL /**< Bit mask for SMU_SYSRTC */ -#define _SMU_PPUNSPATD1_SYSRTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SYSRTC_DEFAULT (_SMU_PPUNSPATD1_SYSRTC_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LCD (0x1UL << 1) /**< LCD Privileged Access */ -#define _SMU_PPUNSPATD1_LCD_SHIFT 1 /**< Shift value for SMU_LCD */ -#define _SMU_PPUNSPATD1_LCD_MASK 0x2UL /**< Bit mask for SMU_LCD */ -#define _SMU_PPUNSPATD1_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LCD_DEFAULT (_SMU_PPUNSPATD1_LCD_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_KEYSCAN (0x1UL << 2) /**< KEYSCAN Privileged Access */ -#define _SMU_PPUNSPATD1_KEYSCAN_SHIFT 2 /**< Shift value for SMU_KEYSCAN */ -#define _SMU_PPUNSPATD1_KEYSCAN_MASK 0x4UL /**< Bit mask for SMU_KEYSCAN */ -#define _SMU_PPUNSPATD1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_KEYSCAN_DEFAULT (_SMU_PPUNSPATD1_KEYSCAN_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_DMEM (0x1UL << 3) /**< DMEM Privileged Access */ -#define _SMU_PPUNSPATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ -#define _SMU_PPUNSPATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ -#define _SMU_PPUNSPATD1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_DMEM_DEFAULT (_SMU_PPUNSPATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LCDRF (0x1UL << 4) /**< LCDRF Privileged Access */ -#define _SMU_PPUNSPATD1_LCDRF_SHIFT 4 /**< Shift value for SMU_LCDRF */ -#define _SMU_PPUNSPATD1_LCDRF_MASK 0x10UL /**< Bit mask for SMU_LCDRF */ -#define _SMU_PPUNSPATD1_LCDRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LCDRF_DEFAULT (_SMU_PPUNSPATD1_LCDRF_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_PFMXPPRF (0x1UL << 5) /**< PFMXPPRF Privileged Access */ -#define _SMU_PPUNSPATD1_PFMXPPRF_SHIFT 5 /**< Shift value for SMU_PFMXPPRF */ -#define _SMU_PPUNSPATD1_PFMXPPRF_MASK 0x20UL /**< Bit mask for SMU_PFMXPPRF */ -#define _SMU_PPUNSPATD1_PFMXPPRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_PFMXPPRF_DEFAULT (_SMU_PPUNSPATD1_PFMXPPRF_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_RADIOAES (0x1UL << 6) /**< RADIOAES Privileged Access */ -#define _SMU_PPUNSPATD1_RADIOAES_SHIFT 6 /**< Shift value for SMU_RADIOAES */ -#define _SMU_PPUNSPATD1_RADIOAES_MASK 0x40UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_PPUNSPATD1_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_RADIOAES_DEFAULT (_SMU_PPUNSPATD1_RADIOAES_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SMU (0x1UL << 7) /**< SMU Privileged Access */ -#define _SMU_PPUNSPATD1_SMU_SHIFT 7 /**< Shift value for SMU_SMU */ -#define _SMU_PPUNSPATD1_SMU_MASK 0x80UL /**< Bit mask for SMU_SMU */ -#define _SMU_PPUNSPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SMU_DEFAULT (_SMU_PPUNSPATD1_SMU_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SMUCFGNS (0x1UL << 8) /**< SMUCFGNS Privileged Access */ -#define _SMU_PPUNSPATD1_SMUCFGNS_SHIFT 8 /**< Shift value for SMU_SMUCFGNS */ -#define _SMU_PPUNSPATD1_SMUCFGNS_MASK 0x100UL /**< Bit mask for SMU_SMUCFGNS */ -#define _SMU_PPUNSPATD1_SMUCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SMUCFGNS_DEFAULT (_SMU_PPUNSPATD1_SMUCFGNS_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LETIMER0 (0x1UL << 9) /**< LETIMER0 Privileged Access */ -#define _SMU_PPUNSPATD1_LETIMER0_SHIFT 9 /**< Shift value for SMU_LETIMER0 */ -#define _SMU_PPUNSPATD1_LETIMER0_MASK 0x200UL /**< Bit mask for SMU_LETIMER0 */ -#define _SMU_PPUNSPATD1_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LETIMER0_DEFAULT (_SMU_PPUNSPATD1_LETIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_IADC0 (0x1UL << 10) /**< IADC0 Privileged Access */ -#define _SMU_PPUNSPATD1_IADC0_SHIFT 10 /**< Shift value for SMU_IADC0 */ -#define _SMU_PPUNSPATD1_IADC0_MASK 0x400UL /**< Bit mask for SMU_IADC0 */ -#define _SMU_PPUNSPATD1_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_IADC0_DEFAULT (_SMU_PPUNSPATD1_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_ACMP0 (0x1UL << 11) /**< ACMP0 Privileged Access */ -#define _SMU_PPUNSPATD1_ACMP0_SHIFT 11 /**< Shift value for SMU_ACMP0 */ -#define _SMU_PPUNSPATD1_ACMP0_MASK 0x800UL /**< Bit mask for SMU_ACMP0 */ -#define _SMU_PPUNSPATD1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_ACMP0_DEFAULT (_SMU_PPUNSPATD1_ACMP0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_ACMP1 (0x1UL << 12) /**< ACMP1 Privileged Access */ -#define _SMU_PPUNSPATD1_ACMP1_SHIFT 12 /**< Shift value for SMU_ACMP1 */ -#define _SMU_PPUNSPATD1_ACMP1_MASK 0x1000UL /**< Bit mask for SMU_ACMP1 */ -#define _SMU_PPUNSPATD1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_ACMP1_DEFAULT (_SMU_PPUNSPATD1_ACMP1_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_AMUXCP0 (0x1UL << 13) /**< AMUXCP0 Privileged Access */ -#define _SMU_PPUNSPATD1_AMUXCP0_SHIFT 13 /**< Shift value for SMU_AMUXCP0 */ -#define _SMU_PPUNSPATD1_AMUXCP0_MASK 0x2000UL /**< Bit mask for SMU_AMUXCP0 */ -#define _SMU_PPUNSPATD1_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_AMUXCP0_DEFAULT (_SMU_PPUNSPATD1_AMUXCP0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_VDAC0 (0x1UL << 14) /**< VDAC0 Privileged Access */ -#define _SMU_PPUNSPATD1_VDAC0_SHIFT 14 /**< Shift value for SMU_VDAC0 */ -#define _SMU_PPUNSPATD1_VDAC0_MASK 0x4000UL /**< Bit mask for SMU_VDAC0 */ -#define _SMU_PPUNSPATD1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_VDAC0_DEFAULT (_SMU_PPUNSPATD1_VDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_PCNT (0x1UL << 15) /**< PCNT Privileged Access */ -#define _SMU_PPUNSPATD1_PCNT_SHIFT 15 /**< Shift value for SMU_PCNT */ -#define _SMU_PPUNSPATD1_PCNT_MASK 0x8000UL /**< Bit mask for SMU_PCNT */ -#define _SMU_PPUNSPATD1_PCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_PCNT_DEFAULT (_SMU_PPUNSPATD1_PCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LESENSE (0x1UL << 16) /**< LESENSE Privileged Access */ -#define _SMU_PPUNSPATD1_LESENSE_SHIFT 16 /**< Shift value for SMU_LESENSE */ -#define _SMU_PPUNSPATD1_LESENSE_MASK 0x10000UL /**< Bit mask for SMU_LESENSE */ -#define _SMU_PPUNSPATD1_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LESENSE_DEFAULT (_SMU_PPUNSPATD1_LESENSE_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_HFRCO1 (0x1UL << 17) /**< HFRCO1 Privileged Access */ -#define _SMU_PPUNSPATD1_HFRCO1_SHIFT 17 /**< Shift value for SMU_HFRCO1 */ -#define _SMU_PPUNSPATD1_HFRCO1_MASK 0x20000UL /**< Bit mask for SMU_HFRCO1 */ -#define _SMU_PPUNSPATD1_HFRCO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_HFRCO1_DEFAULT (_SMU_PPUNSPATD1_HFRCO1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_HFXO0 (0x1UL << 18) /**< HFXO0 Privileged Access */ -#define _SMU_PPUNSPATD1_HFXO0_SHIFT 18 /**< Shift value for SMU_HFXO0 */ -#define _SMU_PPUNSPATD1_HFXO0_MASK 0x40000UL /**< Bit mask for SMU_HFXO0 */ -#define _SMU_PPUNSPATD1_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_HFXO0_DEFAULT (_SMU_PPUNSPATD1_HFXO0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_I2C0 (0x1UL << 19) /**< I2C0 Privileged Access */ -#define _SMU_PPUNSPATD1_I2C0_SHIFT 19 /**< Shift value for SMU_I2C0 */ -#define _SMU_PPUNSPATD1_I2C0_MASK 0x80000UL /**< Bit mask for SMU_I2C0 */ -#define _SMU_PPUNSPATD1_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_I2C0_DEFAULT (_SMU_PPUNSPATD1_I2C0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_WDOG0 (0x1UL << 20) /**< WDOG0 Privileged Access */ -#define _SMU_PPUNSPATD1_WDOG0_SHIFT 20 /**< Shift value for SMU_WDOG0 */ -#define _SMU_PPUNSPATD1_WDOG0_MASK 0x100000UL /**< Bit mask for SMU_WDOG0 */ -#define _SMU_PPUNSPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_WDOG0_DEFAULT (_SMU_PPUNSPATD1_WDOG0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_WDOG1 (0x1UL << 21) /**< WDOG1 Privileged Access */ -#define _SMU_PPUNSPATD1_WDOG1_SHIFT 21 /**< Shift value for SMU_WDOG1 */ -#define _SMU_PPUNSPATD1_WDOG1_MASK 0x200000UL /**< Bit mask for SMU_WDOG1 */ -#define _SMU_PPUNSPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_WDOG1_DEFAULT (_SMU_PPUNSPATD1_WDOG1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_EUSART0 (0x1UL << 22) /**< EUSART0 Privileged Access */ -#define _SMU_PPUNSPATD1_EUSART0_SHIFT 22 /**< Shift value for SMU_EUSART0 */ -#define _SMU_PPUNSPATD1_EUSART0_MASK 0x400000UL /**< Bit mask for SMU_EUSART0 */ -#define _SMU_PPUNSPATD1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_EUSART0_DEFAULT (_SMU_PPUNSPATD1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SEMAILBOX (0x1UL << 23) /**< SEMAILBOX Privileged Access */ -#define _SMU_PPUNSPATD1_SEMAILBOX_SHIFT 23 /**< Shift value for SMU_SEMAILBOX */ -#define _SMU_PPUNSPATD1_SEMAILBOX_MASK 0x800000UL /**< Bit mask for SMU_SEMAILBOX */ -#define _SMU_PPUNSPATD1_SEMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SEMAILBOX_DEFAULT (_SMU_PPUNSPATD1_SEMAILBOX_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_AHBRADIO (0x1UL << 25) /**< AHBRADIO Privileged Access */ -#define _SMU_PPUNSPATD1_AHBRADIO_SHIFT 25 /**< Shift value for SMU_AHBRADIO */ -#define _SMU_PPUNSPATD1_AHBRADIO_MASK 0x2000000UL /**< Bit mask for SMU_AHBRADIO */ -#define _SMU_PPUNSPATD1_AHBRADIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_AHBRADIO_DEFAULT (_SMU_PPUNSPATD1_AHBRADIO_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_MASK 0x03FFFFFFUL /**< Mask for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SYSRTC (0x1UL << 0) /**< SYSRTC Privileged Access */ +#define _SMU_PPUNSPATD1_SYSRTC_SHIFT 0 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUNSPATD1_SYSRTC_MASK 0x1UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUNSPATD1_SYSRTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SYSRTC_DEFAULT (_SMU_PPUNSPATD1_SYSRTC_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LCD (0x1UL << 1) /**< LCD Privileged Access */ +#define _SMU_PPUNSPATD1_LCD_SHIFT 1 /**< Shift value for SMU_LCD */ +#define _SMU_PPUNSPATD1_LCD_MASK 0x2UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUNSPATD1_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LCD_DEFAULT (_SMU_PPUNSPATD1_LCD_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_KEYSCAN (0x1UL << 2) /**< KEYSCAN Privileged Access */ +#define _SMU_PPUNSPATD1_KEYSCAN_SHIFT 2 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUNSPATD1_KEYSCAN_MASK 0x4UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUNSPATD1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_KEYSCAN_DEFAULT (_SMU_PPUNSPATD1_KEYSCAN_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DMEM (0x1UL << 3) /**< DMEM Privileged Access */ +#define _SMU_PPUNSPATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUNSPATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUNSPATD1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DMEM_DEFAULT (_SMU_PPUNSPATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LCDRF (0x1UL << 4) /**< LCDRF Privileged Access */ +#define _SMU_PPUNSPATD1_LCDRF_SHIFT 4 /**< Shift value for SMU_LCDRF */ +#define _SMU_PPUNSPATD1_LCDRF_MASK 0x10UL /**< Bit mask for SMU_LCDRF */ +#define _SMU_PPUNSPATD1_LCDRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LCDRF_DEFAULT (_SMU_PPUNSPATD1_LCDRF_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PFMXPPRF (0x1UL << 5) /**< PFMXPPRF Privileged Access */ +#define _SMU_PPUNSPATD1_PFMXPPRF_SHIFT 5 /**< Shift value for SMU_PFMXPPRF */ +#define _SMU_PPUNSPATD1_PFMXPPRF_MASK 0x20UL /**< Bit mask for SMU_PFMXPPRF */ +#define _SMU_PPUNSPATD1_PFMXPPRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PFMXPPRF_DEFAULT (_SMU_PPUNSPATD1_PFMXPPRF_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES (0x1UL << 6) /**< RADIOAES Privileged Access */ +#define _SMU_PPUNSPATD1_RADIOAES_SHIFT 6 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_MASK 0x40UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES_DEFAULT (_SMU_PPUNSPATD1_RADIOAES_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU (0x1UL << 7) /**< SMU Privileged Access */ +#define _SMU_PPUNSPATD1_SMU_SHIFT 7 /**< Shift value for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_MASK 0x80UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU_DEFAULT (_SMU_PPUNSPATD1_SMU_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS (0x1UL << 8) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUNSPATD1_SMUCFGNS_SHIFT 8 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_MASK 0x100UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS_DEFAULT (_SMU_PPUNSPATD1_SMUCFGNS_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0 (0x1UL << 9) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUNSPATD1_LETIMER0_SHIFT 9 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_MASK 0x200UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0_DEFAULT (_SMU_PPUNSPATD1_LETIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0 (0x1UL << 10) /**< IADC0 Privileged Access */ +#define _SMU_PPUNSPATD1_IADC0_SHIFT 10 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_MASK 0x400UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0_DEFAULT (_SMU_PPUNSPATD1_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP0 (0x1UL << 11) /**< ACMP0 Privileged Access */ +#define _SMU_PPUNSPATD1_ACMP0_SHIFT 11 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUNSPATD1_ACMP0_MASK 0x800UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUNSPATD1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP0_DEFAULT (_SMU_PPUNSPATD1_ACMP0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP1 (0x1UL << 12) /**< ACMP1 Privileged Access */ +#define _SMU_PPUNSPATD1_ACMP1_SHIFT 12 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUNSPATD1_ACMP1_MASK 0x1000UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUNSPATD1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP1_DEFAULT (_SMU_PPUNSPATD1_ACMP1_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0 (0x1UL << 13) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUNSPATD1_AMUXCP0_SHIFT 13 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_MASK 0x2000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0_DEFAULT (_SMU_PPUNSPATD1_AMUXCP0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC0 (0x1UL << 14) /**< VDAC0 Privileged Access */ +#define _SMU_PPUNSPATD1_VDAC0_SHIFT 14 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUNSPATD1_VDAC0_MASK 0x4000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUNSPATD1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC0_DEFAULT (_SMU_PPUNSPATD1_VDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PCNT (0x1UL << 15) /**< PCNT Privileged Access */ +#define _SMU_PPUNSPATD1_PCNT_SHIFT 15 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUNSPATD1_PCNT_MASK 0x8000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUNSPATD1_PCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PCNT_DEFAULT (_SMU_PPUNSPATD1_PCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LESENSE (0x1UL << 16) /**< LESENSE Privileged Access */ +#define _SMU_PPUNSPATD1_LESENSE_SHIFT 16 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUNSPATD1_LESENSE_MASK 0x10000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUNSPATD1_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LESENSE_DEFAULT (_SMU_PPUNSPATD1_LESENSE_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFRCO1 (0x1UL << 17) /**< HFRCO1 Privileged Access */ +#define _SMU_PPUNSPATD1_HFRCO1_SHIFT 17 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUNSPATD1_HFRCO1_MASK 0x20000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUNSPATD1_HFRCO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFRCO1_DEFAULT (_SMU_PPUNSPATD1_HFRCO1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFXO0 (0x1UL << 18) /**< HFXO0 Privileged Access */ +#define _SMU_PPUNSPATD1_HFXO0_SHIFT 18 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUNSPATD1_HFXO0_MASK 0x40000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUNSPATD1_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFXO0_DEFAULT (_SMU_PPUNSPATD1_HFXO0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0 (0x1UL << 19) /**< I2C0 Privileged Access */ +#define _SMU_PPUNSPATD1_I2C0_SHIFT 19 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_MASK 0x80000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0_DEFAULT (_SMU_PPUNSPATD1_I2C0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0 (0x1UL << 20) /**< WDOG0 Privileged Access */ +#define _SMU_PPUNSPATD1_WDOG0_SHIFT 20 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_MASK 0x100000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0_DEFAULT (_SMU_PPUNSPATD1_WDOG0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG1 (0x1UL << 21) /**< WDOG1 Privileged Access */ +#define _SMU_PPUNSPATD1_WDOG1_SHIFT 21 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUNSPATD1_WDOG1_MASK 0x200000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUNSPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG1_DEFAULT (_SMU_PPUNSPATD1_WDOG1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART0 (0x1UL << 22) /**< EUSART0 Privileged Access */ +#define _SMU_PPUNSPATD1_EUSART0_SHIFT 22 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUNSPATD1_EUSART0_MASK 0x400000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUNSPATD1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART0_DEFAULT (_SMU_PPUNSPATD1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SEMAILBOX (0x1UL << 23) /**< SEMAILBOX Privileged Access */ +#define _SMU_PPUNSPATD1_SEMAILBOX_SHIFT 23 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUNSPATD1_SEMAILBOX_MASK 0x800000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUNSPATD1_SEMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SEMAILBOX_DEFAULT (_SMU_PPUNSPATD1_SEMAILBOX_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AHBRADIO (0x1UL << 25) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUNSPATD1_AHBRADIO_SHIFT 25 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD1_AHBRADIO_MASK 0x2000000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD1_AHBRADIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AHBRADIO_DEFAULT (_SMU_PPUNSPATD1_AHBRADIO_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ /* Bit fields for SMU PPUNSFS */ -#define _SMU_PPUNSFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSFS */ -#define _SMU_PPUNSFS_MASK 0x000000FFUL /**< Mask for SMU_PPUNSFS */ -#define _SMU_PPUNSFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ -#define _SMU_PPUNSFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ -#define _SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSFS */ -#define SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_MASK 0x000000FFUL /**< Mask for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSFS */ +#define SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSFS */ /* Bit fields for SMU BMPUNSPATD0 */ -#define _SMU_BMPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUNSPATD0 */ -#define _SMU_BMPUNSPATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ -#define _SMU_BMPUNSPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ -#define _SMU_BMPUNSPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_BMPUNSPATD0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOAES_DEFAULT (_SMU_BMPUNSPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */ -#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */ -#define _SMU_BMPUNSPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ -#define _SMU_BMPUNSPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ -#define _SMU_BMPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_LDMA_DEFAULT (_SMU_BMPUNSPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RFECA0 (0x1UL << 6) /**< RFECA0 privileged mode */ -#define _SMU_BMPUNSPATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ -#define _SMU_BMPUNSPATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ -#define _SMU_BMPUNSPATD0_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RFECA0_DEFAULT (_SMU_BMPUNSPATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RFECA1 (0x1UL << 7) /**< RFECA1 privileged mode */ -#define _SMU_BMPUNSPATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ -#define _SMU_BMPUNSPATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ -#define _SMU_BMPUNSPATD0_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RFECA1_DEFAULT (_SMU_BMPUNSPATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA privileged mode */ -#define _SMU_BMPUNSPATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ -#define _SMU_BMPUNSPATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ -#define _SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ +#define _SMU_BMPUNSPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES_DEFAULT (_SMU_BMPUNSPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */ +#define _SMU_BMPUNSPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA_DEFAULT (_SMU_BMPUNSPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA0 (0x1UL << 6) /**< RFECA0 privileged mode */ +#define _SMU_BMPUNSPATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUNSPATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUNSPATD0_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA0_DEFAULT (_SMU_BMPUNSPATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA1 (0x1UL << 7) /**< RFECA1 privileged mode */ +#define _SMU_BMPUNSPATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUNSPATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUNSPATD0_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA1_DEFAULT (_SMU_BMPUNSPATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA privileged mode */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ /** @} End of group EFR32SG28_SMU_CFGNS_BitFields */ /** @} End of group EFR32SG28_SMU_CFGNS */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_syscfg.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_syscfg.h index 140a5a49c1..e73978e1a3 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32SG28 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_sysrtc.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_sysrtc.h index ddd580260d..b8630480d6 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_sysrtc.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_SYSRTC_H #define EFR32SG28_SYSRTC_H - #define SYSRTC_HAS_SET_CLEAR /**************************************************************************//** @@ -43,103 +42,102 @@ *****************************************************************************/ /** SYSRTC Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP VERSION */ - __IOM uint32_t EN; /**< Module Enable Register */ - __IOM uint32_t SWRST; /**< Software Reset Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status register */ - __IOM uint32_t CNT; /**< Counter Value Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - uint32_t RESERVED2[3U]; /**< Reserved for future use */ - __IOM uint32_t GRP0_IF; /**< Group Interrupt Flags */ - __IOM uint32_t GRP0_IEN; /**< Group Interrupt Enables */ - __IOM uint32_t GRP0_CTRL; /**< Group Control Register */ - __IOM uint32_t GRP0_CMP0VALUE; /**< Compare 0 Value Register */ - __IOM uint32_t GRP0_CMP1VALUE; /**< Compare 1 Value Register */ - __IM uint32_t GRP0_CAP0VALUE; /**< Capture 0 Value Register */ - __IM uint32_t GRP0_SYNCBUSY; /**< Synchronization busy Register */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - uint32_t RESERVED5[7U]; /**< Reserved for future use */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - uint32_t RESERVED7[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP VERSION */ - __IOM uint32_t EN_SET; /**< Module Enable Register */ - __IOM uint32_t SWRST_SET; /**< Software Reset Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status register */ - __IOM uint32_t CNT_SET; /**< Counter Value Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - uint32_t RESERVED8[3U]; /**< Reserved for future use */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - uint32_t RESERVED10[3U]; /**< Reserved for future use */ - __IOM uint32_t GRP0_IF_SET; /**< Group Interrupt Flags */ - __IOM uint32_t GRP0_IEN_SET; /**< Group Interrupt Enables */ - __IOM uint32_t GRP0_CTRL_SET; /**< Group Control Register */ - __IOM uint32_t GRP0_CMP0VALUE_SET; /**< Compare 0 Value Register */ - __IOM uint32_t GRP0_CMP1VALUE_SET; /**< Compare 1 Value Register */ - __IM uint32_t GRP0_CAP0VALUE_SET; /**< Capture 0 Value Register */ - __IM uint32_t GRP0_SYNCBUSY_SET; /**< Synchronization busy Register */ - uint32_t RESERVED11[1U]; /**< Reserved for future use */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - uint32_t RESERVED13[7U]; /**< Reserved for future use */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - uint32_t RESERVED15[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP VERSION */ - __IOM uint32_t EN_CLR; /**< Module Enable Register */ - __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status register */ - __IOM uint32_t CNT_CLR; /**< Counter Value Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - uint32_t RESERVED16[3U]; /**< Reserved for future use */ - uint32_t RESERVED17[1U]; /**< Reserved for future use */ - uint32_t RESERVED18[3U]; /**< Reserved for future use */ - __IOM uint32_t GRP0_IF_CLR; /**< Group Interrupt Flags */ - __IOM uint32_t GRP0_IEN_CLR; /**< Group Interrupt Enables */ - __IOM uint32_t GRP0_CTRL_CLR; /**< Group Control Register */ - __IOM uint32_t GRP0_CMP0VALUE_CLR; /**< Compare 0 Value Register */ - __IOM uint32_t GRP0_CMP1VALUE_CLR; /**< Compare 1 Value Register */ - __IM uint32_t GRP0_CAP0VALUE_CLR; /**< Capture 0 Value Register */ - __IM uint32_t GRP0_SYNCBUSY_CLR; /**< Synchronization busy Register */ - uint32_t RESERVED19[1U]; /**< Reserved for future use */ - uint32_t RESERVED20[1U]; /**< Reserved for future use */ - uint32_t RESERVED21[7U]; /**< Reserved for future use */ - uint32_t RESERVED22[1U]; /**< Reserved for future use */ - uint32_t RESERVED23[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP VERSION */ - __IOM uint32_t EN_TGL; /**< Module Enable Register */ - __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status register */ - __IOM uint32_t CNT_TGL; /**< Counter Value Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - uint32_t RESERVED24[3U]; /**< Reserved for future use */ - uint32_t RESERVED25[1U]; /**< Reserved for future use */ - uint32_t RESERVED26[3U]; /**< Reserved for future use */ - __IOM uint32_t GRP0_IF_TGL; /**< Group Interrupt Flags */ - __IOM uint32_t GRP0_IEN_TGL; /**< Group Interrupt Enables */ - __IOM uint32_t GRP0_CTRL_TGL; /**< Group Control Register */ - __IOM uint32_t GRP0_CMP0VALUE_TGL; /**< Compare 0 Value Register */ - __IOM uint32_t GRP0_CMP1VALUE_TGL; /**< Compare 1 Value Register */ - __IM uint32_t GRP0_CAP0VALUE_TGL; /**< Capture 0 Value Register */ - __IM uint32_t GRP0_SYNCBUSY_TGL; /**< Synchronization busy Register */ - uint32_t RESERVED27[1U]; /**< Reserved for future use */ - uint32_t RESERVED28[1U]; /**< Reserved for future use */ - uint32_t RESERVED29[7U]; /**< Reserved for future use */ - uint32_t RESERVED30[1U]; /**< Reserved for future use */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP VERSION */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY; /**< Synchronization busy Register */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED8[3U]; /**< Reserved for future use */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_SET; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_SET; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_SET; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_SET; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_SET; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_SET; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_SET; /**< Synchronization busy Register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + uint32_t RESERVED15[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED16[3U]; /**< Reserved for future use */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_CLR; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_CLR; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_CLR; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_CLR; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_CLR; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_CLR; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_CLR; /**< Synchronization busy Register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[7U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + uint32_t RESERVED24[3U]; /**< Reserved for future use */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_TGL; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_TGL; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_TGL; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_TGL; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_TGL; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_TGL; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_TGL; /**< Synchronization busy Register */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + uint32_t RESERVED29[7U]; /**< Reserved for future use */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ } SYSRTC_TypeDef; /** @} End of group EFR32SG28_SYSRTC */ @@ -151,270 +149,270 @@ typedef struct *****************************************************************************/ /* Bit fields for SYSRTC IPVERSION */ -#define _SYSRTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for SYSRTC_IPVERSION */ -#define _SYSRTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_IPVERSION */ -#define _SYSRTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSRTC_IPVERSION */ -#define _SYSRTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_IPVERSION */ -#define _SYSRTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSRTC_IPVERSION */ -#define SYSRTC_IPVERSION_IPVERSION_DEFAULT (_SYSRTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSRTC_IPVERSION */ +#define SYSRTC_IPVERSION_IPVERSION_DEFAULT (_SYSRTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_IPVERSION */ /* Bit fields for SYSRTC EN */ -#define _SYSRTC_EN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_EN */ -#define _SYSRTC_EN_MASK 0x00000003UL /**< Mask for SYSRTC_EN */ -#define SYSRTC_EN_EN (0x1UL << 0) /**< SYSRTC Enable */ -#define _SYSRTC_EN_EN_SHIFT 0 /**< Shift value for SYSRTC_EN */ -#define _SYSRTC_EN_EN_MASK 0x1UL /**< Bit mask for SYSRTC_EN */ -#define _SYSRTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ -#define SYSRTC_EN_EN_DEFAULT (_SYSRTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_EN */ -#define SYSRTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _SYSRTC_EN_DISABLING_SHIFT 1 /**< Shift value for SYSRTC_DISABLING */ -#define _SYSRTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for SYSRTC_DISABLING */ -#define _SYSRTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ -#define SYSRTC_EN_DISABLING_DEFAULT (_SYSRTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_EN */ +#define _SYSRTC_EN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_EN */ +#define _SYSRTC_EN_MASK 0x00000003UL /**< Mask for SYSRTC_EN */ +#define SYSRTC_EN_EN (0x1UL << 0) /**< SYSRTC Enable */ +#define _SYSRTC_EN_EN_SHIFT 0 /**< Shift value for SYSRTC_EN */ +#define _SYSRTC_EN_EN_MASK 0x1UL /**< Bit mask for SYSRTC_EN */ +#define _SYSRTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_EN_DEFAULT (_SYSRTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _SYSRTC_EN_DISABLING_SHIFT 1 /**< Shift value for SYSRTC_DISABLING */ +#define _SYSRTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for SYSRTC_DISABLING */ +#define _SYSRTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_DISABLING_DEFAULT (_SYSRTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_EN */ /* Bit fields for SYSRTC SWRST */ -#define _SYSRTC_SWRST_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SWRST */ -#define _SYSRTC_SWRST_MASK 0x00000003UL /**< Mask for SYSRTC_SWRST */ -#define SYSRTC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ -#define _SYSRTC_SWRST_SWRST_SHIFT 0 /**< Shift value for SYSRTC_SWRST */ -#define _SYSRTC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for SYSRTC_SWRST */ -#define _SYSRTC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ -#define SYSRTC_SWRST_SWRST_DEFAULT (_SYSRTC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ -#define SYSRTC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ -#define _SYSRTC_SWRST_RESETTING_SHIFT 1 /**< Shift value for SYSRTC_RESETTING */ -#define _SYSRTC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for SYSRTC_RESETTING */ -#define _SYSRTC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ -#define SYSRTC_SWRST_RESETTING_DEFAULT (_SYSRTC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_MASK 0x00000003UL /**< Mask for SYSRTC_SWRST */ +#define SYSRTC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _SYSRTC_SWRST_SWRST_SHIFT 0 /**< Shift value for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_SWRST_DEFAULT (_SYSRTC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _SYSRTC_SWRST_RESETTING_SHIFT 1 /**< Shift value for SYSRTC_RESETTING */ +#define _SYSRTC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for SYSRTC_RESETTING */ +#define _SYSRTC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_RESETTING_DEFAULT (_SYSRTC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ /* Bit fields for SYSRTC CFG */ -#define _SYSRTC_CFG_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CFG */ -#define _SYSRTC_CFG_MASK 0x00000001UL /**< Mask for SYSRTC_CFG */ -#define SYSRTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ -#define _SYSRTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for SYSRTC_DEBUGRUN */ -#define _SYSRTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for SYSRTC_DEBUGRUN */ -#define _SYSRTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CFG */ -#define _SYSRTC_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for SYSRTC_CFG */ -#define _SYSRTC_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for SYSRTC_CFG */ -#define SYSRTC_CFG_DEBUGRUN_DEFAULT (_SYSRTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CFG */ -#define SYSRTC_CFG_DEBUGRUN_DISABLE (_SYSRTC_CFG_DEBUGRUN_DISABLE << 0) /**< Shifted mode DISABLE for SYSRTC_CFG */ -#define SYSRTC_CFG_DEBUGRUN_ENABLE (_SYSRTC_CFG_DEBUGRUN_ENABLE << 0) /**< Shifted mode ENABLE for SYSRTC_CFG */ +#define _SYSRTC_CFG_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CFG */ +#define _SYSRTC_CFG_MASK 0x00000001UL /**< Mask for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _SYSRTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for SYSRTC_DEBUGRUN */ +#define _SYSRTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for SYSRTC_DEBUGRUN */ +#define _SYSRTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CFG */ +#define _SYSRTC_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for SYSRTC_CFG */ +#define _SYSRTC_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_DEFAULT (_SYSRTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_DISABLE (_SYSRTC_CFG_DEBUGRUN_DISABLE << 0) /**< Shifted mode DISABLE for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_ENABLE (_SYSRTC_CFG_DEBUGRUN_ENABLE << 0) /**< Shifted mode ENABLE for SYSRTC_CFG */ /* Bit fields for SYSRTC CMD */ -#define _SYSRTC_CMD_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CMD */ -#define _SYSRTC_CMD_MASK 0x00000003UL /**< Mask for SYSRTC_CMD */ -#define SYSRTC_CMD_START (0x1UL << 0) /**< Start SYSRTC */ -#define _SYSRTC_CMD_START_SHIFT 0 /**< Shift value for SYSRTC_START */ -#define _SYSRTC_CMD_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ -#define _SYSRTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ -#define SYSRTC_CMD_START_DEFAULT (_SYSRTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CMD */ -#define SYSRTC_CMD_STOP (0x1UL << 1) /**< Stop SYSRTC */ -#define _SYSRTC_CMD_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ -#define _SYSRTC_CMD_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ -#define _SYSRTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ -#define SYSRTC_CMD_STOP_DEFAULT (_SYSRTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_CMD */ +#define _SYSRTC_CMD_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CMD */ +#define _SYSRTC_CMD_MASK 0x00000003UL /**< Mask for SYSRTC_CMD */ +#define SYSRTC_CMD_START (0x1UL << 0) /**< Start SYSRTC */ +#define _SYSRTC_CMD_START_SHIFT 0 /**< Shift value for SYSRTC_START */ +#define _SYSRTC_CMD_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ +#define _SYSRTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_START_DEFAULT (_SYSRTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_STOP (0x1UL << 1) /**< Stop SYSRTC */ +#define _SYSRTC_CMD_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ +#define _SYSRTC_CMD_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ +#define _SYSRTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_STOP_DEFAULT (_SYSRTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_CMD */ /* Bit fields for SYSRTC STATUS */ -#define _SYSRTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_STATUS */ -#define _SYSRTC_STATUS_MASK 0x00000007UL /**< Mask for SYSRTC_STATUS */ -#define SYSRTC_STATUS_RUNNING (0x1UL << 0) /**< SYSRTC running status */ -#define _SYSRTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for SYSRTC_RUNNING */ -#define _SYSRTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for SYSRTC_RUNNING */ -#define _SYSRTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ -#define SYSRTC_STATUS_RUNNING_DEFAULT (_SYSRTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ -#define SYSRTC_STATUS_LOCKSTATUS (0x1UL << 1) /**< Lock Status */ -#define _SYSRTC_STATUS_LOCKSTATUS_SHIFT 1 /**< Shift value for SYSRTC_LOCKSTATUS */ -#define _SYSRTC_STATUS_LOCKSTATUS_MASK 0x2UL /**< Bit mask for SYSRTC_LOCKSTATUS */ -#define _SYSRTC_STATUS_LOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ -#define _SYSRTC_STATUS_LOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SYSRTC_STATUS */ -#define _SYSRTC_STATUS_LOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for SYSRTC_STATUS */ -#define SYSRTC_STATUS_LOCKSTATUS_DEFAULT (_SYSRTC_STATUS_LOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ -#define SYSRTC_STATUS_LOCKSTATUS_UNLOCKED (_SYSRTC_STATUS_LOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for SYSRTC_STATUS */ -#define SYSRTC_STATUS_LOCKSTATUS_LOCKED (_SYSRTC_STATUS_LOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_MASK 0x00000007UL /**< Mask for SYSRTC_STATUS */ +#define SYSRTC_STATUS_RUNNING (0x1UL << 0) /**< SYSRTC running status */ +#define _SYSRTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for SYSRTC_RUNNING */ +#define _SYSRTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for SYSRTC_RUNNING */ +#define _SYSRTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_RUNNING_DEFAULT (_SYSRTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS (0x1UL << 1) /**< Lock Status */ +#define _SYSRTC_STATUS_LOCKSTATUS_SHIFT 1 /**< Shift value for SYSRTC_LOCKSTATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_MASK 0x2UL /**< Bit mask for SYSRTC_LOCKSTATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_DEFAULT (_SYSRTC_STATUS_LOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_UNLOCKED (_SYSRTC_STATUS_LOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_LOCKED (_SYSRTC_STATUS_LOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for SYSRTC_STATUS */ /* Bit fields for SYSRTC CNT */ -#define _SYSRTC_CNT_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CNT */ -#define _SYSRTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_CNT */ -#define _SYSRTC_CNT_CNT_SHIFT 0 /**< Shift value for SYSRTC_CNT */ -#define _SYSRTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CNT */ -#define _SYSRTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CNT */ -#define SYSRTC_CNT_CNT_DEFAULT (_SYSRTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CNT */ +#define _SYSRTC_CNT_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CNT */ +#define _SYSRTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_SHIFT 0 /**< Shift value for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CNT */ +#define SYSRTC_CNT_CNT_DEFAULT (_SYSRTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CNT */ /* Bit fields for SYSRTC SYNCBUSY */ -#define _SYSRTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SYNCBUSY */ -#define _SYSRTC_SYNCBUSY_MASK 0x0000000FUL /**< Mask for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START bitfield */ -#define _SYSRTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for SYSRTC_START */ -#define _SYSRTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ -#define _SYSRTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_START_DEFAULT (_SYSRTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP bitfield */ -#define _SYSRTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ -#define _SYSRTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ -#define _SYSRTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_STOP_DEFAULT (_SYSRTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_CNT (0x1UL << 2) /**< Sync busy for CNT bitfield */ -#define _SYSRTC_SYNCBUSY_CNT_SHIFT 2 /**< Shift value for SYSRTC_CNT */ -#define _SYSRTC_SYNCBUSY_CNT_MASK 0x4UL /**< Bit mask for SYSRTC_CNT */ -#define _SYSRTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_CNT_DEFAULT (_SYSRTC_SYNCBUSY_CNT_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ +#define _SYSRTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SYNCBUSY */ +#define _SYSRTC_SYNCBUSY_MASK 0x0000000FUL /**< Mask for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START bitfield */ +#define _SYSRTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for SYSRTC_START */ +#define _SYSRTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ +#define _SYSRTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_START_DEFAULT (_SYSRTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP bitfield */ +#define _SYSRTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ +#define _SYSRTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ +#define _SYSRTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_STOP_DEFAULT (_SYSRTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_CNT (0x1UL << 2) /**< Sync busy for CNT bitfield */ +#define _SYSRTC_SYNCBUSY_CNT_SHIFT 2 /**< Shift value for SYSRTC_CNT */ +#define _SYSRTC_SYNCBUSY_CNT_MASK 0x4UL /**< Bit mask for SYSRTC_CNT */ +#define _SYSRTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_CNT_DEFAULT (_SYSRTC_SYNCBUSY_CNT_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ /* Bit fields for SYSRTC LOCK */ -#define _SYSRTC_LOCK_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_LOCK */ -#define _SYSRTC_LOCK_MASK 0x0000FFFFUL /**< Mask for SYSRTC_LOCK */ -#define _SYSRTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for SYSRTC_LOCKKEY */ -#define _SYSRTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for SYSRTC_LOCKKEY */ -#define _SYSRTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_LOCK */ -#define _SYSRTC_LOCK_LOCKKEY_UNLOCK 0x00004776UL /**< Mode UNLOCK for SYSRTC_LOCK */ -#define SYSRTC_LOCK_LOCKKEY_DEFAULT (_SYSRTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_LOCK */ -#define SYSRTC_LOCK_LOCKKEY_UNLOCK (_SYSRTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_MASK 0x0000FFFFUL /**< Mask for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for SYSRTC_LOCKKEY */ +#define _SYSRTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for SYSRTC_LOCKKEY */ +#define _SYSRTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_LOCKKEY_UNLOCK 0x00004776UL /**< Mode UNLOCK for SYSRTC_LOCK */ +#define SYSRTC_LOCK_LOCKKEY_DEFAULT (_SYSRTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_LOCK */ +#define SYSRTC_LOCK_LOCKKEY_UNLOCK (_SYSRTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SYSRTC_LOCK */ /* Bit fields for SYSRTC GRP0_IF */ -#define _SYSRTC_GRP0_IF_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IF */ -#define _SYSRTC_GRP0_IF_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_OVF (0x1UL << 0) /**< Overflow Interrupt Flag */ -#define _SYSRTC_GRP0_IF_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ -#define _SYSRTC_GRP0_IF_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ -#define _SYSRTC_GRP0_IF_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_OVF_DEFAULT (_SYSRTC_GRP0_IF_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Flag */ -#define _SYSRTC_GRP0_IF_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ -#define _SYSRTC_GRP0_IF_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ -#define _SYSRTC_GRP0_IF_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CMP0_DEFAULT (_SYSRTC_GRP0_IF_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Flag */ -#define _SYSRTC_GRP0_IF_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ -#define _SYSRTC_GRP0_IF_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ -#define _SYSRTC_GRP0_IF_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CMP1_DEFAULT (_SYSRTC_GRP0_IF_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Flag */ -#define _SYSRTC_GRP0_IF_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ -#define _SYSRTC_GRP0_IF_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ -#define _SYSRTC_GRP0_IF_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CAP0_DEFAULT (_SYSRTC_GRP0_IF_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define _SYSRTC_GRP0_IF_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IF */ +#define _SYSRTC_GRP0_IF_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_OVF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _SYSRTC_GRP0_IF_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IF_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IF_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_OVF_DEFAULT (_SYSRTC_GRP0_IF_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IF_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IF_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP0_DEFAULT (_SYSRTC_GRP0_IF_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IF_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IF_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP1_DEFAULT (_SYSRTC_GRP0_IF_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IF_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IF_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CAP0_DEFAULT (_SYSRTC_GRP0_IF_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ /* Bit fields for SYSRTC GRP0_IEN */ -#define _SYSRTC_GRP0_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IEN */ -#define _SYSRTC_GRP0_IEN_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_OVF (0x1UL << 0) /**< Overflow Interrupt Enable */ -#define _SYSRTC_GRP0_IEN_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ -#define _SYSRTC_GRP0_IEN_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ -#define _SYSRTC_GRP0_IEN_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_OVF_DEFAULT (_SYSRTC_GRP0_IEN_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Enable */ -#define _SYSRTC_GRP0_IEN_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ -#define _SYSRTC_GRP0_IEN_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ -#define _SYSRTC_GRP0_IEN_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CMP0_DEFAULT (_SYSRTC_GRP0_IEN_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Enable */ -#define _SYSRTC_GRP0_IEN_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ -#define _SYSRTC_GRP0_IEN_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ -#define _SYSRTC_GRP0_IEN_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CMP1_DEFAULT (_SYSRTC_GRP0_IEN_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Enable */ -#define _SYSRTC_GRP0_IEN_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ -#define _SYSRTC_GRP0_IEN_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ -#define _SYSRTC_GRP0_IEN_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CAP0_DEFAULT (_SYSRTC_GRP0_IEN_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define _SYSRTC_GRP0_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IEN */ +#define _SYSRTC_GRP0_IEN_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_OVF (0x1UL << 0) /**< Overflow Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IEN_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IEN_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_OVF_DEFAULT (_SYSRTC_GRP0_IEN_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IEN_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IEN_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP0_DEFAULT (_SYSRTC_GRP0_IEN_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IEN_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IEN_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP1_DEFAULT (_SYSRTC_GRP0_IEN_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IEN_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IEN_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CAP0_DEFAULT (_SYSRTC_GRP0_IEN_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ /* Bit fields for SYSRTC GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_MASK 0x000007FFUL /**< Mask for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0EN (0x1UL << 0) /**< Compare 0 Enable */ -#define _SYSRTC_GRP0_CTRL_CMP0EN_SHIFT 0 /**< Shift value for SYSRTC_CMP0EN */ -#define _SYSRTC_GRP0_CTRL_CMP0EN_MASK 0x1UL /**< Bit mask for SYSRTC_CMP0EN */ -#define _SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1EN (0x1UL << 1) /**< Compare 1 Enable */ -#define _SYSRTC_GRP0_CTRL_CMP1EN_SHIFT 1 /**< Shift value for SYSRTC_CMP1EN */ -#define _SYSRTC_GRP0_CTRL_CMP1EN_MASK 0x2UL /**< Bit mask for SYSRTC_CMP1EN */ -#define _SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EN (0x1UL << 2) /**< Capture 0 Enable */ -#define _SYSRTC_GRP0_CTRL_CAP0EN_SHIFT 2 /**< Shift value for SYSRTC_CAP0EN */ -#define _SYSRTC_GRP0_CTRL_CAP0EN_MASK 0x4UL /**< Bit mask for SYSRTC_CAP0EN */ -#define _SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SHIFT 3 /**< Shift value for SYSRTC_CMP0CMOA */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_MASK 0x38UL /**< Bit mask for SYSRTC_CMP0CMOA */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR << 3) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_SET (_SYSRTC_GRP0_CTRL_CMP0CMOA_SET << 3) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE << 3) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE << 3) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF << 3) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT 6 /**< Shift value for SYSRTC_CMP1CMOA */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_MASK 0x1C0UL /**< Bit mask for SYSRTC_CMP1CMOA */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR << 6) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_SET (_SYSRTC_GRP0_CTRL_CMP1CMOA_SET << 6) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE << 6) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE << 6) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF << 6) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT 9 /**< Shift value for SYSRTC_CAP0EDGE */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_MASK 0x600UL /**< Bit mask for SYSRTC_CAP0EDGE */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_RISING 0x00000000UL /**< Mode RISING for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING 0x00000001UL /**< Mode FALLING for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH 0x00000002UL /**< Mode BOTH for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EDGE_RISING (_SYSRTC_GRP0_CTRL_CAP0EDGE_RISING << 9) /**< Shifted mode RISING for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING (_SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING << 9) /**< Shifted mode FALLING for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH (_SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH << 9) /**< Shifted mode BOTH for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_MASK 0x000007FFUL /**< Mask for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0EN (0x1UL << 0) /**< Compare 0 Enable */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_SHIFT 0 /**< Shift value for SYSRTC_CMP0EN */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_MASK 0x1UL /**< Bit mask for SYSRTC_CMP0EN */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1EN (0x1UL << 1) /**< Compare 1 Enable */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_SHIFT 1 /**< Shift value for SYSRTC_CMP1EN */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_MASK 0x2UL /**< Bit mask for SYSRTC_CMP1EN */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EN (0x1UL << 2) /**< Capture 0 Enable */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_SHIFT 2 /**< Shift value for SYSRTC_CAP0EN */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_MASK 0x4UL /**< Bit mask for SYSRTC_CAP0EN */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SHIFT 3 /**< Shift value for SYSRTC_CMP0CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_MASK 0x38UL /**< Bit mask for SYSRTC_CMP0CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR << 3) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_SET (_SYSRTC_GRP0_CTRL_CMP0CMOA_SET << 3) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE << 3) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE << 3) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF << 3) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT 6 /**< Shift value for SYSRTC_CMP1CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_MASK 0x1C0UL /**< Bit mask for SYSRTC_CMP1CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR << 6) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_SET (_SYSRTC_GRP0_CTRL_CMP1CMOA_SET << 6) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE << 6) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE << 6) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF << 6) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT 9 /**< Shift value for SYSRTC_CAP0EDGE */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_MASK 0x600UL /**< Bit mask for SYSRTC_CAP0EDGE */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_RISING 0x00000000UL /**< Mode RISING for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING 0x00000001UL /**< Mode FALLING for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH 0x00000002UL /**< Mode BOTH for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_RISING (_SYSRTC_GRP0_CTRL_CAP0EDGE_RISING << 9) /**< Shifted mode RISING for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING (_SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING << 9) /**< Shifted mode FALLING for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH (_SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH << 9) /**< Shifted mode BOTH for SYSRTC_GRP0_CTRL */ /* Bit fields for SYSRTC GRP0_CMP0VALUE */ -#define _SYSRTC_GRP0_CMP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP0VALUE */ -#define _SYSRTC_GRP0_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP0VALUE */ -#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP0VALUE */ -#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP0VALUE */ -#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP0VALUE */ -#define SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP0VALUE*/ +#define _SYSRTC_GRP0_CMP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP0VALUE */ +#define SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP0VALUE*/ /* Bit fields for SYSRTC GRP0_CMP1VALUE */ -#define _SYSRTC_GRP0_CMP1VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP1VALUE */ -#define _SYSRTC_GRP0_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP1VALUE */ -#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP1VALUE */ -#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP1VALUE */ -#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP1VALUE */ -#define SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP1VALUE*/ +#define _SYSRTC_GRP0_CMP1VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP1VALUE */ +#define SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP1VALUE*/ /* Bit fields for SYSRTC GRP0_CAP0VALUE */ -#define _SYSRTC_GRP0_CAP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CAP0VALUE */ -#define _SYSRTC_GRP0_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CAP0VALUE */ -#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CAP0VALUE */ -#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CAP0VALUE */ -#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CAP0VALUE */ -#define SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT (_SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CAP0VALUE*/ +#define _SYSRTC_GRP0_CAP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CAP0VALUE */ +#define SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT (_SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CAP0VALUE*/ /* Bit fields for SYSRTC GRP0_SYNCBUSY */ -#define _SYSRTC_GRP0_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_SYNCBUSY */ -#define _SYSRTC_GRP0_SYNCBUSY_MASK 0x00000007UL /**< Mask for SYSRTC_GRP0_SYNCBUSY */ -#define SYSRTC_GRP0_SYNCBUSY_CTRL (0x1UL << 0) /**< Sync busy for CTRL register */ -#define _SYSRTC_GRP0_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for SYSRTC_CTRL */ -#define _SYSRTC_GRP0_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for SYSRTC_CTRL */ -#define _SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ -#define SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ -#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE (0x1UL << 1) /**< Sync busy for CMP0VALUE register */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_SHIFT 1 /**< Shift value for SYSRTC_CMP0VALUE */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0VALUE */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ -#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ -#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE (0x1UL << 2) /**< Sync busy for CMP1VALUE register */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_SHIFT 2 /**< Shift value for SYSRTC_CMP1VALUE */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1VALUE */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ -#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ +#define _SYSRTC_GRP0_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_SYNCBUSY */ +#define _SYSRTC_GRP0_SYNCBUSY_MASK 0x00000007UL /**< Mask for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CTRL (0x1UL << 0) /**< Sync busy for CTRL register */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for SYSRTC_CTRL */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for SYSRTC_CTRL */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ +#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE (0x1UL << 1) /**< Sync busy for CMP0VALUE register */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_SHIFT 1 /**< Shift value for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ +#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE (0x1UL << 2) /**< Sync busy for CMP1VALUE register */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_SHIFT 2 /**< Shift value for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ /** @} End of group EFR32SG28_SYSRTC_BitFields */ /** @} End of group EFR32SG28_SYSRTC */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_timer.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_timer.h index 94fe293390..a5de4a4e0f 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_timer.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_timer.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_TIMER_H #define EFR32SG28_TIMER_H - #define TIMER_HAS_SET_CLEAR /**************************************************************************//** @@ -43,121 +42,118 @@ *****************************************************************************/ /** TIMER CC Register Group Declaration. */ -typedef struct -{ - __IOM uint32_t CFG; /**< CC Channel Configuration Register */ - __IOM uint32_t CTRL; /**< CC Channel Control Register */ - __IOM uint32_t OC; /**< OC Channel Value Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t OCB; /**< OC Channel Value Buffer Register */ - __IM uint32_t ICF; /**< IC Channel Value Register */ - __IM uint32_t ICOF; /**< IC Channel Value Overflow Register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ +typedef struct { + __IOM uint32_t CFG; /**< CC Channel Configuration Register */ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t OC; /**< OC Channel Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t OCB; /**< OC Channel Value Buffer Register */ + __IM uint32_t ICF; /**< IC Channel Value Register */ + __IM uint32_t ICOF; /**< IC Channel Value Overflow Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ } TIMER_CC_TypeDef; - /** TIMER Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t TOP; /**< Counter Top Value Register */ - __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ - __IOM uint32_t CNT; /**< Counter Value Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ - __IOM uint32_t EN; /**< module en */ - uint32_t RESERVED1[11U]; /**< Reserved for future use */ - TIMER_CC_TypeDef CC[3U]; /**< Compare/Capture Channel */ - uint32_t RESERVED2[8U]; /**< Reserved for future use */ - __IOM uint32_t DTCFG; /**< DTI Configuration Register */ - __IOM uint32_t DTTIMECFG; /**< DTI Time Configuration Register */ - __IOM uint32_t DTFCFG; /**< DTI Fault Configuration Register */ - __IOM uint32_t DTCTRL; /**< DTI Control Register */ - __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ - __IM uint32_t DTFAULT; /**< DTI Fault Register */ - __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ - __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ - uint32_t RESERVED3[960U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t TOP_SET; /**< Counter Top Value Register */ - __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ - __IOM uint32_t CNT_SET; /**< Counter Value Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< TIMER Configuration Lock Register */ - __IOM uint32_t EN_SET; /**< module en */ - uint32_t RESERVED5[11U]; /**< Reserved for future use */ - TIMER_CC_TypeDef CC_SET[3U]; /**< Compare/Capture Channel */ - uint32_t RESERVED6[8U]; /**< Reserved for future use */ - __IOM uint32_t DTCFG_SET; /**< DTI Configuration Register */ - __IOM uint32_t DTTIMECFG_SET; /**< DTI Time Configuration Register */ - __IOM uint32_t DTFCFG_SET; /**< DTI Fault Configuration Register */ - __IOM uint32_t DTCTRL_SET; /**< DTI Control Register */ - __IOM uint32_t DTOGEN_SET; /**< DTI Output Generation Enable Register */ - __IM uint32_t DTFAULT_SET; /**< DTI Fault Register */ - __IOM uint32_t DTFAULTC_SET; /**< DTI Fault Clear Register */ - __IOM uint32_t DTLOCK_SET; /**< DTI Configuration Lock Register */ - uint32_t RESERVED7[960U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t TOP_CLR; /**< Counter Top Value Register */ - __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ - __IOM uint32_t CNT_CLR; /**< Counter Value Register */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< TIMER Configuration Lock Register */ - __IOM uint32_t EN_CLR; /**< module en */ - uint32_t RESERVED9[11U]; /**< Reserved for future use */ - TIMER_CC_TypeDef CC_CLR[3U]; /**< Compare/Capture Channel */ - uint32_t RESERVED10[8U]; /**< Reserved for future use */ - __IOM uint32_t DTCFG_CLR; /**< DTI Configuration Register */ - __IOM uint32_t DTTIMECFG_CLR; /**< DTI Time Configuration Register */ - __IOM uint32_t DTFCFG_CLR; /**< DTI Fault Configuration Register */ - __IOM uint32_t DTCTRL_CLR; /**< DTI Control Register */ - __IOM uint32_t DTOGEN_CLR; /**< DTI Output Generation Enable Register */ - __IM uint32_t DTFAULT_CLR; /**< DTI Fault Register */ - __IOM uint32_t DTFAULTC_CLR; /**< DTI Fault Clear Register */ - __IOM uint32_t DTLOCK_CLR; /**< DTI Configuration Lock Register */ - uint32_t RESERVED11[960U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t TOP_TGL; /**< Counter Top Value Register */ - __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ - __IOM uint32_t CNT_TGL; /**< Counter Value Register */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< TIMER Configuration Lock Register */ - __IOM uint32_t EN_TGL; /**< module en */ - uint32_t RESERVED13[11U]; /**< Reserved for future use */ - TIMER_CC_TypeDef CC_TGL[3U]; /**< Compare/Capture Channel */ - uint32_t RESERVED14[8U]; /**< Reserved for future use */ - __IOM uint32_t DTCFG_TGL; /**< DTI Configuration Register */ - __IOM uint32_t DTTIMECFG_TGL; /**< DTI Time Configuration Register */ - __IOM uint32_t DTFCFG_TGL; /**< DTI Fault Configuration Register */ - __IOM uint32_t DTCTRL_TGL; /**< DTI Control Register */ - __IOM uint32_t DTOGEN_TGL; /**< DTI Output Generation Enable Register */ - __IM uint32_t DTFAULT_TGL; /**< DTI Fault Register */ - __IOM uint32_t DTFAULTC_TGL; /**< DTI Fault Clear Register */ - __IOM uint32_t DTLOCK_TGL; /**< DTI Configuration Lock Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t TOP; /**< Counter Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN; /**< module en */ + uint32_t RESERVED1[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ + uint32_t RESERVED3[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_SET; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_SET; /**< module en */ + uint32_t RESERVED5[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_SET[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED6[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_SET; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_SET; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_SET; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_SET; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_SET; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_SET; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_SET; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_SET; /**< DTI Configuration Lock Register */ + uint32_t RESERVED7[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_CLR; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_CLR; /**< module en */ + uint32_t RESERVED9[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_CLR[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED10[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_CLR; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_CLR; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_CLR; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_CLR; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_CLR; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_CLR; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_CLR; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_CLR; /**< DTI Configuration Lock Register */ + uint32_t RESERVED11[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_TGL; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_TGL; /**< module en */ + uint32_t RESERVED13[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_TGL[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED14[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_TGL; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_TGL; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_TGL; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_TGL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_TGL; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_TGL; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_TGL; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_TGL; /**< DTI Configuration Lock Register */ } TIMER_TypeDef; /** @} End of group EFR32SG28_TIMER */ @@ -169,853 +165,853 @@ typedef struct *****************************************************************************/ /* Bit fields for TIMER IPVERSION */ -#define _TIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for TIMER_IPVERSION */ -#define _TIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for TIMER_IPVERSION */ -#define _TIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for TIMER_IPVERSION */ -#define _TIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_IPVERSION */ -#define _TIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for TIMER_IPVERSION */ -#define TIMER_IPVERSION_IPVERSION_DEFAULT (_TIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for TIMER_IPVERSION */ +#define TIMER_IPVERSION_IPVERSION_DEFAULT (_TIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IPVERSION */ /* Bit fields for TIMER CFG */ -#define _TIMER_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CFG */ -#define _TIMER_CFG_MASK 0x0FFF1FFBUL /**< Mask for TIMER_CFG */ -#define _TIMER_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ -#define _TIMER_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ -#define _TIMER_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CFG */ -#define _TIMER_CFG_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CFG */ -#define _TIMER_CFG_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CFG */ -#define _TIMER_CFG_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CFG */ -#define TIMER_CFG_MODE_DEFAULT (_TIMER_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_MODE_UP (_TIMER_CFG_MODE_UP << 0) /**< Shifted mode UP for TIMER_CFG */ -#define TIMER_CFG_MODE_DOWN (_TIMER_CFG_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CFG */ -#define TIMER_CFG_MODE_UPDOWN (_TIMER_CFG_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CFG */ -#define TIMER_CFG_MODE_QDEC (_TIMER_CFG_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CFG */ -#define TIMER_CFG_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ -#define _TIMER_CFG_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ -#define _TIMER_CFG_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ -#define _TIMER_CFG_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ -#define _TIMER_CFG_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ -#define TIMER_CFG_SYNC_DEFAULT (_TIMER_CFG_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_SYNC_DISABLE (_TIMER_CFG_SYNC_DISABLE << 3) /**< Shifted mode DISABLE for TIMER_CFG */ -#define TIMER_CFG_SYNC_ENABLE (_TIMER_CFG_SYNC_ENABLE << 3) /**< Shifted mode ENABLE for TIMER_CFG */ -#define TIMER_CFG_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ -#define _TIMER_CFG_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ -#define _TIMER_CFG_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ -#define _TIMER_CFG_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_OSMEN_DEFAULT (_TIMER_CFG_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ -#define _TIMER_CFG_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ -#define _TIMER_CFG_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ -#define _TIMER_CFG_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CFG */ -#define _TIMER_CFG_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CFG */ -#define TIMER_CFG_QDM_DEFAULT (_TIMER_CFG_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_QDM_X2 (_TIMER_CFG_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CFG */ -#define TIMER_CFG_QDM_X4 (_TIMER_CFG_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CFG */ -#define TIMER_CFG_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ -#define _TIMER_CFG_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ -#define _TIMER_CFG_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ -#define _TIMER_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_DEBUGRUN_HALT 0x00000000UL /**< Mode HALT for TIMER_CFG */ -#define _TIMER_CFG_DEBUGRUN_RUN 0x00000001UL /**< Mode RUN for TIMER_CFG */ -#define TIMER_CFG_DEBUGRUN_DEFAULT (_TIMER_CFG_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_DEBUGRUN_HALT (_TIMER_CFG_DEBUGRUN_HALT << 6) /**< Shifted mode HALT for TIMER_CFG */ -#define TIMER_CFG_DEBUGRUN_RUN (_TIMER_CFG_DEBUGRUN_RUN << 6) /**< Shifted mode RUN for TIMER_CFG */ -#define TIMER_CFG_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ -#define _TIMER_CFG_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ -#define _TIMER_CFG_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ -#define _TIMER_CFG_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_DMACLRACT_DEFAULT (_TIMER_CFG_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_CLKSEL_SHIFT 8 /**< Shift value for TIMER_CLKSEL */ -#define _TIMER_CFG_CLKSEL_MASK 0x300UL /**< Bit mask for TIMER_CLKSEL */ -#define _TIMER_CFG_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK 0x00000000UL /**< Mode PRESCEM01GRPACLK for TIMER_CFG */ -#define _TIMER_CFG_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CFG */ -#define _TIMER_CFG_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CFG */ -#define TIMER_CFG_CLKSEL_DEFAULT (_TIMER_CFG_CLKSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_CLKSEL_PRESCEM01GRPACLK (_TIMER_CFG_CLKSEL_PRESCEM01GRPACLK << 8) /**< Shifted mode PRESCEM01GRPACLK for TIMER_CFG */ -#define TIMER_CFG_CLKSEL_CC1 (_TIMER_CFG_CLKSEL_CC1 << 8) /**< Shifted mode CC1 for TIMER_CFG */ -#define TIMER_CFG_CLKSEL_TIMEROUF (_TIMER_CFG_CLKSEL_TIMEROUF << 8) /**< Shifted mode TIMEROUF for TIMER_CFG */ -#define TIMER_CFG_RETIMEEN (0x1UL << 10) /**< PWM output retimed enable */ -#define _TIMER_CFG_RETIMEEN_SHIFT 10 /**< Shift value for TIMER_RETIMEEN */ -#define _TIMER_CFG_RETIMEEN_MASK 0x400UL /**< Bit mask for TIMER_RETIMEEN */ -#define _TIMER_CFG_RETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_RETIMEEN_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ -#define _TIMER_CFG_RETIMEEN_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ -#define TIMER_CFG_RETIMEEN_DEFAULT (_TIMER_CFG_RETIMEEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_RETIMEEN_DISABLE (_TIMER_CFG_RETIMEEN_DISABLE << 10) /**< Shifted mode DISABLE for TIMER_CFG */ -#define TIMER_CFG_RETIMEEN_ENABLE (_TIMER_CFG_RETIMEEN_ENABLE << 10) /**< Shifted mode ENABLE for TIMER_CFG */ -#define TIMER_CFG_DISSYNCOUT (0x1UL << 11) /**< Disable Timer Start/Stop/Reload output */ -#define _TIMER_CFG_DISSYNCOUT_SHIFT 11 /**< Shift value for TIMER_DISSYNCOUT */ -#define _TIMER_CFG_DISSYNCOUT_MASK 0x800UL /**< Bit mask for TIMER_DISSYNCOUT */ -#define _TIMER_CFG_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_DISSYNCOUT_EN 0x00000000UL /**< Mode EN for TIMER_CFG */ -#define _TIMER_CFG_DISSYNCOUT_DIS 0x00000001UL /**< Mode DIS for TIMER_CFG */ -#define TIMER_CFG_DISSYNCOUT_DEFAULT (_TIMER_CFG_DISSYNCOUT_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_DISSYNCOUT_EN (_TIMER_CFG_DISSYNCOUT_EN << 11) /**< Shifted mode EN for TIMER_CFG */ -#define TIMER_CFG_DISSYNCOUT_DIS (_TIMER_CFG_DISSYNCOUT_DIS << 11) /**< Shifted mode DIS for TIMER_CFG */ -#define TIMER_CFG_RETIMESEL (0x1UL << 12) /**< PWM output retime select */ -#define _TIMER_CFG_RETIMESEL_SHIFT 12 /**< Shift value for TIMER_RETIMESEL */ -#define _TIMER_CFG_RETIMESEL_MASK 0x1000UL /**< Bit mask for TIMER_RETIMESEL */ -#define _TIMER_CFG_RETIMESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_RETIMESEL_DEFAULT (_TIMER_CFG_RETIMESEL_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_ATI (0x1UL << 16) /**< Always Track Inputs */ -#define _TIMER_CFG_ATI_SHIFT 16 /**< Shift value for TIMER_ATI */ -#define _TIMER_CFG_ATI_MASK 0x10000UL /**< Bit mask for TIMER_ATI */ -#define _TIMER_CFG_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_ATI_DEFAULT (_TIMER_CFG_ATI_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_RSSCOIST (0x1UL << 17) /**< Reload-Start Sets COIST */ -#define _TIMER_CFG_RSSCOIST_SHIFT 17 /**< Shift value for TIMER_RSSCOIST */ -#define _TIMER_CFG_RSSCOIST_MASK 0x20000UL /**< Bit mask for TIMER_RSSCOIST */ -#define _TIMER_CFG_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_RSSCOIST_DEFAULT (_TIMER_CFG_RSSCOIST_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_PRESC_SHIFT 18 /**< Shift value for TIMER_PRESC */ -#define _TIMER_CFG_PRESC_MASK 0xFFC0000UL /**< Bit mask for TIMER_PRESC */ -#define _TIMER_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV8 0x00000007UL /**< Mode DIV8 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV16 0x0000000FUL /**< Mode DIV16 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV32 0x0000001FUL /**< Mode DIV32 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV64 0x0000003FUL /**< Mode DIV64 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV128 0x0000007FUL /**< Mode DIV128 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV256 0x000000FFUL /**< Mode DIV256 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV512 0x000001FFUL /**< Mode DIV512 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV1024 0x000003FFUL /**< Mode DIV1024 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DEFAULT (_TIMER_CFG_PRESC_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV1 (_TIMER_CFG_PRESC_DIV1 << 18) /**< Shifted mode DIV1 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV2 (_TIMER_CFG_PRESC_DIV2 << 18) /**< Shifted mode DIV2 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV4 (_TIMER_CFG_PRESC_DIV4 << 18) /**< Shifted mode DIV4 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV8 (_TIMER_CFG_PRESC_DIV8 << 18) /**< Shifted mode DIV8 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV16 (_TIMER_CFG_PRESC_DIV16 << 18) /**< Shifted mode DIV16 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV32 (_TIMER_CFG_PRESC_DIV32 << 18) /**< Shifted mode DIV32 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV64 (_TIMER_CFG_PRESC_DIV64 << 18) /**< Shifted mode DIV64 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV128 (_TIMER_CFG_PRESC_DIV128 << 18) /**< Shifted mode DIV128 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV256 (_TIMER_CFG_PRESC_DIV256 << 18) /**< Shifted mode DIV256 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV512 (_TIMER_CFG_PRESC_DIV512 << 18) /**< Shifted mode DIV512 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV1024 (_TIMER_CFG_PRESC_DIV1024 << 18) /**< Shifted mode DIV1024 for TIMER_CFG */ +#define _TIMER_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CFG */ +#define _TIMER_CFG_MASK 0x0FFF1FFBUL /**< Mask for TIMER_CFG */ +#define _TIMER_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CFG */ +#define _TIMER_CFG_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CFG */ +#define TIMER_CFG_MODE_DEFAULT (_TIMER_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_MODE_UP (_TIMER_CFG_MODE_UP << 0) /**< Shifted mode UP for TIMER_CFG */ +#define TIMER_CFG_MODE_DOWN (_TIMER_CFG_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_UPDOWN (_TIMER_CFG_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_QDEC (_TIMER_CFG_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CFG */ +#define TIMER_CFG_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _TIMER_CFG_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_DEFAULT (_TIMER_CFG_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_SYNC_DISABLE (_TIMER_CFG_SYNC_DISABLE << 3) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_ENABLE (_TIMER_CFG_SYNC_ENABLE << 3) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _TIMER_CFG_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_OSMEN_DEFAULT (_TIMER_CFG_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _TIMER_CFG_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _TIMER_CFG_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _TIMER_CFG_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CFG */ +#define _TIMER_CFG_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CFG */ +#define TIMER_CFG_QDM_DEFAULT (_TIMER_CFG_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM_X2 (_TIMER_CFG_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CFG */ +#define TIMER_CFG_QDM_X4 (_TIMER_CFG_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _TIMER_CFG_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_HALT 0x00000000UL /**< Mode HALT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_RUN 0x00000001UL /**< Mode RUN for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_DEFAULT (_TIMER_CFG_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_HALT (_TIMER_CFG_DEBUGRUN_HALT << 6) /**< Shifted mode HALT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_RUN (_TIMER_CFG_DEBUGRUN_RUN << 6) /**< Shifted mode RUN for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _TIMER_CFG_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT_DEFAULT (_TIMER_CFG_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_SHIFT 8 /**< Shift value for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_MASK 0x300UL /**< Bit mask for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK 0x00000000UL /**< Mode PRESCEM01GRPACLK for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_DEFAULT (_TIMER_CFG_CLKSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_PRESCEM01GRPACLK (_TIMER_CFG_CLKSEL_PRESCEM01GRPACLK << 8) /**< Shifted mode PRESCEM01GRPACLK for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_CC1 (_TIMER_CFG_CLKSEL_CC1 << 8) /**< Shifted mode CC1 for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_TIMEROUF (_TIMER_CFG_CLKSEL_TIMEROUF << 8) /**< Shifted mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN (0x1UL << 10) /**< PWM output retimed enable */ +#define _TIMER_CFG_RETIMEEN_SHIFT 10 /**< Shift value for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_MASK 0x400UL /**< Bit mask for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DEFAULT (_TIMER_CFG_RETIMEEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DISABLE (_TIMER_CFG_RETIMEEN_DISABLE << 10) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_ENABLE (_TIMER_CFG_RETIMEEN_ENABLE << 10) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT (0x1UL << 11) /**< Disable Timer Start/Stop/Reload output */ +#define _TIMER_CFG_DISSYNCOUT_SHIFT 11 /**< Shift value for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_MASK 0x800UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_EN 0x00000000UL /**< Mode EN for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_DIS 0x00000001UL /**< Mode DIS for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DEFAULT (_TIMER_CFG_DISSYNCOUT_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_EN (_TIMER_CFG_DISSYNCOUT_EN << 11) /**< Shifted mode EN for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DIS (_TIMER_CFG_DISSYNCOUT_DIS << 11) /**< Shifted mode DIS for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL (0x1UL << 12) /**< PWM output retime select */ +#define _TIMER_CFG_RETIMESEL_SHIFT 12 /**< Shift value for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_MASK 0x1000UL /**< Bit mask for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL_DEFAULT (_TIMER_CFG_RETIMESEL_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI (0x1UL << 16) /**< Always Track Inputs */ +#define _TIMER_CFG_ATI_SHIFT 16 /**< Shift value for TIMER_ATI */ +#define _TIMER_CFG_ATI_MASK 0x10000UL /**< Bit mask for TIMER_ATI */ +#define _TIMER_CFG_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI_DEFAULT (_TIMER_CFG_ATI_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST (0x1UL << 17) /**< Reload-Start Sets COIST */ +#define _TIMER_CFG_RSSCOIST_SHIFT 17 /**< Shift value for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_MASK 0x20000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST_DEFAULT (_TIMER_CFG_RSSCOIST_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_SHIFT 18 /**< Shift value for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_MASK 0xFFC0000UL /**< Bit mask for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV8 0x00000007UL /**< Mode DIV8 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV16 0x0000000FUL /**< Mode DIV16 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV32 0x0000001FUL /**< Mode DIV32 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV64 0x0000003FUL /**< Mode DIV64 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV128 0x0000007FUL /**< Mode DIV128 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV256 0x000000FFUL /**< Mode DIV256 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV512 0x000001FFUL /**< Mode DIV512 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1024 0x000003FFUL /**< Mode DIV1024 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DEFAULT (_TIMER_CFG_PRESC_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1 (_TIMER_CFG_PRESC_DIV1 << 18) /**< Shifted mode DIV1 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV2 (_TIMER_CFG_PRESC_DIV2 << 18) /**< Shifted mode DIV2 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV4 (_TIMER_CFG_PRESC_DIV4 << 18) /**< Shifted mode DIV4 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV8 (_TIMER_CFG_PRESC_DIV8 << 18) /**< Shifted mode DIV8 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV16 (_TIMER_CFG_PRESC_DIV16 << 18) /**< Shifted mode DIV16 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV32 (_TIMER_CFG_PRESC_DIV32 << 18) /**< Shifted mode DIV32 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV64 (_TIMER_CFG_PRESC_DIV64 << 18) /**< Shifted mode DIV64 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV128 (_TIMER_CFG_PRESC_DIV128 << 18) /**< Shifted mode DIV128 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV256 (_TIMER_CFG_PRESC_DIV256 << 18) /**< Shifted mode DIV256 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV512 (_TIMER_CFG_PRESC_DIV512 << 18) /**< Shifted mode DIV512 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1024 (_TIMER_CFG_PRESC_DIV1024 << 18) /**< Shifted mode DIV1024 for TIMER_CFG */ /* Bit fields for TIMER CTRL */ -#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ -#define _TIMER_CTRL_MASK 0x0000001FUL /**< Mask for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_SHIFT 0 /**< Shift value for TIMER_RISEA */ -#define _TIMER_CTRL_RISEA_MASK 0x3UL /**< Bit mask for TIMER_RISEA */ -#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 0) /**< Shifted mode NONE for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 0) /**< Shifted mode START for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 0) /**< Shifted mode STOP for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 0) /**< Shifted mode RELOADSTART for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_SHIFT 2 /**< Shift value for TIMER_FALLA */ -#define _TIMER_CTRL_FALLA_MASK 0xCUL /**< Bit mask for TIMER_FALLA */ -#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 2) /**< Shifted mode NONE for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 2) /**< Shifted mode START for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 2) /**< Shifted mode STOP for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 2) /**< Shifted mode RELOADSTART for TIMER_CTRL */ -#define TIMER_CTRL_X2CNT (0x1UL << 4) /**< 2x Count Mode */ -#define _TIMER_CTRL_X2CNT_SHIFT 4 /**< Shift value for TIMER_X2CNT */ -#define _TIMER_CTRL_X2CNT_MASK 0x10UL /**< Bit mask for TIMER_X2CNT */ -#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ -#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ +#define _TIMER_CTRL_MASK 0x0000001FUL /**< Mask for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_SHIFT 0 /**< Shift value for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_MASK 0x3UL /**< Bit mask for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 0) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 0) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 0) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 0) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_SHIFT 2 /**< Shift value for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_MASK 0xCUL /**< Bit mask for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 2) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 2) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 2) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 2) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT (0x1UL << 4) /**< 2x Count Mode */ +#define _TIMER_CTRL_X2CNT_SHIFT 4 /**< Shift value for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_MASK 0x10UL /**< Bit mask for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ /* Bit fields for TIMER CMD */ -#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ -#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ -#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ -#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ -#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ -#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ -#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ -#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ -#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ -#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ -#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ -#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ +#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ +#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ /* Bit fields for TIMER STATUS */ -#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ -#define _TIMER_STATUS_MASK 0x07070777UL /**< Mask for TIMER_STATUS */ -#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ -#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ -#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ -#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ -#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ -#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ -#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ -#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ -#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ -#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ -#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOP Buffer Valid */ -#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ -#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ -#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_TIMERLOCKSTATUS (0x1UL << 4) /**< Timer lock status */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_SHIFT 4 /**< Shift value for TIMER_TIMERLOCKSTATUS */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_MASK 0x10UL /**< Bit mask for TIMER_TIMERLOCKSTATUS */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ -#define TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT (_TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED << 4) /**< Shifted mode UNLOCKED for TIMER_STATUS */ -#define TIMER_STATUS_TIMERLOCKSTATUS_LOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_LOCKED << 4) /**< Shifted mode LOCKED for TIMER_STATUS */ -#define TIMER_STATUS_DTILOCKSTATUS (0x1UL << 5) /**< DTI lock status */ -#define _TIMER_STATUS_DTILOCKSTATUS_SHIFT 5 /**< Shift value for TIMER_DTILOCKSTATUS */ -#define _TIMER_STATUS_DTILOCKSTATUS_MASK 0x20UL /**< Bit mask for TIMER_DTILOCKSTATUS */ -#define _TIMER_STATUS_DTILOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_DTILOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ -#define _TIMER_STATUS_DTILOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ -#define TIMER_STATUS_DTILOCKSTATUS_DEFAULT (_TIMER_STATUS_DTILOCKSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_DTILOCKSTATUS_UNLOCKED (_TIMER_STATUS_DTILOCKSTATUS_UNLOCKED << 5) /**< Shifted mode UNLOCKED for TIMER_STATUS */ -#define TIMER_STATUS_DTILOCKSTATUS_LOCKED (_TIMER_STATUS_DTILOCKSTATUS_LOCKED << 5) /**< Shifted mode LOCKED for TIMER_STATUS */ -#define TIMER_STATUS_SYNCBUSY (0x1UL << 6) /**< Sync Busy */ -#define _TIMER_STATUS_SYNCBUSY_SHIFT 6 /**< Shift value for TIMER_SYNCBUSY */ -#define _TIMER_STATUS_SYNCBUSY_MASK 0x40UL /**< Bit mask for TIMER_SYNCBUSY */ -#define _TIMER_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_SYNCBUSY_DEFAULT (_TIMER_STATUS_SYNCBUSY_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV0 (0x1UL << 8) /**< Output Compare Buffer Valid */ -#define _TIMER_STATUS_OCBV0_SHIFT 8 /**< Shift value for TIMER_OCBV0 */ -#define _TIMER_STATUS_OCBV0_MASK 0x100UL /**< Bit mask for TIMER_OCBV0 */ -#define _TIMER_STATUS_OCBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV0_DEFAULT (_TIMER_STATUS_OCBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV1 (0x1UL << 9) /**< Output Compare Buffer Valid */ -#define _TIMER_STATUS_OCBV1_SHIFT 9 /**< Shift value for TIMER_OCBV1 */ -#define _TIMER_STATUS_OCBV1_MASK 0x200UL /**< Bit mask for TIMER_OCBV1 */ -#define _TIMER_STATUS_OCBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV1_DEFAULT (_TIMER_STATUS_OCBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV2 (0x1UL << 10) /**< Output Compare Buffer Valid */ -#define _TIMER_STATUS_OCBV2_SHIFT 10 /**< Shift value for TIMER_OCBV2 */ -#define _TIMER_STATUS_OCBV2_MASK 0x400UL /**< Bit mask for TIMER_OCBV2 */ -#define _TIMER_STATUS_OCBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV2_DEFAULT (_TIMER_STATUS_OCBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY0 (0x1UL << 16) /**< Input capture fifo empty */ -#define _TIMER_STATUS_ICFEMPTY0_SHIFT 16 /**< Shift value for TIMER_ICFEMPTY0 */ -#define _TIMER_STATUS_ICFEMPTY0_MASK 0x10000UL /**< Bit mask for TIMER_ICFEMPTY0 */ -#define _TIMER_STATUS_ICFEMPTY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY0_DEFAULT (_TIMER_STATUS_ICFEMPTY0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY1 (0x1UL << 17) /**< Input capture fifo empty */ -#define _TIMER_STATUS_ICFEMPTY1_SHIFT 17 /**< Shift value for TIMER_ICFEMPTY1 */ -#define _TIMER_STATUS_ICFEMPTY1_MASK 0x20000UL /**< Bit mask for TIMER_ICFEMPTY1 */ -#define _TIMER_STATUS_ICFEMPTY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY1_DEFAULT (_TIMER_STATUS_ICFEMPTY1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY2 (0x1UL << 18) /**< Input capture fifo empty */ -#define _TIMER_STATUS_ICFEMPTY2_SHIFT 18 /**< Shift value for TIMER_ICFEMPTY2 */ -#define _TIMER_STATUS_ICFEMPTY2_MASK 0x40000UL /**< Bit mask for TIMER_ICFEMPTY2 */ -#define _TIMER_STATUS_ICFEMPTY2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY2_DEFAULT (_TIMER_STATUS_ICFEMPTY2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< Compare/Capture Polarity */ -#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ -#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ -#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< Compare/Capture Polarity */ -#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ -#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ -#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< Compare/Capture Polarity */ -#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ -#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ -#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ +#define _TIMER_STATUS_MASK 0x07070777UL /**< Mask for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOP Buffer Valid */ +#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS (0x1UL << 4) /**< Timer lock status */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_SHIFT 4 /**< Shift value for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_MASK 0x10UL /**< Bit mask for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT (_TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED << 4) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_LOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_LOCKED << 4) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS (0x1UL << 5) /**< DTI lock status */ +#define _TIMER_STATUS_DTILOCKSTATUS_SHIFT 5 /**< Shift value for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_MASK 0x20UL /**< Bit mask for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_DEFAULT (_TIMER_STATUS_DTILOCKSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_UNLOCKED (_TIMER_STATUS_DTILOCKSTATUS_UNLOCKED << 5) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_LOCKED (_TIMER_STATUS_DTILOCKSTATUS_LOCKED << 5) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY (0x1UL << 6) /**< Sync Busy */ +#define _TIMER_STATUS_SYNCBUSY_SHIFT 6 /**< Shift value for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_MASK 0x40UL /**< Bit mask for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY_DEFAULT (_TIMER_STATUS_SYNCBUSY_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0 (0x1UL << 8) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV0_SHIFT 8 /**< Shift value for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_MASK 0x100UL /**< Bit mask for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0_DEFAULT (_TIMER_STATUS_OCBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1 (0x1UL << 9) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV1_SHIFT 9 /**< Shift value for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_MASK 0x200UL /**< Bit mask for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1_DEFAULT (_TIMER_STATUS_OCBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2 (0x1UL << 10) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV2_SHIFT 10 /**< Shift value for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_MASK 0x400UL /**< Bit mask for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2_DEFAULT (_TIMER_STATUS_OCBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0 (0x1UL << 16) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY0_SHIFT 16 /**< Shift value for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_MASK 0x10000UL /**< Bit mask for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0_DEFAULT (_TIMER_STATUS_ICFEMPTY0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1 (0x1UL << 17) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY1_SHIFT 17 /**< Shift value for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_MASK 0x20000UL /**< Bit mask for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1_DEFAULT (_TIMER_STATUS_ICFEMPTY1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2 (0x1UL << 18) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY2_SHIFT 18 /**< Shift value for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_MASK 0x40000UL /**< Bit mask for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2_DEFAULT (_TIMER_STATUS_ICFEMPTY2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ /* Bit fields for TIMER IF */ -#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ -#define _TIMER_IF_MASK 0x07770077UL /**< Mask for TIMER_IF */ -#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ -#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ -#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ -#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ -#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ -#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ -#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ -#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ -#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ -#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC0 (0x1UL << 4) /**< Capture Compare Channel 0 Interrupt Flag */ -#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ -#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ -#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC1 (0x1UL << 5) /**< Capture Compare Channel 1 Interrupt Flag */ -#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ -#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ -#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC2 (0x1UL << 6) /**< Capture Compare Channel 2 Interrupt Flag */ -#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ -#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ -#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL0 (0x1UL << 16) /**< Input Capture Watermark Level Full */ -#define _TIMER_IF_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ -#define _TIMER_IF_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ -#define _TIMER_IF_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL0_DEFAULT (_TIMER_IF_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL1 (0x1UL << 17) /**< Input Capture Watermark Level Full */ -#define _TIMER_IF_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ -#define _TIMER_IF_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ -#define _TIMER_IF_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL1_DEFAULT (_TIMER_IF_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL2 (0x1UL << 18) /**< Input Capture Watermark Level Full */ -#define _TIMER_IF_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ -#define _TIMER_IF_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ -#define _TIMER_IF_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL2_DEFAULT (_TIMER_IF_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF0 (0x1UL << 20) /**< Input Capture FIFO overflow */ -#define _TIMER_IF_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ -#define _TIMER_IF_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ -#define _TIMER_IF_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF0_DEFAULT (_TIMER_IF_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF1 (0x1UL << 21) /**< Input Capture FIFO overflow */ -#define _TIMER_IF_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ -#define _TIMER_IF_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ -#define _TIMER_IF_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF1_DEFAULT (_TIMER_IF_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF2 (0x1UL << 22) /**< Input Capture FIFO overflow */ -#define _TIMER_IF_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ -#define _TIMER_IF_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ -#define _TIMER_IF_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF2_DEFAULT (_TIMER_IF_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF0 (0x1UL << 24) /**< Input capture FIFO underflow */ -#define _TIMER_IF_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ -#define _TIMER_IF_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ -#define _TIMER_IF_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF0_DEFAULT (_TIMER_IF_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF1 (0x1UL << 25) /**< Input capture FIFO underflow */ -#define _TIMER_IF_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ -#define _TIMER_IF_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ -#define _TIMER_IF_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF1_DEFAULT (_TIMER_IF_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF2 (0x1UL << 26) /**< Input capture FIFO underflow */ -#define _TIMER_IF_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ -#define _TIMER_IF_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ -#define _TIMER_IF_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF2_DEFAULT (_TIMER_IF_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IF */ +#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ +#define _TIMER_IF_MASK 0x07770077UL /**< Mask for TIMER_IF */ +#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0 (0x1UL << 4) /**< Capture Compare Channel 0 Interrupt Flag */ +#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1 (0x1UL << 5) /**< Capture Compare Channel 1 Interrupt Flag */ +#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2 (0x1UL << 6) /**< Capture Compare Channel 2 Interrupt Flag */ +#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0 (0x1UL << 16) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0_DEFAULT (_TIMER_IF_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1 (0x1UL << 17) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1_DEFAULT (_TIMER_IF_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2 (0x1UL << 18) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2_DEFAULT (_TIMER_IF_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0 (0x1UL << 20) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0_DEFAULT (_TIMER_IF_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1 (0x1UL << 21) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1_DEFAULT (_TIMER_IF_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2 (0x1UL << 22) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2_DEFAULT (_TIMER_IF_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0 (0x1UL << 24) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0_DEFAULT (_TIMER_IF_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1 (0x1UL << 25) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1_DEFAULT (_TIMER_IF_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2 (0x1UL << 26) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2_DEFAULT (_TIMER_IF_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IF */ /* Bit fields for TIMER IEN */ -#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ -#define _TIMER_IEN_MASK 0x07770077UL /**< Mask for TIMER_IEN */ -#define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ -#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ -#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ -#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */ -#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ -#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ -#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */ -#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ -#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ -#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ -#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ -#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ -#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ -#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ -#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ -#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ -#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ -#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ -#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL0 (0x1UL << 16) /**< ICFWLFULL0 Interrupt Enable */ -#define _TIMER_IEN_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ -#define _TIMER_IEN_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ -#define _TIMER_IEN_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL0_DEFAULT (_TIMER_IEN_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL1 (0x1UL << 17) /**< ICFWLFULL1 Interrupt Enable */ -#define _TIMER_IEN_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ -#define _TIMER_IEN_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ -#define _TIMER_IEN_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL1_DEFAULT (_TIMER_IEN_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL2 (0x1UL << 18) /**< ICFWLFULL2 Interrupt Enable */ -#define _TIMER_IEN_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ -#define _TIMER_IEN_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ -#define _TIMER_IEN_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL2_DEFAULT (_TIMER_IEN_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF0 (0x1UL << 20) /**< ICFOF0 Interrupt Enable */ -#define _TIMER_IEN_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ -#define _TIMER_IEN_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ -#define _TIMER_IEN_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF0_DEFAULT (_TIMER_IEN_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF1 (0x1UL << 21) /**< ICFOF1 Interrupt Enable */ -#define _TIMER_IEN_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ -#define _TIMER_IEN_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ -#define _TIMER_IEN_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF1_DEFAULT (_TIMER_IEN_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF2 (0x1UL << 22) /**< ICFOF2 Interrupt Enable */ -#define _TIMER_IEN_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ -#define _TIMER_IEN_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ -#define _TIMER_IEN_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF2_DEFAULT (_TIMER_IEN_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF0 (0x1UL << 24) /**< ICFUF0 Interrupt Enable */ -#define _TIMER_IEN_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ -#define _TIMER_IEN_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ -#define _TIMER_IEN_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF0_DEFAULT (_TIMER_IEN_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF1 (0x1UL << 25) /**< ICFUF1 Interrupt Enable */ -#define _TIMER_IEN_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ -#define _TIMER_IEN_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ -#define _TIMER_IEN_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF1_DEFAULT (_TIMER_IEN_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF2 (0x1UL << 26) /**< ICFUF2 Interrupt Enable */ -#define _TIMER_IEN_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ -#define _TIMER_IEN_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ -#define _TIMER_IEN_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF2_DEFAULT (_TIMER_IEN_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ +#define _TIMER_IEN_MASK 0x07770077UL /**< Mask for TIMER_IEN */ +#define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ +#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */ +#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */ +#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0 (0x1UL << 16) /**< ICFWLFULL0 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0_DEFAULT (_TIMER_IEN_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1 (0x1UL << 17) /**< ICFWLFULL1 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1_DEFAULT (_TIMER_IEN_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2 (0x1UL << 18) /**< ICFWLFULL2 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2_DEFAULT (_TIMER_IEN_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0 (0x1UL << 20) /**< ICFOF0 Interrupt Enable */ +#define _TIMER_IEN_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0_DEFAULT (_TIMER_IEN_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1 (0x1UL << 21) /**< ICFOF1 Interrupt Enable */ +#define _TIMER_IEN_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1_DEFAULT (_TIMER_IEN_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2 (0x1UL << 22) /**< ICFOF2 Interrupt Enable */ +#define _TIMER_IEN_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2_DEFAULT (_TIMER_IEN_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0 (0x1UL << 24) /**< ICFUF0 Interrupt Enable */ +#define _TIMER_IEN_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0_DEFAULT (_TIMER_IEN_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1 (0x1UL << 25) /**< ICFUF1 Interrupt Enable */ +#define _TIMER_IEN_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1_DEFAULT (_TIMER_IEN_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2 (0x1UL << 26) /**< ICFUF2 Interrupt Enable */ +#define _TIMER_IEN_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2_DEFAULT (_TIMER_IEN_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IEN */ /* Bit fields for TIMER TOP */ -#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ -#define _TIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOP */ -#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ -#define _TIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ -#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ -#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ +#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ +#define _TIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _TIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ +#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ /* Bit fields for TIMER TOPB */ -#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ -#define _TIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOPB */ -#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ -#define _TIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ -#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ -#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ +#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ +#define _TIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ +#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ /* Bit fields for TIMER CNT */ -#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ -#define _TIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CNT */ -#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ -#define _TIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ -#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ -#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ +#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ +#define _TIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _TIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ +#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ /* Bit fields for TIMER LOCK */ -#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ -#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ -#define _TIMER_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ -#define _TIMER_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ -#define _TIMER_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ -#define _TIMER_LOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ -#define TIMER_LOCK_LOCKKEY_DEFAULT (_TIMER_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ -#define TIMER_LOCK_LOCKKEY_UNLOCK (_TIMER_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ +#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ +#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_DEFAULT (_TIMER_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_UNLOCK (_TIMER_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ /* Bit fields for TIMER EN */ -#define _TIMER_EN_RESETVALUE 0x00000000UL /**< Default value for TIMER_EN */ -#define _TIMER_EN_MASK 0x00000003UL /**< Mask for TIMER_EN */ -#define TIMER_EN_EN (0x1UL << 0) /**< Timer Module Enable */ -#define _TIMER_EN_EN_SHIFT 0 /**< Shift value for TIMER_EN */ -#define _TIMER_EN_EN_MASK 0x1UL /**< Bit mask for TIMER_EN */ -#define _TIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ -#define TIMER_EN_EN_DEFAULT (_TIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_EN */ -#define TIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _TIMER_EN_DISABLING_SHIFT 1 /**< Shift value for TIMER_DISABLING */ -#define _TIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for TIMER_DISABLING */ -#define _TIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ -#define TIMER_EN_DISABLING_DEFAULT (_TIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_EN */ +#define _TIMER_EN_RESETVALUE 0x00000000UL /**< Default value for TIMER_EN */ +#define _TIMER_EN_MASK 0x00000003UL /**< Mask for TIMER_EN */ +#define TIMER_EN_EN (0x1UL << 0) /**< Timer Module Enable */ +#define _TIMER_EN_EN_SHIFT 0 /**< Shift value for TIMER_EN */ +#define _TIMER_EN_EN_MASK 0x1UL /**< Bit mask for TIMER_EN */ +#define _TIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ +#define TIMER_EN_EN_DEFAULT (_TIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_EN */ +#define TIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _TIMER_EN_DISABLING_SHIFT 1 /**< Shift value for TIMER_DISABLING */ +#define _TIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for TIMER_DISABLING */ +#define _TIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ +#define TIMER_EN_DISABLING_DEFAULT (_TIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_EN */ /* Bit fields for TIMER CC_CFG */ -#define _TIMER_CC_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MASK 0x003E0013UL /**< Mask for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ -#define _TIMER_CC_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ -#define _TIMER_CC_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_DEFAULT (_TIMER_CC_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_OFF (_TIMER_CC_CFG_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_INPUTCAPTURE (_TIMER_CC_CFG_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_OUTPUTCOMPARE (_TIMER_CC_CFG_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_PWM (_TIMER_CC_CFG_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CFG */ -#define TIMER_CC_CFG_COIST (0x1UL << 4) /**< Compare Output Initial State */ -#define _TIMER_CC_CFG_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ -#define _TIMER_CC_CFG_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ -#define _TIMER_CC_CFG_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_COIST_DEFAULT (_TIMER_CC_CFG_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_SHIFT 17 /**< Shift value for TIMER_INSEL */ -#define _TIMER_CC_CFG_INSEL_MASK 0x60000UL /**< Bit mask for TIMER_INSEL */ -#define _TIMER_CC_CFG_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_PRSSYNC 0x00000001UL /**< Mode PRSSYNC for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL 0x00000002UL /**< Mode PRSASYNCLEVEL for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_PRSASYNCPULSE 0x00000003UL /**< Mode PRSASYNCPULSE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_DEFAULT (_TIMER_CC_CFG_INSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_PIN (_TIMER_CC_CFG_INSEL_PIN << 17) /**< Shifted mode PIN for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_PRSSYNC (_TIMER_CC_CFG_INSEL_PRSSYNC << 17) /**< Shifted mode PRSSYNC for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_PRSASYNCLEVEL (_TIMER_CC_CFG_INSEL_PRSASYNCLEVEL << 17) /**< Shifted mode PRSASYNCLEVEL for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_PRSASYNCPULSE (_TIMER_CC_CFG_INSEL_PRSASYNCPULSE << 17) /**< Shifted mode PRSASYNCPULSE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_PRSCONF (0x1UL << 19) /**< PRS Configuration */ -#define _TIMER_CC_CFG_PRSCONF_SHIFT 19 /**< Shift value for TIMER_PRSCONF */ -#define _TIMER_CC_CFG_PRSCONF_MASK 0x80000UL /**< Bit mask for TIMER_PRSCONF */ -#define _TIMER_CC_CFG_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CFG */ -#define TIMER_CC_CFG_PRSCONF_DEFAULT (_TIMER_CC_CFG_PRSCONF_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_PRSCONF_PULSE (_TIMER_CC_CFG_PRSCONF_PULSE << 19) /**< Shifted mode PULSE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_PRSCONF_LEVEL (_TIMER_CC_CFG_PRSCONF_LEVEL << 19) /**< Shifted mode LEVEL for TIMER_CC_CFG */ -#define TIMER_CC_CFG_FILT (0x1UL << 20) /**< Digital Filter */ -#define _TIMER_CC_CFG_FILT_SHIFT 20 /**< Shift value for TIMER_FILT */ -#define _TIMER_CC_CFG_FILT_MASK 0x100000UL /**< Bit mask for TIMER_FILT */ -#define _TIMER_CC_CFG_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_FILT_DEFAULT (_TIMER_CC_CFG_FILT_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_FILT_DISABLE (_TIMER_CC_CFG_FILT_DISABLE << 20) /**< Shifted mode DISABLE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_FILT_ENABLE (_TIMER_CC_CFG_FILT_ENABLE << 20) /**< Shifted mode ENABLE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_ICFWL (0x1UL << 21) /**< Input Capture FIFO watermark level */ -#define _TIMER_CC_CFG_ICFWL_SHIFT 21 /**< Shift value for TIMER_ICFWL */ -#define _TIMER_CC_CFG_ICFWL_MASK 0x200000UL /**< Bit mask for TIMER_ICFWL */ -#define _TIMER_CC_CFG_ICFWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_ICFWL_DEFAULT (_TIMER_CC_CFG_ICFWL_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MASK 0x003E0013UL /**< Mask for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_DEFAULT (_TIMER_CC_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OFF (_TIMER_CC_CFG_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_INPUTCAPTURE (_TIMER_CC_CFG_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OUTPUTCOMPARE (_TIMER_CC_CFG_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_PWM (_TIMER_CC_CFG_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _TIMER_CC_CFG_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST_DEFAULT (_TIMER_CC_CFG_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_SHIFT 17 /**< Shift value for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_MASK 0x60000UL /**< Bit mask for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSSYNC 0x00000001UL /**< Mode PRSSYNC for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL 0x00000002UL /**< Mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCPULSE 0x00000003UL /**< Mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_DEFAULT (_TIMER_CC_CFG_INSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PIN (_TIMER_CC_CFG_INSEL_PIN << 17) /**< Shifted mode PIN for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSSYNC (_TIMER_CC_CFG_INSEL_PRSSYNC << 17) /**< Shifted mode PRSSYNC for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCLEVEL (_TIMER_CC_CFG_INSEL_PRSASYNCLEVEL << 17) /**< Shifted mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCPULSE (_TIMER_CC_CFG_INSEL_PRSASYNCPULSE << 17) /**< Shifted mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF (0x1UL << 19) /**< PRS Configuration */ +#define _TIMER_CC_CFG_PRSCONF_SHIFT 19 /**< Shift value for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_MASK 0x80000UL /**< Bit mask for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_DEFAULT (_TIMER_CC_CFG_PRSCONF_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_PULSE (_TIMER_CC_CFG_PRSCONF_PULSE << 19) /**< Shifted mode PULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_LEVEL (_TIMER_CC_CFG_PRSCONF_LEVEL << 19) /**< Shifted mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT (0x1UL << 20) /**< Digital Filter */ +#define _TIMER_CC_CFG_FILT_SHIFT 20 /**< Shift value for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_MASK 0x100000UL /**< Bit mask for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DEFAULT (_TIMER_CC_CFG_FILT_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DISABLE (_TIMER_CC_CFG_FILT_DISABLE << 20) /**< Shifted mode DISABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_ENABLE (_TIMER_CC_CFG_FILT_ENABLE << 20) /**< Shifted mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL (0x1UL << 21) /**< Input Capture FIFO watermark level */ +#define _TIMER_CC_CFG_ICFWL_SHIFT 21 /**< Shift value for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_MASK 0x200000UL /**< Bit mask for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL_DEFAULT (_TIMER_CC_CFG_ICFWL_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ /* Bit fields for TIMER CC_CTRL */ -#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_MASK 0x0F003F04UL /**< Mask for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ -#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ -#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ -#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ -#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ -#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ -#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ -#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ -#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ -#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ -#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ -#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL*/ -#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MASK 0x0F003F04UL /**< Mask for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL*/ +#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ /* Bit fields for TIMER CC_OC */ -#define _TIMER_CC_OC_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OC */ -#define _TIMER_CC_OC_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OC */ -#define _TIMER_CC_OC_OC_SHIFT 0 /**< Shift value for TIMER_OC */ -#define _TIMER_CC_OC_OC_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OC */ -#define _TIMER_CC_OC_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OC */ -#define TIMER_CC_OC_OC_DEFAULT (_TIMER_CC_OC_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OC */ +#define _TIMER_CC_OC_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OC */ +#define _TIMER_CC_OC_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OC */ +#define _TIMER_CC_OC_OC_SHIFT 0 /**< Shift value for TIMER_OC */ +#define _TIMER_CC_OC_OC_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OC */ +#define _TIMER_CC_OC_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OC */ +#define TIMER_CC_OC_OC_DEFAULT (_TIMER_CC_OC_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OC */ /* Bit fields for TIMER CC_OCB */ -#define _TIMER_CC_OCB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OCB */ -#define _TIMER_CC_OCB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OCB */ -#define _TIMER_CC_OCB_OCB_SHIFT 0 /**< Shift value for TIMER_OCB */ -#define _TIMER_CC_OCB_OCB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OCB */ -#define _TIMER_CC_OCB_OCB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OCB */ -#define TIMER_CC_OCB_OCB_DEFAULT (_TIMER_CC_OCB_OCB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_OCB_SHIFT 0 /**< Shift value for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OCB */ +#define TIMER_CC_OCB_OCB_DEFAULT (_TIMER_CC_OCB_OCB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OCB */ /* Bit fields for TIMER CC_ICF */ -#define _TIMER_CC_ICF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICF */ -#define _TIMER_CC_ICF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICF */ -#define _TIMER_CC_ICF_ICF_SHIFT 0 /**< Shift value for TIMER_ICF */ -#define _TIMER_CC_ICF_ICF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICF */ -#define _TIMER_CC_ICF_ICF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICF */ -#define TIMER_CC_ICF_ICF_DEFAULT (_TIMER_CC_ICF_ICF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_ICF_SHIFT 0 /**< Shift value for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICF */ +#define TIMER_CC_ICF_ICF_DEFAULT (_TIMER_CC_ICF_ICF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICF */ /* Bit fields for TIMER CC_ICOF */ -#define _TIMER_CC_ICOF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICOF */ -#define _TIMER_CC_ICOF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICOF */ -#define _TIMER_CC_ICOF_ICOF_SHIFT 0 /**< Shift value for TIMER_ICOF */ -#define _TIMER_CC_ICOF_ICOF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICOF */ -#define _TIMER_CC_ICOF_ICOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICOF */ -#define TIMER_CC_ICOF_ICOF_DEFAULT (_TIMER_CC_ICOF_ICOF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_ICOF_SHIFT 0 /**< Shift value for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICOF */ +#define TIMER_CC_ICOF_ICOF_DEFAULT (_TIMER_CC_ICOF_ICOF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICOF */ /* Bit fields for TIMER DTCFG */ -#define _TIMER_DTCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCFG */ -#define _TIMER_DTCFG_MASK 0x00000E03UL /**< Mask for TIMER_DTCFG */ -#define TIMER_DTCFG_DTEN (0x1UL << 0) /**< DTI Enable */ -#define _TIMER_DTCFG_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ -#define _TIMER_DTCFG_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ -#define _TIMER_DTCFG_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTEN_DEFAULT (_TIMER_DTCFG_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ -#define _TIMER_DTCFG_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ -#define _TIMER_DTCFG_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ -#define _TIMER_DTCFG_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define _TIMER_DTCFG_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCFG */ -#define _TIMER_DTCFG_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCFG */ -#define TIMER_DTCFG_DTDAS_DEFAULT (_TIMER_DTCFG_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTDAS_NORESTART (_TIMER_DTCFG_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCFG */ -#define TIMER_DTCFG_DTDAS_RESTART (_TIMER_DTCFG_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCFG */ -#define TIMER_DTCFG_DTAR (0x1UL << 9) /**< DTI Always Run */ -#define _TIMER_DTCFG_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ -#define _TIMER_DTCFG_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ -#define _TIMER_DTCFG_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTAR_DEFAULT (_TIMER_DTCFG_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ -#define _TIMER_DTCFG_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ -#define _TIMER_DTCFG_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ -#define _TIMER_DTCFG_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTFATS_DEFAULT (_TIMER_DTCFG_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTPRSEN (0x1UL << 11) /**< DTI PRS Source Enable */ -#define _TIMER_DTCFG_DTPRSEN_SHIFT 11 /**< Shift value for TIMER_DTPRSEN */ -#define _TIMER_DTCFG_DTPRSEN_MASK 0x800UL /**< Bit mask for TIMER_DTPRSEN */ -#define _TIMER_DTCFG_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTPRSEN_DEFAULT (_TIMER_DTCFG_DTPRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define _TIMER_DTCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCFG */ +#define _TIMER_DTCFG_MASK 0x00000E03UL /**< Mask for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _TIMER_DTCFG_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN_DEFAULT (_TIMER_DTCFG_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _TIMER_DTCFG_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_DEFAULT (_TIMER_DTCFG_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_NORESTART (_TIMER_DTCFG_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_RESTART (_TIMER_DTCFG_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _TIMER_DTCFG_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR_DEFAULT (_TIMER_DTCFG_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _TIMER_DTCFG_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS_DEFAULT (_TIMER_DTCFG_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN (0x1UL << 11) /**< DTI PRS Source Enable */ +#define _TIMER_DTCFG_DTPRSEN_SHIFT 11 /**< Shift value for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_MASK 0x800UL /**< Bit mask for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN_DEFAULT (_TIMER_DTCFG_DTPRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_DTCFG */ /* Bit fields for TIMER DTTIMECFG */ -#define _TIMER_DTTIMECFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIMECFG */ -#define _TIMER_DTTIMECFG_MASK 0x003FFFFFUL /**< Mask for TIMER_DTTIMECFG */ -#define _TIMER_DTTIMECFG_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ -#define _TIMER_DTTIMECFG_DTPRESC_MASK 0x3FFUL /**< Bit mask for TIMER_DTPRESC */ -#define _TIMER_DTTIMECFG_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ -#define TIMER_DTTIMECFG_DTPRESC_DEFAULT (_TIMER_DTTIMECFG_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ -#define _TIMER_DTTIMECFG_DTRISET_SHIFT 10 /**< Shift value for TIMER_DTRISET */ -#define _TIMER_DTTIMECFG_DTRISET_MASK 0xFC00UL /**< Bit mask for TIMER_DTRISET */ -#define _TIMER_DTTIMECFG_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ -#define TIMER_DTTIMECFG_DTRISET_DEFAULT (_TIMER_DTTIMECFG_DTRISET_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ -#define _TIMER_DTTIMECFG_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ -#define _TIMER_DTTIMECFG_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ -#define _TIMER_DTTIMECFG_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ -#define TIMER_DTTIMECFG_DTFALLT_DEFAULT (_TIMER_DTTIMECFG_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_MASK 0x003FFFFFUL /**< Mask for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_MASK 0x3FFUL /**< Bit mask for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTPRESC_DEFAULT (_TIMER_DTTIMECFG_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTRISET_SHIFT 10 /**< Shift value for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_MASK 0xFC00UL /**< Bit mask for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTRISET_DEFAULT (_TIMER_DTTIMECFG_DTRISET_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTFALLT_DEFAULT (_TIMER_DTTIMECFG_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ /* Bit fields for TIMER DTFCFG */ -#define _TIMER_DTFCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_MASK 0x1F030000UL /**< Mask for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ -#define _TIMER_DTFCFG_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ -#define _TIMER_DTFCFG_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_DEFAULT (_TIMER_DTFCFG_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_NONE (_TIMER_DTFCFG_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_INACTIVE (_TIMER_DTFCFG_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_CLEAR (_TIMER_DTFCFG_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_TRISTATE (_TIMER_DTFCFG_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ -#define _TIMER_DTFCFG_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ -#define _TIMER_DTFCFG_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ -#define _TIMER_DTFCFG_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTPRS0FEN_DEFAULT (_TIMER_DTFCFG_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ -#define _TIMER_DTFCFG_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ -#define _TIMER_DTFCFG_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ -#define _TIMER_DTFCFG_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTPRS1FEN_DEFAULT (_TIMER_DTFCFG_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ -#define _TIMER_DTFCFG_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ -#define _TIMER_DTFCFG_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ -#define _TIMER_DTFCFG_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTDBGFEN_DEFAULT (_TIMER_DTFCFG_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ -#define _TIMER_DTFCFG_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ -#define _TIMER_DTFCFG_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ -#define _TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT (_TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTEM23FEN (0x1UL << 28) /**< DTI EM23 Fault Enable */ -#define _TIMER_DTFCFG_DTEM23FEN_SHIFT 28 /**< Shift value for TIMER_DTEM23FEN */ -#define _TIMER_DTFCFG_DTEM23FEN_MASK 0x10000000UL /**< Bit mask for TIMER_DTEM23FEN */ -#define _TIMER_DTFCFG_DTEM23FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTEM23FEN_DEFAULT (_TIMER_DTFCFG_DTEM23FEN_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_MASK 0x1F030000UL /**< Mask for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_DEFAULT (_TIMER_DTFCFG_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_NONE (_TIMER_DTFCFG_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_INACTIVE (_TIMER_DTFCFG_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_CLEAR (_TIMER_DTFCFG_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_TRISTATE (_TIMER_DTFCFG_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN_DEFAULT (_TIMER_DTFCFG_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN_DEFAULT (_TIMER_DTFCFG_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _TIMER_DTFCFG_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN_DEFAULT (_TIMER_DTFCFG_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT (_TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN (0x1UL << 28) /**< DTI EM23 Fault Enable */ +#define _TIMER_DTFCFG_DTEM23FEN_SHIFT 28 /**< Shift value for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_MASK 0x10000000UL /**< Bit mask for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN_DEFAULT (_TIMER_DTFCFG_DTEM23FEN_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ /* Bit fields for TIMER DTCTRL */ -#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ -#define _TIMER_DTCTRL_MASK 0x00000003UL /**< Mask for TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTCINV (0x1UL << 0) /**< DTI Complementary Output Invert. */ -#define _TIMER_DTCTRL_DTCINV_SHIFT 0 /**< Shift value for TIMER_DTCINV */ -#define _TIMER_DTCTRL_DTCINV_MASK 0x1UL /**< Bit mask for TIMER_DTCINV */ -#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTIPOL (0x1UL << 1) /**< DTI Inactive Polarity */ -#define _TIMER_DTCTRL_DTIPOL_SHIFT 1 /**< Shift value for TIMER_DTIPOL */ -#define _TIMER_DTCTRL_DTIPOL_MASK 0x2UL /**< Bit mask for TIMER_DTIPOL */ -#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_MASK 0x00000003UL /**< Mask for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV (0x1UL << 0) /**< DTI Complementary Output Invert. */ +#define _TIMER_DTCTRL_DTCINV_SHIFT 0 /**< Shift value for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_MASK 0x1UL /**< Bit mask for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL (0x1UL << 1) /**< DTI Inactive Polarity */ +#define _TIMER_DTCTRL_DTIPOL_SHIFT 1 /**< Shift value for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_MASK 0x2UL /**< Bit mask for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ /* Bit fields for TIMER DTOGEN */ -#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ -#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CCn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ -#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ -#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CCn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ -#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ -#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CCn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ -#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ -#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTIn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ -#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ -#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTIn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ -#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ -#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTIn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ -#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ -#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ /* Bit fields for TIMER DTFAULT */ -#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ -#define _TIMER_DTFAULT_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ -#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ -#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ -#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ -#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ -#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ -#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ -#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ -#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ -#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ -#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ -#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ -#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTEM23F (0x1UL << 4) /**< DTI EM23 Entry Fault */ -#define _TIMER_DTFAULT_DTEM23F_SHIFT 4 /**< Shift value for TIMER_DTEM23F */ -#define _TIMER_DTFAULT_DTEM23F_MASK 0x10UL /**< Bit mask for TIMER_DTEM23F */ -#define _TIMER_DTFAULT_DTEM23F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTEM23F_DEFAULT (_TIMER_DTFAULT_DTEM23F_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F (0x1UL << 4) /**< DTI EM23 Entry Fault */ +#define _TIMER_DTFAULT_DTEM23F_SHIFT 4 /**< Shift value for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_MASK 0x10UL /**< Bit mask for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F_DEFAULT (_TIMER_DTFAULT_DTEM23F_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ /* Bit fields for TIMER DTFAULTC */ -#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ -#define _TIMER_DTFAULTC_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ -#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ -#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ -#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ -#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ -#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ -#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ -#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ -#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ -#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ -#define _TIMER_DTFAULTC_DTLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPFC */ -#define _TIMER_DTFAULTC_DTLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPFC */ -#define _TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTEM23FC (0x1UL << 4) /**< DTI EM23 Fault Clear */ -#define _TIMER_DTFAULTC_DTEM23FC_SHIFT 4 /**< Shift value for TIMER_DTEM23FC */ -#define _TIMER_DTFAULTC_DTEM23FC_MASK 0x10UL /**< Bit mask for TIMER_DTEM23FC */ -#define _TIMER_DTFAULTC_DTEM23FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTEM23FC_DEFAULT (_TIMER_DTFAULTC_DTEM23FC_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC (0x1UL << 4) /**< DTI EM23 Fault Clear */ +#define _TIMER_DTFAULTC_DTEM23FC_SHIFT 4 /**< Shift value for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_MASK 0x10UL /**< Bit mask for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC_DEFAULT (_TIMER_DTFAULTC_DTEM23FC_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ /* Bit fields for TIMER DTLOCK */ -#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ -#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ -#define _TIMER_DTLOCK_DTILOCKKEY_SHIFT 0 /**< Shift value for TIMER_DTILOCKKEY */ -#define _TIMER_DTLOCK_DTILOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_DTILOCKKEY */ -#define _TIMER_DTLOCK_DTILOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ -#define _TIMER_DTLOCK_DTILOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ -#define TIMER_DTLOCK_DTILOCKKEY_DEFAULT (_TIMER_DTLOCK_DTILOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ -#define TIMER_DTLOCK_DTILOCKKEY_UNLOCK (_TIMER_DTLOCK_DTILOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_SHIFT 0 /**< Shift value for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_DEFAULT (_TIMER_DTLOCK_DTILOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_UNLOCK (_TIMER_DTLOCK_DTILOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ /** @} End of group EFR32SG28_TIMER_BitFields */ /** @} End of group EFR32SG28_TIMER */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ulfrco.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ulfrco.h index 0ddcd2beb3..bc4b30f957 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_ulfrco.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_ULFRCO_H #define EFR32SG28_ULFRCO_H - #define ULFRCO_HAS_SET_CLEAR /**************************************************************************//** @@ -43,35 +42,34 @@ *****************************************************************************/ /** ULFRCO Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP version */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - uint32_t RESERVED1[2U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED2[1017U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED5[1017U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - uint32_t RESERVED7[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED8[1017U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - uint32_t RESERVED10[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED8[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED10[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ } ULFRCO_TypeDef; /** @} End of group EFR32SG28_ULFRCO */ @@ -83,64 +81,64 @@ typedef struct *****************************************************************************/ /* Bit fields for ULFRCO IPVERSION */ -#define _ULFRCO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ULFRCO_IPVERSION */ -#define _ULFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ULFRCO_IPVERSION */ -#define _ULFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ULFRCO_IPVERSION */ -#define _ULFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ULFRCO_IPVERSION */ -#define _ULFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ULFRCO_IPVERSION */ -#define ULFRCO_IPVERSION_IPVERSION_DEFAULT (_ULFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ULFRCO_IPVERSION */ +#define ULFRCO_IPVERSION_IPVERSION_DEFAULT (_ULFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IPVERSION */ /* Bit fields for ULFRCO STATUS */ -#define _ULFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_STATUS */ -#define _ULFRCO_STATUS_MASK 0x00010001UL /**< Mask for ULFRCO_STATUS */ -#define ULFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ -#define _ULFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ -#define _ULFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ -#define _ULFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ -#define ULFRCO_STATUS_RDY_DEFAULT (_ULFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ -#define ULFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ -#define _ULFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for ULFRCO_ENS */ -#define _ULFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for ULFRCO_ENS */ -#define _ULFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ -#define ULFRCO_STATUS_ENS_DEFAULT (_ULFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ +#define _ULFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_STATUS */ +#define _ULFRCO_STATUS_MASK 0x00010001UL /**< Mask for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _ULFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY_DEFAULT (_ULFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _ULFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS_DEFAULT (_ULFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ /* Bit fields for ULFRCO IF */ -#define _ULFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IF */ -#define _ULFRCO_IF_MASK 0x00000007UL /**< Mask for ULFRCO_IF */ -#define ULFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ -#define _ULFRCO_IF_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ -#define _ULFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ -#define _ULFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_RDY_DEFAULT (_ULFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_POSEDGE (0x1UL << 1) /**< Positive Edge Interrupt Flag */ -#define _ULFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ -#define _ULFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ -#define _ULFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_POSEDGE_DEFAULT (_ULFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_NEGEDGE (0x1UL << 2) /**< Negative Edge Interrupt Flag */ -#define _ULFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ -#define _ULFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ -#define _ULFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_NEGEDGE_DEFAULT (_ULFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define _ULFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IF */ +#define _ULFRCO_IF_MASK 0x00000007UL /**< Mask for ULFRCO_IF */ +#define ULFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _ULFRCO_IF_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_RDY_DEFAULT (_ULFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE (0x1UL << 1) /**< Positive Edge Interrupt Flag */ +#define _ULFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE_DEFAULT (_ULFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE (0x1UL << 2) /**< Negative Edge Interrupt Flag */ +#define _ULFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE_DEFAULT (_ULFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IF */ /* Bit fields for ULFRCO IEN */ -#define _ULFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IEN */ -#define _ULFRCO_IEN_MASK 0x00000007UL /**< Mask for ULFRCO_IEN */ -#define ULFRCO_IEN_RDY (0x1UL << 0) /**< Enable Ready Interrupt */ -#define _ULFRCO_IEN_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ -#define _ULFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ -#define _ULFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_RDY_DEFAULT (_ULFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_POSEDGE (0x1UL << 1) /**< Enable Positive Edge Interrupt */ -#define _ULFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ -#define _ULFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ -#define _ULFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_POSEDGE_DEFAULT (_ULFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Enable Negative Edge Interrupt */ -#define _ULFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ -#define _ULFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ -#define _ULFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_NEGEDGE_DEFAULT (_ULFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define _ULFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IEN */ +#define _ULFRCO_IEN_MASK 0x00000007UL /**< Mask for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY (0x1UL << 0) /**< Enable Ready Interrupt */ +#define _ULFRCO_IEN_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY_DEFAULT (_ULFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE (0x1UL << 1) /**< Enable Positive Edge Interrupt */ +#define _ULFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE_DEFAULT (_ULFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Enable Negative Edge Interrupt */ +#define _ULFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE_DEFAULT (_ULFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IEN */ /** @} End of group EFR32SG28_ULFRCO_BitFields */ /** @} End of group EFR32SG28_ULFRCO */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_usart.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_usart.h index bebea5b6f0..5b7b288889 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_usart.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_usart.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_USART_H #define EFR32SG28_USART_H - #define USART_HAS_SET_CLEAR /**************************************************************************//** @@ -43,119 +42,118 @@ *****************************************************************************/ /** USART Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< USART Enable */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t FRAME; /**< USART Frame Format Register */ - __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< USART Status Register */ - __IOM uint32_t CLKDIV; /**< Clock Control Register */ - __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ - __IM uint32_t RXDATA; /**< RX Buffer Data Register */ - __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ - __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ - __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ - __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek R... */ - __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ - __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ - __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ - __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t IRCTRL; /**< IrDA Control Register */ - __IOM uint32_t I2SCTRL; /**< I2S Control Register */ - __IOM uint32_t TIMING; /**< Timing Register */ - __IOM uint32_t CTRLX; /**< Control Register Extended */ - __IOM uint32_t TIMECMP0; /**< Timer Compare 0 */ - __IOM uint32_t TIMECMP1; /**< Timer Compare 1 */ - __IOM uint32_t TIMECMP2; /**< Timer Compare 2 */ - uint32_t RESERVED0[997U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< USART Enable */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t FRAME_SET; /**< USART Frame Format Register */ - __IOM uint32_t TRIGCTRL_SET; /**< USART Trigger Control register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< USART Status Register */ - __IOM uint32_t CLKDIV_SET; /**< Clock Control Register */ - __IM uint32_t RXDATAX_SET; /**< RX Buffer Data Extended Register */ - __IM uint32_t RXDATA_SET; /**< RX Buffer Data Register */ - __IM uint32_t RXDOUBLEX_SET; /**< RX Buffer Double Data Extended Register */ - __IM uint32_t RXDOUBLE_SET; /**< RX FIFO Double Data Register */ - __IM uint32_t RXDATAXP_SET; /**< RX Buffer Data Extended Peek Register */ - __IM uint32_t RXDOUBLEXP_SET; /**< RX Buffer Double Data Extended Peek R... */ - __IOM uint32_t TXDATAX_SET; /**< TX Buffer Data Extended Register */ - __IOM uint32_t TXDATA_SET; /**< TX Buffer Data Register */ - __IOM uint32_t TXDOUBLEX_SET; /**< TX Buffer Double Data Extended Register */ - __IOM uint32_t TXDOUBLE_SET; /**< TX Buffer Double Data Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t IRCTRL_SET; /**< IrDA Control Register */ - __IOM uint32_t I2SCTRL_SET; /**< I2S Control Register */ - __IOM uint32_t TIMING_SET; /**< Timing Register */ - __IOM uint32_t CTRLX_SET; /**< Control Register Extended */ - __IOM uint32_t TIMECMP0_SET; /**< Timer Compare 0 */ - __IOM uint32_t TIMECMP1_SET; /**< Timer Compare 1 */ - __IOM uint32_t TIMECMP2_SET; /**< Timer Compare 2 */ - uint32_t RESERVED1[997U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< USART Enable */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t FRAME_CLR; /**< USART Frame Format Register */ - __IOM uint32_t TRIGCTRL_CLR; /**< USART Trigger Control register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< USART Status Register */ - __IOM uint32_t CLKDIV_CLR; /**< Clock Control Register */ - __IM uint32_t RXDATAX_CLR; /**< RX Buffer Data Extended Register */ - __IM uint32_t RXDATA_CLR; /**< RX Buffer Data Register */ - __IM uint32_t RXDOUBLEX_CLR; /**< RX Buffer Double Data Extended Register */ - __IM uint32_t RXDOUBLE_CLR; /**< RX FIFO Double Data Register */ - __IM uint32_t RXDATAXP_CLR; /**< RX Buffer Data Extended Peek Register */ - __IM uint32_t RXDOUBLEXP_CLR; /**< RX Buffer Double Data Extended Peek R... */ - __IOM uint32_t TXDATAX_CLR; /**< TX Buffer Data Extended Register */ - __IOM uint32_t TXDATA_CLR; /**< TX Buffer Data Register */ - __IOM uint32_t TXDOUBLEX_CLR; /**< TX Buffer Double Data Extended Register */ - __IOM uint32_t TXDOUBLE_CLR; /**< TX Buffer Double Data Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t IRCTRL_CLR; /**< IrDA Control Register */ - __IOM uint32_t I2SCTRL_CLR; /**< I2S Control Register */ - __IOM uint32_t TIMING_CLR; /**< Timing Register */ - __IOM uint32_t CTRLX_CLR; /**< Control Register Extended */ - __IOM uint32_t TIMECMP0_CLR; /**< Timer Compare 0 */ - __IOM uint32_t TIMECMP1_CLR; /**< Timer Compare 1 */ - __IOM uint32_t TIMECMP2_CLR; /**< Timer Compare 2 */ - uint32_t RESERVED2[997U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< USART Enable */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t FRAME_TGL; /**< USART Frame Format Register */ - __IOM uint32_t TRIGCTRL_TGL; /**< USART Trigger Control register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< USART Status Register */ - __IOM uint32_t CLKDIV_TGL; /**< Clock Control Register */ - __IM uint32_t RXDATAX_TGL; /**< RX Buffer Data Extended Register */ - __IM uint32_t RXDATA_TGL; /**< RX Buffer Data Register */ - __IM uint32_t RXDOUBLEX_TGL; /**< RX Buffer Double Data Extended Register */ - __IM uint32_t RXDOUBLE_TGL; /**< RX FIFO Double Data Register */ - __IM uint32_t RXDATAXP_TGL; /**< RX Buffer Data Extended Peek Register */ - __IM uint32_t RXDOUBLEXP_TGL; /**< RX Buffer Double Data Extended Peek R... */ - __IOM uint32_t TXDATAX_TGL; /**< TX Buffer Data Extended Register */ - __IOM uint32_t TXDATA_TGL; /**< TX Buffer Data Register */ - __IOM uint32_t TXDOUBLEX_TGL; /**< TX Buffer Double Data Extended Register */ - __IOM uint32_t TXDOUBLE_TGL; /**< TX Buffer Double Data Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t IRCTRL_TGL; /**< IrDA Control Register */ - __IOM uint32_t I2SCTRL_TGL; /**< I2S Control Register */ - __IOM uint32_t TIMING_TGL; /**< Timing Register */ - __IOM uint32_t CTRLX_TGL; /**< Control Register Extended */ - __IOM uint32_t TIMECMP0_TGL; /**< Timer Compare 0 */ - __IOM uint32_t TIMECMP1_TGL; /**< Timer Compare 1 */ - __IOM uint32_t TIMECMP2_TGL; /**< Timer Compare 2 */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< USART Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t FRAME; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< USART Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL; /**< I2S Control Register */ + __IOM uint32_t TIMING; /**< Timing Register */ + __IOM uint32_t CTRLX; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2; /**< Timer Compare 2 */ + uint32_t RESERVED0[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< USART Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t FRAME_SET; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_SET; /**< USART Trigger Control register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< USART Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Control Register */ + __IM uint32_t RXDATAX_SET; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_SET; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_SET; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_SET; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_SET; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_SET; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_SET; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_SET; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_SET; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_SET; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_SET; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_SET; /**< I2S Control Register */ + __IOM uint32_t TIMING_SET; /**< Timing Register */ + __IOM uint32_t CTRLX_SET; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_SET; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_SET; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_SET; /**< Timer Compare 2 */ + uint32_t RESERVED1[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< USART Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t FRAME_CLR; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< USART Trigger Control register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< USART Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Control Register */ + __IM uint32_t RXDATAX_CLR; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_CLR; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_CLR; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_CLR; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_CLR; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_CLR; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_CLR; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_CLR; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_CLR; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_CLR; /**< I2S Control Register */ + __IOM uint32_t TIMING_CLR; /**< Timing Register */ + __IOM uint32_t CTRLX_CLR; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_CLR; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_CLR; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_CLR; /**< Timer Compare 2 */ + uint32_t RESERVED2[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< USART Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t FRAME_TGL; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< USART Trigger Control register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< USART Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Control Register */ + __IM uint32_t RXDATAX_TGL; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_TGL; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_TGL; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_TGL; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_TGL; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_TGL; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_TGL; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_TGL; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_TGL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_TGL; /**< I2S Control Register */ + __IOM uint32_t TIMING_TGL; /**< Timing Register */ + __IOM uint32_t CTRLX_TGL; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_TGL; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_TGL; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_TGL; /**< Timer Compare 2 */ } USART_TypeDef; /** @} End of group EFR32SG28_USART */ @@ -167,11 +165,11 @@ typedef struct *****************************************************************************/ /* Bit fields for USART IPVERSION */ -#define _USART_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for USART_IPVERSION */ -#define _USART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for USART_IPVERSION */ -#define _USART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for USART_IPVERSION */ -#define _USART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for USART_IPVERSION */ -#define _USART_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IPVERSION */ +#define _USART_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for USART_IPVERSION */ +#define _USART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IPVERSION */ #define USART_IPVERSION_IPVERSION_DEFAULT (_USART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IPVERSION */ /* Bit fields for USART EN */ @@ -184,327 +182,327 @@ typedef struct #define USART_EN_EN_DEFAULT (_USART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_EN */ /* Bit fields for USART CTRL */ -#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ -#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ -#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ -#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ -#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ -#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SYNC_DISABLE (_USART_CTRL_SYNC_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_SYNC_ENABLE (_USART_CTRL_SYNC_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ -#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ -#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ -#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_LOOPBK_DISABLE (_USART_CTRL_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_LOOPBK_ENABLE (_USART_CTRL_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ -#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ -#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ -#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CCEN_DISABLE (_USART_CTRL_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_CCEN_ENABLE (_USART_CTRL_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ -#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ -#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ -#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MPM_DISABLE (_USART_CTRL_MPM_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_MPM_ENABLE (_USART_CTRL_MPM_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ -#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ -#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ -#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ -#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ -#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ -#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ -#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ -#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ -#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ -#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ -#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ -#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ -#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ -#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ -#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ -#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ -#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ -#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ -#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ -#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ -#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ -#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ -#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ -#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ -#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ +#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ +#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ +#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ +#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ +#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ +#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SYNC_DISABLE (_USART_CTRL_SYNC_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_SYNC_ENABLE (_USART_CTRL_SYNC_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK_DISABLE (_USART_CTRL_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_ENABLE (_USART_CTRL_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ +#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ +#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN_DISABLE (_USART_CTRL_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CCEN_ENABLE (_USART_CTRL_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ +#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ +#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM_DISABLE (_USART_CTRL_MPM_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MPM_ENABLE (_USART_CTRL_MPM_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ +#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ +#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ +#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ +#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ +#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ +#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ +#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ +#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ +#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ +#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ +#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ +#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ +#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ +#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ #define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ -#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ -#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ -#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ -#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MSBF_DISABLE (_USART_CTRL_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_MSBF_ENABLE (_USART_CTRL_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Chip Select In Main Mode */ -#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ -#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ -#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ -#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ -#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ -#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ -#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ -#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ -#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ -#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ -#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ -#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ -#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ -#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ -#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ -#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ -#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_RXINV_DISABLE (_USART_CTRL_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_RXINV_ENABLE (_USART_CTRL_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ -#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ -#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ -#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_TXINV_DISABLE (_USART_CTRL_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_TXINV_ENABLE (_USART_CTRL_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ -#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ -#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ -#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_CSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CSINV_DISABLE (_USART_CTRL_CSINV_DISABLE << 15) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_CSINV_ENABLE (_USART_CTRL_CSINV_ENABLE << 15) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ -#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ -#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ -#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ -#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ -#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ -#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_AUTOTRI_DISABLE (_USART_CTRL_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_AUTOTRI_ENABLE (_USART_CTRL_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ -#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ -#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ -#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ -#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ -#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ -#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ -#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ -#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ -#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ -#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ -#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ -#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ -#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ -#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ -#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_ERRSDMA_DISABLE (_USART_CTRL_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_ERRSDMA_ENABLE (_USART_CTRL_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ -#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ -#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ -#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_ERRSRX_DISABLE (_USART_CTRL_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_ERRSRX_ENABLE (_USART_CTRL_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ -#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ -#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ -#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_ERRSTX_DISABLE (_USART_CTRL_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_ERRSTX_ENABLE (_USART_CTRL_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Secondary Setup Early */ -#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ -#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ -#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ -#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ -#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ -#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_BYTESWAP_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_BYTESWAP_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_BYTESWAP_DISABLE (_USART_CTRL_BYTESWAP_DISABLE << 28) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_BYTESWAP_ENABLE (_USART_CTRL_BYTESWAP_ENABLE << 28) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ -#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ -#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ -#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ -#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ -#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ -#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Main Sample Delay */ -#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ -#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ -#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ +#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ +#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MSBF_DISABLE (_USART_CTRL_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MSBF_ENABLE (_USART_CTRL_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Chip Select In Main Mode */ +#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ +#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ +#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ +#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ +#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ +#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ +#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ +#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ +#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ +#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ +#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ +#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ +#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ +#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_RXINV_DISABLE (_USART_CTRL_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_RXINV_ENABLE (_USART_CTRL_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ +#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ +#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV_DISABLE (_USART_CTRL_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_TXINV_ENABLE (_USART_CTRL_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ +#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ +#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ +#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV_DISABLE (_USART_CTRL_CSINV_DISABLE << 15) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CSINV_ENABLE (_USART_CTRL_CSINV_ENABLE << 15) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ +#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DISABLE (_USART_CTRL_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_ENABLE (_USART_CTRL_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ +#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ +#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ +#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ +#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ +#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ +#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DISABLE (_USART_CTRL_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_ENABLE (_USART_CTRL_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX_DISABLE (_USART_CTRL_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_ENABLE (_USART_CTRL_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX_DISABLE (_USART_CTRL_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_ENABLE (_USART_CTRL_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Secondary Setup Early */ +#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ +#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DISABLE (_USART_CTRL_BYTESWAP_DISABLE << 28) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_ENABLE (_USART_CTRL_BYTESWAP_ENABLE << 28) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ +#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ +#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ +#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Main Sample Delay */ +#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ /* Bit fields for USART FRAME */ -#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ -#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ -#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ -#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ -#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ -#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ -#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ -#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ -#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ -#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ -#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ -#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ -#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ -#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ -#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ -#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ -#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ -#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ -#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ -#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ -#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ -#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ -#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ -#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ -#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ -#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ -#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ -#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ -#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ -#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ -#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ -#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ -#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ -#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ -#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ -#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ -#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ -#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ -#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ -#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ -#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ -#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ -#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ -#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ -#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ -#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ +#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ +#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ +#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ +#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ +#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ +#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ +#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ +#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ +#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ +#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ +#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ +#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ +#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ +#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ +#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ +#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ +#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ +#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ +#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ +#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ +#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ +#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ +#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ +#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ +#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ #define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ -#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ +#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ /* Bit fields for USART TRIGCTRL */ -#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ -#define _USART_TRIGCTRL_MASK 0x00001FF0UL /**< Mask for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ -#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ -#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ -#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ -#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ -#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ -#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ -#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ -#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ -#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_MASK 0x00001FF0UL /**< Mask for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ +#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ +#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ +#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of */ -#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ -#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ -#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of */ -#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ -#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ -#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of */ -#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ -#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ -#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of f */ -#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ -#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ -#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of f */ -#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ -#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ -#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of f */ -#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ -#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ -#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ #define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ /* Bit fields for USART CMD */ @@ -572,99 +570,99 @@ typedef struct #define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ /* Bit fields for USART STATUS */ -#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ -#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ -#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ -#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ -#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ -#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ -#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ -#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ -#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Main Mode */ -#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ -#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ -#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ -#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ -#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ -#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ -#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ -#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ -#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ -#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ -#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ -#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ -#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ -#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ -#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ -#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ -#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ -#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ -#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ -#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ -#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ -#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ -#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ -#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ -#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ -#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ -#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ -#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ -#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ -#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ -#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ -#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ -#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ -#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ -#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ -#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ -#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ -#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ -#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ +#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ +#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ +#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ +#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ +#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ +#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Main Mode */ +#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ +#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ +#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ +#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ +#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ +#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ +#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ +#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ +#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ +#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ +#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ +#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ +#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ +#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ +#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ +#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ +#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ +#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ #define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ -#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ -#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ -#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ /* Bit fields for USART CLKDIV */ -#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ -#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ -#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ -#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ -#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ -#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ -#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ -#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ -#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ -#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ +#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ +#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ +#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ +#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ #define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ /* Bit fields for USART RXDATAX */ @@ -694,36 +692,36 @@ typedef struct #define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ /* Bit fields for USART RXDOUBLEX */ -#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ -#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ -#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ -#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ -#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ -#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ -#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ -#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ -#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ -#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ -#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ -#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ -#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ +#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ +#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ #define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ -#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ -#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ -#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ -#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ -#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ -#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ +#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ +#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ /* Bit fields for USART RXDOUBLE */ #define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ @@ -756,36 +754,36 @@ typedef struct #define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ /* Bit fields for USART RXDOUBLEXP */ -#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ -#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ -#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ -#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ -#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ -#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ -#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ -#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ -#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ -#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ -#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ -#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ -#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ +#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ +#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ #define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ -#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ -#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ -#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ -#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ -#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ -#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ +#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ +#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ /* Bit fields for USART TXDATAX */ #define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ @@ -829,66 +827,66 @@ typedef struct #define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ /* Bit fields for USART TXDOUBLEX */ -#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ -#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ -#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ -#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ -#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ -#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ -#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ -#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ -#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ -#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ -#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ -#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ -#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ -#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ -#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ -#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ -#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ -#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ -#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ -#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ -#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ -#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ -#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ -#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ -#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ -#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ -#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ -#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ -#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ -#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ -#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ -#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ -#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ -#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ #define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ -#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ -#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ -#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ /* Bit fields for USART TXDOUBLE */ #define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ @@ -1298,133 +1296,133 @@ typedef struct #define USART_CTRLX_CLKPRSEN_DEFAULT (_USART_CTRLX_CLKPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRLX */ /* Bit fields for USART TIMECMP0 */ -#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ -#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ -#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ -#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ -#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ -#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ -#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ -#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ -#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ -#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ -#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ -#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ -#define _USART_TIMECMP0_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ +#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ +#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP0 */ #define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ #define USART_TIMECMP0_RESTARTEN_DISABLE (_USART_TIMECMP0_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP0 */ -#define USART_TIMECMP0_RESTARTEN_ENABLE (_USART_TIMECMP0_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_ENABLE (_USART_TIMECMP0_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP0 */ /* Bit fields for USART TIMECMP1 */ -#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ -#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ -#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ -#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ -#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ -#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ -#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ -#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ -#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ -#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ -#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ -#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ -#define _USART_TIMECMP1_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ +#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ +#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP1 */ #define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ #define USART_TIMECMP1_RESTARTEN_DISABLE (_USART_TIMECMP1_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP1 */ -#define USART_TIMECMP1_RESTARTEN_ENABLE (_USART_TIMECMP1_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_ENABLE (_USART_TIMECMP1_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP1 */ /* Bit fields for USART TIMECMP2 */ -#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ -#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ -#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ -#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ -#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ -#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ -#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ -#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ -#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ -#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ -#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ -#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ -#define _USART_TIMECMP2_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ +#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ +#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP2 */ #define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ #define USART_TIMECMP2_RESTARTEN_DISABLE (_USART_TIMECMP2_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP2 */ -#define USART_TIMECMP2_RESTARTEN_ENABLE (_USART_TIMECMP2_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_ENABLE (_USART_TIMECMP2_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP2 */ /** @} End of group EFR32SG28_USART_BitFields */ /** @} End of group EFR32SG28_USART */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_vdac.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_vdac.h index 60004ec684..38ff5fae35 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_vdac.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_vdac.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_VDAC_H #define EFR32SG28_VDAC_H - #define VDAC_HAS_SET_CLEAR /**************************************************************************//** @@ -43,83 +42,82 @@ *****************************************************************************/ /** VDAC Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< Module Enable */ - __IOM uint32_t SWRST; /**< Software Reset Register */ - __IOM uint32_t CFG; /**< Config Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t CH0CFG; /**< Channel 0 Config Register */ - __IOM uint32_t CH1CFG; /**< Channel 1 Config Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t CH0F; /**< Channel 0 Data Write Fifo */ - __IOM uint32_t CH1F; /**< Channel 1 Data Write Fifo */ - __IOM uint32_t OUTCTRL; /**< DAC Output Control */ - __IOM uint32_t OUTTIMERCFG; /**< DAC Out Timer Config Register */ - uint32_t RESERVED0[50U]; /**< Reserved for future use */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - uint32_t RESERVED2[63U]; /**< Reserved for future use */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - uint32_t RESERVED4[895U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< Module Enable */ - __IOM uint32_t SWRST_SET; /**< Software Reset Register */ - __IOM uint32_t CFG_SET; /**< Config Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t CH0CFG_SET; /**< Channel 0 Config Register */ - __IOM uint32_t CH1CFG_SET; /**< Channel 1 Config Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t CH0F_SET; /**< Channel 0 Data Write Fifo */ - __IOM uint32_t CH1F_SET; /**< Channel 1 Data Write Fifo */ - __IOM uint32_t OUTCTRL_SET; /**< DAC Output Control */ - __IOM uint32_t OUTTIMERCFG_SET; /**< DAC Out Timer Config Register */ - uint32_t RESERVED5[50U]; /**< Reserved for future use */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - uint32_t RESERVED7[63U]; /**< Reserved for future use */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - uint32_t RESERVED9[895U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< Module Enable */ - __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ - __IOM uint32_t CFG_CLR; /**< Config Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t CH0CFG_CLR; /**< Channel 0 Config Register */ - __IOM uint32_t CH1CFG_CLR; /**< Channel 1 Config Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t CH0F_CLR; /**< Channel 0 Data Write Fifo */ - __IOM uint32_t CH1F_CLR; /**< Channel 1 Data Write Fifo */ - __IOM uint32_t OUTCTRL_CLR; /**< DAC Output Control */ - __IOM uint32_t OUTTIMERCFG_CLR; /**< DAC Out Timer Config Register */ - uint32_t RESERVED10[50U]; /**< Reserved for future use */ - uint32_t RESERVED11[1U]; /**< Reserved for future use */ - uint32_t RESERVED12[63U]; /**< Reserved for future use */ - uint32_t RESERVED13[1U]; /**< Reserved for future use */ - uint32_t RESERVED14[895U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< Module Enable */ - __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ - __IOM uint32_t CFG_TGL; /**< Config Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t CH0CFG_TGL; /**< Channel 0 Config Register */ - __IOM uint32_t CH1CFG_TGL; /**< Channel 1 Config Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t CH0F_TGL; /**< Channel 0 Data Write Fifo */ - __IOM uint32_t CH1F_TGL; /**< Channel 1 Data Write Fifo */ - __IOM uint32_t OUTCTRL_TGL; /**< DAC Output Control */ - __IOM uint32_t OUTTIMERCFG_TGL; /**< DAC Out Timer Config Register */ - uint32_t RESERVED15[50U]; /**< Reserved for future use */ - uint32_t RESERVED16[1U]; /**< Reserved for future use */ - uint32_t RESERVED17[63U]; /**< Reserved for future use */ - uint32_t RESERVED18[1U]; /**< Reserved for future use */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Module Enable */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Config Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CH0CFG; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG; /**< Channel 1 Config Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG; /**< DAC Out Timer Config Register */ + uint32_t RESERVED0[50U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[63U]; /**< Reserved for future use */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Module Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Config Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CH0CFG_SET; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_SET; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_SET; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_SET; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_SET; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_SET; /**< DAC Out Timer Config Register */ + uint32_t RESERVED5[50U]; /**< Reserved for future use */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[63U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Module Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Config Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CH0CFG_CLR; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_CLR; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_CLR; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_CLR; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_CLR; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_CLR; /**< DAC Out Timer Config Register */ + uint32_t RESERVED10[50U]; /**< Reserved for future use */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[63U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + uint32_t RESERVED14[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Module Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Config Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CH0CFG_TGL; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_TGL; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_TGL; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_TGL; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_TGL; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_TGL; /**< DAC Out Timer Config Register */ + uint32_t RESERVED15[50U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[63U]; /**< Reserved for future use */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ } VDAC_TypeDef; /** @} End of group EFR32SG28_VDAC */ @@ -131,646 +129,646 @@ typedef struct *****************************************************************************/ /* Bit fields for VDAC IPVERSION */ -#define _VDAC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for VDAC_IPVERSION */ -#define _VDAC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for VDAC_IPVERSION */ -#define _VDAC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for VDAC_IPVERSION */ -#define _VDAC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for VDAC_IPVERSION */ -#define _VDAC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for VDAC_IPVERSION */ -#define VDAC_IPVERSION_IPVERSION_DEFAULT (_VDAC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for VDAC_IPVERSION */ +#define VDAC_IPVERSION_IPVERSION_DEFAULT (_VDAC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IPVERSION */ /* Bit fields for VDAC EN */ -#define _VDAC_EN_RESETVALUE 0x00000000UL /**< Default value for VDAC_EN */ -#define _VDAC_EN_MASK 0x00000003UL /**< Mask for VDAC_EN */ -#define VDAC_EN_EN (0x1UL << 0) /**< VDAC Module Enable */ -#define _VDAC_EN_EN_SHIFT 0 /**< Shift value for VDAC_EN */ -#define _VDAC_EN_EN_MASK 0x1UL /**< Bit mask for VDAC_EN */ -#define _VDAC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ -#define _VDAC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_EN */ -#define _VDAC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for VDAC_EN */ -#define VDAC_EN_EN_DEFAULT (_VDAC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_EN */ -#define VDAC_EN_EN_DISABLE (_VDAC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_EN */ -#define VDAC_EN_EN_ENABLE (_VDAC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for VDAC_EN */ -#define VDAC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _VDAC_EN_DISABLING_SHIFT 1 /**< Shift value for VDAC_DISABLING */ -#define _VDAC_EN_DISABLING_MASK 0x2UL /**< Bit mask for VDAC_DISABLING */ -#define _VDAC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ -#define VDAC_EN_DISABLING_DEFAULT (_VDAC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_EN */ +#define _VDAC_EN_RESETVALUE 0x00000000UL /**< Default value for VDAC_EN */ +#define _VDAC_EN_MASK 0x00000003UL /**< Mask for VDAC_EN */ +#define VDAC_EN_EN (0x1UL << 0) /**< VDAC Module Enable */ +#define _VDAC_EN_EN_SHIFT 0 /**< Shift value for VDAC_EN */ +#define _VDAC_EN_EN_MASK 0x1UL /**< Bit mask for VDAC_EN */ +#define _VDAC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ +#define _VDAC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_EN */ +#define _VDAC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for VDAC_EN */ +#define VDAC_EN_EN_DEFAULT (_VDAC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_EN */ +#define VDAC_EN_EN_DISABLE (_VDAC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_EN */ +#define VDAC_EN_EN_ENABLE (_VDAC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for VDAC_EN */ +#define VDAC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _VDAC_EN_DISABLING_SHIFT 1 /**< Shift value for VDAC_DISABLING */ +#define _VDAC_EN_DISABLING_MASK 0x2UL /**< Bit mask for VDAC_DISABLING */ +#define _VDAC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ +#define VDAC_EN_DISABLING_DEFAULT (_VDAC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_EN */ /* Bit fields for VDAC SWRST */ -#define _VDAC_SWRST_RESETVALUE 0x00000000UL /**< Default value for VDAC_SWRST */ -#define _VDAC_SWRST_MASK 0x00000003UL /**< Mask for VDAC_SWRST */ -#define VDAC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ -#define _VDAC_SWRST_SWRST_SHIFT 0 /**< Shift value for VDAC_SWRST */ -#define _VDAC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for VDAC_SWRST */ -#define _VDAC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ -#define VDAC_SWRST_SWRST_DEFAULT (_VDAC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_SWRST */ -#define VDAC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ -#define _VDAC_SWRST_RESETTING_SHIFT 1 /**< Shift value for VDAC_RESETTING */ -#define _VDAC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for VDAC_RESETTING */ -#define _VDAC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ -#define VDAC_SWRST_RESETTING_DEFAULT (_VDAC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_SWRST */ +#define _VDAC_SWRST_RESETVALUE 0x00000000UL /**< Default value for VDAC_SWRST */ +#define _VDAC_SWRST_MASK 0x00000003UL /**< Mask for VDAC_SWRST */ +#define VDAC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _VDAC_SWRST_SWRST_SHIFT 0 /**< Shift value for VDAC_SWRST */ +#define _VDAC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for VDAC_SWRST */ +#define _VDAC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_SWRST_DEFAULT (_VDAC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _VDAC_SWRST_RESETTING_SHIFT 1 /**< Shift value for VDAC_RESETTING */ +#define _VDAC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for VDAC_RESETTING */ +#define _VDAC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_RESETTING_DEFAULT (_VDAC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_SWRST */ /* Bit fields for VDAC CFG */ -#define _VDAC_CFG_RESETVALUE 0x20000000UL /**< Default value for VDAC_CFG */ -#define _VDAC_CFG_MASK 0xFF7F3FBFUL /**< Mask for VDAC_CFG */ -#define VDAC_CFG_DIFF (0x1UL << 0) /**< Differential Mode */ -#define _VDAC_CFG_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */ -#define _VDAC_CFG_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */ -#define _VDAC_CFG_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_DIFF_SINGLEENDED 0x00000000UL /**< Mode SINGLEENDED for VDAC_CFG */ -#define _VDAC_CFG_DIFF_DIFFERENTIAL 0x00000001UL /**< Mode DIFFERENTIAL for VDAC_CFG */ -#define VDAC_CFG_DIFF_DEFAULT (_VDAC_CFG_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_DIFF_SINGLEENDED (_VDAC_CFG_DIFF_SINGLEENDED << 0) /**< Shifted mode SINGLEENDED for VDAC_CFG */ -#define VDAC_CFG_DIFF_DIFFERENTIAL (_VDAC_CFG_DIFF_DIFFERENTIAL << 0) /**< Shifted mode DIFFERENTIAL for VDAC_CFG */ -#define VDAC_CFG_SINEMODE (0x1UL << 1) /**< Sine Mode */ -#define _VDAC_CFG_SINEMODE_SHIFT 1 /**< Shift value for VDAC_SINEMODE */ -#define _VDAC_CFG_SINEMODE_MASK 0x2UL /**< Bit mask for VDAC_SINEMODE */ -#define _VDAC_CFG_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_SINEMODE_DISSINEMODE 0x00000000UL /**< Mode DISSINEMODE for VDAC_CFG */ -#define _VDAC_CFG_SINEMODE_ENSINEMODE 0x00000001UL /**< Mode ENSINEMODE for VDAC_CFG */ -#define VDAC_CFG_SINEMODE_DEFAULT (_VDAC_CFG_SINEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_SINEMODE_DISSINEMODE (_VDAC_CFG_SINEMODE_DISSINEMODE << 1) /**< Shifted mode DISSINEMODE for VDAC_CFG */ -#define VDAC_CFG_SINEMODE_ENSINEMODE (_VDAC_CFG_SINEMODE_ENSINEMODE << 1) /**< Shifted mode ENSINEMODE for VDAC_CFG */ -#define VDAC_CFG_SINERESET (0x1UL << 2) /**< Sine Wave Reset When inactive */ -#define _VDAC_CFG_SINERESET_SHIFT 2 /**< Shift value for VDAC_SINERESET */ -#define _VDAC_CFG_SINERESET_MASK 0x4UL /**< Bit mask for VDAC_SINERESET */ -#define _VDAC_CFG_SINERESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_SINERESET_DEFAULT (_VDAC_CFG_SINERESET_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_CH0PRESCRST (0x1UL << 3) /**< Channel 0 Start Reset Prescaler */ -#define _VDAC_CFG_CH0PRESCRST_SHIFT 3 /**< Shift value for VDAC_CH0PRESCRST */ -#define _VDAC_CFG_CH0PRESCRST_MASK 0x8UL /**< Bit mask for VDAC_CH0PRESCRST */ -#define _VDAC_CFG_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_CH0PRESCRST_NORESETPRESC 0x00000000UL /**< Mode NORESETPRESC for VDAC_CFG */ -#define _VDAC_CFG_CH0PRESCRST_RESETPRESC 0x00000001UL /**< Mode RESETPRESC for VDAC_CFG */ -#define VDAC_CFG_CH0PRESCRST_DEFAULT (_VDAC_CFG_CH0PRESCRST_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_CH0PRESCRST_NORESETPRESC (_VDAC_CFG_CH0PRESCRST_NORESETPRESC << 3) /**< Shifted mode NORESETPRESC for VDAC_CFG */ -#define VDAC_CFG_CH0PRESCRST_RESETPRESC (_VDAC_CFG_CH0PRESCRST_RESETPRESC << 3) /**< Shifted mode RESETPRESC for VDAC_CFG */ -#define _VDAC_CFG_REFRSEL_SHIFT 4 /**< Shift value for VDAC_REFRSEL */ -#define _VDAC_CFG_REFRSEL_MASK 0x30UL /**< Bit mask for VDAC_REFRSEL */ -#define _VDAC_CFG_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_REFRSEL_V125 0x00000000UL /**< Mode V125 for VDAC_CFG */ -#define _VDAC_CFG_REFRSEL_V25 0x00000001UL /**< Mode V25 for VDAC_CFG */ -#define _VDAC_CFG_REFRSEL_VDD 0x00000002UL /**< Mode VDD for VDAC_CFG */ -#define _VDAC_CFG_REFRSEL_EXT 0x00000003UL /**< Mode EXT for VDAC_CFG */ -#define VDAC_CFG_REFRSEL_DEFAULT (_VDAC_CFG_REFRSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_REFRSEL_V125 (_VDAC_CFG_REFRSEL_V125 << 4) /**< Shifted mode V125 for VDAC_CFG */ -#define VDAC_CFG_REFRSEL_V25 (_VDAC_CFG_REFRSEL_V25 << 4) /**< Shifted mode V25 for VDAC_CFG */ -#define VDAC_CFG_REFRSEL_VDD (_VDAC_CFG_REFRSEL_VDD << 4) /**< Shifted mode VDD for VDAC_CFG */ -#define VDAC_CFG_REFRSEL_EXT (_VDAC_CFG_REFRSEL_EXT << 4) /**< Shifted mode EXT for VDAC_CFG */ -#define _VDAC_CFG_PRESC_SHIFT 7 /**< Shift value for VDAC_PRESC */ -#define _VDAC_CFG_PRESC_MASK 0x3F80UL /**< Bit mask for VDAC_PRESC */ -#define _VDAC_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_PRESC_DEFAULT (_VDAC_CFG_PRESC_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_SHIFT 16 /**< Shift value for VDAC_TIMEROVRFLOWPERIOD */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_MASK 0x70000UL /**< Bit mask for VDAC_TIMEROVRFLOWPERIOD */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT (_VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 << 16) /**< Shifted mode CYCLES2 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 << 16) /**< Shifted mode CYCLES4 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 << 16) /**< Shifted mode CYCLES8 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 << 16) /**< Shifted mode CYCLES16 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 << 16) /**< Shifted mode CYCLES32 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 << 16) /**< Shifted mode CYCLES64 for VDAC_CFG */ -#define VDAC_CFG_SINEMODEPRS (0x1UL << 19) /**< Sinemode prs */ -#define _VDAC_CFG_SINEMODEPRS_SHIFT 19 /**< Shift value for VDAC_SINEMODEPRS */ -#define _VDAC_CFG_SINEMODEPRS_MASK 0x80000UL /**< Bit mask for VDAC_SINEMODEPRS */ -#define _VDAC_CFG_SINEMODEPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_SINEMODEPRS_DISSINEMODEPRS 0x00000000UL /**< Mode DISSINEMODEPRS for VDAC_CFG */ -#define _VDAC_CFG_SINEMODEPRS_ENSINEMODEPRS 0x00000001UL /**< Mode ENSINEMODEPRS for VDAC_CFG */ -#define VDAC_CFG_SINEMODEPRS_DEFAULT (_VDAC_CFG_SINEMODEPRS_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_SINEMODEPRS_DISSINEMODEPRS (_VDAC_CFG_SINEMODEPRS_DISSINEMODEPRS << 19) /**< Shifted mode DISSINEMODEPRS for VDAC_CFG */ -#define VDAC_CFG_SINEMODEPRS_ENSINEMODEPRS (_VDAC_CFG_SINEMODEPRS_ENSINEMODEPRS << 19) /**< Shifted mode ENSINEMODEPRS for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_SHIFT 20 /**< Shift value for VDAC_REFRESHPERIOD */ -#define _VDAC_CFG_REFRESHPERIOD_MASK 0x700000UL /**< Bit mask for VDAC_REFRESHPERIOD */ -#define _VDAC_CFG_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES128 0x00000006UL /**< Mode CYCLES128 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES256 0x00000007UL /**< Mode CYCLES256 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_DEFAULT (_VDAC_CFG_REFRESHPERIOD_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES2 (_VDAC_CFG_REFRESHPERIOD_CYCLES2 << 20) /**< Shifted mode CYCLES2 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES4 (_VDAC_CFG_REFRESHPERIOD_CYCLES4 << 20) /**< Shifted mode CYCLES4 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES8 (_VDAC_CFG_REFRESHPERIOD_CYCLES8 << 20) /**< Shifted mode CYCLES8 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES16 (_VDAC_CFG_REFRESHPERIOD_CYCLES16 << 20) /**< Shifted mode CYCLES16 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES32 (_VDAC_CFG_REFRESHPERIOD_CYCLES32 << 20) /**< Shifted mode CYCLES32 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES64 (_VDAC_CFG_REFRESHPERIOD_CYCLES64 << 20) /**< Shifted mode CYCLES64 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES128 (_VDAC_CFG_REFRESHPERIOD_CYCLES128 << 20) /**< Shifted mode CYCLES128 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES256 (_VDAC_CFG_REFRESHPERIOD_CYCLES256 << 20) /**< Shifted mode CYCLES256 for VDAC_CFG */ -#define VDAC_CFG_BIASKEEPWARM (0x1UL << 24) /**< Bias Keepwarm Mode Enable */ -#define _VDAC_CFG_BIASKEEPWARM_SHIFT 24 /**< Shift value for VDAC_BIASKEEPWARM */ -#define _VDAC_CFG_BIASKEEPWARM_MASK 0x1000000UL /**< Bit mask for VDAC_BIASKEEPWARM */ -#define _VDAC_CFG_BIASKEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_BIASKEEPWARM_DEFAULT (_VDAC_CFG_BIASKEEPWARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_DMAWU (0x1UL << 25) /**< VDAC DMA Wakeup */ -#define _VDAC_CFG_DMAWU_SHIFT 25 /**< Shift value for VDAC_DMAWU */ -#define _VDAC_CFG_DMAWU_MASK 0x2000000UL /**< Bit mask for VDAC_DMAWU */ -#define _VDAC_CFG_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_DMAWU_DEFAULT (_VDAC_CFG_DMAWU_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_ONDEMANDCLK (0x1UL << 26) /**< Always allow clk_dac */ -#define _VDAC_CFG_ONDEMANDCLK_SHIFT 26 /**< Shift value for VDAC_ONDEMANDCLK */ -#define _VDAC_CFG_ONDEMANDCLK_MASK 0x4000000UL /**< Bit mask for VDAC_ONDEMANDCLK */ -#define _VDAC_CFG_ONDEMANDCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_ONDEMANDCLK_DEFAULT (_VDAC_CFG_ONDEMANDCLK_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_DBGHALT (0x1UL << 27) /**< Debug Halt */ -#define _VDAC_CFG_DBGHALT_SHIFT 27 /**< Shift value for VDAC_DBGHALT */ -#define _VDAC_CFG_DBGHALT_MASK 0x8000000UL /**< Bit mask for VDAC_DBGHALT */ -#define _VDAC_CFG_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CFG */ -#define _VDAC_CFG_DBGHALT_HALT 0x00000001UL /**< Mode HALT for VDAC_CFG */ -#define VDAC_CFG_DBGHALT_DEFAULT (_VDAC_CFG_DBGHALT_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_DBGHALT_NORMAL (_VDAC_CFG_DBGHALT_NORMAL << 27) /**< Shifted mode NORMAL for VDAC_CFG */ -#define VDAC_CFG_DBGHALT_HALT (_VDAC_CFG_DBGHALT_HALT << 27) /**< Shifted mode HALT for VDAC_CFG */ -#define _VDAC_CFG_WARMUPTIME_SHIFT 28 /**< Shift value for VDAC_WARMUPTIME */ -#define _VDAC_CFG_WARMUPTIME_MASK 0x70000000UL /**< Bit mask for VDAC_WARMUPTIME */ -#define _VDAC_CFG_WARMUPTIME_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_WARMUPTIME_DEFAULT (_VDAC_CFG_WARMUPTIME_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_OUTENPRS (0x1UL << 31) /**< PRS Controlled Output Enable */ -#define _VDAC_CFG_OUTENPRS_SHIFT 31 /**< Shift value for VDAC_OUTENPRS */ -#define _VDAC_CFG_OUTENPRS_MASK 0x80000000UL /**< Bit mask for VDAC_OUTENPRS */ -#define _VDAC_CFG_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_OUTENPRS_DISOUTENPRS 0x00000000UL /**< Mode DISOUTENPRS for VDAC_CFG */ -#define _VDAC_CFG_OUTENPRS_ENOUTENPRS 0x00000001UL /**< Mode ENOUTENPRS for VDAC_CFG */ -#define VDAC_CFG_OUTENPRS_DEFAULT (_VDAC_CFG_OUTENPRS_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_OUTENPRS_DISOUTENPRS (_VDAC_CFG_OUTENPRS_DISOUTENPRS << 31) /**< Shifted mode DISOUTENPRS for VDAC_CFG */ -#define VDAC_CFG_OUTENPRS_ENOUTENPRS (_VDAC_CFG_OUTENPRS_ENOUTENPRS << 31) /**< Shifted mode ENOUTENPRS for VDAC_CFG */ +#define _VDAC_CFG_RESETVALUE 0x20000000UL /**< Default value for VDAC_CFG */ +#define _VDAC_CFG_MASK 0xFF7F3FBFUL /**< Mask for VDAC_CFG */ +#define VDAC_CFG_DIFF (0x1UL << 0) /**< Differential Mode */ +#define _VDAC_CFG_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */ +#define _VDAC_CFG_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */ +#define _VDAC_CFG_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_DIFF_SINGLEENDED 0x00000000UL /**< Mode SINGLEENDED for VDAC_CFG */ +#define _VDAC_CFG_DIFF_DIFFERENTIAL 0x00000001UL /**< Mode DIFFERENTIAL for VDAC_CFG */ +#define VDAC_CFG_DIFF_DEFAULT (_VDAC_CFG_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DIFF_SINGLEENDED (_VDAC_CFG_DIFF_SINGLEENDED << 0) /**< Shifted mode SINGLEENDED for VDAC_CFG */ +#define VDAC_CFG_DIFF_DIFFERENTIAL (_VDAC_CFG_DIFF_DIFFERENTIAL << 0) /**< Shifted mode DIFFERENTIAL for VDAC_CFG */ +#define VDAC_CFG_SINEMODE (0x1UL << 1) /**< Sine Mode */ +#define _VDAC_CFG_SINEMODE_SHIFT 1 /**< Shift value for VDAC_SINEMODE */ +#define _VDAC_CFG_SINEMODE_MASK 0x2UL /**< Bit mask for VDAC_SINEMODE */ +#define _VDAC_CFG_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_SINEMODE_DISSINEMODE 0x00000000UL /**< Mode DISSINEMODE for VDAC_CFG */ +#define _VDAC_CFG_SINEMODE_ENSINEMODE 0x00000001UL /**< Mode ENSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_DEFAULT (_VDAC_CFG_SINEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_DISSINEMODE (_VDAC_CFG_SINEMODE_DISSINEMODE << 1) /**< Shifted mode DISSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_ENSINEMODE (_VDAC_CFG_SINEMODE_ENSINEMODE << 1) /**< Shifted mode ENSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINERESET (0x1UL << 2) /**< Sine Wave Reset When inactive */ +#define _VDAC_CFG_SINERESET_SHIFT 2 /**< Shift value for VDAC_SINERESET */ +#define _VDAC_CFG_SINERESET_MASK 0x4UL /**< Bit mask for VDAC_SINERESET */ +#define _VDAC_CFG_SINERESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_SINERESET_DEFAULT (_VDAC_CFG_SINERESET_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST (0x1UL << 3) /**< Channel 0 Start Reset Prescaler */ +#define _VDAC_CFG_CH0PRESCRST_SHIFT 3 /**< Shift value for VDAC_CH0PRESCRST */ +#define _VDAC_CFG_CH0PRESCRST_MASK 0x8UL /**< Bit mask for VDAC_CH0PRESCRST */ +#define _VDAC_CFG_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_CH0PRESCRST_NORESETPRESC 0x00000000UL /**< Mode NORESETPRESC for VDAC_CFG */ +#define _VDAC_CFG_CH0PRESCRST_RESETPRESC 0x00000001UL /**< Mode RESETPRESC for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_DEFAULT (_VDAC_CFG_CH0PRESCRST_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_NORESETPRESC (_VDAC_CFG_CH0PRESCRST_NORESETPRESC << 3) /**< Shifted mode NORESETPRESC for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_RESETPRESC (_VDAC_CFG_CH0PRESCRST_RESETPRESC << 3) /**< Shifted mode RESETPRESC for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_SHIFT 4 /**< Shift value for VDAC_REFRSEL */ +#define _VDAC_CFG_REFRSEL_MASK 0x30UL /**< Bit mask for VDAC_REFRSEL */ +#define _VDAC_CFG_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_V125 0x00000000UL /**< Mode V125 for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_V25 0x00000001UL /**< Mode V25 for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_VDD 0x00000002UL /**< Mode VDD for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_EXT 0x00000003UL /**< Mode EXT for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_DEFAULT (_VDAC_CFG_REFRSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_V125 (_VDAC_CFG_REFRSEL_V125 << 4) /**< Shifted mode V125 for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_V25 (_VDAC_CFG_REFRSEL_V25 << 4) /**< Shifted mode V25 for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_VDD (_VDAC_CFG_REFRSEL_VDD << 4) /**< Shifted mode VDD for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_EXT (_VDAC_CFG_REFRSEL_EXT << 4) /**< Shifted mode EXT for VDAC_CFG */ +#define _VDAC_CFG_PRESC_SHIFT 7 /**< Shift value for VDAC_PRESC */ +#define _VDAC_CFG_PRESC_MASK 0x3F80UL /**< Bit mask for VDAC_PRESC */ +#define _VDAC_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_PRESC_DEFAULT (_VDAC_CFG_PRESC_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_SHIFT 16 /**< Shift value for VDAC_TIMEROVRFLOWPERIOD */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_MASK 0x70000UL /**< Bit mask for VDAC_TIMEROVRFLOWPERIOD */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT (_VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 << 16) /**< Shifted mode CYCLES2 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 << 16) /**< Shifted mode CYCLES4 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 << 16) /**< Shifted mode CYCLES8 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 << 16) /**< Shifted mode CYCLES16 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 << 16) /**< Shifted mode CYCLES32 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 << 16) /**< Shifted mode CYCLES64 for VDAC_CFG */ +#define VDAC_CFG_SINEMODEPRS (0x1UL << 19) /**< Sinemode prs */ +#define _VDAC_CFG_SINEMODEPRS_SHIFT 19 /**< Shift value for VDAC_SINEMODEPRS */ +#define _VDAC_CFG_SINEMODEPRS_MASK 0x80000UL /**< Bit mask for VDAC_SINEMODEPRS */ +#define _VDAC_CFG_SINEMODEPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_SINEMODEPRS_DISSINEMODEPRS 0x00000000UL /**< Mode DISSINEMODEPRS for VDAC_CFG */ +#define _VDAC_CFG_SINEMODEPRS_ENSINEMODEPRS 0x00000001UL /**< Mode ENSINEMODEPRS for VDAC_CFG */ +#define VDAC_CFG_SINEMODEPRS_DEFAULT (_VDAC_CFG_SINEMODEPRS_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_SINEMODEPRS_DISSINEMODEPRS (_VDAC_CFG_SINEMODEPRS_DISSINEMODEPRS << 19) /**< Shifted mode DISSINEMODEPRS for VDAC_CFG */ +#define VDAC_CFG_SINEMODEPRS_ENSINEMODEPRS (_VDAC_CFG_SINEMODEPRS_ENSINEMODEPRS << 19) /**< Shifted mode ENSINEMODEPRS for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_SHIFT 20 /**< Shift value for VDAC_REFRESHPERIOD */ +#define _VDAC_CFG_REFRESHPERIOD_MASK 0x700000UL /**< Bit mask for VDAC_REFRESHPERIOD */ +#define _VDAC_CFG_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES128 0x00000006UL /**< Mode CYCLES128 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES256 0x00000007UL /**< Mode CYCLES256 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_DEFAULT (_VDAC_CFG_REFRESHPERIOD_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES2 (_VDAC_CFG_REFRESHPERIOD_CYCLES2 << 20) /**< Shifted mode CYCLES2 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES4 (_VDAC_CFG_REFRESHPERIOD_CYCLES4 << 20) /**< Shifted mode CYCLES4 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES8 (_VDAC_CFG_REFRESHPERIOD_CYCLES8 << 20) /**< Shifted mode CYCLES8 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES16 (_VDAC_CFG_REFRESHPERIOD_CYCLES16 << 20) /**< Shifted mode CYCLES16 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES32 (_VDAC_CFG_REFRESHPERIOD_CYCLES32 << 20) /**< Shifted mode CYCLES32 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES64 (_VDAC_CFG_REFRESHPERIOD_CYCLES64 << 20) /**< Shifted mode CYCLES64 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES128 (_VDAC_CFG_REFRESHPERIOD_CYCLES128 << 20) /**< Shifted mode CYCLES128 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES256 (_VDAC_CFG_REFRESHPERIOD_CYCLES256 << 20) /**< Shifted mode CYCLES256 for VDAC_CFG */ +#define VDAC_CFG_BIASKEEPWARM (0x1UL << 24) /**< Bias Keepwarm Mode Enable */ +#define _VDAC_CFG_BIASKEEPWARM_SHIFT 24 /**< Shift value for VDAC_BIASKEEPWARM */ +#define _VDAC_CFG_BIASKEEPWARM_MASK 0x1000000UL /**< Bit mask for VDAC_BIASKEEPWARM */ +#define _VDAC_CFG_BIASKEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_BIASKEEPWARM_DEFAULT (_VDAC_CFG_BIASKEEPWARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DMAWU (0x1UL << 25) /**< VDAC DMA Wakeup */ +#define _VDAC_CFG_DMAWU_SHIFT 25 /**< Shift value for VDAC_DMAWU */ +#define _VDAC_CFG_DMAWU_MASK 0x2000000UL /**< Bit mask for VDAC_DMAWU */ +#define _VDAC_CFG_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DMAWU_DEFAULT (_VDAC_CFG_DMAWU_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_ONDEMANDCLK (0x1UL << 26) /**< Always allow clk_dac */ +#define _VDAC_CFG_ONDEMANDCLK_SHIFT 26 /**< Shift value for VDAC_ONDEMANDCLK */ +#define _VDAC_CFG_ONDEMANDCLK_MASK 0x4000000UL /**< Bit mask for VDAC_ONDEMANDCLK */ +#define _VDAC_CFG_ONDEMANDCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_ONDEMANDCLK_DEFAULT (_VDAC_CFG_ONDEMANDCLK_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT (0x1UL << 27) /**< Debug Halt */ +#define _VDAC_CFG_DBGHALT_SHIFT 27 /**< Shift value for VDAC_DBGHALT */ +#define _VDAC_CFG_DBGHALT_MASK 0x8000000UL /**< Bit mask for VDAC_DBGHALT */ +#define _VDAC_CFG_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CFG */ +#define _VDAC_CFG_DBGHALT_HALT 0x00000001UL /**< Mode HALT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_DEFAULT (_VDAC_CFG_DBGHALT_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_NORMAL (_VDAC_CFG_DBGHALT_NORMAL << 27) /**< Shifted mode NORMAL for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_HALT (_VDAC_CFG_DBGHALT_HALT << 27) /**< Shifted mode HALT for VDAC_CFG */ +#define _VDAC_CFG_WARMUPTIME_SHIFT 28 /**< Shift value for VDAC_WARMUPTIME */ +#define _VDAC_CFG_WARMUPTIME_MASK 0x70000000UL /**< Bit mask for VDAC_WARMUPTIME */ +#define _VDAC_CFG_WARMUPTIME_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_WARMUPTIME_DEFAULT (_VDAC_CFG_WARMUPTIME_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_OUTENPRS (0x1UL << 31) /**< PRS Controlled Output Enable */ +#define _VDAC_CFG_OUTENPRS_SHIFT 31 /**< Shift value for VDAC_OUTENPRS */ +#define _VDAC_CFG_OUTENPRS_MASK 0x80000000UL /**< Bit mask for VDAC_OUTENPRS */ +#define _VDAC_CFG_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_OUTENPRS_DISOUTENPRS 0x00000000UL /**< Mode DISOUTENPRS for VDAC_CFG */ +#define _VDAC_CFG_OUTENPRS_ENOUTENPRS 0x00000001UL /**< Mode ENOUTENPRS for VDAC_CFG */ +#define VDAC_CFG_OUTENPRS_DEFAULT (_VDAC_CFG_OUTENPRS_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_OUTENPRS_DISOUTENPRS (_VDAC_CFG_OUTENPRS_DISOUTENPRS << 31) /**< Shifted mode DISOUTENPRS for VDAC_CFG */ +#define VDAC_CFG_OUTENPRS_ENOUTENPRS (_VDAC_CFG_OUTENPRS_ENOUTENPRS << 31) /**< Shifted mode ENOUTENPRS for VDAC_CFG */ /* Bit fields for VDAC STATUS */ -#define _VDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for VDAC_STATUS */ -#define _VDAC_STATUS_MASK 0xFCDBF333UL /**< Mask for VDAC_STATUS */ -#define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */ -#define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */ -#define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */ -#define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */ -#define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */ -#define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */ -#define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warmed Status */ -#define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */ -#define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */ -#define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warmed Status */ -#define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */ -#define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */ -#define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOFULL (0x1UL << 8) /**< Channel 0 FIFO Full Status */ -#define _VDAC_STATUS_CH0FIFOFULL_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFULL */ -#define _VDAC_STATUS_CH0FIFOFULL_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFULL */ -#define _VDAC_STATUS_CH0FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOFULL_DEFAULT (_VDAC_STATUS_CH0FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOFULL (0x1UL << 9) /**< Channel 1 FIFO Full Status */ -#define _VDAC_STATUS_CH1FIFOFULL_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFULL */ -#define _VDAC_STATUS_CH1FIFOFULL_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFULL */ -#define _VDAC_STATUS_CH1FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOFULL_DEFAULT (_VDAC_STATUS_CH1FIFOFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define _VDAC_STATUS_CH0FIFOCNT_SHIFT 12 /**< Shift value for VDAC_CH0FIFOCNT */ -#define _VDAC_STATUS_CH0FIFOCNT_MASK 0x7000UL /**< Bit mask for VDAC_CH0FIFOCNT */ -#define _VDAC_STATUS_CH0FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOCNT_DEFAULT (_VDAC_STATUS_CH0FIFOCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define _VDAC_STATUS_CH1FIFOCNT_SHIFT 15 /**< Shift value for VDAC_CH1FIFOCNT */ -#define _VDAC_STATUS_CH1FIFOCNT_MASK 0x38000UL /**< Bit mask for VDAC_CH1FIFOCNT */ -#define _VDAC_STATUS_CH1FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOCNT_DEFAULT (_VDAC_STATUS_CH1FIFOCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0CURRENTSTATE (0x1UL << 19) /**< Channel 0 Current Status */ -#define _VDAC_STATUS_CH0CURRENTSTATE_SHIFT 19 /**< Shift value for VDAC_CH0CURRENTSTATE */ -#define _VDAC_STATUS_CH0CURRENTSTATE_MASK 0x80000UL /**< Bit mask for VDAC_CH0CURRENTSTATE */ -#define _VDAC_STATUS_CH0CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH0CURRENTSTATE_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1CURRENTSTATE (0x1UL << 20) /**< Channel 1 Current Status */ -#define _VDAC_STATUS_CH1CURRENTSTATE_SHIFT 20 /**< Shift value for VDAC_CH1CURRENTSTATE */ -#define _VDAC_STATUS_CH1CURRENTSTATE_MASK 0x100000UL /**< Bit mask for VDAC_CH1CURRENTSTATE */ -#define _VDAC_STATUS_CH1CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH1CURRENTSTATE_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOEMPTY (0x1UL << 22) /**< Channel 0 FIFO Empty Status */ -#define _VDAC_STATUS_CH0FIFOEMPTY_SHIFT 22 /**< Shift value for VDAC_CH0FIFOEMPTY */ -#define _VDAC_STATUS_CH0FIFOEMPTY_MASK 0x400000UL /**< Bit mask for VDAC_CH0FIFOEMPTY */ -#define _VDAC_STATUS_CH0FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH0FIFOEMPTY_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOEMPTY (0x1UL << 23) /**< Channel 1 FIFO Empty Status */ -#define _VDAC_STATUS_CH1FIFOEMPTY_SHIFT 23 /**< Shift value for VDAC_CH1FIFOEMPTY */ -#define _VDAC_STATUS_CH1FIFOEMPTY_MASK 0x800000UL /**< Bit mask for VDAC_CH1FIFOEMPTY */ -#define _VDAC_STATUS_CH1FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH1FIFOEMPTY_DEFAULT << 23) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOFLBUSY (0x1UL << 26) /**< CH0 FIFO Flush Sync Busy */ -#define _VDAC_STATUS_CH0FIFOFLBUSY_SHIFT 26 /**< Shift value for VDAC_CH0FIFOFLBUSY */ -#define _VDAC_STATUS_CH0FIFOFLBUSY_MASK 0x4000000UL /**< Bit mask for VDAC_CH0FIFOFLBUSY */ -#define _VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOFLBUSY (0x1UL << 27) /**< CH1 FIFO Flush Sync Busy */ -#define _VDAC_STATUS_CH1FIFOFLBUSY_SHIFT 27 /**< Shift value for VDAC_CH1FIFOFLBUSY */ -#define _VDAC_STATUS_CH1FIFOFLBUSY_MASK 0x8000000UL /**< Bit mask for VDAC_CH1FIFOFLBUSY */ -#define _VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_ABUSINPUTCONFLICT (0x1UL << 28) /**< ABUS Input Conflict Status */ -#define _VDAC_STATUS_ABUSINPUTCONFLICT_SHIFT 28 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_STATUS_ABUSINPUTCONFLICT_MASK 0x10000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT (_VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_SINEACTIVE (0x1UL << 29) /**< Sine Wave Output Status on Channel */ -#define _VDAC_STATUS_SINEACTIVE_SHIFT 29 /**< Shift value for VDAC_SINEACTIVE */ -#define _VDAC_STATUS_SINEACTIVE_MASK 0x20000000UL /**< Bit mask for VDAC_SINEACTIVE */ -#define _VDAC_STATUS_SINEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_SINEACTIVE_DEFAULT (_VDAC_STATUS_SINEACTIVE_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_ABUSALLOCERR (0x1UL << 30) /**< ABUS Allocation Error Status */ -#define _VDAC_STATUS_ABUSALLOCERR_SHIFT 30 /**< Shift value for VDAC_ABUSALLOCERR */ -#define _VDAC_STATUS_ABUSALLOCERR_MASK 0x40000000UL /**< Bit mask for VDAC_ABUSALLOCERR */ -#define _VDAC_STATUS_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_ABUSALLOCERR_DEFAULT (_VDAC_STATUS_ABUSALLOCERR_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy Combined */ -#define _VDAC_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for VDAC_SYNCBUSY */ -#define _VDAC_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for VDAC_SYNCBUSY */ -#define _VDAC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_SYNCBUSY_DEFAULT (_VDAC_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define _VDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for VDAC_STATUS */ +#define _VDAC_STATUS_MASK 0xFCDBF333UL /**< Mask for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */ +#define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */ +#define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warmed Status */ +#define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warmed Status */ +#define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFULL (0x1UL << 8) /**< Channel 0 FIFO Full Status */ +#define _VDAC_STATUS_CH0FIFOFULL_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFULL */ +#define _VDAC_STATUS_CH0FIFOFULL_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFULL */ +#define _VDAC_STATUS_CH0FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFULL_DEFAULT (_VDAC_STATUS_CH0FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFULL (0x1UL << 9) /**< Channel 1 FIFO Full Status */ +#define _VDAC_STATUS_CH1FIFOFULL_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFULL */ +#define _VDAC_STATUS_CH1FIFOFULL_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFULL */ +#define _VDAC_STATUS_CH1FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFULL_DEFAULT (_VDAC_STATUS_CH1FIFOFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define _VDAC_STATUS_CH0FIFOCNT_SHIFT 12 /**< Shift value for VDAC_CH0FIFOCNT */ +#define _VDAC_STATUS_CH0FIFOCNT_MASK 0x7000UL /**< Bit mask for VDAC_CH0FIFOCNT */ +#define _VDAC_STATUS_CH0FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOCNT_DEFAULT (_VDAC_STATUS_CH0FIFOCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define _VDAC_STATUS_CH1FIFOCNT_SHIFT 15 /**< Shift value for VDAC_CH1FIFOCNT */ +#define _VDAC_STATUS_CH1FIFOCNT_MASK 0x38000UL /**< Bit mask for VDAC_CH1FIFOCNT */ +#define _VDAC_STATUS_CH1FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOCNT_DEFAULT (_VDAC_STATUS_CH1FIFOCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0CURRENTSTATE (0x1UL << 19) /**< Channel 0 Current Status */ +#define _VDAC_STATUS_CH0CURRENTSTATE_SHIFT 19 /**< Shift value for VDAC_CH0CURRENTSTATE */ +#define _VDAC_STATUS_CH0CURRENTSTATE_MASK 0x80000UL /**< Bit mask for VDAC_CH0CURRENTSTATE */ +#define _VDAC_STATUS_CH0CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH0CURRENTSTATE_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1CURRENTSTATE (0x1UL << 20) /**< Channel 1 Current Status */ +#define _VDAC_STATUS_CH1CURRENTSTATE_SHIFT 20 /**< Shift value for VDAC_CH1CURRENTSTATE */ +#define _VDAC_STATUS_CH1CURRENTSTATE_MASK 0x100000UL /**< Bit mask for VDAC_CH1CURRENTSTATE */ +#define _VDAC_STATUS_CH1CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH1CURRENTSTATE_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOEMPTY (0x1UL << 22) /**< Channel 0 FIFO Empty Status */ +#define _VDAC_STATUS_CH0FIFOEMPTY_SHIFT 22 /**< Shift value for VDAC_CH0FIFOEMPTY */ +#define _VDAC_STATUS_CH0FIFOEMPTY_MASK 0x400000UL /**< Bit mask for VDAC_CH0FIFOEMPTY */ +#define _VDAC_STATUS_CH0FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH0FIFOEMPTY_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOEMPTY (0x1UL << 23) /**< Channel 1 FIFO Empty Status */ +#define _VDAC_STATUS_CH1FIFOEMPTY_SHIFT 23 /**< Shift value for VDAC_CH1FIFOEMPTY */ +#define _VDAC_STATUS_CH1FIFOEMPTY_MASK 0x800000UL /**< Bit mask for VDAC_CH1FIFOEMPTY */ +#define _VDAC_STATUS_CH1FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH1FIFOEMPTY_DEFAULT << 23) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFLBUSY (0x1UL << 26) /**< CH0 FIFO Flush Sync Busy */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_SHIFT 26 /**< Shift value for VDAC_CH0FIFOFLBUSY */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_MASK 0x4000000UL /**< Bit mask for VDAC_CH0FIFOFLBUSY */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFLBUSY (0x1UL << 27) /**< CH1 FIFO Flush Sync Busy */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_SHIFT 27 /**< Shift value for VDAC_CH1FIFOFLBUSY */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_MASK 0x8000000UL /**< Bit mask for VDAC_CH1FIFOFLBUSY */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSINPUTCONFLICT (0x1UL << 28) /**< ABUS Input Conflict Status */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_SHIFT 28 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_MASK 0x10000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT (_VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SINEACTIVE (0x1UL << 29) /**< Sine Wave Output Status on Channel */ +#define _VDAC_STATUS_SINEACTIVE_SHIFT 29 /**< Shift value for VDAC_SINEACTIVE */ +#define _VDAC_STATUS_SINEACTIVE_MASK 0x20000000UL /**< Bit mask for VDAC_SINEACTIVE */ +#define _VDAC_STATUS_SINEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SINEACTIVE_DEFAULT (_VDAC_STATUS_SINEACTIVE_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSALLOCERR (0x1UL << 30) /**< ABUS Allocation Error Status */ +#define _VDAC_STATUS_ABUSALLOCERR_SHIFT 30 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_STATUS_ABUSALLOCERR_MASK 0x40000000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_STATUS_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSALLOCERR_DEFAULT (_VDAC_STATUS_ABUSALLOCERR_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy Combined */ +#define _VDAC_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for VDAC_SYNCBUSY */ +#define _VDAC_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for VDAC_SYNCBUSY */ +#define _VDAC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SYNCBUSY_DEFAULT (_VDAC_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_STATUS */ /* Bit fields for VDAC CH0CFG */ -#define _VDAC_CH0CFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH0CFG */ -#define VDAC_CH0CFG_CONVMODE (0x1UL << 0) /**< Channel 0 Conversion Mode */ -#define _VDAC_CH0CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ -#define _VDAC_CH0CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ -#define _VDAC_CH0CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CFG */ -#define VDAC_CH0CFG_CONVMODE_DEFAULT (_VDAC_CH0CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_CONVMODE_CONTINUOUS (_VDAC_CH0CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CFG */ -#define VDAC_CH0CFG_CONVMODE_SAMPLEOFF (_VDAC_CH0CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CFG */ -#define VDAC_CH0CFG_POWERMODE (0x1UL << 2) /**< Channel 0 Power Mode */ -#define _VDAC_CH0CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ -#define _VDAC_CH0CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ -#define _VDAC_CH0CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH0CFG */ -#define VDAC_CH0CFG_POWERMODE_DEFAULT (_VDAC_CH0CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_POWERMODE_HIGHPOWER (_VDAC_CH0CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH0CFG */ -#define VDAC_CH0CFG_POWERMODE_LOWPOWER (_VDAC_CH0CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ -#define _VDAC_CH0CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ -#define _VDAC_CH0CFG_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_LESENSE 0x00000003UL /**< Mode LESENSE for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_DEFAULT (_VDAC_CH0CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_NONE (_VDAC_CH0CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_SW (_VDAC_CH0CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_SYNCPRS (_VDAC_CH0CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_LESENSE (_VDAC_CH0CFG_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH0CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_ASYNCPRS (_VDAC_CH0CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ -#define _VDAC_CH0CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ -#define _VDAC_CH0CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ -#define VDAC_CH0CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH0CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_REFRESHSOURCE_NONE (_VDAC_CH0CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH0CFG */ -#define VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH0CFG */ -#define VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ -#define VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ -#define _VDAC_CH0CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ -#define _VDAC_CH0CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_FIFODVL_DEFAULT (_VDAC_CH0CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 0 High Cap Load Mode Enable */ -#define _VDAC_CH0CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ -#define _VDAC_CH0CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ -#define _VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_KEEPWARM (0x1UL << 16) /**< Channel 0 Keepwarm Mode Enable */ -#define _VDAC_CH0CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ -#define _VDAC_CH0CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ -#define _VDAC_CH0CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_KEEPWARM_DEFAULT (_VDAC_CH0CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE (0x1UL << 0) /**< Channel 0 Conversion Mode */ +#define _VDAC_CH0CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH0CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH0CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_DEFAULT (_VDAC_CH0CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_CONTINUOUS (_VDAC_CH0CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_SAMPLEOFF (_VDAC_CH0CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE (0x1UL << 2) /**< Channel 0 Power Mode */ +#define _VDAC_CH0CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ +#define _VDAC_CH0CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ +#define _VDAC_CH0CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_DEFAULT (_VDAC_CH0CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_HIGHPOWER (_VDAC_CH0CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_LOWPOWER (_VDAC_CH0CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH0CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH0CFG_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_LESENSE 0x00000003UL /**< Mode LESENSE for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_DEFAULT (_VDAC_CH0CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_NONE (_VDAC_CH0CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_SW (_VDAC_CH0CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_SYNCPRS (_VDAC_CH0CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_LESENSE (_VDAC_CH0CFG_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH0CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_ASYNCPRS (_VDAC_CH0CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ +#define _VDAC_CH0CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ +#define _VDAC_CH0CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH0CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_NONE (_VDAC_CH0CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ +#define _VDAC_CH0CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ +#define _VDAC_CH0CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_FIFODVL_DEFAULT (_VDAC_CH0CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 0 High Cap Load Mode Enable */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_KEEPWARM (0x1UL << 16) /**< Channel 0 Keepwarm Mode Enable */ +#define _VDAC_CH0CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ +#define _VDAC_CH0CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ +#define _VDAC_CH0CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_KEEPWARM_DEFAULT (_VDAC_CH0CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ /* Bit fields for VDAC CH1CFG */ -#define _VDAC_CH1CFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH1CFG */ -#define VDAC_CH1CFG_CONVMODE (0x1UL << 0) /**< Channel 1 Conversion Mode */ -#define _VDAC_CH1CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ -#define _VDAC_CH1CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ -#define _VDAC_CH1CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CFG */ -#define VDAC_CH1CFG_CONVMODE_DEFAULT (_VDAC_CH1CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_CONVMODE_CONTINUOUS (_VDAC_CH1CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CFG */ -#define VDAC_CH1CFG_CONVMODE_SAMPLEOFF (_VDAC_CH1CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CFG */ -#define VDAC_CH1CFG_POWERMODE (0x1UL << 2) /**< Channel 1 Power Mode */ -#define _VDAC_CH1CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ -#define _VDAC_CH1CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ -#define _VDAC_CH1CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH1CFG */ -#define VDAC_CH1CFG_POWERMODE_DEFAULT (_VDAC_CH1CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_POWERMODE_HIGHPOWER (_VDAC_CH1CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH1CFG */ -#define VDAC_CH1CFG_POWERMODE_LOWPOWER (_VDAC_CH1CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ -#define _VDAC_CH1CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ -#define _VDAC_CH1CFG_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_DEFAULT (_VDAC_CH1CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_NONE (_VDAC_CH1CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_SW (_VDAC_CH1CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_SYNCPRS (_VDAC_CH1CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH1CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_ASYNCPRS (_VDAC_CH1CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ -#define _VDAC_CH1CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ -#define _VDAC_CH1CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ -#define VDAC_CH1CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH1CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_REFRESHSOURCE_NONE (_VDAC_CH1CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH1CFG */ -#define VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH1CFG */ -#define VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ -#define VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ -#define _VDAC_CH1CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ -#define _VDAC_CH1CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_FIFODVL_DEFAULT (_VDAC_CH1CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 1 High Cap Load Mode Enable */ -#define _VDAC_CH1CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ -#define _VDAC_CH1CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ -#define _VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_KEEPWARM (0x1UL << 16) /**< Channel 1 Keepwarm Mode Enable */ -#define _VDAC_CH1CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ -#define _VDAC_CH1CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ -#define _VDAC_CH1CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_KEEPWARM_DEFAULT (_VDAC_CH1CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE (0x1UL << 0) /**< Channel 1 Conversion Mode */ +#define _VDAC_CH1CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH1CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH1CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_DEFAULT (_VDAC_CH1CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_CONTINUOUS (_VDAC_CH1CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_SAMPLEOFF (_VDAC_CH1CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE (0x1UL << 2) /**< Channel 1 Power Mode */ +#define _VDAC_CH1CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ +#define _VDAC_CH1CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ +#define _VDAC_CH1CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_DEFAULT (_VDAC_CH1CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_HIGHPOWER (_VDAC_CH1CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_LOWPOWER (_VDAC_CH1CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH1CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH1CFG_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_DEFAULT (_VDAC_CH1CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_NONE (_VDAC_CH1CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_SW (_VDAC_CH1CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_SYNCPRS (_VDAC_CH1CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH1CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_ASYNCPRS (_VDAC_CH1CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ +#define _VDAC_CH1CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ +#define _VDAC_CH1CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH1CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_NONE (_VDAC_CH1CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ +#define _VDAC_CH1CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ +#define _VDAC_CH1CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_FIFODVL_DEFAULT (_VDAC_CH1CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 1 High Cap Load Mode Enable */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_KEEPWARM (0x1UL << 16) /**< Channel 1 Keepwarm Mode Enable */ +#define _VDAC_CH1CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ +#define _VDAC_CH1CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ +#define _VDAC_CH1CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_KEEPWARM_DEFAULT (_VDAC_CH1CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ /* Bit fields for VDAC CMD */ -#define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */ -#define _VDAC_CMD_MASK 0x00000F33UL /**< Mask for VDAC_CMD */ -#define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */ -#define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */ -#define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */ -#define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */ -#define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */ -#define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */ -#define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1EN (0x1UL << 4) /**< DAC Channel 1 Enable */ -#define _VDAC_CMD_CH1EN_SHIFT 4 /**< Shift value for VDAC_CH1EN */ -#define _VDAC_CMD_CH1EN_MASK 0x10UL /**< Bit mask for VDAC_CH1EN */ -#define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1DIS (0x1UL << 5) /**< DAC Channel 1 Disable */ -#define _VDAC_CMD_CH1DIS_SHIFT 5 /**< Shift value for VDAC_CH1DIS */ -#define _VDAC_CMD_CH1DIS_MASK 0x20UL /**< Bit mask for VDAC_CH1DIS */ -#define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH0FIFOFLUSH (0x1UL << 8) /**< CH0 WFIFO Flush */ -#define _VDAC_CMD_CH0FIFOFLUSH_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFLUSH */ -#define _VDAC_CMD_CH0FIFOFLUSH_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFLUSH */ -#define _VDAC_CMD_CH0FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH0FIFOFLUSH_DEFAULT (_VDAC_CMD_CH0FIFOFLUSH_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1FIFOFLUSH (0x1UL << 9) /**< CH1 WFIFO Flush */ -#define _VDAC_CMD_CH1FIFOFLUSH_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFLUSH */ -#define _VDAC_CMD_CH1FIFOFLUSH_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFLUSH */ -#define _VDAC_CMD_CH1FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1FIFOFLUSH_DEFAULT (_VDAC_CMD_CH1FIFOFLUSH_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_SINEMODESTART (0x1UL << 10) /**< Start Sine Wave Generation */ -#define _VDAC_CMD_SINEMODESTART_SHIFT 10 /**< Shift value for VDAC_SINEMODESTART */ -#define _VDAC_CMD_SINEMODESTART_MASK 0x400UL /**< Bit mask for VDAC_SINEMODESTART */ -#define _VDAC_CMD_SINEMODESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_SINEMODESTART_DEFAULT (_VDAC_CMD_SINEMODESTART_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_SINEMODESTOP (0x1UL << 11) /**< Stop Sine Wave Generation */ -#define _VDAC_CMD_SINEMODESTOP_SHIFT 11 /**< Shift value for VDAC_SINEMODESTOP */ -#define _VDAC_CMD_SINEMODESTOP_MASK 0x800UL /**< Bit mask for VDAC_SINEMODESTOP */ -#define _VDAC_CMD_SINEMODESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_SINEMODESTOP_DEFAULT (_VDAC_CMD_SINEMODESTOP_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */ +#define _VDAC_CMD_MASK 0x00000F33UL /**< Mask for VDAC_CMD */ +#define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */ +#define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */ +#define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN (0x1UL << 4) /**< DAC Channel 1 Enable */ +#define _VDAC_CMD_CH1EN_SHIFT 4 /**< Shift value for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_MASK 0x10UL /**< Bit mask for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS (0x1UL << 5) /**< DAC Channel 1 Disable */ +#define _VDAC_CMD_CH1DIS_SHIFT 5 /**< Shift value for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_MASK 0x20UL /**< Bit mask for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0FIFOFLUSH (0x1UL << 8) /**< CH0 WFIFO Flush */ +#define _VDAC_CMD_CH0FIFOFLUSH_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFLUSH */ +#define _VDAC_CMD_CH0FIFOFLUSH_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFLUSH */ +#define _VDAC_CMD_CH0FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0FIFOFLUSH_DEFAULT (_VDAC_CMD_CH0FIFOFLUSH_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1FIFOFLUSH (0x1UL << 9) /**< CH1 WFIFO Flush */ +#define _VDAC_CMD_CH1FIFOFLUSH_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFLUSH */ +#define _VDAC_CMD_CH1FIFOFLUSH_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFLUSH */ +#define _VDAC_CMD_CH1FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1FIFOFLUSH_DEFAULT (_VDAC_CMD_CH1FIFOFLUSH_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTART (0x1UL << 10) /**< Start Sine Wave Generation */ +#define _VDAC_CMD_SINEMODESTART_SHIFT 10 /**< Shift value for VDAC_SINEMODESTART */ +#define _VDAC_CMD_SINEMODESTART_MASK 0x400UL /**< Bit mask for VDAC_SINEMODESTART */ +#define _VDAC_CMD_SINEMODESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTART_DEFAULT (_VDAC_CMD_SINEMODESTART_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTOP (0x1UL << 11) /**< Stop Sine Wave Generation */ +#define _VDAC_CMD_SINEMODESTOP_SHIFT 11 /**< Shift value for VDAC_SINEMODESTOP */ +#define _VDAC_CMD_SINEMODESTOP_MASK 0x800UL /**< Bit mask for VDAC_SINEMODESTOP */ +#define _VDAC_CMD_SINEMODESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTOP_DEFAULT (_VDAC_CMD_SINEMODESTOP_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CMD */ /* Bit fields for VDAC IF */ -#define _VDAC_IF_RESETVALUE 0x00000000UL /**< Default value for VDAC_IF */ -#define _VDAC_IF_MASK 0x04340333UL /**< Mask for VDAC_IF */ -#define VDAC_IF_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ -#define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ -#define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ -#define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ -#define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ -#define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ -#define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ -#define _VDAC_IF_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ -#define _VDAC_IF_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ -#define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ -#define _VDAC_IF_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ -#define _VDAC_IF_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ -#define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ -#define _VDAC_IF_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ -#define _VDAC_IF_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ -#define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ -#define _VDAC_IF_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ -#define _VDAC_IF_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ -#define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_ABUSALLOCERR (0x1UL << 18) /**< ABUS Port Allocation Error Flag */ -#define _VDAC_IF_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ -#define _VDAC_IF_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ -#define _VDAC_IF_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_ABUSALLOCERR_DEFAULT (_VDAC_IF_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ -#define _VDAC_IF_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ -#define _VDAC_IF_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ -#define _VDAC_IF_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0DVL_DEFAULT (_VDAC_IF_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ -#define _VDAC_IF_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ -#define _VDAC_IF_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ -#define _VDAC_IF_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1DVL_DEFAULT (_VDAC_IF_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Error Flag */ -#define _VDAC_IF_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_IF_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_IF_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IF_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IF */ +#define _VDAC_IF_RESETVALUE 0x00000000UL /**< Default value for VDAC_IF */ +#define _VDAC_IF_MASK 0x04340333UL /**< Mask for VDAC_IF */ +#define VDAC_IF_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSALLOCERR (0x1UL << 18) /**< ABUS Port Allocation Error Flag */ +#define _VDAC_IF_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_IF_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_IF_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSALLOCERR_DEFAULT (_VDAC_IF_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ +#define _VDAC_IF_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ +#define _VDAC_IF_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ +#define _VDAC_IF_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0DVL_DEFAULT (_VDAC_IF_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ +#define _VDAC_IF_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ +#define _VDAC_IF_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ +#define _VDAC_IF_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1DVL_DEFAULT (_VDAC_IF_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Error Flag */ +#define _VDAC_IF_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IF_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IF_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IF_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IF */ /* Bit fields for VDAC IEN */ -#define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */ -#define _VDAC_IEN_MASK 0x04340333UL /**< Mask for VDAC_IEN */ -#define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ -#define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ -#define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ -#define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ -#define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ -#define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ -#define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ -#define _VDAC_IEN_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ -#define _VDAC_IEN_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ -#define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ -#define _VDAC_IEN_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ -#define _VDAC_IEN_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ -#define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ -#define _VDAC_IEN_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ -#define _VDAC_IEN_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ -#define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ -#define _VDAC_IEN_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ -#define _VDAC_IEN_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ -#define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_ABUSALLOCERR (0x1UL << 18) /**< ABUS Allocation Error Interrupt Flag */ -#define _VDAC_IEN_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ -#define _VDAC_IEN_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ -#define _VDAC_IEN_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_ABUSALLOCERR_DEFAULT (_VDAC_IEN_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ -#define _VDAC_IEN_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ -#define _VDAC_IEN_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ -#define _VDAC_IEN_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0DVL_DEFAULT (_VDAC_IEN_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ -#define _VDAC_IEN_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ -#define _VDAC_IEN_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ -#define _VDAC_IEN_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1DVL_DEFAULT (_VDAC_IEN_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Interrupt Flag */ -#define _VDAC_IEN_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_IEN_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */ +#define _VDAC_IEN_MASK 0x04340333UL /**< Mask for VDAC_IEN */ +#define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ +#define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ +#define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ +#define _VDAC_IEN_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ +#define _VDAC_IEN_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ +#define _VDAC_IEN_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ +#define _VDAC_IEN_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSALLOCERR (0x1UL << 18) /**< ABUS Allocation Error Interrupt Flag */ +#define _VDAC_IEN_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_IEN_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_IEN_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSALLOCERR_DEFAULT (_VDAC_IEN_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ +#define _VDAC_IEN_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ +#define _VDAC_IEN_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ +#define _VDAC_IEN_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0DVL_DEFAULT (_VDAC_IEN_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ +#define _VDAC_IEN_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ +#define _VDAC_IEN_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ +#define _VDAC_IEN_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1DVL_DEFAULT (_VDAC_IEN_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Interrupt Flag */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IEN */ /* Bit fields for VDAC CH0F */ -#define _VDAC_CH0F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0F */ -#define _VDAC_CH0F_MASK 0x00000FFFUL /**< Mask for VDAC_CH0F */ -#define _VDAC_CH0F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ -#define _VDAC_CH0F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ -#define _VDAC_CH0F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0F */ -#define VDAC_CH0F_DATA_DEFAULT (_VDAC_CH0F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0F */ +#define _VDAC_CH0F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0F */ +#define _VDAC_CH0F_MASK 0x00000FFFUL /**< Mask for VDAC_CH0F */ +#define _VDAC_CH0F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH0F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH0F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0F */ +#define VDAC_CH0F_DATA_DEFAULT (_VDAC_CH0F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0F */ /* Bit fields for VDAC CH1F */ -#define _VDAC_CH1F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1F */ -#define _VDAC_CH1F_MASK 0x00000FFFUL /**< Mask for VDAC_CH1F */ -#define _VDAC_CH1F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ -#define _VDAC_CH1F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ -#define _VDAC_CH1F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1F */ -#define VDAC_CH1F_DATA_DEFAULT (_VDAC_CH1F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1F */ +#define _VDAC_CH1F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1F */ +#define _VDAC_CH1F_MASK 0x00000FFFUL /**< Mask for VDAC_CH1F */ +#define _VDAC_CH1F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH1F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH1F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1F */ +#define VDAC_CH1F_DATA_DEFAULT (_VDAC_CH1F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1F */ /* Bit fields for VDAC OUTCTRL */ -#define _VDAC_OUTCTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_MASK 0x7FDFF333UL /**< Mask for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_MAINOUTENCH0 (0x1UL << 0) /**< CH0 Main Output Enable */ -#define _VDAC_OUTCTRL_MAINOUTENCH0_SHIFT 0 /**< Shift value for VDAC_MAINOUTENCH0 */ -#define _VDAC_OUTCTRL_MAINOUTENCH0_MASK 0x1UL /**< Bit mask for VDAC_MAINOUTENCH0 */ -#define _VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_MAINOUTENCH1 (0x1UL << 1) /**< CH1 Main Output Enable */ -#define _VDAC_OUTCTRL_MAINOUTENCH1_SHIFT 1 /**< Shift value for VDAC_MAINOUTENCH1 */ -#define _VDAC_OUTCTRL_MAINOUTENCH1_MASK 0x2UL /**< Bit mask for VDAC_MAINOUTENCH1 */ -#define _VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_AUXOUTENCH0 (0x1UL << 4) /**< CH0 Alternative Output Enable */ -#define _VDAC_OUTCTRL_AUXOUTENCH0_SHIFT 4 /**< Shift value for VDAC_AUXOUTENCH0 */ -#define _VDAC_OUTCTRL_AUXOUTENCH0_MASK 0x10UL /**< Bit mask for VDAC_AUXOUTENCH0 */ -#define _VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_AUXOUTENCH1 (0x1UL << 5) /**< CH1 Alternative Output Enable */ -#define _VDAC_OUTCTRL_AUXOUTENCH1_SHIFT 5 /**< Shift value for VDAC_AUXOUTENCH1 */ -#define _VDAC_OUTCTRL_AUXOUTENCH1_MASK 0x20UL /**< Bit mask for VDAC_AUXOUTENCH1 */ -#define _VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_SHORTCH0 (0x1UL << 8) /**< CH1 Main and Alternative Output Short */ -#define _VDAC_OUTCTRL_SHORTCH0_SHIFT 8 /**< Shift value for VDAC_SHORTCH0 */ -#define _VDAC_OUTCTRL_SHORTCH0_MASK 0x100UL /**< Bit mask for VDAC_SHORTCH0 */ -#define _VDAC_OUTCTRL_SHORTCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_SHORTCH0_DEFAULT (_VDAC_OUTCTRL_SHORTCH0_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_SHORTCH1 (0x1UL << 9) /**< CH0 Main and Alternative Output Short */ -#define _VDAC_OUTCTRL_SHORTCH1_SHIFT 9 /**< Shift value for VDAC_SHORTCH1 */ -#define _VDAC_OUTCTRL_SHORTCH1_MASK 0x200UL /**< Bit mask for VDAC_SHORTCH1 */ -#define _VDAC_OUTCTRL_SHORTCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_SHORTCH1_DEFAULT (_VDAC_OUTCTRL_SHORTCH1_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_SHIFT 12 /**< Shift value for VDAC_ABUSPORTSELCH0 */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_MASK 0x7000UL /**< Bit mask for VDAC_ABUSPORTSELCH0 */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH0_NONE << 12) /**< Shifted mode NONE for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA << 12) /**< Shifted mode PORTA for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB << 12) /**< Shifted mode PORTB for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC << 12) /**< Shifted mode PORTC for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD << 12) /**< Shifted mode PORTD for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPINSELCH0_SHIFT 15 /**< Shift value for VDAC_ABUSPINSELCH0 */ -#define _VDAC_OUTCTRL_ABUSPINSELCH0_MASK 0x1F8000UL /**< Bit mask for VDAC_ABUSPINSELCH0 */ -#define _VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_SHIFT 22 /**< Shift value for VDAC_ABUSPORTSELCH1 */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_MASK 0x1C00000UL /**< Bit mask for VDAC_ABUSPORTSELCH1 */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH1_NONE << 22) /**< Shifted mode NONE for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA << 22) /**< Shifted mode PORTA for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB << 22) /**< Shifted mode PORTB for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC << 22) /**< Shifted mode PORTC for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD << 22) /**< Shifted mode PORTD for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPINSELCH1_SHIFT 25 /**< Shift value for VDAC_ABUSPINSELCH1 */ -#define _VDAC_OUTCTRL_ABUSPINSELCH1_MASK 0x7E000000UL /**< Bit mask for VDAC_ABUSPINSELCH1 */ -#define _VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_MASK 0x7FDFF333UL /**< Mask for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH0 (0x1UL << 0) /**< CH0 Main Output Enable */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_SHIFT 0 /**< Shift value for VDAC_MAINOUTENCH0 */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_MASK 0x1UL /**< Bit mask for VDAC_MAINOUTENCH0 */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH1 (0x1UL << 1) /**< CH1 Main Output Enable */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_SHIFT 1 /**< Shift value for VDAC_MAINOUTENCH1 */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_MASK 0x2UL /**< Bit mask for VDAC_MAINOUTENCH1 */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH0 (0x1UL << 4) /**< CH0 Alternative Output Enable */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_SHIFT 4 /**< Shift value for VDAC_AUXOUTENCH0 */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_MASK 0x10UL /**< Bit mask for VDAC_AUXOUTENCH0 */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH1 (0x1UL << 5) /**< CH1 Alternative Output Enable */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_SHIFT 5 /**< Shift value for VDAC_AUXOUTENCH1 */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_MASK 0x20UL /**< Bit mask for VDAC_AUXOUTENCH1 */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH0 (0x1UL << 8) /**< CH1 Main and Alternative Output Short */ +#define _VDAC_OUTCTRL_SHORTCH0_SHIFT 8 /**< Shift value for VDAC_SHORTCH0 */ +#define _VDAC_OUTCTRL_SHORTCH0_MASK 0x100UL /**< Bit mask for VDAC_SHORTCH0 */ +#define _VDAC_OUTCTRL_SHORTCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH0_DEFAULT (_VDAC_OUTCTRL_SHORTCH0_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH1 (0x1UL << 9) /**< CH0 Main and Alternative Output Short */ +#define _VDAC_OUTCTRL_SHORTCH1_SHIFT 9 /**< Shift value for VDAC_SHORTCH1 */ +#define _VDAC_OUTCTRL_SHORTCH1_MASK 0x200UL /**< Bit mask for VDAC_SHORTCH1 */ +#define _VDAC_OUTCTRL_SHORTCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH1_DEFAULT (_VDAC_OUTCTRL_SHORTCH1_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_SHIFT 12 /**< Shift value for VDAC_ABUSPORTSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_MASK 0x7000UL /**< Bit mask for VDAC_ABUSPORTSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH0_NONE << 12) /**< Shifted mode NONE for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA << 12) /**< Shifted mode PORTA for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB << 12) /**< Shifted mode PORTB for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC << 12) /**< Shifted mode PORTC for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD << 12) /**< Shifted mode PORTD for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_SHIFT 15 /**< Shift value for VDAC_ABUSPINSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_MASK 0x1F8000UL /**< Bit mask for VDAC_ABUSPINSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_SHIFT 22 /**< Shift value for VDAC_ABUSPORTSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_MASK 0x1C00000UL /**< Bit mask for VDAC_ABUSPORTSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH1_NONE << 22) /**< Shifted mode NONE for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA << 22) /**< Shifted mode PORTA for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB << 22) /**< Shifted mode PORTB for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC << 22) /**< Shifted mode PORTC for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD << 22) /**< Shifted mode PORTD for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_SHIFT 25 /**< Shift value for VDAC_ABUSPINSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_MASK 0x7E000000UL /**< Bit mask for VDAC_ABUSPINSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ /* Bit fields for VDAC OUTTIMERCFG */ -#define _VDAC_OUTTIMERCFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTTIMERCFG */ -#define _VDAC_OUTTIMERCFG_MASK 0x01FF83FFUL /**< Mask for VDAC_OUTTIMERCFG */ -#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_SHIFT 0 /**< Shift value for VDAC_CH0OUTHOLDTIME */ -#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK 0x3FFUL /**< Bit mask for VDAC_CH0OUTHOLDTIME */ -#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ -#define VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ -#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_SHIFT 15 /**< Shift value for VDAC_CH1OUTHOLDTIME */ -#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_MASK 0x1FF8000UL /**< Bit mask for VDAC_CH1OUTHOLDTIME */ -#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ -#define VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_MASK 0x01FF83FFUL /**< Mask for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_SHIFT 0 /**< Shift value for VDAC_CH0OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK 0x3FFUL /**< Bit mask for VDAC_CH0OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ +#define VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_SHIFT 15 /**< Shift value for VDAC_CH1OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_MASK 0x1FF8000UL /**< Bit mask for VDAC_CH1OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ +#define VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ /** @} End of group EFR32SG28_VDAC_BitFields */ /** @} End of group EFR32SG28_VDAC */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_wdog.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_wdog.h index fba808b084..98f98bfaad 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_wdog.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28_wdog.h @@ -3,21 +3,21 @@ * @brief EFR32SG28 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -29,7 +29,6 @@ *****************************************************************************/ #ifndef EFR32SG28_WDOG_H #define EFR32SG28_WDOG_H - #define WDOG_HAS_SET_CLEAR /**************************************************************************//** @@ -43,51 +42,50 @@ *****************************************************************************/ /** WDOG Register Declaration. */ -typedef struct -{ - __IM uint32_t IPVERSION; /**< IP Version Register */ - __IOM uint32_t EN; /**< Enable Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CMD; /**< Command Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK; /**< Lock Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version Register */ - __IOM uint32_t EN_SET; /**< Enable Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_SET; /**< Lock Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - uint32_t RESERVED3[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version Register */ - __IOM uint32_t EN_CLR; /**< Enable Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_CLR; /**< Lock Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - uint32_t RESERVED5[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version Register */ - __IOM uint32_t EN_TGL; /**< Enable Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_TGL; /**< Lock Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ } WDOG_TypeDef; /** @} End of group EFR32SG28_WDOG */ @@ -99,276 +97,276 @@ typedef struct *****************************************************************************/ /* Bit fields for WDOG IPVERSION */ -#define _WDOG_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for WDOG_IPVERSION */ -#define _WDOG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for WDOG_IPVERSION */ -#define _WDOG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for WDOG_IPVERSION */ -#define _WDOG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for WDOG_IPVERSION */ -#define _WDOG_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for WDOG_IPVERSION */ -#define WDOG_IPVERSION_IPVERSION_DEFAULT (_WDOG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for WDOG_IPVERSION */ +#define WDOG_IPVERSION_IPVERSION_DEFAULT (_WDOG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IPVERSION */ /* Bit fields for WDOG EN */ -#define _WDOG_EN_RESETVALUE 0x00000000UL /**< Default value for WDOG_EN */ -#define _WDOG_EN_MASK 0x00000003UL /**< Mask for WDOG_EN */ -#define WDOG_EN_EN (0x1UL << 0) /**< Module Enable */ -#define _WDOG_EN_EN_SHIFT 0 /**< Shift value for WDOG_EN */ -#define _WDOG_EN_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ -#define _WDOG_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ -#define WDOG_EN_EN_DEFAULT (_WDOG_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_EN */ -#define WDOG_EN_DISABLING (0x1UL << 1) /**< Disabling busy status */ -#define _WDOG_EN_DISABLING_SHIFT 1 /**< Shift value for WDOG_DISABLING */ -#define _WDOG_EN_DISABLING_MASK 0x2UL /**< Bit mask for WDOG_DISABLING */ -#define _WDOG_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ -#define WDOG_EN_DISABLING_DEFAULT (_WDOG_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_EN */ +#define _WDOG_EN_RESETVALUE 0x00000000UL /**< Default value for WDOG_EN */ +#define _WDOG_EN_MASK 0x00000003UL /**< Mask for WDOG_EN */ +#define WDOG_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _WDOG_EN_EN_SHIFT 0 /**< Shift value for WDOG_EN */ +#define _WDOG_EN_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ +#define _WDOG_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ +#define WDOG_EN_EN_DEFAULT (_WDOG_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_EN */ +#define WDOG_EN_DISABLING (0x1UL << 1) /**< Disabling busy status */ +#define _WDOG_EN_DISABLING_SHIFT 1 /**< Shift value for WDOG_DISABLING */ +#define _WDOG_EN_DISABLING_MASK 0x2UL /**< Bit mask for WDOG_DISABLING */ +#define _WDOG_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ +#define WDOG_EN_DISABLING_DEFAULT (_WDOG_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_EN */ /* Bit fields for WDOG CFG */ -#define _WDOG_CFG_RESETVALUE 0x000F0000UL /**< Default value for WDOG_CFG */ -#define _WDOG_CFG_MASK 0x730F073FUL /**< Mask for WDOG_CFG */ -#define WDOG_CFG_CLRSRC (0x1UL << 0) /**< WDOG Clear Source */ -#define _WDOG_CFG_CLRSRC_SHIFT 0 /**< Shift value for WDOG_CLRSRC */ -#define _WDOG_CFG_CLRSRC_MASK 0x1UL /**< Bit mask for WDOG_CLRSRC */ -#define _WDOG_CFG_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CFG */ -#define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode PRSSRC0 for WDOG_CFG */ -#define WDOG_CFG_CLRSRC_DEFAULT (_WDOG_CFG_CLRSRC_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_CLRSRC_SW (_WDOG_CFG_CLRSRC_SW << 0) /**< Shifted mode SW for WDOG_CFG */ -#define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifted mode PRSSRC0 for WDOG_CFG */ -#define WDOG_CFG_EM1RUN (0x1UL << 1) /**< EM1 Run */ -#define _WDOG_CFG_EM1RUN_SHIFT 1 /**< Shift value for WDOG_EM1RUN */ -#define _WDOG_CFG_EM1RUN_MASK 0x2UL /**< Bit mask for WDOG_EM1RUN */ -#define _WDOG_CFG_EM1RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_EM1RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_EM1RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM1RUN_DEFAULT (_WDOG_CFG_EM1RUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_EM1RUN_DISABLE (_WDOG_CFG_EM1RUN_DISABLE << 1) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_EM1RUN_ENABLE (_WDOG_CFG_EM1RUN_ENABLE << 1) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM2RUN (0x1UL << 2) /**< EM2 Run */ -#define _WDOG_CFG_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ -#define _WDOG_CFG_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ -#define _WDOG_CFG_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_EM2RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_EM2RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM2RUN_DEFAULT (_WDOG_CFG_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_EM2RUN_DISABLE (_WDOG_CFG_EM2RUN_DISABLE << 2) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_EM2RUN_ENABLE (_WDOG_CFG_EM2RUN_ENABLE << 2) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM3RUN (0x1UL << 3) /**< EM3 Run */ -#define _WDOG_CFG_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ -#define _WDOG_CFG_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ -#define _WDOG_CFG_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_EM3RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_EM3RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM3RUN_DEFAULT (_WDOG_CFG_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_EM3RUN_DISABLE (_WDOG_CFG_EM3RUN_DISABLE << 3) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_EM3RUN_ENABLE (_WDOG_CFG_EM3RUN_ENABLE << 3) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM4BLOCK (0x1UL << 4) /**< EM4 Block */ -#define _WDOG_CFG_EM4BLOCK_SHIFT 4 /**< Shift value for WDOG_EM4BLOCK */ -#define _WDOG_CFG_EM4BLOCK_MASK 0x10UL /**< Bit mask for WDOG_EM4BLOCK */ -#define _WDOG_CFG_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_EM4BLOCK_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_EM4BLOCK_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM4BLOCK_DEFAULT (_WDOG_CFG_EM4BLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_EM4BLOCK_DISABLE (_WDOG_CFG_EM4BLOCK_DISABLE << 4) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_EM4BLOCK_ENABLE (_WDOG_CFG_EM4BLOCK_ENABLE << 4) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_DEBUGRUN (0x1UL << 5) /**< Debug Mode Run */ -#define _WDOG_CFG_DEBUGRUN_SHIFT 5 /**< Shift value for WDOG_DEBUGRUN */ -#define _WDOG_CFG_DEBUGRUN_MASK 0x20UL /**< Bit mask for WDOG_DEBUGRUN */ -#define _WDOG_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_DEBUGRUN_DEFAULT (_WDOG_CFG_DEBUGRUN_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_DEBUGRUN_DISABLE (_WDOG_CFG_DEBUGRUN_DISABLE << 5) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_DEBUGRUN_ENABLE (_WDOG_CFG_DEBUGRUN_ENABLE << 5) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_WDOGRSTDIS (0x1UL << 8) /**< WDOG Reset Disable */ -#define _WDOG_CFG_WDOGRSTDIS_SHIFT 8 /**< Shift value for WDOG_WDOGRSTDIS */ -#define _WDOG_CFG_WDOGRSTDIS_MASK 0x100UL /**< Bit mask for WDOG_WDOGRSTDIS */ -#define _WDOG_CFG_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CFG */ -#define _WDOG_CFG_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CFG */ -#define WDOG_CFG_WDOGRSTDIS_DEFAULT (_WDOG_CFG_WDOGRSTDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_WDOGRSTDIS_EN (_WDOG_CFG_WDOGRSTDIS_EN << 8) /**< Shifted mode EN for WDOG_CFG */ -#define WDOG_CFG_WDOGRSTDIS_DIS (_WDOG_CFG_WDOGRSTDIS_DIS << 8) /**< Shifted mode DIS for WDOG_CFG */ -#define WDOG_CFG_PRS0MISSRSTEN (0x1UL << 9) /**< PRS Src0 Missing Event WDOG Reset */ -#define _WDOG_CFG_PRS0MISSRSTEN_SHIFT 9 /**< Shift value for WDOG_PRS0MISSRSTEN */ -#define _WDOG_CFG_PRS0MISSRSTEN_MASK 0x200UL /**< Bit mask for WDOG_PRS0MISSRSTEN */ -#define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_PRS0MISSRSTEN_DEFAULT (_WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_PRS1MISSRSTEN (0x1UL << 10) /**< PRS Src1 Missing Event WDOG Reset */ -#define _WDOG_CFG_PRS1MISSRSTEN_SHIFT 10 /**< Shift value for WDOG_PRS1MISSRSTEN */ -#define _WDOG_CFG_PRS1MISSRSTEN_MASK 0x400UL /**< Bit mask for WDOG_PRS1MISSRSTEN */ -#define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SHIFT 16 /**< Shift value for WDOG_PERSEL */ -#define _WDOG_CFG_PERSEL_MASK 0xF0000UL /**< Bit mask for WDOG_PERSEL */ -#define _WDOG_CFG_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL0 0x00000000UL /**< Mode SEL0 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL8 0x00000008UL /**< Mode SEL8 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL9 0x00000009UL /**< Mode SEL9 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL10 0x0000000AUL /**< Mode SEL10 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL11 0x0000000BUL /**< Mode SEL11 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL12 0x0000000CUL /**< Mode SEL12 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL13 0x0000000DUL /**< Mode SEL13 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL14 0x0000000EUL /**< Mode SEL14 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL15 0x0000000FUL /**< Mode SEL15 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_DEFAULT (_WDOG_CFG_PERSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL0 (_WDOG_CFG_PERSEL_SEL0 << 16) /**< Shifted mode SEL0 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL1 (_WDOG_CFG_PERSEL_SEL1 << 16) /**< Shifted mode SEL1 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL2 (_WDOG_CFG_PERSEL_SEL2 << 16) /**< Shifted mode SEL2 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL3 (_WDOG_CFG_PERSEL_SEL3 << 16) /**< Shifted mode SEL3 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL4 (_WDOG_CFG_PERSEL_SEL4 << 16) /**< Shifted mode SEL4 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL5 (_WDOG_CFG_PERSEL_SEL5 << 16) /**< Shifted mode SEL5 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL6 (_WDOG_CFG_PERSEL_SEL6 << 16) /**< Shifted mode SEL6 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL7 (_WDOG_CFG_PERSEL_SEL7 << 16) /**< Shifted mode SEL7 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL8 (_WDOG_CFG_PERSEL_SEL8 << 16) /**< Shifted mode SEL8 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL9 (_WDOG_CFG_PERSEL_SEL9 << 16) /**< Shifted mode SEL9 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL10 (_WDOG_CFG_PERSEL_SEL10 << 16) /**< Shifted mode SEL10 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL11 (_WDOG_CFG_PERSEL_SEL11 << 16) /**< Shifted mode SEL11 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL12 (_WDOG_CFG_PERSEL_SEL12 << 16) /**< Shifted mode SEL12 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL13 (_WDOG_CFG_PERSEL_SEL13 << 16) /**< Shifted mode SEL13 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL14 (_WDOG_CFG_PERSEL_SEL14 << 16) /**< Shifted mode SEL14 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL15 (_WDOG_CFG_PERSEL_SEL15 << 16) /**< Shifted mode SEL15 for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_SHIFT 24 /**< Shift value for WDOG_WARNSEL */ -#define _WDOG_CFG_WARNSEL_MASK 0x3000000UL /**< Bit mask for WDOG_WARNSEL */ -#define _WDOG_CFG_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_DEFAULT (_WDOG_CFG_WARNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_DIS (_WDOG_CFG_WARNSEL_DIS << 24) /**< Shifted mode DIS for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_SEL1 (_WDOG_CFG_WARNSEL_SEL1 << 24) /**< Shifted mode SEL1 for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_SEL2 (_WDOG_CFG_WARNSEL_SEL2 << 24) /**< Shifted mode SEL2 for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_SEL3 (_WDOG_CFG_WARNSEL_SEL3 << 24) /**< Shifted mode SEL3 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SHIFT 28 /**< Shift value for WDOG_WINSEL */ -#define _WDOG_CFG_WINSEL_MASK 0x70000000UL /**< Bit mask for WDOG_WINSEL */ -#define _WDOG_CFG_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_DEFAULT (_WDOG_CFG_WINSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_WINSEL_DIS (_WDOG_CFG_WINSEL_DIS << 28) /**< Shifted mode DIS for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL1 (_WDOG_CFG_WINSEL_SEL1 << 28) /**< Shifted mode SEL1 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL2 (_WDOG_CFG_WINSEL_SEL2 << 28) /**< Shifted mode SEL2 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL3 (_WDOG_CFG_WINSEL_SEL3 << 28) /**< Shifted mode SEL3 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL4 (_WDOG_CFG_WINSEL_SEL4 << 28) /**< Shifted mode SEL4 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL5 (_WDOG_CFG_WINSEL_SEL5 << 28) /**< Shifted mode SEL5 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL6 (_WDOG_CFG_WINSEL_SEL6 << 28) /**< Shifted mode SEL6 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL7 (_WDOG_CFG_WINSEL_SEL7 << 28) /**< Shifted mode SEL7 for WDOG_CFG */ +#define _WDOG_CFG_RESETVALUE 0x000F0000UL /**< Default value for WDOG_CFG */ +#define _WDOG_CFG_MASK 0x730F073FUL /**< Mask for WDOG_CFG */ +#define WDOG_CFG_CLRSRC (0x1UL << 0) /**< WDOG Clear Source */ +#define _WDOG_CFG_CLRSRC_SHIFT 0 /**< Shift value for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_MASK 0x1UL /**< Bit mask for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_DEFAULT (_WDOG_CFG_CLRSRC_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_SW (_WDOG_CFG_CLRSRC_SW << 0) /**< Shifted mode SW for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifted mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_EM1RUN (0x1UL << 1) /**< EM1 Run */ +#define _WDOG_CFG_EM1RUN_SHIFT 1 /**< Shift value for WDOG_EM1RUN */ +#define _WDOG_CFG_EM1RUN_MASK 0x2UL /**< Bit mask for WDOG_EM1RUN */ +#define _WDOG_CFG_EM1RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM1RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM1RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_DEFAULT (_WDOG_CFG_EM1RUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_DISABLE (_WDOG_CFG_EM1RUN_DISABLE << 1) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_ENABLE (_WDOG_CFG_EM1RUN_ENABLE << 1) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN (0x1UL << 2) /**< EM2 Run */ +#define _WDOG_CFG_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DEFAULT (_WDOG_CFG_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DISABLE (_WDOG_CFG_EM2RUN_DISABLE << 2) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_ENABLE (_WDOG_CFG_EM2RUN_ENABLE << 2) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN (0x1UL << 3) /**< EM3 Run */ +#define _WDOG_CFG_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DEFAULT (_WDOG_CFG_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DISABLE (_WDOG_CFG_EM3RUN_DISABLE << 3) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_ENABLE (_WDOG_CFG_EM3RUN_ENABLE << 3) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK (0x1UL << 4) /**< EM4 Block */ +#define _WDOG_CFG_EM4BLOCK_SHIFT 4 /**< Shift value for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_MASK 0x10UL /**< Bit mask for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DEFAULT (_WDOG_CFG_EM4BLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DISABLE (_WDOG_CFG_EM4BLOCK_DISABLE << 4) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_ENABLE (_WDOG_CFG_EM4BLOCK_ENABLE << 4) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN (0x1UL << 5) /**< Debug Mode Run */ +#define _WDOG_CFG_DEBUGRUN_SHIFT 5 /**< Shift value for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_MASK 0x20UL /**< Bit mask for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DEFAULT (_WDOG_CFG_DEBUGRUN_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DISABLE (_WDOG_CFG_DEBUGRUN_DISABLE << 5) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_ENABLE (_WDOG_CFG_DEBUGRUN_ENABLE << 5) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS (0x1UL << 8) /**< WDOG Reset Disable */ +#define _WDOG_CFG_WDOGRSTDIS_SHIFT 8 /**< Shift value for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_MASK 0x100UL /**< Bit mask for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DEFAULT (_WDOG_CFG_WDOGRSTDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_EN (_WDOG_CFG_WDOGRSTDIS_EN << 8) /**< Shifted mode EN for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DIS (_WDOG_CFG_WDOGRSTDIS_DIS << 8) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN (0x1UL << 9) /**< PRS Src0 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS0MISSRSTEN_SHIFT 9 /**< Shift value for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_MASK 0x200UL /**< Bit mask for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN_DEFAULT (_WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN (0x1UL << 10) /**< PRS Src1 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS1MISSRSTEN_SHIFT 10 /**< Shift value for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_MASK 0x400UL /**< Bit mask for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SHIFT 16 /**< Shift value for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_MASK 0xF0000UL /**< Bit mask for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL0 0x00000000UL /**< Mode SEL0 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL8 0x00000008UL /**< Mode SEL8 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL9 0x00000009UL /**< Mode SEL9 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL10 0x0000000AUL /**< Mode SEL10 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL11 0x0000000BUL /**< Mode SEL11 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL12 0x0000000CUL /**< Mode SEL12 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL13 0x0000000DUL /**< Mode SEL13 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL14 0x0000000EUL /**< Mode SEL14 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL15 0x0000000FUL /**< Mode SEL15 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_DEFAULT (_WDOG_CFG_PERSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL0 (_WDOG_CFG_PERSEL_SEL0 << 16) /**< Shifted mode SEL0 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL1 (_WDOG_CFG_PERSEL_SEL1 << 16) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL2 (_WDOG_CFG_PERSEL_SEL2 << 16) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL3 (_WDOG_CFG_PERSEL_SEL3 << 16) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL4 (_WDOG_CFG_PERSEL_SEL4 << 16) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL5 (_WDOG_CFG_PERSEL_SEL5 << 16) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL6 (_WDOG_CFG_PERSEL_SEL6 << 16) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL7 (_WDOG_CFG_PERSEL_SEL7 << 16) /**< Shifted mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL8 (_WDOG_CFG_PERSEL_SEL8 << 16) /**< Shifted mode SEL8 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL9 (_WDOG_CFG_PERSEL_SEL9 << 16) /**< Shifted mode SEL9 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL10 (_WDOG_CFG_PERSEL_SEL10 << 16) /**< Shifted mode SEL10 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL11 (_WDOG_CFG_PERSEL_SEL11 << 16) /**< Shifted mode SEL11 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL12 (_WDOG_CFG_PERSEL_SEL12 << 16) /**< Shifted mode SEL12 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL13 (_WDOG_CFG_PERSEL_SEL13 << 16) /**< Shifted mode SEL13 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL14 (_WDOG_CFG_PERSEL_SEL14 << 16) /**< Shifted mode SEL14 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL15 (_WDOG_CFG_PERSEL_SEL15 << 16) /**< Shifted mode SEL15 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SHIFT 24 /**< Shift value for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_MASK 0x3000000UL /**< Bit mask for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DEFAULT (_WDOG_CFG_WARNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DIS (_WDOG_CFG_WARNSEL_DIS << 24) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL1 (_WDOG_CFG_WARNSEL_SEL1 << 24) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL2 (_WDOG_CFG_WARNSEL_SEL2 << 24) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL3 (_WDOG_CFG_WARNSEL_SEL3 << 24) /**< Shifted mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SHIFT 28 /**< Shift value for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_MASK 0x70000000UL /**< Bit mask for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DEFAULT (_WDOG_CFG_WINSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DIS (_WDOG_CFG_WINSEL_DIS << 28) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL1 (_WDOG_CFG_WINSEL_SEL1 << 28) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL2 (_WDOG_CFG_WINSEL_SEL2 << 28) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL3 (_WDOG_CFG_WINSEL_SEL3 << 28) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL4 (_WDOG_CFG_WINSEL_SEL4 << 28) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL5 (_WDOG_CFG_WINSEL_SEL5 << 28) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL6 (_WDOG_CFG_WINSEL_SEL6 << 28) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL7 (_WDOG_CFG_WINSEL_SEL7 << 28) /**< Shifted mode SEL7 for WDOG_CFG */ /* Bit fields for WDOG CMD */ -#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ -#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ -#define WDOG_CMD_CLEAR (0x1UL << 0) /**< WDOG Timer Clear */ -#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ -#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ -#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ -#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ -#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ -#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ -#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ -#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ +#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ +#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ +#define WDOG_CMD_CLEAR (0x1UL << 0) /**< WDOG Timer Clear */ +#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ +#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ /* Bit fields for WDOG STATUS */ -#define _WDOG_STATUS_RESETVALUE 0x00000000UL /**< Default value for WDOG_STATUS */ -#define _WDOG_STATUS_MASK 0x80000000UL /**< Mask for WDOG_STATUS */ -#define WDOG_STATUS_LOCK (0x1UL << 31) /**< WDOG Configuration Lock Status */ -#define _WDOG_STATUS_LOCK_SHIFT 31 /**< Shift value for WDOG_LOCK */ -#define _WDOG_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for WDOG_LOCK */ -#define _WDOG_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_STATUS */ -#define _WDOG_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WDOG_STATUS */ -#define _WDOG_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for WDOG_STATUS */ -#define WDOG_STATUS_LOCK_DEFAULT (_WDOG_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_STATUS */ -#define WDOG_STATUS_LOCK_UNLOCKED (_WDOG_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for WDOG_STATUS */ -#define WDOG_STATUS_LOCK_LOCKED (_WDOG_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for WDOG_STATUS */ +#define _WDOG_STATUS_RESETVALUE 0x00000000UL /**< Default value for WDOG_STATUS */ +#define _WDOG_STATUS_MASK 0x80000000UL /**< Mask for WDOG_STATUS */ +#define WDOG_STATUS_LOCK (0x1UL << 31) /**< WDOG Configuration Lock Status */ +#define _WDOG_STATUS_LOCK_SHIFT 31 /**< Shift value for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_DEFAULT (_WDOG_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_UNLOCKED (_WDOG_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_LOCKED (_WDOG_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for WDOG_STATUS */ /* Bit fields for WDOG IF */ -#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ -#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ -#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ -#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ -#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ -#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ -#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ -#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ -#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ -#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ -#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ -#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Flag */ -#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ -#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ -#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Flag */ -#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ -#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ -#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ +#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ +#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ +#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ +#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ +#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ /* Bit fields for WDOG IEN */ -#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ -#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ -#define WDOG_IEN_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Enable */ -#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ -#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ -#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Enable */ -#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ -#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ -#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_WIN (0x1UL << 2) /**< WDOG Window Interrupt Enable */ -#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ -#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ -#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Enable */ -#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ -#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ -#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Enable */ -#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ -#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ -#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ +#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ +#define WDOG_IEN_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Enable */ +#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Enable */ +#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN (0x1UL << 2) /**< WDOG Window Interrupt Enable */ +#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ /* Bit fields for WDOG LOCK */ -#define _WDOG_LOCK_RESETVALUE 0x0000ABE8UL /**< Default value for WDOG_LOCK */ -#define _WDOG_LOCK_MASK 0x0000FFFFUL /**< Mask for WDOG_LOCK */ -#define _WDOG_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for WDOG_LOCKKEY */ -#define _WDOG_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for WDOG_LOCKKEY */ -#define _WDOG_LOCK_LOCKKEY_DEFAULT 0x0000ABE8UL /**< Mode DEFAULT for WDOG_LOCK */ -#define _WDOG_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WDOG_LOCK */ -#define _WDOG_LOCK_LOCKKEY_UNLOCK 0x0000ABE8UL /**< Mode UNLOCK for WDOG_LOCK */ -#define WDOG_LOCK_LOCKKEY_DEFAULT (_WDOG_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_LOCK */ -#define WDOG_LOCK_LOCKKEY_LOCK (_WDOG_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WDOG_LOCK */ -#define WDOG_LOCK_LOCKKEY_UNLOCK (_WDOG_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WDOG_LOCK */ +#define _WDOG_LOCK_RESETVALUE 0x0000ABE8UL /**< Default value for WDOG_LOCK */ +#define _WDOG_LOCK_MASK 0x0000FFFFUL /**< Mask for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_DEFAULT 0x0000ABE8UL /**< Mode DEFAULT for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_UNLOCK 0x0000ABE8UL /**< Mode UNLOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_DEFAULT (_WDOG_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_LOCK (_WDOG_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_UNLOCK (_WDOG_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WDOG_LOCK */ /* Bit fields for WDOG SYNCBUSY */ -#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ -#define _WDOG_SYNCBUSY_MASK 0x00000001UL /**< Mask for WDOG_SYNCBUSY */ -#define WDOG_SYNCBUSY_CMD (0x1UL << 0) /**< Sync Busy for Cmd Register */ -#define _WDOG_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for WDOG_CMD */ -#define _WDOG_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for WDOG_CMD */ -#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ -#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_MASK 0x00000001UL /**< Mask for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD (0x1UL << 0) /**< Sync Busy for Cmd Register */ +#define _WDOG_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ /** @} End of group EFR32SG28_WDOG_BitFields */ /** @} End of group EFR32SG28_WDOG */ diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b320f1024im48.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b320f1024im48.h index 22e7e155cd..0ca1d4dd0d 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b320f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b320f1024im48.h @@ -4,7 +4,7 @@ * for EFR32SG28B320F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b320f1024im68.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b320f1024im68.h index c6f307ff91..6ae1a152e1 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b320f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b320f1024im68.h @@ -4,7 +4,7 @@ * for EFR32SG28B320F1024IM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b322f1024im48.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b322f1024im48.h index ce8754a24e..808d25d30e 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b322f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b322f1024im48.h @@ -4,7 +4,7 @@ * for EFR32SG28B322F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b322f1024im68.h b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b322f1024im68.h index a1432910c9..299b39f8ef 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b322f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/efr32sg28b322f1024im68.h @@ -4,7 +4,7 @@ * for EFR32SG28B322F1024IM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/em_device.h b/platform/Device/SiliconLabs/EFR32SG28/Include/em_device.h index b777e1b447..dfba41eecc 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/em_device.h @@ -9,24 +9,26 @@ * @verbatim * Example: Add "-DEFM32G890F128" to your build options, to define part * Add "#include "em_device.h" to your source files + + * * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be @@ -41,10 +43,13 @@ #define EM_DEVICE_H #if defined(EFR32SG28B320F1024IM48) #include "efr32sg28b320f1024im48.h" + #elif defined(EFR32SG28B320F1024IM68) #include "efr32sg28b320f1024im68.h" + #elif defined(EFR32SG28B322F1024IM48) #include "efr32sg28b322f1024im48.h" + #elif defined(EFR32SG28B322F1024IM68) #include "efr32sg28b322f1024im68.h" diff --git a/platform/Device/SiliconLabs/EFR32SG28/Include/system_efr32sg28.h b/platform/Device/SiliconLabs/EFR32SG28/Include/system_efr32sg28.h index 10d8da79a4..7a84636fa4 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Include/system_efr32sg28.h +++ b/platform/Device/SiliconLabs/EFR32SG28/Include/system_efr32sg28.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32SG28 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32SG28/Source/GCC/efr32sg28.ld b/platform/Device/SiliconLabs/EFR32SG28/Source/GCC/efr32sg28.ld index 02705e7aa7..b57c564a08 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Source/GCC/efr32sg28.ld +++ b/platform/Device/SiliconLabs/EFR32SG28/Source/GCC/efr32sg28.ld @@ -6,21 +6,21 @@ * Linker script for Silicon Labs EFR32SG28 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib - * + * * The licensor of this software is Silicon Laboratories Inc. - * + * * This software is provided 'as-is', without any express or implied * warranty. In no event will the authors be held liable for any damages * arising from the use of this software. - * + * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: - * + * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be diff --git a/platform/Device/SiliconLabs/EFR32SG28/Source/IAR/startup_efr32sg28.s b/platform/Device/SiliconLabs/EFR32SG28/Source/IAR/startup_efr32sg28.s index 3dda7c56f1..947e8dffbc 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Source/IAR/startup_efr32sg28.s +++ b/platform/Device/SiliconLabs/EFR32SG28/Source/IAR/startup_efr32sg28.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFR32SG28/Source/system_efr32sg28.c b/platform/Device/SiliconLabs/EFR32SG28/Source/system_efr32sg28.c index 14039e2aa5..c7d0600db4 100644 --- a/platform/Device/SiliconLabs/EFR32SG28/Source/system_efr32sg28.c +++ b/platform/Device/SiliconLabs/EFR32SG28/Source/system_efr32sg28.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32SG28 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_acmp.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_acmp.h index 8dad94de1f..7f086f2a5f 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_acmp.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_aes.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_aes.h index fd7505d14f..b021395e8b 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_aes.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_aes.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_buram.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_buram.h index 6949a9755d..f00f3fb7d9 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_buram.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_buram.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_burtc.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_burtc.h index 71305224ed..7aced0d758 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_burtc.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_cmu.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_cmu.h index 16a1127a84..29da8d3909 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_cmu.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dcdc.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dcdc.h index 558a8a5727..1474de66bb 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_devinfo.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_devinfo.h index 7839297e94..ace729070a 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dma_descriptor.h index d4ce9d92bd..2299a1b495 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dpll.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dpll.h index db51c18dbb..989e39d391 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dpll.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_emu.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_emu.h index ad643e7622..5e79a0a9da 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_emu.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_emu.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_eusart.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_eusart.h index 38b55f6d73..99e864e6ec 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_eusart.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_fsrco.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_fsrco.h index b9cf4f4ae1..3f75bc6d1f 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpcrc.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpcrc.h index ab5e46fd4a..2ac3ceb731 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio.h index bdec28a2d1..0c00a4f85c 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio_port.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio_port.h index bca5a0e51f..55953fb5af 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfrco.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfrco.h index 36187d6e95..e4a8b50552 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfxo.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfxo.h index c2c2fd5561..4296b7baf2 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_i2c.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_i2c.h index d4c2d623b6..f4a3f7a405 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_i2c.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_iadc.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_iadc.h index 09c5820325..a01773122d 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_iadc.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_icache.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_icache.h index 16879af2c0..7ea0e2217c 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_icache.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_icache.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_keyscan.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_keyscan.h index 1e213ffbd4..a1f1565e44 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_keyscan.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcd.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcd.h index efaa873ebf..24a98e3fb3 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcd.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcd.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcdrf.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcdrf.h index 6de46b8280..42aa2d56b8 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcdrf.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcdrf.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldma.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldma.h index 70d962e3e9..8429b232dc 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldma.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar.h index fed4de8ca4..4879ce5d65 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar_defines.h index 7a11159fad..f3b7ab8825 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lesense.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lesense.h index 163803fe3a..c3f55ee2fc 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lesense.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lesense.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_letimer.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_letimer.h index d13112c473..42bd2c5b78 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_letimer.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfrco.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfrco.h index fc67d34bf7..5704c04888 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfxo.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfxo.h index 43cfdb450f..3863dc8854 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mailbox.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mailbox.h index 910a8dbf2b..fee8e70797 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mpahbram.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mpahbram.h index e16b03d2ad..8463a51db1 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_msc.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_msc.h index 3fa41a4cae..3ccd2558eb 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_msc.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_msc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pcnt.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pcnt.h index f585cc472f..8d07270162 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pfmxpprf.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pfmxpprf.h index 34f01660a1..8fb709d56f 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pfmxpprf.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pfmxpprf.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs.h index 226ab3715d..7d5a49a1cd 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs_signals.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs_signals.h index b6132005c0..49d1defa4d 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_scratchpad.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_scratchpad.h index 5b8931d339..065f133209 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_semailbox.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_semailbox.h index 3e0fa8629c..0a05564d11 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_smu.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_smu.h index 3c72e342c8..6a53a14f3f 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_smu.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_smu.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_syscfg.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_syscfg.h index 948d6c7065..e66926f516 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_sysrtc.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_sysrtc.h index 200ccb29e5..fd825b8e46 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_timer.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_timer.h index bcb12fcead..0702011107 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_timer.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_timer.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ulfrco.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ulfrco.h index 6ade65b91c..bdbb677738 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_usart.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_usart.h index 1dbac2c6f8..a5a89f273e 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_usart.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_usart.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_vdac.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_vdac.h index 95b54cf241..65b0b350b2 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_vdac.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_wdog.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_wdog.h index fde664806a..615c8141a0 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_wdog.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32ZG23 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm40.h index 6979cbd7bb..03c932d823 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm40.h @@ -4,7 +4,7 @@ * for EFR32ZG23A010F512GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm48.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm48.h index bff2c065fb..19103378fd 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm48.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm48.h @@ -4,7 +4,7 @@ * for EFR32ZG23A010F512GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm40.h index 30adcf990f..870b760155 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm40.h @@ -4,7 +4,7 @@ * for EFR32ZG23A020F512GM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm48.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm48.h index 0cf52a9d9e..85ddf49d28 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm48.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm48.h @@ -4,7 +4,7 @@ * for EFR32ZG23A020F512GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im40.h index 78ab31eccb..e9b4e48e4a 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im40.h @@ -4,7 +4,7 @@ * for EFR32ZG23B010F512IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im48.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im48.h index fa25e5a9fb..a703e9facd 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im48.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im48.h @@ -4,7 +4,7 @@ * for EFR32ZG23B010F512IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b011f512im40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b011f512im40.h index c1fa8c101f..01effe4688 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b011f512im40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b011f512im40.h @@ -4,7 +4,7 @@ * for EFR32ZG23B011F512IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im40.h index 15fc37732e..a9cc96357a 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im40.h @@ -4,7 +4,7 @@ * for EFR32ZG23B020F512IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im48.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im48.h index 5d83f97eaf..c5a2f5fa63 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im48.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im48.h @@ -4,7 +4,7 @@ * for EFR32ZG23B020F512IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b021f512im40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b021f512im40.h index f1a35467f9..dcca1e3493 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b021f512im40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b021f512im40.h @@ -4,7 +4,7 @@ * for EFR32ZG23B021F512IM40 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/em_device.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/em_device.h index cf008a0395..5d395cdd83 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/system_efr32zg23.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/system_efr32zg23.h index bb722eceff..f7c2695351 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/system_efr32zg23.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/system_efr32zg23.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32ZG23 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Source/GCC/efr32zg23.ld b/platform/Device/SiliconLabs/EFR32ZG23/Source/GCC/efr32zg23.ld index ec8c3fa36a..b2e21dc002 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Source/GCC/efr32zg23.ld +++ b/platform/Device/SiliconLabs/EFR32ZG23/Source/GCC/efr32zg23.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs EFR32ZG23 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Source/IAR/startup_efr32zg23.s b/platform/Device/SiliconLabs/EFR32ZG23/Source/IAR/startup_efr32zg23.s index f9da709b0f..931ff6e71e 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Source/IAR/startup_efr32zg23.s +++ b/platform/Device/SiliconLabs/EFR32ZG23/Source/IAR/startup_efr32zg23.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Source/system_efr32zg23.c b/platform/Device/SiliconLabs/EFR32ZG23/Source/system_efr32zg23.c index 93adf74e25..8458e75096 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Source/system_efr32zg23.c +++ b/platform/Device/SiliconLabs/EFR32ZG23/Source/system_efr32zg23.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32ZG23 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_acmp.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_acmp.h index 998d03ec20..45f0a072ea 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_acmp.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_acmp.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_aes.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_aes.h index 23c963a4cc..ec213d0db0 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_aes.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_aes.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_buram.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_buram.h index 04df122b57..fdda57eb19 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_buram.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_buram.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_burtc.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_burtc.h index 537b6e0929..bd0e50ab59 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_burtc.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_burtc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_cmu.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_cmu.h index 0ddc7178ff..3844098b45 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_cmu.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_cmu.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dcdc.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dcdc.h index e1d3c66bcd..16fc3afd0a 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dcdc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_devinfo.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_devinfo.h index 07706fddf1..11db64a439 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_devinfo.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dma_descriptor.h index 0004d0e74b..d9ab86395f 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dpll.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dpll.h index b79add5039..a851c93905 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dpll.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_dpll.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_emu.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_emu.h index 47d13ef736..16afa761a1 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_emu.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_emu.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_eusart.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_eusart.h index 7d469e7548..19b3242ed2 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_eusart.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_eusart.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_fsrco.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_fsrco.h index 7ebd6dfcb2..69d6ead253 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_fsrco.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_fsrco.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpcrc.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpcrc.h index c2d62fc8ca..720f8b827d 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpcrc.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpcrc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpio.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpio.h index 69ef62aa32..9f292293d4 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpio.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpio.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpio_port.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpio_port.h index 4e9fb8de36..910759595f 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpio_port.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_gpio_port.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_hfrco.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_hfrco.h index 0e379b3a27..c483f32ab6 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_hfrco.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_hfrco.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_hfxo.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_hfxo.h index ec7e97c5b3..87c8259597 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_hfxo.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_hfxo.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_i2c.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_i2c.h index a0d755e506..b3b2f670b6 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_i2c.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_i2c.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_iadc.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_iadc.h index c16aa9e27c..725bb67cf8 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_iadc.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_iadc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_icache.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_icache.h index a1cf90ee2e..180052402e 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_icache.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_icache.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_keyscan.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_keyscan.h index 97ef43533a..139f24c29f 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_keyscan.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_keyscan.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lcd.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lcd.h index c5a78b3f52..4394d10cf0 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lcd.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lcd.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lcdrf.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lcdrf.h index dddfefe3e6..90083783a4 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lcdrf.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lcdrf.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldma.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldma.h index a07306d722..3f37daf122 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldma.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldma.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldmaxbar.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldmaxbar.h index 359eb0ca35..0d27ec6225 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldmaxbar.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldmaxbar_defines.h index 108a8bbc9a..059e47ac0a 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lesense.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lesense.h index b1ac6c9640..6e1eb70196 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lesense.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lesense.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_letimer.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_letimer.h index 6e7667d216..d8ff22b7a9 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_letimer.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_letimer.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lfrco.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lfrco.h index 742856f979..6e15b9cad1 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lfrco.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lfrco.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lfxo.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lfxo.h index 12bf0847ff..3459f8438d 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lfxo.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_lfxo.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mailbox.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mailbox.h index 63631d30c3..7f646b0b36 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mailbox.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mailbox.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mpahbram.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mpahbram.h index f4f2299c90..4a2cfa0057 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mpahbram.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mpahbram.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_msc.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_msc.h index a63275810a..15be34c68e 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_msc.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_msc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mvp.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mvp.h index c7677ad5e1..48d57f64a1 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mvp.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_mvp.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_pcnt.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_pcnt.h index edd7c0ad76..14052e14ff 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_pcnt.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_pcnt.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_pfmxpprf.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_pfmxpprf.h index 73dbd81bdb..9e31fc386c 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_pfmxpprf.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_pfmxpprf.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_prs.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_prs.h index 24593aa105..52607d9bc2 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_prs.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_prs.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_prs_signals.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_prs_signals.h index fe2f0b53fb..3161445175 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_prs_signals.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_scratchpad.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_scratchpad.h index 5de0aa2e75..9620688fb9 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_scratchpad.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_scratchpad.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_semailbox.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_semailbox.h index 75dbed8cd7..d0416d3e4a 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_semailbox.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_semailbox.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_smu.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_smu.h index 1b067cf745..517758d636 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_smu.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_smu.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_syscfg.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_syscfg.h index 23f5a151d8..98feeec167 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_syscfg.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_syscfg.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_sysrtc.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_sysrtc.h index a646257031..52970c1af1 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_sysrtc.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_sysrtc.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_timer.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_timer.h index 96c1474f54..c7b530fd5a 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_timer.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_timer.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ulfrco.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ulfrco.h index 17a09bbcab..c80fc06911 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ulfrco.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_ulfrco.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_usart.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_usart.h index ebf37c6393..e845c71317 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_usart.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_usart.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_vdac.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_vdac.h index b0bb56b1ae..efbe42171c 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_vdac.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_vdac.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_wdog.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_wdog.h index e2f682472b..019a46fb48 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_wdog.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28_wdog.h @@ -3,7 +3,7 @@ * @brief EFR32ZG28 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a110f1024gm48.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a110f1024gm48.h index b76641588f..0941412f54 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a110f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a110f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32ZG28A110F1024GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a110f1024gm68.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a110f1024gm68.h index 2df5f35bbc..bfe6901c75 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a110f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a110f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32ZG28A110F1024GM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a112f1024gm48.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a112f1024gm48.h index 3be9d687aa..5c1ff04c54 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a112f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a112f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32ZG28A112F1024GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a112f1024gm68.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a112f1024gm68.h index 3edf2d679f..deab08b8a2 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a112f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a112f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32ZG28A112F1024GM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a120f1024gm48.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a120f1024gm48.h index 8486bbe07e..85f99b62a9 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a120f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a120f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32ZG28A120F1024GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a120f1024gm68.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a120f1024gm68.h index 7f48968df4..9226e8e7e7 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a120f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a120f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32ZG28A120F1024GM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a122f1024gm48.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a122f1024gm48.h index fea4f5e3cd..fb13a72f9a 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a122f1024gm48.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a122f1024gm48.h @@ -4,7 +4,7 @@ * for EFR32ZG28A122F1024GM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a122f1024gm68.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a122f1024gm68.h index ea9ba0c4ee..26b1947dcd 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a122f1024gm68.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28a122f1024gm68.h @@ -4,7 +4,7 @@ * for EFR32ZG28A122F1024GM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b310f1024im48.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b310f1024im48.h index 1d6d02b274..0eec357183 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b310f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b310f1024im48.h @@ -4,7 +4,7 @@ * for EFR32ZG28B310F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b310f1024im68.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b310f1024im68.h index 24f2aaaa31..51ae5437e0 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b310f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b310f1024im68.h @@ -4,7 +4,7 @@ * for EFR32ZG28B310F1024IM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b312f1024im48.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b312f1024im48.h index ca0e373044..910728b8f7 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b312f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b312f1024im48.h @@ -4,7 +4,7 @@ * for EFR32ZG28B312F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b312f1024im68.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b312f1024im68.h index 5740c39d35..a73cab9ce2 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b312f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b312f1024im68.h @@ -4,7 +4,7 @@ * for EFR32ZG28B312F1024IM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b320f1024im48.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b320f1024im48.h index 13e294f550..a034c01446 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b320f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b320f1024im48.h @@ -4,7 +4,7 @@ * for EFR32ZG28B320F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b320f1024im68.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b320f1024im68.h index e6fed61a8c..c375600d1b 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b320f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b320f1024im68.h @@ -4,7 +4,7 @@ * for EFR32ZG28B320F1024IM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b322f1024im48.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b322f1024im48.h index c4c17f292d..cef5c0fd14 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b322f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b322f1024im48.h @@ -4,7 +4,7 @@ * for EFR32ZG28B322F1024IM48 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b322f1024im68.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b322f1024im68.h index 55ba16e6fc..46e79652d3 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b322f1024im68.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/efr32zg28b322f1024im68.h @@ -4,7 +4,7 @@ * for EFR32ZG28B322F1024IM68 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/em_device.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/em_device.h index c2de63b7ae..3811914940 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Include/system_efr32zg28.h b/platform/Device/SiliconLabs/EFR32ZG28/Include/system_efr32zg28.h index ba6b2b0f2f..2d3806f7d4 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Include/system_efr32zg28.h +++ b/platform/Device/SiliconLabs/EFR32ZG28/Include/system_efr32zg28.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for EFR32ZG28 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Source/GCC/efr32zg28.ld b/platform/Device/SiliconLabs/EFR32ZG28/Source/GCC/efr32zg28.ld index 6557598a81..2a42e26dda 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Source/GCC/efr32zg28.ld +++ b/platform/Device/SiliconLabs/EFR32ZG28/Source/GCC/efr32zg28.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs EFR32ZG28 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Source/IAR/startup_efr32zg28.s b/platform/Device/SiliconLabs/EFR32ZG28/Source/IAR/startup_efr32zg28.s index 7e2b9590d0..1617a04d96 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Source/IAR/startup_efr32zg28.s +++ b/platform/Device/SiliconLabs/EFR32ZG28/Source/IAR/startup_efr32zg28.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/EFR32ZG28/Source/system_efr32zg28.c b/platform/Device/SiliconLabs/EFR32ZG28/Source/system_efr32zg28.c index aef37eda1c..fdbba5a352 100644 --- a/platform/Device/SiliconLabs/EFR32ZG28/Source/system_efr32zg28.c +++ b/platform/Device/SiliconLabs/EFR32ZG28/Source/system_efr32zg28.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for EFR32ZG28 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/em_device.h b/platform/Device/SiliconLabs/FGM23/Include/em_device.h index c9ed64176e..969b0b93e0 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/em_device.h +++ b/platform/Device/SiliconLabs/FGM23/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm230sa27hgn.h b/platform/Device/SiliconLabs/FGM23/Include/fgm230sa27hgn.h index ff3480ba1a..9fad6be046 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm230sa27hgn.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm230sa27hgn.h @@ -4,7 +4,7 @@ * for FGM230SA27HGN ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm230sb27hgn.h b/platform/Device/SiliconLabs/FGM23/Include/fgm230sb27hgn.h index b05ea5ef0c..7ec7215c40 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm230sb27hgn.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm230sb27hgn.h @@ -4,7 +4,7 @@ * for FGM230SB27HGN ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_acmp.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_acmp.h index 3ad851d654..471a5efc26 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_acmp.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_acmp.h @@ -3,7 +3,7 @@ * @brief FGM23 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_aes.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_aes.h index 7b57af4082..70bb674531 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_aes.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_aes.h @@ -3,7 +3,7 @@ * @brief FGM23 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_buram.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_buram.h index ff44995fbe..1d445dd808 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_buram.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_buram.h @@ -3,7 +3,7 @@ * @brief FGM23 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_burtc.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_burtc.h index 58aeefe75b..2c5b9cca35 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_burtc.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_burtc.h @@ -3,7 +3,7 @@ * @brief FGM23 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_cmu.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_cmu.h index c2381a121e..1c88ce92ed 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_cmu.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_cmu.h @@ -3,7 +3,7 @@ * @brief FGM23 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_dcdc.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_dcdc.h index 8c336c0ce9..b99d718ee2 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_dcdc.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_dcdc.h @@ -3,7 +3,7 @@ * @brief FGM23 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_devinfo.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_devinfo.h index 3a6ee61695..1e4cdea70b 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_devinfo.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_devinfo.h @@ -3,7 +3,7 @@ * @brief FGM23 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_dma_descriptor.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_dma_descriptor.h index 8664828113..df2767ca03 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_dma_descriptor.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief FGM23 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_dpll.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_dpll.h index d3711a6d90..f5a0b6c5b6 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_dpll.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_dpll.h @@ -3,7 +3,7 @@ * @brief FGM23 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_emu.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_emu.h index 40848f0f73..518da7be95 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_emu.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_emu.h @@ -3,7 +3,7 @@ * @brief FGM23 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_eusart.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_eusart.h index 4a81dd47e1..e1fae52332 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_eusart.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_eusart.h @@ -3,7 +3,7 @@ * @brief FGM23 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_fsrco.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_fsrco.h index 404341c704..6967f902b1 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_fsrco.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_fsrco.h @@ -3,7 +3,7 @@ * @brief FGM23 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpcrc.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpcrc.h index c971feef2d..ebe6e66dbd 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpcrc.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpcrc.h @@ -3,7 +3,7 @@ * @brief FGM23 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpio.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpio.h index 72ead0163f..edfe20c995 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpio.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpio.h @@ -3,7 +3,7 @@ * @brief FGM23 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpio_port.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpio_port.h index 3c9c69796d..e59abe16ef 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpio_port.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_gpio_port.h @@ -3,7 +3,7 @@ * @brief FGM23 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_hfrco.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_hfrco.h index 3387bf82f0..817eb7fd4d 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_hfrco.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_hfrco.h @@ -3,7 +3,7 @@ * @brief FGM23 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_hfxo.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_hfxo.h index e6a11cec8a..90a30cac92 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_hfxo.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_hfxo.h @@ -3,7 +3,7 @@ * @brief FGM23 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_i2c.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_i2c.h index 98a932451c..d6df107c12 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_i2c.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_i2c.h @@ -3,7 +3,7 @@ * @brief FGM23 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_iadc.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_iadc.h index ccced49648..0c22d953ac 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_iadc.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_iadc.h @@ -3,7 +3,7 @@ * @brief FGM23 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_icache.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_icache.h index af84d2625e..0642751f7b 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_icache.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_icache.h @@ -3,7 +3,7 @@ * @brief FGM23 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_keyscan.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_keyscan.h index ffa1a09662..2d4869503f 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_keyscan.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_keyscan.h @@ -3,7 +3,7 @@ * @brief FGM23 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lcd.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lcd.h index 88f1e1c715..573598d437 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lcd.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lcd.h @@ -3,7 +3,7 @@ * @brief FGM23 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lcdrf.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lcdrf.h index 800b278f05..4f0b55807f 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lcdrf.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lcdrf.h @@ -3,7 +3,7 @@ * @brief FGM23 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldma.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldma.h index 5e21bd8c99..31177e15e4 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldma.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldma.h @@ -3,7 +3,7 @@ * @brief FGM23 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar.h index 528eb2f8a8..3e9c72f0be 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief FGM23 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar_defines.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar_defines.h index 77d5220639..bdc3e41112 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief FGM23 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lesense.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lesense.h index 75a6cc0957..92703e64ea 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lesense.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lesense.h @@ -3,7 +3,7 @@ * @brief FGM23 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_letimer.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_letimer.h index ac879c8642..226969ea25 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_letimer.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_letimer.h @@ -3,7 +3,7 @@ * @brief FGM23 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lfrco.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lfrco.h index 2a6814f306..f44066b317 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lfrco.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lfrco.h @@ -3,7 +3,7 @@ * @brief FGM23 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lfxo.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lfxo.h index e354df7809..fcc5f78d0d 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_lfxo.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_lfxo.h @@ -3,7 +3,7 @@ * @brief FGM23 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_mailbox.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_mailbox.h index df1b768b2b..4001ca489f 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_mailbox.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_mailbox.h @@ -3,7 +3,7 @@ * @brief FGM23 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_mpahbram.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_mpahbram.h index a177309b2c..80b58a9ced 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_mpahbram.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_mpahbram.h @@ -3,7 +3,7 @@ * @brief FGM23 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_msc.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_msc.h index 00f1c02af6..e7f9bb652a 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_msc.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_msc.h @@ -3,7 +3,7 @@ * @brief FGM23 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_pcnt.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_pcnt.h index 50b4ca1218..ac388a5520 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_pcnt.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_pcnt.h @@ -3,7 +3,7 @@ * @brief FGM23 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_pfmxpprf.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_pfmxpprf.h index 144b5d873f..cdd62686d8 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_pfmxpprf.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_pfmxpprf.h @@ -3,7 +3,7 @@ * @brief FGM23 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs.h index 67371d0e01..44dffc6b42 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs.h @@ -3,7 +3,7 @@ * @brief FGM23 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs_signals.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs_signals.h index 14c7047224..feb1c9e4f7 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs_signals.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs_signals.h @@ -3,7 +3,7 @@ * @brief FGM23 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_scratchpad.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_scratchpad.h index 79d95ab9a1..0b8dcc800f 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_scratchpad.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_scratchpad.h @@ -3,7 +3,7 @@ * @brief FGM23 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_semailbox.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_semailbox.h index 593c17cf6b..cc5318b94e 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_semailbox.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_semailbox.h @@ -3,7 +3,7 @@ * @brief FGM23 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_smu.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_smu.h index ec33fcb545..4ae34e0a9d 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_smu.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_smu.h @@ -3,7 +3,7 @@ * @brief FGM23 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_syscfg.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_syscfg.h index 97e0cdda5d..d26f79aa73 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_syscfg.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_syscfg.h @@ -3,7 +3,7 @@ * @brief FGM23 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_sysrtc.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_sysrtc.h index acd226f746..d3a264f85b 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_sysrtc.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_sysrtc.h @@ -3,7 +3,7 @@ * @brief FGM23 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_timer.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_timer.h index b5406bfba0..eea3abeada 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_timer.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_timer.h @@ -3,7 +3,7 @@ * @brief FGM23 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ulfrco.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ulfrco.h index ab42e5376f..ede7d94779 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ulfrco.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ulfrco.h @@ -3,7 +3,7 @@ * @brief FGM23 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_usart.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_usart.h index 6cc4f176b4..0da61fc6c5 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_usart.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_usart.h @@ -3,7 +3,7 @@ * @brief FGM23 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_vdac.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_vdac.h index f88e3edbf7..24d780f61e 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_vdac.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_vdac.h @@ -3,7 +3,7 @@ * @brief FGM23 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_wdog.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_wdog.h index 3e1e08a0ad..d67c66cf94 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_wdog.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_wdog.h @@ -3,7 +3,7 @@ * @brief FGM23 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Include/system_fgm23.h b/platform/Device/SiliconLabs/FGM23/Include/system_fgm23.h index 0283983737..a59bdf1cd2 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/system_fgm23.h +++ b/platform/Device/SiliconLabs/FGM23/Include/system_fgm23.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for FGM23 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Source/GCC/fgm23.ld b/platform/Device/SiliconLabs/FGM23/Source/GCC/fgm23.ld index c46343fa21..adc7193b65 100644 --- a/platform/Device/SiliconLabs/FGM23/Source/GCC/fgm23.ld +++ b/platform/Device/SiliconLabs/FGM23/Source/GCC/fgm23.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs FGM23 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/FGM23/Source/IAR/startup_fgm23.s b/platform/Device/SiliconLabs/FGM23/Source/IAR/startup_fgm23.s index d0fb4ffabc..2a72398c33 100644 --- a/platform/Device/SiliconLabs/FGM23/Source/IAR/startup_fgm23.s +++ b/platform/Device/SiliconLabs/FGM23/Source/IAR/startup_fgm23.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/FGM23/Source/system_fgm23.c b/platform/Device/SiliconLabs/FGM23/Source/system_fgm23.c index f4c55a20b1..715f4999fb 100644 --- a/platform/Device/SiliconLabs/FGM23/Source/system_fgm23.c +++ b/platform/Device/SiliconLabs/FGM23/Source/system_fgm23.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for FGM23 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/em_device.h b/platform/Device/SiliconLabs/MGM21/Include/em_device.h index 6cebe6372c..d7f57be7a8 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/em_device.h +++ b/platform/Device/SiliconLabs/MGM21/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jif.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jif.h index efa32340e5..8eb2dc6143 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jif.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jif.h @@ -4,7 +4,7 @@ * for MGM210L022JIF ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jnf.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jnf.h index 36a0dd2a74..880c0baf66 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jnf.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jnf.h @@ -4,7 +4,7 @@ * for MGM210L022JNF ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jif.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jif.h index 3ddc73fbe2..ce8b5e67a7 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jif.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jif.h @@ -4,7 +4,7 @@ * for MGM210LA22JIF ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jnf.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jnf.h index c698a761de..bb06435506 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jnf.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jnf.h @@ -4,7 +4,7 @@ * for MGM210LA22JNF ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210p022jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210p022jia.h index 4f063acc3f..0349df70d5 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210p022jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210p022jia.h @@ -4,7 +4,7 @@ * for MGM210P022JIA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210p032jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210p032jia.h index 10850b79ef..d7ddcae8d7 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210p032jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210p032jia.h @@ -4,7 +4,7 @@ * for MGM210P032JIA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210pa22jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210pa22jia.h index 557f76a980..dbcc0a06c2 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210pa22jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210pa22jia.h @@ -4,7 +4,7 @@ * for MGM210PA22JIA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210pa32jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210pa32jia.h index 3be01161bf..23b8e84d61 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210pa32jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210pa32jia.h @@ -4,7 +4,7 @@ * for MGM210PA32JIA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210pb22jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210pb22jia.h index 85116164f2..d515dff745 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210pb22jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210pb22jia.h @@ -4,7 +4,7 @@ * for MGM210PB22JIA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210pb32jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210pb32jia.h index 43d67566d7..b1d28badfe 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210pb32jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210pb32jia.h @@ -4,7 +4,7 @@ * for MGM210PB32JIA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm211la02jnf.h b/platform/Device/SiliconLabs/MGM21/Include/mgm211la02jnf.h index 89be18dd56..617960fcc0 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm211la02jnf.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm211la02jnf.h @@ -4,7 +4,7 @@ * for MGM211LA02JNF ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_acmp.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_acmp.h index c558da6d19..e20fe729a6 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_acmp.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_acmp.h @@ -3,7 +3,7 @@ * @brief MGM21 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_aes.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_aes.h index 46c0615e32..4b7e55f66a 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_aes.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_aes.h @@ -3,7 +3,7 @@ * @brief MGM21 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_bufc.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_bufc.h index 059b39f2e6..ca220229a2 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_bufc.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_bufc.h @@ -3,7 +3,7 @@ * @brief MGM21 BUFC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_buram.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_buram.h index dbd4688d79..026ca582f7 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_buram.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_buram.h @@ -3,7 +3,7 @@ * @brief MGM21 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_burtc.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_burtc.h index 5fa01fefe3..a86a45f9d2 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_burtc.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_burtc.h @@ -3,7 +3,7 @@ * @brief MGM21 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_cmu.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_cmu.h index 3f803d2d24..cd8374f9cf 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_cmu.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_cmu.h @@ -3,7 +3,7 @@ * @brief MGM21 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_devinfo.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_devinfo.h index 6b07a31a2a..0316eba3d2 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_devinfo.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_devinfo.h @@ -3,7 +3,7 @@ * @brief MGM21 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_dma_descriptor.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_dma_descriptor.h index 4e2d7f03c3..1af7413d37 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_dma_descriptor.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief MGM21 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_dpll.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_dpll.h index 5e394ac026..adf6af57e8 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_dpll.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_dpll.h @@ -3,7 +3,7 @@ * @brief MGM21 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_emu.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_emu.h index 08a37efcd0..c470918224 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_emu.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_emu.h @@ -3,7 +3,7 @@ * @brief MGM21 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_fsrco.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_fsrco.h index 7415237ae7..41317c782f 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_fsrco.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_fsrco.h @@ -3,7 +3,7 @@ * @brief MGM21 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpcrc.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpcrc.h index 96b614d370..d05545bb91 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpcrc.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpcrc.h @@ -3,7 +3,7 @@ * @brief MGM21 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpio.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpio.h index 2f3c1d4720..224b42b898 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpio.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpio.h @@ -3,7 +3,7 @@ * @brief MGM21 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpio_port.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpio_port.h index 5ff20bf2d2..dc8c51e5f5 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpio_port.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_gpio_port.h @@ -3,7 +3,7 @@ * @brief MGM21 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_hfrco.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_hfrco.h index 3df6e47c69..dcc78955ed 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_hfrco.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_hfrco.h @@ -3,7 +3,7 @@ * @brief MGM21 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_hfxo.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_hfxo.h index 130ffd6224..c00bf79b32 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_hfxo.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_hfxo.h @@ -3,7 +3,7 @@ * @brief MGM21 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_i2c.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_i2c.h index deebaa5856..30a093bab7 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_i2c.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_i2c.h @@ -3,7 +3,7 @@ * @brief MGM21 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_iadc.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_iadc.h index 172143fb27..84e815f94c 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_iadc.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_iadc.h @@ -3,7 +3,7 @@ * @brief MGM21 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_icache.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_icache.h index 48562663a3..f24d59abc8 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_icache.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_icache.h @@ -3,7 +3,7 @@ * @brief MGM21 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldma.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldma.h index 89fcf9bff0..62b73b5e3c 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldma.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldma.h @@ -3,7 +3,7 @@ * @brief MGM21 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar.h index 65c2199f09..d4ce3a2438 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief MGM21 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar_defines.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar_defines.h index 582309e8a1..656120fdde 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief MGM21 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_letimer.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_letimer.h index c923cb5b84..6fcc84e5ce 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_letimer.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_letimer.h @@ -3,7 +3,7 @@ * @brief MGM21 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_lfrco.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_lfrco.h index bf1f80aebb..a905826c64 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_lfrco.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_lfrco.h @@ -3,7 +3,7 @@ * @brief MGM21 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_lfxo.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_lfxo.h index 7f08a0f553..da03df02c8 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_lfxo.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_lfxo.h @@ -3,7 +3,7 @@ * @brief MGM21 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_lvgd.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_lvgd.h index 12e109071f..41ea0749ad 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_lvgd.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_lvgd.h @@ -3,7 +3,7 @@ * @brief MGM21 LVGD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_msc.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_msc.h index 15e6fd63d0..9e7e1b8bfc 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_msc.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_msc.h @@ -3,7 +3,7 @@ * @brief MGM21 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs.h index e4fd80e537..c3bb2ebf30 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs.h @@ -3,7 +3,7 @@ * @brief MGM21 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs_signals.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs_signals.h index bb36ee3418..bb9ab3cc0d 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs_signals.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs_signals.h @@ -3,7 +3,7 @@ * @brief MGM21 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_rtcc.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_rtcc.h index 6aa812aeaf..6949057150 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_rtcc.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_rtcc.h @@ -3,7 +3,7 @@ * @brief MGM21 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_semailbox.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_semailbox.h index b7202babf6..ff02b13da8 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_semailbox.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_semailbox.h @@ -3,7 +3,7 @@ * @brief MGM21 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_smu.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_smu.h index b0ff900c42..fce3b33299 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_smu.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_smu.h @@ -3,7 +3,7 @@ * @brief MGM21 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_syscfg.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_syscfg.h index fed13fc2dd..28ec42edd8 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_syscfg.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_syscfg.h @@ -3,7 +3,7 @@ * @brief MGM21 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_timer.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_timer.h index 12a8cff4b5..0f01e9d4a8 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_timer.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_timer.h @@ -3,7 +3,7 @@ * @brief MGM21 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ulfrco.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ulfrco.h index e690071fc0..b4cb404910 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ulfrco.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ulfrco.h @@ -3,7 +3,7 @@ * @brief MGM21 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_usart.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_usart.h index 65d9b39a52..4859e03ff4 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_usart.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_usart.h @@ -3,7 +3,7 @@ * @brief MGM21 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_wdog.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_wdog.h index ac7c7c40f4..839b36d10b 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_wdog.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_wdog.h @@ -3,7 +3,7 @@ * @brief MGM21 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Include/system_mgm21.h b/platform/Device/SiliconLabs/MGM21/Include/system_mgm21.h index 86f12ee81c..3f7e778b62 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/system_mgm21.h +++ b/platform/Device/SiliconLabs/MGM21/Include/system_mgm21.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for MGM21 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Source/GCC/mgm21.ld b/platform/Device/SiliconLabs/MGM21/Source/GCC/mgm21.ld index 8e5fbee0c9..5b01af72dd 100644 --- a/platform/Device/SiliconLabs/MGM21/Source/GCC/mgm21.ld +++ b/platform/Device/SiliconLabs/MGM21/Source/GCC/mgm21.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs MGM21 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM21/Source/IAR/startup_mgm21.s b/platform/Device/SiliconLabs/MGM21/Source/IAR/startup_mgm21.s index be0fed87e5..9670bafd92 100644 --- a/platform/Device/SiliconLabs/MGM21/Source/IAR/startup_mgm21.s +++ b/platform/Device/SiliconLabs/MGM21/Source/IAR/startup_mgm21.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/MGM21/Source/system_mgm21.c b/platform/Device/SiliconLabs/MGM21/Source/system_mgm21.c index 5fea164ecf..a4dc1654d6 100644 --- a/platform/Device/SiliconLabs/MGM21/Source/system_mgm21.c +++ b/platform/Device/SiliconLabs/MGM21/Source/system_mgm21.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for MGM21 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/em_device.h b/platform/Device/SiliconLabs/MGM22/Include/em_device.h index cf2b95ce80..650ec467ee 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/em_device.h +++ b/platform/Device/SiliconLabs/MGM22/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm220pc22hna.h b/platform/Device/SiliconLabs/MGM22/Include/mgm220pc22hna.h index 2c8cd93212..b1003042f6 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm220pc22hna.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm220pc22hna.h @@ -4,7 +4,7 @@ * for MGM220PC22HNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_aes.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_aes.h index 40d69453e0..cc8f9fa5b6 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_aes.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_aes.h @@ -3,7 +3,7 @@ * @brief MGM22 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_buram.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_buram.h index f43b51b56f..383546b257 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_buram.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_buram.h @@ -3,7 +3,7 @@ * @brief MGM22 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_burtc.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_burtc.h index 86d490c963..57a1a7ba74 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_burtc.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_burtc.h @@ -3,7 +3,7 @@ * @brief MGM22 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_cmu.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_cmu.h index d9869f6bc0..28a843508a 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_cmu.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_cmu.h @@ -3,7 +3,7 @@ * @brief MGM22 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_cryptoacc.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_cryptoacc.h index 9d3c847a2a..47ed8a2fbd 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_cryptoacc.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_cryptoacc.h @@ -3,7 +3,7 @@ * @brief MGM22 CRYPTOACC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_dcdc.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_dcdc.h index 1a9c333a81..194835a663 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_dcdc.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_dcdc.h @@ -3,7 +3,7 @@ * @brief MGM22 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_devinfo.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_devinfo.h index d9a01b3ad9..6bbd1bb0fc 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_devinfo.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_devinfo.h @@ -3,7 +3,7 @@ * @brief MGM22 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_dma_descriptor.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_dma_descriptor.h index bfc39944fb..8d92d67816 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief MGM22 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_dpll.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_dpll.h index 29a1251398..4a2c6f39cd 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_dpll.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_dpll.h @@ -3,7 +3,7 @@ * @brief MGM22 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_emu.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_emu.h index b87de3efeb..c8038588b4 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_emu.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_emu.h @@ -3,7 +3,7 @@ * @brief MGM22 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_eusart.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_eusart.h index ea7f12bb4d..2e633aaca7 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_eusart.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_eusart.h @@ -3,7 +3,7 @@ * @brief MGM22 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_fsrco.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_fsrco.h index 3cb16956fa..0bdb3c1659 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_fsrco.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_fsrco.h @@ -3,7 +3,7 @@ * @brief MGM22 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpcrc.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpcrc.h index 46e848c4d5..edf8ffe121 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpcrc.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpcrc.h @@ -3,7 +3,7 @@ * @brief MGM22 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpio.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpio.h index f2dc4c6116..3cb5f7bfbc 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpio.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpio.h @@ -3,7 +3,7 @@ * @brief MGM22 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpio_port.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpio_port.h index de4ce9235a..822fb2487a 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpio_port.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_gpio_port.h @@ -3,7 +3,7 @@ * @brief MGM22 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_hfrco.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_hfrco.h index 4874cbdc78..0708770871 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_hfrco.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_hfrco.h @@ -3,7 +3,7 @@ * @brief MGM22 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_hfxo.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_hfxo.h index b48c205298..8b57758c1c 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_hfxo.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_hfxo.h @@ -3,7 +3,7 @@ * @brief MGM22 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_i2c.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_i2c.h index f9d313e94c..239017c314 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_i2c.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_i2c.h @@ -3,7 +3,7 @@ * @brief MGM22 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_iadc.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_iadc.h index 6b92678384..c475330c9a 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_iadc.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_iadc.h @@ -3,7 +3,7 @@ * @brief MGM22 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_icache.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_icache.h index d9ad7b8aff..d10c256021 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_icache.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_icache.h @@ -3,7 +3,7 @@ * @brief MGM22 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldma.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldma.h index 6df67e22a9..ed61555332 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldma.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldma.h @@ -3,7 +3,7 @@ * @brief MGM22 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar.h index f42b558f4e..0e7206b0ca 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief MGM22 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar_defines.h index 8ef36a29ab..835b615332 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief MGM22 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_letimer.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_letimer.h index b43d2f1d1b..cede2648cf 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_letimer.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_letimer.h @@ -3,7 +3,7 @@ * @brief MGM22 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_lfrco.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_lfrco.h index c124b6308f..105239f4af 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_lfrco.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_lfrco.h @@ -3,7 +3,7 @@ * @brief MGM22 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_lfxo.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_lfxo.h index 86f37b17a2..35083b15e7 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_lfxo.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_lfxo.h @@ -3,7 +3,7 @@ * @brief MGM22 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_msc.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_msc.h index 3f9803deaf..7ffafcb050 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_msc.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_msc.h @@ -3,7 +3,7 @@ * @brief MGM22 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_pdm.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_pdm.h index b5a344dd52..6c6c9d6f90 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_pdm.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_pdm.h @@ -3,7 +3,7 @@ * @brief MGM22 PDM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs.h index 613b9973f9..7ae3edd3c3 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs.h @@ -3,7 +3,7 @@ * @brief MGM22 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs_signals.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs_signals.h index 1dcc6f34db..fe42f552a0 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs_signals.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs_signals.h @@ -3,7 +3,7 @@ * @brief MGM22 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_rtcc.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_rtcc.h index 2ede942d23..bf4dea0c99 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_rtcc.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_rtcc.h @@ -3,7 +3,7 @@ * @brief MGM22 RTCC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_smu.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_smu.h index c6203d53ed..bd15e156af 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_smu.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_smu.h @@ -3,7 +3,7 @@ * @brief MGM22 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_syscfg.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_syscfg.h index 4a771cd41d..ba810b2425 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_syscfg.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_syscfg.h @@ -3,7 +3,7 @@ * @brief MGM22 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_timer.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_timer.h index 9049077068..58c9bb17cf 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_timer.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_timer.h @@ -3,7 +3,7 @@ * @brief MGM22 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ulfrco.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ulfrco.h index 4510cf2141..72f02c5cc8 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ulfrco.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ulfrco.h @@ -3,7 +3,7 @@ * @brief MGM22 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_usart.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_usart.h index b952632679..402440c2b9 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_usart.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_usart.h @@ -3,7 +3,7 @@ * @brief MGM22 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_wdog.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_wdog.h index fbd1b57f4b..0fff1b2136 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_wdog.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_wdog.h @@ -3,7 +3,7 @@ * @brief MGM22 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Include/system_mgm22.h b/platform/Device/SiliconLabs/MGM22/Include/system_mgm22.h index 2786687ff0..07a6d376b2 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/system_mgm22.h +++ b/platform/Device/SiliconLabs/MGM22/Include/system_mgm22.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for MGM22 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Source/GCC/mgm22.ld b/platform/Device/SiliconLabs/MGM22/Source/GCC/mgm22.ld index cf2c69eeeb..3e05f6082a 100644 --- a/platform/Device/SiliconLabs/MGM22/Source/GCC/mgm22.ld +++ b/platform/Device/SiliconLabs/MGM22/Source/GCC/mgm22.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs MGM22 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM22/Source/IAR/startup_mgm22.s b/platform/Device/SiliconLabs/MGM22/Source/IAR/startup_mgm22.s index 99cebeb017..904cb1cad0 100644 --- a/platform/Device/SiliconLabs/MGM22/Source/IAR/startup_mgm22.s +++ b/platform/Device/SiliconLabs/MGM22/Source/IAR/startup_mgm22.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/MGM22/Source/system_mgm22.c b/platform/Device/SiliconLabs/MGM22/Source/system_mgm22.c index e6312cee4c..5fd0e00695 100644 --- a/platform/Device/SiliconLabs/MGM22/Source/system_mgm22.c +++ b/platform/Device/SiliconLabs/MGM22/Source/system_mgm22.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for MGM22 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/em_device.h b/platform/Device/SiliconLabs/MGM24/Include/em_device.h index 7d6939f195..1cd2761b3d 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/em_device.h +++ b/platform/Device/SiliconLabs/MGM24/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240l022rnf.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240l022rnf.h index 0418e22a91..dceacd6379 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240l022rnf.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240l022rnf.h @@ -4,7 +4,7 @@ * for MGM240L022RNF ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vif.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vif.h index 5a9855192d..6b983c1e4b 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vif.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vif.h @@ -4,7 +4,7 @@ * for MGM240L022VIF ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vnf.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vnf.h index d52662b6f4..9cd6a175ff 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vnf.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vnf.h @@ -4,7 +4,7 @@ * for MGM240L022VNF ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240la22uif.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240la22uif.h index 0879cd7ee2..0d1f8339fa 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240la22uif.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240la22uif.h @@ -4,7 +4,7 @@ * for MGM240LA22UIF ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240la22vif.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240la22vif.h index 9e12c83afa..f7289e520d 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240la22vif.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240la22vif.h @@ -4,7 +4,7 @@ * for MGM240LA22VIF ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240ld22vif.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240ld22vif.h index 28af983b6e..55cedefaa3 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240ld22vif.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240ld22vif.h @@ -4,7 +4,7 @@ * for MGM240LD22VIF ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa22vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa22vna.h index 9e419c23a0..bf9557d768 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa22vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa22vna.h @@ -4,7 +4,7 @@ * for MGM240PA22VNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vna.h index 1fcef26ad1..e93f833114 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vna.h @@ -4,7 +4,7 @@ * for MGM240PA32VNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vnn.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vnn.h index eb588ee1f0..7aae196f86 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vnn.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vnn.h @@ -4,7 +4,7 @@ * for MGM240PA32VNN ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb22vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb22vna.h index 1d0446b391..1a78bc61d8 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb22vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb22vna.h @@ -4,7 +4,7 @@ * for MGM240PB22VNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vna.h index 931a9eef2e..bcf02c3833 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vna.h @@ -4,7 +4,7 @@ * for MGM240PB32VNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vnn.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vnn.h index b1575c9306..4e32d8a029 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vnn.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vnn.h @@ -4,7 +4,7 @@ * for MGM240PB32VNN ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240sa22vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240sa22vna.h index 494685c3d5..ea26128ac0 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240sa22vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240sa22vna.h @@ -4,7 +4,7 @@ * for MGM240SA22VNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240sb22vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240sb22vna.h index 543bf72524..1fcd9220b1 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240sb22vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240sb22vna.h @@ -4,7 +4,7 @@ * for MGM240SB22VNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240sd22vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240sd22vna.h index 5f44f3c2d8..86bc541341 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240sd22vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240sd22vna.h @@ -4,7 +4,7 @@ * for MGM240SD22VNA ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_acmp.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_acmp.h index 8af89d1b17..71e68afd0e 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_acmp.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_acmp.h @@ -3,7 +3,7 @@ * @brief MGM24 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_aes.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_aes.h index c78c690a05..befc77f39f 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_aes.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_aes.h @@ -3,7 +3,7 @@ * @brief MGM24 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_buram.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_buram.h index 459dc22a81..e1576341b8 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_buram.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_buram.h @@ -3,7 +3,7 @@ * @brief MGM24 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_burtc.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_burtc.h index df1b9b5d47..56e8701fec 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_burtc.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_burtc.h @@ -3,7 +3,7 @@ * @brief MGM24 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_cmu.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_cmu.h index 3070b6dbf7..27894fff54 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_cmu.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_cmu.h @@ -3,7 +3,7 @@ * @brief MGM24 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_dcdc.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_dcdc.h index cc7991516c..93445f210d 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_dcdc.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_dcdc.h @@ -3,7 +3,7 @@ * @brief MGM24 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_devinfo.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_devinfo.h index 19cc5eb59c..627e93bb51 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_devinfo.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_devinfo.h @@ -3,7 +3,7 @@ * @brief MGM24 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_dma_descriptor.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_dma_descriptor.h index 9d6859823e..80915c733f 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_dma_descriptor.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief MGM24 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_dpll.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_dpll.h index 63e4439bea..68b9e8f8de 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_dpll.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_dpll.h @@ -3,7 +3,7 @@ * @brief MGM24 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_emu.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_emu.h index c02c55a131..e7705653ee 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_emu.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_emu.h @@ -3,7 +3,7 @@ * @brief MGM24 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_eusart.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_eusart.h index cbc6ad9c6e..a229aaddef 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_eusart.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_eusart.h @@ -3,7 +3,7 @@ * @brief MGM24 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_fsrco.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_fsrco.h index 4d67f79130..fc322d051e 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_fsrco.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_fsrco.h @@ -3,7 +3,7 @@ * @brief MGM24 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpcrc.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpcrc.h index e2b2f30a9e..a11ab5c631 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpcrc.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpcrc.h @@ -3,7 +3,7 @@ * @brief MGM24 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpio.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpio.h index 0038d607ea..f4f0004b3c 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpio.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpio.h @@ -3,7 +3,7 @@ * @brief MGM24 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpio_port.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpio_port.h index 99090b2e99..b53f84bbfb 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpio_port.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_gpio_port.h @@ -3,7 +3,7 @@ * @brief MGM24 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_hfrco.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_hfrco.h index 1bb612d1dc..a16b142bd6 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_hfrco.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_hfrco.h @@ -3,7 +3,7 @@ * @brief MGM24 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_hfxo.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_hfxo.h index 6c923716ea..48f835f081 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_hfxo.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_hfxo.h @@ -3,7 +3,7 @@ * @brief MGM24 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_i2c.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_i2c.h index 89809933b1..bd60e92e40 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_i2c.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_i2c.h @@ -3,7 +3,7 @@ * @brief MGM24 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_iadc.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_iadc.h index 9572e27e57..d6c1c49921 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_iadc.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_iadc.h @@ -3,7 +3,7 @@ * @brief MGM24 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_icache.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_icache.h index e94006c156..0a7493fd3f 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_icache.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_icache.h @@ -3,7 +3,7 @@ * @brief MGM24 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_keyscan.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_keyscan.h index b67ba5ad87..a8304435a5 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_keyscan.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_keyscan.h @@ -3,7 +3,7 @@ * @brief MGM24 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldma.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldma.h index 1dea165e68..547ae95feb 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldma.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldma.h @@ -3,7 +3,7 @@ * @brief MGM24 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar.h index a30db7c0e3..b657504772 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief MGM24 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar_defines.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar_defines.h index 9aac3b3840..7a6be30e68 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief MGM24 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_letimer.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_letimer.h index 8fd04c2ed7..173409a55e 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_letimer.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_letimer.h @@ -3,7 +3,7 @@ * @brief MGM24 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_lfrco.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_lfrco.h index 75241ea302..029edbf161 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_lfrco.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_lfrco.h @@ -3,7 +3,7 @@ * @brief MGM24 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_lfxo.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_lfxo.h index 67b1bc212a..74b46ef5a0 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_lfxo.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_lfxo.h @@ -3,7 +3,7 @@ * @brief MGM24 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_mailbox.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_mailbox.h index 53ea9a5ba5..446e4fdd33 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_mailbox.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_mailbox.h @@ -3,7 +3,7 @@ * @brief MGM24 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_mpahbram.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_mpahbram.h index 7cfad6c610..ba248d4f35 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_mpahbram.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_mpahbram.h @@ -3,7 +3,7 @@ * @brief MGM24 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_msc.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_msc.h index 064ad29735..add044ce90 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_msc.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_msc.h @@ -3,7 +3,7 @@ * @brief MGM24 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_mvp.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_mvp.h index 317975c10b..a176ebff83 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_mvp.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_mvp.h @@ -3,7 +3,7 @@ * @brief MGM24 MVP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_pcnt.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_pcnt.h index a59f4de2fa..54d1b06095 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_pcnt.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_pcnt.h @@ -3,7 +3,7 @@ * @brief MGM24 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs.h index 96c5106256..b9e9cc5a31 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs.h @@ -3,7 +3,7 @@ * @brief MGM24 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs_signals.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs_signals.h index f9fcd0e8c0..f4373adb33 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs_signals.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs_signals.h @@ -3,7 +3,7 @@ * @brief MGM24 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_scratchpad.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_scratchpad.h index 2f3d9c0f44..bddd735aa5 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_scratchpad.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_scratchpad.h @@ -3,7 +3,7 @@ * @brief MGM24 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_semailbox.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_semailbox.h index ed00ce94b3..80c86c5a57 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_semailbox.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_semailbox.h @@ -3,7 +3,7 @@ * @brief MGM24 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_smu.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_smu.h index a255594139..c13622da2e 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_smu.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_smu.h @@ -3,7 +3,7 @@ * @brief MGM24 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_syscfg.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_syscfg.h index c3601320ad..0f52fdf2dd 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_syscfg.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_syscfg.h @@ -3,7 +3,7 @@ * @brief MGM24 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_sysrtc.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_sysrtc.h index 732adc0d15..045b998855 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_sysrtc.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_sysrtc.h @@ -3,7 +3,7 @@ * @brief MGM24 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_timer.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_timer.h index 07d7c88ef0..606fd0199a 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_timer.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_timer.h @@ -3,7 +3,7 @@ * @brief MGM24 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ulfrco.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ulfrco.h index 0e409e87ec..6bbc988c85 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ulfrco.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ulfrco.h @@ -3,7 +3,7 @@ * @brief MGM24 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_usart.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_usart.h index 9279ed5983..018f84cfb3 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_usart.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_usart.h @@ -3,7 +3,7 @@ * @brief MGM24 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_vdac.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_vdac.h index 70052ada2c..bf828a12f9 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_vdac.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_vdac.h @@ -3,7 +3,7 @@ * @brief MGM24 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_wdog.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_wdog.h index bc2ed04378..0cd8de5a5c 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_wdog.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_wdog.h @@ -3,7 +3,7 @@ * @brief MGM24 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Include/system_mgm24.h b/platform/Device/SiliconLabs/MGM24/Include/system_mgm24.h index aff636bbc9..bf4f418ad1 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/system_mgm24.h +++ b/platform/Device/SiliconLabs/MGM24/Include/system_mgm24.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for MGM24 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Source/GCC/mgm24.ld b/platform/Device/SiliconLabs/MGM24/Source/GCC/mgm24.ld index ca0b659eb7..d4d281149b 100644 --- a/platform/Device/SiliconLabs/MGM24/Source/GCC/mgm24.ld +++ b/platform/Device/SiliconLabs/MGM24/Source/GCC/mgm24.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs MGM24 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/MGM24/Source/IAR/startup_mgm24.s b/platform/Device/SiliconLabs/MGM24/Source/IAR/startup_mgm24.s index c1f90c945d..9e218bca71 100644 --- a/platform/Device/SiliconLabs/MGM24/Source/IAR/startup_mgm24.s +++ b/platform/Device/SiliconLabs/MGM24/Source/IAR/startup_mgm24.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/MGM24/Source/system_mgm24.c b/platform/Device/SiliconLabs/MGM24/Source/system_mgm24.c index bf58b81705..9b46756978 100644 --- a/platform/Device/SiliconLabs/MGM24/Source/system_mgm24.c +++ b/platform/Device/SiliconLabs/MGM24/Source/system_mgm24.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for MGM24 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/em_device.h b/platform/Device/SiliconLabs/ZGM23/Include/em_device.h index 148369ef65..772f3e883e 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/em_device.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/em_device.h @@ -14,7 +14,7 @@ * @endverbatim ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/system_zgm23.h b/platform/Device/SiliconLabs/ZGM23/Include/system_zgm23.h index 797def0d70..50e46a3ddf 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/system_zgm23.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/system_zgm23.h @@ -3,7 +3,7 @@ * @brief CMSIS system header file for ZGM23 ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hgn.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hgn.h index 4c68bfac12..225405118c 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hgn.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hgn.h @@ -4,7 +4,7 @@ * for ZGM230SA27HGN ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hnn.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hnn.h index c778c7c0fe..ed9997dd52 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hnn.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hnn.h @@ -4,7 +4,7 @@ * for ZGM230SA27HNN ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hgn.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hgn.h index 6eecf0c6d5..0ef546c7df 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hgn.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hgn.h @@ -4,7 +4,7 @@ * for ZGM230SB27HGN ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hnn.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hnn.h index 0f56a0f1eb..39ca2468b3 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hnn.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hnn.h @@ -4,7 +4,7 @@ * for ZGM230SB27HNN ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_acmp.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_acmp.h index efc591d9a9..29b3084672 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_acmp.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_acmp.h @@ -3,7 +3,7 @@ * @brief ZGM23 ACMP register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_aes.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_aes.h index ce0755aa0d..bcca160f5d 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_aes.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_aes.h @@ -3,7 +3,7 @@ * @brief ZGM23 AES register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_buram.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_buram.h index 5b369e388f..458e1de9a7 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_buram.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_buram.h @@ -3,7 +3,7 @@ * @brief ZGM23 BURAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_burtc.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_burtc.h index d88e209bb1..f81e44d23f 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_burtc.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_burtc.h @@ -3,7 +3,7 @@ * @brief ZGM23 BURTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_cmu.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_cmu.h index 5a4dcaa773..ddc26c8e3a 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_cmu.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_cmu.h @@ -3,7 +3,7 @@ * @brief ZGM23 CMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dcdc.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dcdc.h index 7e845f3b01..c2fe0e0a46 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dcdc.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dcdc.h @@ -3,7 +3,7 @@ * @brief ZGM23 DCDC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_devinfo.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_devinfo.h index 6e5a829da3..32cd070c6f 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_devinfo.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_devinfo.h @@ -3,7 +3,7 @@ * @brief ZGM23 DEVINFO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dma_descriptor.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dma_descriptor.h index f6a3bbe244..1e41bcc442 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dma_descriptor.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dma_descriptor.h @@ -3,7 +3,7 @@ * @brief ZGM23 DMA descriptor bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dpll.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dpll.h index 3405cff6e9..40249ba1a7 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dpll.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dpll.h @@ -3,7 +3,7 @@ * @brief ZGM23 DPLL register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_emu.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_emu.h index 75fbc82498..251a1f9765 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_emu.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_emu.h @@ -3,7 +3,7 @@ * @brief ZGM23 EMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_eusart.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_eusart.h index 57c122fe4c..8614ea8760 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_eusart.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_eusart.h @@ -3,7 +3,7 @@ * @brief ZGM23 EUSART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_fsrco.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_fsrco.h index 78ba1c293e..816d11c9e3 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_fsrco.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_fsrco.h @@ -3,7 +3,7 @@ * @brief ZGM23 FSRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpcrc.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpcrc.h index b7ce4f5ef3..c97971da9d 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpcrc.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpcrc.h @@ -3,7 +3,7 @@ * @brief ZGM23 GPCRC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpio.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpio.h index 8d5c02658f..b3d433fe36 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpio.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpio.h @@ -3,7 +3,7 @@ * @brief ZGM23 GPIO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpio_port.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpio_port.h index 9ef6326519..5271c28944 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpio_port.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_gpio_port.h @@ -3,7 +3,7 @@ * @brief ZGM23 GPIO Port register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_hfrco.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_hfrco.h index 7655f41e0b..51b53057f4 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_hfrco.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_hfrco.h @@ -3,7 +3,7 @@ * @brief ZGM23 HFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_hfxo.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_hfxo.h index e9378a793e..9a3fd55474 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_hfxo.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_hfxo.h @@ -3,7 +3,7 @@ * @brief ZGM23 HFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_i2c.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_i2c.h index 5032b2a821..a1c09e6eae 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_i2c.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_i2c.h @@ -3,7 +3,7 @@ * @brief ZGM23 I2C register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_iadc.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_iadc.h index 20c7389a5f..f10194fc2c 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_iadc.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_iadc.h @@ -3,7 +3,7 @@ * @brief ZGM23 IADC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_icache.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_icache.h index 3a664519a1..c076b82f1e 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_icache.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_icache.h @@ -3,7 +3,7 @@ * @brief ZGM23 ICACHE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_keyscan.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_keyscan.h index cebba1f91d..425b40123d 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_keyscan.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_keyscan.h @@ -3,7 +3,7 @@ * @brief ZGM23 KEYSCAN register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lcd.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lcd.h index 9d5d0138f8..793ea29e8d 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lcd.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lcd.h @@ -3,7 +3,7 @@ * @brief ZGM23 LCD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lcdrf.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lcdrf.h index e04d71bf85..32b5b7cc1d 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lcdrf.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lcdrf.h @@ -3,7 +3,7 @@ * @brief ZGM23 LCDRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldma.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldma.h index 88ff1ae893..3ea9bc7a8e 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldma.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldma.h @@ -3,7 +3,7 @@ * @brief ZGM23 LDMA register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar.h index 9e3fc6a826..f36d5b0a97 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar.h @@ -3,7 +3,7 @@ * @brief ZGM23 LDMAXBAR register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar_defines.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar_defines.h index 24f8d8c90f..d048a6fd9d 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar_defines.h @@ -3,7 +3,7 @@ * @brief ZGM23 LDMA XBAR channel request soruce definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lesense.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lesense.h index a5144739b4..e8b7375633 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lesense.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lesense.h @@ -3,7 +3,7 @@ * @brief ZGM23 LESENSE register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_letimer.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_letimer.h index 7799399f18..2b9ece1993 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_letimer.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_letimer.h @@ -3,7 +3,7 @@ * @brief ZGM23 LETIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lfrco.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lfrco.h index a25c86ec64..fbd076ccb2 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lfrco.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lfrco.h @@ -3,7 +3,7 @@ * @brief ZGM23 LFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lfxo.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lfxo.h index 883f0451b5..c2d56190c2 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lfxo.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_lfxo.h @@ -3,7 +3,7 @@ * @brief ZGM23 LFXO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_mailbox.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_mailbox.h index 95c29ab4d7..30f0dffaea 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_mailbox.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_mailbox.h @@ -3,7 +3,7 @@ * @brief ZGM23 MAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_mpahbram.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_mpahbram.h index 0c595b7678..8a26ddc2d9 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_mpahbram.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_mpahbram.h @@ -3,7 +3,7 @@ * @brief ZGM23 MPAHBRAM register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_msc.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_msc.h index e3626e5a4d..5d70970143 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_msc.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_msc.h @@ -3,7 +3,7 @@ * @brief ZGM23 MSC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_pcnt.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_pcnt.h index e54ce94f4b..51062e7587 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_pcnt.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_pcnt.h @@ -3,7 +3,7 @@ * @brief ZGM23 PCNT register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_pfmxpprf.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_pfmxpprf.h index b7aedf7317..078bfc9573 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_pfmxpprf.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_pfmxpprf.h @@ -3,7 +3,7 @@ * @brief ZGM23 PFMXPPRF register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs.h index 768f944aee..14823c42b3 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs.h @@ -3,7 +3,7 @@ * @brief ZGM23 PRS register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs_signals.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs_signals.h index f33363e834..3939ba1508 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs_signals.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs_signals.h @@ -3,7 +3,7 @@ * @brief ZGM23 PRS register signal bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_scratchpad.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_scratchpad.h index 9151b81608..4afb9e654b 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_scratchpad.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_scratchpad.h @@ -3,7 +3,7 @@ * @brief ZGM23 SCRATCHPAD register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_semailbox.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_semailbox.h index 0c7924287c..49deb8e29c 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_semailbox.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_semailbox.h @@ -3,7 +3,7 @@ * @brief ZGM23 SEMAILBOX register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_smu.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_smu.h index 68a8cd8dbf..b40fb6674a 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_smu.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_smu.h @@ -3,7 +3,7 @@ * @brief ZGM23 SMU register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_syscfg.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_syscfg.h index 77fd8de1f0..56592a74f1 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_syscfg.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_syscfg.h @@ -3,7 +3,7 @@ * @brief ZGM23 SYSCFG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_sysrtc.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_sysrtc.h index 631b721347..ee250cdbd8 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_sysrtc.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_sysrtc.h @@ -3,7 +3,7 @@ * @brief ZGM23 SYSRTC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_timer.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_timer.h index 373c851855..b996b3e699 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_timer.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_timer.h @@ -3,7 +3,7 @@ * @brief ZGM23 TIMER register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ulfrco.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ulfrco.h index e64775a509..f29649b48d 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ulfrco.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ulfrco.h @@ -3,7 +3,7 @@ * @brief ZGM23 ULFRCO register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_usart.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_usart.h index fa693140c9..f5e462ed0c 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_usart.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_usart.h @@ -3,7 +3,7 @@ * @brief ZGM23 USART register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_vdac.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_vdac.h index 8db9c63796..4ea6364f5b 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_vdac.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_vdac.h @@ -3,7 +3,7 @@ * @brief ZGM23 VDAC register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_wdog.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_wdog.h index 7c452eead2..cb32140c4d 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_wdog.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_wdog.h @@ -3,7 +3,7 @@ * @brief ZGM23 WDOG register and bit field definitions ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Source/GCC/zgm23.ld b/platform/Device/SiliconLabs/ZGM23/Source/GCC/zgm23.ld index 96f73d4bf7..b402ec17eb 100644 --- a/platform/Device/SiliconLabs/ZGM23/Source/GCC/zgm23.ld +++ b/platform/Device/SiliconLabs/ZGM23/Source/GCC/zgm23.ld @@ -6,7 +6,7 @@ * Linker script for Silicon Labs ZGM23 devices ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/platform/Device/SiliconLabs/ZGM23/Source/IAR/startup_zgm23.s b/platform/Device/SiliconLabs/ZGM23/Source/IAR/startup_zgm23.s index 4a1840ee98..b0b9cb678d 100644 --- a/platform/Device/SiliconLabs/ZGM23/Source/IAR/startup_zgm23.s +++ b/platform/Device/SiliconLabs/ZGM23/Source/IAR/startup_zgm23.s @@ -17,7 +17,7 @@ ; * ; *****************************************************************************/ ;/* -; * Copyright 2009-2023 ARM Limited. All rights reserved. +; * Copyright 2009-2024 ARM Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * diff --git a/platform/Device/SiliconLabs/ZGM23/Source/system_zgm23.c b/platform/Device/SiliconLabs/ZGM23/Source/system_zgm23.c index 79c44bf1fa..40014286cf 100644 --- a/platform/Device/SiliconLabs/ZGM23/Source/system_zgm23.c +++ b/platform/Device/SiliconLabs/ZGM23/Source/system_zgm23.c @@ -3,7 +3,7 @@ * @brief CMSIS Cortex-M33 system support for ZGM23 devices. ****************************************************************************** * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com ****************************************************************************** * * SPDX-License-Identifier: Zlib diff --git a/platform/bootloader/bootloader_production_templates.xml b/platform/bootloader/bootloader_production_templates.xml index 539d6a6b62..56d62117ab 100644 --- a/platform/bootloader/bootloader_production_templates.xml +++ b/platform/bootloader/bootloader_production_templates.xml @@ -22,7 +22,7 @@ - + @@ -38,7 +38,7 @@ - + @@ -54,7 +54,7 @@ - + @@ -340,7 +340,7 @@ - + @@ -385,7 +385,7 @@ - + @@ -400,7 +400,7 @@ - + @@ -460,7 +460,7 @@ - + @@ -475,7 +475,7 @@ - + @@ -490,7 +490,7 @@ - + @@ -505,7 +505,7 @@ - + @@ -520,7 +520,7 @@ - + @@ -535,7 +535,7 @@ - + diff --git a/platform/bootloader/config/btl_config.h b/platform/bootloader/config/btl_config.h index 0c91a90778..8cd7513308 100644 --- a/platform/bootloader/config/btl_config.h +++ b/platform/bootloader/config/btl_config.h @@ -41,7 +41,7 @@ MISRAC_ENABLE #endif #ifndef BOOTLOADER_VERSION_MAIN_CUSTOMER -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 2 #endif #define BOOTLOADER_VERSION_MAIN (BOOTLOADER_VERSION_MAIN_MAJOR << 24 \ diff --git a/platform/bootloader/config/s1/device_sdid_80/btl_core_cfg.h b/platform/bootloader/config/s1/device_sdid_80/btl_core_cfg.h index 2226fc05f5..dfc928d926 100644 --- a/platform/bootloader/config/s1/device_sdid_80/btl_core_cfg.h +++ b/platform/bootloader/config/s1/device_sdid_80/btl_core_cfg.h @@ -90,7 +90,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 2 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/s1/device_sdid_80/device_has_radio/btl_core_cfg.h b/platform/bootloader/config/s1/device_sdid_80/device_has_radio/btl_core_cfg.h index 5383b2b193..757db2c5d8 100644 --- a/platform/bootloader/config/s1/device_sdid_80/device_has_radio/btl_core_cfg.h +++ b/platform/bootloader/config/s1/device_sdid_80/device_has_radio/btl_core_cfg.h @@ -90,7 +90,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 2 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/s1/device_series_1/btl_core_cfg.h b/platform/bootloader/config/s1/device_series_1/btl_core_cfg.h index b6add5ce01..beaf943b86 100644 --- a/platform/bootloader/config/s1/device_series_1/btl_core_cfg.h +++ b/platform/bootloader/config/s1/device_series_1/btl_core_cfg.h @@ -91,7 +91,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 2 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/s2/device_sdid_205/apploader/btl_core_cfg.h b/platform/bootloader/config/s2/device_sdid_205/apploader/btl_core_cfg.h index df88d592be..910fae87f0 100644 --- a/platform/bootloader/config/s2/device_sdid_205/apploader/btl_core_cfg.h +++ b/platform/bootloader/config/s2/device_sdid_205/apploader/btl_core_cfg.h @@ -103,7 +103,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 2 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/s2/device_sdid_205/apploader/btl_core_s_cfg.h b/platform/bootloader/config/s2/device_sdid_205/apploader/btl_core_s_cfg.h index 9176b41972..1f0cee2ed4 100644 --- a/platform/bootloader/config/s2/device_sdid_205/apploader/btl_core_s_cfg.h +++ b/platform/bootloader/config/s2/device_sdid_205/apploader/btl_core_s_cfg.h @@ -93,7 +93,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 2 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/s2/device_sdid_205/btl_core_cfg.h b/platform/bootloader/config/s2/device_sdid_205/btl_core_cfg.h index d11c411f4a..fe3f8505a9 100644 --- a/platform/bootloader/config/s2/device_sdid_205/btl_core_cfg.h +++ b/platform/bootloader/config/s2/device_sdid_205/btl_core_cfg.h @@ -114,7 +114,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 2 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/s2/device_sdid_205/btl_core_s_cfg.h b/platform/bootloader/config/s2/device_sdid_205/btl_core_s_cfg.h index 389994e86d..5a7311f3e1 100644 --- a/platform/bootloader/config/s2/device_sdid_205/btl_core_s_cfg.h +++ b/platform/bootloader/config/s2/device_sdid_205/btl_core_s_cfg.h @@ -93,7 +93,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 2 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/s2/device_series_2/apploader/btl_core_cfg.h b/platform/bootloader/config/s2/device_series_2/apploader/btl_core_cfg.h index 0803776055..fdbd9a983d 100644 --- a/platform/bootloader/config/s2/device_series_2/apploader/btl_core_cfg.h +++ b/platform/bootloader/config/s2/device_series_2/apploader/btl_core_cfg.h @@ -103,7 +103,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 2 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/s2/device_series_2/apploader/btl_core_s_cfg.h b/platform/bootloader/config/s2/device_series_2/apploader/btl_core_s_cfg.h index 1c1af3994d..7d570e7d24 100644 --- a/platform/bootloader/config/s2/device_series_2/apploader/btl_core_s_cfg.h +++ b/platform/bootloader/config/s2/device_series_2/apploader/btl_core_s_cfg.h @@ -98,7 +98,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 2 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/s2/device_series_2/btl_core_cfg.h b/platform/bootloader/config/s2/device_series_2/btl_core_cfg.h index 1d898da56d..e8006b701f 100644 --- a/platform/bootloader/config/s2/device_series_2/btl_core_cfg.h +++ b/platform/bootloader/config/s2/device_series_2/btl_core_cfg.h @@ -114,7 +114,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 2 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/s2/device_series_2/btl_core_s_cfg.h b/platform/bootloader/config/s2/device_series_2/btl_core_s_cfg.h index 96bde852dd..25d50f2bb0 100644 --- a/platform/bootloader/config/s2/device_series_2/btl_core_s_cfg.h +++ b/platform/bootloader/config/s2/device_series_2/btl_core_s_cfg.h @@ -98,7 +98,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 2 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/core/btl_main_s.c b/platform/bootloader/core/btl_main_s.c index 9ba5331040..52f61728c3 100644 --- a/platform/bootloader/core/btl_main_s.c +++ b/platform/bootloader/core/btl_main_s.c @@ -98,6 +98,10 @@ const uint32_t linker_sg_begin @ "Veneer$$CMSE"; #endif typedef void (*tz_nonsecure_function_void)(void) __attribute__((cmse_nonsecure_call)); +#ifdef BOOTLOADER_SUPPORT_STORAGE +extern const BootloaderStorageFunctions_t storageFunctions; +#endif + // ----------------------------------------------------------------------------- // Bootloader main stage table diff --git a/platform/common/inc/sl_gsdk_version.h b/platform/common/inc/sl_gsdk_version.h index 932d201e49..8fe6fd2b7d 100644 --- a/platform/common/inc/sl_gsdk_version.h +++ b/platform/common/inc/sl_gsdk_version.h @@ -31,7 +31,7 @@ #define SL_GSDK_MAJOR_VERSION 4 #define SL_GSDK_MINOR_VERSION 4 -#define SL_GSDK_PATCH_VERSION 1 +#define SL_GSDK_PATCH_VERSION 2 #define SL_GSDK_VERSION ((SL_GSDK_MAJOR_VERSION << 8) \ | (SL_GSDK_MINOR_VERSION << 4) \ diff --git a/platform/common/toolchain/gcc/linkerfile_base.ld.jinja b/platform/common/toolchain/gcc/linkerfile_base.ld.jinja index ed95dcbf2e..6515a1e668 100644 --- a/platform/common/toolchain/gcc/linkerfile_base.ld.jinja +++ b/platform/common/toolchain/gcc/linkerfile_base.ld.jinja @@ -358,7 +358,7 @@ SECTIONS {% if trustzone_secure is not defined %} {%- if app_flash_start and app_flash_size %} app_flash_end = 0x{{ '%0x' % (app_flash_start) }} + 0x{{ '%0x' % (app_flash_size) }}; - ASSERT( (linker_storage_end + SIZEOF(.internal_storage)) <= app_flash_end, "Internal storage is excessing the flash size !") + ASSERT( (linker_storage_begin + SIZEOF(.internal_storage)) <= app_flash_end, "Internal storage is excessing the flash size !") {%- endif %} {%- endif %} {#- trustzone_secure #} diff --git a/platform/driver/button/src/sl_simple_button.c b/platform/driver/button/src/sl_simple_button.c index e0a37e4b5d..7c095bb32b 100644 --- a/platform/driver/button/src/sl_simple_button.c +++ b/platform/driver/button/src/sl_simple_button.c @@ -86,6 +86,46 @@ sl_status_t sl_simple_button_init(const sl_button_t *handle) if (simple_button->mode == SL_SIMPLE_BUTTON_MODE_INTERRUPT) { GPIOINT_Init(); + +#if defined(_SILICON_LABS_32B_SERIES_2) + // Try to register an EM4WU interrupt for the given pin + interrupt = GPIOINT_EM4WUCallbackRegisterExt(simple_button->port, + simple_button->pin, + (GPIOINT_IrqCallbackPtrExt_t)sli_simple_button_on_change, + button); + if (interrupt == INTERRUPT_UNAVAILABLE) { + // if the pin not EM4WU-compatible, instead register a regualr interrupt + interrupt = GPIOINT_CallbackRegisterExt(simple_button->pin, + (GPIOINT_IrqCallbackPtrExt_t)sli_simple_button_on_change, + button); + EFM_ASSERT(interrupt != INTERRUPT_UNAVAILABLE); + GPIO_ExtIntConfig(simple_button->port, + simple_button->pin, + interrupt, + true, + true, + true); + } else { + // If the pin is EM4WU-compatible, setup the pin as an EM4WU pin + GPIO_EM4WUExtIntConfig(simple_button->port, + simple_button->pin, + interrupt, + SL_SIMPLE_BUTTON_POLARITY, + true); + + // Since EM4WU interrupts are level-sensitive and not edge-sensitive, also register a regular edge-sensitive interrupt to capture the other edge + interrupt = GPIOINT_CallbackRegisterExt(simple_button->pin, + (GPIOINT_IrqCallbackPtrExt_t)sli_simple_button_on_change, + button); + EFM_ASSERT(interrupt != INTERRUPT_UNAVAILABLE); + GPIO_ExtIntConfig(simple_button->port, + simple_button->pin, + interrupt, + (SL_SIMPLE_BUTTON_POLARITY == 0U), // Register a Rising Edge interrupt for an Active Low button + (SL_SIMPLE_BUTTON_POLARITY == 1U), // Register a Falling Edge interrupt for an Active High button + true); + } +#else interrupt = GPIOINT_CallbackRegisterExt(simple_button->pin, (GPIOINT_IrqCallbackPtrExt_t)sli_simple_button_on_change, button); @@ -96,6 +136,7 @@ sl_status_t sl_simple_button_init(const sl_button_t *handle) true, true, true); +#endif } return SL_STATUS_OK; diff --git a/platform/emdrv/gpiointerrupt/inc/gpiointerrupt.h b/platform/emdrv/gpiointerrupt/inc/gpiointerrupt.h index 2ab8065747..0ccd1302d9 100644 --- a/platform/emdrv/gpiointerrupt/inc/gpiointerrupt.h +++ b/platform/emdrv/gpiointerrupt/inc/gpiointerrupt.h @@ -32,6 +32,7 @@ #define GPIOINTERRUPT_H #include "em_device.h" +#include "em_gpio.h" #ifdef __cplusplus extern "C" { @@ -78,6 +79,13 @@ void GPIOINT_CallbackRegister(uint8_t intNo, GPIOINT_IrqCallbackPtr_t callbackPt unsigned int GPIOINT_CallbackRegisterExt(uint8_t pin, GPIOINT_IrqCallbackPtrExt_t callbackPtr, void *callbackCtx); __STATIC_INLINE void GPIOINT_CallbackUnRegister(uint8_t intNo); +#if defined(_SILICON_LABS_32B_SERIES_2) +unsigned int GPIOINT_EM4WUCallbackRegisterExt(GPIO_Port_TypeDef port, + uint8_t pin, + GPIOINT_IrqCallbackPtrExt_t callbackPtr, + void *callbackCtx); +__STATIC_INLINE void GPIOINT_EM4WUCallbackUnRegister(uint8_t intNo); +#endif /***************************************************************************//** * @brief * Unregister user callback for a given pin interrupt number. @@ -94,6 +102,28 @@ __STATIC_INLINE void GPIOINT_CallbackUnRegister(uint8_t intNo) GPIOINT_CallbackRegister(intNo, 0); } +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Unregister user EM4WU callback for a given pin interrupt number. + * + * @details + * Use this function to unregister a EM4WU callback. + * + * @param[in] intNo + * Pin interrupt number for the EM4WU callback. + * + ******************************************************************************/ +__STATIC_INLINE void GPIOINT_EM4WUCallbackUnRegister(uint8_t intNo) +{ +#if defined(_GPIO_IEN_EM4WUIEN_SHIFT) + GPIOINT_CallbackRegister(_GPIO_IEN_EM4WUIEN_SHIFT + intNo, 0); +#else + GPIOINT_CallbackRegister(_GPIO_IEN_EM4WUIEN0_SHIFT + intNo, 0); +#endif +} +#endif + /** @} (end addtogroup gpioint) */ #ifdef __cplusplus } diff --git a/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c b/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c index 049a97070a..a8e559e074 100755 --- a/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c +++ b/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c @@ -28,7 +28,6 @@ * ******************************************************************************/ -#include "em_gpio.h" #include "em_core.h" #include "gpiointerrupt.h" #include "sl_assert.h" @@ -126,6 +125,95 @@ void GPIOINT_CallbackRegister(uint8_t intNo, GPIOINT_IrqCallbackPtr_t callbackPt ) } +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Registers user em4 wakeup callback for given port and pin interrupt number. + * + * @details + * Use this function to register an EM4 wakeup callback with context which shall + * be called upon interrupt generated for a given pin number. + * The function will return an interrupt number if one is available and pin is + * EM4WU compatible. + * Interrupt itself must be configured externally. + * + * @param[in] port + * GPIO Port for the callback. + * @param[in] pin + * Pin number for the callback. + * @param[in] callbackPtr + * A pointer to callback function. + * @param[in] callbackCtx + * A pointer to the callback context. + * + * @return + * Interrupt number, or INTERRUPT_UNAVAILABLE if all are in use or pin doesn't + * support em4 wakeup. + ******************************************************************************/ +unsigned int GPIOINT_EM4WUCallbackRegisterExt(GPIO_Port_TypeDef port, + uint8_t pin, + GPIOINT_IrqCallbackPtrExt_t callbackPtr, + void *callbackCtx) +{ + CORE_DECLARE_IRQ_STATE; + unsigned int intNo = INTERRUPT_UNAVAILABLE; + + CORE_ENTER_ATOMIC(); + + if (false) { + /* Check all the EM4WU Pins and check if given pin matches any of them. */ +#if defined(GPIO_EM4WU0_PORT) + } else if (GPIO_EM4WU0_PORT == port && GPIO_EM4WU0_PIN == pin) { + intNo = 0; +#endif +#if defined(GPIO_EM4WU3_PORT) + } else if (GPIO_EM4WU3_PORT == port && GPIO_EM4WU3_PIN == pin) { + intNo = 3; +#endif +#if defined(GPIO_EM4WU4_PORT) + } else if (GPIO_EM4WU4_PORT == port && GPIO_EM4WU4_PIN == pin) { + intNo = 4; +#endif +#if defined(GPIO_EM4WU6_PORT) + } else if (GPIO_EM4WU6_PORT == port && GPIO_EM4WU6_PIN == pin) { + intNo = 6; +#endif +#if defined(GPIO_EM4WU7_PORT) + } else if (GPIO_EM4WU7_PORT == port && GPIO_EM4WU7_PIN == pin) { + intNo = 7; +#endif +#if defined(GPIO_EM4WU8_PORT) + } else if (GPIO_EM4WU8_PORT == port && GPIO_EM4WU8_PIN == pin) { + intNo = 8; +#endif +#if defined(GPIO_EM4WU9_PORT) + } else if (GPIO_EM4WU9_PORT == port && GPIO_EM4WU9_PIN == pin) { + intNo = 9; +#endif +#if defined(GPIO_EM4WU10_PORT) + } else if (GPIO_EM4WU10_PORT == port && GPIO_EM4WU10_PIN == pin) { + intNo = 10; +#endif + } + + if (intNo != INTERRUPT_UNAVAILABLE) { +#if defined(_GPIO_IEN_EM4WUIEN_SHIFT) + gpioCallbacks[_GPIO_IEN_EM4WUIEN_SHIFT + intNo].callback = (void *)callbackPtr; + gpioCallbacks[_GPIO_IEN_EM4WUIEN_SHIFT + intNo].context = callbackCtx; + gpioCallbacks[_GPIO_IEN_EM4WUIEN_SHIFT + intNo].context_flag = true; +#else + gpioCallbacks[_GPIO_IEN_EM4WUIEN0_SHIFT + intNo].callback = (void *)callbackPtr; + gpioCallbacks[_GPIO_IEN_EM4WUIEN0_SHIFT + intNo].context = callbackCtx; + gpioCallbacks[_GPIO_IEN_EM4WUIEN0_SHIFT + intNo].context_flag = true; +#endif + } + + CORE_EXIT_ATOMIC(); + + return intNo; +} +#endif + /***************************************************************************//** * @brief * Registers user callback for given pin interrupt number. diff --git a/platform/emdrv/nvm3/lib/libnvm3_CM0P_gcc.a b/platform/emdrv/nvm3/lib/libnvm3_CM0P_gcc.a index cff1011eb9..1b8a8b642b 100644 --- a/platform/emdrv/nvm3/lib/libnvm3_CM0P_gcc.a +++ b/platform/emdrv/nvm3/lib/libnvm3_CM0P_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4af13c49532b7c95779ad5a42750e0039d13eff5efcbbfef1756207b54c37613 +oid sha256:1864b6ee5d46e68c0e721c5716d8da6e8a2c21f6329e28304c3c97eefc65bacd size 34118 diff --git a/platform/emdrv/nvm3/lib/libnvm3_CM0P_iar.a b/platform/emdrv/nvm3/lib/libnvm3_CM0P_iar.a index faf868ed7f..7818cda92a 100644 --- a/platform/emdrv/nvm3/lib/libnvm3_CM0P_iar.a +++ b/platform/emdrv/nvm3/lib/libnvm3_CM0P_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a361c50f3c79f976a90659991d4ceeb4583e95777373d99deb667930d4ee822b +oid sha256:8a65cfb1ab7f9612777bb4cc1f6411ea251ddd2aacbd8f5dd5f6281fb564c509 size 75390 diff --git a/platform/emdrv/nvm3/lib/libnvm3_CM33_gcc.a b/platform/emdrv/nvm3/lib/libnvm3_CM33_gcc.a index 89d020e9f2..711bfa8199 100644 --- a/platform/emdrv/nvm3/lib/libnvm3_CM33_gcc.a +++ b/platform/emdrv/nvm3/lib/libnvm3_CM33_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2b9e8852ece38584a14706550567482cdb605c4a4610db41590c0c43334c691d +oid sha256:8b2af3f34a4c301b8c787e3b833562dd802882c00b3a4d8821779722a125c891 size 33522 diff --git a/platform/emdrv/nvm3/lib/libnvm3_CM33_iar.a b/platform/emdrv/nvm3/lib/libnvm3_CM33_iar.a index ede6289cf5..1d2f25529d 100644 --- a/platform/emdrv/nvm3/lib/libnvm3_CM33_iar.a +++ b/platform/emdrv/nvm3/lib/libnvm3_CM33_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1d8c963c2f2c480a6acab07210f15743caec62e3d89132816f0c56d306726d4d +oid sha256:ce1c6cf7a023e467fd166dfdfe7e07ff8e90226cdfa98f1a49af528a5e34dcb0 size 113024 diff --git a/platform/emdrv/nvm3/lib/libnvm3_CM3_gcc.a b/platform/emdrv/nvm3/lib/libnvm3_CM3_gcc.a index 4083e98d58..c32a7829c3 100644 --- a/platform/emdrv/nvm3/lib/libnvm3_CM3_gcc.a +++ b/platform/emdrv/nvm3/lib/libnvm3_CM3_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2abcdfd39a7fe7faae798fffc9d01305e4eb572b703a660ac1ff359f11a1796d +oid sha256:c2f1876b50d8fa44fff98ea3e799bec4a220a92505c0b21f20aaedf30e03e295 size 33486 diff --git a/platform/emdrv/nvm3/lib/libnvm3_CM3_iar.a b/platform/emdrv/nvm3/lib/libnvm3_CM3_iar.a index 198fc5b2e1..c3f1d913b7 100644 --- a/platform/emdrv/nvm3/lib/libnvm3_CM3_iar.a +++ b/platform/emdrv/nvm3/lib/libnvm3_CM3_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2785d376315766d7ff61d8380bea1ff517b5c4290811a3f2490a0c558751dacf +oid sha256:b240fadc83a22381303930fdb26856c72089348386adb563c7dbbda36055b425 size 113062 diff --git a/platform/emdrv/nvm3/lib/libnvm3_CM4_gcc.a b/platform/emdrv/nvm3/lib/libnvm3_CM4_gcc.a index d9459bb6d5..42832e5f81 100644 --- a/platform/emdrv/nvm3/lib/libnvm3_CM4_gcc.a +++ b/platform/emdrv/nvm3/lib/libnvm3_CM4_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d0210b83c941e5881fa3286018e98c31ddf8f3a4a4933ffb35cca1d916540c50 +oid sha256:1f7ab1794c96a2bf24ae13a1af19359002ae5354f66528286a435ef430295122 size 33494 diff --git a/platform/emdrv/nvm3/lib/libnvm3_CM4_iar.a b/platform/emdrv/nvm3/lib/libnvm3_CM4_iar.a index f104411780..544bcd437a 100644 --- a/platform/emdrv/nvm3/lib/libnvm3_CM4_iar.a +++ b/platform/emdrv/nvm3/lib/libnvm3_CM4_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:868b97f24db69aa3a3ee004a47232a4d8bd2ffe68342d3c7aa9415b1cb0fdb80 +oid sha256:e84d26707496690c984a4aea91049e4ae87f72636eebb7f9a0dd1ec964955855 size 113854 diff --git a/platform/emdrv/spidrv/script/spidrv_eusart_validation.lua b/platform/emdrv/spidrv/script/spidrv_eusart_validation.lua index 8d691ae545..54c7ed5947 100644 --- a/platform/emdrv/spidrv/script/spidrv_eusart_validation.lua +++ b/platform/emdrv/spidrv/script/spidrv_eusart_validation.lua @@ -51,27 +51,29 @@ for k, v in pairs(spidrv.instances) do end end else - local hfxo_frequency = tonumber(slc.config("SL_DEVICE_INIT_HFXO_FREQ").value) - if hfxo_frequency / spi_bitrate > max_clkdiv then - validation.warning( - "clkdiv is too high, need to be equal or smaller than 256", - validation.target_for_defines({str_spi_bitrate}), - "Set a higher bitrate or lower the reference clock hfxo", - nil) - elseif hfxo_frequency / spi_bitrate < min_clkdiv then - validation.warning( - "clkdiv is too low, need to be equal or higher than 1", - validation.target_for_defines({str_spi_bitrate}), - "Set a lower bitrate or higher the reference clock hfxo", - nil) + if slc.config("SL_DEVICE_INIT_HFXO_FREQ") ~= nil then + local hfxo_frequency = tonumber(slc.config("SL_DEVICE_INIT_HFXO_FREQ").value) + if hfxo_frequency / spi_bitrate > max_clkdiv then + validation.warning( + "clkdiv is too high, need to be equal or smaller than 256", + validation.target_for_defines({str_spi_bitrate}), + "Set a higher bitrate or lower the reference clock hfxo", + nil) + elseif hfxo_frequency / spi_bitrate < min_clkdiv then + validation.warning( + "clkdiv is too low, need to be equal or higher than 1", + validation.target_for_defines({str_spi_bitrate}), + "Set a lower bitrate or higher the reference clock hfxo", + nil) + end end end - if (config_control.value == "spidrvCsControlAuto") and config_cs == nil then - local msg = instance .. " : SPIDRV is configured to control CS, but no CS pin is selected" - validation.error(msg, - validation.target_for_defines({str_cs_port}), - "CS must be controlled by the application, or a CS pin must be configured", - nil) + if config_control ~=nil and (config_control.value == "spidrvCsControlAuto") and config_cs == nil then + local msg = instance .. " : SPIDRV is configured to control CS, but no CS pin is selected" + validation.error(msg, + validation.target_for_defines({str_cs_port}), + "CS must be controlled by the application, or a CS pin must be configured", + nil) end -end \ No newline at end of file +end diff --git a/platform/emdrv/spidrv/script/spidrv_usart_validation.lua b/platform/emdrv/spidrv/script/spidrv_usart_validation.lua index b3e7ecb007..3b83b53e60 100644 --- a/platform/emdrv/spidrv/script/spidrv_usart_validation.lua +++ b/platform/emdrv/spidrv/script/spidrv_usart_validation.lua @@ -33,52 +33,54 @@ for k, v in pairs(spidrv.instances) do nil) end else - freq = tonumber(slc.config("SL_DEVICE_INIT_HFXO_FREQ").value) - selected_clkdiv = freq / (2 * spi_bitrate) - if selected_clkdiv > max_clkdiv then - validation.warning( - "clkdiv is too high, need to be equal or smaller than 256", - validation.target_for_defines({str_spi_bitrate}), - "Set a higher bitrate or lower the reference clock hfxo", - nil) - elseif selected_clkdiv < min_clkdiv then + if slc.config("SL_DEVICE_INIT_HFXO_FREQ") ~= nil then + freq = tonumber(slc.config("SL_DEVICE_INIT_HFXO_FREQ").value) + selected_clkdiv = freq / (2 * spi_bitrate) + if selected_clkdiv > max_clkdiv then validation.warning( - "clkdiv is too low, need to be equal or higher than 1", - validation.target_for_defines({str_spi_bitrate}), - "Set a lower bitrate or higher the reference clock hfxo", - nil) + "clkdiv is too high, need to be equal or smaller than 256", + validation.target_for_defines({str_spi_bitrate}), + "Set a higher bitrate or lower the reference clock hfxo", + nil) + elseif selected_clkdiv < min_clkdiv then + validation.warning( + "clkdiv is too low, need to be equal or higher than 1", + validation.target_for_defines({str_spi_bitrate}), + "Set a lower bitrate or higher the reference clock hfxo", + nil) + end end end - - if spi_mode == "spidrvMaster" then - if spi_bitrate > (freq / 2) then - validation.warning( - "Bitrate of SPI master mode must be equal or lower than half of the peripheral clock frequency", - validation.target_for_defines({str_spi_bitrate}), - "Set bitrate equal or lower than half of the peripheral clock frequency", - nil) - end - else - if slc.is_provided("device_generic_family_efr32xg22") or slc.is_provided("device_generic_family_efr32xg23") or slc.is_provided("device_generic_family_efr32xg24") then - if spi_bitrate > (freq / 6) then + if freq ~=nil then + if spi_mode == "spidrvMaster" then + if spi_bitrate > (freq / 2) then validation.warning( - "Bitrate of SPI slave mode must be equal or lower than one sixth of the peripheral clock frequency", + "Bitrate of SPI master mode must be equal or lower than half of the peripheral clock frequency", validation.target_for_defines({str_spi_bitrate}), - "Set bitrate equal or lower than one sixth of the peripheral clock frequency", + "Set bitrate equal or lower than half of the peripheral clock frequency", nil) end else - if spi_bitrate > (freq / 8) then - validation.warning( - "Bitrate of SPI slave mode must be equal or lower than one eighth of the peripheral clock frequency", - validation.target_for_defines({str_spi_bitrate}), - "Set bitrate equal or lower than one eighth of the peripheral clock frequency", - nil) + if slc.is_provided("device_generic_family_efr32xg22") or slc.is_provided("device_generic_family_efr32xg23") or slc.is_provided("device_generic_family_efr32xg24") then + if spi_bitrate > (freq / 6) then + validation.warning( + "Bitrate of SPI slave mode must be equal or lower than one sixth of the peripheral clock frequency", + validation.target_for_defines({str_spi_bitrate}), + "Set bitrate equal or lower than one sixth of the peripheral clock frequency", + nil) + end + else + if spi_bitrate > (freq / 8) then + validation.warning( + "Bitrate of SPI slave mode must be equal or lower than one eighth of the peripheral clock frequency", + validation.target_for_defines({str_spi_bitrate}), + "Set bitrate equal or lower than one eighth of the peripheral clock frequency", + nil) + end end end end - - if (config_control.value == "spidrvCsControlAuto") and config_cs == nil then + if config_control ~=nil and (config_control.value == "spidrvCsControlAuto") and config_cs == nil then local msg = instance .. " : SPIDRV is configured to control CS, but no CS pin is selected" validation.error(msg, validation.target_for_defines({str_cs_port}), diff --git a/platform/emlib/src/em_burtc.c b/platform/emlib/src/em_burtc.c index fef386c35e..d79eacfa4b 100644 --- a/platform/emlib/src/em_burtc.c +++ b/platform/emlib/src/em_burtc.c @@ -244,7 +244,9 @@ void BURTC_Enable(bool enable) BURTC_Stop(); BURTC_SyncWait(); /* Wait for the stop to synchronize */ BURTC->EN_CLR = BURTC_EN_EN; -#if defined(_BURTC_EN_DISABLING_MASK) +#if defined(_BURTC_SYNCBUSY_EN_MASK) + regSync(BURTC_SYNCBUSY_EN); +#elif defined(_BURTC_EN_DISABLING_MASK) while (BURTC->EN & _BURTC_EN_DISABLING_MASK) { /* Wait for disabling to finish */ } diff --git a/platform/emlib/src/em_emu.c b/platform/emlib/src/em_emu.c index feadce55f7..feb649ecdd 100644 --- a/platform/emlib/src/em_emu.c +++ b/platform/emlib/src/em_emu.c @@ -35,6 +35,7 @@ #include "sl_assert.h" #include "em_cmu.h" +#include "em_gpio.h" #include "sl_common.h" #include "em_core.h" #include "em_system.h" @@ -1011,6 +1012,12 @@ void EMU_EnterEM2(bool restore) EMU_EM23PresleepHook(); EMU_EFPEM23PresleepHook(); + +#if defined(_GPIO_IF_EM4WU_MASK) + // Clear all EM4WU interrupts before entering sleep + GPIO_IntClear(_GPIO_IF_EM4WU_MASK); +#endif + #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) \ || defined(ERRATA_FIX_EMU_E110_ENABLE) #if defined(ERRATA_FIX_EMU_E110_ENABLE) @@ -1210,6 +1217,11 @@ void EMU_EnterEM3(bool restore) dcdcHsFixLnBlock(); #endif +#if defined(_GPIO_IF_EM4WU_MASK) + // Clear all EM4WU interrupts before entering sleep + GPIO_IntClear(_GPIO_IF_EM4WU_MASK); +#endif + EMU_EM23PresleepHook(); #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) \ || defined(ERRATA_FIX_EMU_E110_ENABLE) @@ -1520,6 +1532,11 @@ void EMU_EnterEM4(void) EMU_EM4PresleepHook(); EMU_EFPEM4PresleepHook(); +#if defined(_GPIO_IF_EM4WU_MASK) + // Clear all EM4WU interrupts before entering sleep + GPIO_IntClear(_GPIO_IF_EM4WU_MASK); +#endif + for (i = 0; i < 4; i++) { #if defined(_EMU_EM4CTRL_EM4ENTRY_SHIFT) EMU->EM4CTRL = em4seq2; diff --git a/platform/hwconf_data/hwconfig.hwdata b/platform/hwconf_data/hwconfig.hwdata index 6044cce332..26aff8e7fc 100644 --- a/platform/hwconf_data/hwconfig.hwdata +++ b/platform/hwconf_data/hwconfig.hwdata @@ -1,267 +1,267 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/platform/micrium_os/micrium-tcpx.properties b/platform/micrium_os/micrium-tcpx.properties index db20f5e2ee..ad4f5c0fd2 100644 --- a/platform/micrium_os/micrium-tcpx.properties +++ b/platform/micrium_os/micrium-tcpx.properties @@ -1,5 +1,5 @@ -version=5.15.2 +version=5.15.3 dependantSdkVersion=4.3.0 label=Micrium OS Network description=SL-MOS-TCPX-PKG000-P-SPL diff --git a/platform/micrium_os/net/source/http/server/http_server_req.c b/platform/micrium_os/net/source/http/server/http_server_req.c index 6e7b438cda..aaeeab5e50 100644 --- a/platform/micrium_os/net/source/http/server/http_server_req.c +++ b/platform/micrium_os/net/source/http/server/http_server_req.c @@ -1816,6 +1816,9 @@ static CPU_CHAR *HTTPsReq_HdrParseValGet(CPU_CHAR *p_field, len = (p_field_end - p_val); p_val = Str_Char_N(p_val, len, ASCII_CHAR_COLON); // Field val located after ':' (see Note #1a). + if (p_val == DEF_NULL) { + return (DEF_NULL); + } p_val++; len = (p_field_end - p_val); diff --git a/platform/radio/mac/lower-mac.h b/platform/radio/mac/lower-mac.h index 45054b3c3d..8876f00b37 100644 --- a/platform/radio/mac/lower-mac.h +++ b/platform/radio/mac/lower-mac.h @@ -60,8 +60,15 @@ enum extern LowerMacState sli_802154mac_lower_mac_state; #ifdef HIGH_DATARATE_PHY -#define PHY_HEADER_SIZE_ADJUST_2MBPS 3u +#define PHY_HEADER_SIZE_ADJUST_2MBPS 4u #define HIGH_DATARATE_PHY_PACKET_START_INDEX 1u +// 802.15.4 2-byte PHR +// Spec: [ 0 | 1-2 | 3 | 4 | 5-15 ] +// [ Mode Switch | Reserved | FCS Type | Whitening | Frame Length ] +// RBIT: [ 15 | 14-13 | 12 | 11 | 10-0 ] +#define PHR2BYTE_REV_LENGTH_MASK (0x07FFu) // <10:0> 11-bit length field +#define PHR2BYTE_REV_WHITEN_MASK (0x0800u) // <11> 0=unwhitened, 1=whitened +#define PHR2BYTE_REV_CRC_2_MASK (0x1000u) // <12> 0=4-byte CRC, 1=2-byte CRC #endif //HIGH_DATARATE_PHY // MAC TX Options Bitmask #ifdef DOXYGEN_SHOULD_SKIP_THIS diff --git a/platform/radio/rail_lib/apps/component/rail_test_core.slcc b/platform/radio/rail_lib/apps/component/rail_test_core.slcc index 269744b39c..f977baa156 100644 --- a/platform/radio/rail_lib/apps/component/rail_test_core.slcc +++ b/platform/radio/rail_lib/apps/component/rail_test_core.slcc @@ -618,6 +618,15 @@ template_contribution: - type: uint16 help: "lengthBytes: range 64-RX_BUFFER_SIZE" + - name: cli_command + value: + name: setTxFifo + handler: setTxFifo + help: "Set the transmit buffer length." + argument: + - type: uint16 + help: "lengthBytes: range 64-TX_BUFFER_SIZE, 0 for default size" + - name: cli_command value: name: setTxFifoThreshold diff --git a/platform/radio/rail_lib/apps/railtest/app_ci/154_rx_ci.c b/platform/radio/rail_lib/apps/railtest/app_ci/154_rx_ci.c index b3e46dfec3..0bbdc2b7d5 100644 --- a/platform/radio/rail_lib/apps/railtest/app_ci/154_rx_ci.c +++ b/platform/radio/rail_lib/apps/railtest/app_ci/154_rx_ci.c @@ -238,7 +238,7 @@ static IEEE802154_2p4GHzConfig_t ieee802154Configs[] = { { "IEEE802154_2P4_MODE_ANT_DIV_COEX", &RAIL_IEEE802154_Config2p4GHzRadioAntDivCoex }, { "IEEE802154_2P4_MODE_FEM", &RAIL_IEEE802154_Config2p4GHzRadioFem }, { "IEEE802154_2P4_MODE_ANT_DIV_FEM", &RAIL_IEEE802154_Config2p4GHzRadioAntDivFem }, - { "IEEE802154_2P4_MODE_COEX_FEM", &RAIL_IEEE802154_Config2p4GHzRadioAntDivCoex }, + { "IEEE802154_2P4_MODE_COEX_FEM", &RAIL_IEEE802154_Config2p4GHzRadioCoexFem }, { "IEEE802154_2P4_MODE_ANT_DIV_COEX_FEM", &RAIL_IEEE802154_Config2p4GHzRadioAntDivCoexFem }, #if RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY { "IEEE802154_2P4_MODE_CUSTOM1", &RAIL_IEEE802154_Config2p4GHzRadioCustom1 }, diff --git a/platform/radio/rail_lib/apps/railtest/app_ci/packet_ci.c b/platform/radio/rail_lib/apps/railtest/app_ci/packet_ci.c index 6cca17b43a..b4db7e4ba1 100644 --- a/platform/radio/rail_lib/apps/railtest/app_ci/packet_ci.c +++ b/platform/radio/rail_lib/apps/railtest/app_ci/packet_ci.c @@ -366,6 +366,20 @@ RAIL_Status_t RAILCb_SetupRxFifo(RAIL_Handle_t railHandle) return status; } +void setTxFifo(sl_cli_command_arg_t *args) +{ + uint16_t reqFifoBytes = sl_cli_get_argument_uint16(args, 0); + uint16_t actFifoBytes = configureTxFifo(reqFifoBytes); + if (reqFifoBytes == 0U) { + reqFifoBytes = actFifoBytes; + } + responsePrint(sl_cli_get_command_string(args, 0), + "TxFifoBytes:%u,Success:%s", + actFifoBytes, + (((actFifoBytes > 0U) && (actFifoBytes == reqFifoBytes)) + ? "True" : "False")); +} + void fifoModeTestOptions(sl_cli_command_arg_t *args) { char *outputStr[] = { "Disabled", "Enabled" }; diff --git a/platform/radio/rail_lib/apps/railtest/app_common.h b/platform/radio/rail_lib/apps/railtest/app_common.h index 59e59e159e..9e1d596fa8 100644 --- a/platform/radio/rail_lib/apps/railtest/app_common.h +++ b/platform/radio/rail_lib/apps/railtest/app_common.h @@ -615,7 +615,7 @@ bool inAppMode(AppMode_t appMode, char *command); bool inRadioState(RAIL_RadioState_t state, char *command); bool parseTimeModeFromString(char *str, RAIL_TimeMode_t *mode); const char *configuredRxAntenna(RAIL_RxOptions_t rxOptions); -RAIL_Status_t configureTxFifo(void); +uint16_t configureTxFifo(uint16_t fifoBytes); void updateStats(int32_t newValue, Stats_t *stats); void rfSensedCheck(void); diff --git a/platform/radio/rail_lib/apps/railtest/app_main.c b/platform/radio/rail_lib/apps/railtest/app_main.c index e37e0ef4eb..271a5763fb 100644 --- a/platform/radio/rail_lib/apps/railtest/app_main.c +++ b/platform/radio/rail_lib/apps/railtest/app_main.c @@ -367,7 +367,7 @@ void sl_rail_test_internal_app_init(void) getPti(NULL); // Set TX FIFO, and verify that the size is correct - if (configureTxFifo() != RAIL_STATUS_NO_ERROR) { + if (configureTxFifo(SL_RAIL_TEST_TX_BUFFER_SIZE) != SL_RAIL_TEST_TX_BUFFER_SIZE) { while (1) ; } @@ -1547,11 +1547,13 @@ char *handleToString(RAIL_Handle_t railHandle) return "r";//for RAILtest vs MP configuration } -RAIL_Status_t configureTxFifo(void) +uint16_t configureTxFifo(uint16_t fifoBytes) { - uint16_t fifoSize = RAIL_SetTxFifo(railHandle, txFifo.fifo, 0, SL_RAIL_TEST_TX_BUFFER_SIZE); - if (fifoSize != SL_RAIL_TEST_TX_BUFFER_SIZE) { - return RAIL_STATUS_INVALID_PARAMETER; + if (fifoBytes == 0U) { + fifoBytes = SL_RAIL_TEST_TX_BUFFER_SIZE; } - return RAIL_STATUS_NO_ERROR; + if (fifoBytes > SL_RAIL_TEST_TX_BUFFER_SIZE) { + return 0U; + } + return RAIL_SetTxFifo(railHandle, txFifo.fifo, 0, fifoBytes); } diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111a256v2_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111a256v2_gcc.a index ba56a39e31..07fc2cd184 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111a256v2_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111a256v2_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:01f817f254f3b9c042850c3a407d28d247760729d69505d372b8b6464dcc4e58 +oid sha256:6959910796d4ac442d5994fba364d970feea344491051611ac6f183cae7bb2d4 size 57588 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111a256v2_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111a256v2_iar.a index 39ade7480b..8e7a5bf11c 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111a256v2_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111a256v2_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:718f6c9120c5fd0669a6dabe453452e66a551a6d7f6fab8b4d0cd2af42b217d5 +oid sha256:6407df2660c74f9348777d49e84923654e665ead10fcdc0bd3ea8341b68c7d56 size 39984 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111e256v2_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111e256v2_gcc.a index b997bd153b..017d02be47 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111e256v2_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111e256v2_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8c75af99f56e4aa23b8018478035d90727105a4c1393d862195529dded2b6b33 +oid sha256:bb87e8366dc72f5ef04e24e1c25166e8d7ef03719410b1d9a6d89c84b50e73dd size 57588 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111e256v2_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111e256v2_iar.a index ee90d4696d..2362ada2ad 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111e256v2_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111e256v2_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:18517e842b73d1c0c398b7c08b11439f64bbc44de568178b122d0f4acb2d84db +oid sha256:32017fa9fff5ba911ec7de2ec87bc57c7e557a6fad60d43d2b9e9cbfe742c4de size 39984 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm113a256v2_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm113a256v2_gcc.a index 762db9a4d1..08e3ce3721 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm113a256v2_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm113a256v2_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4b643336579510cd2dba39c3839b2629724bd5f6fbe705c488e75a711ae15b63 +oid sha256:34890ca6edb3a39b430f7a7b359c13336bfce3fd84223b849449620876fe4c0a size 57588 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm113a256v2_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm113a256v2_iar.a index e024486e4b..68b3ff53c2 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm113a256v2_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm113a256v2_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:851d39dd431052166b5e45af949a79e5e1e10223745dc34631b17f09fa85ad5c +oid sha256:9501a9fcdcfe2150436d3d5adf8f622ac727bc72ff2f25c3abfd68c87b088868 size 39984 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s12f256ga_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s12f256ga_gcc.a index 9e277143b6..d64c3b89c4 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s12f256ga_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s12f256ga_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e2e33e080d519e8712eaf8695ca0c3dafebd88a21f6b31449ebe41d848eefc3c +oid sha256:620d3c77aa0d66afe6bf438a139b8490b2abae11833aca1bb45543de0968499b size 57596 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s12f256ga_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s12f256ga_iar.a index 8b38c8348b..078c2693ef 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s12f256ga_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s12f256ga_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid 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100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s22f256ga_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s22f256ga_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f77f67d774ad393df48f8fbc879ccbcf7bdc58133cddbf03af83efce8c6652cf +oid sha256:e1e1ae765de6d24f0dc14ee5cf91ba95e00c1322eeb8d74e6571fe022502e117 size 40010 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121a256v2_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121a256v2_gcc.a index 0045840c64..c74532f5ef 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121a256v2_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121a256v2_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5eea3962589111a4f1d9c192b89471e1d9cb401db86b3e455fd87542c0ea20c2 +oid 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b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:368675414c04cc6e14a6f4bcfa5fdff1f7085357ac950ceffc7db3cea91f521a -size 1484048 +oid sha256:03445b30c480fb3ea345e10dbcdd872c3cdb8071b478de8341939761e2e32fe9 +size 1484156 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_iar_release.a index 6224a170cb..f3601ceebb 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1990367f2e77e1ff3581a9a06a279c0d4653edfa01e0e6abebc964bfd1ab4c6a -size 2120724 +oid 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b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c4fb23c03a098f64f55176defaf0f8b4c0223c3be664de163fa21a0102c57d37 -size 1540240 +oid sha256:ab1793ad7f25f94f5b30966adbe2dbd3f129e5bafec61af78b655986a6e4853c +size 1540332 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_iar_release.a index 93e4f0e2f8..69c12aa2f5 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7283420f966cf3f8cf10ba33f989896b281b1ebfeee2c858ceb30aa3f543e58f -size 2223488 +oid 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b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8dc2ba4a8cd669a9daeb01b4ee15bea187166de656186c8eb6eb19592a229d32 -size 1481932 +oid sha256:c48995192587f2e945625fe11df9fcb34d1908bc26330812fb339306fbde1f08 +size 1482036 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_iar_release.a index 2076815263..1d86a79a1f 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a093f4e31038b7b2437b63dae72b193ddd247bbe7e795a9e62c51abf281355bb -size 2115468 +oid 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b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg28_iar_release.a index 9e85856488..9b6a1337bc 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg28_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg28_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7d1c2bf34e4ab3ff79d5e010ed52f29a9e487a2164a18298313390121b7a8de3 -size 2232386 +oid sha256:8e24bb7b42c3ebcbb1bc820d50cc8e864fe30266158ec3aeb7681fafc2255b8b +size 2233262 diff --git a/platform/radio/rail_lib/autogen/ver_def.h b/platform/radio/rail_lib/autogen/ver_def.h index 0d8064918b..732e6d0058 100644 --- a/platform/radio/rail_lib/autogen/ver_def.h +++ b/platform/radio/rail_lib/autogen/ver_def.h @@ -42,10 +42,10 @@ typedef struct // LOCAL_COMMITS_FLAG << 1 | DIRTY_FLAG) } FW_GIT_INFO_t; -#define GIT_INFO_SHORT_HASH (0x5b562c1aUL) +#define GIT_INFO_SHORT_HASH (0xc2af6a8aUL) #define GIT_INFO_TAG_MAJOR (2) #define GIT_INFO_TAG_MINOR (16) -#define GIT_INFO_TAG_REV (1) +#define GIT_INFO_TAG_REV (2) #define GIT_INFO_TAG_BUILD (0) #define GIT_INFO_DETAILS (0x10) diff --git a/platform/radio/rail_lib/common/rail.h b/platform/radio/rail_lib/common/rail.h index c46eefbd6a..d3caa35c7b 100644 --- a/platform/radio/rail_lib/common/rail.h +++ b/platform/radio/rail_lib/common/rail.h @@ -1544,13 +1544,15 @@ RAIL_Status_t RAIL_Wake(RAIL_Time_t elapsedTime); * * @return Status code indicating success of the function call. * - * @note Call this function only when the application is built - * and initialized with Power Manager plugin. - * RAIL will perform timer synchronization, upon transitioning from EM2 or lower - * to EM1 or higher energy mode or vice-versa, in the Power Manager EM - * transition callback. Since EM transition callbacks are not called in a - * deterministic order, it is suggested to not call any RAIL time dependent APIs - * in an EM transition callback. + * @note This function must be called only when the application is built + * and initialized with Power Manager plugin and when the radio is idle. + * RAIL will perform timer synchronization, upon transitioning from EM2 or + * lower to EM1 or higher energy mode or vice-versa, in the Power Manager EM + * transition callback. + * + * @warning Since EM transition callbacks are not called in a deterministic + * order, it is suggested to not call any RAIL time dependent APIs + * in an EM transition callback. */ RAIL_Status_t RAIL_InitPowerManager(void); diff --git a/platform/radio/rail_lib/plugin/component/rail_util_power_manager_init.slcc b/platform/radio/rail_lib/plugin/component/rail_util_power_manager_init.slcc index df7053d095..4d6d836635 100644 --- a/platform/radio/rail_lib/plugin/component/rail_util_power_manager_init.slcc +++ b/platform/radio/rail_lib/plugin/component/rail_util_power_manager_init.slcc @@ -25,4 +25,4 @@ template_contribution: event: stack_init include: sl_rail_util_power_manager_init.h handler: sl_rail_util_power_manager_init - priority: 9999 + priority: -9010 diff --git a/platform/radio/rail_lib/plugin/component/rail_util_sequencer.slcc b/platform/radio/rail_lib/plugin/component/rail_util_sequencer.slcc index 76b896469c..0eab120c05 100644 --- a/platform/radio/rail_lib/plugin/component/rail_util_sequencer.slcc +++ b/platform/radio/rail_lib/plugin/component/rail_util_sequencer.slcc @@ -20,14 +20,8 @@ config_file: - path: platform/radio/rail_lib/plugin/rail_util_sequencer/config/efr32xg24/pa_20dbm/sl_rail_util_sequencer_config.h condition: [device_sdid_215, device_pa_20dbm] file_id: rail_util_sequencer_config - - path: platform/radio/rail_lib/plugin/rail_util_sequencer/config/efr32xg13/seq_1_zwave/sl_rail_util_sequencer_config.h - condition: - - device_sdid_89 - unless: - - rail_util_ieee802154_high_speed_phy - file_id: rail_util_sequencer_config - - path: platform/radio/rail_lib/plugin/rail_util_sequencer/config/efr32xg13/seq_2_high_bw_phy/sl_rail_util_sequencer_config.h - condition: [device_sdid_89, rail_util_ieee802154_high_speed_phy] + - path: platform/radio/rail_lib/plugin/rail_util_sequencer/config/efr32xg13/sl_rail_util_sequencer_config.h + condition: [device_sdid_89] file_id: rail_util_sequencer_config source: - path: platform/radio/rail_lib/plugin/rail_util_sequencer/sl_rail_util_sequencer.c diff --git a/platform/radio/rail_lib/plugin/rail_util_sequencer/config/efr32xg13/seq_2_high_bw_phy/sl_rail_util_sequencer_config.h b/platform/radio/rail_lib/plugin/rail_util_sequencer/config/efr32xg13/sl_rail_util_sequencer_config.h similarity index 80% rename from platform/radio/rail_lib/plugin/rail_util_sequencer/config/efr32xg13/seq_2_high_bw_phy/sl_rail_util_sequencer_config.h rename to platform/radio/rail_lib/plugin/rail_util_sequencer/config/efr32xg13/sl_rail_util_sequencer_config.h index c4c54ac2cd..49140bac91 100644 --- a/platform/radio/rail_lib/plugin/rail_util_sequencer/config/efr32xg13/seq_2_high_bw_phy/sl_rail_util_sequencer_config.h +++ b/platform/radio/rail_lib/plugin/rail_util_sequencer/config/efr32xg13/sl_rail_util_sequencer_config.h @@ -32,6 +32,13 @@ #define SL_RAIL_UTIL_SEQUENCER_H #include "rail.h" +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_RAIL_UTIL_IEEE802154_HIGH_SPEED_PHY_PRESENT) +#include "sl_rail_util_ieee802154_high_speed_phy_config.h" +#endif #ifdef __cplusplus extern "C" { @@ -39,7 +46,12 @@ extern "C" { #define SL_RAIL_UTIL_SEQUENCER_RUNTIME_IMAGE_SELECTION 0 +#if (defined(SL_CATALOG_RAIL_UTIL_IEEE802154_HIGH_SPEED_PHY_PRESENT) \ + && (SL_RAIL_UTIL_IEEE802154_2P4_2MBPS_PHY_ENABLED == 1)) #define SL_RAIL_UTIL_SEQUENCER_IMAGE RAIL_SEQ_IMAGE_HIGH_BW_PHY +#else +#define SL_RAIL_UTIL_SEQUENCER_IMAGE RAIL_SEQ_IMAGE_ZWAVE +#endif #ifdef __cplusplus } diff --git a/platform/release-highlights.txt b/platform/release-highlights.txt old mode 100644 new mode 100755 index 8797ccb833..5a7a1117c2 Binary files a/platform/release-highlights.txt and b/platform/release-highlights.txt differ diff --git a/platform/security/component/psa_crypto.slcc b/platform/security/component/psa_crypto.slcc index 30e04e7f5f..135f023f95 100644 --- a/platform/security/component/psa_crypto.slcc +++ b/platform/security/component/psa_crypto.slcc @@ -60,7 +60,6 @@ requires: condition: [device_series_2] - name: psa_crypto_common - name: sl_si91x_psa_crypto - from: wiseconnect3_sdk condition: [device_si91x] # Inclusion of source and config components depends on which TZ state we are diff --git a/platform/security/component/psa_crypto_ccm.slcc b/platform/security/component/psa_crypto_ccm.slcc index 2df796bbb3..41323d8dd0 100644 --- a/platform/security/component/psa_crypto_ccm.slcc +++ b/platform/security/component/psa_crypto_ccm.slcc @@ -13,10 +13,8 @@ requires: - name: mbedtls_ccm condition: [device_series_0] - name: sl_si91x_psa_aead - from: wiseconnect3_sdk condition: [device_si91x] - name: sl_si91x_psa_wrap - from: wiseconnect3_sdk condition: [device_si91x] template_contribution: - name: psa_crypto_config diff --git a/platform/security/component/psa_crypto_chachapoly.slcc b/platform/security/component/psa_crypto_chachapoly.slcc index 9bdfe1c06d..b5f57a8955 100644 --- a/platform/security/component/psa_crypto_chachapoly.slcc +++ b/platform/security/component/psa_crypto_chachapoly.slcc @@ -26,10 +26,8 @@ requires: - name: mbedtls_chachapoly condition: [device_security_rot] - name: sl_si91x_psa_aead - from: wiseconnect3_sdk condition: [device_si91x] - name: sl_si91x_psa_wrap - from: wiseconnect3_sdk condition: [device_si91x] template_contribution: - name: psa_crypto_config diff --git a/platform/security/component/psa_crypto_cipher_cbc.slcc b/platform/security/component/psa_crypto_cipher_cbc.slcc index 8602164d13..daa182082f 100644 --- a/platform/security/component/psa_crypto_cipher_cbc.slcc +++ b/platform/security/component/psa_crypto_cipher_cbc.slcc @@ -13,7 +13,6 @@ requires: - name: mbedtls_cipher_cbc condition: [device_series_0] - name: sl_si91x_psa_aes - from: wiseconnect3_sdk condition: [device_si91x] template_contribution: - name: psa_crypto_config diff --git a/platform/security/component/psa_crypto_cipher_ctr.slcc b/platform/security/component/psa_crypto_cipher_ctr.slcc index eac7fbde22..7a6d3cdf8a 100644 --- a/platform/security/component/psa_crypto_cipher_ctr.slcc +++ b/platform/security/component/psa_crypto_cipher_ctr.slcc @@ -12,7 +12,6 @@ requires: - name: mbedtls_cipher_ctr condition: [device_series_0] - name: sl_si91x_psa_aes - from: wiseconnect3_sdk condition: [device_si91x] template_contribution: - name: psa_crypto_config diff --git a/platform/security/component/psa_crypto_cipher_ecb.slcc b/platform/security/component/psa_crypto_cipher_ecb.slcc index 901a1eee85..fd2e626003 100644 --- a/platform/security/component/psa_crypto_cipher_ecb.slcc +++ b/platform/security/component/psa_crypto_cipher_ecb.slcc @@ -13,7 +13,6 @@ requires: - name: mbedtls_aes condition: [device_series_0] - name: sl_si91x_psa_aes - from: wiseconnect3_sdk condition: [device_si91x] template_contribution: - name: psa_crypto_config diff --git a/platform/security/component/psa_crypto_cmac.slcc b/platform/security/component/psa_crypto_cmac.slcc index 2c47175363..9d8db451c7 100644 --- a/platform/security/component/psa_crypto_cmac.slcc +++ b/platform/security/component/psa_crypto_cmac.slcc @@ -12,6 +12,8 @@ requires: - name: psa_crypto_aes - name: mbedtls_cmac condition: [device_series_0] + - name: sl_si91x_psa_mac + condition: [device_si91x] template_contribution: - name: psa_crypto_config value: PSA_WANT_ALG_CMAC 1 diff --git a/platform/security/component/psa_crypto_ecc.slcc b/platform/security/component/psa_crypto_ecc.slcc index 5510f10788..6fbdbe2421 100644 --- a/platform/security/component/psa_crypto_ecc.slcc +++ b/platform/security/component/psa_crypto_ecc.slcc @@ -27,8 +27,7 @@ requires: condition: [device_series_0] - name: mbedtls_ecc condition: [device_series_1] - - name: sl_si91x_psa_ecdh - from: wiseconnect3_sdk + - name: mbedtls_ecc condition: [device_si91x] recommends: diff --git a/platform/security/component/psa_crypto_ecc_secp192r1.slcc b/platform/security/component/psa_crypto_ecc_secp192r1.slcc index 0351c9e64c..c3df13b6e2 100644 --- a/platform/security/component/psa_crypto_ecc_secp192r1.slcc +++ b/platform/security/component/psa_crypto_ecc_secp192r1.slcc @@ -16,6 +16,8 @@ requires: condition: [device_series_0] - name: mbedtls_ecc_secp192r1 condition: [device_series_1] + - name: mbedtls_ecc_secp192r1 + condition: [device_si91x] template_contribution: - name: psa_crypto_config value: PSA_WANT_ECC_SECP_R1_192 1 diff --git a/platform/security/component/psa_crypto_ecc_secp224r1.slcc b/platform/security/component/psa_crypto_ecc_secp224r1.slcc index 81ce99654c..97f07f5e67 100644 --- a/platform/security/component/psa_crypto_ecc_secp224r1.slcc +++ b/platform/security/component/psa_crypto_ecc_secp224r1.slcc @@ -18,6 +18,8 @@ requires: condition: [device_series_1] - name: mbedtls_ecc_secp224r1 condition: [device_sdid_200] + - name: mbedtls_ecc_secp224r1 + condition: [device_si91x] template_contribution: - name: psa_crypto_config value: PSA_WANT_ECC_SECP_R1_224 1 diff --git a/platform/security/component/psa_crypto_ecc_secp256r1.slcc b/platform/security/component/psa_crypto_ecc_secp256r1.slcc index f3b4f08f65..8c36639a14 100644 --- a/platform/security/component/psa_crypto_ecc_secp256r1.slcc +++ b/platform/security/component/psa_crypto_ecc_secp256r1.slcc @@ -16,6 +16,8 @@ requires: condition: [device_series_0] - name: mbedtls_ecc_secp256r1 condition: [device_series_1] + - name: mbedtls_ecc_secp256r1 + condition: [device_si91x] template_contribution: - name: psa_crypto_config value: PSA_WANT_ECC_SECP_R1_256 1 diff --git a/platform/security/component/psa_crypto_ecdh.slcc b/platform/security/component/psa_crypto_ecdh.slcc index ef58c4bdda..c3e757cf29 100644 --- a/platform/security/component/psa_crypto_ecdh.slcc +++ b/platform/security/component/psa_crypto_ecdh.slcc @@ -13,6 +13,14 @@ requires: condition: [device_series_0] - name: mbedtls_ecdh condition: [device_series_1] + - name: sl_si91x_psa_ecdh + condition: [device_si91x] + - name: mbedtls_ecdh + condition: [device_si91x, psa_crypto_ecc_secp224r1] + - name: mbedtls_ecdh + condition: [device_si91x, psa_crypto_ecc_secp384r1] + - name: mbedtls_ecdh + condition: [device_si91x, psa_crypto_ecc_secp521r1] # EFR32xG21 (SDID:200) does not support acceleration of the SECP224R1 curve. - name: mbedtls_ecdh condition: [device_sdid_200, psa_crypto_ecc_secp224r1] diff --git a/platform/security/component/psa_crypto_ecdsa.slcc b/platform/security/component/psa_crypto_ecdsa.slcc index d5305e7ff0..b14beab210 100644 --- a/platform/security/component/psa_crypto_ecdsa.slcc +++ b/platform/security/component/psa_crypto_ecdsa.slcc @@ -17,6 +17,16 @@ requires: condition: [device_series_0] - name: mbedtls_ecdsa condition: [device_series_1] + - name: sl_si91x_psa_ecdsa + condition: [device_si91x] + - name: sl_si91x_psa_wrap + condition: [device_si91x] + - name: mbedtls_ecdsa + condition: [device_si91x, psa_crypto_ecc_secp192r1] + - name: mbedtls_ecdsa + condition: [device_si91x, psa_crypto_ecc_secp384r1] + - name: mbedtls_ecdsa + condition: [device_si91x, psa_crypto_ecc_secp521r1] # EFR32xG21 (SDID:200) does not support acceleration of the SECP224R1 curve. - name: mbedtls_ecdsa condition: [device_sdid_200, psa_crypto_ecc_secp224r1] diff --git a/platform/security/component/psa_crypto_gcm.slcc b/platform/security/component/psa_crypto_gcm.slcc index a8a7941772..96999f1dac 100644 --- a/platform/security/component/psa_crypto_gcm.slcc +++ b/platform/security/component/psa_crypto_gcm.slcc @@ -17,10 +17,8 @@ requires: - name: mbedtls_gcm condition: [device_series_0] - name: sl_si91x_psa_aead - from: wiseconnect3_sdk condition: [device_si91x] - name: sl_si91x_psa_wrap - from: wiseconnect3_sdk condition: [device_si91x] template_contribution: - name: psa_crypto_config diff --git a/platform/security/component/psa_crypto_hash.slcc b/platform/security/component/psa_crypto_hash.slcc index a55f585ad3..d125022125 100644 --- a/platform/security/component/psa_crypto_hash.slcc +++ b/platform/security/component/psa_crypto_hash.slcc @@ -15,7 +15,6 @@ requires: - name: psa_crypto - name: psa_hash_function - name: sl_si91x_psa_sha - from: wiseconnect3_sdk condition: [device_si91x] recommends: diff --git a/platform/security/component/psa_crypto_hmac.slcc b/platform/security/component/psa_crypto_hmac.slcc index e8e5f24db5..2f3a3276b4 100644 --- a/platform/security/component/psa_crypto_hmac.slcc +++ b/platform/security/component/psa_crypto_hmac.slcc @@ -14,8 +14,7 @@ requires: condition: [device_series_0] - name: mbedtls_hmac condition: [device_series_1] - - name: sl_si91x_psa_hmac - from: wiseconnect3_sdk + - name: sl_si91x_psa_mac condition: [device_si91x] template_contribution: - name: psa_crypto_config diff --git a/platform/security/component/psa_crypto_trng.slcc b/platform/security/component/psa_crypto_trng.slcc index 1bb2e81382..712a102f1e 100644 --- a/platform/security/component/psa_crypto_trng.slcc +++ b/platform/security/component/psa_crypto_trng.slcc @@ -53,7 +53,6 @@ requires: - name: psa_driver condition: [trustzone_secure] - name: sl_si91x_psa_trng - from: wiseconnect3_sdk condition: [device_si91x] - name: emlib_cmu condition: [device_has_trng] diff --git a/platform/security/component/psa_driver.slcc b/platform/security/component/psa_driver.slcc index 609b47a38e..a40b5742ab 100644 --- a/platform/security/component/psa_driver.slcc +++ b/platform/security/component/psa_driver.slcc @@ -24,6 +24,10 @@ requires: # (trustzone_unaware) should be used. - name: trustzone_security_state + # Can be used to check whether or not certain platform components are included + # in the end-project. + - name: component_catalog + recommends: # Assume that projects are TZ unaware unless a state is explicitly included. - id: trustzone_unaware diff --git a/platform/security/sl_component/sl_mbedtls_support/config/sli_psa_acceleration.h b/platform/security/sl_component/sl_mbedtls_support/config/sli_psa_acceleration.h index 0f3559b9ca..7f95ee5f7d 100644 --- a/platform/security/sl_component/sl_mbedtls_support/config/sli_psa_acceleration.h +++ b/platform/security/sl_component/sl_mbedtls_support/config/sli_psa_acceleration.h @@ -74,9 +74,7 @@ // ------------------------------------- // MAC -#if !defined(SLI_MBEDTLS_DEVICE_SI91X) - #define MBEDTLS_PSA_ACCEL_ALG_CMAC -#endif +#define MBEDTLS_PSA_ACCEL_ALG_CMAC #if defined(SLI_MBEDTLS_DEVICE_S2) || defined(SLI_MBEDTLS_DEVICE_SI91X) #define MBEDTLS_PSA_ACCEL_ALG_HMAC @@ -100,21 +98,21 @@ #define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_224 #endif -#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) || defined(SLI_MBEDTLS_DEVICE_SI91X) +#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) #define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_384 #define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_521 #endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) || defined(SLI_MBEDTLS_DEVICE_SI91X) +#if defined(SLI_MBEDTLS_DEVICE_VSE) #define MBEDTLS_PSA_ACCEL_ECC_SECP_K1_256 #endif #if defined(SLI_MBEDTLS_DEVICE_HSE_V1) && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) \ - || defined(SLI_MBEDTLS_DEVICE_HSE_V2) || defined(SLI_MBEDTLS_DEVICE_SI91X) + || defined(SLI_MBEDTLS_DEVICE_HSE_V2) #define MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_255 #endif -#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) || defined(SLI_MBEDTLS_DEVICE_SI91X) +#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) #define MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_448 #endif @@ -128,7 +126,7 @@ // ------------------------------------- // Signature -#if defined(SLI_MBEDTLS_DEVICE_S2) +#if defined(SLI_MBEDTLS_DEVICE_S2) || defined(SLI_MBEDTLS_DEVICE_SI91X) #define MBEDTLS_PSA_ACCEL_ALG_ECDSA #endif diff --git a/platform/security/sl_component/sl_mbedtls_support/config/template/psa_crypto_config.h b/platform/security/sl_component/sl_mbedtls_support/config/template/psa_crypto_config.h index 7d9144b3bb..20703b41d2 100644 --- a/platform/security/sl_component/sl_mbedtls_support/config/template/psa_crypto_config.h +++ b/platform/security/sl_component/sl_mbedtls_support/config/template/psa_crypto_config.h @@ -110,6 +110,42 @@ // +// Power optimization configuration + +// Store already-generated random bytes before putting the device to sleep +// Using the hardware TRNG (for example through psa_generate_random()) will +// consume a non-negligible amount of power. A start-up routine must pass +// and a relatively large minimum amount of random bytes will be generated. +// Use cases where the device is frequently entering EM2/EM3 and thereafter +// consumes a small amount of data from the TRNG may benefit from buffering +// the existing random bytes before putting the device to sleep. These +// buffered bytes are then consumed until exhaustion before the TRNG needs +// to be initialized and used again. +// +// NOTE: this configuration option is only applicable for devices with a +// Virtual Secure Engine (VSE), and requires the 'Power Manager' component +// to be included in the project. +// +// Default: 0 +#define SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP (0) + +// Number of random words to buffer before putting the device to sleep <1-63> +// This option can be used to decrease the amount of random words that +// (if enabled) are buffered before the device enters EM2/EM3. Lowering this +// number will result in less static RAM usage, but also means that the TRNG +// potentially has to be initialized more times--leading to increased power +// consumption. By default this option in configured to buffer as much TRNG +// data as possible (limited by the depth of the TRNG FIFO). +// +// NOTE: this configuration option is only applicable when +// SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP is enabled. +// +// Default: 63 +#define SL_VSE_MAX_TRNG_WORDS_BUFFERED_DURING_SLEEP (63) +// + +// + // <<< end of configuration section >>> // ----------------------------------------------------------------------------- diff --git a/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_driver_trng.c b/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_driver_trng.c index eea804c723..472597719c 100644 --- a/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_driver_trng.c +++ b/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_driver_trng.c @@ -48,6 +48,15 @@ #include "sl_assert.h" #include "em_device.h" +#if (SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP) + #include "sl_component_catalog.h" + #if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + #include "sl_power_manager.h" + #else + #error "The 'Power Manager' component must be included in the project" + #endif // SL_CATALOG_POWER_MANAGER_PRESENT +#endif // SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + //------------------------------------------------------------------------------ // Defines @@ -58,32 +67,128 @@ // seriously bad state and cannot be initialized properly. #define MAX_INITIALIZATION_ATTEMPTS (4) +// Magic word written to the random data buffer in RAM. Used as a basic sanity +// check to make sure that the data actually has been retained during sleep. +#define BUFFERED_RANDOMNESS_MAGIC_WORD (0xF55E0830) + +//------------------------------------------------------------------------------ +// Forward Declarations + +static void cryptoacc_trng_get_random_wrapper(void *unused_state, + block_t output); + +#if SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + +static void store_trng_fifo_data(sl_power_manager_em_t from, + sl_power_manager_em_t to); + +#endif // SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + //------------------------------------------------------------------------------ -// Constants +// Static Constants static const block_t trng_fifo_block = { .addr = (uint8_t *)ADDR_BA431_FIFO, .len = 0, - .flags = BLOCK_S_CONST_ADDR + .flags = BLOCK_S_CONST_ADDR, }; -//------------------------------------------------------------------------------ -// Forward Declarations +#if SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP -static void cryptoacc_trng_get_random_wrapper(void *unused_state, - block_t output); +static const sl_power_manager_em_transition_event_info_t buffer_trng_data_event = { + .event_mask = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 + | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3, + .on_event = store_trng_fifo_data, +}; + +#endif // SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP //------------------------------------------------------------------------------ -// Global Data +// Global Constants const struct sx_rng sli_cryptoacc_trng_wrapper = { .param = NULL, .get_rand_blk = cryptoacc_trng_get_random_wrapper, }; +//------------------------------------------------------------------------------ +// Static Variables + +#if SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + +static sl_power_manager_em_transition_event_handle_t buffer_trng_handle = { 0 }; + +// Keep all of the buffered randomness in the .bss section. Powering down the +// RAM bank containing this section would be a clear user error. We prefer to +// not use the heap for this data since the heap section expands (based on the +// linkerfile) into RAM banks that technically would be OK to power down. +static uint32_t buffered_randomness[SL_VSE_MAX_TRNG_WORDS_BUFFERED_DURING_SLEEP + 1] + = { 0 }; +static size_t n_buffered_random_bytes = 0; + +#endif // SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + //------------------------------------------------------------------------------ // Static Function Definitions +#if SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + +/* + * \brief + * Callback function for buffering all bytes currently in the TRNG FIFO. + * + * \details + * Will be called by the Power Manager on EM2/EM3 entry. Before this function + * returns, it will unsubscribe to the Power Manager event that caused it to + * trigger. + * + * \attention + * This function will disable the TRNG (NDRBG). + */ +static void store_trng_fifo_data(sl_power_manager_em_t from, + sl_power_manager_em_t to) +{ + (void)to; + (void)from; + + // It should be safe to assume that the CRYPTOACC resource won't be acquired + // by anyone when we're entering EM2/EM2. + if (cryptoacc_management_acquire() != PSA_SUCCESS) { + return; + } + + // We don't want the TRNG to start refilling the FIFO after we've read all of + // the remaining data (since we'll necessarily go below the refill threshold). + ba431_disable_ndrng(); + + block_t buffered_randomness_block = + block_t_convert(buffered_randomness, + SX_MIN(sizeof(uint32_t) * ba431_read_fifolevel(), + SL_VSE_MAX_TRNG_WORDS_BUFFERED_DURING_SLEEP * sizeof(uint32_t))); + + memcpy_blk(buffered_randomness_block, + trng_fifo_block, + buffered_randomness_block.len); + + if (cryptoacc_management_release() != PSA_SUCCESS) { + return; + } + + n_buffered_random_bytes = buffered_randomness_block.len; + + // Write a magic word to the end of the RAM buffer. This will be checked + // before the buffered data is used, as a basic sanity check that the data was + // actually retained in EM2/EM3. + buffered_randomness[SL_VSE_MAX_TRNG_WORDS_BUFFERED_DURING_SLEEP] + = BUFFERED_RANDOMNESS_MAGIC_WORD; + + // We are no longer interested in knowing if the device goes to sleep now that + // we have buffered the TRNG data. + sl_power_manager_unsubscribe_em_transition_event(&buffer_trng_handle); +} + +#endif // SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + static psa_status_t wait_until_trng_is_ready_for_sleep(void) { // We do not want to risk clocking down the CRYPTOACC while the ring @@ -156,7 +261,7 @@ static psa_status_t initialize_trng(void) } // The implementation of sx_trng_get_rand_blk() doesn't actually assert - // that the startup check passed succesfully (only that the TRNG is no + // that the startup check passed successfully (only that the TRNG is no // longer in a reset- or startup state). Therefore, we will implement our // own functions for waiting until the startup has completed and then // getting randomness from the TRNG FIFO. @@ -164,7 +269,7 @@ static psa_status_t initialize_trng(void) continue; } - // When we reach this point, the TRNG has started succesfully and is ready + // When we reach this point, the TRNG has started successfully and is ready // to be used. return PSA_SUCCESS; } @@ -199,13 +304,56 @@ static bool trng_needs_initialization(void) static psa_status_t cryptoacc_trng_get_random(block_t output) { + EFM_ASSERT(!(output.flags & BLOCK_S_CONST_ADDR)); + + #if SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + // Service as much of the request as possible from the already collected + // randomness which was buffered when EM2/EM3 was entered previously. + if ((n_buffered_random_bytes > 0) + && (buffered_randomness[SL_VSE_MAX_TRNG_WORDS_BUFFERED_DURING_SLEEP] + == BUFFERED_RANDOMNESS_MAGIC_WORD)) { + block_t chunk_block = block_t_convert(output.addr, + SX_MIN(output.len, + n_buffered_random_bytes)); + uint8_t *start_of_unused_randomness + = (uint8_t *)buffered_randomness + + SL_VSE_MAX_TRNG_WORDS_BUFFERED_DURING_SLEEP * sizeof(uint32_t) + - n_buffered_random_bytes; + block_t buffered_randomness_block = + block_t_convert(start_of_unused_randomness, n_buffered_random_bytes); + memcpy_blk(chunk_block, buffered_randomness_block, chunk_block.len); + + n_buffered_random_bytes -= chunk_block.len; + output.len -= chunk_block.len; + output.addr += chunk_block.len; + + if (n_buffered_random_bytes == 0) { + // Remove the magic word from RAM. + buffered_randomness[SL_VSE_MAX_TRNG_WORDS_BUFFERED_DURING_SLEEP] = 0; + } + if (output.len == 0) { + return PSA_SUCCESS; + } + } + #endif // SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + if (trng_needs_initialization()) { - // In addition to configuring the TRNG, this funtion will also wait until + // In addition to configuring the TRNG, this function will also wait until // the hardware is fully ready for usage. psa_status_t status = initialize_trng(); if (status != PSA_SUCCESS) { return status; } + + #if SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + // Now that we have initialized the TRNG, we know that its FIFO level will + // never go below the threshold level (outside of the duration of this + // function). In order to avoid wasting already generated random words, we + // will now register a callback function for storing randomness on EM2/EM3 + // entry. + sl_power_manager_subscribe_em_transition_event(&buffer_trng_handle, + &buffer_trng_data_event); + #endif // SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP } size_t n_bytes_generated = 0; @@ -222,7 +370,12 @@ static psa_status_t cryptoacc_trng_get_random(block_t output) // Potential bad states reached by the TRNG during the above randomness // generation will be handled by this function. - return wait_until_trng_is_ready_for_sleep(); + psa_status_t status = wait_until_trng_is_ready_for_sleep(); + if (status != PSA_SUCCESS) { + return status; + } + + return PSA_SUCCESS; } //------------------------------------------------------------------------------ @@ -238,7 +391,7 @@ static psa_status_t cryptoacc_trng_get_random(block_t output) * compilation units as well. * * \note - * This function does not assume any responsibility to aquire and release + * This function does not assume any responsibility to acquire and release * ownership of the CRYPTOACC peripheral. * * \warning diff --git a/platform/service/cpc/src/sl_cpc_drv_xmodem.c b/platform/service/cpc/src/sl_cpc_drv_xmodem.c index d2bf6d3120..e99a3cb8be 100644 --- a/platform/service/cpc/src/sl_cpc_drv_xmodem.c +++ b/platform/service/cpc/src/sl_cpc_drv_xmodem.c @@ -401,8 +401,13 @@ bool sli_cpc_is_bootloader_running(void) if (bootloader_has_been_probed) { return is_bootloader_running; } + bootloader_has_been_probed = true; + + memset(frame.data, 0x00, XMODEM_DATA_SIZE); - memset(frame.data, 0x00, sizeof(frame.data)); + for (size_t i = 0; i != 16; i++) { + (void) SL_CPC_DRV_UART_PERIPHERAL->RXDATA; + } // Since this is a unique descriptor being used to start a transfer, its okay for it to be declared on the // stack and not being a global variable. This is because the DMADRV_LdmaStartTransfer function takes the @@ -410,8 +415,8 @@ bool sli_cpc_is_bootloader_running(void) // so this descriptor can disappear after this function return and there will be no problem. LDMA_Descriptor_t fwu_receive_prompt_descriptor = (LDMA_Descriptor_t) LDMA_DESCRIPTOR_SINGLE_P2M_BYTE( &(SL_CPC_DRV_UART_PERIPHERAL->RXDATA), - frame.data, - sizeof(frame.data) - 1); // Leave space for a trailing \0 + &frame.data[0], + XMODEM_DATA_SIZE - 1); // Leave space for a trailing \0 fwu_receive_prompt_descriptor.xfer.doneIfs = 0; // No interrupt @@ -441,7 +446,7 @@ bool sli_cpc_is_bootloader_running(void) sl_udelay_wait(GECKO_STRING_USEC + BOOTLOADER_SAFE_MARGIN_USEC); - if (!strstr((char*)frame.data, gecko_string)) { + if (!strstr((char*)frame.data, &gecko_string[2])) { DMADRV_StopTransfer(read_channel); is_bootloader_running = false; goto end_of_function; @@ -471,7 +476,6 @@ bool sli_cpc_is_bootloader_running(void) is_bootloader_running = true; end_of_function: - bootloader_has_been_probed = true; return is_bootloader_running; } diff --git a/platform/service/device_init/src/sl_device_init_rffpll_s2.c b/platform/service/device_init/src/sl_device_init_rffpll_s2.c index 504659d1c6..5a38e452f3 100644 --- a/platform/service/device_init/src/sl_device_init_rffpll_s2.c +++ b/platform/service/device_init/src/sl_device_init_rffpll_s2.c @@ -62,7 +62,7 @@ sl_device_init_rffpll_config_t rffpll_band_config_39MHz[] = { { 97500000, 23, 7, 115 }, // Band 780 MHz { 97500000, 20, 6, 100 }, // Band 863 MHz { 97500000, 23, 7, 115 }, // Band 896 MHz - { 96520000, 20, 6, 99 }, // Band 928 MHz + { 97500000, 23, 7, 115 }, // Band 928 MHz { 97500000, 20, 6, 100 } // Band 9xx MHz (covers from 901 to 928 MHz) }; diff --git a/platform/service/hfxo_manager/src/sl_hfxo_manager_hal_s2.c b/platform/service/hfxo_manager/src/sl_hfxo_manager_hal_s2.c index 318d7385c5..6f2580b525 100644 --- a/platform/service/hfxo_manager/src/sl_hfxo_manager_hal_s2.c +++ b/platform/service/hfxo_manager/src/sl_hfxo_manager_hal_s2.c @@ -30,6 +30,7 @@ #include "em_device.h" #if defined(_SILICON_LABS_32B_SERIES_2) #include "sl_assert.h" +#include "em_core.h" #include "sli_hfxo_manager.h" #include "sl_hfxo_manager.h" #include "sl_hfxo_manager_config.h" @@ -132,7 +133,7 @@ void sli_hfxo_manager_init_hardware(void) { // Increase HFXO Interrupt priority so that it won't be masked by BASEPRI // and will preempt other interrupts. - NVIC_SetPriority(HFXO_IRQ_NUMBER, 2); + NVIC_SetPriority(HFXO_IRQ_NUMBER, CORE_ATOMIC_BASE_PRIORITY_LEVEL - 1); // Enable HFXO Interrupt if HFXO is used #if _SILICON_LABS_32B_SERIES_2_CONFIG >= 2 diff --git a/platform/service/legacy_ncp_spi/src/spi-protocol.c b/platform/service/legacy_ncp_spi/src/spi-protocol.c index e3be8849a5..d3032e0c9d 100644 --- a/platform/service/legacy_ncp_spi/src/spi-protocol.c +++ b/platform/service/legacy_ncp_spi/src/spi-protocol.c @@ -133,6 +133,20 @@ void halHostSerialPowerup(void) BSP_SPINCP_NWAKE_PIN, gpioModeInputPullFilter, 1); + #if defined(_SILICON_LABS_32B_SERIES_2) + uint32_t interrupt; + interrupt = GPIOINT_EM4WUCallbackRegisterExt(BSP_SPINCP_NWAKE_PORT, + BSP_SPINCP_NWAKE_PIN, + NULL, + NULL); + if (interrupt != INTERRUPT_UNAVAILABLE) { + GPIO_EM4WUExtIntConfig(BSP_SPINCP_NWAKE_PORT, + BSP_SPINCP_NWAKE_PIN, + interrupt, + false, + true); + } + #endif // defined(_SILICON_LABS_32B_SERIES_2) GPIO_ExtIntConfig(BSP_SPINCP_NWAKE_PORT, BSP_SPINCP_NWAKE_PIN, BSP_SPINCP_NWAKE_PIN, diff --git a/platform/service/sim_eeprom/sim_eeprom1/lib/libsim_eeprom1_CM4_gcc.a b/platform/service/sim_eeprom/sim_eeprom1/lib/libsim_eeprom1_CM4_gcc.a index 6c8eea3c22..3b845e679d 100644 --- a/platform/service/sim_eeprom/sim_eeprom1/lib/libsim_eeprom1_CM4_gcc.a +++ b/platform/service/sim_eeprom/sim_eeprom1/lib/libsim_eeprom1_CM4_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ebebfaa847a4eecaa941a3943aa942a82ea70ed853c97928001b4d716d3c46c5 +oid sha256:05e411a6528930fe7d725e7516df4d7e5fd89238c69cad2588ed57a2d7e588dc size 40436 diff --git a/platform/service/sim_eeprom/sim_eeprom1/lib/libsim_eeprom1_CM4_iar.a b/platform/service/sim_eeprom/sim_eeprom1/lib/libsim_eeprom1_CM4_iar.a index 27d8dd564e..8367b547e7 100644 --- a/platform/service/sim_eeprom/sim_eeprom1/lib/libsim_eeprom1_CM4_iar.a +++ b/platform/service/sim_eeprom/sim_eeprom1/lib/libsim_eeprom1_CM4_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:553a0076345ebc70c88134f737cc75849a2625cdd69e9d322bd5d7cfb4572299 +oid sha256:484259d8a1b9df21ac7e22cb492cda593c052c743c17042746b2500c615ed3a1 size 30558 diff --git a/platform/service/sim_eeprom/sim_eeprom1_to_sim_eeprom2_upgrade/lib/libsim_eeprom1_to_sim_eeprom2_upgrade_CM4_gcc.a b/platform/service/sim_eeprom/sim_eeprom1_to_sim_eeprom2_upgrade/lib/libsim_eeprom1_to_sim_eeprom2_upgrade_CM4_gcc.a index 3cb621fc51..58e81f19d8 100644 --- a/platform/service/sim_eeprom/sim_eeprom1_to_sim_eeprom2_upgrade/lib/libsim_eeprom1_to_sim_eeprom2_upgrade_CM4_gcc.a +++ b/platform/service/sim_eeprom/sim_eeprom1_to_sim_eeprom2_upgrade/lib/libsim_eeprom1_to_sim_eeprom2_upgrade_CM4_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9ee6721c5d322c2dbed1213ef5e5d0dd7c2cac6cfb1a3ba8d12a7b026aca0fc6 +oid sha256:3cc04410d72fbad09844c9baddbb02f7e6cbe81b66680de1a9dc9ee0d215587b size 26374 diff --git a/platform/service/sim_eeprom/sim_eeprom1_to_sim_eeprom2_upgrade/lib/libsim_eeprom1_to_sim_eeprom2_upgrade_CM4_iar.a b/platform/service/sim_eeprom/sim_eeprom1_to_sim_eeprom2_upgrade/lib/libsim_eeprom1_to_sim_eeprom2_upgrade_CM4_iar.a index 5c179239d1..fa2cdefe28 100644 --- a/platform/service/sim_eeprom/sim_eeprom1_to_sim_eeprom2_upgrade/lib/libsim_eeprom1_to_sim_eeprom2_upgrade_CM4_iar.a +++ b/platform/service/sim_eeprom/sim_eeprom1_to_sim_eeprom2_upgrade/lib/libsim_eeprom1_to_sim_eeprom2_upgrade_CM4_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4f2c9571489b75e8695b85aee7c7874c1e8a4797da5b5bc7013ad798de44a600 +oid sha256:7223f5537b87b79a1f3967de9ee6fcf6bfb900134311fcd408a84f4e7daa83df size 19238 diff --git a/platform/service/sim_eeprom/sim_eeprom2/lib/libsim_eeprom2_CM4_gcc.a b/platform/service/sim_eeprom/sim_eeprom2/lib/libsim_eeprom2_CM4_gcc.a index 78f86067ab..ad273ba6ff 100644 --- a/platform/service/sim_eeprom/sim_eeprom2/lib/libsim_eeprom2_CM4_gcc.a +++ b/platform/service/sim_eeprom/sim_eeprom2/lib/libsim_eeprom2_CM4_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:adcf1438170717dc0fb24bb4cf353aa0e9a720349e21661940b54350becac2cc +oid sha256:e60097918c5dda79e0c9140f3fa5321c5eb4461ea47c50048caa065e501c8c5b size 51300 diff --git a/platform/service/sim_eeprom/sim_eeprom2/lib/libsim_eeprom2_CM4_iar.a b/platform/service/sim_eeprom/sim_eeprom2/lib/libsim_eeprom2_CM4_iar.a index a916e79946..78d6d13d86 100644 --- a/platform/service/sim_eeprom/sim_eeprom2/lib/libsim_eeprom2_CM4_iar.a +++ b/platform/service/sim_eeprom/sim_eeprom2/lib/libsim_eeprom2_CM4_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c356158d892debc238bfd4a2e55b95331cd3355b6357be4a9dd5a7d9a1520bfe +oid sha256:3deed96e400d837c0a86b27bc439e274af874dbb0257c6a35807141666681203 size 47016 diff --git a/platform/service/sim_eeprom/sim_eeprom2_to_nvm3_upgrade/lib/libsim_eeprom2_to_nvm3_upgrade_CM4_gcc.a b/platform/service/sim_eeprom/sim_eeprom2_to_nvm3_upgrade/lib/libsim_eeprom2_to_nvm3_upgrade_CM4_gcc.a index ce8f444bcd..983ee31674 100644 --- a/platform/service/sim_eeprom/sim_eeprom2_to_nvm3_upgrade/lib/libsim_eeprom2_to_nvm3_upgrade_CM4_gcc.a +++ b/platform/service/sim_eeprom/sim_eeprom2_to_nvm3_upgrade/lib/libsim_eeprom2_to_nvm3_upgrade_CM4_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:be1373d4a220e1fd2fcbc0cc3baf940b742cdad1a1c44f3ba91de3ad68e39c63 +oid sha256:b215dda48423beb43a939835c4d9523f30143cd34ce02629a7a7f9cfe8a5d25f size 21410 diff --git a/platform/service/sim_eeprom/sim_eeprom2_to_nvm3_upgrade/lib/libsim_eeprom2_to_nvm3_upgrade_CM4_iar.a b/platform/service/sim_eeprom/sim_eeprom2_to_nvm3_upgrade/lib/libsim_eeprom2_to_nvm3_upgrade_CM4_iar.a index a54c63796a..043b003e92 100644 --- a/platform/service/sim_eeprom/sim_eeprom2_to_nvm3_upgrade/lib/libsim_eeprom2_to_nvm3_upgrade_CM4_iar.a +++ b/platform/service/sim_eeprom/sim_eeprom2_to_nvm3_upgrade/lib/libsim_eeprom2_to_nvm3_upgrade_CM4_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8bc27aa3cfce6c6d4eef42eeafce7edba352b719c63889e393245446e2e0b664 +oid sha256:92d20da2a787c5fc6f20c09f40a4dbbd6cfd05d382f11082ecf15538cadbe22d size 11840 diff --git a/platform/service/token_manager/src/sl_token_manufacturing.c b/platform/service/token_manager/src/sl_token_manufacturing.c index 002a852f35..03fba877bf 100644 --- a/platform/service/token_manager/src/sl_token_manufacturing.c +++ b/platform/service/token_manager/src/sl_token_manufacturing.c @@ -166,6 +166,8 @@ EmberStatus halInternalFlashErase(uint8_t eraseType, uint32_t address) ret = MSC_MassErase(); #endif // !defined (_SILICON_LABS_32B_SERIES_2) } else { + // EMHAL-2846: Ensure page boundary alignment + address &= ~(FLASH_PAGE_SIZE - 1); ret = MSC_ErasePage((uint32_t *) address); } diff --git a/protocol/bluetooth/api/sl_bt.xapi b/protocol/bluetooth/api/sl_bt.xapi index abcf61ceee..d724e6f270 100644 --- a/protocol/bluetooth/api/sl_bt.xapi +++ b/protocol/bluetooth/api/sl_bt.xapi @@ -1,5 +1,5 @@ - + @@ -243,6 +243,7 @@ + diff --git a/protocol/bluetooth/api/sl_btmesh.xapi b/protocol/bluetooth/api/sl_btmesh.xapi index f86157019f..d2916856f4 100644 --- a/protocol/bluetooth/api/sl_btmesh.xapi +++ b/protocol/bluetooth/api/sl_btmesh.xapi @@ -1,5 +1,5 @@ - + @@ -384,6 +384,37 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -1428,6 +1459,15 @@ + + + + + + + + + @@ -1451,6 +1491,9 @@ + + + @@ -7411,9 +7454,14 @@ - + + + + + + @@ -7423,6 +7471,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + @@ -7431,5 +7503,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/protocol/bluetooth/api/sli_bgapi_debug.xapi b/protocol/bluetooth/api/sli_bgapi_debug.xapi index abe5d8a244..5df5546803 100644 --- a/protocol/bluetooth/api/sli_bgapi_debug.xapi +++ b/protocol/bluetooth/api/sli_bgapi_debug.xapi @@ -1,5 +1,5 @@ - + diff --git a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg12_gcc_release.a b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg12_gcc_release.a index f5e9604004..e38f37fe8c 100644 --- a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg12_gcc_release.a +++ b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg12_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3899e4f4ca392b9cf7cc3aca06e81c10cafd43ceda8e072055aca000a6c85e73 -size 269730 +oid sha256:939f4e49504fc6d1d34678c166cb0fc1024b25e2c689bfbb3866a77d25ab39db +size 270282 diff --git a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg12_iar_release.a b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg12_iar_release.a index 32e6dd20ca..e1ddfb2247 100644 --- a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg12_iar_release.a +++ b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg12_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0686dcc58342412edc4206321ab3ae683769342fb18f320a6f1370219651a574 -size 576396 +oid sha256:c3070f6c1b59992c93a6b8ec1397efa2003092263ab9caa94c4e1f0eda1a74a3 +size 576576 diff --git a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg13_gcc_release.a b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg13_gcc_release.a index df3f13266f..ed17d28260 100644 --- a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg13_gcc_release.a +++ b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg13_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a785fa923355ceef41124844fac931f14491b6120964865de61c9ac72095814b -size 269730 +oid sha256:9224aeecd9355f49e9723ad51852c0b9f5d30217152c554dcbab4714ad77ffad +size 270282 diff --git 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a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg1_gcc_release.a +++ b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg1_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d5c5b8e42a190cb9485f032b79b5f497744bda13fcb9fa184fc4634a79ed46b0 -size 269718 +oid sha256:c5cbd5b15e4220a8248698ebac46c49dfec2767f7d45bab422134c26d77fc7ce +size 270258 diff --git a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg1_iar_release.a b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg1_iar_release.a index 899e67034c..4ce7d93b11 100644 --- a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg1_iar_release.a +++ b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg1_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:18f9cb691bdb0ebacc47a468783f94ee95c63d94f3ab42f9e82103f03d28f3db -size 591480 +oid sha256:77d25cf46c6fbea3d130bbb5ae56f776346df30b1f91a4e3559b072b1673620f +size 591658 diff --git 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a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg22_iar_release.a +++ b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg22_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5315f2a25cf639ca0582e736796ae501b0a845a9301721bd87377e19e86bbd90 -size 580168 +oid sha256:c5bc3d579b6e72b679814400ba7f1485aefb1b5a9b477f0e95ef62ce8a77af7e +size 580348 diff --git a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg24_gcc_release.a b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg24_gcc_release.a index 71c9dad870..1498a3cf91 100644 --- a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg24_gcc_release.a +++ b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg24_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1f2430ffe8d0750cdeee3316805e35037fb6c1a542f6068c41a240b829e7c138 -size 266522 +oid sha256:fde8f04da144f31976a1938f05463b2809c30cb193a117fef6a03ee14b309599 +size 267062 diff --git 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a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg28_gcc_release.a +++ b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg28_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fb8e6679e66f2e9823d795aedbef95862bd02a99d96e2d90614f44d4dcf8f16f -size 266522 +oid sha256:12ce4cc943e9cf4ca64d091cde5d612c9e971ebd768bb56e87143dc16f3d66eb +size 267062 diff --git a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg28_iar_release.a b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg28_iar_release.a index 999e329161..14c89400e3 100644 --- a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg28_iar_release.a +++ b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg28_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d51b97dc11516c41df90ec182ce1274d4cdf43591bcf0219251a9d2483b9bdb6 -size 581286 +oid sha256:aea54da875406debecc0fbc965986a8e025819084aaac650f393681432a2ebbe +size 581464 diff --git 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a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg21_iar_release.a b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg21_iar_release.a index efcd775128..4b9d2f70ca 100644 --- a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg21_iar_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg21_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2164cd3e8d8bb9a8c0781113861ece30423fabbd58bceffc60eefee027e2ec72 -size 23396508 +oid sha256:bee790ff5b4ddc3ba584b452e71ae891f0c43a639798814e8e6d13595168153b +size 23571182 diff --git a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_gcc_release.a b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_gcc_release.a index 8887fafba7..2e00ffc282 100644 --- a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_gcc_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c01a6fea1782ed0b11f93b8f9c923f08d32c3970ff8248ba5d828bc51a71f53b -size 9292628 +oid sha256:c830ec6ef55622aeccf1b8961921cf49f9efe2957392f45ce5ede8f68e252d3d +size 9339736 diff --git a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_iar_release.a b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_iar_release.a index 530fc95d77..807117731f 100644 --- a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_iar_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d04a37b5748b472854a2008d4d11dc9c9308eb36066e6905b98c2a974a26e6f0 -size 23404192 +oid sha256:dfc44010f71f4c3fd24dc5e96a1f6c64f713df096101d920a02875d43bdc6c81 +size 23578844 diff --git a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg24_gcc_release.a b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg24_gcc_release.a index d2d586a637..936dfaf6b8 100644 --- a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg24_gcc_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg24_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:674889084d27040aba7bc5337a6d26b9bec25ed405f5de0e5ec15db3b4f4c82c -size 9301736 +oid sha256:b922f3ce752af7bb21616dd5fd2e83bfc6da4a51d9d3902dbd6790280957eedd +size 9348844 diff --git a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg24_iar_release.a b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg24_iar_release.a index deb0a16b08..bf35f08dce 100644 --- a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg24_iar_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg24_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:991b538c35a80c8ce5690e0ce9e1be8d40b6d4c159e3c040aaea8b7c3e91f50e -size 23411898 +oid sha256:a057bc8edd79783f4bd00ec9eb7205c6cee780347c7046712cf6d334bbe68010 +size 23586574 diff --git a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg27_gcc_release.a b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg27_gcc_release.a index 846d3ab074..14aa606cbc 100644 --- a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg27_gcc_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg27_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:abe7825f0af08fb4334b3aab43e63ab1b656b45706ee88cf4922b9162166bb34 -size 9293364 +oid sha256:2f11d23c1395217a9e31eea414b95ff60a517f03f6a750dc796686a6a56ec40f +size 9340472 diff --git a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg27_iar_release.a b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg27_iar_release.a index 13fe3b32c3..7e75690559 100644 --- a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg27_iar_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg27_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a4886c37a7f319393b0abff302bc682400ce9d47715925b51ee9da107d39c3e7 -size 23407038 +oid sha256:bcdff096c143f3a0baaa78e7e025f35d25ecf3930d46bfafb39588b628b3a664 +size 23581680 diff --git a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg28_gcc_release.a b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg28_gcc_release.a index 769dc0710c..0fd66f031f 100644 --- a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg28_gcc_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg28_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:eb25b9e9d3a5918f154e0822052e134a5220965cafad360a0d6cee4a18bb9e69 -size 9303084 +oid sha256:38d55c062ed3c933c32c27f666395ca1a03f346f9f5036538de1bdde89eb8806 +size 9350192 diff --git a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg28_iar_release.a b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg28_iar_release.a index d91a03274e..fc38aa923e 100644 --- a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg28_iar_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg28_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0e2ec54a5432f74e0ae5d6017a01714478c6bfa7815cec292bbb2befaac2dd5d -size 23416436 +oid sha256:f063529f288a6656ef3c8a54bf36a60ffb88879eff046d0eb5b38031d2502ede +size 23591108 diff --git a/protocol/bluetooth/inc/sl_bt_api.h b/protocol/bluetooth/inc/sl_bt_api.h index 793d7652c6..edf0d6ffc6 100644 --- a/protocol/bluetooth/inc/sl_bt_api.h +++ b/protocol/bluetooth/inc/sl_bt_api.h @@ -882,34 +882,38 @@ typedef struct sl_bt_evt_system_hardware_error_s sl_bt_evt_system_hardware_error ******************************************************************************/ PACKSTRUCT( struct sl_bt_evt_system_resource_exhausted_s { - uint8_t num_buffers_discarded; /**< The system has temporarily run - out of the pre-allocated data - buffers that are allocated based - on SL_BT_CONFIG_BUFFER_SIZE - configuration and some expendable - data or event had to be discarded - to satisfy a non-expendble buffer - allocation. A typical case is - discarding scan reports when a - large inflow of scan reports - exceeds the speed at which the - application drains the BGAPI - event queue. */ - uint8_t num_buffer_allocation_failures; /**< The system has run out of the - pre-allocated data buffers that - are allocated based on - SL_BT_CONFIG_BUFFER_SIZE - configuration and a buffer - allocation has failed. */ - uint8_t num_heap_allocation_failures; /**< The Bluetooth stack has failed to - make an allocation from the heap. - Note that only allocations made - by the Bluetooth stack are - detected and reported by this - field. Allocation failures in - other components that use - sl_malloc() or malloc() are not - included in this count. */ + uint8_t num_buffers_discarded; /**< The system has temporarily run + out of the pre-allocated data + buffers that are allocated based + on SL_BT_CONFIG_BUFFER_SIZE + configuration and some + expendable data or event had to + be discarded to satisfy a + non-expendble buffer allocation. + A typical case is discarding + scan reports when a large inflow + of scan reports exceeds the + speed at which the application + drains the BGAPI event queue. */ + uint8_t num_buffer_allocation_failures; /**< The system has run out of the + pre-allocated data buffers that + are allocated based on + SL_BT_CONFIG_BUFFER_SIZE + configuration and a buffer + allocation has failed. */ + uint8_t num_heap_allocation_failures; /**< The Bluetooth stack has failed + to make an allocation from the + heap. Note that only allocations + made by the Bluetooth stack are + detected and reported by this + field. Allocation failures in + other components that use + sl_malloc() or malloc() are not + included in this count. */ + uint8_t num_message_allocation_failures; /**< The system has run out of + internal pre-allocated message + items and the creation of an + internal message has failed. */ }); typedef struct sl_bt_evt_system_resource_exhausted_s sl_bt_evt_system_resource_exhausted_t; @@ -2310,12 +2314,11 @@ sl_status_t sl_bt_advertiser_set_channel_map(uint8_t advertising_set, * goes over the global value that was set using the @ref * sl_bt_system_set_tx_power command, the global value will be the maximum * limit. The maximum TX power of legacy advertising is further constrained to - * be less than +10 dBm. Extended advertising TX power can be +10 dBm and over - * if Adaptive Frequency Hopping is enabled. This setting has no effect on - * periodic advertising. + * be less than +10 dBm. The extended advertising and periodic advertising TX + * power can be +10 dBm and over if Adaptive Frequency Hopping is enabled. * - * This setting will take effect next time the legacy or extended advertising is - * enabled. + * This setting will take effect next time the legacy, extended or periodic + * advertising is enabled. * * By default, maximum advertising TX power is limited by the global value. * diff --git a/protocol/bluetooth/inc/sl_bt_version.h b/protocol/bluetooth/inc/sl_bt_version.h index 66e9c9c8f7..6c3e6f33c7 100644 --- a/protocol/bluetooth/inc/sl_bt_version.h +++ b/protocol/bluetooth/inc/sl_bt_version.h @@ -35,24 +35,24 @@ * * An increment indicates new backwards compatible functionalities. */ -#define SL_BT_VERSION_MINOR 0 +#define SL_BT_VERSION_MINOR 1 /** * @brief The patch number of Bluetooth SDK version * * An increment indicates backwards compatible bug fixes. */ -#define SL_BT_VERSION_PATCH 1 +#define SL_BT_VERSION_PATCH 0 /** * @brief The build number which the Bluetooth SDK was created from */ -#define SL_BT_VERSION_BUILD 206 +#define SL_BT_VERSION_BUILD 236 /** * @brief The hash value of the build the Bluetooth SDK was created from */ -#define SL_BT_VERSION_HASH {0x5b,0x56,0x2c,0x1a,0x0e,0x64,0x78,0xa5,0x6f,0x6d,0xcd,0xd4,0x17,0x91,0x18,0x7e,0xaf,0x86,0x8e,0xf6} +#define SL_BT_VERSION_HASH {0xc2,0xaf,0x6a,0x8a,0x80,0x37,0xfc,0x08,0xe1,0xfd,0xa7,0x1e,0xfc,0x26,0x54,0xae,0x1c,0xcf,0x36,0x6b} /** * Deprecated and replaced by SL_BT_VERSION_MAJOR diff --git a/protocol/bluetooth/inc/sl_btmesh_api.h b/protocol/bluetooth/inc/sl_btmesh_api.h index 536f8f7bcc..eca87484d2 100644 --- a/protocol/bluetooth/inc/sl_btmesh_api.h +++ b/protocol/bluetooth/inc/sl_btmesh_api.h @@ -154,6 +154,10 @@ extern "C" { #define sl_btmesh_cmd_node_set_oob_uri_id 0x33140028 #define sl_btmesh_cmd_node_get_oob_uri_id 0x34140028 #define sl_btmesh_cmd_node_set_proxy_service_uuid_id 0x35140028 +#define sl_btmesh_cmd_node_set_proxy_service_scan_response_id 0x37140028 +#define sl_btmesh_cmd_node_clear_proxy_service_scan_response_id 0x38140028 +#define sl_btmesh_cmd_node_set_provisioning_service_scan_response_id 0x39140028 +#define sl_btmesh_cmd_node_clear_provisioning_service_scan_response_id 0x3a140028 #define sl_btmesh_rsp_node_init_id 0x00140028 #define sl_btmesh_rsp_node_set_exportable_keys_id 0x24140028 #define sl_btmesh_rsp_node_start_unprov_beaconing_id 0x01140028 @@ -198,6 +202,10 @@ extern "C" { #define sl_btmesh_rsp_node_set_oob_uri_id 0x33140028 #define sl_btmesh_rsp_node_get_oob_uri_id 0x34140028 #define sl_btmesh_rsp_node_set_proxy_service_uuid_id 0x35140028 +#define sl_btmesh_rsp_node_set_proxy_service_scan_response_id 0x37140028 +#define sl_btmesh_rsp_node_clear_proxy_service_scan_response_id 0x38140028 +#define sl_btmesh_rsp_node_set_provisioning_service_scan_response_id 0x39140028 +#define sl_btmesh_rsp_node_clear_provisioning_service_scan_response_id 0x3a140028 /** * @brief Flags for allowed provisioning algorithms during provisioning, which @@ -1867,6 +1875,87 @@ sl_status_t sl_btmesh_node_get_oob_uri(size_t max_uri_size, ******************************************************************************/ sl_status_t sl_btmesh_node_set_proxy_service_uuid(uint16_t uuid); +/***************************************************************************//** + * + * Set Mesh Proxy Service scan response data. + * + * This command sets the scan response data for a Mesh Proxy Service + * advertisement. The Mesh Proxy Service advertisement is a connectable and + * scannable advertisement, meaning that a client can issue a scan request and + * receive a scan response that carries additional data relevant to the service. + * This setting will take effect next time the Mesh Proxy Service advertisement + * is started. + * + * @param[in] netkey_index Index of the network key associated with the proxy + * service advertisement. The caller may set scan response data separately for + * each network key, so that data encrypted and/or authenticated with the + * network key can be used as a scan response, if desired. + * @param[in] scan_response_data_len Length of data in @p scan_response_data + * @param[in] scan_response_data Binary scan response data encoded as AD types + * as defined in the Core specification. Data must fit into a SCAN_RSP PDU. It + * is up to the caller to ensure that valid data is given. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_btmesh_node_set_proxy_service_scan_response(uint16_t netkey_index, + size_t scan_response_data_len, + const uint8_t* scan_response_data); + +/***************************************************************************//** + * + * Clear Mesh Proxy Service scan response data. + * + * This command clears the scan response data for a Mesh Proxy Service + * advertisement. This setting will take effect next time the Mesh Proxy Service + * advertisement is started. + * + * @param[in] netkey_index Index of the network key associated with the proxy + * service advertisement. The caller may set scan response data separately for + * each network key, so that data encrypted and/or authenticated with the + * network key can be used as a scan response, if desired. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_btmesh_node_clear_proxy_service_scan_response(uint16_t netkey_index); + +/***************************************************************************//** + * + * Set Mesh Provisioning Service scan response data. + * + * This command sets the scan response data for a Mesh Provisioning Service + * advertisement. The Mesh Provisioning Service advertisement is a connectable + * and scannable advertisement, meaning that a client can issue a scan request + * and receive a scan response that carries additional data relevant to the + * service. This setting will take effect next time the Mesh Provisioning + * Service advertisement is started. + * + * @param[in] scan_response_data_len Length of data in @p scan_response_data + * @param[in] scan_response_data Binary scan response data encoded as AD types + * as defined in the Core specification. Data must fit into a SCAN_RSP PDU. It + * is up to the caller to ensure that valid data is given. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_btmesh_node_set_provisioning_service_scan_response(size_t scan_response_data_len, + const uint8_t* scan_response_data); + +/***************************************************************************//** + * + * Clear Mesh Provisioning Service scan response data. + * + * This command clears the scan response data for a Mesh Provisioning Service + * advertisement. This setting will take effect next time the Mesh Provisioning + * Service advertisement is started. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_btmesh_node_clear_provisioning_service_scan_response(); + /** @} */ // end addtogroup sl_btmesh_node /** @@ -3958,6 +4047,7 @@ sl_status_t sl_btmesh_silabs_config_client_deinit(); #define sl_btmesh_cmd_vendor_model_deinit_id 0x05190028 #define sl_btmesh_cmd_vendor_model_send_tracked_id 0x06190028 #define sl_btmesh_cmd_vendor_model_set_publication_tracked_id 0x07190028 +#define sl_btmesh_cmd_vendor_model_set_option_id 0x08190028 #define sl_btmesh_rsp_vendor_model_send_id 0x00190028 #define sl_btmesh_rsp_vendor_model_set_publication_id 0x01190028 #define sl_btmesh_rsp_vendor_model_clear_publication_id 0x02190028 @@ -3966,6 +4056,24 @@ sl_status_t sl_btmesh_silabs_config_client_deinit(); #define sl_btmesh_rsp_vendor_model_deinit_id 0x05190028 #define sl_btmesh_rsp_vendor_model_send_tracked_id 0x06190028 #define sl_btmesh_rsp_vendor_model_set_publication_tracked_id 0x07190028 +#define sl_btmesh_rsp_vendor_model_set_option_id 0x08190028 + +/** + * @brief Key values to identify vendor model configuration options + */ +typedef enum +{ + sl_btmesh_vendor_model_heap_work_buffer = 0x0 /**< (0x0) If set to 1, each + vendor model allocates a + heap work buffer for + messages being received. + If set to 0, no heap work + buffer allocation is made, + which saves memory but + risks losing messages in a + high load environment. + Range: 0...1 Default: 1 */ +} sl_btmesh_vendor_model_options_t; /** * @addtogroup sl_btmesh_evt_vendor_model_receive sl_btmesh_evt_vendor_model_receive @@ -4324,6 +4432,23 @@ sl_status_t sl_btmesh_vendor_model_set_publication_tracked(uint16_t elem_index, const uint8_t* payload, uint16_t *handle); +/***************************************************************************//** + * + * Set global vendor model configuration options. + * + * This command sets global configuration options for all vendor models. Options + * take effect when models are initialized, so this command should be called + * before any @ref sl_btmesh_vendor_model_init call. + * + * @param[in] option Enum @ref sl_btmesh_vendor_model_options_t. Configuration + * option. + * @param[in] value Configuration value + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_btmesh_vendor_model_set_option(uint8_t option, uint32_t value); + /** @} */ // end addtogroup sl_btmesh_vendor_model /** @@ -22183,6 +22308,9 @@ sl_status_t sl_btmesh_silabs_config_server_get_network_pdu(uint16_t *max_size); #define sl_btmesh_cmd_diagnostic_get_relay_id 0x046c0028 #define sl_btmesh_cmd_diagnostic_get_statistics_id 0x056c0028 #define sl_btmesh_cmd_diagnostic_clear_statistics_id 0x066c0028 +#define sl_btmesh_cmd_diagnostic_enable_friend_id 0x076c0028 +#define sl_btmesh_cmd_diagnostic_disable_friend_id 0x086c0028 +#define sl_btmesh_cmd_diagnostic_get_friend_id 0x096c0028 #define sl_btmesh_rsp_diagnostic_init_id 0x006c0028 #define sl_btmesh_rsp_diagnostic_deinit_id 0x016c0028 #define sl_btmesh_rsp_diagnostic_enable_relay_id 0x026c0028 @@ -22190,6 +22318,9 @@ sl_status_t sl_btmesh_silabs_config_server_get_network_pdu(uint16_t *max_size); #define sl_btmesh_rsp_diagnostic_get_relay_id 0x046c0028 #define sl_btmesh_rsp_diagnostic_get_statistics_id 0x056c0028 #define sl_btmesh_rsp_diagnostic_clear_statistics_id 0x066c0028 +#define sl_btmesh_rsp_diagnostic_enable_friend_id 0x076c0028 +#define sl_btmesh_rsp_diagnostic_disable_friend_id 0x086c0028 +#define sl_btmesh_rsp_diagnostic_get_friend_id 0x096c0028 /** * @addtogroup sl_btmesh_evt_diagnostic_relay sl_btmesh_evt_diagnostic_relay @@ -22217,6 +22348,95 @@ typedef struct sl_btmesh_evt_diagnostic_relay_s sl_btmesh_evt_diagnostic_relay_t /** @} */ // end addtogroup sl_btmesh_evt_diagnostic_relay +/** + * @addtogroup sl_btmesh_evt_diagnostic_friend_queue sl_btmesh_evt_diagnostic_friend_queue + * @{ + * @brief Event for LPN message queuing + */ + +/** @brief Identifier of the friend_queue event */ +#define sl_btmesh_evt_diagnostic_friend_queue_id 0x016c00a8 + +/***************************************************************************//** + * @brief Data structure of the friend_queue event + ******************************************************************************/ +PACKSTRUCT( struct sl_btmesh_evt_diagnostic_friend_queue_s +{ + uint16_t netkey_index; /**< Index of the network key used in friendship */ + uint16_t lpn; /**< LPN address */ + uint16_t src; /**< Source address of the message */ + uint16_t dst; /**< Destination address of the message */ + uint32_t ivi; /**< IV index used to secure the message */ + uint32_t seq; /**< Sequence number of the message */ +}); + +typedef struct sl_btmesh_evt_diagnostic_friend_queue_s sl_btmesh_evt_diagnostic_friend_queue_t; + +/** @} */ // end addtogroup sl_btmesh_evt_diagnostic_friend_queue + +/** + * @addtogroup sl_btmesh_evt_diagnostic_friend_relay sl_btmesh_evt_diagnostic_friend_relay + * @{ + * @brief Event for LPN message relaying as a response to a poll request from + * the LPN + */ + +/** @brief Identifier of the friend_relay event */ +#define sl_btmesh_evt_diagnostic_friend_relay_id 0x026c00a8 + +/***************************************************************************//** + * @brief Data structure of the friend_relay event + ******************************************************************************/ +PACKSTRUCT( struct sl_btmesh_evt_diagnostic_friend_relay_s +{ + uint16_t netkey_index; /**< Index of the network key used in friendship */ + uint16_t lpn; /**< LPN address */ + uint16_t src; /**< Source address of the message */ + uint16_t dst; /**< Destination address of the message */ + uint32_t ivi; /**< IV index used to secure the message */ + uint32_t seq; /**< Sequence number of the message */ +}); + +typedef struct sl_btmesh_evt_diagnostic_friend_relay_s sl_btmesh_evt_diagnostic_friend_relay_t; + +/** @} */ // end addtogroup sl_btmesh_evt_diagnostic_friend_relay + +/** + * @addtogroup sl_btmesh_evt_diagnostic_friend_remove sl_btmesh_evt_diagnostic_friend_remove + * @{ + * @brief Event for removing a message from friendship queue + */ + +/** @brief Identifier of the friend_remove event */ +#define sl_btmesh_evt_diagnostic_friend_remove_id 0x036c00a8 + +/***************************************************************************//** + * @brief Data structure of the friend_remove event + ******************************************************************************/ +PACKSTRUCT( struct sl_btmesh_evt_diagnostic_friend_remove_s +{ + uint16_t netkey_index; /**< Index of the network key used in friendship */ + uint16_t lpn; /**< LPN address */ + uint16_t src; /**< Source address of the message */ + uint16_t dst; /**< Destination address of the message */ + uint32_t ivi; /**< IV index used to secure the message */ + uint32_t seq; /**< Sequence number of the message */ + uint8_t reason; /**< Reason for removing the message. The following + reasons are defined: + - 0: The message has been acknowledged as + delivered by the LPN + - 1: The message queue has overflowed and the + oldest message was dropped + - 2: A newer segment acknowledgement has been + inserted to the message queue + - 3: Invalidated message segments have been + cleaned up */ +}); + +typedef struct sl_btmesh_evt_diagnostic_friend_remove_s sl_btmesh_evt_diagnostic_friend_remove_t; + +/** @} */ // end addtogroup sl_btmesh_evt_diagnostic_friend_remove + /***************************************************************************//** * * Initialize Diagnostic Utilities. @@ -22277,8 +22497,17 @@ sl_status_t sl_btmesh_diagnostic_get_relay(uint32_t *relay_counter); /***************************************************************************//** * - * Get Bluetooth mesh stack statistics data counters. + * Get a chunk of Bluetooth mesh stack statistics data counters. As there can be + * a large amount of statistics, it has to be retrieved as chunks. The + * application is free to specify the size of the chunk it wants to use, but + * keep in mind that for the NCP use case there may be limited size buffers in + * the underlying serial channel. * + * @param[in] requested_chunk Size of the statistics data chunk requested + * @param[in] requested_offset Byte offset to the statistics data chunk + * requested + * @param[out] total_length Total length of the statistics data in the system + * @param[out] chunk_offset Byte offset to the statistics data chunk delivered * @param[in] max_statistics_size Size of output buffer passed in @p statistics * @param[out] statistics_len On return, set to the length of output data * written to @p statistics @@ -22287,7 +22516,11 @@ sl_status_t sl_btmesh_diagnostic_get_relay(uint32_t *relay_counter); * @return SL_STATUS_OK if successful. Error code otherwise. * ******************************************************************************/ -sl_status_t sl_btmesh_diagnostic_get_statistics(size_t max_statistics_size, +sl_status_t sl_btmesh_diagnostic_get_statistics(uint32_t requested_chunk, + uint32_t requested_offset, + uint32_t *total_length, + uint32_t *chunk_offset, + size_t max_statistics_size, size_t *statistics_len, uint8_t *statistics); @@ -22301,6 +22534,62 @@ sl_status_t sl_btmesh_diagnostic_get_statistics(size_t max_statistics_size, ******************************************************************************/ sl_status_t sl_btmesh_diagnostic_clear_statistics(); +/***************************************************************************//** + * + * Enable event sending for friendship diagnostics on the friend node side. + * NOTE: On NCP target this can saturate the NCP PHY interface. An alternative + * for this is @ref sl_btmesh_diagnostic_get_friend + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_btmesh_evt_diagnostic_friend_queue + * - @ref sl_btmesh_evt_diagnostic_friend_relay + * - @ref sl_btmesh_evt_diagnostic_friend_remove + * + ******************************************************************************/ +sl_status_t sl_btmesh_diagnostic_enable_friend(); + +/***************************************************************************//** + * + * Disable event sending for friendship diagnostics on the friend node side. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_btmesh_diagnostic_disable_friend(); + +/***************************************************************************//** + * + * Get friend event counters. + * + * @param[out] queue_counter Number of messages queued for LPNs. + * @param[out] relay_counter Number of messages relayed to LPNs as a response to + * polls. + * @param[out] remove_counter_sent Number of messages discarded from LPN + * friendship queues due to message having been to sent to LPN and + * acknowledged by LPN by it sending the next poll. + * @param[out] remove_counter_old_pdu Number of messages discarded from LPN + * friendship queues due to message queue overflow, resulting in the need to + * flush the oldest PDU un the queue + * @param[out] remove_counter_old_segack Number of messages discarded from LPN + * friendship queues due to a new segment acknowledgement message replacing an + * old one in the queue. + * @param[out] remove_counter_old_segment Number of messages discarded from LPN + * friendship queues due to invalidated segments being removed from the queue. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_btmesh_diagnostic_get_friend(uint32_t *queue_counter, + uint32_t *relay_counter, + uint32_t *remove_counter_sent, + uint32_t *remove_counter_old_pdu, + uint32_t *remove_counter_old_segack, + uint32_t *remove_counter_old_segment); + /** @} */ // end addtogroup sl_btmesh_diagnostic @@ -22560,6 +22849,9 @@ PACKSTRUCT( struct sl_btmesh_msg { sl_btmesh_evt_silabs_config_server_model_option_changed_t evt_silabs_config_server_model_option_changed; /**< Data field for silabs_config_server model_option_changed event*/ sl_btmesh_evt_silabs_config_server_network_pdu_changed_t evt_silabs_config_server_network_pdu_changed; /**< Data field for silabs_config_server network_pdu_changed event*/ sl_btmesh_evt_diagnostic_relay_t evt_diagnostic_relay; /**< Data field for diagnostic relay event*/ + sl_btmesh_evt_diagnostic_friend_queue_t evt_diagnostic_friend_queue; /**< Data field for diagnostic friend_queue event*/ + sl_btmesh_evt_diagnostic_friend_relay_t evt_diagnostic_friend_relay; /**< Data field for diagnostic friend_relay event*/ + sl_btmesh_evt_diagnostic_friend_remove_t evt_diagnostic_friend_remove; /**< Data field for diagnostic friend_remove event*/ uint8_t payload[SL_BGAPI_MAX_PAYLOAD_SIZE]; } data; }); diff --git a/protocol/bluetooth/inc/sl_btmesh_capi_types.h b/protocol/bluetooth/inc/sl_btmesh_capi_types.h index 01f2f7f60d..1d7beca540 100644 --- a/protocol/bluetooth/inc/sl_btmesh_capi_types.h +++ b/protocol/bluetooth/inc/sl_btmesh_capi_types.h @@ -709,6 +709,16 @@ typedef enum { mesh_instr_tx_complete = 0x22, mesh_instr_tx_cancelled = 0x23, + + mesh_instr_friend_pdu_queued = 0x24, + mesh_instr_friend_pdu_relayed = 0x25, + mesh_instr_friend_pdu_removed = 0x26, + + mesh_instr_trans_sdu_handled = 0x27, + mesh_instr_trans_sdu_not_handled = 0x28, + + mesh_instr_trans_sdu_decryption_failure = 0x29, + mesh_instr_trans_sdu_decrypted = 0x2a, } mesh_instr_event_t; /** Instrumentation result codes for dropping a network PDU */ @@ -717,6 +727,7 @@ typedef enum { mesh_instr_net_pdu_dropped_invalid_src = 0x01, mesh_instr_net_pdu_dropped_invalid_dst = 0x02, mesh_instr_net_pdu_dropped_internal_error = 0x03, + mesh_instr_net_pdu_dropped_lpn_discard = 0x04, mesh_instr_net_pdu_dropped_reason_last } mesh_instr_net_pdu_dropped_reason_t; @@ -732,6 +743,7 @@ typedef enum { mesh_instr_net_pdu_not_relayed_hop_limit = 0x01, mesh_instr_net_pdu_not_relayed_out_of_memory = 0x02, mesh_instr_net_pdu_not_relayed_internal_error = 0x03, + mesh_instr_net_pdu_not_relayed_no_proxy = 0x04, mesh_instr_net_pdu_not_relayed_reason_last } mesh_instr_net_pdu_not_relayed_reason_t; @@ -754,9 +766,19 @@ typedef enum { mesh_instr_trans_pdu_not_handled_out_of_recv = 0x06, mesh_instr_trans_pdu_not_handled_out_of_memory = 0x07, mesh_instr_trans_pdu_not_handled_header_mismatch = 0x08, + mesh_instr_trans_pdu_not_handled_replayed_pdu = 0x09, + mesh_instr_trans_pdu_not_handled_internal_error = 0x0a, mesh_instr_trans_pdu_not_handled_reason_last } mesh_instr_trans_pdu_not_handled_reason_t; +/** Instrumentation result codes for not handling a received transport SDU */ +typedef enum { + mesh_instr_trans_sdu_not_handled_lpn_message = 0x00, + mesh_instr_trans_sdu_not_handled_no_decryption = 0x01, + mesh_instr_trans_sdu_not_handled_internal_error = 0x02, + mesh_instr_trans_sdu_not_handled_reason_last +} mesh_instr_trans_sdu_not_handled_reason_t; + /** Instrumentation result codes for not sending a transport layer acknowledgement */ typedef enum { mesh_instr_trans_ack_not_sent_out_of_memory = 0x00, @@ -810,6 +832,15 @@ typedef enum { mesh_instr_trans_send_status_last } mesh_instr_trans_send_status_t; +/** Instrumentation result codes for removing a PDU from network queue */ +typedef enum { + mesh_instr_friend_pdu_removed_sent = 0x00, + mesh_instr_friend_pdu_removed_old_pdu = 0x01, + mesh_instr_friend_pdu_removed_old_segack = 0x02, + mesh_instr_friend_pdu_removed_old_segment = 0x03, + mesh_instr_friend_pdu_removed_reason_last, +} mesh_instr_friend_pdu_removed_reason_t; + /** Mesh stack statistics counters */ typedef struct { /** Network decryption failure counter */ @@ -873,6 +904,22 @@ typedef struct { uint32_t trans_sender_timer_set; /** Transport sender timer expired counter */ uint32_t trans_sender_timer_expired; + + /** Friend PDU queued counter */ + uint32_t friend_pdu_queued; + /** Friend PDU relayed counter */ + uint32_t friend_pdu_relayed; + /** Friend PDU removed counter */ + uint32_t friend_pdu_removed[mesh_instr_friend_pdu_removed_reason_last]; + + /** Transport SDU processed counter */ + uint32_t trans_sdu_handled; + /** Transport SDU not handled counter */ + uint32_t trans_sdu_not_handled[mesh_instr_trans_sdu_not_handled_reason_last]; + /** Transport decryption failure counter */ + uint32_t trans_sdu_decryption_failure; + /** Transport decryption success counter */ + uint32_t trans_sdu_decrypted; } mesh_statistics_t; /** Instrumentation result codes for not sending an advertisement */ diff --git a/protocol/bluetooth/inc/sli_btmesh_api.h b/protocol/bluetooth/inc/sli_btmesh_api.h index 4b3e68bc86..da0ec69bae 100644 --- a/protocol/bluetooth/inc/sli_btmesh_api.h +++ b/protocol/bluetooth/inc/sli_btmesh_api.h @@ -124,6 +124,10 @@ enum sli_btmesh_command_id sli_btmesh_node_set_oob_uri_command_id = 0x33, sli_btmesh_node_get_oob_uri_command_id = 0x34, sli_btmesh_node_set_proxy_service_uuid_command_id = 0x35, + sli_btmesh_node_set_proxy_service_scan_response_command_id = 0x37, + sli_btmesh_node_clear_proxy_service_scan_response_command_id = 0x38, + sli_btmesh_node_set_provisioning_service_scan_response_command_id = 0x39, + sli_btmesh_node_clear_provisioning_service_scan_response_command_id = 0x3a, sli_btmesh_prov_init_command_id = 0x00, sli_btmesh_prov_scan_unprov_beacons_command_id = 0x01, sli_btmesh_prov_create_provisioning_session_command_id = 0x41, @@ -186,6 +190,7 @@ enum sli_btmesh_command_id sli_btmesh_vendor_model_deinit_command_id = 0x05, sli_btmesh_vendor_model_send_tracked_command_id = 0x06, sli_btmesh_vendor_model_set_publication_tracked_command_id = 0x07, + sli_btmesh_vendor_model_set_option_command_id = 0x08, sli_btmesh_health_client_init_command_id = 0x07, sli_btmesh_health_client_deinit_command_id = 0x08, sli_btmesh_health_client_get_command_id = 0x00, @@ -589,6 +594,9 @@ enum sli_btmesh_command_id sli_btmesh_diagnostic_get_relay_command_id = 0x04, sli_btmesh_diagnostic_get_statistics_command_id = 0x05, sli_btmesh_diagnostic_clear_statistics_command_id = 0x06, + sli_btmesh_diagnostic_enable_friend_command_id = 0x07, + sli_btmesh_diagnostic_disable_friend_command_id = 0x08, + sli_btmesh_diagnostic_get_friend_command_id = 0x09, }; enum sli_btmesh_response_id @@ -637,6 +645,10 @@ enum sli_btmesh_response_id sli_btmesh_node_set_oob_uri_response_id = 0x33, sli_btmesh_node_get_oob_uri_response_id = 0x34, sli_btmesh_node_set_proxy_service_uuid_response_id = 0x35, + sli_btmesh_node_set_proxy_service_scan_response_response_id = 0x37, + sli_btmesh_node_clear_proxy_service_scan_response_response_id = 0x38, + sli_btmesh_node_set_provisioning_service_scan_response_response_id = 0x39, + sli_btmesh_node_clear_provisioning_service_scan_response_response_id = 0x3a, sli_btmesh_prov_init_response_id = 0x00, sli_btmesh_prov_scan_unprov_beacons_response_id = 0x01, sli_btmesh_prov_create_provisioning_session_response_id = 0x41, @@ -699,6 +711,7 @@ enum sli_btmesh_response_id sli_btmesh_vendor_model_deinit_response_id = 0x05, sli_btmesh_vendor_model_send_tracked_response_id = 0x06, sli_btmesh_vendor_model_set_publication_tracked_response_id = 0x07, + sli_btmesh_vendor_model_set_option_response_id = 0x08, sli_btmesh_health_client_init_response_id = 0x07, sli_btmesh_health_client_deinit_response_id = 0x08, sli_btmesh_health_client_get_response_id = 0x00, @@ -1102,6 +1115,9 @@ enum sli_btmesh_response_id sli_btmesh_diagnostic_get_relay_response_id = 0x04, sli_btmesh_diagnostic_get_statistics_response_id = 0x05, sli_btmesh_diagnostic_clear_statistics_response_id = 0x06, + sli_btmesh_diagnostic_enable_friend_response_id = 0x07, + sli_btmesh_diagnostic_disable_friend_response_id = 0x08, + sli_btmesh_diagnostic_get_friend_response_id = 0x09, }; enum sli_btmesh_event_id @@ -1350,6 +1366,9 @@ enum sli_btmesh_event_id sli_btmesh_silabs_config_server_model_option_changed_event_id = 0x01, sli_btmesh_silabs_config_server_network_pdu_changed_event_id = 0x02, sli_btmesh_diagnostic_relay_event_id = 0x00, + sli_btmesh_diagnostic_friend_queue_event_id = 0x01, + sli_btmesh_diagnostic_friend_relay_event_id = 0x02, + sli_btmesh_diagnostic_friend_remove_event_id = 0x03, }; PACKSTRUCT( struct sl_bt_rsp_error_s @@ -1580,6 +1599,31 @@ PACKSTRUCT( struct sl_btmesh_cmd_node_set_proxy_service_uuid_s typedef struct sl_btmesh_cmd_node_set_proxy_service_uuid_s sl_btmesh_cmd_node_set_proxy_service_uuid_t; +PACKSTRUCT( struct sl_btmesh_cmd_node_set_proxy_service_scan_response_s +{ + uint16_t netkey_index; + uint8array scan_response_data; +}); + +typedef struct sl_btmesh_cmd_node_set_proxy_service_scan_response_s sl_btmesh_cmd_node_set_proxy_service_scan_response_t; + + +PACKSTRUCT( struct sl_btmesh_cmd_node_clear_proxy_service_scan_response_s +{ + uint16_t netkey_index; +}); + +typedef struct sl_btmesh_cmd_node_clear_proxy_service_scan_response_s sl_btmesh_cmd_node_clear_proxy_service_scan_response_t; + + +PACKSTRUCT( struct sl_btmesh_cmd_node_set_provisioning_service_scan_response_s +{ + uint8array scan_response_data; +}); + +typedef struct sl_btmesh_cmd_node_set_provisioning_service_scan_response_s sl_btmesh_cmd_node_set_provisioning_service_scan_response_t; + + PACKSTRUCT( struct sl_btmesh_cmd_prov_create_provisioning_session_s { uint16_t netkey_index; @@ -2116,6 +2160,15 @@ PACKSTRUCT( struct sl_btmesh_cmd_vendor_model_set_publication_tracked_s typedef struct sl_btmesh_cmd_vendor_model_set_publication_tracked_s sl_btmesh_cmd_vendor_model_set_publication_tracked_t; +PACKSTRUCT( struct sl_btmesh_cmd_vendor_model_set_option_s +{ + uint8_t option; + uint32_t value; +}); + +typedef struct sl_btmesh_cmd_vendor_model_set_option_s sl_btmesh_cmd_vendor_model_set_option_t; + + PACKSTRUCT( struct sl_btmesh_cmd_health_client_get_s { uint16_t server_address; @@ -5438,6 +5491,15 @@ PACKSTRUCT( struct sl_btmesh_cmd_silabs_config_server_set_network_pdu_s typedef struct sl_btmesh_cmd_silabs_config_server_set_network_pdu_s sl_btmesh_cmd_silabs_config_server_set_network_pdu_t; +PACKSTRUCT( struct sl_btmesh_cmd_diagnostic_get_statistics_s +{ + uint32_t requested_chunk; + uint32_t requested_offset; +}); + +typedef struct sl_btmesh_cmd_diagnostic_get_statistics_s sl_btmesh_cmd_diagnostic_get_statistics_t; + + PACKSTRUCT( struct sl_btmesh_rsp_node_init_s @@ -5813,6 +5875,38 @@ PACKSTRUCT( struct sl_btmesh_rsp_node_set_proxy_service_uuid_s typedef struct sl_btmesh_rsp_node_set_proxy_service_uuid_s sl_btmesh_rsp_node_set_proxy_service_uuid_t; +PACKSTRUCT( struct sl_btmesh_rsp_node_set_proxy_service_scan_response_s +{ + uint16_t result; +}); + +typedef struct sl_btmesh_rsp_node_set_proxy_service_scan_response_s sl_btmesh_rsp_node_set_proxy_service_scan_response_t; + + +PACKSTRUCT( struct sl_btmesh_rsp_node_clear_proxy_service_scan_response_s +{ + uint16_t result; +}); + +typedef struct sl_btmesh_rsp_node_clear_proxy_service_scan_response_s sl_btmesh_rsp_node_clear_proxy_service_scan_response_t; + + +PACKSTRUCT( struct sl_btmesh_rsp_node_set_provisioning_service_scan_response_s +{ + uint16_t result; +}); + +typedef struct sl_btmesh_rsp_node_set_provisioning_service_scan_response_s sl_btmesh_rsp_node_set_provisioning_service_scan_response_t; + + +PACKSTRUCT( struct sl_btmesh_rsp_node_clear_provisioning_service_scan_response_s +{ + uint16_t result; +}); + +typedef struct sl_btmesh_rsp_node_clear_provisioning_service_scan_response_s sl_btmesh_rsp_node_clear_provisioning_service_scan_response_t; + + PACKSTRUCT( struct sl_btmesh_rsp_prov_init_s { uint16_t result; @@ -6323,6 +6417,14 @@ PACKSTRUCT( struct sl_btmesh_rsp_vendor_model_set_publication_tracked_s typedef struct sl_btmesh_rsp_vendor_model_set_publication_tracked_s sl_btmesh_rsp_vendor_model_set_publication_tracked_t; +PACKSTRUCT( struct sl_btmesh_rsp_vendor_model_set_option_s +{ + uint16_t result; +}); + +typedef struct sl_btmesh_rsp_vendor_model_set_option_s sl_btmesh_rsp_vendor_model_set_option_t; + + PACKSTRUCT( struct sl_btmesh_rsp_health_client_init_s { uint16_t result; @@ -9741,6 +9843,8 @@ typedef struct sl_btmesh_rsp_diagnostic_get_relay_s sl_btmesh_rsp_diagnostic_get PACKSTRUCT( struct sl_btmesh_rsp_diagnostic_get_statistics_s { uint16_t result; + uint32_t total_length; + uint32_t chunk_offset; uint8array statistics; }); @@ -9755,6 +9859,36 @@ PACKSTRUCT( struct sl_btmesh_rsp_diagnostic_clear_statistics_s typedef struct sl_btmesh_rsp_diagnostic_clear_statistics_s sl_btmesh_rsp_diagnostic_clear_statistics_t; +PACKSTRUCT( struct sl_btmesh_rsp_diagnostic_enable_friend_s +{ + uint16_t result; +}); + +typedef struct sl_btmesh_rsp_diagnostic_enable_friend_s sl_btmesh_rsp_diagnostic_enable_friend_t; + + +PACKSTRUCT( struct sl_btmesh_rsp_diagnostic_disable_friend_s +{ + uint16_t result; +}); + +typedef struct sl_btmesh_rsp_diagnostic_disable_friend_s sl_btmesh_rsp_diagnostic_disable_friend_t; + + +PACKSTRUCT( struct sl_btmesh_rsp_diagnostic_get_friend_s +{ + uint16_t result; + uint32_t queue_counter; + uint32_t relay_counter; + uint32_t remove_counter_sent; + uint32_t remove_counter_old_pdu; + uint32_t remove_counter_old_segack; + uint32_t remove_counter_old_segment; +}); + +typedef struct sl_btmesh_rsp_diagnostic_get_friend_s sl_btmesh_rsp_diagnostic_get_friend_t; + + PACKSTRUCT( struct sl_btmesh_packet { uint32_t header; @@ -9786,6 +9920,9 @@ PACKSTRUCT( struct sl_btmesh_packet { sl_btmesh_cmd_node_get_local_model_metadata_page_t cmd_node_get_local_model_metadata_page; sl_btmesh_cmd_node_set_oob_uri_t cmd_node_set_oob_uri; sl_btmesh_cmd_node_set_proxy_service_uuid_t cmd_node_set_proxy_service_uuid; + sl_btmesh_cmd_node_set_proxy_service_scan_response_t cmd_node_set_proxy_service_scan_response; + sl_btmesh_cmd_node_clear_proxy_service_scan_response_t cmd_node_clear_proxy_service_scan_response; + sl_btmesh_cmd_node_set_provisioning_service_scan_response_t cmd_node_set_provisioning_service_scan_response; sl_btmesh_cmd_prov_create_provisioning_session_t cmd_prov_create_provisioning_session; sl_btmesh_cmd_prov_set_provisioning_suspend_event_t cmd_prov_set_provisioning_suspend_event; sl_btmesh_cmd_prov_provision_adv_device_t cmd_prov_provision_adv_device; @@ -9840,6 +9977,7 @@ PACKSTRUCT( struct sl_btmesh_packet { sl_btmesh_cmd_vendor_model_deinit_t cmd_vendor_model_deinit; sl_btmesh_cmd_vendor_model_send_tracked_t cmd_vendor_model_send_tracked; sl_btmesh_cmd_vendor_model_set_publication_tracked_t cmd_vendor_model_set_publication_tracked; + sl_btmesh_cmd_vendor_model_set_option_t cmd_vendor_model_set_option; sl_btmesh_cmd_health_client_get_t cmd_health_client_get; sl_btmesh_cmd_health_client_clear_t cmd_health_client_clear; sl_btmesh_cmd_health_client_test_t cmd_health_client_test; @@ -10161,6 +10299,7 @@ PACKSTRUCT( struct sl_btmesh_packet { sl_btmesh_cmd_silabs_config_server_set_model_enable_t cmd_silabs_config_server_set_model_enable; sl_btmesh_cmd_silabs_config_server_get_model_enable_t cmd_silabs_config_server_get_model_enable; sl_btmesh_cmd_silabs_config_server_set_network_pdu_t cmd_silabs_config_server_set_network_pdu; + sl_btmesh_cmd_diagnostic_get_statistics_t cmd_diagnostic_get_statistics; sl_btmesh_rsp_node_init_t rsp_node_init; sl_btmesh_rsp_node_set_exportable_keys_t rsp_node_set_exportable_keys; sl_btmesh_rsp_node_start_unprov_beaconing_t rsp_node_start_unprov_beaconing; @@ -10205,6 +10344,10 @@ PACKSTRUCT( struct sl_btmesh_packet { sl_btmesh_rsp_node_set_oob_uri_t rsp_node_set_oob_uri; sl_btmesh_rsp_node_get_oob_uri_t rsp_node_get_oob_uri; sl_btmesh_rsp_node_set_proxy_service_uuid_t rsp_node_set_proxy_service_uuid; + sl_btmesh_rsp_node_set_proxy_service_scan_response_t rsp_node_set_proxy_service_scan_response; + sl_btmesh_rsp_node_clear_proxy_service_scan_response_t rsp_node_clear_proxy_service_scan_response; + sl_btmesh_rsp_node_set_provisioning_service_scan_response_t rsp_node_set_provisioning_service_scan_response; + sl_btmesh_rsp_node_clear_provisioning_service_scan_response_t rsp_node_clear_provisioning_service_scan_response; sl_btmesh_rsp_prov_init_t rsp_prov_init; sl_btmesh_rsp_prov_scan_unprov_beacons_t rsp_prov_scan_unprov_beacons; sl_btmesh_rsp_prov_create_provisioning_session_t rsp_prov_create_provisioning_session; @@ -10267,6 +10410,7 @@ PACKSTRUCT( struct sl_btmesh_packet { sl_btmesh_rsp_vendor_model_deinit_t rsp_vendor_model_deinit; sl_btmesh_rsp_vendor_model_send_tracked_t rsp_vendor_model_send_tracked; sl_btmesh_rsp_vendor_model_set_publication_tracked_t rsp_vendor_model_set_publication_tracked; + sl_btmesh_rsp_vendor_model_set_option_t rsp_vendor_model_set_option; sl_btmesh_rsp_health_client_init_t rsp_health_client_init; sl_btmesh_rsp_health_client_deinit_t rsp_health_client_deinit; sl_btmesh_rsp_health_client_get_t rsp_health_client_get; @@ -10670,6 +10814,9 @@ PACKSTRUCT( struct sl_btmesh_packet { sl_btmesh_rsp_diagnostic_get_relay_t rsp_diagnostic_get_relay; sl_btmesh_rsp_diagnostic_get_statistics_t rsp_diagnostic_get_statistics; sl_btmesh_rsp_diagnostic_clear_statistics_t rsp_diagnostic_clear_statistics; + sl_btmesh_rsp_diagnostic_enable_friend_t rsp_diagnostic_enable_friend; + sl_btmesh_rsp_diagnostic_disable_friend_t rsp_diagnostic_disable_friend; + sl_btmesh_rsp_diagnostic_get_friend_t rsp_diagnostic_get_friend; sl_btmesh_evt_node_initialized_t evt_node_initialized; sl_btmesh_evt_node_provisioned_t evt_node_provisioned; sl_btmesh_evt_node_config_get_t evt_node_config_get; @@ -10910,6 +11057,9 @@ PACKSTRUCT( struct sl_btmesh_packet { sl_btmesh_evt_silabs_config_server_model_option_changed_t evt_silabs_config_server_model_option_changed; sl_btmesh_evt_silabs_config_server_network_pdu_changed_t evt_silabs_config_server_network_pdu_changed; sl_btmesh_evt_diagnostic_relay_t evt_diagnostic_relay; + sl_btmesh_evt_diagnostic_friend_queue_t evt_diagnostic_friend_queue; + sl_btmesh_evt_diagnostic_friend_relay_t evt_diagnostic_friend_relay; + sl_btmesh_evt_diagnostic_friend_remove_t evt_diagnostic_friend_remove; uint8_t payload[SL_BGAPI_MAX_PAYLOAD_SIZE]; } data; }); diff --git a/protocol/bluetooth/lib/EFR32XG1/GCC/binapploader.o b/protocol/bluetooth/lib/EFR32XG1/GCC/binapploader.o index bbe57889c9..e397abb4ed 100644 --- a/protocol/bluetooth/lib/EFR32XG1/GCC/binapploader.o +++ b/protocol/bluetooth/lib/EFR32XG1/GCC/binapploader.o @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid 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https://git-lfs.github.com/spec/v1 -oid sha256:698f59ab8be714be41bd7bc6682fbed57f96c3f9f466432046902765071edc2a -size 2127078 +oid sha256:d368fec94b308d6d2f8a556af16213be6b1e2224572386c88e32d395042b5bdf +size 2148182 diff --git a/protocol/bluetooth/lib/EFR32XG12/GCC/libbtmesh_dfu_ncp_fw_list.a b/protocol/bluetooth/lib/EFR32XG12/GCC/libbtmesh_dfu_ncp_fw_list.a index 56af8a8187..33028026f2 100644 --- a/protocol/bluetooth/lib/EFR32XG12/GCC/libbtmesh_dfu_ncp_fw_list.a +++ b/protocol/bluetooth/lib/EFR32XG12/GCC/libbtmesh_dfu_ncp_fw_list.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c55c5d9cda66e51ab521b025d5d8cff331b037ad41c0e6dd248178e7d5b20596 +oid sha256:e1f0613259f12f6f8332f2ef6b78510f6246ac2cc197176df6e43ee374ffeb67 size 6778 diff --git a/protocol/bluetooth/lib/EFR32XG12/GCC/libbtmesh_model_dfu.a b/protocol/bluetooth/lib/EFR32XG12/GCC/libbtmesh_model_dfu.a index 9c46b9424e..944e6b77de 100644 --- a/protocol/bluetooth/lib/EFR32XG12/GCC/libbtmesh_model_dfu.a +++ b/protocol/bluetooth/lib/EFR32XG12/GCC/libbtmesh_model_dfu.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:baf5ad3f60e1393ef765e53843300272dff91bd4dc52f079dde0c2020a672ef5 +oid sha256:0687db3c66b1b2b041ca2428e35740440d95ac1b0492b4ad401fd3520a488c98 size 84522 diff --git a/protocol/bluetooth/lib/EFR32XG12/GCC/libbtmesh_model_mbt.a b/protocol/bluetooth/lib/EFR32XG12/GCC/libbtmesh_model_mbt.a index d8df7c82c7..bfdf326286 100644 --- a/protocol/bluetooth/lib/EFR32XG12/GCC/libbtmesh_model_mbt.a +++ b/protocol/bluetooth/lib/EFR32XG12/GCC/libbtmesh_model_mbt.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e3a123c933c9bdce0cb64c8e422593fcb0179b6d22fa264bc9e76635cab4cb9d +oid sha256:57971ec031292b127e382267e6b5dfd2d1e990409bddeb058e26ac9808f3a2a1 size 40948 diff --git a/protocol/bluetooth/lib/EFR32XG12/GCC/libpsstore.a b/protocol/bluetooth/lib/EFR32XG12/GCC/libpsstore.a index bdbc578dd6..cb6d22b7a1 100644 --- a/protocol/bluetooth/lib/EFR32XG12/GCC/libpsstore.a +++ b/protocol/bluetooth/lib/EFR32XG12/GCC/libpsstore.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b4ea17b333703ce7937e0f050439a32b709b9fc5b483315c53cfe3fbe39d8798 +oid sha256:6dfd2468ca500c1b9b7fd27f88eef893451abd2ee157cb5547b6aae0e64c8cfc size 12846 diff --git a/protocol/bluetooth/lib/EFR32XG12/IAR/binapploader.o b/protocol/bluetooth/lib/EFR32XG12/IAR/binapploader.o index c5732e0053..15391da9a4 100644 --- a/protocol/bluetooth/lib/EFR32XG12/IAR/binapploader.o +++ b/protocol/bluetooth/lib/EFR32XG12/IAR/binapploader.o @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3777619de4ce46e1c24ec0cbfddb7b409420d8222b7f50c41eed14e718f71030 +oid sha256:66b3d59e0eb33db52411adeb85dc123a98113af3facd6672b86433a2b6310965 size 47652 diff --git a/protocol/bluetooth/lib/EFR32XG12/IAR/binapploader_nvm3.o b/protocol/bluetooth/lib/EFR32XG12/IAR/binapploader_nvm3.o index 8d9424f86e..1d3f0259e8 100644 --- a/protocol/bluetooth/lib/EFR32XG12/IAR/binapploader_nvm3.o +++ b/protocol/bluetooth/lib/EFR32XG12/IAR/binapploader_nvm3.o @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:419f250132f2605b31bea66464b4adf8d66f53c8c460be5180fe330657c669d5 +oid sha256:f3a9bfdf485737125d0a1864ddfe2128045dd3e04812190d9d31de255c865792 size 53796 diff --git a/protocol/bluetooth/lib/EFR32XG12/IAR/libbluetooth_mesh.a b/protocol/bluetooth/lib/EFR32XG12/IAR/libbluetooth_mesh.a index a878246da6..635255dbb2 100644 --- a/protocol/bluetooth/lib/EFR32XG12/IAR/libbluetooth_mesh.a +++ b/protocol/bluetooth/lib/EFR32XG12/IAR/libbluetooth_mesh.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:25213cc51d5820fbdd90f84bd34d73a60bb19f2d732d71b556a24b30661e0ddf -size 5819782 +oid sha256:b05c008236e0a42721645ea679538a0970e3708253a8c4bf464f879475b5f700 +size 5867222 diff --git a/protocol/bluetooth/lib/EFR32XG12/IAR/libbtmesh_dfu_ncp_fw_list.a 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sha256:25107f5c74c199a99832ddce3f5c5295bdfa1554e90c7cf31197f90603452252 -size 1448806 +oid sha256:72fd50a618f119bded41693fcb8d37e681366e274c1a0b4c62bd59ecf9207a10 +size 1445878 diff --git a/protocol/bluetooth/lib/libbluetooth_host_efr32xg14_iar_release.a b/protocol/bluetooth/lib/libbluetooth_host_efr32xg14_iar_release.a index 046085b085..fd6a956d03 100644 --- a/protocol/bluetooth/lib/libbluetooth_host_efr32xg14_iar_release.a +++ b/protocol/bluetooth/lib/libbluetooth_host_efr32xg14_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a1b408baa5ec6d1ce3ded3cdac5c93aa0dafa942805f61847028b4dd0772d8b2 -size 3799440 +oid sha256:115a387a3d079fca64dc8a22f78a48e0c8faf831c5a6df80f62d75dcb21d6049 +size 3783776 diff --git a/protocol/bluetooth/lib/libbluetooth_host_efr32xg1_gcc_release.a b/protocol/bluetooth/lib/libbluetooth_host_efr32xg1_gcc_release.a index 45d0c1036b..23ad46a73f 100644 --- a/protocol/bluetooth/lib/libbluetooth_host_efr32xg1_gcc_release.a +++ b/protocol/bluetooth/lib/libbluetooth_host_efr32xg1_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3e2a230aad4b35c0a90ead3c987966bb7705707843b06d3e83cd9a3a852d337b -size 1278188 +oid sha256:0ccafe15efb1ddb1e2704bee6f7da8f5326d3f712ca1551f3aaf06ea1ed6c11e +size 1275260 diff --git a/protocol/bluetooth/lib/libbluetooth_host_efr32xg1_iar_release.a b/protocol/bluetooth/lib/libbluetooth_host_efr32xg1_iar_release.a index 9c643530f1..b1078bb560 100644 --- a/protocol/bluetooth/lib/libbluetooth_host_efr32xg1_iar_release.a +++ b/protocol/bluetooth/lib/libbluetooth_host_efr32xg1_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:690ee914a4a1345d2450014c0cd76a6226394cf7819d6bf2d96ca4408cd1969b -size 3412596 +oid sha256:61ef2f94a0a583f6a960902b2967530bb03dc1b708e7e14880a826b121c62de6 +size 3396936 diff --git a/protocol/bluetooth/lib/libbluetooth_host_efr32xg21_gcc_release.a b/protocol/bluetooth/lib/libbluetooth_host_efr32xg21_gcc_release.a index 6fee0a0118..573a48ea00 100644 --- a/protocol/bluetooth/lib/libbluetooth_host_efr32xg21_gcc_release.a +++ b/protocol/bluetooth/lib/libbluetooth_host_efr32xg21_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4bcdd947dc472d9b3da3d2c3d54a18f3a48f4b434f0ac5ad8ea23183abc42475 -size 1455468 +oid sha256:85a2ed6f9e8a7339fd9e5590948848dd2d156872de67886e055ced0dc57d8110 +size 1452520 diff --git a/protocol/bluetooth/lib/libbluetooth_host_efr32xg21_iar_release.a b/protocol/bluetooth/lib/libbluetooth_host_efr32xg21_iar_release.a index 2b6c43f366..c2084f56d3 100644 --- a/protocol/bluetooth/lib/libbluetooth_host_efr32xg21_iar_release.a +++ b/protocol/bluetooth/lib/libbluetooth_host_efr32xg21_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:943367f66c89937958742217573c017876796249ee8932e27d6b9c172d068703 -size 3799930 +oid sha256:1e4af10add78a01560561c546d65d823a61f84b758511ef398d7d6dc116e02cf +size 3784270 diff --git a/protocol/bluetooth/lib/libbluetooth_host_efr32xg22_gcc_release.a b/protocol/bluetooth/lib/libbluetooth_host_efr32xg22_gcc_release.a index ee846f26be..31121d2830 100644 --- a/protocol/bluetooth/lib/libbluetooth_host_efr32xg22_gcc_release.a +++ b/protocol/bluetooth/lib/libbluetooth_host_efr32xg22_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:859324546ec7a481a3b06f7bb2f69cf2957e10f1a0cbe1f8fb6e236dc800d1e2 -size 1455312 +oid sha256:00dc7c457c6e1fffb1013859b26e79a435d17303cabb929ff1aaf361510a34a6 +size 1452364 diff --git a/protocol/bluetooth/lib/libbluetooth_host_efr32xg22_iar_release.a b/protocol/bluetooth/lib/libbluetooth_host_efr32xg22_iar_release.a index 5180e9817d..7a56ac1034 100644 --- a/protocol/bluetooth/lib/libbluetooth_host_efr32xg22_iar_release.a +++ b/protocol/bluetooth/lib/libbluetooth_host_efr32xg22_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4d709dc2251b7fc65ca1cdf9c76b07e18c4ec95a53fa51b90c9b1145483d8944 -size 3799638 +oid sha256:683c841ad7fdfcbc7f232a38e67acf59db20826196f0c692f2d1e3d20f071bbc +size 3783974 diff --git a/protocol/bluetooth/lib/libbluetooth_host_efr32xg24_gcc_release.a b/protocol/bluetooth/lib/libbluetooth_host_efr32xg24_gcc_release.a index e75d1f0e0d..316e5b952d 100644 --- a/protocol/bluetooth/lib/libbluetooth_host_efr32xg24_gcc_release.a +++ b/protocol/bluetooth/lib/libbluetooth_host_efr32xg24_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cde8ce71c29f2fa77c4bb5f5050768cc01548b3591e34c44f43ee2c390b2c670 -size 1455468 +oid sha256:a7826f1b4ca59ccb7757285398bf6b28a6723fa597b56cce37d0ce2cd7141fbc +size 1452520 diff --git a/protocol/bluetooth/lib/libbluetooth_host_efr32xg24_iar_release.a b/protocol/bluetooth/lib/libbluetooth_host_efr32xg24_iar_release.a index cb8c4935f0..22db1b40a4 100644 --- a/protocol/bluetooth/lib/libbluetooth_host_efr32xg24_iar_release.a +++ b/protocol/bluetooth/lib/libbluetooth_host_efr32xg24_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e8fb27af2e299fc2cab60aeff66a57cf7725b498f8463f59b9dbce9933acf686 -size 3799930 +oid sha256:4e38ab93b1247d405897069c6e591a8cecc9516c308cd0c8cbcee4f0a80a5e43 +size 3784270 diff --git a/protocol/bluetooth/lib/libbluetooth_host_efr32xg27_gcc_release.a b/protocol/bluetooth/lib/libbluetooth_host_efr32xg27_gcc_release.a index b54fd1d3e7..7be93b70c1 100644 --- a/protocol/bluetooth/lib/libbluetooth_host_efr32xg27_gcc_release.a +++ b/protocol/bluetooth/lib/libbluetooth_host_efr32xg27_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ee8a165ead89d3bf6d595a462badd3ff89fd94c3920fbf4db683bd87427ca553 -size 1455312 +oid sha256:affb431b72de7265c949ddae63149a46bed2dfd1b19912a97e48e7e5a3237a3c +size 1452364 diff --git a/protocol/bluetooth/lib/libbluetooth_host_efr32xg27_iar_release.a b/protocol/bluetooth/lib/libbluetooth_host_efr32xg27_iar_release.a index db054e1e05..4ba1ae1c1f 100644 --- a/protocol/bluetooth/lib/libbluetooth_host_efr32xg27_iar_release.a +++ b/protocol/bluetooth/lib/libbluetooth_host_efr32xg27_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3c97bdc1a098c9f9e19d8beae51e5dc2ec45dbc7675cefb2cde75f0db1be087b -size 3799638 +oid sha256:3de8e2acbf764099b14472e99642ef2b22057e76d8d1c2da0993fc551224701d +size 3783974 diff --git a/protocol/bluetooth/lib/libbluetooth_host_efr32xg28_gcc_release.a b/protocol/bluetooth/lib/libbluetooth_host_efr32xg28_gcc_release.a index 36bc89f135..f3000b9134 100644 --- a/protocol/bluetooth/lib/libbluetooth_host_efr32xg28_gcc_release.a +++ b/protocol/bluetooth/lib/libbluetooth_host_efr32xg28_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:df4c314b3beb1248d5208a1034720a527f2a1e390c18f6f528cbaa95ec46a96d -size 1455468 +oid sha256:4fb074eac85b88a9d2f9831f1433d829c58b16e2ac889ba8f0945be16c3832bd +size 1452520 diff --git a/protocol/bluetooth/lib/libbluetooth_host_efr32xg28_iar_release.a b/protocol/bluetooth/lib/libbluetooth_host_efr32xg28_iar_release.a index a707dec553..3f428f03ee 100644 --- a/protocol/bluetooth/lib/libbluetooth_host_efr32xg28_iar_release.a +++ b/protocol/bluetooth/lib/libbluetooth_host_efr32xg28_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a17f9ef9ed33f41cd2c8d7db1e6121a4b4962049014f0f2844a0c9e7e1eef48a -size 3799930 +oid sha256:f9ee4b5f4e5b11e3beb4c39f6d573f96be653e8798d0a6e069401058c24d977d +size 3784270 diff --git a/protocol/bluetooth/src/sl_btmesh_ncp_host_api.c b/protocol/bluetooth/src/sl_btmesh_ncp_host_api.c index a7aee6c19b..be8c537d78 100644 --- a/protocol/bluetooth/src/sl_btmesh_ncp_host_api.c +++ b/protocol/bluetooth/src/sl_btmesh_ncp_host_api.c @@ -804,6 +804,79 @@ sl_status_t sl_btmesh_node_set_proxy_service_uuid(uint16_t uuid) { } +sl_status_t sl_btmesh_node_set_proxy_service_scan_response(uint16_t netkey_index, + size_t scan_response_data_len, + const uint8_t* scan_response_data) { + struct sl_btmesh_packet *cmd = (struct sl_btmesh_packet *)sl_btmesh_cmd_msg; + + struct sl_btmesh_packet *rsp = (struct sl_btmesh_packet *)sl_btmesh_rsp_msg; + + cmd->data.cmd_node_set_proxy_service_scan_response.netkey_index=netkey_index; + if ((3+scan_response_data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_node_set_proxy_service_scan_response.scan_response_data.len=scan_response_data_len; + memcpy(cmd->data.cmd_node_set_proxy_service_scan_response.scan_response_data.data,scan_response_data,scan_response_data_len); + + cmd->header=sl_btmesh_cmd_node_set_proxy_service_scan_response_id+(((3+scan_response_data_len)&0xff)<<8)+(((3+scan_response_data_len)&0x700)>>8); + + + sl_btmesh_host_handle_command(); + return rsp->data.rsp_node_set_proxy_service_scan_response.result; + +} + +sl_status_t sl_btmesh_node_clear_proxy_service_scan_response(uint16_t netkey_index) { + struct sl_btmesh_packet *cmd = (struct sl_btmesh_packet *)sl_btmesh_cmd_msg; + + struct sl_btmesh_packet *rsp = (struct sl_btmesh_packet *)sl_btmesh_rsp_msg; + + cmd->data.cmd_node_clear_proxy_service_scan_response.netkey_index=netkey_index; + + cmd->header=sl_btmesh_cmd_node_clear_proxy_service_scan_response_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_btmesh_host_handle_command(); + return rsp->data.rsp_node_clear_proxy_service_scan_response.result; + +} + +sl_status_t sl_btmesh_node_set_provisioning_service_scan_response(size_t scan_response_data_len, + const uint8_t* scan_response_data) { + struct sl_btmesh_packet *cmd = (struct sl_btmesh_packet *)sl_btmesh_cmd_msg; + + struct sl_btmesh_packet *rsp = (struct sl_btmesh_packet *)sl_btmesh_rsp_msg; + + if ((1+scan_response_data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_node_set_provisioning_service_scan_response.scan_response_data.len=scan_response_data_len; + memcpy(cmd->data.cmd_node_set_provisioning_service_scan_response.scan_response_data.data,scan_response_data,scan_response_data_len); + + cmd->header=sl_btmesh_cmd_node_set_provisioning_service_scan_response_id+(((1+scan_response_data_len)&0xff)<<8)+(((1+scan_response_data_len)&0x700)>>8); + + + sl_btmesh_host_handle_command(); + return rsp->data.rsp_node_set_provisioning_service_scan_response.result; + +} + +sl_status_t sl_btmesh_node_clear_provisioning_service_scan_response() { + struct sl_btmesh_packet *cmd = (struct sl_btmesh_packet *)sl_btmesh_cmd_msg; + + struct sl_btmesh_packet *rsp = (struct sl_btmesh_packet *)sl_btmesh_rsp_msg; + + + cmd->header=sl_btmesh_cmd_node_clear_provisioning_service_scan_response_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_btmesh_host_handle_command(); + return rsp->data.rsp_node_clear_provisioning_service_scan_response.result; + +} + sl_status_t sl_btmesh_prov_init() { struct sl_btmesh_packet *cmd = (struct sl_btmesh_packet *)sl_btmesh_cmd_msg; @@ -2060,6 +2133,22 @@ sl_status_t sl_btmesh_vendor_model_set_publication_tracked(uint16_t elem_index, } +sl_status_t sl_btmesh_vendor_model_set_option(uint8_t option, uint32_t value) { + struct sl_btmesh_packet *cmd = (struct sl_btmesh_packet *)sl_btmesh_cmd_msg; + + struct sl_btmesh_packet *rsp = (struct sl_btmesh_packet *)sl_btmesh_rsp_msg; + + cmd->data.cmd_vendor_model_set_option.option=option; + cmd->data.cmd_vendor_model_set_option.value=value; + + cmd->header=sl_btmesh_cmd_vendor_model_set_option_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_btmesh_host_handle_command(); + return rsp->data.rsp_vendor_model_set_option.result; + +} + sl_status_t sl_btmesh_health_client_init() { struct sl_btmesh_packet *cmd = (struct sl_btmesh_packet *)sl_btmesh_cmd_msg; @@ -10593,18 +10682,30 @@ sl_status_t sl_btmesh_diagnostic_get_relay(uint32_t *relay_counter) { } -sl_status_t sl_btmesh_diagnostic_get_statistics(size_t max_statistics_size, +sl_status_t sl_btmesh_diagnostic_get_statistics(uint32_t requested_chunk, + uint32_t requested_offset, + uint32_t *total_length, + uint32_t *chunk_offset, + size_t max_statistics_size, size_t *statistics_len, uint8_t *statistics) { struct sl_btmesh_packet *cmd = (struct sl_btmesh_packet *)sl_btmesh_cmd_msg; struct sl_btmesh_packet *rsp = (struct sl_btmesh_packet *)sl_btmesh_rsp_msg; + cmd->data.cmd_diagnostic_get_statistics.requested_chunk=requested_chunk; + cmd->data.cmd_diagnostic_get_statistics.requested_offset=requested_offset; - cmd->header=sl_btmesh_cmd_diagnostic_get_statistics_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + cmd->header=sl_btmesh_cmd_diagnostic_get_statistics_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); sl_btmesh_host_handle_command(); + if (total_length) { + *total_length = rsp->data.rsp_diagnostic_get_statistics.total_length; + } + if (chunk_offset) { + *chunk_offset = rsp->data.rsp_diagnostic_get_statistics.chunk_offset; + } if (statistics_len) { *statistics_len = rsp->data.rsp_diagnostic_get_statistics.statistics.len; } @@ -10628,3 +10729,68 @@ sl_status_t sl_btmesh_diagnostic_clear_statistics() { return rsp->data.rsp_diagnostic_clear_statistics.result; } + +sl_status_t sl_btmesh_diagnostic_enable_friend() { + struct sl_btmesh_packet *cmd = (struct sl_btmesh_packet *)sl_btmesh_cmd_msg; + + struct sl_btmesh_packet *rsp = (struct sl_btmesh_packet *)sl_btmesh_rsp_msg; + + + cmd->header=sl_btmesh_cmd_diagnostic_enable_friend_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_btmesh_host_handle_command(); + return rsp->data.rsp_diagnostic_enable_friend.result; + +} + +sl_status_t sl_btmesh_diagnostic_disable_friend() { + struct sl_btmesh_packet *cmd = (struct sl_btmesh_packet *)sl_btmesh_cmd_msg; + + struct sl_btmesh_packet *rsp = (struct sl_btmesh_packet *)sl_btmesh_rsp_msg; + + + cmd->header=sl_btmesh_cmd_diagnostic_disable_friend_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_btmesh_host_handle_command(); + return rsp->data.rsp_diagnostic_disable_friend.result; + +} + +sl_status_t sl_btmesh_diagnostic_get_friend(uint32_t *queue_counter, + uint32_t *relay_counter, + uint32_t *remove_counter_sent, + uint32_t *remove_counter_old_pdu, + uint32_t *remove_counter_old_segack, + uint32_t *remove_counter_old_segment) { + struct sl_btmesh_packet *cmd = (struct sl_btmesh_packet *)sl_btmesh_cmd_msg; + + struct sl_btmesh_packet *rsp = (struct sl_btmesh_packet *)sl_btmesh_rsp_msg; + + + cmd->header=sl_btmesh_cmd_diagnostic_get_friend_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_btmesh_host_handle_command(); + if (queue_counter) { + *queue_counter = rsp->data.rsp_diagnostic_get_friend.queue_counter; + } + if (relay_counter) { + *relay_counter = rsp->data.rsp_diagnostic_get_friend.relay_counter; + } + if (remove_counter_sent) { + *remove_counter_sent = rsp->data.rsp_diagnostic_get_friend.remove_counter_sent; + } + if (remove_counter_old_pdu) { + *remove_counter_old_pdu = rsp->data.rsp_diagnostic_get_friend.remove_counter_old_pdu; + } + if (remove_counter_old_segack) { + *remove_counter_old_segack = rsp->data.rsp_diagnostic_get_friend.remove_counter_old_segack; + } + if (remove_counter_old_segment) { + *remove_counter_old_segment = rsp->data.rsp_diagnostic_get_friend.remove_counter_old_segment; + } + return rsp->data.rsp_diagnostic_get_friend.result; + +} diff --git a/protocol/flex/app-framework-common/app_framework_common.c b/protocol/flex/app-framework-common/app_framework_common.c index 2941338f5f..20f7ce7114 100644 --- a/protocol/flex/app-framework-common/app_framework_common.c +++ b/protocol/flex/app-framework-common/app_framework_common.c @@ -27,7 +27,7 @@ * ******************************************************************************/ -#include +#include "sl-connect-assert.h" #include "callback_dispatcher.h" #include "app_framework_callback.h" #include "stack/core/sl-connect-watchdog.h" @@ -57,7 +57,7 @@ static uint32_t savedResetCause; void connect_standard_phy_2_4g(void) { - assert(emberPhyConfigInit(EMBER_STANDARD_PHY_2_4GHZ) == EMBER_SUCCESS); + CONNECT_STACK_ASSERT(emberPhyConfigInit(EMBER_STANDARD_PHY_2_4GHZ) == EMBER_SUCCESS); } void connect_stack_init(void) @@ -76,7 +76,7 @@ void connect_stack_init(void) // Initialize the radio and the stack. If this fails, we have to assert // because something is wrong. status = stack_init(); - assert(status == EMBER_SUCCESS); + CONNECT_STACK_ASSERT(status == EMBER_SUCCESS); } uint32_t emberAfGetResetCause(void) diff --git a/protocol/flex/app-framework-common/app_framework_sleep.c b/protocol/flex/app-framework-common/app_framework_sleep.c index d08c99e5b9..72839c029a 100644 --- a/protocol/flex/app-framework-common/app_framework_sleep.c +++ b/protocol/flex/app-framework-common/app_framework_sleep.c @@ -29,7 +29,7 @@ // Define module name for Power Manager debuging feature. #define CURRENT_MODULE_NAME "FLEX" -#include +#include "sl-connect-assert.h" #include "callback_dispatcher.h" #include "app_framework_callback.h" #include "stack/core/sli-connect-interrupt-manipulation.h" @@ -150,7 +150,7 @@ bool connect_is_ok_to_sleep(void) // If durations_ms is 0 it means we could not enter em2, so we see how long we // can enter em1 instead. if (duration_ms == 0) { - assert(em1_requirement_set); + CONNECT_STACK_ASSERT(em1_requirement_set); duration_ms = emberStackIdleTimeMs(NULL); duration_ms = emberMsToNextEvent(emAppEvents, duration_ms); @@ -168,12 +168,12 @@ bool connect_is_ok_to_sleep(void) if (app_allowed && duration_ms > 0 && duration_ms < MAX_INT32U_VALUE) { // We can enter em1 or em2 for a limited amount of time: either way we set // a timer to wake us up. - assert(sl_sleeptimer_restart_timer_ms(&wakeup_timer_id, - duration_ms, - wakeup_timer_callback, - NULL, - 0u, - 0u) == SL_STATUS_OK); + CONNECT_STACK_ASSERT(sl_sleeptimer_restart_timer_ms(&wakeup_timer_id, + duration_ms, + wakeup_timer_callback, + NULL, + 0u, + 0u) == SL_STATUS_OK); } return app_allowed; diff --git a/protocol/flex/app/ncp-app/main.c b/protocol/flex/app/ncp-app/main.c index 926b4dd147..215478c14a 100644 --- a/protocol/flex/app/ncp-app/main.c +++ b/protocol/flex/app/ncp-app/main.c @@ -14,7 +14,7 @@ * ******************************************************************************/ -#include +#include "sl-connect-assert.h" #include "sl_component_catalog.h" #include "sl_system_init.h" #include "app_framework_common.h" @@ -40,11 +40,11 @@ RAIL_Status_t RAILCb_SetupRxFifo(RAIL_Handle_t railHandle) if (!rail_rx_fifo_is_initialized) { uint16_t rxFifoSize = RAIL_RX_FIFO_SIZE; phy_rx_fifo = (uint8_t *)malloc(rxFifoSize); - assert(phy_rx_fifo != NULL); - assert(RAIL_SetRxFifo(railHandle, &phy_rx_fifo[0], &rxFifoSize) - == RAIL_STATUS_NO_ERROR); + CONNECT_STACK_ASSERT(phy_rx_fifo != NULL); + CONNECT_STACK_ASSERT(RAIL_SetRxFifo(railHandle, &phy_rx_fifo[0], &rxFifoSize) + == RAIL_STATUS_NO_ERROR); // Check that the allocated memory size in RAIL corresponds to what we want - assert(rxFifoSize == RAIL_RX_FIFO_SIZE); + CONNECT_STACK_ASSERT(rxFifoSize == RAIL_RX_FIFO_SIZE); rail_rx_fifo_is_initialized = true; } return RAIL_STATUS_NO_ERROR; diff --git a/protocol/flex/cmsis-stack-ipc/cmsis-rtos-af-task.c b/protocol/flex/cmsis-stack-ipc/cmsis-rtos-af-task.c index 806b1127d1..2556c99652 100644 --- a/protocol/flex/cmsis-stack-ipc/cmsis-rtos-af-task.c +++ b/protocol/flex/cmsis-stack-ipc/cmsis-rtos-af-task.c @@ -27,7 +27,7 @@ * ******************************************************************************/ -#include +#include "sl-connect-assert.h" #include "cmsis-rtos-ipc-config.h" #include "stack/include/ember.h" @@ -67,8 +67,9 @@ void emAfPluginCmsisRtosAppFrameworkTask(void *p_arg) void emAfPluginCmsisRtosWakeUpAppFrameworkTask(void) { - assert((osEventFlagsSet(emAfPluginCmsisRtosFlags, - FLAG_STACK_CALLBACK_PENDING) & CMSIS_RTOS_ERROR_MASK) == 0); + CONNECT_STACK_ASSERT((osEventFlagsSet(emAfPluginCmsisRtosFlags, + FLAG_STACK_CALLBACK_PENDING) + & CMSIS_RTOS_ERROR_MASK) == 0); } //------------------------------------------------------------------------------ @@ -77,7 +78,7 @@ void emAfPluginCmsisRtosWakeUpAppFrameworkTask(void) static void appFrameworkTaskYield(void) { uint32_t idleTimeMs = emberMsToNextEvent(emAppEvents, - EMBER_AF_PLUGIN_CMSIS_RTOS_APP_FRAMEWORK_YIELD_TIMEOUT_MS); + CMSIS_RTOS_APP_FRAMEWORK_YIELD_TIMEOUT_MS); if (idleTimeMs > 0) { uint32_t yieldTimeTicks = (osKernelGetTickFreq() * idleTimeMs) / 1000; diff --git a/protocol/flex/cmsis-stack-ipc/cmsis-rtos-ipc-common.c b/protocol/flex/cmsis-stack-ipc/cmsis-rtos-ipc-common.c index 2fee7f26f3..e7bcc0588f 100644 --- a/protocol/flex/cmsis-stack-ipc/cmsis-rtos-ipc-common.c +++ b/protocol/flex/cmsis-stack-ipc/cmsis-rtos-ipc-common.c @@ -28,7 +28,7 @@ ******************************************************************************/ #include -#include +#include "sl-connect-assert.h" #include #include "cmsis-rtos-ipc-config.h" @@ -77,15 +77,15 @@ void emAfPluginCmsisRtosIpcInit(void) }; emAfPluginCmsisRtosFlags = osEventFlagsNew(&rtosFlagsAttr); - assert(emAfPluginCmsisRtosFlags != NULL); + CONNECT_STACK_ASSERT(emAfPluginCmsisRtosFlags != NULL); commandMutex = osMutexNew(NULL); - assert(commandMutex != NULL); + CONNECT_STACK_ASSERT(commandMutex != NULL); callbackQueue = osMessageQueueNew(EMBER_AF_PLUGIN_CMSIS_RTOS_MAX_CALLBACK_QUEUE_SIZE, (sizeof(EmberBufferDesc) + 3) & (~3) /* align to 4 bytes */, NULL); - assert(callbackQueue != NULL); + CONNECT_STACK_ASSERT(callbackQueue != NULL); } uint8_t *sendBlockingCommand(uint8_t *apiCommandBuffer) @@ -93,7 +93,7 @@ uint8_t *sendBlockingCommand(uint8_t *apiCommandBuffer) (void)apiCommandBuffer; // This API can not be called from the stack task (the stack task calls // stack APIs directly). - assert(!isCurrentTaskStackTask()); + CONNECT_STACK_ASSERT(!isCurrentTaskStackTask()); // Post the "command pending" flag, wake up the stack and pend for the // "response" pending flag. @@ -108,7 +108,7 @@ void sendResponse(uint8_t *apiCommandBuffer, uint16_t commandLength) (void)apiCommandBuffer; (void)commandLength; // This API must be called from the stack task. - assert(isCurrentTaskStackTask()); + CONNECT_STACK_ASSERT(isCurrentTaskStackTask()); postResponsePendingFlag(); } @@ -117,7 +117,7 @@ void emAfPluginCmsisRtosProcessIncomingApiCommand(void) uint32_t status = pendCommandPendingFlag(); // This API must be called from the stack task. - assert(isCurrentTaskStackTask()); + CONNECT_STACK_ASSERT(isCurrentTaskStackTask()); /* Need to check that the pend did not result in an error * and that the expected flag is present. @@ -133,7 +133,7 @@ void emAfPluginCmsisRtosProcessIncomingApiCommand(void) void sendCallbackCommand(uint8_t *callbackCommandBuffer, uint16_t commandLength) { // This API must be called from the stack task. - assert(isCurrentTaskStackTask()); + CONNECT_STACK_ASSERT(isCurrentTaskStackTask()); // Queue is full or no memory available: either way just return. if (callbackCommandBuffer == NULL) { @@ -175,7 +175,7 @@ bool emAfPluginCmsisRtosProcessIncomingCallbackCommand(void) // This API can not be called from the stack task (the stack task calls // stack APIs directly). - assert(!isCurrentTaskStackTask()); + CONNECT_STACK_ASSERT(!isCurrentTaskStackTask()); osMessageQueueGet(callbackQueue, (void *)&callbackBufferDescriptorGet, @@ -210,16 +210,16 @@ bool isCurrentTaskStackTask(void) void acquireCommandMutex(void) { - assert(!isCurrentTaskStackTask()); + CONNECT_STACK_ASSERT(!isCurrentTaskStackTask()); - assert(osMutexAcquire(commandMutex, osWaitForever) == osOK); + CONNECT_STACK_ASSERT(osMutexAcquire(commandMutex, osWaitForever) == osOK); } void releaseCommandMutex(void) { - assert(!isCurrentTaskStackTask()); + CONNECT_STACK_ASSERT(!isCurrentTaskStackTask()); - assert(osMutexRelease(commandMutex) == osOK); + CONNECT_STACK_ASSERT(osMutexRelease(commandMutex) == osOK); } uint8_t *getApiCommandPointer() @@ -280,26 +280,30 @@ static uint32_t pendCommandPendingFlag(void) static void postCommandPendingFlag(void) { - assert((osEventFlagsSet(emAfPluginCmsisRtosFlags, - FLAG_IPC_COMMAND_PENDING) & CMSIS_RTOS_ERROR_MASK) == 0); + CONNECT_STACK_ASSERT((osEventFlagsSet(emAfPluginCmsisRtosFlags, + FLAG_IPC_COMMAND_PENDING) + & CMSIS_RTOS_ERROR_MASK) == 0); } static void pendResponsePendingFlag(void) { - assert((osEventFlagsWait(emAfPluginCmsisRtosFlags, - FLAG_IPC_RESPONSE_PENDING, - osFlagsWaitAny, - osWaitForever) & CMSIS_RTOS_ERROR_MASK) == 0); + CONNECT_STACK_ASSERT((osEventFlagsWait(emAfPluginCmsisRtosFlags, + FLAG_IPC_RESPONSE_PENDING, + osFlagsWaitAny, + osWaitForever) + & CMSIS_RTOS_ERROR_MASK) == 0); } static void postResponsePendingFlag(void) { - assert((osEventFlagsSet(emAfPluginCmsisRtosFlags, - FLAG_IPC_RESPONSE_PENDING) & CMSIS_RTOS_ERROR_MASK) == 0); + CONNECT_STACK_ASSERT((osEventFlagsSet(emAfPluginCmsisRtosFlags, + FLAG_IPC_RESPONSE_PENDING) + & CMSIS_RTOS_ERROR_MASK) == 0); } static void postCallbackPendingFlag(void) { - assert((osEventFlagsSet(emAfPluginCmsisRtosFlags, - FLAG_STACK_CALLBACK_PENDING) & CMSIS_RTOS_ERROR_MASK) == 0); + CONNECT_STACK_ASSERT((osEventFlagsSet(emAfPluginCmsisRtosFlags, + FLAG_STACK_CALLBACK_PENDING) + & CMSIS_RTOS_ERROR_MASK) == 0); } diff --git a/protocol/flex/cmsis-stack-ipc/cmsis-rtos-support.c b/protocol/flex/cmsis-stack-ipc/cmsis-rtos-support.c index f46ab50d51..4f3d5feefb 100644 --- a/protocol/flex/cmsis-stack-ipc/cmsis-rtos-support.c +++ b/protocol/flex/cmsis-stack-ipc/cmsis-rtos-support.c @@ -27,7 +27,7 @@ * ******************************************************************************/ -#include +#include "sl-connect-assert.h" #include "sl_component_catalog.h" #include "cmsis-rtos-ipc-config.h" @@ -64,13 +64,13 @@ void emberAfPluginCmsisRtosIpcInit(void) void emberAfPluginCmsisRtosAcquireBufferSystemMutex(void) { - assert(osMutexAcquire(bufferSystemMutex, - osWaitForever) == osOK); + CONNECT_STACK_ASSERT(osMutexAcquire(bufferSystemMutex, + osWaitForever) == osOK); } void emberAfPluginCmsisRtosReleaseBufferSystemMutex(void) { - assert(osMutexRelease(bufferSystemMutex) == osOK); + CONNECT_STACK_ASSERT(osMutexRelease(bufferSystemMutex) == osOK); } //------------------------------------------------------------------------------ @@ -99,10 +99,10 @@ void emAfPluginCmsisRtosInitTasks(void) connectStackId = osThreadNew(emAfPluginCmsisRtosStackTask, NULL, &connectStackattribute); - assert(connectStackId != 0); + CONNECT_STACK_ASSERT(connectStackId != 0); bufferSystemMutex = osMutexNew(NULL); - assert(bufferSystemMutex != NULL); + CONNECT_STACK_ASSERT(bufferSystemMutex != NULL); emAfPluginCmsisRtosIpcInit(); @@ -122,7 +122,7 @@ void emAfPluginCmsisRtosInitTasks(void) appFrameworkId = osThreadNew(emAfPluginCmsisRtosAppFrameworkTask, NULL, &appFrameWorkattribute); - assert(appFrameworkId != 0); + CONNECT_STACK_ASSERT(appFrameworkId != 0); } //------------------------------------------------------------------------------ @@ -153,6 +153,6 @@ bool emAfPluginCmsisStackIdleHandler(uint32_t *idleTimeMs) { (void)idleTimeMs; - assert(0); + CONNECT_STACK_ASSERT(0); return false; } diff --git a/protocol/flex/cmsis-stack-ipc/cmsis-rtos-support.h b/protocol/flex/cmsis-stack-ipc/cmsis-rtos-support.h index b3d81d468b..a899998719 100644 --- a/protocol/flex/cmsis-stack-ipc/cmsis-rtos-support.h +++ b/protocol/flex/cmsis-stack-ipc/cmsis-rtos-support.h @@ -39,6 +39,10 @@ #define FLAG_IPC_RESPONSE_PENDING 0x08 #define CMSIS_RTOS_ERROR_MASK 0x80000000 +// The Application Framework Task yield timeout in milliseconds. +// This is the most the application task shall yield. Upon timeout, +// the task will check again if yielding is possible. +#define CMSIS_RTOS_APP_FRAMEWORK_YIELD_TIMEOUT_MS (250) //------------------------------------------------------------------------------ // Public APIs diff --git a/protocol/flex/cmsis-stack-ipc/cmsis-rtos-vncp-task.c b/protocol/flex/cmsis-stack-ipc/cmsis-rtos-vncp-task.c index 8201aa104a..04411e42e7 100644 --- a/protocol/flex/cmsis-stack-ipc/cmsis-rtos-vncp-task.c +++ b/protocol/flex/cmsis-stack-ipc/cmsis-rtos-vncp-task.c @@ -29,7 +29,7 @@ // Define module name for Power Manager debuging feature. #define CURRENT_MODULE_NAME "FLEX_RTOS_VNCP_TASK" -#include +#include "sl-connect-assert.h" #include "cmsis-rtos-ipc-config.h" #include "sl_component_catalog.h" @@ -78,8 +78,9 @@ void emAfPluginCmsisRtosStackTask(void *p_arg) // This can be called from ISR. void emAfPluginCmsisRtosWakeUpConnectStackTask(void) { - assert((osEventFlagsSet(emAfPluginCmsisRtosFlags, - FLAG_STACK_ACTION_PENDING) & CMSIS_RTOS_ERROR_MASK) == 0); + CONNECT_STACK_ASSERT((osEventFlagsSet(emAfPluginCmsisRtosFlags, + FLAG_STACK_ACTION_PENDING) + & CMSIS_RTOS_ERROR_MASK) == 0); } //------------------------------------------------------------------------------ diff --git a/protocol/flex/cmsis-stack-ipc/config/cmsis-rtos-ipc-config.h b/protocol/flex/cmsis-stack-ipc/config/cmsis-rtos-ipc-config.h index 1ec06e649d..55a8aa2e4b 100644 --- a/protocol/flex/cmsis-stack-ipc/config/cmsis-rtos-ipc-config.h +++ b/protocol/flex/cmsis-stack-ipc/config/cmsis-rtos-ipc-config.h @@ -57,11 +57,6 @@ // The size in 32-bit words of the Application Framework task call stack. #define EMBER_AF_PLUGIN_CMSIS_RTOS_APP_FRAMEWORK_STACK_SIZE (500) -// Application Framework Task yield timeout -// Default: 1000000 -// The Application Framework Task yield timeout in milliseconds. This is the most the application task shall yield. Upon timeout, the task will check again if yielding is possible. -#define EMBER_AF_PLUGIN_CMSIS_RTOS_APP_FRAMEWORK_YIELD_TIMEOUT_MS (1000000) - // Max callback queue size <5-20> // Default: 10 // The maximum number of simultaneous callback messages from the stack task to the application tasks. diff --git a/protocol/flex/component/connect_stack_common.slcc b/protocol/flex/component/connect_stack_common.slcc index 24d3b687d9..2ee14ce76f 100644 --- a/protocol/flex/component/connect_stack_common.slcc +++ b/protocol/flex/component/connect_stack_common.slcc @@ -72,6 +72,7 @@ include: - "power_manager" - path: "stack/core" file_list: + - path: "sl-connect-assert.h" - path: "sli-connect-api.h" - path: "sli-connect-interrupt-manipulation.h" - path: "sli-connect-token.h" diff --git a/protocol/flex/csp/csp-command-callbacks.c b/protocol/flex/csp/csp-command-callbacks.c index 50240e449a..6a97718d48 100644 --- a/protocol/flex/csp/csp-command-callbacks.c +++ b/protocol/flex/csp/csp-command-callbacks.c @@ -17,7 +17,7 @@ // *** Generated file. Do not edit! *** // vNCP Version: 1.0 -#include +#include "sl-connect-assert.h" #include "stack/include/ember.h" #include "csp-format.h" @@ -481,7 +481,7 @@ static void frequencyHoppingStartClientCompleteCommandHandler(uint8_t *callbackP void handleIncomingCallbackCommand(uint16_t commandId, uint8_t *callbackParams) { - assert(!isCurrentTaskStackTask()); + CONNECT_STACK_ASSERT(!isCurrentTaskStackTask()); switch (commandId) { case EMBER_STACK_STATUS_HANDLER_IPC_COMMAND_ID: diff --git a/protocol/flex/csp/csp-command-vncp.c b/protocol/flex/csp/csp-command-vncp.c index 6ce2ead220..8eb0974497 100644 --- a/protocol/flex/csp/csp-command-vncp.c +++ b/protocol/flex/csp/csp-command-vncp.c @@ -17,7 +17,7 @@ // *** Generated file. Do not edit! *** // vNCP Version: 1.0 -#include +#include "sl-connect-assert.h" #include "stack/include/ember.h" #include "ncp/ncp-security.h" #include "stack/core/sli-connect-api.h" @@ -1510,7 +1510,7 @@ static void getDefaultChannelCommandHandler(uint8_t *apiCommandData) void handleIncomingApiCommand(uint16_t commandId, uint8_t *apiCommandData) { - assert(isCurrentTaskStackTask()); + CONNECT_STACK_ASSERT(isCurrentTaskStackTask()); switch (commandId) { case EMBER_NETWORK_STATE_IPC_COMMAND_ID: diff --git a/protocol/flex/csp/csp-format.c b/protocol/flex/csp/csp-format.c index 6a7cfade7a..5af212db86 100644 --- a/protocol/flex/csp/csp-format.c +++ b/protocol/flex/csp/csp-format.c @@ -14,7 +14,7 @@ * ******************************************************************************/ -#include +#include "sl-connect-assert.h" #include #include "stack/include/ember.h" #include "stack/core/sli-connect-api.h" @@ -188,7 +188,7 @@ uint8_t computeCommandLength(uint8_t initialLength, const char* format, va_list break; } default: - assert(false); + CONNECT_STACK_ASSERT(false); break; } } @@ -293,14 +293,14 @@ uint16_t formatResponseCommandFromArgList(uint8_t *buffer, } default: // confused! - assert(false); + CONNECT_STACK_ASSERT(false); break; } } uint16_t length = finger - buffer; // sanity check - assert(length <= bufferSize); + CONNECT_STACK_ASSERT(length <= bufferSize); return length; } diff --git a/protocol/flex/libs/libconnect-aes-security-library-efr32xg1-gcc.a b/protocol/flex/libs/libconnect-aes-security-library-efr32xg1-gcc.a index 769d96c630..51665db9f8 100644 --- a/protocol/flex/libs/libconnect-aes-security-library-efr32xg1-gcc.a +++ b/protocol/flex/libs/libconnect-aes-security-library-efr32xg1-gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a45820f0272ce5626606e5284e7c6506b05b1514af2840b7d4e2876f83da410e -size 65762 +oid sha256:6737a21bb9c7c7862f0b46a4a246de2c1858518b9fc2d8d34e9ce9040644a481 +size 65458 diff --git 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a/protocol/flex/libs/libconnect-stack-counters-library-efr32xg1-iar.a b/protocol/flex/libs/libconnect-stack-counters-library-efr32xg1-iar.a index d882df195a..755310b252 100644 --- a/protocol/flex/libs/libconnect-stack-counters-library-efr32xg1-iar.a +++ b/protocol/flex/libs/libconnect-stack-counters-library-efr32xg1-iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4f21bc0b1205d0be429e4e1a0ee84b76e6d120c2fc15ae23b768163a17b7397e -size 4714 +oid sha256:3b3131c76ca11ef9a429ff9f4a42109d855e157dcd4ada056ec3b46e3b6c701f +size 4620 diff --git a/protocol/flex/libs/libconnect-stack-counters-library-efr32xg1x-gcc.a b/protocol/flex/libs/libconnect-stack-counters-library-efr32xg1x-gcc.a index 34dd172c16..571122cfbe 100644 --- a/protocol/flex/libs/libconnect-stack-counters-library-efr32xg1x-gcc.a +++ b/protocol/flex/libs/libconnect-stack-counters-library-efr32xg1x-gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cc67ad27890fb6e14d24454da1efca847be2cff65ac73440d897071aa64c0100 -size 10344 +oid sha256:501aabcbb9237051fbdfad1c638dc4f705b5eb91d296cd1755ba3df7dd6568a6 +size 10128 diff --git a/protocol/flex/libs/libconnect-stack-counters-library-efr32xg1x-iar.a b/protocol/flex/libs/libconnect-stack-counters-library-efr32xg1x-iar.a index 5d82d38246..6eb55e0114 100644 --- a/protocol/flex/libs/libconnect-stack-counters-library-efr32xg1x-iar.a +++ b/protocol/flex/libs/libconnect-stack-counters-library-efr32xg1x-iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:94423dda2226356381e9a603158d9862f7671f0a013a43faaf175dae71ee7998 -size 4802 +oid sha256:f93e869ac736a153d45c5576f9be4a6ad0f6b3777c7c694b66613f1784006e69 +size 4710 diff --git a/protocol/flex/libs/libconnect-stack-counters-library-efr32xg2x-gcc.a b/protocol/flex/libs/libconnect-stack-counters-library-efr32xg2x-gcc.a index 2b1a0b9b5f..575dddbd9a 100644 --- a/protocol/flex/libs/libconnect-stack-counters-library-efr32xg2x-gcc.a +++ b/protocol/flex/libs/libconnect-stack-counters-library-efr32xg2x-gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d03b19fffbd531916932aa3b31e8c3732dd2570d02d5986ffe5b78e4ba1abd99 -size 10356 +oid sha256:04355d800b19aa3c5984d51c9bea9b7ccc1e0683ba38dff2941d3e89733631b8 +size 10140 diff --git a/protocol/flex/libs/libconnect-stack-counters-library-efr32xg2x-iar.a b/protocol/flex/libs/libconnect-stack-counters-library-efr32xg2x-iar.a index b23d8014fd..024c27e730 100644 --- a/protocol/flex/libs/libconnect-stack-counters-library-efr32xg2x-iar.a +++ b/protocol/flex/libs/libconnect-stack-counters-library-efr32xg2x-iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2376286177043a1159c24dff178603b44ed6d72c35415bd614293672a8fe2eb9 -size 4804 +oid sha256:53eb299392b6f68d4f2b5a870e6549c28d96bfc7deb19bc1ad871f38e794df39 +size 4712 diff --git a/protocol/flex/mailbox/mailbox-client/mailbox-client.c b/protocol/flex/mailbox/mailbox-client/mailbox-client.c index 5072d009aa..01daa6e43e 100644 --- a/protocol/flex/mailbox/mailbox-client/mailbox-client.c +++ b/protocol/flex/mailbox/mailbox-client/mailbox-client.c @@ -28,7 +28,7 @@ ******************************************************************************/ #include -#include +#include "sl-connect-assert.h" #include "mailbox-client-config.h" #include "stack/include/ember.h" @@ -192,7 +192,7 @@ void emAfPluginMailboxClientEventHandler(void) 0, // tag false); // moreMessages } else { - assert(0); + CONNECT_STACK_ASSERT(0); } } @@ -302,7 +302,7 @@ static void addMessageCommandSentHandler(EmberStatus status, EmberNodeId server, EmberNodeId destination) { - assert(internalState == CLIENT_STATE_SUBMIT_PENDING); + CONNECT_STACK_ASSERT(internalState == CLIENT_STATE_SUBMIT_PENDING); if (tag == pendingMessageData.tag && destination == pendingMessageData.destination @@ -371,7 +371,7 @@ static EmberStatus sendGetMessageCommand(EmberNodeId server, static void getMessageCommandSentHandler(EmberStatus status, EmberNodeId server) { - assert(internalState == CLIENT_STATE_CHECK_MAILBOX_PENDING); + CONNECT_STACK_ASSERT(internalState == CLIENT_STATE_CHECK_MAILBOX_PENDING); if (server == pendingMessageData.server) { if (status == EMBER_SUCCESS) { diff --git a/protocol/flex/ncp/ncp-cpc-interface.c b/protocol/flex/ncp/ncp-cpc-interface.c index a0bf4bb14a..86b8dd399e 100644 --- a/protocol/flex/ncp/ncp-cpc-interface.c +++ b/protocol/flex/ncp/ncp-cpc-interface.c @@ -17,7 +17,7 @@ #include "sli_cpc.h" #include "sl_cpc.h" #include -#include +#include "sl-connect-assert.h" #include "stack/include/ember.h" #include "ncp-cpc-interface.h" #include "csp-format.h" @@ -57,7 +57,7 @@ static void on_write_completed(sl_cpc_user_endpoint_id_t endpoint_id, void *buff void sli_connect_ncp_process_incoming_api_command(uint8_t *apiCommandData) { // This API must be called from the stack task. - assert(isCurrentTaskStackTask()); + CONNECT_STACK_ASSERT(isCurrentTaskStackTask()); uint16_t commandId = emberFetchHighLowInt16u(apiCommandData); handleIncomingApiCommand(commandId, apiCommandData); @@ -94,7 +94,7 @@ static void cpc_error_cb(uint8_t endpoint_id, void *arg) uint8_t state = sl_cpc_get_endpoint_state(&connect_endpoint_handle); if (state == SL_CPC_STATE_ERROR_DESTINATION_UNREACHABLE) { sl_status_t status = sl_cpc_close_endpoint(&connect_endpoint_handle); - assert(status == SL_STATUS_OK); + CONNECT_STACK_ASSERT(status == SL_STATUS_OK); connected = false; emberEventControlSetActive(sl_connect_ncp_endpoint_deconnection_event); } @@ -184,6 +184,6 @@ bool connect_cpc_open_endpoint(void) void connect_stack_cpc_init(void) { - assert(connect_cpc_open_endpoint()); + CONNECT_STACK_ASSERT(connect_cpc_open_endpoint()); emberNcpSetLongMessagesUse(false); } diff --git a/protocol/flex/ncp/ncp-security.c b/protocol/flex/ncp/ncp-security.c index e8a9a41445..b5e9c3d54d 100644 --- a/protocol/flex/ncp/ncp-security.c +++ b/protocol/flex/ncp/ncp-security.c @@ -106,7 +106,7 @@ EmberStatus emApiSetNcpSecurityKey(uint8_t *keyContents, uint8_t keyLength) void sli_connect_ncp_key_loader_handler(void) { psa_key_id_t key_id; - sl_token_set_data(TOKEN_STACK_SECURITY_KEY_ID, + sl_token_get_data(TOKEN_STACK_SECURITY_KEY_ID, 0, (tokTypeStackKeyID*)&key_id, TOKEN_STACK_SECURITY_KEY_ID_SIZE); diff --git a/protocol/flex/ota-broadcast-bootloader/ota-broadcast-bootloader-client/ota-broadcast-bootloader-client.c b/protocol/flex/ota-broadcast-bootloader/ota-broadcast-bootloader-client/ota-broadcast-bootloader-client.c index cc99bc4a13..23c0249595 100644 --- a/protocol/flex/ota-broadcast-bootloader/ota-broadcast-bootloader-client/ota-broadcast-bootloader-client.c +++ b/protocol/flex/ota-broadcast-bootloader/ota-broadcast-bootloader-client/ota-broadcast-bootloader-client.c @@ -28,7 +28,7 @@ ******************************************************************************/ #include -#include +#include "sl-connect-assert.h" #include "ota-broadcast-bootloader-client-config.h" #include "stack/include/ember.h" @@ -191,7 +191,7 @@ static void initSegmentsBitmask(void) { uint8_t *segmentBitmaskBufferPtr; - assert(segmentBitmaskBuffer != EMBER_NULL_BUFFER); + CONNECT_STACK_ASSERT(segmentBitmaskBuffer != EMBER_NULL_BUFFER); #if defined(SL_CATALOG_KERNEL_PRESENT) emberAfPluginCmsisRtosAcquireBufferSystemMutex(); @@ -212,7 +212,7 @@ static bool getSegmentBit(uint16_t segmentIndex) uint8_t *segmentBitmaskBufferPtr; bool ret; - assert(segmentBitmaskBuffer != EMBER_NULL_BUFFER); + CONNECT_STACK_ASSERT(segmentBitmaskBuffer != EMBER_NULL_BUFFER); #if defined(SL_CATALOG_KERNEL_PRESENT) emberAfPluginCmsisRtosAcquireBufferSystemMutex(); @@ -234,7 +234,7 @@ static void setSegmentBit(uint16_t segmentIndex) uint8_t bitIndex = ((segmentIndex % MAX_SEGMENTS_IN_A_BLOCK) % 8); uint8_t *segmentBitmaskBufferPtr; - assert(segmentBitmaskBuffer != EMBER_NULL_BUFFER); + CONNECT_STACK_ASSERT(segmentBitmaskBuffer != EMBER_NULL_BUFFER); #if defined(SL_CATALOG_KERNEL_PRESENT) emberAfPluginCmsisRtosAcquireBufferSystemMutex(); @@ -268,7 +268,7 @@ static uint16_t getTotalSegmentsCount(void) uint16_t totalSegments = (uint16_t)(imageInfo.size / MAX_SEGMENT_PAYLOAD_LENGTH); - assert(imageInfo.size > 0); + CONNECT_STACK_ASSERT(imageInfo.size > 0); if ((imageInfo.size % MAX_SEGMENT_PAYLOAD_LENGTH) > 0) { totalSegments++; @@ -416,7 +416,7 @@ static void sendMissingSegmentsResponse(EmberNodeId serverId, uint8_t i; uint8_t *segmensBitmaskBufferPtr; - assert(segmentBitmaskBuffer != EMBER_NULL_BUFFER); + CONNECT_STACK_ASSERT(segmentBitmaskBuffer != EMBER_NULL_BUFFER); #if defined(SL_CATALOG_KERNEL_PRESENT) emberAfPluginCmsisRtosAcquireBufferSystemMutex(); @@ -569,7 +569,7 @@ static void historyTableAddEntry(uint8_t otaProtocolStatus, } } - assert(entryIndex < HISTORY_TABLE_SIZE); + CONNECT_STACK_ASSERT(entryIndex < HISTORY_TABLE_SIZE); scriptCheckHistoryTableAdd(entryIndex); diff --git a/protocol/flex/ota-broadcast-bootloader/ota-broadcast-bootloader-server/ota-broadcast-bootloader-server.c b/protocol/flex/ota-broadcast-bootloader/ota-broadcast-bootloader-server/ota-broadcast-bootloader-server.c index 09ffeba30e..9afd0c6357 100644 --- a/protocol/flex/ota-broadcast-bootloader/ota-broadcast-bootloader-server/ota-broadcast-bootloader-server.c +++ b/protocol/flex/ota-broadcast-bootloader/ota-broadcast-bootloader-server/ota-broadcast-bootloader-server.c @@ -28,7 +28,7 @@ ******************************************************************************/ #include -#include +#include "sl-connect-assert.h" #include "ota-broadcast-bootloader-server-config.h" #include "stack/include/ember.h" @@ -625,9 +625,9 @@ uint8_t emGetOrSetTargetMiscInfo(uint16_t targetIndex, uint8_t *targetListBufferPtr; uint8_t retVal = 0; - assert(currentTargetListBuffer != EMBER_NULL_BUFFER - && emberGetBufferLength(currentTargetListBuffer) - >= (targetIndex + 1) * TARGET_LIST_ENTRY_LENGTH); + CONNECT_STACK_ASSERT(currentTargetListBuffer != EMBER_NULL_BUFFER + && emberGetBufferLength(currentTargetListBuffer) + >= (targetIndex + 1) * TARGET_LIST_ENTRY_LENGTH); #if defined(SL_CATALOG_KERNEL_PRESENT) emberAfPluginCmsisRtosAcquireBufferSystemMutex(); @@ -660,9 +660,9 @@ uint8_t emGetOrSetTargetApplicationStatus(uint16_t targetIndex, uint8_t *targetListBufferPtr; uint8_t retVal = 0; - assert(currentTargetListBuffer != EMBER_NULL_BUFFER - && emberGetBufferLength(currentTargetListBuffer) - >= (targetIndex + 1) * TARGET_LIST_ENTRY_LENGTH); + CONNECT_STACK_ASSERT(currentTargetListBuffer != EMBER_NULL_BUFFER + && emberGetBufferLength(currentTargetListBuffer) + >= (targetIndex + 1) * TARGET_LIST_ENTRY_LENGTH); #if defined(SL_CATALOG_KERNEL_PRESENT) emberAfPluginCmsisRtosAcquireBufferSystemMutex(); @@ -693,7 +693,7 @@ uint16_t emTargetLookup(EmberNodeId targetShortId) uint8_t *targetListBufferPtr; uint16_t i; - assert(currentTargetListBuffer != EMBER_NULL_BUFFER); + CONNECT_STACK_ASSERT(currentTargetListBuffer != EMBER_NULL_BUFFER); #if defined(SL_CATALOG_KERNEL_PRESENT) emberAfPluginCmsisRtosAcquireBufferSystemMutex(); @@ -738,7 +738,7 @@ static void initTargetList(EmberNodeId *targetList, uint16_t targetListLength) uint16_t i; uint8_t *targetListBufferPtr; - assert(targetListBuffer != EMBER_NULL_BUFFER); + CONNECT_STACK_ASSERT(targetListBuffer != EMBER_NULL_BUFFER); #if defined(SL_CATALOG_KERNEL_PRESENT) emberAfPluginCmsisRtosAcquireBufferSystemMutex(); @@ -797,7 +797,7 @@ bool currentBlockCompleted(void) uint8_t *segmentBitmaskBufferPtr; uint16_t i; - assert(segmentBitmaskBuffer != EMBER_NULL_BUFFER); + CONNECT_STACK_ASSERT(segmentBitmaskBuffer != EMBER_NULL_BUFFER); #if defined(SL_CATALOG_KERNEL_PRESENT) emberAfPluginCmsisRtosAcquireBufferSystemMutex(); @@ -829,7 +829,7 @@ static bool segmentIndexToBit(uint16_t segmentIndex) uint8_t *segmentBitmaskBufferPtr; bool ret; - assert(segmentBitmaskBuffer != EMBER_NULL_BUFFER); + CONNECT_STACK_ASSERT(segmentBitmaskBuffer != EMBER_NULL_BUFFER); #if defined(SL_CATALOG_KERNEL_PRESENT) emberAfPluginCmsisRtosAcquireBufferSystemMutex(); @@ -929,7 +929,7 @@ static void queryNextTargetForMissingSegments(void) lastSegmentIndex = getTotalSegmentsCount() - 1; } - assert(targetListBuffer != EMBER_NULL_BUFFER); + CONNECT_STACK_ASSERT(targetListBuffer != EMBER_NULL_BUFFER); #if defined(SL_CATALOG_KERNEL_PRESENT) emberAfPluginCmsisRtosAcquireBufferSystemMutex(); @@ -1001,7 +1001,7 @@ static void scheduleImageDistributionProcessNextTask(bool newSegmentOrNewTarget) // querying process. nextSegmentOrTargetIndex = 0; stackErrorsCount = 0; - assert(segmentBitmaskBuffer != EMBER_NULL_BUFFER); + CONNECT_STACK_ASSERT(segmentBitmaskBuffer != EMBER_NULL_BUFFER); #if defined(SL_CATALOG_KERNEL_PRESENT) emberAfPluginCmsisRtosAcquireBufferSystemMutex(); @@ -1017,7 +1017,7 @@ static void scheduleImageDistributionProcessNextTask(bool newSegmentOrNewTarget) // Here we assert: if we started a new broadcast round we had at least // one active target. - assert(updateNextTargetIndex(false)); + CONNECT_STACK_ASSERT(updateNextTargetIndex(false)); internalState = STATE_OTA_SERVER_MISSING_SEGMENTS_UNICAST_INTERVAL; } @@ -1074,7 +1074,7 @@ static void scheduleImageDistributionProcessNextTask(bool newSegmentOrNewTarget) nextSegmentOrTargetIndex = currentBlockIndex * MAX_SEGMENTS_IN_A_BLOCK; // We assert here: if we got here, there should be at least a segment // to be sent. - assert(updateNextSegmentIndex(false)); + CONNECT_STACK_ASSERT(updateNextSegmentIndex(false)); // If we reached the maximum broadcast rounds, fail distribution. if (currentBlockBroadcastRoundsCount @@ -1099,7 +1099,7 @@ static void scheduleImageDistributionProcessNextTask(bool newSegmentOrNewTarget) break; default: - assert(0); + CONNECT_STACK_ASSERT(0); } } @@ -1158,7 +1158,7 @@ static void initSegmentsBitmask(void) { uint8_t *segmentBitmaskBufferPtr; - assert(segmentBitmaskBuffer != EMBER_NULL_BUFFER); + CONNECT_STACK_ASSERT(segmentBitmaskBuffer != EMBER_NULL_BUFFER); #if defined(SL_CATALOG_KERNEL_PRESENT) emberAfPluginCmsisRtosAcquireBufferSystemMutex(); @@ -1177,7 +1177,7 @@ static void processMissingSegmentsBitmask(uint8_t *bitmask) uint8_t i; uint8_t *segmentBitmaskBufferPtr; - assert(segmentBitmaskBuffer != EMBER_NULL_BUFFER); + CONNECT_STACK_ASSERT(segmentBitmaskBuffer != EMBER_NULL_BUFFER); #if defined(SL_CATALOG_KERNEL_PRESENT) emberAfPluginCmsisRtosAcquireBufferSystemMutex(); @@ -1203,7 +1203,7 @@ static void queryNextTargetForTargetStatus(void) EmberNodeId destination; uint8_t *targetListBufferPtr; - assert(targetListBuffer != EMBER_NULL_BUFFER); + CONNECT_STACK_ASSERT(targetListBuffer != EMBER_NULL_BUFFER); #if defined(SL_CATALOG_KERNEL_PRESENT) emberAfPluginCmsisRtosAcquireBufferSystemMutex(); @@ -1247,7 +1247,7 @@ static void queryNextTargetForTargetStatus(void) static void scheduleTargetStatusRequestProcessNextTask(bool newTarget) { - assert(serverInTargetStatusRequestProcess()); + CONNECT_STACK_ASSERT(serverInTargetStatusRequestProcess()); if (stackErrorsCount >= EMBER_AF_PLUGIN_OTA_BROADCAST_BOOTLOADER_SERVER_MAX_STACK_ERRORS) { targetsStatusRequestProcessFinished(EMBER_OTA_BROADCAST_BOOTLOADER_STATUS_STACK_ERROR); @@ -1305,7 +1305,7 @@ static void requestNextTargetForBootload(void) EmberStatus status; uint32_t delayMs; - assert(targetListBuffer != EMBER_NULL_BUFFER); + CONNECT_STACK_ASSERT(targetListBuffer != EMBER_NULL_BUFFER); #if defined(SL_CATALOG_KERNEL_PRESENT) emberAfPluginCmsisRtosAcquireBufferSystemMutex(); @@ -1358,7 +1358,7 @@ static void requestNextTargetForBootload(void) static void scheduleBootloadRequestProcessNextTask(bool newTarget) { - assert(serverInBootloadRequestProcess()); + CONNECT_STACK_ASSERT(serverInBootloadRequestProcess()); if (stackErrorsCount >= EMBER_AF_PLUGIN_OTA_BROADCAST_BOOTLOADER_SERVER_MAX_STACK_ERRORS) { bootloadRequestProcessFinished(EMBER_OTA_BROADCAST_BOOTLOADER_STATUS_STACK_ERROR); diff --git a/protocol/flex/ota-unicast-bootloader/ota-unicast-bootloader-client/ota-unicast-bootloader-client.c b/protocol/flex/ota-unicast-bootloader/ota-unicast-bootloader-client/ota-unicast-bootloader-client.c index 2cd69f0f5e..7a64921833 100644 --- a/protocol/flex/ota-unicast-bootloader/ota-unicast-bootloader-client/ota-unicast-bootloader-client.c +++ b/protocol/flex/ota-unicast-bootloader/ota-unicast-bootloader-client/ota-unicast-bootloader-client.c @@ -27,7 +27,7 @@ * ******************************************************************************/ -#include +#include "sl-connect-assert.h" #include "ota-unicast-bootloader-client-config.h" #include "stack/include/ember.h" @@ -165,7 +165,7 @@ static uint32_t getTotalSegmentsCount(void) uint32_t totalSegments = (uint32_t)(imageInfo.size / MAX_SEGMENT_PAYLOAD_LENGTH); - assert(imageInfo.size > 0); + CONNECT_STACK_ASSERT(imageInfo.size > 0); if ((imageInfo.size % MAX_SEGMENT_PAYLOAD_LENGTH) > 0) { totalSegments++; diff --git a/protocol/flex/ota-unicast-bootloader/ota-unicast-bootloader-server/ota-unicast-bootloader-server.c b/protocol/flex/ota-unicast-bootloader/ota-unicast-bootloader-server/ota-unicast-bootloader-server.c index 62a3629511..5aee48cc1b 100644 --- a/protocol/flex/ota-unicast-bootloader/ota-unicast-bootloader-server/ota-unicast-bootloader-server.c +++ b/protocol/flex/ota-unicast-bootloader/ota-unicast-bootloader-server/ota-unicast-bootloader-server.c @@ -27,7 +27,7 @@ * ******************************************************************************/ -#include +#include "sl-connect-assert.h" #include "ota-unicast-bootloader-server-config.h" #include "stack/include/ember.h" @@ -541,7 +541,7 @@ static void scheduleImageDistributionProcessNextTask(bool newSegment) } break; default: - assert(0); + CONNECT_STACK_ASSERT(0); } } @@ -615,7 +615,7 @@ static void requestTargetForBootload(void) static void scheduleBootloadRequestProcessNextTask(bool targetResponeded, uint8_t targetResponseStatus) { - assert(serverInBootloadRequestProcess()); + CONNECT_STACK_ASSERT(serverInBootloadRequestProcess()); if (stackErrorsCount >= EMBER_AF_PLUGIN_OTA_UNICAST_BOOTLOADER_SERVER_MAX_STACK_ERRORS) { bootloadRequestProcessFinished(EMBER_OTA_UNICAST_BOOTLOADER_STATUS_STACK_ERROR); diff --git a/protocol/flex/stack/config/config.h b/protocol/flex/stack/config/config.h index 2707927be0..5df31f54a9 100644 --- a/protocol/flex/stack/config/config.h +++ b/protocol/flex/stack/config/config.h @@ -63,7 +63,7 @@ /** * @brief Build number of the release. Should be stored on 2 bytes. */ -#define EMBER_BUILD_NUMBER 206 +#define EMBER_BUILD_NUMBER 236 /** * @brief Full version number stored on 2 bytes, with each of the four digits diff --git a/protocol/flex/stack/config/ember-configuration.c b/protocol/flex/stack/config/ember-configuration.c index 6f9872b29f..f37a08061c 100644 --- a/protocol/flex/stack/config/ember-configuration.c +++ b/protocol/flex/stack/config/ember-configuration.c @@ -98,5 +98,6 @@ uint32_t *emIndirectQueueTimeouts = indirectQueueTimeouts; uint32_t emberMacIndirectTimeoutMs = EMBER_INDIRECT_TRANSMISSION_TIMEOUT_MS; uint16_t emberCoordinatorFirstShortIdToBeAssigned = EMBER_COORDINATOR_FIRST_SHORT_ID_TO_BE_ASSIGNED; +uint32_t emberNwkRangeExtenderUpdatePeriodSec = EMBER_NWK_RANGE_EXTENDER_UPDATE_PERIOD_SEC; #endif // SL_CATALOG_CONNECT_PARENT_SUPPORT_PRESENT diff --git a/protocol/flex/stack/config/ember-configuration.h b/protocol/flex/stack/config/ember-configuration.h index 6dc70f8841..c9e56ada23 100644 --- a/protocol/flex/stack/config/ember-configuration.h +++ b/protocol/flex/stack/config/ember-configuration.h @@ -60,6 +60,7 @@ extern EmberMacAddress *emIndirectQueueSourceAddresses; extern uint32_t *emIndirectQueueTimeouts; extern uint32_t emberMacIndirectTimeoutMs; +extern uint32_t emberNwkRangeExtenderUpdatePeriodSec; extern uint16_t emberCoordinatorFirstShortIdToBeAssigned; #endif // __EMBER_CONFIGURATION__ diff --git a/protocol/flex/stack/core/sl-connect-assert.h b/protocol/flex/stack/core/sl-connect-assert.h new file mode 100644 index 0000000000..1605a54ab7 --- /dev/null +++ b/protocol/flex/stack/core/sl-connect-assert.h @@ -0,0 +1,34 @@ +/***************************************************************************//** + * @brief Connect custom assert. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef __SL_CONNECT_ASSERT_H__ +#define __SL_CONNECT_ASSERT_H__ + +#include + +#ifdef NDEBUG +#define CONNECT_STACK_ASSERT(exp) (void)(exp) +#else +#define CONNECT_STACK_ASSERT(exp) \ + do { \ + if (!(exp)) { \ + printf("ASSERT in %s:%d\r\n", __FILE__, __LINE__); \ + while (1) {} \ + } \ + } while (0) +#endif // NDEBUG + +#endif // __SL_CONNECT_ASSERT_H__ diff --git a/protocol/flex/stack/framework/event-queue.c b/protocol/flex/stack/framework/event-queue.c index c25683c7f3..13324b9479 100644 --- a/protocol/flex/stack/framework/event-queue.c +++ b/protocol/flex/stack/framework/event-queue.c @@ -28,7 +28,7 @@ // to the halfway point in the list. This would cut the lookup time // almost in half without adding much complexity. -#include +#include "core/sl-connect-assert.h" #include "stack/include/ember.h" #include "core/sli-connect-api.h" #include "stack/core/sli-connect-interrupt-manipulation.h" @@ -48,7 +48,7 @@ void emIsrEventMarker(struct Event_s *event) { (void)event; - assert(false); + CONNECT_STACK_ASSERT(false); } void emInitializeEventQueue(EventQueue *queue) @@ -146,7 +146,7 @@ static void adjustListLocation(EventQueue *queue, Event *event, bool keep) Event *previous = (Event *) queue; Event *finger = queue->events; Event *newLocation = NULL; - assert(event->next != event); + CONNECT_STACK_ASSERT(event->next != event); // Find 'event' in the list, noting the new location if we come across it. while (finger != event) { @@ -172,7 +172,7 @@ static void adjustListLocation(EventQueue *queue, Event *event, bool keep) if (newLocation == NULL) { newLocation = previous; finger = event->next; - assert(event->next != event); + CONNECT_STACK_ASSERT(event->next != event); while (finger != LIST_END && timeGTorEqualInt32u(event->timeToExecute, finger->timeToExecute)) { @@ -257,7 +257,7 @@ void emberEventSetDelayMs(Event *event, uint32_t delay) { EventQueue *queue = event->actions->queue; if (event->actions->marker == emIsrEventMarker) { - assert(delay == 0); + CONNECT_STACK_ASSERT(delay == 0); CORE_ATOMIC_SECTION( if (event->next != NULL) { // already scheduled, do nothing diff --git a/protocol/openthread/component/ot_core_vendor_extension.slcc b/protocol/openthread/component/ot_core_vendor_extension.slcc new file mode 100644 index 0000000000..26249e0cdb --- /dev/null +++ b/protocol/openthread/component/ot_core_vendor_extension.slcc @@ -0,0 +1,17 @@ +id: ot_core_vendor_extension +label: Silicon Labs OpenThread Core Vendor Extension +package: OpenThread +category: OpenThread +quality: production +description: |- + This component implements ot::Extension::ExtensionBase for EFR32. + When used with the OT Crash Handler component, crash info will be printed after the OpenThread instance is initialized. +provides: + - name: ot_core_vendor_extension +ui_hints: + visibility: never +source: + - path: protocol/openthread/src/core/vendor_extension.cpp +define: + - name: OPENTHREAD_ENABLE_VENDOR_EXTENSION + value: 1 \ No newline at end of file diff --git a/protocol/openthread/component/ot_crash_handler.slcc b/protocol/openthread/component/ot_crash_handler.slcc index c0eea4ce9b..fa964b16c7 100644 --- a/protocol/openthread/component/ot_crash_handler.slcc +++ b/protocol/openthread/component/ot_crash_handler.slcc @@ -15,6 +15,9 @@ requires: - name: device - name: emlib_rmu - name: event_handler + - name: ot_core_vendor_extension + condition: + - ot_ncp include: - path: protocol/openthread/src/legacy_hal/include @@ -68,8 +71,19 @@ template_contribution: handler: efr32PrintResetInfo # Maximum priority to ensure this handler is called last during init priority: 10000 - # `efr32PrintResetInfo` is called by `mainloop()` in `sl_ot_rtos_adaptation.c` - # Without this `unless`, the device will be stuck in `otPlatUartFlush()`, - # trying to print crash data. This is because `otPlatUartFlush()` will try - # to use a timer before the kernel is started and before the timer task is created - unless: [freertos] + # Exceptions: + # + # - FreeRTOS + # `efr32PrintResetInfo` is called by `mainloop()` in `sl_ot_rtos_adaptation.c` + # Without this `unless`, the device will be stuck in `otPlatUartFlush()`, + # trying to print crash data. This is because `otPlatUartFlush()` will try + # to use a timer before the kernel is started and before the timer task is created + # + # - ot_ncp + # For RCP with OPENTHREAD_CONFIG_LOG_OUTPUT set to APP, this template + # contribution will cause the logs to be printed over spinel before the + # RCP capabilities are sent to the host. + # + # To print logs on NCP/RCP initialization, use the `ot_core_vendor_extension` + # component with this component. + unless: [freertos, ot_ncp] diff --git a/protocol/openthread/component/ot_ncp_cpc.slcc b/protocol/openthread/component/ot_ncp_cpc.slcc index de08d732ab..ee321ada1c 100644 --- a/protocol/openthread/component/ot_ncp_cpc.slcc +++ b/protocol/openthread/component/ot_ncp_cpc.slcc @@ -35,7 +35,6 @@ requires: - device_sdid_200 recommends: - id: ot_stack_rcp - - id: ot_coex include: - path: util/third_party/openthread/src/ file_list: diff --git a/protocol/openthread/component/ot_platform_abstraction.slcc b/protocol/openthread/component/ot_platform_abstraction.slcc index aae5eb507c..da4bf43c75 100644 --- a/protocol/openthread/component/ot_platform_abstraction.slcc +++ b/protocol/openthread/component/ot_platform_abstraction.slcc @@ -28,8 +28,6 @@ requires: - name: gatt_configuration condition: - bluetooth_stack -recommends: - - id: ot_coex config_file: - path: protocol/openthread/config/sl_openthread_rtos_config.h condition: diff --git a/protocol/openthread/config/sl_openthread_generic_config.h b/protocol/openthread/config/sl_openthread_generic_config.h index 92ed2e17dc..7ed1dd71d4 100644 --- a/protocol/openthread/config/sl_openthread_generic_config.h +++ b/protocol/openthread/config/sl_openthread_generic_config.h @@ -68,7 +68,7 @@ #define PACKAGE_NAME "SL-OPENTHREAD" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "SL-OPENTHREAD/2.4.1.0_GitHub-7074a43e4" +#define PACKAGE_STRING "SL-OPENTHREAD/2.4.2.0_GitHub-7074a43e4" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "openthread" @@ -80,13 +80,13 @@ * Note: When adding the label below with OpenThread version, please make * sure it is a valid GitHub version. Avoid merge or local commit hashes. */ -#define PACKAGE_VERSION "2.4.1.0_GitHub-7074a43e4" +#define PACKAGE_VERSION "2.4.2.0_GitHub-7074a43e4" /* Define to 1 if you have the ANSI C header files. */ #define STDC_HEADERS 1 /* Version number of package */ -#define VERSION "2.4.1.0_GitHub-7074a43e4" +#define VERSION "2.4.2.0_GitHub-7074a43e4" /* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most significant byte first (like Motorola and SPARC, unlike Intel). */ diff --git a/protocol/openthread/documentation/release-highlights.txt b/protocol/openthread/documentation/release-highlights.txt index 9b3f586e24..dcd559be98 100644 --- a/protocol/openthread/documentation/release-highlights.txt +++ b/protocol/openthread/documentation/release-highlights.txt @@ -1,5 +1,5 @@ -Silicon Labs OpenThread SDK 2.4.1.0 +Silicon Labs OpenThread SDK 2.4.2.0 Thread: -- Targeted quality improvements and bug fixes -Multi-Protocol -- Targeted quality improvements and bug fixes \ No newline at end of file +- Targeted quality improvements and bug fixes. +Multiprotocol +- Targeted quality improvements and bug fixes. \ No newline at end of file diff --git a/protocol/openthread/documentation/slOpenthread_docContent.xml b/protocol/openthread/documentation/slOpenthread_docContent.xml index 43982d7173..47bc8e1d02 100644 --- a/protocol/openthread/documentation/slOpenthread_docContent.xml +++ b/protocol/openthread/documentation/slOpenthread_docContent.xml @@ -12,7 +12,7 @@ " itemURI="file:an1247-efr32-secure-vault-tamper.pdf" label="AN1247: Anti-Tamper Protection Configuration and Use" priority="50"> - @@ -33,6 +33,10 @@ " itemURI="file:an1311-mbedtls-psa-crypto-porting-guide.pdf" label="AN1311: Integrating Crypto Functionality Using PSA Crypto Compared to Mbed TLS" priority="50"> + + + @@ -98,16 +102,10 @@ - - - - - - + @@ -138,8 +136,10 @@ " itemURI="file:an1329-using-secure-vault-openthread.pdf" label="AN1329: Using Silicon Labs Secure Vault Features with OpenThread" priority="50"/> - + + + diff --git a/protocol/openthread/esf.properties b/protocol/openthread/esf.properties index 74f773ce75..ae6faea2b0 100644 --- a/protocol/openthread/esf.properties +++ b/protocol/openthread/esf.properties @@ -11,10 +11,10 @@ # sure it is a valid GitHub version. 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b/protocol/openthread/libs/libsl_platform_mtd_efr32mg21_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b0cc3da46fe423648c7a21d98455e66e8e6a4867141adb4903ba5d061efd48bf -size 549772 +oid sha256:2952b7dca4fb2e9196c4645875989ae91aecd381807bff5fbcd1067dffe2f05a +size 549256 diff --git a/protocol/openthread/libs/libsl_platform_mtd_efr32mg24_gcc.a b/protocol/openthread/libs/libsl_platform_mtd_efr32mg24_gcc.a index 961cc6020f..0b4566d2c4 100644 --- a/protocol/openthread/libs/libsl_platform_mtd_efr32mg24_gcc.a +++ b/protocol/openthread/libs/libsl_platform_mtd_efr32mg24_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:15b709f8f5b08b029954c446e018e90f3004881252f041d70acf113ebbe7c160 -size 549724 +oid sha256:af7e5d361f8b57d84a38aa30678a23fdaf47e0d7fa76de1388b1ae4eac1b97a9 +size 549208 diff --git a/protocol/openthread/openthread_production_demos.xml b/protocol/openthread/openthread_production_demos.xml index 846a55ebac..eb9423af64 100644 --- a/protocol/openthread/openthread_production_demos.xml +++ b/protocol/openthread/openthread_production_demos.xml @@ -6,7 +6,7 @@ - + @@ -17,7 +17,7 @@ - + @@ -28,7 +28,7 @@ - + @@ -39,7 +39,7 @@ - + @@ -50,7 +50,7 @@ - + @@ -61,7 +61,7 @@ - + @@ -72,7 +72,7 @@ - + @@ -83,7 +83,7 @@ - + @@ -94,7 +94,7 @@ - + @@ -105,7 +105,7 @@ - + @@ -116,7 +116,7 @@ - + @@ -127,7 +127,7 @@ - + @@ -138,7 +138,7 @@ - + @@ -149,7 +149,7 @@ - + @@ -160,7 +160,7 @@ - + @@ -171,7 +171,7 @@ - + @@ -182,7 +182,7 @@ - + @@ -193,7 +193,7 @@ - + @@ -204,7 +204,7 @@ - + @@ -215,7 +215,7 @@ - + @@ -226,7 +226,7 @@ - + @@ -237,7 +237,7 @@ - + @@ -248,7 +248,7 @@ - + @@ -259,7 +259,7 @@ - + @@ -270,7 +270,7 @@ - + @@ -281,7 +281,7 @@ - + @@ -292,7 +292,7 @@ - + @@ -303,7 +303,7 @@ - + @@ -314,7 +314,7 @@ - + @@ -325,7 +325,7 @@ - + @@ -336,7 +336,7 @@ - + @@ -347,7 +347,7 @@ - + @@ -358,7 +358,7 @@ - + @@ -369,7 +369,7 @@ - + @@ -380,7 +380,7 @@ - + @@ -391,7 +391,7 @@ - + @@ -402,7 +402,7 @@ - + @@ -413,7 +413,7 @@ - + @@ -424,7 +424,7 @@ - + @@ -435,7 +435,7 @@ - + @@ -446,7 +446,7 @@ - + @@ -457,7 +457,7 @@ - + @@ -468,7 +468,7 @@ - + @@ -479,7 +479,7 @@ - + @@ -490,7 +490,7 @@ - + @@ -501,7 +501,7 @@ - + @@ -512,7 +512,7 @@ - + @@ -523,7 +523,7 @@ - + @@ -534,7 +534,7 @@ - + @@ -545,7 +545,7 @@ - + @@ -556,7 +556,7 @@ - + @@ -567,7 +567,7 @@ - + @@ -579,7 +579,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + @@ -591,7 +591,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + @@ -603,7 +603,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + @@ -615,7 +615,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + @@ -627,7 +627,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + @@ -638,7 +638,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + @@ -649,7 +649,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + @@ -660,7 +660,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + @@ -671,7 +671,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + @@ -682,7 +682,7 @@ It is identical to the ot-ble-dmp application with the exception that support fo - + diff --git a/protocol/openthread/platform-abstraction/efr32/alarm.c b/protocol/openthread/platform-abstraction/efr32/alarm.c index 5171c64f75..d445a57723 100644 --- a/protocol/openthread/platform-abstraction/efr32/alarm.c +++ b/protocol/openthread/platform-abstraction/efr32/alarm.c @@ -176,8 +176,8 @@ void otPlatAlarmMilliStartAt(otInstance *aInstance, uint32_t aT0, uint32_t aDt) sl_sleeptimer_stop_timer(&sl_handle); - sMsAlarm = aT0 + aDt; - remaining = (int64_t)(sMsAlarm - otPlatAlarmMilliGetNow()); + sMsAlarm = (uint64_t) aT0 + (uint64_t) aDt; + remaining = (int64_t) sMsAlarm - (int64_t) otPlatAlarmMilliGetNow(); sIsMsRunning = true; if (remaining <= 0) @@ -225,7 +225,7 @@ uint64_t efr32AlarmPendingTime(void) uint32_t now = otPlatAlarmMilliGetNow(); if (sIsMsRunning && (sMsAlarm > now)) { - remaining = sMsAlarm - now; + remaining = sMsAlarm - (uint64_t) now; } return remaining; } @@ -256,7 +256,7 @@ void efr32AlarmProcess(otInstance *aInstance) if (sIsMsRunning) { - remaining = (int64_t)(sMsAlarm - otPlatAlarmMilliGetNow()); + remaining = (int64_t) sMsAlarm - (int64_t) otPlatAlarmMilliGetNow(); if (remaining <= 0) { otPlatAlarmMilliStop(aInstance); @@ -267,7 +267,7 @@ void efr32AlarmProcess(otInstance *aInstance) #if OPENTHREAD_CONFIG_PLATFORM_USEC_TIMER_ENABLE if (sIsUsRunning) { - remaining = (int64_t)(sUsAlarm - otPlatAlarmMicroGetNow()); + remaining = (int64_t) sUsAlarm - (int64_t) otPlatAlarmMicroGetNow(); if (remaining <= 0) { otPlatAlarmMicroStop(aInstance); @@ -335,8 +335,8 @@ void otPlatAlarmMicroStartAt(otInstance *aInstance, uint32_t aT0, uint32_t aDt) RAIL_CancelMultiTimer(&rail_timer); - sUsAlarm = aT0 + aDt; - remaining = (int64_t)(sUsAlarm - otPlatAlarmMicroGetNow()); + sUsAlarm = (uint64_t) aT0 + (uint64_t) aDt; + remaining = (int64_t) sUsAlarm - (int64_t) otPlatAlarmMicroGetNow(); sIsUsRunning = true; if (remaining <= 0) diff --git a/protocol/openthread/platform-abstraction/efr32/misc.c b/protocol/openthread/platform-abstraction/efr32/misc.c index f6eb6f2bea..64ac03c4c2 100644 --- a/protocol/openthread/platform-abstraction/efr32/misc.c +++ b/protocol/openthread/platform-abstraction/efr32/misc.c @@ -67,16 +67,23 @@ void otPlatReset(otInstance *aInstance) NVIC_SystemReset(); } -#if defined(SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT) -#if OPENTHREAD_CONFIG_PLATFORM_BOOTLOADER_MODE_ENABLE +OT_TOOL_WEAK void bootloader_rebootAndInstall(void) +{ + // Weak stub function + // This should be discarded in favor of the function definition in bootloader_interface code, when that component is used +} + otError otPlatResetToBootloader(otInstance *aInstance) { OT_UNUSED_VARIABLE(aInstance); bootloader_rebootAndInstall(); - return OT_ERROR_NONE; + + // This should only be reached if the bootloader_interface component is not present. + // When it is present, the stubbed bootloader_rebootAndInstall above is not used. + // Instead, the non-weak definition of the function in the component is used, causing + // the device to reset. + return OT_ERROR_NOT_CAPABLE; } -#endif -#endif otPlatResetReason otPlatGetResetReason(otInstance *aInstance) { diff --git a/protocol/openthread/platform-abstraction/efr32/openthread-core-efr32-config.h b/protocol/openthread/platform-abstraction/efr32/openthread-core-efr32-config.h index 3efc3c1340..7bcc51a58b 100644 --- a/protocol/openthread/platform-abstraction/efr32/openthread-core-efr32-config.h +++ b/protocol/openthread/platform-abstraction/efr32/openthread-core-efr32-config.h @@ -63,8 +63,12 @@ * Allow triggering a platform reset to bootloader mode, if supported. * */ +#ifndef OPENTHREAD_CONFIG_PLATFORM_BOOTLOADER_MODE_ENABLE #if defined(SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT) #define OPENTHREAD_CONFIG_PLATFORM_BOOTLOADER_MODE_ENABLE 1 +#else +#define OPENTHREAD_CONFIG_PLATFORM_BOOTLOADER_MODE_ENABLE 0 +#endif #endif /** diff --git a/protocol/openthread/platform-abstraction/efr32/platform-efr32.h b/protocol/openthread/platform-abstraction/efr32/platform-efr32.h index b5fc976bdf..6d1267e6ab 100644 --- a/protocol/openthread/platform-abstraction/efr32/platform-efr32.h +++ b/protocol/openthread/platform-abstraction/efr32/platform-efr32.h @@ -35,6 +35,10 @@ #ifndef PLATFORM_EFR32_H_ #define PLATFORM_EFR32_H_ +#ifdef __cplusplus +extern "C" { +#endif + #include #include "em_device.h" @@ -198,4 +202,8 @@ otError efr32RadioLoadChannelConfig(uint8_t aChannel, int8_t aTxPower); otError railStatusToOtError(RAIL_Status_t status); +#ifdef __cplusplus +} +#endif + #endif // PLATFORM_EFR32_H_ diff --git a/protocol/openthread/platform-abstraction/efr32/radio.c b/protocol/openthread/platform-abstraction/efr32/radio.c index 716fa57ba1..26bb1f9c84 100644 --- a/protocol/openthread/platform-abstraction/efr32/radio.c +++ b/protocol/openthread/platform-abstraction/efr32/radio.c @@ -231,7 +231,7 @@ typedef struct uint32_t timestamp; } rxPacketDetails; -typedef struct +typedef struct { rxPacketDetails packetInfo; uint8_t psdu[IEEE802154_MAX_LENGTH]; @@ -1007,7 +1007,13 @@ static inline void setInternalFlag(uint16_t flag, bool val) // Returns true if the passed flag is set, false otherwise. static inline bool getInternalFlag(uint16_t flag) { - return ((miscRadioState & flag) != 0); + bool isFlagSet; + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + isFlagSet = (miscRadioState & flag) ? true : false; + CORE_EXIT_ATOMIC(); + + return isFlagSet; } static inline bool txWaitingForAck(void) @@ -1526,11 +1532,11 @@ otRadioState otPlatRadioGetState(otInstance *aInstance) case RAIL_RF_STATE_RX_ACTIVE: radioState = OT_RADIO_STATE_RECEIVE; break; - + case RAIL_RF_STATE_TX_ACTIVE: radioState = OT_RADIO_STATE_TRANSMIT; break; - + case RAIL_RF_STATE_IDLE: radioState = OT_RADIO_STATE_SLEEP; break; @@ -1682,6 +1688,7 @@ otError otPlatRadioTransmit(otInstance *aInstance, otRadioFrame *aFrame) OT_ASSERT(!getInternalFlag(FLAG_ONGOING_TX_DATA)); OT_ASSERT(aFrame == &sTransmitFrame); + OT_ASSERT(aFrame->mPsdu == sTransmitPsdu); setInternalFlag(RADIO_TX_EVENTS, false); sTxFrame = aFrame; @@ -2589,7 +2596,7 @@ static void packetReceivedCallback(RAIL_RxPacketHandle_t packetHandle) #if SL_OPENTHREAD_RADIO_RX_BUFFER_COUNT > 1 if(!packetDetails.isAck) - { + { receiveBufferInUse = getFreeBufferIndex(); otEXPECT_ACTION(receiveBufferInUse < SL_OPENTHREAD_RADIO_RX_BUFFER_COUNT, dropPacket = true); psdu = sReceivePacket[receiveBufferInUse].psdu; @@ -2693,7 +2700,7 @@ static void packetReceivedCallback(RAIL_RxPacketHandle_t packetHandle) (void) RAIL_ReleaseRxPacket(gRailHandle, packetHandle); (void) handlePhyStackEvent(SL_RAIL_UTIL_IEEE802154_STACK_EVENT_RX_CORRUPTED, (uint32_t) isReceivingFrame()); - } + } } static void packetSentCallback(bool isAck) @@ -3045,10 +3052,10 @@ static void RAILCb_Generic(RAIL_Handle_t aRailHandle, RAIL_Events_t aEvents) railDebugCounters.mRailPlatRadioEnergyScanDoneCbCount++; #endif } - // scheduled and unscheduled config events happen very often, + // scheduled and unscheduled config events happen very often, // especially in a DMP situation where there is an active BLE connection. - // Waking up the OT RTOS task on every one of these occurrences causes - // a lower priority CLI task to starve and makes it appear like a code lockup + // Waking up the OT RTOS task on every one of these occurrences causes + // a lower priority CLI task to starve and makes it appear like a code lockup // There is no reason to wake the OT task for these events! if ( !(aEvents & RAIL_EVENT_CONFIG_SCHEDULED) && !(aEvents & RAIL_EVENT_CONFIG_UNSCHEDULED)) { otSysEventSignalPending(); @@ -3068,7 +3075,7 @@ static bool validatePacketDetails(RAIL_RxPacketHandle_t packetHandle, #if RADIO_CONFIG_DEBUG_COUNTERS_SUPPORT rxDebugStep = 0; #endif - + rStatus = RAIL_GetRxPacketDetailsAlt(gRailHandle, packetHandle, pPacketDetails); otEXPECT_ACTION(rStatus == RAIL_STATUS_NO_ERROR, pktValid = false); #if RADIO_CONFIG_DEBUG_COUNTERS_SUPPORT @@ -3364,7 +3371,7 @@ static void processTxComplete(otInstance *aInstance) { otError txStatus; otRadioFrame *ackFrame = NULL; - + if(getInternalFlag(RADIO_TX_EVENTS)) { if(getInternalFlag(EVENT_TX_SUCCESS)) diff --git a/protocol/openthread/platform-abstraction/efr32/sl_rcp_gp_interface.c b/protocol/openthread/platform-abstraction/efr32/sl_rcp_gp_interface.c index 13d9daaaaf..1d8a51f64b 100644 --- a/protocol/openthread/platform-abstraction/efr32/sl_rcp_gp_interface.c +++ b/protocol/openthread/platform-abstraction/efr32/sl_rcp_gp_interface.c @@ -41,6 +41,7 @@ #include #include #include "common/logging.hpp" +#include "utils/code_utils.h" #include "utils/mac_frame.h" // This implements mechanism to buffer outgoing Channel Configuration (0xF3) and @@ -160,6 +161,8 @@ bool sl_gp_intf_is_gp_pkt(otRadioFrame *aFrame, bool isRxFrame) uint8_t fc = *gpFrameStartIndex; + otEXPECT_ACTION(gp_state == SL_GP_STATE_WAITING_FOR_PKT, isGpPkt = false); + otLogDebgPlat("GP RCP INTF : (%s) PL Index = %d Channel = %d Length = %d FC = %0X", isRxFrame ? "Rx" : "Tx", (gpFrameStartIndex - aFrame->mPsdu), @@ -261,10 +264,12 @@ bool sl_gp_intf_is_gp_pkt(otRadioFrame *aFrame, bool isRxFrame) } } } + if (isGpPkt) { otLogDebgPlat("GP RCP INTF: GP filter passed!!"); } +exit: return isGpPkt; } diff --git a/protocol/openthread/platform-abstraction/posix/cpc_interface.cpp b/protocol/openthread/platform-abstraction/posix/cpc_interface.cpp index 8c2680c994..67799f6aa4 100644 --- a/protocol/openthread/platform-abstraction/posix/cpc_interface.cpp +++ b/protocol/openthread/platform-abstraction/posix/cpc_interface.cpp @@ -68,6 +68,7 @@ namespace Posix { // ---------------------------------------------------------------------------- volatile sig_atomic_t CpcInterfaceImpl::sCpcResetReq = false; +bool CpcInterfaceImpl::sIsCpcInitialized = false; CpcInterfaceImpl::CpcInterfaceImpl(const Url::Url &aRadioUrl) : mReceiveFrameCallback(nullptr) @@ -90,18 +91,27 @@ otError CpcInterfaceImpl::Init(ReceiveFrameCallback aCallback, VerifyOrExit(mSockFd == -1, error = OT_ERROR_ALREADY); - if (cpc_init(&mHandle, mRadioUrl.GetPath(), false, HandleSecondaryReset) != 0) + if (!sIsCpcInitialized) { - otLogCritPlat("CPC init failed. Ensure radio-url argument has the form 'spinel+cpc://cpcd_0?iid=<1..3>'"); - DieNow(OT_EXIT_FAILURE); - } + if (cpc_init(&mHandle, mRadioUrl.GetPath(), false, HandleSecondaryReset) != 0) + { + otLogCritPlat("CPC init failed. Ensure radio-url argument has the form 'spinel+cpc://cpcd_0?iid=<1..3>'"); + DieNow(OT_EXIT_FAILURE); + } - mSockFd = cpc_open_endpoint(mHandle, &mEndpoint, mId, 1); + mSockFd = cpc_open_endpoint(mHandle, &mEndpoint, mId, 1); - if (mSockFd < 0) + if (mSockFd < 0) + { + otLogCritPlat("CPC endpoint open failed"); + error = OT_ERROR_FAILED; + } + } + else { - otLogCritPlat("CPC endpoint open failed"); - error = OT_ERROR_FAILED; + // Re-initialize the CPC interface. + SetCpcResetReq(true); + CheckAndReInitCpc(); } if ((value = mRadioUrl.GetValue("cpc-bus-speed"))) @@ -110,6 +120,7 @@ otError CpcInterfaceImpl::Init(ReceiveFrameCallback aCallback, } otLogCritPlat("mCpcBusSpeed = %d", mCpcBusSpeed); + sIsCpcInitialized = true; mReceiveFrameCallback = aCallback; mReceiveFrameContext = aCallbackContext; diff --git a/protocol/openthread/platform-abstraction/posix/cpc_interface.hpp b/protocol/openthread/platform-abstraction/posix/cpc_interface.hpp index 77b56174e4..07d5a3c1c4 100644 --- a/protocol/openthread/platform-abstraction/posix/cpc_interface.hpp +++ b/protocol/openthread/platform-abstraction/posix/cpc_interface.hpp @@ -264,6 +264,7 @@ class CpcInterfaceImpl : public ot::Spinel::SpinelInterface const uint8_t mId = SL_CPC_ENDPOINT_15_4; typedef uint8_t cpcError; static volatile sig_atomic_t sCpcResetReq; + static bool sIsCpcInitialized; otRcpInterfaceMetrics mInterfaceMetrics; diff --git a/protocol/openthread/src/core/vendor_extension.cpp b/protocol/openthread/src/core/vendor_extension.cpp new file mode 100644 index 0000000000..018c783b88 --- /dev/null +++ b/protocol/openthread/src/core/vendor_extension.cpp @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2024, The OpenThread Authors. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file + * This file implements a OpenThread vendor extension for EFR32 + */ + +#include "openthread-core-config.h" + +#include "common/code_utils.hpp" +#include "common/new.hpp" + +#include "instance/extension.hpp" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#include "platform-efr32.h" + +namespace ot { +namespace Extension { + +/** + * Defines the vendor extension object. + * + */ +class Extension : public ExtensionBase +{ +public: + explicit Extension(Instance &aInstance) + : ExtensionBase(aInstance) + { + } +}; + +// ---------------------------------------------------------------------------- +// `ExtensionBase` API +// ---------------------------------------------------------------------------- + +static OT_DEFINE_ALIGNED_VAR(sExtensionRaw, sizeof(Extension), uint64_t); + +ExtensionBase &ExtensionBase::Init(Instance &aInstance) +{ + ExtensionBase *ext = reinterpret_cast(&sExtensionRaw); + + VerifyOrExit(!ext->mIsInitialized); + + ext = new (&sExtensionRaw) Extension(aInstance); + +exit: + return *ext; +} + +void ExtensionBase::SignalInstanceInit(void) +{ + // OpenThread instance is initialized and ready. +} + +void ExtensionBase::SignalNcpInit(Ncp::NcpBase &aNcpBase) +{ + // NCP instance is initialized and ready. + OT_UNUSED_VARIABLE(aNcpBase); + +#if defined(SL_CATALOG_OT_CRASH_HANDLER_PRESENT) + efr32PrintResetInfo(); +#endif +} + +void ExtensionBase::HandleNotifierEvents(Events aEvents) +{ + OT_UNUSED_VARIABLE(aEvents); +} + +} // namespace Extension +} // namespace ot diff --git a/protocol/openthread/src/legacy_hal/diagnostic.c b/protocol/openthread/src/legacy_hal/diagnostic.c index 4e2bba303d..2b5d480c03 100644 --- a/protocol/openthread/src/legacy_hal/diagnostic.c +++ b/protocol/openthread/src/legacy_hal/diagnostic.c @@ -16,6 +16,8 @@ * sections of the MSLA applicable to Source Code. * ******************************************************************************/ +/* clang-format off */ + #include PLATFORM_HEADER #include @@ -26,7 +28,7 @@ #include "em_emu.h" #include "em_rmu.h" -#include "logging.h" +#include // Crash info live in noinit RAM segment that is not modified during startup. NO_INIT(HalCrashInfoType halCrashInfo); diff --git a/protocol/usb/src/sl_usbd_core_os.c b/protocol/usb/src/sl_usbd_core_os.c index 1cd06e05fa..de00f257f0 100644 --- a/protocol/usb/src/sl_usbd_core_os.c +++ b/protocol/usb/src/sl_usbd_core_os.c @@ -64,12 +64,9 @@ static const osMessageQueueAttr_t message_queue_attr = { .mq_size = 0 }; -// parameters for event flags -static osEventFlagsId_t eventflags_handle[SL_USBD_OPEN_ENDPOINTS_QUANTITY]; -static osEventFlagsAttr_t eventflags_attr[SL_USBD_OPEN_ENDPOINTS_QUANTITY]; - -#define EVENT_FLAG_COMPLETE 0x1 // signal posted -#define EVENT_FLAG_ABORT 0x2 // signal aborted +// parameters for semaphore +static osSemaphoreAttr_t sem_attr[SL_USBD_OPEN_ENDPOINTS_QUANTITY]; +static osSemaphoreId_t sem_id[SL_USBD_OPEN_ENDPOINTS_QUANTITY]; // parameters for mutex static osMutexId_t mutex_handle[SL_USBD_OPEN_ENDPOINTS_QUANTITY]; @@ -124,14 +121,13 @@ sl_status_t sli_usbd_core_os_create_endpoint_signal(uint8_t endpoint) return SL_STATUS_FAIL; } - eventflags_attr[endpoint].name = "USBD events"; - eventflags_attr[endpoint].attr_bits = 0; - eventflags_attr[endpoint].cb_mem = NULL; - eventflags_attr[endpoint].cb_size = 0; - - eventflags_handle[endpoint] = osEventFlagsNew(&eventflags_attr[endpoint]); + sem_attr[endpoint].name = "USBD semaphore"; + sem_attr[endpoint].attr_bits = 0u; + sem_attr[endpoint].cb_mem = NULL; + sem_attr[endpoint].cb_size = 0; - if (eventflags_handle[endpoint] == NULL) { + sem_id[endpoint] = osSemaphoreNew(SL_USBD_OPEN_ENDPOINTS_QUANTITY, 0, &sem_attr[endpoint]); + if (sem_id[endpoint] == NULL) { return SL_STATUS_FAIL; } @@ -147,11 +143,11 @@ sl_status_t sli_usbd_core_os_delete_endpoint_signal(uint8_t endpoint) return SL_STATUS_FAIL; } - if (osEventFlagsDelete(eventflags_handle[endpoint]) != osOK) { + if (osSemaphoreDelete(sem_id[endpoint]) != osOK) { return SL_STATUS_FAIL; } - eventflags_handle[endpoint] = NULL; + sem_id[endpoint] = NULL; return SL_STATUS_OK; } @@ -163,7 +159,7 @@ sl_status_t sli_usbd_core_os_pend_endpoint_signal(uint8_t endpoint, uint16_t timeout_ms) { uint32_t ticks; - uint32_t status; + osStatus_t status; if (endpoint >= SL_USBD_OPEN_ENDPOINTS_QUANTITY) { return SL_STATUS_FAIL; @@ -175,20 +171,16 @@ sl_status_t sli_usbd_core_os_pend_endpoint_signal(uint8_t endpoint, ticks = usbd_core_os_ms_to_ticks(timeout_ms); } - status = osEventFlagsWait(eventflags_handle[endpoint], EVENT_FLAG_COMPLETE | EVENT_FLAG_ABORT, osFlagsWaitAny, ticks); + status = osSemaphoreAcquire(sem_id[endpoint], ticks); - if (status == osFlagsErrorTimeout) { + if (status == osErrorTimeout) { return SL_STATUS_TIMEOUT; } - if (status & osFlagsError) { + if (status != osOK) { return SL_STATUS_FAIL; } - if ((status & EVENT_FLAG_ABORT) == EVENT_FLAG_ABORT) { - return SL_STATUS_ABORT; - } - return SL_STATUS_OK; } @@ -201,7 +193,7 @@ sl_status_t sli_usbd_core_os_abort_endpoint_signal(uint8_t endpoint) return SL_STATUS_FAIL; } - if (osEventFlagsSet(eventflags_handle[endpoint], EVENT_FLAG_ABORT) != osOK) { + if (osSemaphoreRelease(sem_id[endpoint]) != osOK) { return SL_STATUS_FAIL; } @@ -217,7 +209,7 @@ sl_status_t sli_usbd_core_os_post_endpoint_signal(uint8_t endpoint) return SL_STATUS_FAIL; } - if (osEventFlagsSet(eventflags_handle[endpoint], EVENT_FLAG_COMPLETE) != osOK) { + if (osSemaphoreRelease(sem_id[endpoint]) != osOK) { return SL_STATUS_FAIL; } diff --git a/protocol/usb/src/sl_usbd_driver_dwc_otg_fs.c b/protocol/usb/src/sl_usbd_driver_dwc_otg_fs.c index 363c6a391e..2205e18332 100644 --- a/protocol/usb/src/sl_usbd_driver_dwc_otg_fs.c +++ b/protocol/usb/src/sl_usbd_driver_dwc_otg_fs.c @@ -56,6 +56,9 @@ ******************************************************************************************************** *******************************************************************************************************/ +#define USB_BULK_IN_OPTIMIZATION_MAX_XFER_BURST_BYTES (8u * MAX_PKT_SIZE) +#define USB_BULK_OUT_OPTIMIZATION_MAX_XFER_BURST_BYTES (8u * MAX_PKT_SIZE) + #define REG_VAL_TO 0x1Fu #define REG_FMOD_TO 0x7FFFFu @@ -984,8 +987,10 @@ sl_status_t sli_usbd_driver_endpoint_rx_start(uint8_t ep_addr, uint8_t ep_phy_nbr; uint16_t ep_pkt_len; uint16_t pkt_cnt; + uint16_t pkt_size_temp; uint32_t ctl_reg; uint32_t tsiz_reg; + uint32_t ep_type; __IOM uint32_t *doep_ctl_ptr; __IOM uint32_t *doep_tsiz_ptr; __IOM uint32_t *doep_dmaaddr_ptr; @@ -999,7 +1004,6 @@ sl_status_t sli_usbd_driver_endpoint_rx_start(uint8_t ep_addr, ep_log_nbr = SL_USBD_ENDPOINT_ADDR_TO_LOG(ep_addr); ep_phy_nbr = SL_USBD_ENDPOINT_ADDR_TO_PHY(ep_addr); - ep_pkt_len = (uint16_t)SLI_USBD_GET_MIN(buf_len, usbd_driver_data.EP_MaxPktSize[ep_phy_nbr]); SLI_USBD_LOG_VRB(("USBD driver EP FIFO RxStart for endpoint addr: 0x", (X)ep_addr)); @@ -1008,6 +1012,20 @@ sl_status_t sli_usbd_driver_endpoint_rx_start(uint8_t ep_addr, doep_tsiz_ptr = (ep_log_nbr != 0) ? &USB_REG->DOEP_REG[ep_log_nbr - 1].TSIZ : &USB_REG->DOEP0TSIZ; doep_dmaaddr_ptr = (ep_log_nbr != 0) ? &USB_REG->DOEP_REG[ep_log_nbr - 1].DMAADDR : &USB_REG->DOEP0DMAADDR; + ep_type = (*doep_ctl_ptr >> 18u) & 0x03u; + + if ((SL_USBD_ENDPOINT_IS_IN(ep_addr) == false) \ + && (ep_type == SL_USBD_ENDPOINT_TYPE_BULK)) { + // The default burst value of USB_BULK_OUT_OPTIMIZATION_MAX_XFER_BURST_BYTES is 8 64-byte packet. + // It allows to have burst of packets between 2 and 8 packets (if the application Rx buffer is large enough) + // before notifying the USB Core layer about a transfer completion. + pkt_size_temp = USB_BULK_OUT_OPTIMIZATION_MAX_XFER_BURST_BYTES; + } else { + pkt_size_temp = usbd_driver_data.EP_MaxPktSize[ep_phy_nbr]; + } + + ep_pkt_len = (uint16_t)SLI_USBD_GET_MIN(buf_len, pkt_size_temp); + // Read Control and Transfer EP registers ctl_reg = *doep_ctl_ptr; tsiz_reg = *doep_tsiz_ptr; @@ -1016,18 +1034,19 @@ sl_status_t sli_usbd_driver_endpoint_rx_start(uint8_t ep_addr, tsiz_reg &= ~(DOEPTSIZx_XFRSIZ_MSK | DOEPTSIZx_PKTCNT_MSK); if (buf_len == 0u) { - tsiz_reg |= usbd_driver_data.EP_MaxPktSize[ep_phy_nbr]; // Set transfer size to max pkt size - tsiz_reg |= (1u << 19u); // Set packet count + tsiz_reg |= usbd_driver_data.EP_MaxPktSize[ep_phy_nbr]; // Set transfer size to max pkt size + tsiz_reg |= (1u << 19u); // Set packet count + pkt_cnt = 1u; } else { pkt_cnt = (ep_pkt_len + (usbd_driver_data.EP_MaxPktSize[ep_phy_nbr] - 1u)) / usbd_driver_data.EP_MaxPktSize[ep_phy_nbr]; - tsiz_reg |= (pkt_cnt << 19u); // Set packet count - // Set transfer size + tsiz_reg |= (pkt_cnt << 19u); // Set packet count + // Set transfer size tsiz_reg |= pkt_cnt * usbd_driver_data.EP_MaxPktSize[ep_phy_nbr]; } usbd_driver_data.EP_AppBufPtr[ep_phy_nbr] = p_buf; - usbd_driver_data.EP_AppBufLen[ep_phy_nbr] = ep_pkt_len; + usbd_driver_data.EP_AppBufLen[ep_phy_nbr] = pkt_cnt * usbd_driver_data.EP_MaxPktSize[ep_phy_nbr]; // Set buffer address to receive data *doep_dmaaddr_ptr = (uint32_t)usbd_driver_data.EP_AppBufPtr[ep_phy_nbr]; @@ -1085,6 +1104,10 @@ sl_status_t sli_usbd_driver_endpoint_rx_zlp(uint8_t ep_addr) /****************************************************************************************************//** * Configure endpoint with buffer to transmit data +* +* Note(s) : (1) USB_BULK_IN_OPTIMIZATION_MAX_XFER_BURST_BYTES is equal to 8 packets of 64 bytes +* because the USB OTG FS peripheral has the following characteristics: the maximum +* number of packets maintained by the core at any time in an IN endpoint FIFO is 8. ********************************************************************************************************/ sl_status_t sli_usbd_driver_endpoint_tx(uint8_t ep_addr, uint8_t *p_buf, @@ -1094,7 +1117,10 @@ sl_status_t sli_usbd_driver_endpoint_tx(uint8_t ep_addr, uint8_t ep_phy_nbr; uint16_t ep_pkt_len; uint8_t ep_log_nbr; + uint16_t pkt_size_temp; + uint32_t ep_type; __IOM uint32_t *diep_dmaaddr_ptr; + __IOM uint32_t *diep_ctl_ptr; // Validate that the buffer is correctly 4 bytes aligned if (((uint32_t)p_buf % BUFFER_BYTE_ALIGNMENT) != 0u) { @@ -1103,7 +1129,19 @@ sl_status_t sli_usbd_driver_endpoint_tx(uint8_t ep_addr, ep_phy_nbr = SL_USBD_ENDPOINT_ADDR_TO_PHY(ep_addr); ep_log_nbr = SL_USBD_ENDPOINT_ADDR_TO_LOG(ep_addr); - ep_pkt_len = (uint16_t)SLI_USBD_GET_MIN(usbd_driver_data.EP_MaxPktSize[ep_phy_nbr], buf_len); + + diep_ctl_ptr = (ep_log_nbr != 0) ? &USB_REG->DIEP_REG[ep_log_nbr - 1].CTL : &USB_REG->DIEP0CTL; + ep_type = (*diep_ctl_ptr >> 18u) & 0x03u; + + if ((SL_USBD_ENDPOINT_IS_IN(ep_addr) == true) \ + && (ep_type == SL_USBD_ENDPOINT_TYPE_BULK)) { + // See Note #1. + pkt_size_temp = USB_BULK_IN_OPTIMIZATION_MAX_XFER_BURST_BYTES; + } else { + pkt_size_temp = usbd_driver_data.EP_MaxPktSize[ep_phy_nbr]; + } + + ep_pkt_len = (uint16_t)SLI_USBD_GET_MIN(pkt_size_temp, buf_len); diep_dmaaddr_ptr = (ep_log_nbr != 0) ? &USB_REG->DIEP_REG[ep_log_nbr - 1].DMAADDR : &USB_REG->DIEP0DMAADDR; @@ -1125,6 +1163,7 @@ sl_status_t sli_usbd_driver_endpoint_tx_start(uint8_t ep_addr, uint8_t ep_log_nbr; uint32_t ctl_reg; uint32_t tsiz_reg; + uint32_t ep_type; __IOM uint32_t *diep_ctl_ptr; __IOM uint32_t *diep_tsiz_ptr; @@ -1142,7 +1181,22 @@ sl_status_t sli_usbd_driver_endpoint_tx_start(uint8_t ep_addr, tsiz_reg &= ~DIEPTSIZx_XFRSIZ_MSK; // Clear EP transfer size tsiz_reg |= buf_len; // Transfer size - tsiz_reg |= (1u << 19u); // Packet count + + ep_type = (*diep_ctl_ptr >> 18u) & 0x03u; + + if ((SL_USBD_ENDPOINT_IS_IN(ep_addr) == true) \ + && (ep_type == SL_USBD_ENDPOINT_TYPE_BULK) + && (buf_len != 0)) { + uint8_t ep_phy_nbr = SL_USBD_ENDPOINT_ADDR_TO_PHY(ep_addr); + uint16_t max_pkt_size = usbd_driver_data.EP_MaxPktSize[ep_phy_nbr]; + uint32_t pkt_cnt = buf_len / max_pkt_size; + + pkt_cnt += ((buf_len % max_pkt_size) == 0u) ? 0 : 1; + + tsiz_reg |= (pkt_cnt << 19u); // Packet count + } else { + tsiz_reg |= (1u << 19u); // Packet count + } // Clear EP NAK mode & Enable EP transmitting. ctl_reg |= DxEPCTLx_BIT_CNAK | DxEPCTLx_BIT_EPENA; @@ -1587,11 +1641,25 @@ static void DWC_EP_OutProcess(void) // Handle OUT transaction complete if (SL_IS_BIT_SET(ep_int_stat, DOEPINTx_BIT_XFRC)) { + uint16_t byte_cnt; + sl_usbd_core_endpoint_read_complete(ep_log_nbr); // Save size of data received uint32_t size_rem = *doep_tsiz_ptr & DOEPTSIZx_XFRSIZ_MSK; - uint16_t byte_cnt = usbd_driver_data.EP_MaxPktSize[ep_phy_nbr] - size_rem; + + uint32_t ep_type = (*doep_ctl_ptr >> 18u) & 0x03u; + + if (ep_type == SL_USBD_ENDPOINT_TYPE_BULK) { + // Bulk OUT supports transfer-level operation. The payload size in memory is equal to + // "application-programmed initial transfer size – core updated final transfer size". + // .EP_AppBufLen[] is used in sli_usbd_driver_endpoint_rx_start() to save the initial app + // transfer size. + byte_cnt = usbd_driver_data.EP_AppBufLen[ep_phy_nbr] - size_rem; + } else { + byte_cnt = usbd_driver_data.EP_MaxPktSize[ep_phy_nbr] - size_rem; + } + usbd_driver_data.EP_PktXferLen[ep_phy_nbr] += byte_cnt; if (ep_log_nbr == 0) { diff --git a/protocol/wisun/app/wisun_rcp/sl_wsrcp_btl_interface.c b/protocol/wisun/app/wisun_rcp/sl_wsrcp_btl_interface.c new file mode 100644 index 0000000000..02b65ca858 --- /dev/null +++ b/protocol/wisun/app/wisun_rcp/sl_wsrcp_btl_interface.c @@ -0,0 +1,27 @@ +/***************************************************************************//** + * Copyright 2023-2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available here[1]. This software is distributed to you in + * Source Code format and is governed by the sections of the MSLA applicable to + * Source Code. + * + * [1] www.silabs.com/about-us/legal/master-software-license-agreement + * + ******************************************************************************/ +#include "sl_component_catalog.h" +#include "sl_wsrcp_btl_interface.h" +#include "sl_wsrcp_log.h" + +#include + +void wisun_rcp_btl_reset(void) +{ + int32_t ret; + + ret = bootloader_init(); + BUG_ON(ret != BOOTLOADER_OK); + bootloader_rebootAndInstall(); +} diff --git a/protocol/wisun/app/wisun_rcp/sl_wsrcp_btl_interface.h b/protocol/wisun/app/wisun_rcp/sl_wsrcp_btl_interface.h index b053f546ec..3fa9e20d2f 100644 --- a/protocol/wisun/app/wisun_rcp/sl_wsrcp_btl_interface.h +++ b/protocol/wisun/app/wisun_rcp/sl_wsrcp_btl_interface.h @@ -14,33 +14,8 @@ #ifndef SL_WSRCP_BTL_INTERFACE_H #define SL_WSRCP_BTL_INTERFACE_H -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif -#include "sl_wsrcp_log.h" - struct sl_wsrcp_mac; -#ifdef SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT -#include - -static inline void wisun_rcp_btl_reset(struct sl_wsrcp_mac *rcp_mac) -{ - int32_t ret; - - (void)rcp_mac; - ret = bootloader_init(); - BUG_ON(ret != BOOTLOADER_OK); - bootloader_rebootAndInstall(); -} -#else -#include "sl_wsrcp_hif.h" - -static inline void wisun_rcp_btl_reset(struct sl_wsrcp_mac *rcp_mac) -{ - (void)rcp_mac; - FATAL(HIF_ENOBTL, "missing bootloader_interface component"); -} -#endif // SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT +void wisun_rcp_btl_reset(void); #endif // SL_WSRCP_BTL_INTERFACE_H diff --git a/protocol/wisun/app/wisun_rcp/sl_wsrcp_hif.h b/protocol/wisun/app/wisun_rcp/sl_wsrcp_hif.h index 319c131ad8..348b932ff8 100644 --- a/protocol/wisun/app/wisun_rcp/sl_wsrcp_hif.h +++ b/protocol/wisun/app/wisun_rcp/sl_wsrcp_hif.h @@ -79,6 +79,7 @@ enum hif_fatal_code { HIF_EINVAL_ADDR_MODE = 0x100e, HIF_EINVAL_SCF = 0x100f, HIF_EINVAL_FRAME = 0x1010, + HIF_EINVAL_CHAN_FIXED = 0x1011, HIF_ENOTSUP = 0x2000, HIF_ENOTSUP_FHSS_DEFAULT = 0x2001, }; diff --git a/protocol/wisun/app/wisun_soc_cli/app_cli.c b/protocol/wisun/app/wisun_soc_cli/app_cli.c index 22d40c5732..9264f7efcb 100644 --- a/protocol/wisun/app/wisun_soc_cli/app_cli.c +++ b/protocol/wisun/app/wisun_soc_cli/app_cli.c @@ -771,6 +771,15 @@ static void app_handle_lfn_multicast_reg_ind(sl_wisun_evt_t *evt) } } +static void app_handle_dhcp_vendor_data_ind(sl_wisun_evt_t *evt) +{ + printf("[Vendor data received: Enterprise Number %"PRIu32"]\r\nPayload: ", evt->evt.dhcp_vendor_data.enterprise_number); + for (uint8_t i = 0; i < evt->evt.dhcp_vendor_data.data_length; i++) { + printf("%02x ", evt->evt.dhcp_vendor_data.data[i]); + } + printf("\r\n"); +} + void sl_wisun_on_event(sl_wisun_evt_t *evt) { sl_status_t result; @@ -825,6 +834,9 @@ void sl_wisun_on_event(sl_wisun_evt_t *evt) case SL_WISUN_MSG_LFN_MULTICAST_REG_IND_ID: app_handle_lfn_multicast_reg_ind(evt); break; + case SL_WISUN_MSG_DHCP_VENDOR_DATA_IND_ID: + app_handle_dhcp_vendor_data_ind(evt); + break; default: printf("[Unknown event: %d]\r\n", evt->header.id); } diff --git a/protocol/wisun/app/wisun_soc_cli/app_settings.c b/protocol/wisun/app/wisun_soc_cli/app_settings.c index 38b0abca1c..ef4b9d35a7 100644 --- a/protocol/wisun/app/wisun_soc_cli/app_settings.c +++ b/protocol/wisun/app/wisun_soc_cli/app_settings.c @@ -147,6 +147,7 @@ #define APP_SETTINGS_WISUN_DEFAULT_CRC_TYPE SL_WISUN_4_BYTES_CRC #define APP_SETTINGS_WISUN_DEFAULT_STF_LENGTH 4 #define APP_SETTINGS_WISUN_DEFAULT_PREAMBLE_LENGTH 56 +#define APP_SETTINGS_WISUN_MAC_NEIGHBOR_TABLE_SIZE 22 #ifndef APP_SETTINGS_APP_DEFAULT_AUTOCONNECT #define APP_SETTINGS_APP_DEFAULT_AUTOCONNECT 0 @@ -231,7 +232,8 @@ static const app_settings_wisun_t app_settings_wisun_default = { .lfn_profile = APP_SETTINGS_WISUN_DEFAULT_LFN_PROFILE, .crc_type = APP_SETTINGS_WISUN_DEFAULT_CRC_TYPE, .stf_length = APP_SETTINGS_WISUN_DEFAULT_STF_LENGTH, - .preamble_length = APP_SETTINGS_WISUN_DEFAULT_PREAMBLE_LENGTH + .preamble_length = APP_SETTINGS_WISUN_DEFAULT_PREAMBLE_LENGTH, + .mac_neighbor_table_size = APP_SETTINGS_WISUN_MAC_NEIGHBOR_TABLE_SIZE, }; static const app_settings_ping_t app_settings_ping_default = { @@ -481,6 +483,12 @@ static sl_status_t app_settings_get_broadcast_channel_mask_str(char *value_str, static sl_status_t app_settings_set_allowed_channels(const char *value_str, const char *key_str, const app_settings_entry_t *entry); +static sl_status_t app_settings_set_neighbor_table_size(const char *value_str, + const char *key_str, + const app_settings_entry_t *entry); +static sl_status_t app_settings_set_trace_filter(const char *value_str, + const char *key_str, + const app_settings_entry_t *entry); static sl_status_t app_settings_set_trace_filter(const char *value_str, const char *key_str, const app_settings_entry_t *entry); @@ -1222,6 +1230,19 @@ const app_settings_entry_t app_settings_entries[] = .get_handler = app_settings_get_rpl_info, .description = "Wi-SUN RPL information" }, + { + .key = "mac_neighbor_table_size", + .domain = app_settings_domain_wisun, + .value_size = APP_SETTINGS_VALUE_SIZE_UINT8, + .input = APP_SETTINGS_INPUT_FLAG_DEFAULT, + .output = APP_SETTINGS_OUTPUT_FLAG_DEFAULT, + .value = &app_settings_wisun.mac_neighbor_table_size, + .input_enum_list = NULL, + .output_enum_list = NULL, + .set_handler = app_settings_set_neighbor_table_size, + .get_handler = app_settings_get_integer, + .description = "Neighbor table size [uint8]" + }, { .key = NULL, .domain = 0, @@ -2781,6 +2802,21 @@ static sl_status_t app_settings_set_allowed_channels(const char *value_str, return ret; } +static sl_status_t app_settings_set_neighbor_table_size(const char *value_str, + const char *key_str, + const app_settings_entry_t *entry) +{ + sl_status_t ret; + + ret = app_settings_set_integer(value_str, key_str, entry); + + if (ret == SL_STATUS_OK) { + ret = sl_wisun_set_neighbor_table_size(app_settings_wisun.mac_neighbor_table_size); + } + + return SL_STATUS_OK; +} + static sl_status_t app_settings_set_trace_filter(const char *value_str, const char *key_str, const app_settings_entry_t *entry) diff --git a/protocol/wisun/app/wisun_soc_cli/app_settings.h b/protocol/wisun/app/wisun_soc_cli/app_settings.h index 660bde1406..0fa6d2ca57 100644 --- a/protocol/wisun/app/wisun_soc_cli/app_settings.h +++ b/protocol/wisun/app/wisun_soc_cli/app_settings.h @@ -72,6 +72,7 @@ typedef struct { uint8_t crc_type; uint8_t preamble_length; uint8_t stf_length; + uint8_t mac_neighbor_table_size; } app_settings_wisun_t; typedef struct { diff --git a/protocol/wisun/component/wisun_rcp_app.slcc b/protocol/wisun/component/wisun_rcp_app.slcc index 9eccd9869d..876cf5945b 100644 --- a/protocol/wisun/component/wisun_rcp_app.slcc +++ b/protocol/wisun/component/wisun_rcp_app.slcc @@ -52,6 +52,8 @@ source: - path: sl_ring.c - path: sl_wsrcp_os_main.c - path: sl_wsrcp_btl_interface.h + - path: sl_wsrcp_btl_interface.c + condition: [bootloader_interface] - path: sl_wsrcp_api.h - path: sl_wsrcp_hif.h diff --git a/protocol/wisun/stack/inc/sl_wisun_api.h b/protocol/wisun/stack/inc/sl_wisun_api.h index 24a30243f3..9a10eb5cc2 100644 --- a/protocol/wisun/stack/inc/sl_wisun_api.h +++ b/protocol/wisun/stack/inc/sl_wisun_api.h @@ -414,6 +414,20 @@ sl_status_t sl_wisun_set_device_private_key_id(uint32_t key_id); *****************************************************************************/ sl_status_t sl_wisun_set_regulation(sl_wisun_regulation_t regulation); +/**************************************************************************//** + * Set neighbor table size. + * + * @param[in] size Size of the neighbor table + * @return SL_STATUS_OK if successful, an error code otherwise + * + * This function sets the limit of regular neighbors supported by the + * node [1, 245], without considering temporary or RPL parents. + * Increasing this parameter means a higher number of potential neighbors + * while lowering it means reduced RAM consumption. + * The default value is 22. + *****************************************************************************/ +sl_status_t sl_wisun_set_neighbor_table_size(uint8_t size); + /**************************************************************************//** * Set the thresholds for transmission duration level event. * diff --git a/protocol/wisun/stack/inc/sl_wisun_events.h b/protocol/wisun/stack/inc/sl_wisun_events.h index b0979ea9e3..cce63dbc2f 100644 --- a/protocol/wisun/stack/inc/sl_wisun_events.h +++ b/protocol/wisun/stack/inc/sl_wisun_events.h @@ -75,7 +75,9 @@ typedef enum { /// This event is sent on LFN Wake Up. SL_WISUN_MSG_LFN_WAKE_UP_IND_ID = 0x90, /// Indicate a multicast group registration finishes - SL_WISUN_MSG_LFN_MULTICAST_REG_IND_ID = 0x91, + SL_WISUN_MSG_LFN_MULTICAST_REG_IND_ID = 0x91, + /// Indicate DHCPv6 Vendor Data + SL_WISUN_MSG_DHCP_VENDOR_DATA_IND_ID = 0x92, } sl_wisun_msg_ind_id_t; /**************************************************************************//** @@ -556,6 +558,35 @@ SL_PACK_END() /** @} (end SL_WISUN_MSG_LFN_MULTICAST_REG_IND) */ +/**************************************************************************//** + * @defgroup SL_WISUN_MSG_DHCP_VENDOR_DATA_IND sl_wisun_msg_dhcp_vendor_data_ind + * @{ + ******************************************************************************/ + +/// Indication message body +SL_PACK_START(1) +typedef struct { + /// Vendor Specific Enterprise Number + uint32_t enterprise_number; + /// Length of Vendor specific data + uint16_t data_length; + /// Vendor specific data + uint8_t data[]; +} SL_ATTRIBUTE_PACKED sl_wisun_msg_dhcp_vendor_data_ind_body_t; +SL_PACK_END() + +/// Indication message +SL_PACK_START(1) +typedef struct { + /// Common message header + sl_wisun_msg_header_t header; + /// Indication message body + sl_wisun_msg_dhcp_vendor_data_ind_body_t body; +} SL_ATTRIBUTE_PACKED sl_wisun_msg_dhcp_vendor_data_ind_t; +SL_PACK_END() + +/** @} (end SL_WISUN_MSG_DHCP_VENDOR_DATA_IND) */ + /// @brief Wi-SUN event definitions /// @details This structure contains a Wi-SUN API event and its associated data. SL_PACK_START(1) @@ -603,6 +634,8 @@ typedef struct { sl_wisun_msg_lfn_wake_up_ind_body_t lfn_wake_up; /// #SL_WISUN_MSG_LFN_MULTICAST_REG_IND_ID event data sl_wisun_msg_lfn_multicast_reg_ind_body_t lfn_multicast_reg; + /// #SL_WISUN_MSG_DHCP_VENDOR_DATA_IND_ID event data + sl_wisun_msg_dhcp_vendor_data_ind_body_t dhcp_vendor_data; } evt; } SL_ATTRIBUTE_PACKED sl_wisun_evt_t; SL_PACK_END() diff --git a/protocol/wisun/stack/inc/sl_wisun_version.h b/protocol/wisun/stack/inc/sl_wisun_version.h index b29480ab27..937d6f2f2d 100644 --- a/protocol/wisun/stack/inc/sl_wisun_version.h +++ b/protocol/wisun/stack/inc/sl_wisun_version.h @@ -36,7 +36,7 @@ #endif #ifndef SL_WISUN_VERSION_MINOR -#define SL_WISUN_VERSION_MINOR 9 +#define SL_WISUN_VERSION_MINOR 10 #endif #ifndef SL_WISUN_VERSION_PATCH diff --git a/protocol/wisun/stack/libwisun_mac_core_efr32xg1x_gcc.a b/protocol/wisun/stack/libwisun_mac_core_efr32xg1x_gcc.a index c7cf5f65b8..89d44cf1a6 100644 --- a/protocol/wisun/stack/libwisun_mac_core_efr32xg1x_gcc.a +++ b/protocol/wisun/stack/libwisun_mac_core_efr32xg1x_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:531ddac1a9821471d281c599cdc0906557b0ce355118724774ea97bc16a25a6b -size 1341470 +oid sha256:44dfbe0d02968a4f17dc5e26b5534dbed68bf768fa5631bc58dc613da52a49e2 +size 1337868 diff --git a/protocol/wisun/stack/libwisun_mac_core_efr32xg1x_iar.a b/protocol/wisun/stack/libwisun_mac_core_efr32xg1x_iar.a index e6156ef5b1..7d0ec2fdb2 100644 --- a/protocol/wisun/stack/libwisun_mac_core_efr32xg1x_iar.a +++ b/protocol/wisun/stack/libwisun_mac_core_efr32xg1x_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cd1d91544915880d39a3b6a27cee7bec91b7966134056b571e557da07f6e45b9 -size 883534 +oid sha256:2f9fa8f6284c49b604b2715381e31fe7c6ed52685c2b8c6c101da42a5a3a80e2 +size 882086 diff --git a/protocol/wisun/stack/libwisun_mac_core_efr32xg2x_gcc.a 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b/protocol/wisun/stack/libwisun_router_core_efr32xg1x_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d14276c15028cd68800090957401ad31ba2ae8f5d264cc466f9b0039ea5fd479 -size 3988194 +oid sha256:829ad00d5354bda6cb330475b21d648ff8eb1582dc6f27c87d4ecc8a30e874a6 +size 3978896 diff --git a/protocol/wisun/stack/libwisun_router_core_efr32xg2x_gcc_debug.a b/protocol/wisun/stack/libwisun_router_core_efr32xg2x_gcc_debug.a index 72e1bf6127..935fdae37a 100644 --- a/protocol/wisun/stack/libwisun_router_core_efr32xg2x_gcc_debug.a +++ b/protocol/wisun/stack/libwisun_router_core_efr32xg2x_gcc_debug.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:36126dd412aee68108941bdda60284104cd6049e900e61fdc65278c94ce50aff -size 8401602 +oid sha256:607272702c5ff7762240d2c4bc784e138086d64c5975c1b883ebe4ef6cbce386 +size 8423034 diff --git a/protocol/wisun/stack/libwisun_router_core_efr32xg2x_gcc_release.a b/protocol/wisun/stack/libwisun_router_core_efr32xg2x_gcc_release.a index 0ea84c4481..adccfb6f57 100644 --- a/protocol/wisun/stack/libwisun_router_core_efr32xg2x_gcc_release.a +++ b/protocol/wisun/stack/libwisun_router_core_efr32xg2x_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:603d83b12c7d275c12dcb571c13f5eec9c4837fa3ce4b8f051cf794ac62a87bf -size 8383772 +oid sha256:05d7fac3f99a24aa8eaed7544b3f5f310ca762899787b2495ab8b2496c6a8fec +size 8405154 diff --git a/protocol/wisun/stack/libwisun_router_core_efr32xg2x_iar_debug.a b/protocol/wisun/stack/libwisun_router_core_efr32xg2x_iar_debug.a index befa916105..16f16d6f9d 100644 --- a/protocol/wisun/stack/libwisun_router_core_efr32xg2x_iar_debug.a +++ b/protocol/wisun/stack/libwisun_router_core_efr32xg2x_iar_debug.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d38d333179dd25b072d29683a7dd0ea8158ce6fe155b1b8adb1005124859659a -size 4031360 +oid sha256:6d31cc1729ee3487f1cb49d55dbc77d8f2864e85902adaedbe8821537b9e633b +size 4022554 diff --git a/protocol/wisun/stack/libwisun_router_core_efr32xg2x_iar_release.a b/protocol/wisun/stack/libwisun_router_core_efr32xg2x_iar_release.a index b7c7086b2e..76ef0ad4cb 100644 --- a/protocol/wisun/stack/libwisun_router_core_efr32xg2x_iar_release.a +++ b/protocol/wisun/stack/libwisun_router_core_efr32xg2x_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c5628e6a666ac9ec8ee58f3999c5b1c0fe70fc1076f82bde9c3794e0919150a0 -size 4023138 +oid sha256:99c77a9b3edbb5e24648898f0c6a2dca9599da68acc78e884f06c0e3cbf28133 +size 4014362 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg1x_gcc_debug.a b/protocol/wisun/stack/libwisun_router_efr32xg1x_gcc_debug.a index 665f68836e..b66e9780ba 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg1x_gcc_debug.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg1x_gcc_debug.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:058f2df44d6c3cf1c44f792fcd56ba3b107ed06e6912cdd1968f05621c3ac115 -size 8805132 +oid sha256:e5309405fb111bb486f892df59f674e2a1cdf00576918f07c5075b43bd9074f9 +size 8827834 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg1x_gcc_release.a b/protocol/wisun/stack/libwisun_router_efr32xg1x_gcc_release.a index 43d3bc5659..aee7af3ed4 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg1x_gcc_release.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg1x_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c6c01af9e47b195409c2bec43899d2ba1734a3f16968291f8aa285e416a34097 -size 8787256 +oid sha256:077b0e1ed9db9c129344bf4aa7b578b82865788763aeae75f13f39096e826c2c +size 8809908 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg1x_iar_debug.a b/protocol/wisun/stack/libwisun_router_efr32xg1x_iar_debug.a index c34a51a860..1231848286 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg1x_iar_debug.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg1x_iar_debug.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f57b5c9c31364f1124039ed15d6eee0a663ee8841639479da370d78fcb2f8fe3 -size 4266082 +oid sha256:2a2f5fc72e35b2d64351d7190eb82ef4ec6b89fed203a53b5ca0a49417e5174b +size 4258114 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg1x_iar_release.a b/protocol/wisun/stack/libwisun_router_efr32xg1x_iar_release.a index 4c722d8eba..da53786143 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg1x_iar_release.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg1x_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e1ed6727b30d03f027d171afa9d56f773d885c51784569b85bf68e5fdbc17864 -size 4257738 +oid sha256:8f98057b292cbc2f858505b2a0db188bd4b09688b546e215a3d49c1d87b0c532 +size 4249802 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg2x_gcc_debug.a b/protocol/wisun/stack/libwisun_router_efr32xg2x_gcc_debug.a index ab01a10f17..6eb94a3fa8 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg2x_gcc_debug.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg2x_gcc_debug.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:eff3e0341643f4428efeaaf46719dd50815ce8adee72d25dc2e6d68bdd223bce -size 8882936 +oid sha256:e3aa070245ca1abecf484ac45c68385e890aa5ee43b5bdeb34891d7d466c76a1 +size 8905508 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg2x_gcc_release.a b/protocol/wisun/stack/libwisun_router_efr32xg2x_gcc_release.a index 8069f665b9..26f9f953b1 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg2x_gcc_release.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg2x_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1ff9c0cc71686e8c28b30dd32b630d4fabe2a561febb2bb436d4fc196890eb41 -size 8865106 +oid sha256:933bb34c8daf2b5174d15e346aea62d60165adc308273223a3e2d44441441c51 +size 8887632 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg2x_iar_debug.a b/protocol/wisun/stack/libwisun_router_efr32xg2x_iar_debug.a index 00829b2860..d89517f716 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg2x_iar_debug.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg2x_iar_debug.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:057b5b0193caed29eca49c9714b68dc76ac389fd3aab3ebdd05dbbda16e117ad -size 4296888 +oid sha256:4dfa9b0da52171d137a30f05e9c9c0944124d29165a527a2cce23bd9a4393643 +size 4287660 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg2x_iar_release.a b/protocol/wisun/stack/libwisun_router_efr32xg2x_iar_release.a index a0180793bf..5e682a6cf4 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg2x_iar_release.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg2x_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2aa22e40e535734521a26143970698e3faed1ce8b5139a608970d2e21caa23a8 -size 4288540 +oid sha256:c2d93bf95d21074fba23ad2d80177d5cd99d385fadd6ff903446668cd2cf7af1 +size 4279336 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_EU_size.txt index 0e97d3f1c9..917f88089b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x34090 0x8006000 -_cmd_handlers 0x2e8 0x803a090 -_zw_protocol_cmd_handlers_lr 0x50 0x803a378 -_zw_protocol_cmd_handlers 0xe8 0x803a3c8 -.ARM.exidx 0x8 0x803a4b0 -.copy.table 0xc 0x803a4b8 -.zero.table 0x0 0x803a4c4 +.text 0x34108 0x8006000 +_cmd_handlers 0x2e8 0x803a108 +_zw_protocol_cmd_handlers_lr 0x50 0x803a3f0 +_zw_protocol_cmd_handlers 0xe8 0x803a440 +.ARM.exidx 0x8 0x803a528 +.copy.table 0xc 0x803a530 +.zero.table 0x0 0x803a53c .stack 0x500 0x20000000 .data 0x534 0x20000500 .bss 0xa6e8 0x20000a34 text_application_ram 0x0 0x2000b11c .heap 0x80 0x2000b120 -.zwave_nvm 0x0 0x803a4c4 -.nvm 0xa000 0x803a4c4 +.zwave_nvm 0x0 0x803a53c +.nvm 0xa000 0x803a53c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x107dc 0x0 -.debug_info 0x29115d 0x0 -.debug_abbrev 0x1ca17 0x0 -.debug_loclists 0x1dedd 0x0 +.debug_info 0x2925b4 0x0 +.debug_abbrev 0x1c9eb 0x0 +.debug_loclists 0x1df8f 0x0 .debug_aranges 0x5ad8 0x0 -.debug_rnglists 0x3b43 0x0 -.debug_line 0x60a67 0x0 -.debug_str 0x8ac63 0x0 -.debug_loc 0x2f047 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x44f3b6 +.debug_rnglists 0x3b56 0x0 +.debug_line 0x60b61 0x0 +.debug_str 0x8ac6c 0x0 +.debug_loc 0x2f131 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x450b73 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 215544 + 215664 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_US_LR_size.txt index 8444dc57f6..ec008f5d68 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x34090 0x8006000 -_cmd_handlers 0x2e8 0x803a090 -_zw_protocol_cmd_handlers_lr 0x50 0x803a378 -_zw_protocol_cmd_handlers 0xe8 0x803a3c8 -.ARM.exidx 0x8 0x803a4b0 -.copy.table 0xc 0x803a4b8 -.zero.table 0x0 0x803a4c4 +.text 0x34108 0x8006000 +_cmd_handlers 0x2e8 0x803a108 +_zw_protocol_cmd_handlers_lr 0x50 0x803a3f0 +_zw_protocol_cmd_handlers 0xe8 0x803a440 +.ARM.exidx 0x8 0x803a528 +.copy.table 0xc 0x803a530 +.zero.table 0x0 0x803a53c .stack 0x500 0x20000000 .data 0x534 0x20000500 .bss 0xa6e8 0x20000a34 text_application_ram 0x0 0x2000b11c .heap 0x80 0x2000b120 -.zwave_nvm 0x0 0x803a4c4 -.nvm 0xa000 0x803a4c4 +.zwave_nvm 0x0 0x803a53c +.nvm 0xa000 0x803a53c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x107dc 0x0 -.debug_info 0x29115d 0x0 -.debug_abbrev 0x1ca17 0x0 -.debug_loclists 0x1dedd 0x0 +.debug_info 0x2925b4 0x0 +.debug_abbrev 0x1c9eb 0x0 +.debug_loclists 0x1df8f 0x0 .debug_aranges 0x5ad8 0x0 -.debug_rnglists 0x3b43 0x0 -.debug_line 0x60a67 0x0 -.debug_str 0x8ac59 0x0 -.debug_loc 0x2f047 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x44f3ac +.debug_rnglists 0x3b56 0x0 +.debug_line 0x60b61 0x0 +.debug_str 0x8ac62 0x0 +.debug_loc 0x2f131 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x450b69 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 215544 + 215664 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_US_size.txt index 0e97d3f1c9..917f88089b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x34090 0x8006000 -_cmd_handlers 0x2e8 0x803a090 -_zw_protocol_cmd_handlers_lr 0x50 0x803a378 -_zw_protocol_cmd_handlers 0xe8 0x803a3c8 -.ARM.exidx 0x8 0x803a4b0 -.copy.table 0xc 0x803a4b8 -.zero.table 0x0 0x803a4c4 +.text 0x34108 0x8006000 +_cmd_handlers 0x2e8 0x803a108 +_zw_protocol_cmd_handlers_lr 0x50 0x803a3f0 +_zw_protocol_cmd_handlers 0xe8 0x803a440 +.ARM.exidx 0x8 0x803a528 +.copy.table 0xc 0x803a530 +.zero.table 0x0 0x803a53c .stack 0x500 0x20000000 .data 0x534 0x20000500 .bss 0xa6e8 0x20000a34 text_application_ram 0x0 0x2000b11c .heap 0x80 0x2000b120 -.zwave_nvm 0x0 0x803a4c4 -.nvm 0xa000 0x803a4c4 +.zwave_nvm 0x0 0x803a53c +.nvm 0xa000 0x803a53c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x107dc 0x0 -.debug_info 0x29115d 0x0 -.debug_abbrev 0x1ca17 0x0 -.debug_loclists 0x1dedd 0x0 +.debug_info 0x2925b4 0x0 +.debug_abbrev 0x1c9eb 0x0 +.debug_loclists 0x1df8f 0x0 .debug_aranges 0x5ad8 0x0 -.debug_rnglists 0x3b43 0x0 -.debug_line 0x60a67 0x0 -.debug_str 0x8ac63 0x0 -.debug_loc 0x2f047 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x44f3b6 +.debug_rnglists 0x3b56 0x0 +.debug_line 0x60b61 0x0 +.debug_str 0x8ac6c 0x0 +.debug_loc 0x2f131 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x450b73 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 215544 + 215664 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2705A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2705A_REGION_EU_size.txt index 044dac768e..df1fd81afd 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2705A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2705A_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x34538 0x8006000 -_cmd_handlers 0x2e8 0x803a538 -_zw_protocol_cmd_handlers_lr 0x50 0x803a820 -_zw_protocol_cmd_handlers 0xe8 0x803a870 -.ARM.exidx 0x8 0x803a958 -.copy.table 0xc 0x803a960 -.zero.table 0x0 0x803a96c +.text 0x345b0 0x8006000 +_cmd_handlers 0x2e8 0x803a5b0 +_zw_protocol_cmd_handlers_lr 0x50 0x803a898 +_zw_protocol_cmd_handlers 0xe8 0x803a8e8 +.ARM.exidx 0x8 0x803a9d0 +.copy.table 0xc 0x803a9d8 +.zero.table 0x0 0x803a9e4 .stack 0x500 0x20000000 .data 0x52c 0x20000500 .bss 0xa650 0x20000a2c text_application_ram 0x0 0x2000b07c .heap 0x80 0x2000b080 -.zwave_nvm 0x0 0x803a96c -.nvm 0xa000 0x803a96c +.zwave_nvm 0x0 0x803a9e4 +.nvm 0xa000 0x803a9e4 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x107ac 0x0 -.debug_info 0x291aeb 0x0 -.debug_abbrev 0x1c784 0x0 -.debug_loclists 0x1e15c 0x0 +.debug_info 0x292f46 0x0 +.debug_abbrev 0x1c758 0x0 +.debug_loclists 0x1e20e 0x0 .debug_aranges 0x5ab0 0x0 -.debug_rnglists 0x3b07 0x0 -.debug_line 0x6051a 0x0 -.debug_str 0x8bc12 0x0 -.debug_loc 0x2ef43 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x450a02 +.debug_rnglists 0x3b1a 0x0 +.debug_line 0x6061c 0x0 +.debug_str 0x8bc1b 0x0 +.debug_loc 0x2f02d 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x4521cb The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 216728 + 216848 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2705A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2705A_REGION_US_LR_size.txt index 3a86ab9621..c9475e5afc 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2705A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2705A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x34538 0x8006000 -_cmd_handlers 0x2e8 0x803a538 -_zw_protocol_cmd_handlers_lr 0x50 0x803a820 -_zw_protocol_cmd_handlers 0xe8 0x803a870 -.ARM.exidx 0x8 0x803a958 -.copy.table 0xc 0x803a960 -.zero.table 0x0 0x803a96c +.text 0x345b0 0x8006000 +_cmd_handlers 0x2e8 0x803a5b0 +_zw_protocol_cmd_handlers_lr 0x50 0x803a898 +_zw_protocol_cmd_handlers 0xe8 0x803a8e8 +.ARM.exidx 0x8 0x803a9d0 +.copy.table 0xc 0x803a9d8 +.zero.table 0x0 0x803a9e4 .stack 0x500 0x20000000 .data 0x52c 0x20000500 .bss 0xa650 0x20000a2c text_application_ram 0x0 0x2000b07c .heap 0x80 0x2000b080 -.zwave_nvm 0x0 0x803a96c -.nvm 0xa000 0x803a96c +.zwave_nvm 0x0 0x803a9e4 +.nvm 0xa000 0x803a9e4 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x107ac 0x0 -.debug_info 0x291aeb 0x0 -.debug_abbrev 0x1c784 0x0 -.debug_loclists 0x1e15c 0x0 +.debug_info 0x292f46 0x0 +.debug_abbrev 0x1c758 0x0 +.debug_loclists 0x1e20e 0x0 .debug_aranges 0x5ab0 0x0 -.debug_rnglists 0x3b07 0x0 -.debug_line 0x6051a 0x0 -.debug_str 0x8bc08 0x0 -.debug_loc 0x2ef43 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x4509f8 +.debug_rnglists 0x3b1a 0x0 +.debug_line 0x6061c 0x0 +.debug_str 0x8bc11 0x0 +.debug_loc 0x2f02d 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x4521c1 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 216728 + 216848 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2705A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2705A_REGION_US_size.txt index 044dac768e..df1fd81afd 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2705A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2705A_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x34538 0x8006000 -_cmd_handlers 0x2e8 0x803a538 -_zw_protocol_cmd_handlers_lr 0x50 0x803a820 -_zw_protocol_cmd_handlers 0xe8 0x803a870 -.ARM.exidx 0x8 0x803a958 -.copy.table 0xc 0x803a960 -.zero.table 0x0 0x803a96c +.text 0x345b0 0x8006000 +_cmd_handlers 0x2e8 0x803a5b0 +_zw_protocol_cmd_handlers_lr 0x50 0x803a898 +_zw_protocol_cmd_handlers 0xe8 0x803a8e8 +.ARM.exidx 0x8 0x803a9d0 +.copy.table 0xc 0x803a9d8 +.zero.table 0x0 0x803a9e4 .stack 0x500 0x20000000 .data 0x52c 0x20000500 .bss 0xa650 0x20000a2c text_application_ram 0x0 0x2000b07c .heap 0x80 0x2000b080 -.zwave_nvm 0x0 0x803a96c -.nvm 0xa000 0x803a96c +.zwave_nvm 0x0 0x803a9e4 +.nvm 0xa000 0x803a9e4 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x107ac 0x0 -.debug_info 0x291aeb 0x0 -.debug_abbrev 0x1c784 0x0 -.debug_loclists 0x1e15c 0x0 +.debug_info 0x292f46 0x0 +.debug_abbrev 0x1c758 0x0 +.debug_loclists 0x1e20e 0x0 .debug_aranges 0x5ab0 0x0 -.debug_rnglists 0x3b07 0x0 -.debug_line 0x6051a 0x0 -.debug_str 0x8bc12 0x0 -.debug_loc 0x2ef43 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x450a02 +.debug_rnglists 0x3b1a 0x0 +.debug_line 0x6061c 0x0 +.debug_str 0x8bc1b 0x0 +.debug_loc 0x2f02d 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x4521cb The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 216728 + 216848 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_EU_size.txt index cdc6391209..d2fe41adb7 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2fa2c 0x0 -_cmd_handlers 0x2e8 0x2fa2c -_zw_protocol_cmd_handlers_lr 0x50 0x2fd14 -_zw_protocol_cmd_handlers 0xe8 0x2fd64 -.ARM.exidx 0x8 0x2fe4c -.copy.table 0xc 0x2fe54 -.zero.table 0x0 0x2fe60 +.text 0x2faac 0x0 +_cmd_handlers 0x2e8 0x2faac +_zw_protocol_cmd_handlers_lr 0x50 0x2fd94 +_zw_protocol_cmd_handlers 0xe8 0x2fde4 +.ARM.exidx 0x8 0x2fecc +.copy.table 0xc 0x2fed4 +.zero.table 0x0 0x2fee0 .stack 0x500 0x20000000 .data 0x3a0 0x20000500 .bss 0x7664 0x200008a0 text_application_ram 0x0 0x20007f04 .heap 0x80 0x20007f08 -.zwave_nvm 0x3000 0x2fe60 -.nvm 0x9000 0x32e60 +.zwave_nvm 0x3000 0x2fee0 +.nvm 0x9000 0x32ee0 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x28a 0x0 -.debug_frame 0xe908 0x0 -.debug_info 0x255bcc 0x0 -.debug_abbrev 0x19d99 0x0 -.debug_loclists 0x13891 0x0 -.debug_aranges 0x50a0 0x0 -.debug_rnglists 0x2b43 0x0 -.debug_line 0x55957 0x0 -.debug_str 0x80d51 0x0 -.debug_loc 0x30552 0x0 -.debug_ranges 0x5db8 0x0 -Total 0x3ea174 +.debug_frame 0xe8e8 0x0 +.debug_info 0x255add 0x0 +.debug_abbrev 0x19d98 0x0 +.debug_loclists 0x138bf 0x0 +.debug_aranges 0x5098 0x0 +.debug_rnglists 0x2b53 0x0 +.debug_line 0x559b6 0x0 +.debug_str 0x80d39 0x0 +.debug_loc 0x3063c 0x0 +.debug_ranges 0x5e00 0x0 +Total 0x3ea293 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197120 + 197248 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_US_LR_size.txt index 6064482fac..5ef565816a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2fa2c 0x0 -_cmd_handlers 0x2e8 0x2fa2c -_zw_protocol_cmd_handlers_lr 0x50 0x2fd14 -_zw_protocol_cmd_handlers 0xe8 0x2fd64 -.ARM.exidx 0x8 0x2fe4c -.copy.table 0xc 0x2fe54 -.zero.table 0x0 0x2fe60 +.text 0x2faac 0x0 +_cmd_handlers 0x2e8 0x2faac +_zw_protocol_cmd_handlers_lr 0x50 0x2fd94 +_zw_protocol_cmd_handlers 0xe8 0x2fde4 +.ARM.exidx 0x8 0x2fecc +.copy.table 0xc 0x2fed4 +.zero.table 0x0 0x2fee0 .stack 0x500 0x20000000 .data 0x3a0 0x20000500 .bss 0x7664 0x200008a0 text_application_ram 0x0 0x20007f04 .heap 0x80 0x20007f08 -.zwave_nvm 0x3000 0x2fe60 -.nvm 0x9000 0x32e60 +.zwave_nvm 0x3000 0x2fee0 +.nvm 0x9000 0x32ee0 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x28a 0x0 -.debug_frame 0xe908 0x0 -.debug_info 0x255bcc 0x0 -.debug_abbrev 0x19d99 0x0 -.debug_loclists 0x13891 0x0 -.debug_aranges 0x50a0 0x0 -.debug_rnglists 0x2b43 0x0 -.debug_line 0x55957 0x0 -.debug_str 0x80d47 0x0 -.debug_loc 0x30552 0x0 -.debug_ranges 0x5db8 0x0 -Total 0x3ea16a +.debug_frame 0xe8e8 0x0 +.debug_info 0x255add 0x0 +.debug_abbrev 0x19d98 0x0 +.debug_loclists 0x138bf 0x0 +.debug_aranges 0x5098 0x0 +.debug_rnglists 0x2b53 0x0 +.debug_line 0x559b6 0x0 +.debug_str 0x80d2f 0x0 +.debug_loc 0x3063c 0x0 +.debug_ranges 0x5e00 0x0 +Total 0x3ea289 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197120 + 197248 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_US_size.txt index cdc6391209..d2fe41adb7 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2fa2c 0x0 -_cmd_handlers 0x2e8 0x2fa2c -_zw_protocol_cmd_handlers_lr 0x50 0x2fd14 -_zw_protocol_cmd_handlers 0xe8 0x2fd64 -.ARM.exidx 0x8 0x2fe4c -.copy.table 0xc 0x2fe54 -.zero.table 0x0 0x2fe60 +.text 0x2faac 0x0 +_cmd_handlers 0x2e8 0x2faac +_zw_protocol_cmd_handlers_lr 0x50 0x2fd94 +_zw_protocol_cmd_handlers 0xe8 0x2fde4 +.ARM.exidx 0x8 0x2fecc +.copy.table 0xc 0x2fed4 +.zero.table 0x0 0x2fee0 .stack 0x500 0x20000000 .data 0x3a0 0x20000500 .bss 0x7664 0x200008a0 text_application_ram 0x0 0x20007f04 .heap 0x80 0x20007f08 -.zwave_nvm 0x3000 0x2fe60 -.nvm 0x9000 0x32e60 +.zwave_nvm 0x3000 0x2fee0 +.nvm 0x9000 0x32ee0 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x28a 0x0 -.debug_frame 0xe908 0x0 -.debug_info 0x255bcc 0x0 -.debug_abbrev 0x19d99 0x0 -.debug_loclists 0x13891 0x0 -.debug_aranges 0x50a0 0x0 -.debug_rnglists 0x2b43 0x0 -.debug_line 0x55957 0x0 -.debug_str 0x80d51 0x0 -.debug_loc 0x30552 0x0 -.debug_ranges 0x5db8 0x0 -Total 0x3ea174 +.debug_frame 0xe8e8 0x0 +.debug_info 0x255add 0x0 +.debug_abbrev 0x19d98 0x0 +.debug_loclists 0x138bf 0x0 +.debug_aranges 0x5098 0x0 +.debug_rnglists 0x2b53 0x0 +.debug_line 0x559b6 0x0 +.debug_str 0x80d39 0x0 +.debug_loc 0x3063c 0x0 +.debug_ranges 0x5e00 0x0 +Total 0x3ea293 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197120 + 197248 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_EU_size.txt index 59f660f6f9..372c30d61e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x30338 0x0 -_cmd_handlers 0x2e8 0x30338 -_zw_protocol_cmd_handlers_lr 0x50 0x30620 -_zw_protocol_cmd_handlers 0xe8 0x30670 -.ARM.exidx 0x8 0x30758 -.copy.table 0xc 0x30760 -.zero.table 0x0 0x3076c +.text 0x303ac 0x0 +_cmd_handlers 0x2e8 0x303ac +_zw_protocol_cmd_handlers_lr 0x50 0x30694 +_zw_protocol_cmd_handlers 0xe8 0x306e4 +.ARM.exidx 0x8 0x307cc +.copy.table 0xc 0x307d4 +.zero.table 0x0 0x307e0 .stack 0x500 0x20000000 .data 0x3a0 0x20000500 .bss 0x9b20 0x200008a0 text_application_ram 0x0 0x2000a3c0 .heap 0x80 0x2000a3c0 -.zwave_nvm 0x3000 0x3076c -.nvm 0x9000 0x3376c +.zwave_nvm 0x3000 0x307e0 +.nvm 0x9000 0x337e0 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x28a 0x0 -.debug_frame 0xe9a8 0x0 -.debug_info 0x2578ce 0x0 -.debug_abbrev 0x19ebb 0x0 -.debug_loclists 0x13b4c 0x0 -.debug_aranges 0x5118 0x0 -.debug_rnglists 0x2bb5 0x0 -.debug_line 0x55d38 0x0 -.debug_str 0x81807 0x0 -.debug_loc 0x30551 0x0 -.debug_ranges 0x5db8 0x0 -Total 0x3f003b +.debug_frame 0xe988 0x0 +.debug_info 0x2577ed 0x0 +.debug_abbrev 0x19eba 0x0 +.debug_loclists 0x13b7a 0x0 +.debug_aranges 0x5110 0x0 +.debug_rnglists 0x2bc5 0x0 +.debug_line 0x55d8d 0x0 +.debug_str 0x817ef 0x0 +.debug_loc 0x3063b 0x0 +.debug_ranges 0x5e00 0x0 +Total 0x3f0152 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 199436 + 199552 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_US_LR_size.txt index 10f04767c1..2a67ad88eb 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x30338 0x0 -_cmd_handlers 0x2e8 0x30338 -_zw_protocol_cmd_handlers_lr 0x50 0x30620 -_zw_protocol_cmd_handlers 0xe8 0x30670 -.ARM.exidx 0x8 0x30758 -.copy.table 0xc 0x30760 -.zero.table 0x0 0x3076c +.text 0x303ac 0x0 +_cmd_handlers 0x2e8 0x303ac +_zw_protocol_cmd_handlers_lr 0x50 0x30694 +_zw_protocol_cmd_handlers 0xe8 0x306e4 +.ARM.exidx 0x8 0x307cc +.copy.table 0xc 0x307d4 +.zero.table 0x0 0x307e0 .stack 0x500 0x20000000 .data 0x3a0 0x20000500 .bss 0x9b20 0x200008a0 text_application_ram 0x0 0x2000a3c0 .heap 0x80 0x2000a3c0 -.zwave_nvm 0x3000 0x3076c -.nvm 0x9000 0x3376c +.zwave_nvm 0x3000 0x307e0 +.nvm 0x9000 0x337e0 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x28a 0x0 -.debug_frame 0xe9a8 0x0 -.debug_info 0x2578ce 0x0 -.debug_abbrev 0x19ebb 0x0 -.debug_loclists 0x13b4c 0x0 -.debug_aranges 0x5118 0x0 -.debug_rnglists 0x2bb5 0x0 -.debug_line 0x55d38 0x0 -.debug_str 0x817fd 0x0 -.debug_loc 0x30551 0x0 -.debug_ranges 0x5db8 0x0 -Total 0x3f0031 +.debug_frame 0xe988 0x0 +.debug_info 0x2577ed 0x0 +.debug_abbrev 0x19eba 0x0 +.debug_loclists 0x13b7a 0x0 +.debug_aranges 0x5110 0x0 +.debug_rnglists 0x2bc5 0x0 +.debug_line 0x55d8d 0x0 +.debug_str 0x817e5 0x0 +.debug_loc 0x3063b 0x0 +.debug_ranges 0x5e00 0x0 +Total 0x3f0148 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 199436 + 199552 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_US_size.txt index 59f660f6f9..372c30d61e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x30338 0x0 -_cmd_handlers 0x2e8 0x30338 -_zw_protocol_cmd_handlers_lr 0x50 0x30620 -_zw_protocol_cmd_handlers 0xe8 0x30670 -.ARM.exidx 0x8 0x30758 -.copy.table 0xc 0x30760 -.zero.table 0x0 0x3076c +.text 0x303ac 0x0 +_cmd_handlers 0x2e8 0x303ac +_zw_protocol_cmd_handlers_lr 0x50 0x30694 +_zw_protocol_cmd_handlers 0xe8 0x306e4 +.ARM.exidx 0x8 0x307cc +.copy.table 0xc 0x307d4 +.zero.table 0x0 0x307e0 .stack 0x500 0x20000000 .data 0x3a0 0x20000500 .bss 0x9b20 0x200008a0 text_application_ram 0x0 0x2000a3c0 .heap 0x80 0x2000a3c0 -.zwave_nvm 0x3000 0x3076c -.nvm 0x9000 0x3376c +.zwave_nvm 0x3000 0x307e0 +.nvm 0x9000 0x337e0 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x28a 0x0 -.debug_frame 0xe9a8 0x0 -.debug_info 0x2578ce 0x0 -.debug_abbrev 0x19ebb 0x0 -.debug_loclists 0x13b4c 0x0 -.debug_aranges 0x5118 0x0 -.debug_rnglists 0x2bb5 0x0 -.debug_line 0x55d38 0x0 -.debug_str 0x81807 0x0 -.debug_loc 0x30551 0x0 -.debug_ranges 0x5db8 0x0 -Total 0x3f003b +.debug_frame 0xe988 0x0 +.debug_info 0x2577ed 0x0 +.debug_abbrev 0x19eba 0x0 +.debug_loclists 0x13b7a 0x0 +.debug_aranges 0x5110 0x0 +.debug_rnglists 0x2bc5 0x0 +.debug_line 0x55d8d 0x0 +.debug_str 0x817ef 0x0 +.debug_loc 0x3063b 0x0 +.debug_ranges 0x5e00 0x0 +Total 0x3f0152 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 199436 + 199552 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_EU_size.txt index 7ed163ca4b..6cbf91b5e3 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x33c98 0x8006000 -_cmd_handlers 0x2e8 0x8039c98 -_zw_protocol_cmd_handlers_lr 0x50 0x8039f80 -_zw_protocol_cmd_handlers 0xe8 0x8039fd0 -.ARM.exidx 0x8 0x803a0b8 -.copy.table 0xc 0x803a0c0 -.zero.table 0x0 0x803a0cc +.text 0x33d10 0x8006000 +_cmd_handlers 0x2e8 0x8039d10 +_zw_protocol_cmd_handlers_lr 0x50 0x8039ff8 +_zw_protocol_cmd_handlers 0xe8 0x803a048 +.ARM.exidx 0x8 0x803a130 +.copy.table 0xc 0x803a138 +.zero.table 0x0 0x803a144 .stack 0x500 0x20000000 .data 0x530 0x20000500 .bss 0xa6e0 0x20000a30 text_application_ram 0x0 0x2000b110 .heap 0x80 0x2000b110 -.zwave_nvm 0x0 0x803a0cc -.nvm 0xa000 0x803a0cc +.zwave_nvm 0x0 0x803a144 +.nvm 0xa000 0x803a144 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x10860 0x0 -.debug_info 0x292963 0x0 -.debug_abbrev 0x1cbe4 0x0 -.debug_loclists 0x1e16a 0x0 +.debug_info 0x293dba 0x0 +.debug_abbrev 0x1cbb8 0x0 +.debug_loclists 0x1e21c 0x0 .debug_aranges 0x5ac8 0x0 -.debug_rnglists 0x3b74 0x0 -.debug_line 0x6115e 0x0 -.debug_str 0x8a6f1 0x0 -.debug_loc 0x2f056 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x450e4b +.debug_rnglists 0x3b87 0x0 +.debug_line 0x61260 0x0 +.debug_str 0x8a6fa 0x0 +.debug_loc 0x2f140 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x452610 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214524 + 214644 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_US_LR_size.txt index 9e83955aa3..b08bcb3921 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x33c98 0x8006000 -_cmd_handlers 0x2e8 0x8039c98 -_zw_protocol_cmd_handlers_lr 0x50 0x8039f80 -_zw_protocol_cmd_handlers 0xe8 0x8039fd0 -.ARM.exidx 0x8 0x803a0b8 -.copy.table 0xc 0x803a0c0 -.zero.table 0x0 0x803a0cc +.text 0x33d10 0x8006000 +_cmd_handlers 0x2e8 0x8039d10 +_zw_protocol_cmd_handlers_lr 0x50 0x8039ff8 +_zw_protocol_cmd_handlers 0xe8 0x803a048 +.ARM.exidx 0x8 0x803a130 +.copy.table 0xc 0x803a138 +.zero.table 0x0 0x803a144 .stack 0x500 0x20000000 .data 0x530 0x20000500 .bss 0xa6e0 0x20000a30 text_application_ram 0x0 0x2000b110 .heap 0x80 0x2000b110 -.zwave_nvm 0x0 0x803a0cc -.nvm 0xa000 0x803a0cc +.zwave_nvm 0x0 0x803a144 +.nvm 0xa000 0x803a144 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x10860 0x0 -.debug_info 0x292963 0x0 -.debug_abbrev 0x1cbe4 0x0 -.debug_loclists 0x1e16a 0x0 +.debug_info 0x293dba 0x0 +.debug_abbrev 0x1cbb8 0x0 +.debug_loclists 0x1e21c 0x0 .debug_aranges 0x5ac8 0x0 -.debug_rnglists 0x3b74 0x0 -.debug_line 0x6115e 0x0 -.debug_str 0x8a6e7 0x0 -.debug_loc 0x2f056 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x450e41 +.debug_rnglists 0x3b87 0x0 +.debug_line 0x61260 0x0 +.debug_str 0x8a6f0 0x0 +.debug_loc 0x2f140 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x452606 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214524 + 214644 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_US_size.txt index 7ed163ca4b..6cbf91b5e3 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x33c98 0x8006000 -_cmd_handlers 0x2e8 0x8039c98 -_zw_protocol_cmd_handlers_lr 0x50 0x8039f80 -_zw_protocol_cmd_handlers 0xe8 0x8039fd0 -.ARM.exidx 0x8 0x803a0b8 -.copy.table 0xc 0x803a0c0 -.zero.table 0x0 0x803a0cc +.text 0x33d10 0x8006000 +_cmd_handlers 0x2e8 0x8039d10 +_zw_protocol_cmd_handlers_lr 0x50 0x8039ff8 +_zw_protocol_cmd_handlers 0xe8 0x803a048 +.ARM.exidx 0x8 0x803a130 +.copy.table 0xc 0x803a138 +.zero.table 0x0 0x803a144 .stack 0x500 0x20000000 .data 0x530 0x20000500 .bss 0xa6e0 0x20000a30 text_application_ram 0x0 0x2000b110 .heap 0x80 0x2000b110 -.zwave_nvm 0x0 0x803a0cc -.nvm 0xa000 0x803a0cc +.zwave_nvm 0x0 0x803a144 +.nvm 0xa000 0x803a144 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x10860 0x0 -.debug_info 0x292963 0x0 -.debug_abbrev 0x1cbe4 0x0 -.debug_loclists 0x1e16a 0x0 +.debug_info 0x293dba 0x0 +.debug_abbrev 0x1cbb8 0x0 +.debug_loclists 0x1e21c 0x0 .debug_aranges 0x5ac8 0x0 -.debug_rnglists 0x3b74 0x0 -.debug_line 0x6115e 0x0 -.debug_str 0x8a6f1 0x0 -.debug_loc 0x2f056 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x450e4b +.debug_rnglists 0x3b87 0x0 +.debug_line 0x61260 0x0 +.debug_str 0x8a6fa 0x0 +.debug_loc 0x2f140 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x452610 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214524 + 214644 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_EU_size.txt index cc74cba57a..3db82fdae9 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x33d4c 0x8006000 -_cmd_handlers 0x2e8 0x8039d4c -_zw_protocol_cmd_handlers_lr 0x50 0x803a034 -_zw_protocol_cmd_handlers 0xe8 0x803a084 -.ARM.exidx 0x8 0x803a16c -.copy.table 0xc 0x803a174 -.zero.table 0x0 0x803a180 +.text 0x33de4 0x8006000 +_cmd_handlers 0x2e8 0x8039de4 +_zw_protocol_cmd_handlers_lr 0x50 0x803a0cc +_zw_protocol_cmd_handlers 0xe8 0x803a11c +.ARM.exidx 0x8 0x803a204 +.copy.table 0xc 0x803a20c +.zero.table 0x0 0x803a218 .stack 0x500 0x20000000 .data 0x530 0x20000500 .bss 0xa6e0 0x20000a30 text_application_ram 0x0 0x2000b110 .heap 0x80 0x2000b110 -.zwave_nvm 0x0 0x803a180 -.nvm 0xa000 0x803a180 +.zwave_nvm 0x0 0x803a218 +.nvm 0xa000 0x803a218 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x10890 0x0 -.debug_info 0x292bdb 0x0 -.debug_abbrev 0x1cce6 0x0 -.debug_loclists 0x1e16a 0x0 +.debug_info 0x294032 0x0 +.debug_abbrev 0x1ccba 0x0 +.debug_loclists 0x1e21c 0x0 .debug_aranges 0x5ae8 0x0 -.debug_rnglists 0x3b87 0x0 -.debug_line 0x61337 0x0 -.debug_str 0x8a8c4 0x0 -.debug_loc 0x2f056 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x451688 +.debug_rnglists 0x3b9a 0x0 +.debug_line 0x61439 0x0 +.debug_str 0x8a8cd 0x0 +.debug_loc 0x2f140 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x452e6d The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214704 + 214856 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_US_LR_size.txt index 18d6bf0f0c..364aab5b46 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x33d4c 0x8006000 -_cmd_handlers 0x2e8 0x8039d4c -_zw_protocol_cmd_handlers_lr 0x50 0x803a034 -_zw_protocol_cmd_handlers 0xe8 0x803a084 -.ARM.exidx 0x8 0x803a16c -.copy.table 0xc 0x803a174 -.zero.table 0x0 0x803a180 +.text 0x33de4 0x8006000 +_cmd_handlers 0x2e8 0x8039de4 +_zw_protocol_cmd_handlers_lr 0x50 0x803a0cc +_zw_protocol_cmd_handlers 0xe8 0x803a11c +.ARM.exidx 0x8 0x803a204 +.copy.table 0xc 0x803a20c +.zero.table 0x0 0x803a218 .stack 0x500 0x20000000 .data 0x530 0x20000500 .bss 0xa6e0 0x20000a30 text_application_ram 0x0 0x2000b110 .heap 0x80 0x2000b110 -.zwave_nvm 0x0 0x803a180 -.nvm 0xa000 0x803a180 +.zwave_nvm 0x0 0x803a218 +.nvm 0xa000 0x803a218 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x10890 0x0 -.debug_info 0x292bdb 0x0 -.debug_abbrev 0x1cce6 0x0 -.debug_loclists 0x1e16a 0x0 +.debug_info 0x294032 0x0 +.debug_abbrev 0x1ccba 0x0 +.debug_loclists 0x1e21c 0x0 .debug_aranges 0x5ae8 0x0 -.debug_rnglists 0x3b87 0x0 -.debug_line 0x61337 0x0 -.debug_str 0x8a8ba 0x0 -.debug_loc 0x2f056 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x45167e +.debug_rnglists 0x3b9a 0x0 +.debug_line 0x61439 0x0 +.debug_str 0x8a8c3 0x0 +.debug_loc 0x2f140 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x452e63 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214704 + 214856 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_US_size.txt index cc74cba57a..3db82fdae9 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x33d4c 0x8006000 -_cmd_handlers 0x2e8 0x8039d4c -_zw_protocol_cmd_handlers_lr 0x50 0x803a034 -_zw_protocol_cmd_handlers 0xe8 0x803a084 -.ARM.exidx 0x8 0x803a16c -.copy.table 0xc 0x803a174 -.zero.table 0x0 0x803a180 +.text 0x33de4 0x8006000 +_cmd_handlers 0x2e8 0x8039de4 +_zw_protocol_cmd_handlers_lr 0x50 0x803a0cc +_zw_protocol_cmd_handlers 0xe8 0x803a11c +.ARM.exidx 0x8 0x803a204 +.copy.table 0xc 0x803a20c +.zero.table 0x0 0x803a218 .stack 0x500 0x20000000 .data 0x530 0x20000500 .bss 0xa6e0 0x20000a30 text_application_ram 0x0 0x2000b110 .heap 0x80 0x2000b110 -.zwave_nvm 0x0 0x803a180 -.nvm 0xa000 0x803a180 +.zwave_nvm 0x0 0x803a218 +.nvm 0xa000 0x803a218 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x10890 0x0 -.debug_info 0x292bdb 0x0 -.debug_abbrev 0x1cce6 0x0 -.debug_loclists 0x1e16a 0x0 +.debug_info 0x294032 0x0 +.debug_abbrev 0x1ccba 0x0 +.debug_loclists 0x1e21c 0x0 .debug_aranges 0x5ae8 0x0 -.debug_rnglists 0x3b87 0x0 -.debug_line 0x61337 0x0 -.debug_str 0x8a8c4 0x0 -.debug_loc 0x2f056 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x451688 +.debug_rnglists 0x3b9a 0x0 +.debug_line 0x61439 0x0 +.debug_str 0x8a8cd 0x0 +.debug_loc 0x2f140 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x452e6d The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214704 + 214856 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_EU_size.txt index 0a9cac7eec..bf2d533b61 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x34060 0x8006000 -_cmd_handlers 0x2e8 0x803a060 -_zw_protocol_cmd_handlers_lr 0x50 0x803a348 -_zw_protocol_cmd_handlers 0xe8 0x803a398 -.ARM.exidx 0x8 0x803a480 -.copy.table 0xc 0x803a488 -.zero.table 0x0 0x803a494 +.text 0x340d8 0x8006000 +_cmd_handlers 0x2e8 0x803a0d8 +_zw_protocol_cmd_handlers_lr 0x50 0x803a3c0 +_zw_protocol_cmd_handlers 0xe8 0x803a410 +.ARM.exidx 0x8 0x803a4f8 +.copy.table 0xc 0x803a500 +.zero.table 0x0 0x803a50c .stack 0x500 0x20000000 .data 0x530 0x20000500 .bss 0xa52c 0x20000a30 text_application_ram 0x0 0x2000af5c .heap 0x80 0x2000af60 -.zwave_nvm 0x0 0x803a494 -.nvm 0xa000 0x803a494 +.zwave_nvm 0x0 0x803a50c +.nvm 0xa000 0x803a50c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x10850 0x0 -.debug_info 0x292693 0x0 -.debug_abbrev 0x1cd79 0x0 -.debug_loclists 0x1d1f6 0x0 +.debug_info 0x293aea 0x0 +.debug_abbrev 0x1cd4d 0x0 +.debug_loclists 0x1d2a8 0x0 .debug_aranges 0x5b20 0x0 -.debug_rnglists 0x3b0d 0x0 -.debug_line 0x60e5b 0x0 -.debug_str 0x8a982 0x0 -.debug_loc 0x2f047 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x44ff10 +.debug_rnglists 0x3b20 0x0 +.debug_line 0x60f53 0x0 +.debug_str 0x8a98b 0x0 +.debug_loc 0x2f131 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x4516cb The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 215492 + 215612 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_US_LR_size.txt index a834bd6e65..34c4819d4c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x34060 0x8006000 -_cmd_handlers 0x2e8 0x803a060 -_zw_protocol_cmd_handlers_lr 0x50 0x803a348 -_zw_protocol_cmd_handlers 0xe8 0x803a398 -.ARM.exidx 0x8 0x803a480 -.copy.table 0xc 0x803a488 -.zero.table 0x0 0x803a494 +.text 0x340d8 0x8006000 +_cmd_handlers 0x2e8 0x803a0d8 +_zw_protocol_cmd_handlers_lr 0x50 0x803a3c0 +_zw_protocol_cmd_handlers 0xe8 0x803a410 +.ARM.exidx 0x8 0x803a4f8 +.copy.table 0xc 0x803a500 +.zero.table 0x0 0x803a50c .stack 0x500 0x20000000 .data 0x530 0x20000500 .bss 0xa52c 0x20000a30 text_application_ram 0x0 0x2000af5c .heap 0x80 0x2000af60 -.zwave_nvm 0x0 0x803a494 -.nvm 0xa000 0x803a494 +.zwave_nvm 0x0 0x803a50c +.nvm 0xa000 0x803a50c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x10850 0x0 -.debug_info 0x292693 0x0 -.debug_abbrev 0x1cd79 0x0 -.debug_loclists 0x1d1f6 0x0 +.debug_info 0x293aea 0x0 +.debug_abbrev 0x1cd4d 0x0 +.debug_loclists 0x1d2a8 0x0 .debug_aranges 0x5b20 0x0 -.debug_rnglists 0x3b0d 0x0 -.debug_line 0x60e5b 0x0 -.debug_str 0x8a978 0x0 -.debug_loc 0x2f047 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x44ff06 +.debug_rnglists 0x3b20 0x0 +.debug_line 0x60f53 0x0 +.debug_str 0x8a981 0x0 +.debug_loc 0x2f131 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x4516c1 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 215492 + 215612 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_US_size.txt index 0a9cac7eec..bf2d533b61 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x34060 0x8006000 -_cmd_handlers 0x2e8 0x803a060 -_zw_protocol_cmd_handlers_lr 0x50 0x803a348 -_zw_protocol_cmd_handlers 0xe8 0x803a398 -.ARM.exidx 0x8 0x803a480 -.copy.table 0xc 0x803a488 -.zero.table 0x0 0x803a494 +.text 0x340d8 0x8006000 +_cmd_handlers 0x2e8 0x803a0d8 +_zw_protocol_cmd_handlers_lr 0x50 0x803a3c0 +_zw_protocol_cmd_handlers 0xe8 0x803a410 +.ARM.exidx 0x8 0x803a4f8 +.copy.table 0xc 0x803a500 +.zero.table 0x0 0x803a50c .stack 0x500 0x20000000 .data 0x530 0x20000500 .bss 0xa52c 0x20000a30 text_application_ram 0x0 0x2000af5c .heap 0x80 0x2000af60 -.zwave_nvm 0x0 0x803a494 -.nvm 0xa000 0x803a494 +.zwave_nvm 0x0 0x803a50c +.nvm 0xa000 0x803a50c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x10850 0x0 -.debug_info 0x292693 0x0 -.debug_abbrev 0x1cd79 0x0 -.debug_loclists 0x1d1f6 0x0 +.debug_info 0x293aea 0x0 +.debug_abbrev 0x1cd4d 0x0 +.debug_loclists 0x1d2a8 0x0 .debug_aranges 0x5b20 0x0 -.debug_rnglists 0x3b0d 0x0 -.debug_line 0x60e5b 0x0 -.debug_str 0x8a982 0x0 -.debug_loc 0x2f047 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x44ff10 +.debug_rnglists 0x3b20 0x0 +.debug_line 0x60f53 0x0 +.debug_str 0x8a98b 0x0 +.debug_loc 0x2f131 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x4516cb The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 215492 + 215612 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_EU_size.txt index 000214ef4d..5b58f64659 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x34060 0x8006000 -_cmd_handlers 0x2e8 0x803a060 -_zw_protocol_cmd_handlers_lr 0x50 0x803a348 -_zw_protocol_cmd_handlers 0xe8 0x803a398 -.ARM.exidx 0x8 0x803a480 -.copy.table 0xc 0x803a488 -.zero.table 0x0 0x803a494 +.text 0x340d8 0x8006000 +_cmd_handlers 0x2e8 0x803a0d8 +_zw_protocol_cmd_handlers_lr 0x50 0x803a3c0 +_zw_protocol_cmd_handlers 0xe8 0x803a410 +.ARM.exidx 0x8 0x803a4f8 +.copy.table 0xc 0x803a500 +.zero.table 0x0 0x803a50c .stack 0x500 0x20000000 .data 0x530 0x20000500 .bss 0xa6e4 0x20000a30 text_application_ram 0x0 0x2000b114 .heap 0x80 0x2000b118 -.zwave_nvm 0x0 0x803a494 -.nvm 0xa000 0x803a494 +.zwave_nvm 0x0 0x803a50c +.nvm 0xa000 0x803a50c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x108c0 0x0 -.debug_info 0x2935aa 0x0 -.debug_abbrev 0x1cdc2 0x0 -.debug_loclists 0x1e16a 0x0 +.debug_info 0x294a01 0x0 +.debug_abbrev 0x1cd96 0x0 +.debug_loclists 0x1e21c 0x0 .debug_aranges 0x5b38 0x0 -.debug_rnglists 0x3b9f 0x0 -.debug_line 0x611e8 0x0 -.debug_str 0x8ae94 0x0 -.debug_loc 0x2f047 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x452955 +.debug_rnglists 0x3bb2 0x0 +.debug_line 0x612e2 0x0 +.debug_str 0x8ae9d 0x0 +.debug_loc 0x2f131 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x454112 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 215492 + 215612 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_US_LR_size.txt index df0f4d4d61..ae8169bc69 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x34060 0x8006000 -_cmd_handlers 0x2e8 0x803a060 -_zw_protocol_cmd_handlers_lr 0x50 0x803a348 -_zw_protocol_cmd_handlers 0xe8 0x803a398 -.ARM.exidx 0x8 0x803a480 -.copy.table 0xc 0x803a488 -.zero.table 0x0 0x803a494 +.text 0x340d8 0x8006000 +_cmd_handlers 0x2e8 0x803a0d8 +_zw_protocol_cmd_handlers_lr 0x50 0x803a3c0 +_zw_protocol_cmd_handlers 0xe8 0x803a410 +.ARM.exidx 0x8 0x803a4f8 +.copy.table 0xc 0x803a500 +.zero.table 0x0 0x803a50c .stack 0x500 0x20000000 .data 0x530 0x20000500 .bss 0xa6e4 0x20000a30 text_application_ram 0x0 0x2000b114 .heap 0x80 0x2000b118 -.zwave_nvm 0x0 0x803a494 -.nvm 0xa000 0x803a494 +.zwave_nvm 0x0 0x803a50c +.nvm 0xa000 0x803a50c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x108c0 0x0 -.debug_info 0x2935aa 0x0 -.debug_abbrev 0x1cdc2 0x0 -.debug_loclists 0x1e16a 0x0 +.debug_info 0x294a01 0x0 +.debug_abbrev 0x1cd96 0x0 +.debug_loclists 0x1e21c 0x0 .debug_aranges 0x5b38 0x0 -.debug_rnglists 0x3b9f 0x0 -.debug_line 0x611e8 0x0 -.debug_str 0x8ae8a 0x0 -.debug_loc 0x2f047 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x45294b +.debug_rnglists 0x3bb2 0x0 +.debug_line 0x612e2 0x0 +.debug_str 0x8ae93 0x0 +.debug_loc 0x2f131 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x454108 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 215492 + 215612 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_US_size.txt index 000214ef4d..5b58f64659 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x34060 0x8006000 -_cmd_handlers 0x2e8 0x803a060 -_zw_protocol_cmd_handlers_lr 0x50 0x803a348 -_zw_protocol_cmd_handlers 0xe8 0x803a398 -.ARM.exidx 0x8 0x803a480 -.copy.table 0xc 0x803a488 -.zero.table 0x0 0x803a494 +.text 0x340d8 0x8006000 +_cmd_handlers 0x2e8 0x803a0d8 +_zw_protocol_cmd_handlers_lr 0x50 0x803a3c0 +_zw_protocol_cmd_handlers 0xe8 0x803a410 +.ARM.exidx 0x8 0x803a4f8 +.copy.table 0xc 0x803a500 +.zero.table 0x0 0x803a50c .stack 0x500 0x20000000 .data 0x530 0x20000500 .bss 0xa6e4 0x20000a30 text_application_ram 0x0 0x2000b114 .heap 0x80 0x2000b118 -.zwave_nvm 0x0 0x803a494 -.nvm 0xa000 0x803a494 +.zwave_nvm 0x0 0x803a50c +.nvm 0xa000 0x803a50c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x108c0 0x0 -.debug_info 0x2935aa 0x0 -.debug_abbrev 0x1cdc2 0x0 -.debug_loclists 0x1e16a 0x0 +.debug_info 0x294a01 0x0 +.debug_abbrev 0x1cd96 0x0 +.debug_loclists 0x1e21c 0x0 .debug_aranges 0x5b38 0x0 -.debug_rnglists 0x3b9f 0x0 -.debug_line 0x611e8 0x0 -.debug_str 0x8ae94 0x0 -.debug_loc 0x2f047 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x452955 +.debug_rnglists 0x3bb2 0x0 +.debug_line 0x612e2 0x0 +.debug_str 0x8ae9d 0x0 +.debug_loc 0x2f131 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x454112 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 215492 + 215612 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_EU_size.txt index b7422c7e25..3252d01466 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2f9cc 0x0 -_cmd_handlers 0x2e8 0x2f9cc -_zw_protocol_cmd_handlers_lr 0x50 0x2fcb4 -_zw_protocol_cmd_handlers 0xe8 0x2fd04 -.ARM.exidx 0x8 0x2fdec -.copy.table 0xc 0x2fdf4 -.zero.table 0x0 0x2fe00 +.text 0x2fa2c 0x0 +_cmd_handlers 0x2e8 0x2fa2c +_zw_protocol_cmd_handlers_lr 0x50 0x2fd14 +_zw_protocol_cmd_handlers 0xe8 0x2fd64 +.ARM.exidx 0x8 0x2fe4c +.copy.table 0xc 0x2fe54 +.zero.table 0x0 0x2fe60 .stack 0x500 0x20000000 .data 0x3a0 0x20000500 .bss 0x7664 0x200008a0 text_application_ram 0x0 0x20007f04 .heap 0x80 0x20007f08 -.zwave_nvm 0x3000 0x2fe00 -.nvm 0x9000 0x32e00 +.zwave_nvm 0x3000 0x2fe60 +.nvm 0x9000 0x32e60 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x28a 0x0 -.debug_frame 0xe900 0x0 -.debug_info 0x255971 0x0 -.debug_abbrev 0x19cae 0x0 -.debug_loclists 0x137f0 0x0 -.debug_aranges 0x50a0 0x0 -.debug_rnglists 0x2b31 0x0 -.debug_line 0x558a6 0x0 -.debug_str 0x80d29 0x0 -.debug_loc 0x30552 0x0 -.debug_ranges 0x5db8 0x0 -Total 0x3e9c3a +.debug_frame 0xe8e0 0x0 +.debug_info 0x255882 0x0 +.debug_abbrev 0x19cad 0x0 +.debug_loclists 0x1381e 0x0 +.debug_aranges 0x5098 0x0 +.debug_rnglists 0x2b41 0x0 +.debug_line 0x55905 0x0 +.debug_str 0x80d11 0x0 +.debug_loc 0x3063c 0x0 +.debug_ranges 0x5e00 0x0 +Total 0x3e9d39 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197024 + 197120 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_US_LR_size.txt index eeb920c20c..6d35dcc82a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2f9cc 0x0 -_cmd_handlers 0x2e8 0x2f9cc -_zw_protocol_cmd_handlers_lr 0x50 0x2fcb4 -_zw_protocol_cmd_handlers 0xe8 0x2fd04 -.ARM.exidx 0x8 0x2fdec -.copy.table 0xc 0x2fdf4 -.zero.table 0x0 0x2fe00 +.text 0x2fa2c 0x0 +_cmd_handlers 0x2e8 0x2fa2c +_zw_protocol_cmd_handlers_lr 0x50 0x2fd14 +_zw_protocol_cmd_handlers 0xe8 0x2fd64 +.ARM.exidx 0x8 0x2fe4c +.copy.table 0xc 0x2fe54 +.zero.table 0x0 0x2fe60 .stack 0x500 0x20000000 .data 0x3a0 0x20000500 .bss 0x7664 0x200008a0 text_application_ram 0x0 0x20007f04 .heap 0x80 0x20007f08 -.zwave_nvm 0x3000 0x2fe00 -.nvm 0x9000 0x32e00 +.zwave_nvm 0x3000 0x2fe60 +.nvm 0x9000 0x32e60 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x28a 0x0 -.debug_frame 0xe900 0x0 -.debug_info 0x255971 0x0 -.debug_abbrev 0x19cae 0x0 -.debug_loclists 0x137f0 0x0 -.debug_aranges 0x50a0 0x0 -.debug_rnglists 0x2b31 0x0 -.debug_line 0x558a6 0x0 -.debug_str 0x80d1f 0x0 -.debug_loc 0x30552 0x0 -.debug_ranges 0x5db8 0x0 -Total 0x3e9c30 +.debug_frame 0xe8e0 0x0 +.debug_info 0x255882 0x0 +.debug_abbrev 0x19cad 0x0 +.debug_loclists 0x1381e 0x0 +.debug_aranges 0x5098 0x0 +.debug_rnglists 0x2b41 0x0 +.debug_line 0x55905 0x0 +.debug_str 0x80d07 0x0 +.debug_loc 0x3063c 0x0 +.debug_ranges 0x5e00 0x0 +Total 0x3e9d2f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197024 + 197120 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_US_size.txt index b7422c7e25..3252d01466 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2f9cc 0x0 -_cmd_handlers 0x2e8 0x2f9cc -_zw_protocol_cmd_handlers_lr 0x50 0x2fcb4 -_zw_protocol_cmd_handlers 0xe8 0x2fd04 -.ARM.exidx 0x8 0x2fdec -.copy.table 0xc 0x2fdf4 -.zero.table 0x0 0x2fe00 +.text 0x2fa2c 0x0 +_cmd_handlers 0x2e8 0x2fa2c +_zw_protocol_cmd_handlers_lr 0x50 0x2fd14 +_zw_protocol_cmd_handlers 0xe8 0x2fd64 +.ARM.exidx 0x8 0x2fe4c +.copy.table 0xc 0x2fe54 +.zero.table 0x0 0x2fe60 .stack 0x500 0x20000000 .data 0x3a0 0x20000500 .bss 0x7664 0x200008a0 text_application_ram 0x0 0x20007f04 .heap 0x80 0x20007f08 -.zwave_nvm 0x3000 0x2fe00 -.nvm 0x9000 0x32e00 +.zwave_nvm 0x3000 0x2fe60 +.nvm 0x9000 0x32e60 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x28a 0x0 -.debug_frame 0xe900 0x0 -.debug_info 0x255971 0x0 -.debug_abbrev 0x19cae 0x0 -.debug_loclists 0x137f0 0x0 -.debug_aranges 0x50a0 0x0 -.debug_rnglists 0x2b31 0x0 -.debug_line 0x558a6 0x0 -.debug_str 0x80d29 0x0 -.debug_loc 0x30552 0x0 -.debug_ranges 0x5db8 0x0 -Total 0x3e9c3a +.debug_frame 0xe8e0 0x0 +.debug_info 0x255882 0x0 +.debug_abbrev 0x19cad 0x0 +.debug_loclists 0x1381e 0x0 +.debug_aranges 0x5098 0x0 +.debug_rnglists 0x2b41 0x0 +.debug_line 0x55905 0x0 +.debug_str 0x80d11 0x0 +.debug_loc 0x3063c 0x0 +.debug_ranges 0x5e00 0x0 +Total 0x3e9d39 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197024 + 197120 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_EU_size.txt index 59f660f6f9..372c30d61e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x30338 0x0 -_cmd_handlers 0x2e8 0x30338 -_zw_protocol_cmd_handlers_lr 0x50 0x30620 -_zw_protocol_cmd_handlers 0xe8 0x30670 -.ARM.exidx 0x8 0x30758 -.copy.table 0xc 0x30760 -.zero.table 0x0 0x3076c +.text 0x303ac 0x0 +_cmd_handlers 0x2e8 0x303ac +_zw_protocol_cmd_handlers_lr 0x50 0x30694 +_zw_protocol_cmd_handlers 0xe8 0x306e4 +.ARM.exidx 0x8 0x307cc +.copy.table 0xc 0x307d4 +.zero.table 0x0 0x307e0 .stack 0x500 0x20000000 .data 0x3a0 0x20000500 .bss 0x9b20 0x200008a0 text_application_ram 0x0 0x2000a3c0 .heap 0x80 0x2000a3c0 -.zwave_nvm 0x3000 0x3076c -.nvm 0x9000 0x3376c +.zwave_nvm 0x3000 0x307e0 +.nvm 0x9000 0x337e0 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x28a 0x0 -.debug_frame 0xe9a8 0x0 -.debug_info 0x2578ce 0x0 -.debug_abbrev 0x19ebb 0x0 -.debug_loclists 0x13b4c 0x0 -.debug_aranges 0x5118 0x0 -.debug_rnglists 0x2bb5 0x0 -.debug_line 0x55d38 0x0 -.debug_str 0x81807 0x0 -.debug_loc 0x30551 0x0 -.debug_ranges 0x5db8 0x0 -Total 0x3f003b +.debug_frame 0xe988 0x0 +.debug_info 0x2577ed 0x0 +.debug_abbrev 0x19eba 0x0 +.debug_loclists 0x13b7a 0x0 +.debug_aranges 0x5110 0x0 +.debug_rnglists 0x2bc5 0x0 +.debug_line 0x55d8d 0x0 +.debug_str 0x817ef 0x0 +.debug_loc 0x3063b 0x0 +.debug_ranges 0x5e00 0x0 +Total 0x3f0152 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 199436 + 199552 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_US_LR_size.txt index 10f04767c1..2a67ad88eb 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x30338 0x0 -_cmd_handlers 0x2e8 0x30338 -_zw_protocol_cmd_handlers_lr 0x50 0x30620 -_zw_protocol_cmd_handlers 0xe8 0x30670 -.ARM.exidx 0x8 0x30758 -.copy.table 0xc 0x30760 -.zero.table 0x0 0x3076c +.text 0x303ac 0x0 +_cmd_handlers 0x2e8 0x303ac +_zw_protocol_cmd_handlers_lr 0x50 0x30694 +_zw_protocol_cmd_handlers 0xe8 0x306e4 +.ARM.exidx 0x8 0x307cc +.copy.table 0xc 0x307d4 +.zero.table 0x0 0x307e0 .stack 0x500 0x20000000 .data 0x3a0 0x20000500 .bss 0x9b20 0x200008a0 text_application_ram 0x0 0x2000a3c0 .heap 0x80 0x2000a3c0 -.zwave_nvm 0x3000 0x3076c -.nvm 0x9000 0x3376c +.zwave_nvm 0x3000 0x307e0 +.nvm 0x9000 0x337e0 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x28a 0x0 -.debug_frame 0xe9a8 0x0 -.debug_info 0x2578ce 0x0 -.debug_abbrev 0x19ebb 0x0 -.debug_loclists 0x13b4c 0x0 -.debug_aranges 0x5118 0x0 -.debug_rnglists 0x2bb5 0x0 -.debug_line 0x55d38 0x0 -.debug_str 0x817fd 0x0 -.debug_loc 0x30551 0x0 -.debug_ranges 0x5db8 0x0 -Total 0x3f0031 +.debug_frame 0xe988 0x0 +.debug_info 0x2577ed 0x0 +.debug_abbrev 0x19eba 0x0 +.debug_loclists 0x13b7a 0x0 +.debug_aranges 0x5110 0x0 +.debug_rnglists 0x2bc5 0x0 +.debug_line 0x55d8d 0x0 +.debug_str 0x817e5 0x0 +.debug_loc 0x3063b 0x0 +.debug_ranges 0x5e00 0x0 +Total 0x3f0148 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 199436 + 199552 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_US_size.txt index 59f660f6f9..372c30d61e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x30338 0x0 -_cmd_handlers 0x2e8 0x30338 -_zw_protocol_cmd_handlers_lr 0x50 0x30620 -_zw_protocol_cmd_handlers 0xe8 0x30670 -.ARM.exidx 0x8 0x30758 -.copy.table 0xc 0x30760 -.zero.table 0x0 0x3076c +.text 0x303ac 0x0 +_cmd_handlers 0x2e8 0x303ac +_zw_protocol_cmd_handlers_lr 0x50 0x30694 +_zw_protocol_cmd_handlers 0xe8 0x306e4 +.ARM.exidx 0x8 0x307cc +.copy.table 0xc 0x307d4 +.zero.table 0x0 0x307e0 .stack 0x500 0x20000000 .data 0x3a0 0x20000500 .bss 0x9b20 0x200008a0 text_application_ram 0x0 0x2000a3c0 .heap 0x80 0x2000a3c0 -.zwave_nvm 0x3000 0x3076c -.nvm 0x9000 0x3376c +.zwave_nvm 0x3000 0x307e0 +.nvm 0x9000 0x337e0 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x28a 0x0 -.debug_frame 0xe9a8 0x0 -.debug_info 0x2578ce 0x0 -.debug_abbrev 0x19ebb 0x0 -.debug_loclists 0x13b4c 0x0 -.debug_aranges 0x5118 0x0 -.debug_rnglists 0x2bb5 0x0 -.debug_line 0x55d38 0x0 -.debug_str 0x81807 0x0 -.debug_loc 0x30551 0x0 -.debug_ranges 0x5db8 0x0 -Total 0x3f003b +.debug_frame 0xe988 0x0 +.debug_info 0x2577ed 0x0 +.debug_abbrev 0x19eba 0x0 +.debug_loclists 0x13b7a 0x0 +.debug_aranges 0x5110 0x0 +.debug_rnglists 0x2bc5 0x0 +.debug_line 0x55d8d 0x0 +.debug_str 0x817ef 0x0 +.debug_loc 0x3063b 0x0 +.debug_ranges 0x5e00 0x0 +Total 0x3f0152 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 199436 + 199552 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_EU_size.txt index b7422c7e25..3252d01466 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2f9cc 0x0 -_cmd_handlers 0x2e8 0x2f9cc -_zw_protocol_cmd_handlers_lr 0x50 0x2fcb4 -_zw_protocol_cmd_handlers 0xe8 0x2fd04 -.ARM.exidx 0x8 0x2fdec -.copy.table 0xc 0x2fdf4 -.zero.table 0x0 0x2fe00 +.text 0x2fa2c 0x0 +_cmd_handlers 0x2e8 0x2fa2c +_zw_protocol_cmd_handlers_lr 0x50 0x2fd14 +_zw_protocol_cmd_handlers 0xe8 0x2fd64 +.ARM.exidx 0x8 0x2fe4c +.copy.table 0xc 0x2fe54 +.zero.table 0x0 0x2fe60 .stack 0x500 0x20000000 .data 0x3a0 0x20000500 .bss 0x7664 0x200008a0 text_application_ram 0x0 0x20007f04 .heap 0x80 0x20007f08 -.zwave_nvm 0x3000 0x2fe00 -.nvm 0x9000 0x32e00 +.zwave_nvm 0x3000 0x2fe60 +.nvm 0x9000 0x32e60 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x28a 0x0 -.debug_frame 0xe900 0x0 -.debug_info 0x255971 0x0 -.debug_abbrev 0x19cae 0x0 -.debug_loclists 0x137f0 0x0 -.debug_aranges 0x50a0 0x0 -.debug_rnglists 0x2b31 0x0 -.debug_line 0x558a6 0x0 -.debug_str 0x80d29 0x0 -.debug_loc 0x30552 0x0 -.debug_ranges 0x5db8 0x0 -Total 0x3e9c3a +.debug_frame 0xe8e0 0x0 +.debug_info 0x255882 0x0 +.debug_abbrev 0x19cad 0x0 +.debug_loclists 0x1381e 0x0 +.debug_aranges 0x5098 0x0 +.debug_rnglists 0x2b41 0x0 +.debug_line 0x55905 0x0 +.debug_str 0x80d11 0x0 +.debug_loc 0x3063c 0x0 +.debug_ranges 0x5e00 0x0 +Total 0x3e9d39 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197024 + 197120 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_US_LR_size.txt index eeb920c20c..6d35dcc82a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2f9cc 0x0 -_cmd_handlers 0x2e8 0x2f9cc -_zw_protocol_cmd_handlers_lr 0x50 0x2fcb4 -_zw_protocol_cmd_handlers 0xe8 0x2fd04 -.ARM.exidx 0x8 0x2fdec -.copy.table 0xc 0x2fdf4 -.zero.table 0x0 0x2fe00 +.text 0x2fa2c 0x0 +_cmd_handlers 0x2e8 0x2fa2c +_zw_protocol_cmd_handlers_lr 0x50 0x2fd14 +_zw_protocol_cmd_handlers 0xe8 0x2fd64 +.ARM.exidx 0x8 0x2fe4c +.copy.table 0xc 0x2fe54 +.zero.table 0x0 0x2fe60 .stack 0x500 0x20000000 .data 0x3a0 0x20000500 .bss 0x7664 0x200008a0 text_application_ram 0x0 0x20007f04 .heap 0x80 0x20007f08 -.zwave_nvm 0x3000 0x2fe00 -.nvm 0x9000 0x32e00 +.zwave_nvm 0x3000 0x2fe60 +.nvm 0x9000 0x32e60 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x28a 0x0 -.debug_frame 0xe900 0x0 -.debug_info 0x255971 0x0 -.debug_abbrev 0x19cae 0x0 -.debug_loclists 0x137f0 0x0 -.debug_aranges 0x50a0 0x0 -.debug_rnglists 0x2b31 0x0 -.debug_line 0x558a6 0x0 -.debug_str 0x80d1f 0x0 -.debug_loc 0x30552 0x0 -.debug_ranges 0x5db8 0x0 -Total 0x3e9c30 +.debug_frame 0xe8e0 0x0 +.debug_info 0x255882 0x0 +.debug_abbrev 0x19cad 0x0 +.debug_loclists 0x1381e 0x0 +.debug_aranges 0x5098 0x0 +.debug_rnglists 0x2b41 0x0 +.debug_line 0x55905 0x0 +.debug_str 0x80d07 0x0 +.debug_loc 0x3063c 0x0 +.debug_ranges 0x5e00 0x0 +Total 0x3e9d2f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197024 + 197120 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_US_size.txt index b7422c7e25..3252d01466 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2f9cc 0x0 -_cmd_handlers 0x2e8 0x2f9cc -_zw_protocol_cmd_handlers_lr 0x50 0x2fcb4 -_zw_protocol_cmd_handlers 0xe8 0x2fd04 -.ARM.exidx 0x8 0x2fdec -.copy.table 0xc 0x2fdf4 -.zero.table 0x0 0x2fe00 +.text 0x2fa2c 0x0 +_cmd_handlers 0x2e8 0x2fa2c +_zw_protocol_cmd_handlers_lr 0x50 0x2fd14 +_zw_protocol_cmd_handlers 0xe8 0x2fd64 +.ARM.exidx 0x8 0x2fe4c +.copy.table 0xc 0x2fe54 +.zero.table 0x0 0x2fe60 .stack 0x500 0x20000000 .data 0x3a0 0x20000500 .bss 0x7664 0x200008a0 text_application_ram 0x0 0x20007f04 .heap 0x80 0x20007f08 -.zwave_nvm 0x3000 0x2fe00 -.nvm 0x9000 0x32e00 +.zwave_nvm 0x3000 0x2fe60 +.nvm 0x9000 0x32e60 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x28a 0x0 -.debug_frame 0xe900 0x0 -.debug_info 0x255971 0x0 -.debug_abbrev 0x19cae 0x0 -.debug_loclists 0x137f0 0x0 -.debug_aranges 0x50a0 0x0 -.debug_rnglists 0x2b31 0x0 -.debug_line 0x558a6 0x0 -.debug_str 0x80d29 0x0 -.debug_loc 0x30552 0x0 -.debug_ranges 0x5db8 0x0 -Total 0x3e9c3a +.debug_frame 0xe8e0 0x0 +.debug_info 0x255882 0x0 +.debug_abbrev 0x19cad 0x0 +.debug_loclists 0x1381e 0x0 +.debug_aranges 0x5098 0x0 +.debug_rnglists 0x2b41 0x0 +.debug_line 0x55905 0x0 +.debug_str 0x80d11 0x0 +.debug_loc 0x3063c 0x0 +.debug_ranges 0x5e00 0x0 +Total 0x3e9d39 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197024 + 197120 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4210A_REGION_US_LR_size.txt index b15ae3b068..fd4202b57f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4210A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x33d8c 0x8006000 -_cmd_handlers 0x2e8 0x8039d8c -_zw_protocol_cmd_handlers_lr 0x50 0x803a074 -_zw_protocol_cmd_handlers 0xe8 0x803a0c4 -.ARM.exidx 0x8 0x803a1ac -.copy.table 0xc 0x803a1b4 -.zero.table 0x0 0x803a1c0 +.text 0x33e04 0x8006000 +_cmd_handlers 0x2e8 0x8039e04 +_zw_protocol_cmd_handlers_lr 0x50 0x803a0ec +_zw_protocol_cmd_handlers 0xe8 0x803a13c +.ARM.exidx 0x8 0x803a224 +.copy.table 0xc 0x803a22c +.zero.table 0x0 0x803a238 .stack 0x500 0x20000000 .data 0x530 0x20000500 .bss 0xa6e0 0x20000a30 text_application_ram 0x0 0x2000b110 .heap 0x80 0x2000b110 -.zwave_nvm 0x0 0x803a1c0 -.nvm 0xa000 0x803a1c0 +.zwave_nvm 0x0 0x803a238 +.nvm 0xa000 0x803a238 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x10898 0x0 -.debug_info 0x292ba5 0x0 -.debug_abbrev 0x1cce6 0x0 -.debug_loclists 0x1e16a 0x0 +.debug_info 0x293ffc 0x0 +.debug_abbrev 0x1ccba 0x0 +.debug_loclists 0x1e21c 0x0 .debug_aranges 0x5ae8 0x0 -.debug_rnglists 0x3b87 0x0 -.debug_line 0x6130e 0x0 -.debug_str 0x8a8ba 0x0 -.debug_loc 0x2f03b 0x0 -.debug_ranges 0x5bb8 0x0 -Total 0x451634 +.debug_rnglists 0x3b9a 0x0 +.debug_line 0x61410 0x0 +.debug_str 0x8a8c3 0x0 +.debug_loc 0x2f125 0x0 +.debug_ranges 0x5c20 0x0 +Total 0x452df9 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214768 + 214888 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400B_REGION_EU_size.txt index d151b6fdad..ca2aa0b6d6 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400B_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x3492c 0x8006000 -_cmd_handlers 0x2e8 0x803a92c -_zw_protocol_cmd_handlers_lr 0x50 0x803ac14 -_zw_protocol_cmd_handlers 0xe8 0x803ac64 -.ARM.exidx 0x8 0x803ad4c -.copy.table 0xc 0x803ad54 -.zero.table 0x0 0x803ad60 +.text 0x349a4 0x8006000 +_cmd_handlers 0x2e8 0x803a9a4 +_zw_protocol_cmd_handlers_lr 0x50 0x803ac8c +_zw_protocol_cmd_handlers 0xe8 0x803acdc +.ARM.exidx 0x8 0x803adc4 +.copy.table 0xc 0x803adcc +.zero.table 0x0 0x803add8 .stack 0x500 0x20000000 .data 0x52c 0x20000500 .bss 0xa650 0x20000a2c text_application_ram 0x0 0x2000b07c .heap 0x80 0x2000b080 -.zwave_nvm 0x0 0x803ad60 -.nvm 0xa000 0x803ad60 +.zwave_nvm 0x0 0x803add8 +.nvm 0xa000 0x803add8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x1095c 0x0 -.debug_info 0x29754c 0x0 -.debug_abbrev 0x1d02d 0x0 -.debug_loclists 0x1e699 0x0 +.debug_info 0x2989a7 0x0 +.debug_abbrev 0x1d001 0x0 +.debug_loclists 0x1e74b 0x0 .debug_aranges 0x5b68 0x0 -.debug_rnglists 0x3bdc 0x0 -.debug_line 0x616d3 0x0 -.debug_str 0x8c149 0x0 -.debug_loc 0x2ef43 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x45906a +.debug_rnglists 0x3bef 0x0 +.debug_line 0x617d5 0x0 +.debug_str 0x8c152 0x0 +.debug_loc 0x2f02d 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x45a833 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217740 + 217860 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400B_REGION_US_LR_size.txt index 4c699bff93..6c885f8568 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400B_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x3492c 0x8006000 -_cmd_handlers 0x2e8 0x803a92c -_zw_protocol_cmd_handlers_lr 0x50 0x803ac14 -_zw_protocol_cmd_handlers 0xe8 0x803ac64 -.ARM.exidx 0x8 0x803ad4c -.copy.table 0xc 0x803ad54 -.zero.table 0x0 0x803ad60 +.text 0x349a4 0x8006000 +_cmd_handlers 0x2e8 0x803a9a4 +_zw_protocol_cmd_handlers_lr 0x50 0x803ac8c +_zw_protocol_cmd_handlers 0xe8 0x803acdc +.ARM.exidx 0x8 0x803adc4 +.copy.table 0xc 0x803adcc +.zero.table 0x0 0x803add8 .stack 0x500 0x20000000 .data 0x52c 0x20000500 .bss 0xa650 0x20000a2c text_application_ram 0x0 0x2000b07c .heap 0x80 0x2000b080 -.zwave_nvm 0x0 0x803ad60 -.nvm 0xa000 0x803ad60 +.zwave_nvm 0x0 0x803add8 +.nvm 0xa000 0x803add8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x1095c 0x0 -.debug_info 0x29754c 0x0 -.debug_abbrev 0x1d02d 0x0 -.debug_loclists 0x1e699 0x0 +.debug_info 0x2989a7 0x0 +.debug_abbrev 0x1d001 0x0 +.debug_loclists 0x1e74b 0x0 .debug_aranges 0x5b68 0x0 -.debug_rnglists 0x3bdc 0x0 -.debug_line 0x616d3 0x0 -.debug_str 0x8c13f 0x0 -.debug_loc 0x2ef43 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x459060 +.debug_rnglists 0x3bef 0x0 +.debug_line 0x617d5 0x0 +.debug_str 0x8c148 0x0 +.debug_loc 0x2f02d 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x45a829 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217740 + 217860 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400B_REGION_US_size.txt index d151b6fdad..ca2aa0b6d6 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400B_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x3492c 0x8006000 -_cmd_handlers 0x2e8 0x803a92c -_zw_protocol_cmd_handlers_lr 0x50 0x803ac14 -_zw_protocol_cmd_handlers 0xe8 0x803ac64 -.ARM.exidx 0x8 0x803ad4c -.copy.table 0xc 0x803ad54 -.zero.table 0x0 0x803ad60 +.text 0x349a4 0x8006000 +_cmd_handlers 0x2e8 0x803a9a4 +_zw_protocol_cmd_handlers_lr 0x50 0x803ac8c +_zw_protocol_cmd_handlers 0xe8 0x803acdc +.ARM.exidx 0x8 0x803adc4 +.copy.table 0xc 0x803adcc +.zero.table 0x0 0x803add8 .stack 0x500 0x20000000 .data 0x52c 0x20000500 .bss 0xa650 0x20000a2c text_application_ram 0x0 0x2000b07c .heap 0x80 0x2000b080 -.zwave_nvm 0x0 0x803ad60 -.nvm 0xa000 0x803ad60 +.zwave_nvm 0x0 0x803add8 +.nvm 0xa000 0x803add8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x1095c 0x0 -.debug_info 0x29754c 0x0 -.debug_abbrev 0x1d02d 0x0 -.debug_loclists 0x1e699 0x0 +.debug_info 0x2989a7 0x0 +.debug_abbrev 0x1d001 0x0 +.debug_loclists 0x1e74b 0x0 .debug_aranges 0x5b68 0x0 -.debug_rnglists 0x3bdc 0x0 -.debug_line 0x616d3 0x0 -.debug_str 0x8c149 0x0 -.debug_loc 0x2ef43 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x45906a +.debug_rnglists 0x3bef 0x0 +.debug_line 0x617d5 0x0 +.debug_str 0x8c152 0x0 +.debug_loc 0x2f02d 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x45a833 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217740 + 217860 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400C_REGION_EU_size.txt index 62b60c07ad..e0091118db 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400C_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x3492c 0x8006000 -_cmd_handlers 0x2e8 0x803a92c -_zw_protocol_cmd_handlers_lr 0x50 0x803ac14 -_zw_protocol_cmd_handlers 0xe8 0x803ac64 -.ARM.exidx 0x8 0x803ad4c -.copy.table 0xc 0x803ad54 -.zero.table 0x0 0x803ad60 +.text 0x349a4 0x8006000 +_cmd_handlers 0x2e8 0x803a9a4 +_zw_protocol_cmd_handlers_lr 0x50 0x803ac8c +_zw_protocol_cmd_handlers 0xe8 0x803acdc +.ARM.exidx 0x8 0x803adc4 +.copy.table 0xc 0x803adcc +.zero.table 0x0 0x803add8 .stack 0x500 0x20000000 .data 0x52c 0x20000500 .bss 0xa650 0x20000a2c text_application_ram 0x0 0x2000b07c .heap 0x80 0x2000b080 -.zwave_nvm 0x0 0x803ad60 -.nvm 0xa000 0x803ad60 +.zwave_nvm 0x0 0x803add8 +.nvm 0xa000 0x803add8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x10970 0x0 -.debug_info 0x2974db 0x0 -.debug_abbrev 0x1d037 0x0 -.debug_loclists 0x1e665 0x0 +.debug_info 0x298936 0x0 +.debug_abbrev 0x1d00b 0x0 +.debug_loclists 0x1e717 0x0 .debug_aranges 0x5b70 0x0 -.debug_rnglists 0x3c05 0x0 -.debug_line 0x616c8 0x0 -.debug_str 0x8c149 0x0 -.debug_loc 0x2ef43 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x459009 +.debug_rnglists 0x3c18 0x0 +.debug_line 0x617ca 0x0 +.debug_str 0x8c152 0x0 +.debug_loc 0x2f02d 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x45a7d2 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217740 + 217860 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400C_REGION_US_LR_size.txt index 0ac03b4101..53199cfc14 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400C_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x3492c 0x8006000 -_cmd_handlers 0x2e8 0x803a92c -_zw_protocol_cmd_handlers_lr 0x50 0x803ac14 -_zw_protocol_cmd_handlers 0xe8 0x803ac64 -.ARM.exidx 0x8 0x803ad4c -.copy.table 0xc 0x803ad54 -.zero.table 0x0 0x803ad60 +.text 0x349a4 0x8006000 +_cmd_handlers 0x2e8 0x803a9a4 +_zw_protocol_cmd_handlers_lr 0x50 0x803ac8c +_zw_protocol_cmd_handlers 0xe8 0x803acdc +.ARM.exidx 0x8 0x803adc4 +.copy.table 0xc 0x803adcc +.zero.table 0x0 0x803add8 .stack 0x500 0x20000000 .data 0x52c 0x20000500 .bss 0xa650 0x20000a2c text_application_ram 0x0 0x2000b07c .heap 0x80 0x2000b080 -.zwave_nvm 0x0 0x803ad60 -.nvm 0xa000 0x803ad60 +.zwave_nvm 0x0 0x803add8 +.nvm 0xa000 0x803add8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x10970 0x0 -.debug_info 0x2974db 0x0 -.debug_abbrev 0x1d037 0x0 -.debug_loclists 0x1e665 0x0 +.debug_info 0x298936 0x0 +.debug_abbrev 0x1d00b 0x0 +.debug_loclists 0x1e717 0x0 .debug_aranges 0x5b70 0x0 -.debug_rnglists 0x3c05 0x0 -.debug_line 0x616c8 0x0 -.debug_str 0x8c13f 0x0 -.debug_loc 0x2ef43 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x458fff +.debug_rnglists 0x3c18 0x0 +.debug_line 0x617ca 0x0 +.debug_str 0x8c148 0x0 +.debug_loc 0x2f02d 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x45a7c8 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217740 + 217860 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400C_REGION_US_size.txt index 62b60c07ad..e0091118db 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4400C_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x3492c 0x8006000 -_cmd_handlers 0x2e8 0x803a92c -_zw_protocol_cmd_handlers_lr 0x50 0x803ac14 -_zw_protocol_cmd_handlers 0xe8 0x803ac64 -.ARM.exidx 0x8 0x803ad4c -.copy.table 0xc 0x803ad54 -.zero.table 0x0 0x803ad60 +.text 0x349a4 0x8006000 +_cmd_handlers 0x2e8 0x803a9a4 +_zw_protocol_cmd_handlers_lr 0x50 0x803ac8c +_zw_protocol_cmd_handlers 0xe8 0x803acdc +.ARM.exidx 0x8 0x803adc4 +.copy.table 0xc 0x803adcc +.zero.table 0x0 0x803add8 .stack 0x500 0x20000000 .data 0x52c 0x20000500 .bss 0xa650 0x20000a2c text_application_ram 0x0 0x2000b07c .heap 0x80 0x2000b080 -.zwave_nvm 0x0 0x803ad60 -.nvm 0xa000 0x803ad60 +.zwave_nvm 0x0 0x803add8 +.nvm 0xa000 0x803add8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x10970 0x0 -.debug_info 0x2974db 0x0 -.debug_abbrev 0x1d037 0x0 -.debug_loclists 0x1e665 0x0 +.debug_info 0x298936 0x0 +.debug_abbrev 0x1d00b 0x0 +.debug_loclists 0x1e717 0x0 .debug_aranges 0x5b70 0x0 -.debug_rnglists 0x3c05 0x0 -.debug_line 0x616c8 0x0 -.debug_str 0x8c149 0x0 -.debug_loc 0x2ef43 0x0 -.debug_ranges 0x5bd0 0x0 -Total 0x459009 +.debug_rnglists 0x3c18 0x0 +.debug_line 0x617ca 0x0 +.debug_str 0x8c152 0x0 +.debug_loc 0x2f02d 0x0 +.debug_ranges 0x5c38 0x0 +Total 0x45a7d2 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217740 + 217860 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4401B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4401B_REGION_US_LR_size.txt index d6156e9d20..3c6e7dc33b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4401B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4401B_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x3494c 0x8006000 -_cmd_handlers 0x2e8 0x803a94c -_zw_protocol_cmd_handlers_lr 0x50 0x803ac34 -_zw_protocol_cmd_handlers 0xe8 0x803ac84 -.ARM.exidx 0x8 0x803ad6c -.copy.table 0xc 0x803ad74 -.zero.table 0x0 0x803ad80 +.text 0x349c4 0x8006000 +_cmd_handlers 0x2e8 0x803a9c4 +_zw_protocol_cmd_handlers_lr 0x50 0x803acac +_zw_protocol_cmd_handlers 0xe8 0x803acfc +.ARM.exidx 0x8 0x803ade4 +.copy.table 0xc 0x803adec +.zero.table 0x0 0x803adf8 .stack 0x500 0x20000000 .data 0x52c 0x20000500 .bss 0xa650 0x20000a2c text_application_ram 0x0 0x2000b07c .heap 0x80 0x2000b080 -.zwave_nvm 0x0 0x803ad80 -.nvm 0xa000 0x803ad80 +.zwave_nvm 0x0 0x803adf8 +.nvm 0xa000 0x803adf8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x10964 0x0 -.debug_info 0x297516 0x0 -.debug_abbrev 0x1d02d 0x0 -.debug_loclists 0x1e699 0x0 +.debug_info 0x298971 0x0 +.debug_abbrev 0x1d001 0x0 +.debug_loclists 0x1e74b 0x0 .debug_aranges 0x5b68 0x0 -.debug_rnglists 0x3bdc 0x0 -.debug_line 0x616aa 0x0 -.debug_str 0x8c13f 0x0 -.debug_loc 0x2ef28 0x0 -.debug_ranges 0x5bb8 0x0 -Total 0x458ff6 +.debug_rnglists 0x3bef 0x0 +.debug_line 0x617ac 0x0 +.debug_str 0x8c148 0x0 +.debug_loc 0x2f012 0x0 +.debug_ranges 0x5c20 0x0 +Total 0x45a7bf The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217772 + 217892 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4401C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4401C_REGION_EU_size.txt index 84b503b7a0..06bbcdd1b3 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4401C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4401C_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x3494c 0x8006000 -_cmd_handlers 0x2e8 0x803a94c -_zw_protocol_cmd_handlers_lr 0x50 0x803ac34 -_zw_protocol_cmd_handlers 0xe8 0x803ac84 -.ARM.exidx 0x8 0x803ad6c -.copy.table 0xc 0x803ad74 -.zero.table 0x0 0x803ad80 +.text 0x349c4 0x8006000 +_cmd_handlers 0x2e8 0x803a9c4 +_zw_protocol_cmd_handlers_lr 0x50 0x803acac +_zw_protocol_cmd_handlers 0xe8 0x803acfc +.ARM.exidx 0x8 0x803ade4 +.copy.table 0xc 0x803adec +.zero.table 0x0 0x803adf8 .stack 0x500 0x20000000 .data 0x52c 0x20000500 .bss 0xa650 0x20000a2c text_application_ram 0x0 0x2000b07c .heap 0x80 0x2000b080 -.zwave_nvm 0x0 0x803ad80 -.nvm 0xa000 0x803ad80 +.zwave_nvm 0x0 0x803adf8 +.nvm 0xa000 0x803adf8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x10978 0x0 -.debug_info 0x2974a5 0x0 -.debug_abbrev 0x1d037 0x0 -.debug_loclists 0x1e665 0x0 +.debug_info 0x298900 0x0 +.debug_abbrev 0x1d00b 0x0 +.debug_loclists 0x1e717 0x0 .debug_aranges 0x5b70 0x0 -.debug_rnglists 0x3c05 0x0 -.debug_line 0x6169f 0x0 -.debug_str 0x8c149 0x0 -.debug_loc 0x2ef28 0x0 -.debug_ranges 0x5bb8 0x0 -Total 0x458f9f +.debug_rnglists 0x3c18 0x0 +.debug_line 0x617a1 0x0 +.debug_str 0x8c152 0x0 +.debug_loc 0x2f012 0x0 +.debug_ranges 0x5c20 0x0 +Total 0x45a768 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217772 + 217892 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4401C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4401C_REGION_US_LR_size.txt index b0e56ebe3d..08410ebe53 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4401C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4401C_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x3494c 0x8006000 -_cmd_handlers 0x2e8 0x803a94c -_zw_protocol_cmd_handlers_lr 0x50 0x803ac34 -_zw_protocol_cmd_handlers 0xe8 0x803ac84 -.ARM.exidx 0x8 0x803ad6c -.copy.table 0xc 0x803ad74 -.zero.table 0x0 0x803ad80 +.text 0x349c4 0x8006000 +_cmd_handlers 0x2e8 0x803a9c4 +_zw_protocol_cmd_handlers_lr 0x50 0x803acac +_zw_protocol_cmd_handlers 0xe8 0x803acfc +.ARM.exidx 0x8 0x803ade4 +.copy.table 0xc 0x803adec +.zero.table 0x0 0x803adf8 .stack 0x500 0x20000000 .data 0x52c 0x20000500 .bss 0xa650 0x20000a2c text_application_ram 0x0 0x2000b07c .heap 0x80 0x2000b080 -.zwave_nvm 0x0 0x803ad80 -.nvm 0xa000 0x803ad80 +.zwave_nvm 0x0 0x803adf8 +.nvm 0xa000 0x803adf8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x10978 0x0 -.debug_info 0x2974a5 0x0 -.debug_abbrev 0x1d037 0x0 -.debug_loclists 0x1e665 0x0 +.debug_info 0x298900 0x0 +.debug_abbrev 0x1d00b 0x0 +.debug_loclists 0x1e717 0x0 .debug_aranges 0x5b70 0x0 -.debug_rnglists 0x3c05 0x0 -.debug_line 0x6169f 0x0 -.debug_str 0x8c13f 0x0 -.debug_loc 0x2ef28 0x0 -.debug_ranges 0x5bb8 0x0 -Total 0x458f95 +.debug_rnglists 0x3c18 0x0 +.debug_line 0x617a1 0x0 +.debug_str 0x8c148 0x0 +.debug_loc 0x2f012 0x0 +.debug_ranges 0x5c20 0x0 +Total 0x45a75e The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217772 + 217892 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4401C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4401C_REGION_US_size.txt index 84b503b7a0..06bbcdd1b3 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4401C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4401C_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x3494c 0x8006000 -_cmd_handlers 0x2e8 0x803a94c -_zw_protocol_cmd_handlers_lr 0x50 0x803ac34 -_zw_protocol_cmd_handlers 0xe8 0x803ac84 -.ARM.exidx 0x8 0x803ad6c -.copy.table 0xc 0x803ad74 -.zero.table 0x0 0x803ad80 +.text 0x349c4 0x8006000 +_cmd_handlers 0x2e8 0x803a9c4 +_zw_protocol_cmd_handlers_lr 0x50 0x803acac +_zw_protocol_cmd_handlers 0xe8 0x803acfc +.ARM.exidx 0x8 0x803ade4 +.copy.table 0xc 0x803adec +.zero.table 0x0 0x803adf8 .stack 0x500 0x20000000 .data 0x52c 0x20000500 .bss 0xa650 0x20000a2c text_application_ram 0x0 0x2000b07c .heap 0x80 0x2000b080 -.zwave_nvm 0x0 0x803ad80 -.nvm 0xa000 0x803ad80 +.zwave_nvm 0x0 0x803adf8 +.nvm 0xa000 0x803adf8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x1b2 0x0 .debug_frame 0x10978 0x0 -.debug_info 0x2974a5 0x0 -.debug_abbrev 0x1d037 0x0 -.debug_loclists 0x1e665 0x0 +.debug_info 0x298900 0x0 +.debug_abbrev 0x1d00b 0x0 +.debug_loclists 0x1e717 0x0 .debug_aranges 0x5b70 0x0 -.debug_rnglists 0x3c05 0x0 -.debug_line 0x6169f 0x0 -.debug_str 0x8c149 0x0 -.debug_loc 0x2ef28 0x0 -.debug_ranges 0x5bb8 0x0 -Total 0x458f9f +.debug_rnglists 0x3c18 0x0 +.debug_line 0x617a1 0x0 +.debug_str 0x8c152 0x0 +.debug_loc 0x2f012 0x0 +.debug_ranges 0x5c20 0x0 +Total 0x45a768 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217772 + 217892 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 40960 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_EU_size.txt index 877bf46126..e03428bb8f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x2d174 0x0 -_cmd_handlers 0x1b8 0x2d174 -_zw_protocol_cmd_handlers 0x70 0x2d32c -_zw_protocol_cmd_handlers_lr 0x30 0x2d39c -.ARM.exidx 0x8 0x2d3cc -.copy.table 0xc 0x2d3d4 -.zero.table 0x0 0x2d3e0 +.text 0x2d1a8 0x0 +_cmd_handlers 0x1b8 0x2d1a8 +_zw_protocol_cmd_handlers 0x70 0x2d360 +_zw_protocol_cmd_handlers_lr 0x30 0x2d3d0 +.ARM.exidx 0x8 0x2d400 +.copy.table 0xc 0x2d408 +.zero.table 0x0 0x2d414 .stack 0x1000 0x20000000 .data 0x3ac 0x20001000 .bss 0xa740 0x200013ac text_application_ram 0x0 0x2000baec .heap 0x800 0x2000baf0 -.zwave_nvm 0x3000 0x2d3e0 -.nvm 0x9000 0x303e0 +.zwave_nvm 0x3000 0x2d414 +.nvm 0x9000 0x30414 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xe630 0x0 -.debug_info 0x3a4ea1 0x0 -.debug_abbrev 0x1d79e 0x0 -.debug_loclists 0x1546b 0x0 -.debug_aranges 0x5268 0x0 -.debug_rnglists 0x2d5d 0x0 -.debug_line 0x56077 0x0 -.debug_str 0x82767 0x0 -.debug_loc 0x2e0bf 0x0 -.debug_ranges 0x5068 0x0 -Total 0x53f380 +.debug_frame 0xe60c 0x0 +.debug_info 0x3a4cb9 0x0 +.debug_abbrev 0x1d79d 0x0 +.debug_loclists 0x15499 0x0 +.debug_aranges 0x5260 0x0 +.debug_rnglists 0x2d6d 0x0 +.debug_line 0x560a1 0x0 +.debug_str 0x8274f 0x0 +.debug_loc 0x2e087 0x0 +.debug_ranges 0x5080 0x0 +Total 0x53f1cf The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 186252 + 186304 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_US_LR_size.txt index b8f3eb3a82..2144ae3520 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x2d174 0x0 -_cmd_handlers 0x1b8 0x2d174 -_zw_protocol_cmd_handlers 0x70 0x2d32c -_zw_protocol_cmd_handlers_lr 0x30 0x2d39c -.ARM.exidx 0x8 0x2d3cc -.copy.table 0xc 0x2d3d4 -.zero.table 0x0 0x2d3e0 +.text 0x2d1a8 0x0 +_cmd_handlers 0x1b8 0x2d1a8 +_zw_protocol_cmd_handlers 0x70 0x2d360 +_zw_protocol_cmd_handlers_lr 0x30 0x2d3d0 +.ARM.exidx 0x8 0x2d400 +.copy.table 0xc 0x2d408 +.zero.table 0x0 0x2d414 .stack 0x1000 0x20000000 .data 0x3ac 0x20001000 .bss 0xa740 0x200013ac text_application_ram 0x0 0x2000baec .heap 0x800 0x2000baf0 -.zwave_nvm 0x3000 0x2d3e0 -.nvm 0x9000 0x303e0 +.zwave_nvm 0x3000 0x2d414 +.nvm 0x9000 0x30414 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xe630 0x0 -.debug_info 0x3a4ea1 0x0 -.debug_abbrev 0x1d79e 0x0 -.debug_loclists 0x1546b 0x0 -.debug_aranges 0x5268 0x0 -.debug_rnglists 0x2d5d 0x0 -.debug_line 0x56077 0x0 -.debug_str 0x8275d 0x0 -.debug_loc 0x2e0bf 0x0 -.debug_ranges 0x5068 0x0 -Total 0x53f376 +.debug_frame 0xe60c 0x0 +.debug_info 0x3a4cb9 0x0 +.debug_abbrev 0x1d79d 0x0 +.debug_loclists 0x15499 0x0 +.debug_aranges 0x5260 0x0 +.debug_rnglists 0x2d6d 0x0 +.debug_line 0x560a1 0x0 +.debug_str 0x82745 0x0 +.debug_loc 0x2e087 0x0 +.debug_ranges 0x5080 0x0 +Total 0x53f1c5 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 186252 + 186304 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_US_size.txt index 877bf46126..e03428bb8f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x2d174 0x0 -_cmd_handlers 0x1b8 0x2d174 -_zw_protocol_cmd_handlers 0x70 0x2d32c -_zw_protocol_cmd_handlers_lr 0x30 0x2d39c -.ARM.exidx 0x8 0x2d3cc -.copy.table 0xc 0x2d3d4 -.zero.table 0x0 0x2d3e0 +.text 0x2d1a8 0x0 +_cmd_handlers 0x1b8 0x2d1a8 +_zw_protocol_cmd_handlers 0x70 0x2d360 +_zw_protocol_cmd_handlers_lr 0x30 0x2d3d0 +.ARM.exidx 0x8 0x2d400 +.copy.table 0xc 0x2d408 +.zero.table 0x0 0x2d414 .stack 0x1000 0x20000000 .data 0x3ac 0x20001000 .bss 0xa740 0x200013ac text_application_ram 0x0 0x2000baec .heap 0x800 0x2000baf0 -.zwave_nvm 0x3000 0x2d3e0 -.nvm 0x9000 0x303e0 +.zwave_nvm 0x3000 0x2d414 +.nvm 0x9000 0x30414 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xe630 0x0 -.debug_info 0x3a4ea1 0x0 -.debug_abbrev 0x1d79e 0x0 -.debug_loclists 0x1546b 0x0 -.debug_aranges 0x5268 0x0 -.debug_rnglists 0x2d5d 0x0 -.debug_line 0x56077 0x0 -.debug_str 0x82767 0x0 -.debug_loc 0x2e0bf 0x0 -.debug_ranges 0x5068 0x0 -Total 0x53f380 +.debug_frame 0xe60c 0x0 +.debug_info 0x3a4cb9 0x0 +.debug_abbrev 0x1d79d 0x0 +.debug_loclists 0x15499 0x0 +.debug_aranges 0x5260 0x0 +.debug_rnglists 0x2d6d 0x0 +.debug_line 0x560a1 0x0 +.debug_str 0x8274f 0x0 +.debug_loc 0x2e087 0x0 +.debug_ranges 0x5080 0x0 +Total 0x53f1cf The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 186252 + 186304 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_EU_size.txt index c4e6364e7e..5776db10f1 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x33cd0 0x8006000 -_cmd_handlers 0x1b8 0x8039cd0 -_zw_protocol_cmd_handlers 0x70 0x8039e88 -_zw_protocol_cmd_handlers_lr 0x30 0x8039ef8 -.ARM.exidx 0x8 0x8039f28 -.copy.table 0xc 0x8039f30 -.zero.table 0x0 0x8039f3c +.text 0x33d28 0x8006000 +_cmd_handlers 0x1b8 0x8039d28 +_zw_protocol_cmd_handlers 0x70 0x8039ee0 +_zw_protocol_cmd_handlers_lr 0x30 0x8039f50 +.ARM.exidx 0x8 0x8039f80 +.copy.table 0xc 0x8039f88 +.zero.table 0x0 0x8039f94 .stack 0x1000 0x20000000 .data 0x528 0x20001000 .bss 0xb28c 0x20001528 text_application_ram 0x0 0x2000c7b4 .heap 0x800 0x2000c7b8 -.zwave_nvm 0x0 0x8039f3c -.nvm 0x8000 0x8039f3c +.zwave_nvm 0x0 0x8039f94 +.nvm 0x8000 0x8039f94 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11a10 0x0 -.debug_info 0x3f5124 0x0 -.debug_abbrev 0x23601 0x0 -.debug_loclists 0x29eb7 0x0 +.debug_frame 0x11a0c 0x0 +.debug_info 0x3f6474 0x0 +.debug_abbrev 0x235d5 0x0 +.debug_loclists 0x29f69 0x0 .debug_aranges 0x6240 0x0 -.debug_rnglists 0x456f 0x0 -.debug_line 0x6d518 0x0 -.debug_str 0x8ccf5 0x0 -.debug_loc 0x2cdd7 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5d3924 +.debug_rnglists 0x4582 0x0 +.debug_line 0x6d5f1 0x0 +.debug_str 0x8ccfe 0x0 +.debug_loc 0x2cd9f 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5d4e43 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214116 + 214204 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_US_LR_size.txt index f22ce29f81..3e149c161a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x33cd0 0x8006000 -_cmd_handlers 0x1b8 0x8039cd0 -_zw_protocol_cmd_handlers 0x70 0x8039e88 -_zw_protocol_cmd_handlers_lr 0x30 0x8039ef8 -.ARM.exidx 0x8 0x8039f28 -.copy.table 0xc 0x8039f30 -.zero.table 0x0 0x8039f3c +.text 0x33d28 0x8006000 +_cmd_handlers 0x1b8 0x8039d28 +_zw_protocol_cmd_handlers 0x70 0x8039ee0 +_zw_protocol_cmd_handlers_lr 0x30 0x8039f50 +.ARM.exidx 0x8 0x8039f80 +.copy.table 0xc 0x8039f88 +.zero.table 0x0 0x8039f94 .stack 0x1000 0x20000000 .data 0x528 0x20001000 .bss 0xb28c 0x20001528 text_application_ram 0x0 0x2000c7b4 .heap 0x800 0x2000c7b8 -.zwave_nvm 0x0 0x8039f3c -.nvm 0x8000 0x8039f3c +.zwave_nvm 0x0 0x8039f94 +.nvm 0x8000 0x8039f94 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11a10 0x0 -.debug_info 0x3f5124 0x0 -.debug_abbrev 0x23601 0x0 -.debug_loclists 0x29eb7 0x0 +.debug_frame 0x11a0c 0x0 +.debug_info 0x3f6474 0x0 +.debug_abbrev 0x235d5 0x0 +.debug_loclists 0x29f69 0x0 .debug_aranges 0x6240 0x0 -.debug_rnglists 0x456f 0x0 -.debug_line 0x6d518 0x0 -.debug_str 0x8cceb 0x0 -.debug_loc 0x2cdd7 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5d391a +.debug_rnglists 0x4582 0x0 +.debug_line 0x6d5f1 0x0 +.debug_str 0x8ccf4 0x0 +.debug_loc 0x2cd9f 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5d4e39 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214116 + 214204 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_US_size.txt index c4e6364e7e..5776db10f1 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x33cd0 0x8006000 -_cmd_handlers 0x1b8 0x8039cd0 -_zw_protocol_cmd_handlers 0x70 0x8039e88 -_zw_protocol_cmd_handlers_lr 0x30 0x8039ef8 -.ARM.exidx 0x8 0x8039f28 -.copy.table 0xc 0x8039f30 -.zero.table 0x0 0x8039f3c +.text 0x33d28 0x8006000 +_cmd_handlers 0x1b8 0x8039d28 +_zw_protocol_cmd_handlers 0x70 0x8039ee0 +_zw_protocol_cmd_handlers_lr 0x30 0x8039f50 +.ARM.exidx 0x8 0x8039f80 +.copy.table 0xc 0x8039f88 +.zero.table 0x0 0x8039f94 .stack 0x1000 0x20000000 .data 0x528 0x20001000 .bss 0xb28c 0x20001528 text_application_ram 0x0 0x2000c7b4 .heap 0x800 0x2000c7b8 -.zwave_nvm 0x0 0x8039f3c -.nvm 0x8000 0x8039f3c +.zwave_nvm 0x0 0x8039f94 +.nvm 0x8000 0x8039f94 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11a10 0x0 -.debug_info 0x3f5124 0x0 -.debug_abbrev 0x23601 0x0 -.debug_loclists 0x29eb7 0x0 +.debug_frame 0x11a0c 0x0 +.debug_info 0x3f6474 0x0 +.debug_abbrev 0x235d5 0x0 +.debug_loclists 0x29f69 0x0 .debug_aranges 0x6240 0x0 -.debug_rnglists 0x456f 0x0 -.debug_line 0x6d518 0x0 -.debug_str 0x8ccf5 0x0 -.debug_loc 0x2cdd7 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5d3924 +.debug_rnglists 0x4582 0x0 +.debug_line 0x6d5f1 0x0 +.debug_str 0x8ccfe 0x0 +.debug_loc 0x2cd9f 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5d4e43 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214116 + 214204 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_EU_size.txt index 4f6068707f..0a9bacff35 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x33d84 0x8006000 -_cmd_handlers 0x1b8 0x8039d84 -_zw_protocol_cmd_handlers 0x70 0x8039f3c -_zw_protocol_cmd_handlers_lr 0x30 0x8039fac -.ARM.exidx 0x8 0x8039fdc -.copy.table 0xc 0x8039fe4 -.zero.table 0x0 0x8039ff0 +.text 0x33ddc 0x8006000 +_cmd_handlers 0x1b8 0x8039ddc +_zw_protocol_cmd_handlers 0x70 0x8039f94 +_zw_protocol_cmd_handlers_lr 0x30 0x803a004 +.ARM.exidx 0x8 0x803a034 +.copy.table 0xc 0x803a03c +.zero.table 0x0 0x803a048 .stack 0x1000 0x20000000 .data 0x52c 0x20001000 .bss 0xb290 0x2000152c text_application_ram 0x0 0x2000c7bc .heap 0x800 0x2000c7c0 -.zwave_nvm 0x0 0x8039ff0 -.nvm 0x8000 0x8039ff0 +.zwave_nvm 0x0 0x803a048 +.nvm 0x8000 0x803a048 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11a40 0x0 -.debug_info 0x3f539c 0x0 -.debug_abbrev 0x23703 0x0 -.debug_loclists 0x29eb7 0x0 +.debug_frame 0x11a3c 0x0 +.debug_info 0x3f66ec 0x0 +.debug_abbrev 0x236d7 0x0 +.debug_loclists 0x29f69 0x0 .debug_aranges 0x6260 0x0 -.debug_rnglists 0x4582 0x0 -.debug_line 0x6d6f1 0x0 -.debug_str 0x8cec8 0x0 -.debug_loc 0x2cdd7 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5d4169 +.debug_rnglists 0x4595 0x0 +.debug_line 0x6d7ca 0x0 +.debug_str 0x8ced1 0x0 +.debug_loc 0x2cd9f 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5d5688 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214300 + 214388 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_US_LR_size.txt index b6e8069517..dbae8a4000 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x33d84 0x8006000 -_cmd_handlers 0x1b8 0x8039d84 -_zw_protocol_cmd_handlers 0x70 0x8039f3c -_zw_protocol_cmd_handlers_lr 0x30 0x8039fac -.ARM.exidx 0x8 0x8039fdc -.copy.table 0xc 0x8039fe4 -.zero.table 0x0 0x8039ff0 +.text 0x33ddc 0x8006000 +_cmd_handlers 0x1b8 0x8039ddc +_zw_protocol_cmd_handlers 0x70 0x8039f94 +_zw_protocol_cmd_handlers_lr 0x30 0x803a004 +.ARM.exidx 0x8 0x803a034 +.copy.table 0xc 0x803a03c +.zero.table 0x0 0x803a048 .stack 0x1000 0x20000000 .data 0x52c 0x20001000 .bss 0xb290 0x2000152c text_application_ram 0x0 0x2000c7bc .heap 0x800 0x2000c7c0 -.zwave_nvm 0x0 0x8039ff0 -.nvm 0x8000 0x8039ff0 +.zwave_nvm 0x0 0x803a048 +.nvm 0x8000 0x803a048 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11a40 0x0 -.debug_info 0x3f539c 0x0 -.debug_abbrev 0x23703 0x0 -.debug_loclists 0x29eb7 0x0 +.debug_frame 0x11a3c 0x0 +.debug_info 0x3f66ec 0x0 +.debug_abbrev 0x236d7 0x0 +.debug_loclists 0x29f69 0x0 .debug_aranges 0x6260 0x0 -.debug_rnglists 0x4582 0x0 -.debug_line 0x6d6f1 0x0 -.debug_str 0x8cebe 0x0 -.debug_loc 0x2cdd7 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5d415f +.debug_rnglists 0x4595 0x0 +.debug_line 0x6d7ca 0x0 +.debug_str 0x8cec7 0x0 +.debug_loc 0x2cd9f 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5d567e The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214300 + 214388 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_US_size.txt index 4f6068707f..0a9bacff35 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x33d84 0x8006000 -_cmd_handlers 0x1b8 0x8039d84 -_zw_protocol_cmd_handlers 0x70 0x8039f3c -_zw_protocol_cmd_handlers_lr 0x30 0x8039fac -.ARM.exidx 0x8 0x8039fdc -.copy.table 0xc 0x8039fe4 -.zero.table 0x0 0x8039ff0 +.text 0x33ddc 0x8006000 +_cmd_handlers 0x1b8 0x8039ddc +_zw_protocol_cmd_handlers 0x70 0x8039f94 +_zw_protocol_cmd_handlers_lr 0x30 0x803a004 +.ARM.exidx 0x8 0x803a034 +.copy.table 0xc 0x803a03c +.zero.table 0x0 0x803a048 .stack 0x1000 0x20000000 .data 0x52c 0x20001000 .bss 0xb290 0x2000152c text_application_ram 0x0 0x2000c7bc .heap 0x800 0x2000c7c0 -.zwave_nvm 0x0 0x8039ff0 -.nvm 0x8000 0x8039ff0 +.zwave_nvm 0x0 0x803a048 +.nvm 0x8000 0x803a048 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11a40 0x0 -.debug_info 0x3f539c 0x0 -.debug_abbrev 0x23703 0x0 -.debug_loclists 0x29eb7 0x0 +.debug_frame 0x11a3c 0x0 +.debug_info 0x3f66ec 0x0 +.debug_abbrev 0x236d7 0x0 +.debug_loclists 0x29f69 0x0 .debug_aranges 0x6260 0x0 -.debug_rnglists 0x4582 0x0 -.debug_line 0x6d6f1 0x0 -.debug_str 0x8cec8 0x0 -.debug_loc 0x2cdd7 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5d4169 +.debug_rnglists 0x4595 0x0 +.debug_line 0x6d7ca 0x0 +.debug_str 0x8ced1 0x0 +.debug_loc 0x2cd9f 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5d5688 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214300 + 214388 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_EU_size.txt index 2103c8c929..d5c900ee78 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x33868 0x8006000 -_cmd_handlers 0x1b8 0x8039868 -_zw_protocol_cmd_handlers 0x70 0x8039a20 -_zw_protocol_cmd_handlers_lr 0x30 0x8039a90 -.ARM.exidx 0x8 0x8039ac0 -.copy.table 0xc 0x8039ac8 -.zero.table 0x0 0x8039ad4 +.text 0x338c0 0x8006000 +_cmd_handlers 0x1b8 0x80398c0 +_zw_protocol_cmd_handlers 0x70 0x8039a78 +_zw_protocol_cmd_handlers_lr 0x30 0x8039ae8 +.ARM.exidx 0x8 0x8039b18 +.copy.table 0xc 0x8039b20 +.zero.table 0x0 0x8039b2c .stack 0x1000 0x20000000 .data 0x52c 0x20001000 .bss 0xb0f0 0x2000152c text_application_ram 0x0 0x2000c61c .heap 0x800 0x2000c620 -.zwave_nvm 0x0 0x8039ad4 -.nvm 0x8000 0x8039ad4 +.zwave_nvm 0x0 0x8039b2c +.nvm 0x8000 0x8039b2c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x113b0 0x0 -.debug_info 0x3ef737 0x0 -.debug_abbrev 0x22d1c 0x0 -.debug_loclists 0x2636e 0x0 +.debug_frame 0x113ac 0x0 +.debug_info 0x3f0a87 0x0 +.debug_abbrev 0x22cf0 0x0 +.debug_loclists 0x26420 0x0 .debug_aranges 0x60c0 0x0 -.debug_rnglists 0x42d8 0x0 -.debug_line 0x6a5fb 0x0 -.debug_str 0x8ca38 0x0 -.debug_loc 0x2cdc8 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5c58a9 +.debug_rnglists 0x42eb 0x0 +.debug_line 0x6a6ca 0x0 +.debug_str 0x8ca41 0x0 +.debug_loc 0x2cd90 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5c6dbe The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 212992 + 213080 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_US_LR_size.txt index 33e7633a43..386a94aacf 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x33868 0x8006000 -_cmd_handlers 0x1b8 0x8039868 -_zw_protocol_cmd_handlers 0x70 0x8039a20 -_zw_protocol_cmd_handlers_lr 0x30 0x8039a90 -.ARM.exidx 0x8 0x8039ac0 -.copy.table 0xc 0x8039ac8 -.zero.table 0x0 0x8039ad4 +.text 0x338c0 0x8006000 +_cmd_handlers 0x1b8 0x80398c0 +_zw_protocol_cmd_handlers 0x70 0x8039a78 +_zw_protocol_cmd_handlers_lr 0x30 0x8039ae8 +.ARM.exidx 0x8 0x8039b18 +.copy.table 0xc 0x8039b20 +.zero.table 0x0 0x8039b2c .stack 0x1000 0x20000000 .data 0x52c 0x20001000 .bss 0xb0f0 0x2000152c text_application_ram 0x0 0x2000c61c .heap 0x800 0x2000c620 -.zwave_nvm 0x0 0x8039ad4 -.nvm 0x8000 0x8039ad4 +.zwave_nvm 0x0 0x8039b2c +.nvm 0x8000 0x8039b2c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x113b0 0x0 -.debug_info 0x3ef737 0x0 -.debug_abbrev 0x22d1c 0x0 -.debug_loclists 0x2636e 0x0 +.debug_frame 0x113ac 0x0 +.debug_info 0x3f0a87 0x0 +.debug_abbrev 0x22cf0 0x0 +.debug_loclists 0x26420 0x0 .debug_aranges 0x60c0 0x0 -.debug_rnglists 0x42d8 0x0 -.debug_line 0x6a5fb 0x0 -.debug_str 0x8ca2e 0x0 -.debug_loc 0x2cdc8 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5c589f +.debug_rnglists 0x42eb 0x0 +.debug_line 0x6a6ca 0x0 +.debug_str 0x8ca37 0x0 +.debug_loc 0x2cd90 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5c6db4 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 212992 + 213080 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_US_size.txt index 2103c8c929..d5c900ee78 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x33868 0x8006000 -_cmd_handlers 0x1b8 0x8039868 -_zw_protocol_cmd_handlers 0x70 0x8039a20 -_zw_protocol_cmd_handlers_lr 0x30 0x8039a90 -.ARM.exidx 0x8 0x8039ac0 -.copy.table 0xc 0x8039ac8 -.zero.table 0x0 0x8039ad4 +.text 0x338c0 0x8006000 +_cmd_handlers 0x1b8 0x80398c0 +_zw_protocol_cmd_handlers 0x70 0x8039a78 +_zw_protocol_cmd_handlers_lr 0x30 0x8039ae8 +.ARM.exidx 0x8 0x8039b18 +.copy.table 0xc 0x8039b20 +.zero.table 0x0 0x8039b2c .stack 0x1000 0x20000000 .data 0x52c 0x20001000 .bss 0xb0f0 0x2000152c text_application_ram 0x0 0x2000c61c .heap 0x800 0x2000c620 -.zwave_nvm 0x0 0x8039ad4 -.nvm 0x8000 0x8039ad4 +.zwave_nvm 0x0 0x8039b2c +.nvm 0x8000 0x8039b2c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x113b0 0x0 -.debug_info 0x3ef737 0x0 -.debug_abbrev 0x22d1c 0x0 -.debug_loclists 0x2636e 0x0 +.debug_frame 0x113ac 0x0 +.debug_info 0x3f0a87 0x0 +.debug_abbrev 0x22cf0 0x0 +.debug_loclists 0x26420 0x0 .debug_aranges 0x60c0 0x0 -.debug_rnglists 0x42d8 0x0 -.debug_line 0x6a5fb 0x0 -.debug_str 0x8ca38 0x0 -.debug_loc 0x2cdc8 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5c58a9 +.debug_rnglists 0x42eb 0x0 +.debug_line 0x6a6ca 0x0 +.debug_str 0x8ca41 0x0 +.debug_loc 0x2cd90 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5c6dbe The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 212992 + 213080 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_EU_size.txt index aceacd8e71..d6d9550896 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x34094 0x8006000 -_cmd_handlers 0x1b8 0x803a094 -_zw_protocol_cmd_handlers 0x70 0x803a24c -_zw_protocol_cmd_handlers_lr 0x30 0x803a2bc -.ARM.exidx 0x8 0x803a2ec -.copy.table 0xc 0x803a2f4 -.zero.table 0x0 0x803a300 +.text 0x340ec 0x8006000 +_cmd_handlers 0x1b8 0x803a0ec +_zw_protocol_cmd_handlers 0x70 0x803a2a4 +_zw_protocol_cmd_handlers_lr 0x30 0x803a314 +.ARM.exidx 0x8 0x803a344 +.copy.table 0xc 0x803a34c +.zero.table 0x0 0x803a358 .stack 0x1000 0x20000000 .data 0x52c 0x20001000 .bss 0xb290 0x2000152c text_application_ram 0x0 0x2000c7bc .heap 0x800 0x2000c7c0 -.zwave_nvm 0x0 0x803a300 -.nvm 0x8000 0x803a300 +.zwave_nvm 0x0 0x803a358 +.nvm 0x8000 0x803a358 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11a70 0x0 -.debug_info 0x3f5d6b 0x0 -.debug_abbrev 0x237df 0x0 -.debug_loclists 0x29ec0 0x0 +.debug_frame 0x11a6c 0x0 +.debug_info 0x3f70bb 0x0 +.debug_abbrev 0x237b3 0x0 +.debug_loclists 0x29f72 0x0 .debug_aranges 0x62b0 0x0 -.debug_rnglists 0x459a 0x0 -.debug_line 0x6d5a2 0x0 -.debug_str 0x8d498 0x0 -.debug_loc 0x2cdc8 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5d5437 +.debug_rnglists 0x45ad 0x0 +.debug_line 0x6d673 0x0 +.debug_str 0x8d4a1 0x0 +.debug_loc 0x2cd90 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5d694e The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 215084 + 215172 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_US_LR_size.txt index 823330964e..35ec780025 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x34094 0x8006000 -_cmd_handlers 0x1b8 0x803a094 -_zw_protocol_cmd_handlers 0x70 0x803a24c -_zw_protocol_cmd_handlers_lr 0x30 0x803a2bc -.ARM.exidx 0x8 0x803a2ec -.copy.table 0xc 0x803a2f4 -.zero.table 0x0 0x803a300 +.text 0x340ec 0x8006000 +_cmd_handlers 0x1b8 0x803a0ec +_zw_protocol_cmd_handlers 0x70 0x803a2a4 +_zw_protocol_cmd_handlers_lr 0x30 0x803a314 +.ARM.exidx 0x8 0x803a344 +.copy.table 0xc 0x803a34c +.zero.table 0x0 0x803a358 .stack 0x1000 0x20000000 .data 0x52c 0x20001000 .bss 0xb290 0x2000152c text_application_ram 0x0 0x2000c7bc .heap 0x800 0x2000c7c0 -.zwave_nvm 0x0 0x803a300 -.nvm 0x8000 0x803a300 +.zwave_nvm 0x0 0x803a358 +.nvm 0x8000 0x803a358 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11a70 0x0 -.debug_info 0x3f5d6b 0x0 -.debug_abbrev 0x237df 0x0 -.debug_loclists 0x29ec0 0x0 +.debug_frame 0x11a6c 0x0 +.debug_info 0x3f70bb 0x0 +.debug_abbrev 0x237b3 0x0 +.debug_loclists 0x29f72 0x0 .debug_aranges 0x62b0 0x0 -.debug_rnglists 0x459a 0x0 -.debug_line 0x6d5a2 0x0 -.debug_str 0x8d48e 0x0 -.debug_loc 0x2cdc8 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5d542d +.debug_rnglists 0x45ad 0x0 +.debug_line 0x6d673 0x0 +.debug_str 0x8d497 0x0 +.debug_loc 0x2cd90 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5d6944 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 215084 + 215172 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_US_size.txt index aceacd8e71..d6d9550896 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x34094 0x8006000 -_cmd_handlers 0x1b8 0x803a094 -_zw_protocol_cmd_handlers 0x70 0x803a24c -_zw_protocol_cmd_handlers_lr 0x30 0x803a2bc -.ARM.exidx 0x8 0x803a2ec -.copy.table 0xc 0x803a2f4 -.zero.table 0x0 0x803a300 +.text 0x340ec 0x8006000 +_cmd_handlers 0x1b8 0x803a0ec +_zw_protocol_cmd_handlers 0x70 0x803a2a4 +_zw_protocol_cmd_handlers_lr 0x30 0x803a314 +.ARM.exidx 0x8 0x803a344 +.copy.table 0xc 0x803a34c +.zero.table 0x0 0x803a358 .stack 0x1000 0x20000000 .data 0x52c 0x20001000 .bss 0xb290 0x2000152c text_application_ram 0x0 0x2000c7bc .heap 0x800 0x2000c7c0 -.zwave_nvm 0x0 0x803a300 -.nvm 0x8000 0x803a300 +.zwave_nvm 0x0 0x803a358 +.nvm 0x8000 0x803a358 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11a70 0x0 -.debug_info 0x3f5d6b 0x0 -.debug_abbrev 0x237df 0x0 -.debug_loclists 0x29ec0 0x0 +.debug_frame 0x11a6c 0x0 +.debug_info 0x3f70bb 0x0 +.debug_abbrev 0x237b3 0x0 +.debug_loclists 0x29f72 0x0 .debug_aranges 0x62b0 0x0 -.debug_rnglists 0x459a 0x0 -.debug_line 0x6d5a2 0x0 -.debug_str 0x8d498 0x0 -.debug_loc 0x2cdc8 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5d5437 +.debug_rnglists 0x45ad 0x0 +.debug_line 0x6d673 0x0 +.debug_str 0x8d4a1 0x0 +.debug_loc 0x2cd90 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5d694e The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 215084 + 215172 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_EU_size.txt index 877bf46126..e03428bb8f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x2d174 0x0 -_cmd_handlers 0x1b8 0x2d174 -_zw_protocol_cmd_handlers 0x70 0x2d32c -_zw_protocol_cmd_handlers_lr 0x30 0x2d39c -.ARM.exidx 0x8 0x2d3cc -.copy.table 0xc 0x2d3d4 -.zero.table 0x0 0x2d3e0 +.text 0x2d1a8 0x0 +_cmd_handlers 0x1b8 0x2d1a8 +_zw_protocol_cmd_handlers 0x70 0x2d360 +_zw_protocol_cmd_handlers_lr 0x30 0x2d3d0 +.ARM.exidx 0x8 0x2d400 +.copy.table 0xc 0x2d408 +.zero.table 0x0 0x2d414 .stack 0x1000 0x20000000 .data 0x3ac 0x20001000 .bss 0xa740 0x200013ac text_application_ram 0x0 0x2000baec .heap 0x800 0x2000baf0 -.zwave_nvm 0x3000 0x2d3e0 -.nvm 0x9000 0x303e0 +.zwave_nvm 0x3000 0x2d414 +.nvm 0x9000 0x30414 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xe630 0x0 -.debug_info 0x3a4ea1 0x0 -.debug_abbrev 0x1d79e 0x0 -.debug_loclists 0x1546b 0x0 -.debug_aranges 0x5268 0x0 -.debug_rnglists 0x2d5d 0x0 -.debug_line 0x56077 0x0 -.debug_str 0x82767 0x0 -.debug_loc 0x2e0bf 0x0 -.debug_ranges 0x5068 0x0 -Total 0x53f380 +.debug_frame 0xe60c 0x0 +.debug_info 0x3a4cb9 0x0 +.debug_abbrev 0x1d79d 0x0 +.debug_loclists 0x15499 0x0 +.debug_aranges 0x5260 0x0 +.debug_rnglists 0x2d6d 0x0 +.debug_line 0x560a1 0x0 +.debug_str 0x8274f 0x0 +.debug_loc 0x2e087 0x0 +.debug_ranges 0x5080 0x0 +Total 0x53f1cf The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 186252 + 186304 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_US_LR_size.txt index b8f3eb3a82..2144ae3520 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x2d174 0x0 -_cmd_handlers 0x1b8 0x2d174 -_zw_protocol_cmd_handlers 0x70 0x2d32c -_zw_protocol_cmd_handlers_lr 0x30 0x2d39c -.ARM.exidx 0x8 0x2d3cc -.copy.table 0xc 0x2d3d4 -.zero.table 0x0 0x2d3e0 +.text 0x2d1a8 0x0 +_cmd_handlers 0x1b8 0x2d1a8 +_zw_protocol_cmd_handlers 0x70 0x2d360 +_zw_protocol_cmd_handlers_lr 0x30 0x2d3d0 +.ARM.exidx 0x8 0x2d400 +.copy.table 0xc 0x2d408 +.zero.table 0x0 0x2d414 .stack 0x1000 0x20000000 .data 0x3ac 0x20001000 .bss 0xa740 0x200013ac text_application_ram 0x0 0x2000baec .heap 0x800 0x2000baf0 -.zwave_nvm 0x3000 0x2d3e0 -.nvm 0x9000 0x303e0 +.zwave_nvm 0x3000 0x2d414 +.nvm 0x9000 0x30414 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xe630 0x0 -.debug_info 0x3a4ea1 0x0 -.debug_abbrev 0x1d79e 0x0 -.debug_loclists 0x1546b 0x0 -.debug_aranges 0x5268 0x0 -.debug_rnglists 0x2d5d 0x0 -.debug_line 0x56077 0x0 -.debug_str 0x8275d 0x0 -.debug_loc 0x2e0bf 0x0 -.debug_ranges 0x5068 0x0 -Total 0x53f376 +.debug_frame 0xe60c 0x0 +.debug_info 0x3a4cb9 0x0 +.debug_abbrev 0x1d79d 0x0 +.debug_loclists 0x15499 0x0 +.debug_aranges 0x5260 0x0 +.debug_rnglists 0x2d6d 0x0 +.debug_line 0x560a1 0x0 +.debug_str 0x82745 0x0 +.debug_loc 0x2e087 0x0 +.debug_ranges 0x5080 0x0 +Total 0x53f1c5 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 186252 + 186304 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_US_size.txt index 877bf46126..e03428bb8f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x2d174 0x0 -_cmd_handlers 0x1b8 0x2d174 -_zw_protocol_cmd_handlers 0x70 0x2d32c -_zw_protocol_cmd_handlers_lr 0x30 0x2d39c -.ARM.exidx 0x8 0x2d3cc -.copy.table 0xc 0x2d3d4 -.zero.table 0x0 0x2d3e0 +.text 0x2d1a8 0x0 +_cmd_handlers 0x1b8 0x2d1a8 +_zw_protocol_cmd_handlers 0x70 0x2d360 +_zw_protocol_cmd_handlers_lr 0x30 0x2d3d0 +.ARM.exidx 0x8 0x2d400 +.copy.table 0xc 0x2d408 +.zero.table 0x0 0x2d414 .stack 0x1000 0x20000000 .data 0x3ac 0x20001000 .bss 0xa740 0x200013ac text_application_ram 0x0 0x2000baec .heap 0x800 0x2000baf0 -.zwave_nvm 0x3000 0x2d3e0 -.nvm 0x9000 0x303e0 +.zwave_nvm 0x3000 0x2d414 +.nvm 0x9000 0x30414 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xe630 0x0 -.debug_info 0x3a4ea1 0x0 -.debug_abbrev 0x1d79e 0x0 -.debug_loclists 0x1546b 0x0 -.debug_aranges 0x5268 0x0 -.debug_rnglists 0x2d5d 0x0 -.debug_line 0x56077 0x0 -.debug_str 0x82767 0x0 -.debug_loc 0x2e0bf 0x0 -.debug_ranges 0x5068 0x0 -Total 0x53f380 +.debug_frame 0xe60c 0x0 +.debug_info 0x3a4cb9 0x0 +.debug_abbrev 0x1d79d 0x0 +.debug_loclists 0x15499 0x0 +.debug_aranges 0x5260 0x0 +.debug_rnglists 0x2d6d 0x0 +.debug_line 0x560a1 0x0 +.debug_str 0x8274f 0x0 +.debug_loc 0x2e087 0x0 +.debug_ranges 0x5080 0x0 +Total 0x53f1cf The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 186252 + 186304 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4209A_REGION_US_LR_size.txt index 44909d64c3..9f30532721 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4209A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x2d06c 0x0 -_cmd_handlers 0x1b8 0x2d06c -_zw_protocol_cmd_handlers 0x70 0x2d224 -_zw_protocol_cmd_handlers_lr 0x30 0x2d294 -.ARM.exidx 0x8 0x2d2c4 -.copy.table 0xc 0x2d2cc -.zero.table 0x0 0x2d2d8 +.text 0x2d0a0 0x0 +_cmd_handlers 0x1b8 0x2d0a0 +_zw_protocol_cmd_handlers 0x70 0x2d258 +_zw_protocol_cmd_handlers_lr 0x30 0x2d2c8 +.ARM.exidx 0x8 0x2d2f8 +.copy.table 0xc 0x2d300 +.zero.table 0x0 0x2d30c .stack 0x1000 0x20000000 .data 0x3a8 0x20001000 .bss 0xa720 0x200013a8 text_application_ram 0x0 0x2000bac8 .heap 0x800 0x2000bac8 -.zwave_nvm 0x3000 0x2d2d8 -.nvm 0x9000 0x302d8 +.zwave_nvm 0x3000 0x2d30c +.nvm 0x9000 0x3030c .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xe638 0x0 -.debug_info 0x3a5346 0x0 -.debug_abbrev 0x1d9fd 0x0 -.debug_loclists 0x1568f 0x0 -.debug_aranges 0x5250 0x0 -.debug_rnglists 0x2d83 0x0 -.debug_line 0x566f9 0x0 -.debug_str 0x82240 0x0 -.debug_loc 0x2e0bf 0x0 -.debug_ranges 0x5068 0x0 -Total 0x53fced +.debug_frame 0xe614 0x0 +.debug_info 0x3a515e 0x0 +.debug_abbrev 0x1d9fc 0x0 +.debug_loclists 0x156bd 0x0 +.debug_aranges 0x5248 0x0 +.debug_rnglists 0x2d93 0x0 +.debug_line 0x5672d 0x0 +.debug_str 0x82228 0x0 +.debug_loc 0x2e087 0x0 +.debug_ranges 0x5080 0x0 +Total 0x53fb46 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 185984 + 186036 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4210A_REGION_US_LR_size.txt index ba23dacb4b..c881e7d5b3 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4210A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x33dc4 0x8006000 -_cmd_handlers 0x1b8 0x8039dc4 -_zw_protocol_cmd_handlers 0x70 0x8039f7c -_zw_protocol_cmd_handlers_lr 0x30 0x8039fec -.ARM.exidx 0x8 0x803a01c -.copy.table 0xc 0x803a024 -.zero.table 0x0 0x803a030 +.text 0x33dfc 0x8006000 +_cmd_handlers 0x1b8 0x8039dfc +_zw_protocol_cmd_handlers 0x70 0x8039fb4 +_zw_protocol_cmd_handlers_lr 0x30 0x803a024 +.ARM.exidx 0x8 0x803a054 +.copy.table 0xc 0x803a05c +.zero.table 0x0 0x803a068 .stack 0x1000 0x20000000 .data 0x52c 0x20001000 .bss 0xb290 0x2000152c text_application_ram 0x0 0x2000c7bc .heap 0x800 0x2000c7c0 -.zwave_nvm 0x0 0x803a030 -.nvm 0x8000 0x803a030 +.zwave_nvm 0x0 0x803a068 +.nvm 0x8000 0x803a068 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11a48 0x0 -.debug_info 0x3f5366 0x0 -.debug_abbrev 0x23703 0x0 -.debug_loclists 0x29eb7 0x0 +.debug_frame 0x11a44 0x0 +.debug_info 0x3f66b6 0x0 +.debug_abbrev 0x236d7 0x0 +.debug_loclists 0x29f69 0x0 .debug_aranges 0x6260 0x0 -.debug_rnglists 0x4582 0x0 -.debug_line 0x6d6c8 0x0 -.debug_str 0x8cebe 0x0 -.debug_loc 0x2cdbc 0x0 -.debug_ranges 0x4f88 0x0 -Total 0x5d4115 +.debug_rnglists 0x4595 0x0 +.debug_line 0x6d7a1 0x0 +.debug_str 0x8cec7 0x0 +.debug_loc 0x2cd84 0x0 +.debug_ranges 0x4fc0 0x0 +Total 0x5d5614 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214364 + 214420 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400B_REGION_EU_size.txt index 55ff78870f..32528a2fe3 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400B_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x34924 0x8006000 -_cmd_handlers 0x1b8 0x803a924 -_zw_protocol_cmd_handlers 0x70 0x803aadc -_zw_protocol_cmd_handlers_lr 0x30 0x803ab4c -.ARM.exidx 0x8 0x803ab7c -.copy.table 0xc 0x803ab84 -.zero.table 0x0 0x803ab90 +.text 0x3497c 0x8006000 +_cmd_handlers 0x1b8 0x803a97c +_zw_protocol_cmd_handlers 0x70 0x803ab34 +_zw_protocol_cmd_handlers_lr 0x30 0x803aba4 +.ARM.exidx 0x8 0x803abd4 +.copy.table 0xc 0x803abdc +.zero.table 0x0 0x803abe8 .stack 0x1000 0x20000000 .data 0x528 0x20001000 .bss 0xb1f8 0x20001528 text_application_ram 0x0 0x2000c720 .heap 0x800 0x2000c720 -.zwave_nvm 0x0 0x803ab90 -.nvm 0x8000 0x803ab90 +.zwave_nvm 0x0 0x803abe8 +.nvm 0x8000 0x803abe8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b0c 0x0 -.debug_info 0x3f9d0d 0x0 -.debug_abbrev 0x23a4a 0x0 -.debug_loclists 0x2a3e6 0x0 +.debug_frame 0x11b08 0x0 +.debug_info 0x3fb061 0x0 +.debug_abbrev 0x23a1e 0x0 +.debug_loclists 0x2a498 0x0 .debug_aranges 0x62e0 0x0 -.debug_rnglists 0x45d7 0x0 -.debug_line 0x6da8d 0x0 -.debug_str 0x8e757 0x0 -.debug_loc 0x2ccc4 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5dbb0d +.debug_rnglists 0x45ea 0x0 +.debug_line 0x6db66 0x0 +.debug_str 0x8e760 0x0 +.debug_loc 0x2cc8c 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5dd030 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217272 + 217360 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400B_REGION_US_LR_size.txt index f7b3b6fc16..8da2345e6a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400B_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x34924 0x8006000 -_cmd_handlers 0x1b8 0x803a924 -_zw_protocol_cmd_handlers 0x70 0x803aadc -_zw_protocol_cmd_handlers_lr 0x30 0x803ab4c -.ARM.exidx 0x8 0x803ab7c -.copy.table 0xc 0x803ab84 -.zero.table 0x0 0x803ab90 +.text 0x3497c 0x8006000 +_cmd_handlers 0x1b8 0x803a97c +_zw_protocol_cmd_handlers 0x70 0x803ab34 +_zw_protocol_cmd_handlers_lr 0x30 0x803aba4 +.ARM.exidx 0x8 0x803abd4 +.copy.table 0xc 0x803abdc +.zero.table 0x0 0x803abe8 .stack 0x1000 0x20000000 .data 0x528 0x20001000 .bss 0xb1f8 0x20001528 text_application_ram 0x0 0x2000c720 .heap 0x800 0x2000c720 -.zwave_nvm 0x0 0x803ab90 -.nvm 0x8000 0x803ab90 +.zwave_nvm 0x0 0x803abe8 +.nvm 0x8000 0x803abe8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b0c 0x0 -.debug_info 0x3f9d0d 0x0 -.debug_abbrev 0x23a4a 0x0 -.debug_loclists 0x2a3e6 0x0 +.debug_frame 0x11b08 0x0 +.debug_info 0x3fb061 0x0 +.debug_abbrev 0x23a1e 0x0 +.debug_loclists 0x2a498 0x0 .debug_aranges 0x62e0 0x0 -.debug_rnglists 0x45d7 0x0 -.debug_line 0x6da8d 0x0 -.debug_str 0x8e74d 0x0 -.debug_loc 0x2ccc4 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5dbb03 +.debug_rnglists 0x45ea 0x0 +.debug_line 0x6db66 0x0 +.debug_str 0x8e756 0x0 +.debug_loc 0x2cc8c 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5dd026 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217272 + 217360 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400B_REGION_US_size.txt index 55ff78870f..32528a2fe3 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400B_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x34924 0x8006000 -_cmd_handlers 0x1b8 0x803a924 -_zw_protocol_cmd_handlers 0x70 0x803aadc -_zw_protocol_cmd_handlers_lr 0x30 0x803ab4c -.ARM.exidx 0x8 0x803ab7c -.copy.table 0xc 0x803ab84 -.zero.table 0x0 0x803ab90 +.text 0x3497c 0x8006000 +_cmd_handlers 0x1b8 0x803a97c +_zw_protocol_cmd_handlers 0x70 0x803ab34 +_zw_protocol_cmd_handlers_lr 0x30 0x803aba4 +.ARM.exidx 0x8 0x803abd4 +.copy.table 0xc 0x803abdc +.zero.table 0x0 0x803abe8 .stack 0x1000 0x20000000 .data 0x528 0x20001000 .bss 0xb1f8 0x20001528 text_application_ram 0x0 0x2000c720 .heap 0x800 0x2000c720 -.zwave_nvm 0x0 0x803ab90 -.nvm 0x8000 0x803ab90 +.zwave_nvm 0x0 0x803abe8 +.nvm 0x8000 0x803abe8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b0c 0x0 -.debug_info 0x3f9d0d 0x0 -.debug_abbrev 0x23a4a 0x0 -.debug_loclists 0x2a3e6 0x0 +.debug_frame 0x11b08 0x0 +.debug_info 0x3fb061 0x0 +.debug_abbrev 0x23a1e 0x0 +.debug_loclists 0x2a498 0x0 .debug_aranges 0x62e0 0x0 -.debug_rnglists 0x45d7 0x0 -.debug_line 0x6da8d 0x0 -.debug_str 0x8e757 0x0 -.debug_loc 0x2ccc4 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5dbb0d +.debug_rnglists 0x45ea 0x0 +.debug_line 0x6db66 0x0 +.debug_str 0x8e760 0x0 +.debug_loc 0x2cc8c 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5dd030 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217272 + 217360 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400C_REGION_EU_size.txt index 9066dff3cc..e4d03f11e5 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400C_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x34924 0x8006000 -_cmd_handlers 0x1b8 0x803a924 -_zw_protocol_cmd_handlers 0x70 0x803aadc -_zw_protocol_cmd_handlers_lr 0x30 0x803ab4c -.ARM.exidx 0x8 0x803ab7c -.copy.table 0xc 0x803ab84 -.zero.table 0x0 0x803ab90 +.text 0x3497c 0x8006000 +_cmd_handlers 0x1b8 0x803a97c +_zw_protocol_cmd_handlers 0x70 0x803ab34 +_zw_protocol_cmd_handlers_lr 0x30 0x803aba4 +.ARM.exidx 0x8 0x803abd4 +.copy.table 0xc 0x803abdc +.zero.table 0x0 0x803abe8 .stack 0x1000 0x20000000 .data 0x528 0x20001000 .bss 0xb1f8 0x20001528 text_application_ram 0x0 0x2000c720 .heap 0x800 0x2000c720 -.zwave_nvm 0x0 0x803ab90 -.nvm 0x8000 0x803ab90 +.zwave_nvm 0x0 0x803abe8 +.nvm 0x8000 0x803abe8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b20 0x0 -.debug_info 0x3f9c9c 0x0 -.debug_abbrev 0x23a54 0x0 -.debug_loclists 0x2a3b2 0x0 +.debug_frame 0x11b1c 0x0 +.debug_info 0x3faff0 0x0 +.debug_abbrev 0x23a28 0x0 +.debug_loclists 0x2a464 0x0 .debug_aranges 0x62e8 0x0 -.debug_rnglists 0x4600 0x0 -.debug_line 0x6da82 0x0 -.debug_str 0x8e757 0x0 -.debug_loc 0x2ccc4 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5dbaac +.debug_rnglists 0x4613 0x0 +.debug_line 0x6db5b 0x0 +.debug_str 0x8e760 0x0 +.debug_loc 0x2cc8c 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5dcfcf The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217272 + 217360 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400C_REGION_US_LR_size.txt index bc522ddd53..21eab7fab1 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400C_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x34924 0x8006000 -_cmd_handlers 0x1b8 0x803a924 -_zw_protocol_cmd_handlers 0x70 0x803aadc -_zw_protocol_cmd_handlers_lr 0x30 0x803ab4c -.ARM.exidx 0x8 0x803ab7c -.copy.table 0xc 0x803ab84 -.zero.table 0x0 0x803ab90 +.text 0x3497c 0x8006000 +_cmd_handlers 0x1b8 0x803a97c +_zw_protocol_cmd_handlers 0x70 0x803ab34 +_zw_protocol_cmd_handlers_lr 0x30 0x803aba4 +.ARM.exidx 0x8 0x803abd4 +.copy.table 0xc 0x803abdc +.zero.table 0x0 0x803abe8 .stack 0x1000 0x20000000 .data 0x528 0x20001000 .bss 0xb1f8 0x20001528 text_application_ram 0x0 0x2000c720 .heap 0x800 0x2000c720 -.zwave_nvm 0x0 0x803ab90 -.nvm 0x8000 0x803ab90 +.zwave_nvm 0x0 0x803abe8 +.nvm 0x8000 0x803abe8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b20 0x0 -.debug_info 0x3f9c9c 0x0 -.debug_abbrev 0x23a54 0x0 -.debug_loclists 0x2a3b2 0x0 +.debug_frame 0x11b1c 0x0 +.debug_info 0x3faff0 0x0 +.debug_abbrev 0x23a28 0x0 +.debug_loclists 0x2a464 0x0 .debug_aranges 0x62e8 0x0 -.debug_rnglists 0x4600 0x0 -.debug_line 0x6da82 0x0 -.debug_str 0x8e74d 0x0 -.debug_loc 0x2ccc4 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5dbaa2 +.debug_rnglists 0x4613 0x0 +.debug_line 0x6db5b 0x0 +.debug_str 0x8e756 0x0 +.debug_loc 0x2cc8c 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5dcfc5 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217272 + 217360 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400C_REGION_US_size.txt index 9066dff3cc..e4d03f11e5 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4400C_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x34924 0x8006000 -_cmd_handlers 0x1b8 0x803a924 -_zw_protocol_cmd_handlers 0x70 0x803aadc -_zw_protocol_cmd_handlers_lr 0x30 0x803ab4c -.ARM.exidx 0x8 0x803ab7c -.copy.table 0xc 0x803ab84 -.zero.table 0x0 0x803ab90 +.text 0x3497c 0x8006000 +_cmd_handlers 0x1b8 0x803a97c +_zw_protocol_cmd_handlers 0x70 0x803ab34 +_zw_protocol_cmd_handlers_lr 0x30 0x803aba4 +.ARM.exidx 0x8 0x803abd4 +.copy.table 0xc 0x803abdc +.zero.table 0x0 0x803abe8 .stack 0x1000 0x20000000 .data 0x528 0x20001000 .bss 0xb1f8 0x20001528 text_application_ram 0x0 0x2000c720 .heap 0x800 0x2000c720 -.zwave_nvm 0x0 0x803ab90 -.nvm 0x8000 0x803ab90 +.zwave_nvm 0x0 0x803abe8 +.nvm 0x8000 0x803abe8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b20 0x0 -.debug_info 0x3f9c9c 0x0 -.debug_abbrev 0x23a54 0x0 -.debug_loclists 0x2a3b2 0x0 +.debug_frame 0x11b1c 0x0 +.debug_info 0x3faff0 0x0 +.debug_abbrev 0x23a28 0x0 +.debug_loclists 0x2a464 0x0 .debug_aranges 0x62e8 0x0 -.debug_rnglists 0x4600 0x0 -.debug_line 0x6da82 0x0 -.debug_str 0x8e757 0x0 -.debug_loc 0x2ccc4 0x0 -.debug_ranges 0x4fa0 0x0 -Total 0x5dbaac +.debug_rnglists 0x4613 0x0 +.debug_line 0x6db5b 0x0 +.debug_str 0x8e760 0x0 +.debug_loc 0x2cc8c 0x0 +.debug_ranges 0x4fd8 0x0 +Total 0x5dcfcf The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217272 + 217360 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4401B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4401B_REGION_US_LR_size.txt index f3a41591a4..bc1eb677f3 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4401B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4401B_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x34944 0x8006000 -_cmd_handlers 0x1b8 0x803a944 -_zw_protocol_cmd_handlers 0x70 0x803aafc -_zw_protocol_cmd_handlers_lr 0x30 0x803ab6c -.ARM.exidx 0x8 0x803ab9c -.copy.table 0xc 0x803aba4 -.zero.table 0x0 0x803abb0 +.text 0x3499c 0x8006000 +_cmd_handlers 0x1b8 0x803a99c +_zw_protocol_cmd_handlers 0x70 0x803ab54 +_zw_protocol_cmd_handlers_lr 0x30 0x803abc4 +.ARM.exidx 0x8 0x803abf4 +.copy.table 0xc 0x803abfc +.zero.table 0x0 0x803ac08 .stack 0x1000 0x20000000 .data 0x528 0x20001000 .bss 0xb1f8 0x20001528 text_application_ram 0x0 0x2000c720 .heap 0x800 0x2000c720 -.zwave_nvm 0x0 0x803abb0 -.nvm 0x8000 0x803abb0 +.zwave_nvm 0x0 0x803ac08 +.nvm 0x8000 0x803ac08 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b14 0x0 -.debug_info 0x3f9cd7 0x0 -.debug_abbrev 0x23a4a 0x0 -.debug_loclists 0x2a3e6 0x0 +.debug_frame 0x11b10 0x0 +.debug_info 0x3fb02b 0x0 +.debug_abbrev 0x23a1e 0x0 +.debug_loclists 0x2a498 0x0 .debug_aranges 0x62e0 0x0 -.debug_rnglists 0x45d7 0x0 -.debug_line 0x6da64 0x0 -.debug_str 0x8e74d 0x0 -.debug_loc 0x2cca9 0x0 -.debug_ranges 0x4f88 0x0 -Total 0x5dba99 +.debug_rnglists 0x45ea 0x0 +.debug_line 0x6db3d 0x0 +.debug_str 0x8e756 0x0 +.debug_loc 0x2cc71 0x0 +.debug_ranges 0x4fc0 0x0 +Total 0x5dcfbc The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217304 + 217392 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4401C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4401C_REGION_EU_size.txt index 480105c848..bea2a412c9 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4401C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4401C_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x34944 0x8006000 -_cmd_handlers 0x1b8 0x803a944 -_zw_protocol_cmd_handlers 0x70 0x803aafc -_zw_protocol_cmd_handlers_lr 0x30 0x803ab6c -.ARM.exidx 0x8 0x803ab9c -.copy.table 0xc 0x803aba4 -.zero.table 0x0 0x803abb0 +.text 0x3499c 0x8006000 +_cmd_handlers 0x1b8 0x803a99c +_zw_protocol_cmd_handlers 0x70 0x803ab54 +_zw_protocol_cmd_handlers_lr 0x30 0x803abc4 +.ARM.exidx 0x8 0x803abf4 +.copy.table 0xc 0x803abfc +.zero.table 0x0 0x803ac08 .stack 0x1000 0x20000000 .data 0x528 0x20001000 .bss 0xb1f8 0x20001528 text_application_ram 0x0 0x2000c720 .heap 0x800 0x2000c720 -.zwave_nvm 0x0 0x803abb0 -.nvm 0x8000 0x803abb0 +.zwave_nvm 0x0 0x803ac08 +.nvm 0x8000 0x803ac08 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b28 0x0 -.debug_info 0x3f9c66 0x0 -.debug_abbrev 0x23a54 0x0 -.debug_loclists 0x2a3b2 0x0 +.debug_frame 0x11b24 0x0 +.debug_info 0x3fafba 0x0 +.debug_abbrev 0x23a28 0x0 +.debug_loclists 0x2a464 0x0 .debug_aranges 0x62e8 0x0 -.debug_rnglists 0x4600 0x0 -.debug_line 0x6da59 0x0 -.debug_str 0x8e757 0x0 -.debug_loc 0x2cca9 0x0 -.debug_ranges 0x4f88 0x0 -Total 0x5dba42 +.debug_rnglists 0x4613 0x0 +.debug_line 0x6db32 0x0 +.debug_str 0x8e760 0x0 +.debug_loc 0x2cc71 0x0 +.debug_ranges 0x4fc0 0x0 +Total 0x5dcf65 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217304 + 217392 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4401C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4401C_REGION_US_LR_size.txt index 5375e6f7cb..9d5929b035 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4401C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4401C_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x34944 0x8006000 -_cmd_handlers 0x1b8 0x803a944 -_zw_protocol_cmd_handlers 0x70 0x803aafc -_zw_protocol_cmd_handlers_lr 0x30 0x803ab6c -.ARM.exidx 0x8 0x803ab9c -.copy.table 0xc 0x803aba4 -.zero.table 0x0 0x803abb0 +.text 0x3499c 0x8006000 +_cmd_handlers 0x1b8 0x803a99c +_zw_protocol_cmd_handlers 0x70 0x803ab54 +_zw_protocol_cmd_handlers_lr 0x30 0x803abc4 +.ARM.exidx 0x8 0x803abf4 +.copy.table 0xc 0x803abfc +.zero.table 0x0 0x803ac08 .stack 0x1000 0x20000000 .data 0x528 0x20001000 .bss 0xb1f8 0x20001528 text_application_ram 0x0 0x2000c720 .heap 0x800 0x2000c720 -.zwave_nvm 0x0 0x803abb0 -.nvm 0x8000 0x803abb0 +.zwave_nvm 0x0 0x803ac08 +.nvm 0x8000 0x803ac08 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b28 0x0 -.debug_info 0x3f9c66 0x0 -.debug_abbrev 0x23a54 0x0 -.debug_loclists 0x2a3b2 0x0 +.debug_frame 0x11b24 0x0 +.debug_info 0x3fafba 0x0 +.debug_abbrev 0x23a28 0x0 +.debug_loclists 0x2a464 0x0 .debug_aranges 0x62e8 0x0 -.debug_rnglists 0x4600 0x0 -.debug_line 0x6da59 0x0 -.debug_str 0x8e74d 0x0 -.debug_loc 0x2cca9 0x0 -.debug_ranges 0x4f88 0x0 -Total 0x5dba38 +.debug_rnglists 0x4613 0x0 +.debug_line 0x6db32 0x0 +.debug_str 0x8e756 0x0 +.debug_loc 0x2cc71 0x0 +.debug_ranges 0x4fc0 0x0 +Total 0x5dcf5b The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217304 + 217392 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4401C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4401C_REGION_US_size.txt index 480105c848..bea2a412c9 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4401C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4401C_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x34944 0x8006000 -_cmd_handlers 0x1b8 0x803a944 -_zw_protocol_cmd_handlers 0x70 0x803aafc -_zw_protocol_cmd_handlers_lr 0x30 0x803ab6c -.ARM.exidx 0x8 0x803ab9c -.copy.table 0xc 0x803aba4 -.zero.table 0x0 0x803abb0 +.text 0x3499c 0x8006000 +_cmd_handlers 0x1b8 0x803a99c +_zw_protocol_cmd_handlers 0x70 0x803ab54 +_zw_protocol_cmd_handlers_lr 0x30 0x803abc4 +.ARM.exidx 0x8 0x803abf4 +.copy.table 0xc 0x803abfc +.zero.table 0x0 0x803ac08 .stack 0x1000 0x20000000 .data 0x528 0x20001000 .bss 0xb1f8 0x20001528 text_application_ram 0x0 0x2000c720 .heap 0x800 0x2000c720 -.zwave_nvm 0x0 0x803abb0 -.nvm 0x8000 0x803abb0 +.zwave_nvm 0x0 0x803ac08 +.nvm 0x8000 0x803ac08 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b28 0x0 -.debug_info 0x3f9c66 0x0 -.debug_abbrev 0x23a54 0x0 -.debug_loclists 0x2a3b2 0x0 +.debug_frame 0x11b24 0x0 +.debug_info 0x3fafba 0x0 +.debug_abbrev 0x23a28 0x0 +.debug_loclists 0x2a464 0x0 .debug_aranges 0x62e8 0x0 -.debug_rnglists 0x4600 0x0 -.debug_line 0x6da59 0x0 -.debug_str 0x8e757 0x0 -.debug_loc 0x2cca9 0x0 -.debug_ranges 0x4f88 0x0 -Total 0x5dba42 +.debug_rnglists 0x4613 0x0 +.debug_line 0x6db32 0x0 +.debug_str 0x8e760 0x0 +.debug_loc 0x2cc71 0x0 +.debug_ranges 0x4fc0 0x0 +Total 0x5dcf65 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217304 + 217392 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD2603A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD2603A_REGION_US_LR_size.txt index e43fefaf0f..6a84636f50 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD2603A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD2603A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer.out : section size addr -.text 0x31078 0x8006000 -_zw_protocol_cmd_handlers 0x70 0x8037078 -_zw_protocol_cmd_handlers_lr 0x30 0x80370e8 -.ARM.exidx 0x8 0x8037118 -.copy.table 0xc 0x8037120 -.zero.table 0x0 0x803712c +.text 0x310d0 0x8006000 +_zw_protocol_cmd_handlers 0x70 0x80370d0 +_zw_protocol_cmd_handlers_lr 0x30 0x8037140 +.ARM.exidx 0x8 0x8037170 +.copy.table 0xc 0x8037178 +.zero.table 0x0 0x8037184 .stack 0x1000 0x20000000 .data 0x550 0x20001000 .bss 0xa6fc 0x20001550 text_application_ram 0x0 0x2000bc4c .heap 0x800 0x2000bc50 -.zwave_nvm 0x0 0x803712c -.nvm 0x8000 0x803712c +.zwave_nvm 0x0 0x8037184 +.nvm 0x8000 0x8037184 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1051c 0x0 -.debug_info 0x31748d 0x0 -.debug_abbrev 0x20a41 0x0 -.debug_loclists 0x264e5 0x0 +.debug_frame 0x10518 0x0 +.debug_info 0x318c5a 0x0 +.debug_abbrev 0x20a48 0x0 +.debug_loclists 0x26597 0x0 .debug_aranges 0x5b88 0x0 -.debug_rnglists 0x3d36 0x0 -.debug_line 0x65cf2 0x0 -.debug_str 0x89e4b 0x0 -.debug_loc 0x2cdd5 0x0 -.debug_ranges 0x4f70 0x0 -Total 0x4df29c +.debug_rnglists 0x3d49 0x0 +.debug_line 0x65e0d 0x0 +.debug_str 0x89e6b 0x0 +.debug_loc 0x2cd9d 0x0 +.debug_ranges 0x4fa8 0x0 +Total 0x4e0cc4 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 202364 + 202452 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD2705A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD2705A_REGION_US_LR_size.txt index 1d43681ed9..d37607b77f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD2705A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD2705A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer.out : section size addr -.text 0x31598 0x8006000 -_zw_protocol_cmd_handlers 0x70 0x8037598 -_zw_protocol_cmd_handlers_lr 0x30 0x8037608 -.ARM.exidx 0x8 0x8037638 -.copy.table 0xc 0x8037640 -.zero.table 0x0 0x803764c +.text 0x315f0 0x8006000 +_zw_protocol_cmd_handlers 0x70 0x80375f0 +_zw_protocol_cmd_handlers_lr 0x30 0x8037660 +.ARM.exidx 0x8 0x8037690 +.copy.table 0xc 0x8037698 +.zero.table 0x0 0x80376a4 .stack 0x1000 0x20000000 .data 0x54c 0x20001000 .bss 0xa668 0x2000154c text_application_ram 0x0 0x2000bbb4 .heap 0x800 0x2000bbb8 -.zwave_nvm 0x0 0x803764c -.nvm 0x8000 0x803764c +.zwave_nvm 0x0 0x80376a4 +.nvm 0x8000 0x80376a4 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x10524 0x0 -.debug_info 0x317fb7 0x0 -.debug_abbrev 0x20812 0x0 -.debug_loclists 0x267a9 0x0 +.debug_frame 0x10520 0x0 +.debug_info 0x319788 0x0 +.debug_abbrev 0x20819 0x0 +.debug_loclists 0x2685b 0x0 .debug_aranges 0x5b60 0x0 -.debug_rnglists 0x3cfa 0x0 -.debug_line 0x65922 0x0 -.debug_str 0x8ae74 0x0 -.debug_loc 0x2ccc2 0x0 -.debug_ranges 0x4f70 0x0 -Total 0x4e0dcd +.debug_rnglists 0x3d0d 0x0 +.debug_line 0x65a45 0x0 +.debug_str 0x8ae94 0x0 +.debug_loc 0x2cc8a 0x0 +.debug_ranges 0x4fa8 0x0 +Total 0x4e2801 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 203672 + 203760 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD4204D_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD4204D_REGION_US_LR_size.txt index ef1a38dc82..ddb3328c2c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD4204D_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD4204D_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer.out : section size addr -.text 0x30dec 0x8006000 -_zw_protocol_cmd_handlers 0x70 0x8036dec -_zw_protocol_cmd_handlers_lr 0x30 0x8036e5c -.ARM.exidx 0x8 0x8036e8c -.copy.table 0xc 0x8036e94 -.zero.table 0x0 0x8036ea0 +.text 0x30e44 0x8006000 +_zw_protocol_cmd_handlers 0x70 0x8036e44 +_zw_protocol_cmd_handlers_lr 0x30 0x8036eb4 +.ARM.exidx 0x8 0x8036ee4 +.copy.table 0xc 0x8036eec +.zero.table 0x0 0x8036ef8 .stack 0x1000 0x20000000 .data 0x550 0x20001000 .bss 0xa6f8 0x20001550 text_application_ram 0x0 0x2000bc48 .heap 0x800 0x2000bc48 -.zwave_nvm 0x0 0x8036ea0 -.nvm 0x8000 0x8036ea0 +.zwave_nvm 0x0 0x8036ef8 +.nvm 0x8000 0x8036ef8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x10608 0x0 -.debug_info 0x3190ad 0x0 -.debug_abbrev 0x20d74 0x0 -.debug_loclists 0x267b7 0x0 +.debug_frame 0x10604 0x0 +.debug_info 0x31a87a 0x0 +.debug_abbrev 0x20d7b 0x0 +.debug_loclists 0x26869 0x0 .debug_aranges 0x5b98 0x0 -.debug_rnglists 0x3d7a 0x0 -.debug_line 0x6673f 0x0 -.debug_str 0x89b22 0x0 -.debug_loc 0x2cdd5 0x0 -.debug_ranges 0x4f70 0x0 -Total 0x4e1a95 +.debug_rnglists 0x3d8d 0x0 +.debug_line 0x66862 0x0 +.debug_str 0x89b42 0x0 +.debug_loc 0x2cd9d 0x0 +.debug_ranges 0x4fa8 0x0 +Total 0x4e34c5 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 201712 + 201800 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD4205B_REGION_US_LR_size.txt index a04c4ba7f2..540bded12e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD4205B_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer.out : section size addr -.text 0x310dc 0x8006000 -_zw_protocol_cmd_handlers 0x70 0x80370dc -_zw_protocol_cmd_handlers_lr 0x30 0x803714c -.ARM.exidx 0x8 0x803717c -.copy.table 0xc 0x8037184 -.zero.table 0x0 0x8037190 +.text 0x31134 0x8006000 +_zw_protocol_cmd_handlers 0x70 0x8037134 +_zw_protocol_cmd_handlers_lr 0x30 0x80371a4 +.ARM.exidx 0x8 0x80371d4 +.copy.table 0xc 0x80371dc +.zero.table 0x0 0x80371e8 .stack 0x1000 0x20000000 .data 0x550 0x20001000 .bss 0xa6fc 0x20001550 text_application_ram 0x0 0x2000bc4c .heap 0x800 0x2000bc50 -.zwave_nvm 0x0 0x8037190 -.nvm 0x8000 0x8037190 +.zwave_nvm 0x0 0x80371e8 +.nvm 0x8000 0x80371e8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x10638 0x0 -.debug_info 0x319a7c 0x0 -.debug_abbrev 0x20e50 0x0 -.debug_loclists 0x267c0 0x0 +.debug_frame 0x10634 0x0 +.debug_info 0x31b249 0x0 +.debug_abbrev 0x20e57 0x0 +.debug_loclists 0x26872 0x0 .debug_aranges 0x5be8 0x0 -.debug_rnglists 0x3d92 0x0 -.debug_line 0x665f8 0x0 -.debug_str 0x8a0e9 0x0 -.debug_loc 0x2cdd5 0x0 -.debug_ranges 0x4f70 0x0 -Total 0x4e2d55 +.debug_rnglists 0x3da5 0x0 +.debug_line 0x66713 0x0 +.debug_str 0x8a109 0x0 +.debug_loc 0x2cd9d 0x0 +.debug_ranges 0x4fa8 0x0 +Total 0x4e477d The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 202464 + 202552 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD4210A_REGION_US_LR_size.txt index 1da5038db0..c9682ca99a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD4210A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer.out : section size addr -.text 0x30e0c 0x8006000 -_zw_protocol_cmd_handlers 0x70 0x8036e0c -_zw_protocol_cmd_handlers_lr 0x30 0x8036e7c -.ARM.exidx 0x8 0x8036eac -.copy.table 0xc 0x8036eb4 -.zero.table 0x0 0x8036ec0 +.text 0x30e64 0x8006000 +_zw_protocol_cmd_handlers 0x70 0x8036e64 +_zw_protocol_cmd_handlers_lr 0x30 0x8036ed4 +.ARM.exidx 0x8 0x8036f04 +.copy.table 0xc 0x8036f0c +.zero.table 0x0 0x8036f18 .stack 0x1000 0x20000000 .data 0x550 0x20001000 .bss 0xa6f8 0x20001550 text_application_ram 0x0 0x2000bc48 .heap 0x800 0x2000bc48 -.zwave_nvm 0x0 0x8036ec0 -.nvm 0x8000 0x8036ec0 +.zwave_nvm 0x0 0x8036f18 +.nvm 0x8000 0x8036f18 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x10610 0x0 -.debug_info 0x319077 0x0 -.debug_abbrev 0x20d74 0x0 -.debug_loclists 0x267b7 0x0 +.debug_frame 0x1060c 0x0 +.debug_info 0x31a844 0x0 +.debug_abbrev 0x20d7b 0x0 +.debug_loclists 0x26869 0x0 .debug_aranges 0x5b98 0x0 -.debug_rnglists 0x3d7a 0x0 -.debug_line 0x66715 0x0 -.debug_str 0x89b22 0x0 -.debug_loc 0x2cdca 0x0 -.debug_ranges 0x4f58 0x0 -Total 0x4e1a3a +.debug_rnglists 0x3d8d 0x0 +.debug_line 0x66838 0x0 +.debug_str 0x89b42 0x0 +.debug_loc 0x2cd92 0x0 +.debug_ranges 0x4f90 0x0 +Total 0x4e346a The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 201744 + 201832 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD4401C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD4401C_REGION_US_LR_size.txt index 1d34acfae7..3ff7493cac 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD4401C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_BRD4401C_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer.out : section size addr -.text 0x319ac 0x8006000 -_zw_protocol_cmd_handlers 0x70 0x80379ac -_zw_protocol_cmd_handlers_lr 0x30 0x8037a1c -.ARM.exidx 0x8 0x8037a4c -.copy.table 0xc 0x8037a54 -.zero.table 0x0 0x8037a60 +.text 0x31a04 0x8006000 +_zw_protocol_cmd_handlers 0x70 0x8037a04 +_zw_protocol_cmd_handlers_lr 0x30 0x8037a74 +.ARM.exidx 0x8 0x8037aa4 +.copy.table 0xc 0x8037aac +.zero.table 0x0 0x8037ab8 .stack 0x1000 0x20000000 .data 0x54c 0x20001000 .bss 0xa668 0x2000154c text_application_ram 0x0 0x2000bbb4 .heap 0x800 0x2000bbb8 -.zwave_nvm 0x0 0x8037a60 -.nvm 0x8000 0x8037a60 +.zwave_nvm 0x0 0x8037ab8 +.nvm 0x8000 0x8037ab8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x106f0 0x0 -.debug_info 0x31d971 0x0 -.debug_abbrev 0x210c5 0x0 -.debug_loclists 0x26cb2 0x0 +.debug_frame 0x106ec 0x0 +.debug_info 0x31f142 0x0 +.debug_abbrev 0x210cc 0x0 +.debug_loclists 0x26d64 0x0 .debug_aranges 0x5c20 0x0 -.debug_rnglists 0x3df8 0x0 -.debug_line 0x66aa6 0x0 -.debug_str 0x8b3b1 0x0 -.debug_loc 0x2ccb7 0x0 -.debug_ranges 0x4f58 0x0 -Total 0x4e937f +.debug_rnglists 0x3e0b 0x0 +.debug_line 0x66bc9 0x0 +.debug_str 0x8b3d1 0x0 +.debug_loc 0x2cc7f 0x0 +.debug_ranges 0x4f90 0x0 +Total 0x4eadb3 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 204716 + 204804 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD2603A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD2603A_REGION_EU_size.txt index 15497854a2..57304f4f2f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD2603A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD2603A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x342a8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803a2a8 -_zaf_cc_config 0x8 0x803a2b8 -_cc_handlers_v3 0x18c 0x803a2c0 -_zw_protocol_cmd_handlers 0x70 0x803a44c -_zw_protocol_cmd_handlers_lr 0x30 0x803a4bc -.ARM.exidx 0x8 0x803a4ec -.copy.table 0xc 0x803a4f4 -.zero.table 0x0 0x803a500 +.text 0x34300 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803a300 +_zaf_cc_config 0x8 0x803a310 +_cc_handlers_v3 0x18c 0x803a318 +_zw_protocol_cmd_handlers 0x70 0x803a4a4 +_zw_protocol_cmd_handlers_lr 0x30 0x803a514 +.ARM.exidx 0x8 0x803a544 +.copy.table 0xc 0x803a54c +.zero.table 0x0 0x803a558 .stack 0x1000 0x20000000 .data 0x4ec 0x20001000 .bss 0xa624 0x200014ec text_application_ram 0x0 0x2000bb10 .heap 0x800 0x2000bb10 -.internal_storage 0x30000 0x803a500 -.zwave_nvm 0x0 0x806a500 -.nvm 0x8000 0x806a500 +.internal_storage 0x30000 0x803a558 +.zwave_nvm 0x0 0x806a558 +.nvm 0x8000 0x806a558 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11ad0 0x0 -.debug_info 0xb48346 0x0 -.debug_abbrev 0x25a48 0x0 -.debug_loclists 0x2a5f1 0x0 +.debug_frame 0x11acc 0x0 +.debug_info 0xb49b13 0x0 +.debug_abbrev 0x25a4f 0x0 +.debug_loclists 0x2a6a3 0x0 .debug_aranges 0x6488 0x0 -.debug_rnglists 0x4892 0x0 -.debug_line 0x70e02 0x0 -.debug_str 0x8d29e 0x0 -.debug_loc 0x2bc8b 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd5c009 +.debug_rnglists 0x48a5 0x0 +.debug_line 0x70f1d 0x0 +.debug_str 0x8d2be 0x0 +.debug_loc 0x2bc53 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd5da31 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 215532 + 215620 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD2705A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD2705A_REGION_EU_size.txt index b3c51eebd2..5c5b5b7e62 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD2705A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD2705A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x346f8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803a6f8 -_zaf_cc_config 0x8 0x803a708 -_cc_handlers_v3 0x18c 0x803a710 -_zw_protocol_cmd_handlers 0x70 0x803a89c -_zw_protocol_cmd_handlers_lr 0x30 0x803a90c -.ARM.exidx 0x8 0x803a93c -.copy.table 0xc 0x803a944 -.zero.table 0x0 0x803a950 +.text 0x34750 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803a750 +_zaf_cc_config 0x8 0x803a760 +_cc_handlers_v3 0x18c 0x803a768 +_zw_protocol_cmd_handlers 0x70 0x803a8f4 +_zw_protocol_cmd_handlers_lr 0x30 0x803a964 +.ARM.exidx 0x8 0x803a994 +.copy.table 0xc 0x803a99c +.zero.table 0x0 0x803a9a8 .stack 0x1000 0x20000000 .data 0x4e8 0x20001000 .bss 0xa58c 0x200014e8 text_application_ram 0x0 0x2000ba74 .heap 0x800 0x2000ba78 -.internal_storage 0x30000 0x803a950 -.zwave_nvm 0x0 0x806a950 -.nvm 0x8000 0x806a950 +.internal_storage 0x30000 0x803a9a8 +.zwave_nvm 0x0 0x806a9a8 +.nvm 0x8000 0x806a9a8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x118d4 0x0 -.debug_info 0xb44a7e 0x0 -.debug_abbrev 0x2549d 0x0 -.debug_loclists 0x2a3b8 0x0 +.debug_frame 0x118d0 0x0 +.debug_info 0xb4624f 0x0 +.debug_abbrev 0x254a4 0x0 +.debug_loclists 0x2a46a 0x0 .debug_aranges 0x63a8 0x0 -.debug_rnglists 0x47cf 0x0 -.debug_line 0x6fe4a 0x0 -.debug_str 0x8d752 0x0 -.debug_loc 0x2bb77 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd5735a +.debug_rnglists 0x47e2 0x0 +.debug_line 0x6ff6d 0x0 +.debug_str 0x8d772 0x0 +.debug_loc 0x2bb3f 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd58d8e The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 216632 + 216720 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_EU_size.txt index fac1f83533..c38044111c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x2d764 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2d764 -_zaf_cc_config 0x8 0x2d774 -_cc_handlers_v3 0x18c 0x2d77c -_zw_protocol_cmd_handlers 0x70 0x2d908 -_zw_protocol_cmd_handlers_lr 0x30 0x2d978 -.ARM.exidx 0x8 0x2d9a8 -.copy.table 0xc 0x2d9b0 -.zero.table 0x0 0x2d9bc +.text 0x2d798 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2d798 +_zaf_cc_config 0x8 0x2d7a8 +_cc_handlers_v3 0x18c 0x2d7b0 +_zw_protocol_cmd_handlers 0x70 0x2d93c +_zw_protocol_cmd_handlers_lr 0x30 0x2d9ac +.ARM.exidx 0x8 0x2d9dc +.copy.table 0xc 0x2d9e4 +.zero.table 0x0 0x2d9f0 .stack 0x1000 0x20000000 .data 0x410 0x20001000 .bss 0x9b4c 0x20001410 text_application_ram 0x0 0x2000af5c .heap 0x800 0x2000af60 -.internal_storage 0x3a000 0x2d9bc -.zwave_nvm 0x3000 0x679bc -.nvm 0x9000 0x6a9bc +.internal_storage 0x3a000 0x2d9f0 +.zwave_nvm 0x3000 0x679f0 +.nvm 0x9000 0x6a9f0 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xebd0 0x0 -.debug_info 0xb006a2 0x0 -.debug_abbrev 0x20435 0x0 -.debug_loclists 0x16cd5 0x0 -.debug_aranges 0x5600 0x0 -.debug_rnglists 0x3337 0x0 -.debug_line 0x5b3cb 0x0 -.debug_str 0x82a83 0x0 -.debug_loc 0x2cef7 0x0 -.debug_ranges 0x4d20 0x0 -Total 0xcddb40 +.debug_frame 0xebac 0x0 +.debug_info 0xb00937 0x0 +.debug_abbrev 0x20467 0x0 +.debug_loclists 0x16d03 0x0 +.debug_aranges 0x55f8 0x0 +.debug_rnglists 0x3347 0x0 +.debug_line 0x5b438 0x0 +.debug_str 0x82a82 0x0 +.debug_loc 0x2cebf 0x0 +.debug_ranges 0x4d38 0x0 +Total 0xcdde99 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 187852 + 187904 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_US_LR_size.txt index 7c5c3b740f..c71c1434f3 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x2d764 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2d764 -_zaf_cc_config 0x8 0x2d774 -_cc_handlers_v3 0x18c 0x2d77c -_zw_protocol_cmd_handlers 0x70 0x2d908 -_zw_protocol_cmd_handlers_lr 0x30 0x2d978 -.ARM.exidx 0x8 0x2d9a8 -.copy.table 0xc 0x2d9b0 -.zero.table 0x0 0x2d9bc +.text 0x2d798 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2d798 +_zaf_cc_config 0x8 0x2d7a8 +_cc_handlers_v3 0x18c 0x2d7b0 +_zw_protocol_cmd_handlers 0x70 0x2d93c +_zw_protocol_cmd_handlers_lr 0x30 0x2d9ac +.ARM.exidx 0x8 0x2d9dc +.copy.table 0xc 0x2d9e4 +.zero.table 0x0 0x2d9f0 .stack 0x1000 0x20000000 .data 0x410 0x20001000 .bss 0x9b4c 0x20001410 text_application_ram 0x0 0x2000af5c .heap 0x800 0x2000af60 -.internal_storage 0x3a000 0x2d9bc -.zwave_nvm 0x3000 0x679bc -.nvm 0x9000 0x6a9bc +.internal_storage 0x3a000 0x2d9f0 +.zwave_nvm 0x3000 0x679f0 +.nvm 0x9000 0x6a9f0 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xebd0 0x0 -.debug_info 0xb006a2 0x0 -.debug_abbrev 0x20435 0x0 -.debug_loclists 0x16cd5 0x0 -.debug_aranges 0x5600 0x0 -.debug_rnglists 0x3337 0x0 -.debug_line 0x5b3cb 0x0 -.debug_str 0x82a79 0x0 -.debug_loc 0x2cef7 0x0 -.debug_ranges 0x4d20 0x0 -Total 0xcddb36 +.debug_frame 0xebac 0x0 +.debug_info 0xb00937 0x0 +.debug_abbrev 0x20467 0x0 +.debug_loclists 0x16d03 0x0 +.debug_aranges 0x55f8 0x0 +.debug_rnglists 0x3347 0x0 +.debug_line 0x5b438 0x0 +.debug_str 0x82a78 0x0 +.debug_loc 0x2cebf 0x0 +.debug_ranges 0x4d38 0x0 +Total 0xcdde8f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 187852 + 187904 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_US_size.txt index fac1f83533..c38044111c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x2d764 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2d764 -_zaf_cc_config 0x8 0x2d774 -_cc_handlers_v3 0x18c 0x2d77c -_zw_protocol_cmd_handlers 0x70 0x2d908 -_zw_protocol_cmd_handlers_lr 0x30 0x2d978 -.ARM.exidx 0x8 0x2d9a8 -.copy.table 0xc 0x2d9b0 -.zero.table 0x0 0x2d9bc +.text 0x2d798 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2d798 +_zaf_cc_config 0x8 0x2d7a8 +_cc_handlers_v3 0x18c 0x2d7b0 +_zw_protocol_cmd_handlers 0x70 0x2d93c +_zw_protocol_cmd_handlers_lr 0x30 0x2d9ac +.ARM.exidx 0x8 0x2d9dc +.copy.table 0xc 0x2d9e4 +.zero.table 0x0 0x2d9f0 .stack 0x1000 0x20000000 .data 0x410 0x20001000 .bss 0x9b4c 0x20001410 text_application_ram 0x0 0x2000af5c .heap 0x800 0x2000af60 -.internal_storage 0x3a000 0x2d9bc -.zwave_nvm 0x3000 0x679bc -.nvm 0x9000 0x6a9bc +.internal_storage 0x3a000 0x2d9f0 +.zwave_nvm 0x3000 0x679f0 +.nvm 0x9000 0x6a9f0 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xebd0 0x0 -.debug_info 0xb006a2 0x0 -.debug_abbrev 0x20435 0x0 -.debug_loclists 0x16cd5 0x0 -.debug_aranges 0x5600 0x0 -.debug_rnglists 0x3337 0x0 -.debug_line 0x5b3cb 0x0 -.debug_str 0x82a83 0x0 -.debug_loc 0x2cef7 0x0 -.debug_ranges 0x4d20 0x0 -Total 0xcddb40 +.debug_frame 0xebac 0x0 +.debug_info 0xb00937 0x0 +.debug_abbrev 0x20467 0x0 +.debug_loclists 0x16d03 0x0 +.debug_aranges 0x55f8 0x0 +.debug_rnglists 0x3347 0x0 +.debug_line 0x5b438 0x0 +.debug_str 0x82a82 0x0 +.debug_loc 0x2cebf 0x0 +.debug_ranges 0x4d38 0x0 +Total 0xcdde99 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 187852 + 187904 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_EU_size.txt index 3d003b24c4..89d11055f2 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x33edc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x8039edc -_zaf_cc_config 0x8 0x8039eec -_cc_handlers_v3 0x18c 0x8039ef4 -_zw_protocol_cmd_handlers 0x70 0x803a080 -_zw_protocol_cmd_handlers_lr 0x30 0x803a0f0 -.ARM.exidx 0x8 0x803a120 -.copy.table 0xc 0x803a128 -.zero.table 0x0 0x803a134 +.text 0x33f34 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x8039f34 +_zaf_cc_config 0x8 0x8039f44 +_cc_handlers_v3 0x18c 0x8039f4c +_zw_protocol_cmd_handlers 0x70 0x803a0d8 +_zw_protocol_cmd_handlers_lr 0x30 0x803a148 +.ARM.exidx 0x8 0x803a178 +.copy.table 0xc 0x803a180 +.zero.table 0x0 0x803a18c .stack 0x1000 0x20000000 .data 0x4ec 0x20001000 .bss 0xa624 0x200014ec text_application_ram 0x0 0x2000bb10 .heap 0x800 0x2000bb10 -.internal_storage 0x30000 0x803a134 -.zwave_nvm 0x0 0x806a134 -.nvm 0x8000 0x806a134 +.internal_storage 0x30000 0x803a18c +.zwave_nvm 0x0 0x806a18c +.nvm 0x8000 0x806a18c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b58 0x0 -.debug_info 0xb49b23 0x0 -.debug_abbrev 0x25c1d 0x0 -.debug_loclists 0x2a865 0x0 +.debug_frame 0x11b54 0x0 +.debug_info 0xb4b2f0 0x0 +.debug_abbrev 0x25c24 0x0 +.debug_loclists 0x2a917 0x0 .debug_aranges 0x6478 0x0 -.debug_rnglists 0x48c3 0x0 -.debug_line 0x714a2 0x0 -.debug_str 0x8cd45 0x0 -.debug_loc 0x2bc8b 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd5da53 +.debug_rnglists 0x48d6 0x0 +.debug_line 0x715c5 0x0 +.debug_str 0x8cd65 0x0 +.debug_loc 0x2bc53 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd5f483 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214560 + 214648 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_US_LR_size.txt index 6c216538a1..7854005a5f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x33edc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x8039edc -_zaf_cc_config 0x8 0x8039eec -_cc_handlers_v3 0x18c 0x8039ef4 -_zw_protocol_cmd_handlers 0x70 0x803a080 -_zw_protocol_cmd_handlers_lr 0x30 0x803a0f0 -.ARM.exidx 0x8 0x803a120 -.copy.table 0xc 0x803a128 -.zero.table 0x0 0x803a134 +.text 0x33f34 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x8039f34 +_zaf_cc_config 0x8 0x8039f44 +_cc_handlers_v3 0x18c 0x8039f4c +_zw_protocol_cmd_handlers 0x70 0x803a0d8 +_zw_protocol_cmd_handlers_lr 0x30 0x803a148 +.ARM.exidx 0x8 0x803a178 +.copy.table 0xc 0x803a180 +.zero.table 0x0 0x803a18c .stack 0x1000 0x20000000 .data 0x4ec 0x20001000 .bss 0xa624 0x200014ec text_application_ram 0x0 0x2000bb10 .heap 0x800 0x2000bb10 -.internal_storage 0x30000 0x803a134 -.zwave_nvm 0x0 0x806a134 -.nvm 0x8000 0x806a134 +.internal_storage 0x30000 0x803a18c +.zwave_nvm 0x0 0x806a18c +.nvm 0x8000 0x806a18c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b58 0x0 -.debug_info 0xb49b23 0x0 -.debug_abbrev 0x25c1d 0x0 -.debug_loclists 0x2a865 0x0 +.debug_frame 0x11b54 0x0 +.debug_info 0xb4b2f0 0x0 +.debug_abbrev 0x25c24 0x0 +.debug_loclists 0x2a917 0x0 .debug_aranges 0x6478 0x0 -.debug_rnglists 0x48c3 0x0 -.debug_line 0x714a2 0x0 -.debug_str 0x8cd3b 0x0 -.debug_loc 0x2bc8b 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd5da49 +.debug_rnglists 0x48d6 0x0 +.debug_line 0x715c5 0x0 +.debug_str 0x8cd5b 0x0 +.debug_loc 0x2bc53 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd5f479 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214560 + 214648 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_US_size.txt index 3d003b24c4..89d11055f2 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x33edc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x8039edc -_zaf_cc_config 0x8 0x8039eec -_cc_handlers_v3 0x18c 0x8039ef4 -_zw_protocol_cmd_handlers 0x70 0x803a080 -_zw_protocol_cmd_handlers_lr 0x30 0x803a0f0 -.ARM.exidx 0x8 0x803a120 -.copy.table 0xc 0x803a128 -.zero.table 0x0 0x803a134 +.text 0x33f34 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x8039f34 +_zaf_cc_config 0x8 0x8039f44 +_cc_handlers_v3 0x18c 0x8039f4c +_zw_protocol_cmd_handlers 0x70 0x803a0d8 +_zw_protocol_cmd_handlers_lr 0x30 0x803a148 +.ARM.exidx 0x8 0x803a178 +.copy.table 0xc 0x803a180 +.zero.table 0x0 0x803a18c .stack 0x1000 0x20000000 .data 0x4ec 0x20001000 .bss 0xa624 0x200014ec text_application_ram 0x0 0x2000bb10 .heap 0x800 0x2000bb10 -.internal_storage 0x30000 0x803a134 -.zwave_nvm 0x0 0x806a134 -.nvm 0x8000 0x806a134 +.internal_storage 0x30000 0x803a18c +.zwave_nvm 0x0 0x806a18c +.nvm 0x8000 0x806a18c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b58 0x0 -.debug_info 0xb49b23 0x0 -.debug_abbrev 0x25c1d 0x0 -.debug_loclists 0x2a865 0x0 +.debug_frame 0x11b54 0x0 +.debug_info 0xb4b2f0 0x0 +.debug_abbrev 0x25c24 0x0 +.debug_loclists 0x2a917 0x0 .debug_aranges 0x6478 0x0 -.debug_rnglists 0x48c3 0x0 -.debug_line 0x714a2 0x0 -.debug_str 0x8cd45 0x0 -.debug_loc 0x2bc8b 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd5da53 +.debug_rnglists 0x48d6 0x0 +.debug_line 0x715c5 0x0 +.debug_str 0x8cd65 0x0 +.debug_loc 0x2bc53 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd5f483 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214560 + 214648 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_EU_size.txt index 23c0f3f494..413981d609 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x33fb0 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x8039fb0 -_zaf_cc_config 0x8 0x8039fc0 -_cc_handlers_v3 0x18c 0x8039fc8 -_zw_protocol_cmd_handlers 0x70 0x803a154 -_zw_protocol_cmd_handlers_lr 0x30 0x803a1c4 -.ARM.exidx 0x8 0x803a1f4 -.copy.table 0xc 0x803a1fc -.zero.table 0x0 0x803a208 +.text 0x34008 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803a008 +_zaf_cc_config 0x8 0x803a018 +_cc_handlers_v3 0x18c 0x803a020 +_zw_protocol_cmd_handlers 0x70 0x803a1ac +_zw_protocol_cmd_handlers_lr 0x30 0x803a21c +.ARM.exidx 0x8 0x803a24c +.copy.table 0xc 0x803a254 +.zero.table 0x0 0x803a260 .stack 0x1000 0x20000000 .data 0x4ec 0x20001000 .bss 0xa624 0x200014ec text_application_ram 0x0 0x2000bb10 .heap 0x800 0x2000bb10 -.internal_storage 0x30000 0x803a208 -.zwave_nvm 0x0 0x806a208 -.nvm 0x8000 0x806a208 +.internal_storage 0x30000 0x803a260 +.zwave_nvm 0x0 0x806a260 +.nvm 0x8000 0x806a260 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b88 0x0 -.debug_info 0xb49d9b 0x0 -.debug_abbrev 0x25d1f 0x0 -.debug_loclists 0x2a865 0x0 +.debug_frame 0x11b84 0x0 +.debug_info 0xb4b568 0x0 +.debug_abbrev 0x25d26 0x0 +.debug_loclists 0x2a917 0x0 .debug_aranges 0x6498 0x0 -.debug_rnglists 0x48d6 0x0 -.debug_line 0x7167b 0x0 -.debug_str 0x8cf18 0x0 -.debug_loc 0x2bc8b 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd5e2b0 +.debug_rnglists 0x48e9 0x0 +.debug_line 0x7179e 0x0 +.debug_str 0x8cf38 0x0 +.debug_loc 0x2bc53 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd5fce0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214772 + 214860 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_US_LR_size.txt index aff452de6f..800cf063f0 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x33fb0 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x8039fb0 -_zaf_cc_config 0x8 0x8039fc0 -_cc_handlers_v3 0x18c 0x8039fc8 -_zw_protocol_cmd_handlers 0x70 0x803a154 -_zw_protocol_cmd_handlers_lr 0x30 0x803a1c4 -.ARM.exidx 0x8 0x803a1f4 -.copy.table 0xc 0x803a1fc -.zero.table 0x0 0x803a208 +.text 0x34008 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803a008 +_zaf_cc_config 0x8 0x803a018 +_cc_handlers_v3 0x18c 0x803a020 +_zw_protocol_cmd_handlers 0x70 0x803a1ac +_zw_protocol_cmd_handlers_lr 0x30 0x803a21c +.ARM.exidx 0x8 0x803a24c +.copy.table 0xc 0x803a254 +.zero.table 0x0 0x803a260 .stack 0x1000 0x20000000 .data 0x4ec 0x20001000 .bss 0xa624 0x200014ec text_application_ram 0x0 0x2000bb10 .heap 0x800 0x2000bb10 -.internal_storage 0x30000 0x803a208 -.zwave_nvm 0x0 0x806a208 -.nvm 0x8000 0x806a208 +.internal_storage 0x30000 0x803a260 +.zwave_nvm 0x0 0x806a260 +.nvm 0x8000 0x806a260 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b88 0x0 -.debug_info 0xb49d9b 0x0 -.debug_abbrev 0x25d1f 0x0 -.debug_loclists 0x2a865 0x0 +.debug_frame 0x11b84 0x0 +.debug_info 0xb4b568 0x0 +.debug_abbrev 0x25d26 0x0 +.debug_loclists 0x2a917 0x0 .debug_aranges 0x6498 0x0 -.debug_rnglists 0x48d6 0x0 -.debug_line 0x7167b 0x0 -.debug_str 0x8cf0e 0x0 -.debug_loc 0x2bc8b 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd5e2a6 +.debug_rnglists 0x48e9 0x0 +.debug_line 0x7179e 0x0 +.debug_str 0x8cf2e 0x0 +.debug_loc 0x2bc53 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd5fcd6 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214772 + 214860 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_US_size.txt index 23c0f3f494..413981d609 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x33fb0 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x8039fb0 -_zaf_cc_config 0x8 0x8039fc0 -_cc_handlers_v3 0x18c 0x8039fc8 -_zw_protocol_cmd_handlers 0x70 0x803a154 -_zw_protocol_cmd_handlers_lr 0x30 0x803a1c4 -.ARM.exidx 0x8 0x803a1f4 -.copy.table 0xc 0x803a1fc -.zero.table 0x0 0x803a208 +.text 0x34008 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803a008 +_zaf_cc_config 0x8 0x803a018 +_cc_handlers_v3 0x18c 0x803a020 +_zw_protocol_cmd_handlers 0x70 0x803a1ac +_zw_protocol_cmd_handlers_lr 0x30 0x803a21c +.ARM.exidx 0x8 0x803a24c +.copy.table 0xc 0x803a254 +.zero.table 0x0 0x803a260 .stack 0x1000 0x20000000 .data 0x4ec 0x20001000 .bss 0xa624 0x200014ec text_application_ram 0x0 0x2000bb10 .heap 0x800 0x2000bb10 -.internal_storage 0x30000 0x803a208 -.zwave_nvm 0x0 0x806a208 -.nvm 0x8000 0x806a208 +.internal_storage 0x30000 0x803a260 +.zwave_nvm 0x0 0x806a260 +.nvm 0x8000 0x806a260 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b88 0x0 -.debug_info 0xb49d9b 0x0 -.debug_abbrev 0x25d1f 0x0 -.debug_loclists 0x2a865 0x0 +.debug_frame 0x11b84 0x0 +.debug_info 0xb4b568 0x0 +.debug_abbrev 0x25d26 0x0 +.debug_loclists 0x2a917 0x0 .debug_aranges 0x6498 0x0 -.debug_rnglists 0x48d6 0x0 -.debug_line 0x7167b 0x0 -.debug_str 0x8cf18 0x0 -.debug_loc 0x2bc8b 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd5e2b0 +.debug_rnglists 0x48e9 0x0 +.debug_line 0x7179e 0x0 +.debug_str 0x8cf38 0x0 +.debug_loc 0x2bc53 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd5fce0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214772 + 214860 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_EU_size.txt index 316c4087c9..8c9c92cab5 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x33a94 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x8039a94 -_zaf_cc_config 0x8 0x8039aa4 -_cc_handlers_v3 0x18c 0x8039aac -_zw_protocol_cmd_handlers 0x70 0x8039c38 -_zw_protocol_cmd_handlers_lr 0x30 0x8039ca8 -.ARM.exidx 0x8 0x8039cd8 -.copy.table 0xc 0x8039ce0 -.zero.table 0x0 0x8039cec +.text 0x33aec 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x8039aec +_zaf_cc_config 0x8 0x8039afc +_cc_handlers_v3 0x18c 0x8039b04 +_zw_protocol_cmd_handlers 0x70 0x8039c90 +_zw_protocol_cmd_handlers_lr 0x30 0x8039d00 +.ARM.exidx 0x8 0x8039d30 +.copy.table 0xc 0x8039d38 +.zero.table 0x0 0x8039d44 .stack 0x1000 0x20000000 .data 0x4ec 0x20001000 .bss 0xa484 0x200014ec text_application_ram 0x0 0x2000b970 .heap 0x800 0x2000b970 -.internal_storage 0x30000 0x8039cec -.zwave_nvm 0x0 0x8069cec -.nvm 0x8000 0x8069cec +.internal_storage 0x30000 0x8039d44 +.zwave_nvm 0x0 0x8069d44 +.nvm 0x8000 0x8069d44 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x114f8 0x0 -.debug_info 0xb44142 0x0 -.debug_abbrev 0x25338 0x0 -.debug_loclists 0x26d1c 0x0 +.debug_frame 0x114f4 0x0 +.debug_info 0xb4590f 0x0 +.debug_abbrev 0x2533f 0x0 +.debug_loclists 0x26dce 0x0 .debug_aranges 0x62f8 0x0 -.debug_rnglists 0x462c 0x0 -.debug_line 0x6e5cd 0x0 -.debug_str 0x8ca88 0x0 -.debug_loc 0x2bc8b 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd4fa53 +.debug_rnglists 0x463f 0x0 +.debug_line 0x6e6e6 0x0 +.debug_str 0x8caa8 0x0 +.debug_loc 0x2bc53 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd51479 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 213464 + 213552 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_US_LR_size.txt index c0bb98182a..3d9b326da8 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x33a94 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x8039a94 -_zaf_cc_config 0x8 0x8039aa4 -_cc_handlers_v3 0x18c 0x8039aac -_zw_protocol_cmd_handlers 0x70 0x8039c38 -_zw_protocol_cmd_handlers_lr 0x30 0x8039ca8 -.ARM.exidx 0x8 0x8039cd8 -.copy.table 0xc 0x8039ce0 -.zero.table 0x0 0x8039cec +.text 0x33aec 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x8039aec +_zaf_cc_config 0x8 0x8039afc +_cc_handlers_v3 0x18c 0x8039b04 +_zw_protocol_cmd_handlers 0x70 0x8039c90 +_zw_protocol_cmd_handlers_lr 0x30 0x8039d00 +.ARM.exidx 0x8 0x8039d30 +.copy.table 0xc 0x8039d38 +.zero.table 0x0 0x8039d44 .stack 0x1000 0x20000000 .data 0x4ec 0x20001000 .bss 0xa484 0x200014ec text_application_ram 0x0 0x2000b970 .heap 0x800 0x2000b970 -.internal_storage 0x30000 0x8039cec -.zwave_nvm 0x0 0x8069cec -.nvm 0x8000 0x8069cec +.internal_storage 0x30000 0x8039d44 +.zwave_nvm 0x0 0x8069d44 +.nvm 0x8000 0x8069d44 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x114f8 0x0 -.debug_info 0xb44142 0x0 -.debug_abbrev 0x25338 0x0 -.debug_loclists 0x26d1c 0x0 +.debug_frame 0x114f4 0x0 +.debug_info 0xb4590f 0x0 +.debug_abbrev 0x2533f 0x0 +.debug_loclists 0x26dce 0x0 .debug_aranges 0x62f8 0x0 -.debug_rnglists 0x462c 0x0 -.debug_line 0x6e5cd 0x0 -.debug_str 0x8ca7e 0x0 -.debug_loc 0x2bc8b 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd4fa49 +.debug_rnglists 0x463f 0x0 +.debug_line 0x6e6e6 0x0 +.debug_str 0x8ca9e 0x0 +.debug_loc 0x2bc53 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd5146f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 213464 + 213552 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_US_size.txt index 316c4087c9..8c9c92cab5 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x33a94 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x8039a94 -_zaf_cc_config 0x8 0x8039aa4 -_cc_handlers_v3 0x18c 0x8039aac -_zw_protocol_cmd_handlers 0x70 0x8039c38 -_zw_protocol_cmd_handlers_lr 0x30 0x8039ca8 -.ARM.exidx 0x8 0x8039cd8 -.copy.table 0xc 0x8039ce0 -.zero.table 0x0 0x8039cec +.text 0x33aec 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x8039aec +_zaf_cc_config 0x8 0x8039afc +_cc_handlers_v3 0x18c 0x8039b04 +_zw_protocol_cmd_handlers 0x70 0x8039c90 +_zw_protocol_cmd_handlers_lr 0x30 0x8039d00 +.ARM.exidx 0x8 0x8039d30 +.copy.table 0xc 0x8039d38 +.zero.table 0x0 0x8039d44 .stack 0x1000 0x20000000 .data 0x4ec 0x20001000 .bss 0xa484 0x200014ec text_application_ram 0x0 0x2000b970 .heap 0x800 0x2000b970 -.internal_storage 0x30000 0x8039cec -.zwave_nvm 0x0 0x8069cec -.nvm 0x8000 0x8069cec +.internal_storage 0x30000 0x8039d44 +.zwave_nvm 0x0 0x8069d44 +.nvm 0x8000 0x8069d44 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x114f8 0x0 -.debug_info 0xb44142 0x0 -.debug_abbrev 0x25338 0x0 -.debug_loclists 0x26d1c 0x0 +.debug_frame 0x114f4 0x0 +.debug_info 0xb4590f 0x0 +.debug_abbrev 0x2533f 0x0 +.debug_loclists 0x26dce 0x0 .debug_aranges 0x62f8 0x0 -.debug_rnglists 0x462c 0x0 -.debug_line 0x6e5cd 0x0 -.debug_str 0x8ca88 0x0 -.debug_loc 0x2bc8b 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd4fa53 +.debug_rnglists 0x463f 0x0 +.debug_line 0x6e6e6 0x0 +.debug_str 0x8caa8 0x0 +.debug_loc 0x2bc53 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd51479 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 213464 + 213552 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_EU_size.txt index 6c2087e753..ed108a6469 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x342a0 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803a2a0 -_zaf_cc_config 0x8 0x803a2b0 -_cc_handlers_v3 0x18c 0x803a2b8 -_zw_protocol_cmd_handlers 0x70 0x803a444 -_zw_protocol_cmd_handlers_lr 0x30 0x803a4b4 -.ARM.exidx 0x8 0x803a4e4 -.copy.table 0xc 0x803a4ec -.zero.table 0x0 0x803a4f8 +.text 0x342f8 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803a2f8 +_zaf_cc_config 0x8 0x803a308 +_cc_handlers_v3 0x18c 0x803a310 +_zw_protocol_cmd_handlers 0x70 0x803a49c +_zw_protocol_cmd_handlers_lr 0x30 0x803a50c +.ARM.exidx 0x8 0x803a53c +.copy.table 0xc 0x803a544 +.zero.table 0x0 0x803a550 .stack 0x1000 0x20000000 .data 0x4ec 0x20001000 .bss 0xa624 0x200014ec text_application_ram 0x0 0x2000bb10 .heap 0x800 0x2000bb10 -.internal_storage 0x30000 0x803a4f8 -.zwave_nvm 0x0 0x806a4f8 -.nvm 0x8000 0x806a4f8 +.internal_storage 0x30000 0x803a550 +.zwave_nvm 0x0 0x806a550 +.nvm 0x8000 0x806a550 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11bb8 0x0 -.debug_info 0xb4a76a 0x0 -.debug_abbrev 0x25dfb 0x0 -.debug_loclists 0x2a86e 0x0 +.debug_frame 0x11bb4 0x0 +.debug_info 0xb4bf37 0x0 +.debug_abbrev 0x25e02 0x0 +.debug_loclists 0x2a920 0x0 .debug_aranges 0x64e8 0x0 -.debug_rnglists 0x48ee 0x0 -.debug_line 0x71574 0x0 -.debug_str 0x8d4e8 0x0 -.debug_loc 0x2bc8b 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd5f5b5 +.debug_rnglists 0x4901 0x0 +.debug_line 0x7168f 0x0 +.debug_str 0x8d508 0x0 +.debug_loc 0x2bc53 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd60fdd The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 215524 + 215612 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_US_LR_size.txt index f227267b5c..2e454da0b0 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x342a0 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803a2a0 -_zaf_cc_config 0x8 0x803a2b0 -_cc_handlers_v3 0x18c 0x803a2b8 -_zw_protocol_cmd_handlers 0x70 0x803a444 -_zw_protocol_cmd_handlers_lr 0x30 0x803a4b4 -.ARM.exidx 0x8 0x803a4e4 -.copy.table 0xc 0x803a4ec -.zero.table 0x0 0x803a4f8 +.text 0x342f8 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803a2f8 +_zaf_cc_config 0x8 0x803a308 +_cc_handlers_v3 0x18c 0x803a310 +_zw_protocol_cmd_handlers 0x70 0x803a49c +_zw_protocol_cmd_handlers_lr 0x30 0x803a50c +.ARM.exidx 0x8 0x803a53c +.copy.table 0xc 0x803a544 +.zero.table 0x0 0x803a550 .stack 0x1000 0x20000000 .data 0x4ec 0x20001000 .bss 0xa624 0x200014ec text_application_ram 0x0 0x2000bb10 .heap 0x800 0x2000bb10 -.internal_storage 0x30000 0x803a4f8 -.zwave_nvm 0x0 0x806a4f8 -.nvm 0x8000 0x806a4f8 +.internal_storage 0x30000 0x803a550 +.zwave_nvm 0x0 0x806a550 +.nvm 0x8000 0x806a550 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11bb8 0x0 -.debug_info 0xb4a76a 0x0 -.debug_abbrev 0x25dfb 0x0 -.debug_loclists 0x2a86e 0x0 +.debug_frame 0x11bb4 0x0 +.debug_info 0xb4bf37 0x0 +.debug_abbrev 0x25e02 0x0 +.debug_loclists 0x2a920 0x0 .debug_aranges 0x64e8 0x0 -.debug_rnglists 0x48ee 0x0 -.debug_line 0x71574 0x0 -.debug_str 0x8d4de 0x0 -.debug_loc 0x2bc8b 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd5f5ab +.debug_rnglists 0x4901 0x0 +.debug_line 0x7168f 0x0 +.debug_str 0x8d4fe 0x0 +.debug_loc 0x2bc53 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd60fd3 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 215524 + 215612 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_US_size.txt index 6c2087e753..ed108a6469 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x342a0 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803a2a0 -_zaf_cc_config 0x8 0x803a2b0 -_cc_handlers_v3 0x18c 0x803a2b8 -_zw_protocol_cmd_handlers 0x70 0x803a444 -_zw_protocol_cmd_handlers_lr 0x30 0x803a4b4 -.ARM.exidx 0x8 0x803a4e4 -.copy.table 0xc 0x803a4ec -.zero.table 0x0 0x803a4f8 +.text 0x342f8 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803a2f8 +_zaf_cc_config 0x8 0x803a308 +_cc_handlers_v3 0x18c 0x803a310 +_zw_protocol_cmd_handlers 0x70 0x803a49c +_zw_protocol_cmd_handlers_lr 0x30 0x803a50c +.ARM.exidx 0x8 0x803a53c +.copy.table 0xc 0x803a544 +.zero.table 0x0 0x803a550 .stack 0x1000 0x20000000 .data 0x4ec 0x20001000 .bss 0xa624 0x200014ec text_application_ram 0x0 0x2000bb10 .heap 0x800 0x2000bb10 -.internal_storage 0x30000 0x803a4f8 -.zwave_nvm 0x0 0x806a4f8 -.nvm 0x8000 0x806a4f8 +.internal_storage 0x30000 0x803a550 +.zwave_nvm 0x0 0x806a550 +.nvm 0x8000 0x806a550 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11bb8 0x0 -.debug_info 0xb4a76a 0x0 -.debug_abbrev 0x25dfb 0x0 -.debug_loclists 0x2a86e 0x0 +.debug_frame 0x11bb4 0x0 +.debug_info 0xb4bf37 0x0 +.debug_abbrev 0x25e02 0x0 +.debug_loclists 0x2a920 0x0 .debug_aranges 0x64e8 0x0 -.debug_rnglists 0x48ee 0x0 -.debug_line 0x71574 0x0 -.debug_str 0x8d4e8 0x0 -.debug_loc 0x2bc8b 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd5f5b5 +.debug_rnglists 0x4901 0x0 +.debug_line 0x7168f 0x0 +.debug_str 0x8d508 0x0 +.debug_loc 0x2bc53 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd60fdd The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 215524 + 215612 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_EU_size.txt index fac1f83533..c38044111c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x2d764 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2d764 -_zaf_cc_config 0x8 0x2d774 -_cc_handlers_v3 0x18c 0x2d77c -_zw_protocol_cmd_handlers 0x70 0x2d908 -_zw_protocol_cmd_handlers_lr 0x30 0x2d978 -.ARM.exidx 0x8 0x2d9a8 -.copy.table 0xc 0x2d9b0 -.zero.table 0x0 0x2d9bc +.text 0x2d798 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2d798 +_zaf_cc_config 0x8 0x2d7a8 +_cc_handlers_v3 0x18c 0x2d7b0 +_zw_protocol_cmd_handlers 0x70 0x2d93c +_zw_protocol_cmd_handlers_lr 0x30 0x2d9ac +.ARM.exidx 0x8 0x2d9dc +.copy.table 0xc 0x2d9e4 +.zero.table 0x0 0x2d9f0 .stack 0x1000 0x20000000 .data 0x410 0x20001000 .bss 0x9b4c 0x20001410 text_application_ram 0x0 0x2000af5c .heap 0x800 0x2000af60 -.internal_storage 0x3a000 0x2d9bc -.zwave_nvm 0x3000 0x679bc -.nvm 0x9000 0x6a9bc +.internal_storage 0x3a000 0x2d9f0 +.zwave_nvm 0x3000 0x679f0 +.nvm 0x9000 0x6a9f0 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xebd0 0x0 -.debug_info 0xb006a2 0x0 -.debug_abbrev 0x20435 0x0 -.debug_loclists 0x16cd5 0x0 -.debug_aranges 0x5600 0x0 -.debug_rnglists 0x3337 0x0 -.debug_line 0x5b3cb 0x0 -.debug_str 0x82a83 0x0 -.debug_loc 0x2cef7 0x0 -.debug_ranges 0x4d20 0x0 -Total 0xcddb40 +.debug_frame 0xebac 0x0 +.debug_info 0xb00937 0x0 +.debug_abbrev 0x20467 0x0 +.debug_loclists 0x16d03 0x0 +.debug_aranges 0x55f8 0x0 +.debug_rnglists 0x3347 0x0 +.debug_line 0x5b438 0x0 +.debug_str 0x82a82 0x0 +.debug_loc 0x2cebf 0x0 +.debug_ranges 0x4d38 0x0 +Total 0xcdde99 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 187852 + 187904 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_US_LR_size.txt index 7c5c3b740f..c71c1434f3 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x2d764 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2d764 -_zaf_cc_config 0x8 0x2d774 -_cc_handlers_v3 0x18c 0x2d77c -_zw_protocol_cmd_handlers 0x70 0x2d908 -_zw_protocol_cmd_handlers_lr 0x30 0x2d978 -.ARM.exidx 0x8 0x2d9a8 -.copy.table 0xc 0x2d9b0 -.zero.table 0x0 0x2d9bc +.text 0x2d798 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2d798 +_zaf_cc_config 0x8 0x2d7a8 +_cc_handlers_v3 0x18c 0x2d7b0 +_zw_protocol_cmd_handlers 0x70 0x2d93c +_zw_protocol_cmd_handlers_lr 0x30 0x2d9ac +.ARM.exidx 0x8 0x2d9dc +.copy.table 0xc 0x2d9e4 +.zero.table 0x0 0x2d9f0 .stack 0x1000 0x20000000 .data 0x410 0x20001000 .bss 0x9b4c 0x20001410 text_application_ram 0x0 0x2000af5c .heap 0x800 0x2000af60 -.internal_storage 0x3a000 0x2d9bc -.zwave_nvm 0x3000 0x679bc -.nvm 0x9000 0x6a9bc +.internal_storage 0x3a000 0x2d9f0 +.zwave_nvm 0x3000 0x679f0 +.nvm 0x9000 0x6a9f0 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xebd0 0x0 -.debug_info 0xb006a2 0x0 -.debug_abbrev 0x20435 0x0 -.debug_loclists 0x16cd5 0x0 -.debug_aranges 0x5600 0x0 -.debug_rnglists 0x3337 0x0 -.debug_line 0x5b3cb 0x0 -.debug_str 0x82a79 0x0 -.debug_loc 0x2cef7 0x0 -.debug_ranges 0x4d20 0x0 -Total 0xcddb36 +.debug_frame 0xebac 0x0 +.debug_info 0xb00937 0x0 +.debug_abbrev 0x20467 0x0 +.debug_loclists 0x16d03 0x0 +.debug_aranges 0x55f8 0x0 +.debug_rnglists 0x3347 0x0 +.debug_line 0x5b438 0x0 +.debug_str 0x82a78 0x0 +.debug_loc 0x2cebf 0x0 +.debug_ranges 0x4d38 0x0 +Total 0xcdde8f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 187852 + 187904 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_US_size.txt index fac1f83533..c38044111c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x2d764 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2d764 -_zaf_cc_config 0x8 0x2d774 -_cc_handlers_v3 0x18c 0x2d77c -_zw_protocol_cmd_handlers 0x70 0x2d908 -_zw_protocol_cmd_handlers_lr 0x30 0x2d978 -.ARM.exidx 0x8 0x2d9a8 -.copy.table 0xc 0x2d9b0 -.zero.table 0x0 0x2d9bc +.text 0x2d798 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2d798 +_zaf_cc_config 0x8 0x2d7a8 +_cc_handlers_v3 0x18c 0x2d7b0 +_zw_protocol_cmd_handlers 0x70 0x2d93c +_zw_protocol_cmd_handlers_lr 0x30 0x2d9ac +.ARM.exidx 0x8 0x2d9dc +.copy.table 0xc 0x2d9e4 +.zero.table 0x0 0x2d9f0 .stack 0x1000 0x20000000 .data 0x410 0x20001000 .bss 0x9b4c 0x20001410 text_application_ram 0x0 0x2000af5c .heap 0x800 0x2000af60 -.internal_storage 0x3a000 0x2d9bc -.zwave_nvm 0x3000 0x679bc -.nvm 0x9000 0x6a9bc +.internal_storage 0x3a000 0x2d9f0 +.zwave_nvm 0x3000 0x679f0 +.nvm 0x9000 0x6a9f0 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xebd0 0x0 -.debug_info 0xb006a2 0x0 -.debug_abbrev 0x20435 0x0 -.debug_loclists 0x16cd5 0x0 -.debug_aranges 0x5600 0x0 -.debug_rnglists 0x3337 0x0 -.debug_line 0x5b3cb 0x0 -.debug_str 0x82a83 0x0 -.debug_loc 0x2cef7 0x0 -.debug_ranges 0x4d20 0x0 -Total 0xcddb40 +.debug_frame 0xebac 0x0 +.debug_info 0xb00937 0x0 +.debug_abbrev 0x20467 0x0 +.debug_loclists 0x16d03 0x0 +.debug_aranges 0x55f8 0x0 +.debug_rnglists 0x3347 0x0 +.debug_line 0x5b438 0x0 +.debug_str 0x82a82 0x0 +.debug_loc 0x2cebf 0x0 +.debug_ranges 0x4d38 0x0 +Total 0xcdde99 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 187852 + 187904 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4209A_REGION_US_LR_size.txt index be8836dce3..105b91e937 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4209A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x2d6bc 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2d6bc -_zaf_cc_config 0x8 0x2d6cc -_cc_handlers_v3 0x18c 0x2d6d4 -_zw_protocol_cmd_handlers 0x70 0x2d860 -_zw_protocol_cmd_handlers_lr 0x30 0x2d8d0 -.ARM.exidx 0x8 0x2d900 -.copy.table 0xc 0x2d908 -.zero.table 0x0 0x2d914 +.text 0x2d6f0 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2d6f0 +_zaf_cc_config 0x8 0x2d700 +_cc_handlers_v3 0x18c 0x2d708 +_zw_protocol_cmd_handlers 0x70 0x2d894 +_zw_protocol_cmd_handlers_lr 0x30 0x2d904 +.ARM.exidx 0x8 0x2d934 +.copy.table 0xc 0x2d93c +.zero.table 0x0 0x2d948 .stack 0x1000 0x20000000 .data 0x410 0x20001000 .bss 0x9b34 0x20001410 text_application_ram 0x0 0x2000af44 .heap 0x800 0x2000af48 -.internal_storage 0x3a000 0x2d914 -.zwave_nvm 0x3000 0x67914 -.nvm 0x9000 0x6a914 +.internal_storage 0x3a000 0x2d948 +.zwave_nvm 0x3000 0x67948 +.nvm 0x9000 0x6a948 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xeda0 0x0 -.debug_info 0xb01c83 0x0 -.debug_abbrev 0x20978 0x0 -.debug_loclists 0x17372 0x0 -.debug_aranges 0x56a0 0x0 -.debug_rnglists 0x33e2 0x0 -.debug_line 0x5c3b3 0x0 -.debug_str 0x82dab 0x0 -.debug_loc 0x2cef7 0x0 -.debug_ranges 0x4d20 0x0 -Total 0xce126c +.debug_frame 0xed7c 0x0 +.debug_info 0xb01f18 0x0 +.debug_abbrev 0x209aa 0x0 +.debug_loclists 0x173a0 0x0 +.debug_aranges 0x5698 0x0 +.debug_rnglists 0x33f2 0x0 +.debug_line 0x5c42a 0x0 +.debug_str 0x82daa 0x0 +.debug_loc 0x2cebf 0x0 +.debug_ranges 0x4d38 0x0 +Total 0xce15cf The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 187684 + 187736 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4210A_REGION_US_LR_size.txt index 5ba720b60e..c5c8ab1535 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4210A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x33fd0 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x8039fd0 -_zaf_cc_config 0x8 0x8039fe0 -_cc_handlers_v3 0x18c 0x8039fe8 -_zw_protocol_cmd_handlers 0x70 0x803a174 -_zw_protocol_cmd_handlers_lr 0x30 0x803a1e4 -.ARM.exidx 0x8 0x803a214 -.copy.table 0xc 0x803a21c -.zero.table 0x0 0x803a228 +.text 0x34028 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803a028 +_zaf_cc_config 0x8 0x803a038 +_cc_handlers_v3 0x18c 0x803a040 +_zw_protocol_cmd_handlers 0x70 0x803a1cc +_zw_protocol_cmd_handlers_lr 0x30 0x803a23c +.ARM.exidx 0x8 0x803a26c +.copy.table 0xc 0x803a274 +.zero.table 0x0 0x803a280 .stack 0x1000 0x20000000 .data 0x4ec 0x20001000 .bss 0xa624 0x200014ec text_application_ram 0x0 0x2000bb10 .heap 0x800 0x2000bb10 -.internal_storage 0x30000 0x803a228 -.zwave_nvm 0x0 0x806a228 -.nvm 0x8000 0x806a228 +.internal_storage 0x30000 0x803a280 +.zwave_nvm 0x0 0x806a280 +.nvm 0x8000 0x806a280 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b90 0x0 -.debug_info 0xb49d67 0x0 -.debug_abbrev 0x25d1f 0x0 -.debug_loclists 0x2a865 0x0 +.debug_frame 0x11b8c 0x0 +.debug_info 0xb4b534 0x0 +.debug_abbrev 0x25d26 0x0 +.debug_loclists 0x2a917 0x0 .debug_aranges 0x6498 0x0 -.debug_rnglists 0x48d6 0x0 -.debug_line 0x71652 0x0 -.debug_str 0x8cf0e 0x0 -.debug_loc 0x2bc7f 0x0 -.debug_ranges 0x4c38 0x0 -Total 0xd5e24d +.debug_rnglists 0x48e9 0x0 +.debug_line 0x71775 0x0 +.debug_str 0x8cf2e 0x0 +.debug_loc 0x2bc47 0x0 +.debug_ranges 0x4c70 0x0 +Total 0xd5fc7d The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 214804 + 214892 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400B_REGION_EU_size.txt index c9bfeb7bf1..826fafc022 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400B_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x34b2c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803ab2c -_zaf_cc_config 0x8 0x803ab3c -_cc_handlers_v3 0x18c 0x803ab44 -_zw_protocol_cmd_handlers 0x70 0x803acd0 -_zw_protocol_cmd_handlers_lr 0x30 0x803ad40 -.ARM.exidx 0x8 0x803ad70 -.copy.table 0xc 0x803ad78 -.zero.table 0x0 0x803ad84 +.text 0x34b84 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803ab84 +_zaf_cc_config 0x8 0x803ab94 +_cc_handlers_v3 0x18c 0x803ab9c +_zw_protocol_cmd_handlers 0x70 0x803ad28 +_zw_protocol_cmd_handlers_lr 0x30 0x803ad98 +.ARM.exidx 0x8 0x803adc8 +.copy.table 0xc 0x803add0 +.zero.table 0x0 0x803addc .stack 0x1000 0x20000000 .data 0x4e8 0x20001000 .bss 0xa58c 0x200014e8 text_application_ram 0x0 0x2000ba74 .heap 0x800 0x2000ba78 -.internal_storage 0x30000 0x803ad84 -.zwave_nvm 0x0 0x806ad84 -.nvm 0x8000 0x806ad84 +.internal_storage 0x30000 0x803addc +.zwave_nvm 0x0 0x806addc +.nvm 0x8000 0x806addc .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11c54 0x0 -.debug_info 0xb4e6d6 0x0 -.debug_abbrev 0x26066 0x0 -.debug_loclists 0x2ad94 0x0 +.debug_frame 0x11c50 0x0 +.debug_info 0xb4fea7 0x0 +.debug_abbrev 0x2606d 0x0 +.debug_loclists 0x2ae46 0x0 .debug_aranges 0x6518 0x0 -.debug_rnglists 0x492b 0x0 -.debug_line 0x71a16 0x0 -.debug_str 0x8e7a7 0x0 -.debug_loc 0x2bb77 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd65bf8 +.debug_rnglists 0x493e 0x0 +.debug_line 0x71b39 0x0 +.debug_str 0x8e7c7 0x0 +.debug_loc 0x2bb3f 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd6762c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217708 + 217796 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400B_REGION_US_LR_size.txt index 61cc370bbe..0b748f35f7 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x34b2c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803ab2c -_zaf_cc_config 0x8 0x803ab3c -_cc_handlers_v3 0x18c 0x803ab44 -_zw_protocol_cmd_handlers 0x70 0x803acd0 -_zw_protocol_cmd_handlers_lr 0x30 0x803ad40 -.ARM.exidx 0x8 0x803ad70 -.copy.table 0xc 0x803ad78 -.zero.table 0x0 0x803ad84 +.text 0x34b84 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803ab84 +_zaf_cc_config 0x8 0x803ab94 +_cc_handlers_v3 0x18c 0x803ab9c +_zw_protocol_cmd_handlers 0x70 0x803ad28 +_zw_protocol_cmd_handlers_lr 0x30 0x803ad98 +.ARM.exidx 0x8 0x803adc8 +.copy.table 0xc 0x803add0 +.zero.table 0x0 0x803addc .stack 0x1000 0x20000000 .data 0x4e8 0x20001000 .bss 0xa58c 0x200014e8 text_application_ram 0x0 0x2000ba74 .heap 0x800 0x2000ba78 -.internal_storage 0x30000 0x803ad84 -.zwave_nvm 0x0 0x806ad84 -.nvm 0x8000 0x806ad84 +.internal_storage 0x30000 0x803addc +.zwave_nvm 0x0 0x806addc +.nvm 0x8000 0x806addc .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11c54 0x0 -.debug_info 0xb4e6d6 0x0 -.debug_abbrev 0x26066 0x0 -.debug_loclists 0x2ad94 0x0 +.debug_frame 0x11c50 0x0 +.debug_info 0xb4fea7 0x0 +.debug_abbrev 0x2606d 0x0 +.debug_loclists 0x2ae46 0x0 .debug_aranges 0x6518 0x0 -.debug_rnglists 0x492b 0x0 -.debug_line 0x71a16 0x0 -.debug_str 0x8e79d 0x0 -.debug_loc 0x2bb77 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd65bee +.debug_rnglists 0x493e 0x0 +.debug_line 0x71b39 0x0 +.debug_str 0x8e7bd 0x0 +.debug_loc 0x2bb3f 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd67622 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217708 + 217796 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400B_REGION_US_size.txt index c9bfeb7bf1..826fafc022 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400B_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x34b2c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803ab2c -_zaf_cc_config 0x8 0x803ab3c -_cc_handlers_v3 0x18c 0x803ab44 -_zw_protocol_cmd_handlers 0x70 0x803acd0 -_zw_protocol_cmd_handlers_lr 0x30 0x803ad40 -.ARM.exidx 0x8 0x803ad70 -.copy.table 0xc 0x803ad78 -.zero.table 0x0 0x803ad84 +.text 0x34b84 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803ab84 +_zaf_cc_config 0x8 0x803ab94 +_cc_handlers_v3 0x18c 0x803ab9c +_zw_protocol_cmd_handlers 0x70 0x803ad28 +_zw_protocol_cmd_handlers_lr 0x30 0x803ad98 +.ARM.exidx 0x8 0x803adc8 +.copy.table 0xc 0x803add0 +.zero.table 0x0 0x803addc .stack 0x1000 0x20000000 .data 0x4e8 0x20001000 .bss 0xa58c 0x200014e8 text_application_ram 0x0 0x2000ba74 .heap 0x800 0x2000ba78 -.internal_storage 0x30000 0x803ad84 -.zwave_nvm 0x0 0x806ad84 -.nvm 0x8000 0x806ad84 +.internal_storage 0x30000 0x803addc +.zwave_nvm 0x0 0x806addc +.nvm 0x8000 0x806addc .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11c54 0x0 -.debug_info 0xb4e6d6 0x0 -.debug_abbrev 0x26066 0x0 -.debug_loclists 0x2ad94 0x0 +.debug_frame 0x11c50 0x0 +.debug_info 0xb4fea7 0x0 +.debug_abbrev 0x2606d 0x0 +.debug_loclists 0x2ae46 0x0 .debug_aranges 0x6518 0x0 -.debug_rnglists 0x492b 0x0 -.debug_line 0x71a16 0x0 -.debug_str 0x8e7a7 0x0 -.debug_loc 0x2bb77 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd65bf8 +.debug_rnglists 0x493e 0x0 +.debug_line 0x71b39 0x0 +.debug_str 0x8e7c7 0x0 +.debug_loc 0x2bb3f 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd6762c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217708 + 217796 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400C_REGION_EU_size.txt index d71a6cbeee..e810c43a59 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x34b2c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803ab2c -_zaf_cc_config 0x8 0x803ab3c -_cc_handlers_v3 0x18c 0x803ab44 -_zw_protocol_cmd_handlers 0x70 0x803acd0 -_zw_protocol_cmd_handlers_lr 0x30 0x803ad40 -.ARM.exidx 0x8 0x803ad70 -.copy.table 0xc 0x803ad78 -.zero.table 0x0 0x803ad84 +.text 0x34b84 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803ab84 +_zaf_cc_config 0x8 0x803ab94 +_cc_handlers_v3 0x18c 0x803ab9c +_zw_protocol_cmd_handlers 0x70 0x803ad28 +_zw_protocol_cmd_handlers_lr 0x30 0x803ad98 +.ARM.exidx 0x8 0x803adc8 +.copy.table 0xc 0x803add0 +.zero.table 0x0 0x803addc .stack 0x1000 0x20000000 .data 0x4e8 0x20001000 .bss 0xa58c 0x200014e8 text_application_ram 0x0 0x2000ba74 .heap 0x800 0x2000ba78 -.internal_storage 0x30000 0x803ad84 -.zwave_nvm 0x0 0x806ad84 -.nvm 0x8000 0x806ad84 +.internal_storage 0x30000 0x803addc +.zwave_nvm 0x0 0x806addc +.nvm 0x8000 0x806addc .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11c68 0x0 -.debug_info 0xb4e665 0x0 -.debug_abbrev 0x26070 0x0 -.debug_loclists 0x2ad60 0x0 +.debug_frame 0x11c64 0x0 +.debug_info 0xb4fe36 0x0 +.debug_abbrev 0x26077 0x0 +.debug_loclists 0x2ae12 0x0 .debug_aranges 0x6520 0x0 -.debug_rnglists 0x4954 0x0 -.debug_line 0x71a0b 0x0 -.debug_str 0x8e7a7 0x0 -.debug_loc 0x2bb77 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd65b97 +.debug_rnglists 0x4967 0x0 +.debug_line 0x71b2e 0x0 +.debug_str 0x8e7c7 0x0 +.debug_loc 0x2bb3f 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd675cb The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217708 + 217796 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400C_REGION_US_LR_size.txt index e51109ed8a..a76276555d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x34b2c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803ab2c -_zaf_cc_config 0x8 0x803ab3c -_cc_handlers_v3 0x18c 0x803ab44 -_zw_protocol_cmd_handlers 0x70 0x803acd0 -_zw_protocol_cmd_handlers_lr 0x30 0x803ad40 -.ARM.exidx 0x8 0x803ad70 -.copy.table 0xc 0x803ad78 -.zero.table 0x0 0x803ad84 +.text 0x34b84 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803ab84 +_zaf_cc_config 0x8 0x803ab94 +_cc_handlers_v3 0x18c 0x803ab9c +_zw_protocol_cmd_handlers 0x70 0x803ad28 +_zw_protocol_cmd_handlers_lr 0x30 0x803ad98 +.ARM.exidx 0x8 0x803adc8 +.copy.table 0xc 0x803add0 +.zero.table 0x0 0x803addc .stack 0x1000 0x20000000 .data 0x4e8 0x20001000 .bss 0xa58c 0x200014e8 text_application_ram 0x0 0x2000ba74 .heap 0x800 0x2000ba78 -.internal_storage 0x30000 0x803ad84 -.zwave_nvm 0x0 0x806ad84 -.nvm 0x8000 0x806ad84 +.internal_storage 0x30000 0x803addc +.zwave_nvm 0x0 0x806addc +.nvm 0x8000 0x806addc .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11c68 0x0 -.debug_info 0xb4e665 0x0 -.debug_abbrev 0x26070 0x0 -.debug_loclists 0x2ad60 0x0 +.debug_frame 0x11c64 0x0 +.debug_info 0xb4fe36 0x0 +.debug_abbrev 0x26077 0x0 +.debug_loclists 0x2ae12 0x0 .debug_aranges 0x6520 0x0 -.debug_rnglists 0x4954 0x0 -.debug_line 0x71a0b 0x0 -.debug_str 0x8e79d 0x0 -.debug_loc 0x2bb77 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd65b8d +.debug_rnglists 0x4967 0x0 +.debug_line 0x71b2e 0x0 +.debug_str 0x8e7bd 0x0 +.debug_loc 0x2bb3f 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd675c1 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217708 + 217796 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400C_REGION_US_size.txt index d71a6cbeee..e810c43a59 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4400C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x34b2c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803ab2c -_zaf_cc_config 0x8 0x803ab3c -_cc_handlers_v3 0x18c 0x803ab44 -_zw_protocol_cmd_handlers 0x70 0x803acd0 -_zw_protocol_cmd_handlers_lr 0x30 0x803ad40 -.ARM.exidx 0x8 0x803ad70 -.copy.table 0xc 0x803ad78 -.zero.table 0x0 0x803ad84 +.text 0x34b84 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803ab84 +_zaf_cc_config 0x8 0x803ab94 +_cc_handlers_v3 0x18c 0x803ab9c +_zw_protocol_cmd_handlers 0x70 0x803ad28 +_zw_protocol_cmd_handlers_lr 0x30 0x803ad98 +.ARM.exidx 0x8 0x803adc8 +.copy.table 0xc 0x803add0 +.zero.table 0x0 0x803addc .stack 0x1000 0x20000000 .data 0x4e8 0x20001000 .bss 0xa58c 0x200014e8 text_application_ram 0x0 0x2000ba74 .heap 0x800 0x2000ba78 -.internal_storage 0x30000 0x803ad84 -.zwave_nvm 0x0 0x806ad84 -.nvm 0x8000 0x806ad84 +.internal_storage 0x30000 0x803addc +.zwave_nvm 0x0 0x806addc +.nvm 0x8000 0x806addc .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11c68 0x0 -.debug_info 0xb4e665 0x0 -.debug_abbrev 0x26070 0x0 -.debug_loclists 0x2ad60 0x0 +.debug_frame 0x11c64 0x0 +.debug_info 0xb4fe36 0x0 +.debug_abbrev 0x26077 0x0 +.debug_loclists 0x2ae12 0x0 .debug_aranges 0x6520 0x0 -.debug_rnglists 0x4954 0x0 -.debug_line 0x71a0b 0x0 -.debug_str 0x8e7a7 0x0 -.debug_loc 0x2bb77 0x0 -.debug_ranges 0x4c50 0x0 -Total 0xd65b97 +.debug_rnglists 0x4967 0x0 +.debug_line 0x71b2e 0x0 +.debug_str 0x8e7c7 0x0 +.debug_loc 0x2bb3f 0x0 +.debug_ranges 0x4c88 0x0 +Total 0xd675cb The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217708 + 217796 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4401B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4401B_REGION_US_LR_size.txt index 618d1c71a6..7291f32674 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4401B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4401B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x34b6c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803ab6c -_zaf_cc_config 0x8 0x803ab7c -_cc_handlers_v3 0x18c 0x803ab84 -_zw_protocol_cmd_handlers 0x70 0x803ad10 -_zw_protocol_cmd_handlers_lr 0x30 0x803ad80 -.ARM.exidx 0x8 0x803adb0 -.copy.table 0xc 0x803adb8 -.zero.table 0x0 0x803adc4 +.text 0x34bc4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803abc4 +_zaf_cc_config 0x8 0x803abd4 +_cc_handlers_v3 0x18c 0x803abdc +_zw_protocol_cmd_handlers 0x70 0x803ad68 +_zw_protocol_cmd_handlers_lr 0x30 0x803add8 +.ARM.exidx 0x8 0x803ae08 +.copy.table 0xc 0x803ae10 +.zero.table 0x0 0x803ae1c .stack 0x1000 0x20000000 .data 0x4e8 0x20001000 .bss 0xa58c 0x200014e8 text_application_ram 0x0 0x2000ba74 .heap 0x800 0x2000ba78 -.internal_storage 0x30000 0x803adc4 -.zwave_nvm 0x0 0x806adc4 -.nvm 0x8000 0x806adc4 +.internal_storage 0x30000 0x803ae1c +.zwave_nvm 0x0 0x806ae1c +.nvm 0x8000 0x806ae1c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11c5c 0x0 -.debug_info 0xb4e6a2 0x0 -.debug_abbrev 0x26066 0x0 -.debug_loclists 0x2ad94 0x0 +.debug_frame 0x11c58 0x0 +.debug_info 0xb4fe73 0x0 +.debug_abbrev 0x2606d 0x0 +.debug_loclists 0x2ae46 0x0 .debug_aranges 0x6518 0x0 -.debug_rnglists 0x492b 0x0 -.debug_line 0x719ec 0x0 -.debug_str 0x8e79d 0x0 -.debug_loc 0x2bb6c 0x0 -.debug_ranges 0x4c38 0x0 -Total 0xd65bb5 +.debug_rnglists 0x493e 0x0 +.debug_line 0x71b0f 0x0 +.debug_str 0x8e7bd 0x0 +.debug_loc 0x2bb34 0x0 +.debug_ranges 0x4c70 0x0 +Total 0xd675e9 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217772 + 217860 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4401C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4401C_REGION_EU_size.txt index 124888722e..bec7699341 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4401C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4401C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x34b6c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803ab6c -_zaf_cc_config 0x8 0x803ab7c -_cc_handlers_v3 0x18c 0x803ab84 -_zw_protocol_cmd_handlers 0x70 0x803ad10 -_zw_protocol_cmd_handlers_lr 0x30 0x803ad80 -.ARM.exidx 0x8 0x803adb0 -.copy.table 0xc 0x803adb8 -.zero.table 0x0 0x803adc4 +.text 0x34bc4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803abc4 +_zaf_cc_config 0x8 0x803abd4 +_cc_handlers_v3 0x18c 0x803abdc +_zw_protocol_cmd_handlers 0x70 0x803ad68 +_zw_protocol_cmd_handlers_lr 0x30 0x803add8 +.ARM.exidx 0x8 0x803ae08 +.copy.table 0xc 0x803ae10 +.zero.table 0x0 0x803ae1c .stack 0x1000 0x20000000 .data 0x4e8 0x20001000 .bss 0xa58c 0x200014e8 text_application_ram 0x0 0x2000ba74 .heap 0x800 0x2000ba78 -.internal_storage 0x30000 0x803adc4 -.zwave_nvm 0x0 0x806adc4 -.nvm 0x8000 0x806adc4 +.internal_storage 0x30000 0x803ae1c +.zwave_nvm 0x0 0x806ae1c +.nvm 0x8000 0x806ae1c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11c70 0x0 -.debug_info 0xb4e631 0x0 -.debug_abbrev 0x26070 0x0 -.debug_loclists 0x2ad60 0x0 +.debug_frame 0x11c6c 0x0 +.debug_info 0xb4fe02 0x0 +.debug_abbrev 0x26077 0x0 +.debug_loclists 0x2ae12 0x0 .debug_aranges 0x6520 0x0 -.debug_rnglists 0x4954 0x0 -.debug_line 0x719e1 0x0 -.debug_str 0x8e7a7 0x0 -.debug_loc 0x2bb6c 0x0 -.debug_ranges 0x4c38 0x0 -Total 0xd65b5e +.debug_rnglists 0x4967 0x0 +.debug_line 0x71b04 0x0 +.debug_str 0x8e7c7 0x0 +.debug_loc 0x2bb34 0x0 +.debug_ranges 0x4c70 0x0 +Total 0xd67592 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217772 + 217860 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4401C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4401C_REGION_US_LR_size.txt index 24ce2efb47..cd24cbd9d0 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4401C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4401C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x34b6c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803ab6c -_zaf_cc_config 0x8 0x803ab7c -_cc_handlers_v3 0x18c 0x803ab84 -_zw_protocol_cmd_handlers 0x70 0x803ad10 -_zw_protocol_cmd_handlers_lr 0x30 0x803ad80 -.ARM.exidx 0x8 0x803adb0 -.copy.table 0xc 0x803adb8 -.zero.table 0x0 0x803adc4 +.text 0x34bc4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803abc4 +_zaf_cc_config 0x8 0x803abd4 +_cc_handlers_v3 0x18c 0x803abdc +_zw_protocol_cmd_handlers 0x70 0x803ad68 +_zw_protocol_cmd_handlers_lr 0x30 0x803add8 +.ARM.exidx 0x8 0x803ae08 +.copy.table 0xc 0x803ae10 +.zero.table 0x0 0x803ae1c .stack 0x1000 0x20000000 .data 0x4e8 0x20001000 .bss 0xa58c 0x200014e8 text_application_ram 0x0 0x2000ba74 .heap 0x800 0x2000ba78 -.internal_storage 0x30000 0x803adc4 -.zwave_nvm 0x0 0x806adc4 -.nvm 0x8000 0x806adc4 +.internal_storage 0x30000 0x803ae1c +.zwave_nvm 0x0 0x806ae1c +.nvm 0x8000 0x806ae1c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11c70 0x0 -.debug_info 0xb4e631 0x0 -.debug_abbrev 0x26070 0x0 -.debug_loclists 0x2ad60 0x0 +.debug_frame 0x11c6c 0x0 +.debug_info 0xb4fe02 0x0 +.debug_abbrev 0x26077 0x0 +.debug_loclists 0x2ae12 0x0 .debug_aranges 0x6520 0x0 -.debug_rnglists 0x4954 0x0 -.debug_line 0x719e1 0x0 -.debug_str 0x8e79d 0x0 -.debug_loc 0x2bb6c 0x0 -.debug_ranges 0x4c38 0x0 -Total 0xd65b54 +.debug_rnglists 0x4967 0x0 +.debug_line 0x71b04 0x0 +.debug_str 0x8e7bd 0x0 +.debug_loc 0x2bb34 0x0 +.debug_ranges 0x4c70 0x0 +Total 0xd67588 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217772 + 217860 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4401C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4401C_REGION_US_size.txt index 124888722e..bec7699341 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4401C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4401C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x34b6c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803ab6c -_zaf_cc_config 0x8 0x803ab7c -_cc_handlers_v3 0x18c 0x803ab84 -_zw_protocol_cmd_handlers 0x70 0x803ad10 -_zw_protocol_cmd_handlers_lr 0x30 0x803ad80 -.ARM.exidx 0x8 0x803adb0 -.copy.table 0xc 0x803adb8 -.zero.table 0x0 0x803adc4 +.text 0x34bc4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803abc4 +_zaf_cc_config 0x8 0x803abd4 +_cc_handlers_v3 0x18c 0x803abdc +_zw_protocol_cmd_handlers 0x70 0x803ad68 +_zw_protocol_cmd_handlers_lr 0x30 0x803add8 +.ARM.exidx 0x8 0x803ae08 +.copy.table 0xc 0x803ae10 +.zero.table 0x0 0x803ae1c .stack 0x1000 0x20000000 .data 0x4e8 0x20001000 .bss 0xa58c 0x200014e8 text_application_ram 0x0 0x2000ba74 .heap 0x800 0x2000ba78 -.internal_storage 0x30000 0x803adc4 -.zwave_nvm 0x0 0x806adc4 -.nvm 0x8000 0x806adc4 +.internal_storage 0x30000 0x803ae1c +.zwave_nvm 0x0 0x806ae1c +.nvm 0x8000 0x806ae1c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11c70 0x0 -.debug_info 0xb4e631 0x0 -.debug_abbrev 0x26070 0x0 -.debug_loclists 0x2ad60 0x0 +.debug_frame 0x11c6c 0x0 +.debug_info 0xb4fe02 0x0 +.debug_abbrev 0x26077 0x0 +.debug_loclists 0x2ae12 0x0 .debug_aranges 0x6520 0x0 -.debug_rnglists 0x4954 0x0 -.debug_line 0x719e1 0x0 -.debug_str 0x8e7a7 0x0 -.debug_loc 0x2bb6c 0x0 -.debug_ranges 0x4c38 0x0 -Total 0xd65b5e +.debug_rnglists 0x4967 0x0 +.debug_line 0x71b04 0x0 +.debug_str 0x8e7c7 0x0 +.debug_loc 0x2bb34 0x0 +.debug_ranges 0x4c70 0x0 +Total 0xd67592 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 217772 + 217860 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_EU_size.txt index af7d0c90dd..1036e72096 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x304d4 0x0 -_zaf_event_distributor_cc_event_handler 0x30 0x304d4 -_zaf_cc_config 0x8 0x30504 -_cc_handlers_v3 0x240 0x3050c -_zw_protocol_cmd_handlers 0x70 0x3074c -_zw_protocol_cmd_handlers_lr 0x30 0x307bc -.ARM.exidx 0x8 0x307ec -.copy.table 0xc 0x307f4 -.zero.table 0x0 0x30800 +.text 0x304c8 0x0 +_zaf_event_distributor_cc_event_handler 0x30 0x304c8 +_zaf_cc_config 0x8 0x304f8 +_cc_handlers_v3 0x240 0x30500 +_zw_protocol_cmd_handlers 0x70 0x30740 +_zw_protocol_cmd_handlers_lr 0x30 0x307b0 +.ARM.exidx 0x8 0x307e0 +.copy.table 0xc 0x307e8 +.zero.table 0x0 0x307f4 .stack 0x1000 0x20000000 .data 0x41c 0x20001000 .bss 0x9fd4 0x2000141c text_application_ram 0x0 0x2000b3f0 .heap 0x800 0x2000b3f0 -.internal_storage 0x3a000 0x30800 -.zwave_nvm 0x3000 0x6a800 -.nvm 0x9000 0x6d800 +.internal_storage 0x3a000 0x307f4 +.zwave_nvm 0x3000 0x6a7f4 +.nvm 0x9000 0x6d7f4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf730 0x0 -.debug_info 0xcfbadf 0x0 -.debug_abbrev 0x22bf3 0x0 -.debug_loclists 0x18b68 0x0 -.debug_aranges 0x5a98 0x0 -.debug_rnglists 0x37b5 0x0 -.debug_line 0x60d3d 0x0 -.debug_str 0x86fb8 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xeec678 +.debug_frame 0xf704 0x0 +.debug_info 0xcfbcb9 0x0 +.debug_abbrev 0x22bae 0x0 +.debug_loclists 0x18b54 0x0 +.debug_aranges 0x5a90 0x0 +.debug_rnglists 0x37c4 0x0 +.debug_line 0x60d4d 0x0 +.debug_str 0x86f80 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xeec780 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 199708 + 199696 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_US_LR_size.txt index ec2d943b27..08420a49a3 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x304d4 0x0 -_zaf_event_distributor_cc_event_handler 0x30 0x304d4 -_zaf_cc_config 0x8 0x30504 -_cc_handlers_v3 0x240 0x3050c -_zw_protocol_cmd_handlers 0x70 0x3074c -_zw_protocol_cmd_handlers_lr 0x30 0x307bc -.ARM.exidx 0x8 0x307ec -.copy.table 0xc 0x307f4 -.zero.table 0x0 0x30800 +.text 0x304c8 0x0 +_zaf_event_distributor_cc_event_handler 0x30 0x304c8 +_zaf_cc_config 0x8 0x304f8 +_cc_handlers_v3 0x240 0x30500 +_zw_protocol_cmd_handlers 0x70 0x30740 +_zw_protocol_cmd_handlers_lr 0x30 0x307b0 +.ARM.exidx 0x8 0x307e0 +.copy.table 0xc 0x307e8 +.zero.table 0x0 0x307f4 .stack 0x1000 0x20000000 .data 0x41c 0x20001000 .bss 0x9fd4 0x2000141c text_application_ram 0x0 0x2000b3f0 .heap 0x800 0x2000b3f0 -.internal_storage 0x3a000 0x30800 -.zwave_nvm 0x3000 0x6a800 -.nvm 0x9000 0x6d800 +.internal_storage 0x3a000 0x307f4 +.zwave_nvm 0x3000 0x6a7f4 +.nvm 0x9000 0x6d7f4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf730 0x0 -.debug_info 0xcfbadf 0x0 -.debug_abbrev 0x22bf3 0x0 -.debug_loclists 0x18b68 0x0 -.debug_aranges 0x5a98 0x0 -.debug_rnglists 0x37b5 0x0 -.debug_line 0x60d3d 0x0 -.debug_str 0x86fae 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xeec66e +.debug_frame 0xf704 0x0 +.debug_info 0xcfbcb9 0x0 +.debug_abbrev 0x22bae 0x0 +.debug_loclists 0x18b54 0x0 +.debug_aranges 0x5a90 0x0 +.debug_rnglists 0x37c4 0x0 +.debug_line 0x60d4d 0x0 +.debug_str 0x86f76 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xeec776 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 199708 + 199696 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_US_size.txt index af7d0c90dd..1036e72096 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x304d4 0x0 -_zaf_event_distributor_cc_event_handler 0x30 0x304d4 -_zaf_cc_config 0x8 0x30504 -_cc_handlers_v3 0x240 0x3050c -_zw_protocol_cmd_handlers 0x70 0x3074c -_zw_protocol_cmd_handlers_lr 0x30 0x307bc -.ARM.exidx 0x8 0x307ec -.copy.table 0xc 0x307f4 -.zero.table 0x0 0x30800 +.text 0x304c8 0x0 +_zaf_event_distributor_cc_event_handler 0x30 0x304c8 +_zaf_cc_config 0x8 0x304f8 +_cc_handlers_v3 0x240 0x30500 +_zw_protocol_cmd_handlers 0x70 0x30740 +_zw_protocol_cmd_handlers_lr 0x30 0x307b0 +.ARM.exidx 0x8 0x307e0 +.copy.table 0xc 0x307e8 +.zero.table 0x0 0x307f4 .stack 0x1000 0x20000000 .data 0x41c 0x20001000 .bss 0x9fd4 0x2000141c text_application_ram 0x0 0x2000b3f0 .heap 0x800 0x2000b3f0 -.internal_storage 0x3a000 0x30800 -.zwave_nvm 0x3000 0x6a800 -.nvm 0x9000 0x6d800 +.internal_storage 0x3a000 0x307f4 +.zwave_nvm 0x3000 0x6a7f4 +.nvm 0x9000 0x6d7f4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf730 0x0 -.debug_info 0xcfbadf 0x0 -.debug_abbrev 0x22bf3 0x0 -.debug_loclists 0x18b68 0x0 -.debug_aranges 0x5a98 0x0 -.debug_rnglists 0x37b5 0x0 -.debug_line 0x60d3d 0x0 -.debug_str 0x86fb8 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xeec678 +.debug_frame 0xf704 0x0 +.debug_info 0xcfbcb9 0x0 +.debug_abbrev 0x22bae 0x0 +.debug_loclists 0x18b54 0x0 +.debug_aranges 0x5a90 0x0 +.debug_rnglists 0x37c4 0x0 +.debug_line 0x60d4d 0x0 +.debug_str 0x86f80 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xeec780 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 199708 + 199696 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_EU_size.txt index 5b00425811..fde0571d5c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37350 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803d350 -_zaf_cc_config 0x8 0x803d380 -_cc_handlers_v3 0x240 0x803d388 -_zw_protocol_cmd_handlers 0x70 0x803d5c8 -_zw_protocol_cmd_handlers_lr 0x30 0x803d638 -.ARM.exidx 0x8 0x803d668 -.copy.table 0xc 0x803d670 -.zero.table 0x0 0x803d67c +.text 0x37388 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803d388 +_zaf_cc_config 0x8 0x803d3b8 +_cc_handlers_v3 0x240 0x803d3c0 +_zw_protocol_cmd_handlers 0x70 0x803d600 +_zw_protocol_cmd_handlers_lr 0x30 0x803d670 +.ARM.exidx 0x8 0x803d6a0 +.copy.table 0xc 0x803d6a8 +.zero.table 0x0 0x803d6b4 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xab48 0x2000159c text_application_ram 0x0 0x2000c0e4 .heap 0x800 0x2000c0e8 -.internal_storage 0x30000 0x803d67c -.zwave_nvm 0x0 0x806d67c -.nvm 0x8000 0x806d67c +.internal_storage 0x30000 0x803d6b4 +.zwave_nvm 0x0 0x806d6b4 +.nvm 0x8000 0x806d6b4 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12818 0x0 -.debug_info 0xd46251 0x0 -.debug_abbrev 0x284d1 0x0 -.debug_loclists 0x2cede 0x0 +.debug_frame 0x1280c 0x0 +.debug_info 0xd47969 0x0 +.debug_abbrev 0x2845c 0x0 +.debug_loclists 0x2cf51 0x0 .debug_aranges 0x6958 0x0 -.debug_rnglists 0x4ef7 0x0 -.debug_line 0x777cf 0x0 -.debug_str 0x9079d 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf6eb40 +.debug_rnglists 0x4efd 0x0 +.debug_line 0x778a4 0x0 +.debug_str 0x90786 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf70346 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228376 + 228432 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_US_LR_size.txt index 602c75834b..d81c5ff919 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37350 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803d350 -_zaf_cc_config 0x8 0x803d380 -_cc_handlers_v3 0x240 0x803d388 -_zw_protocol_cmd_handlers 0x70 0x803d5c8 -_zw_protocol_cmd_handlers_lr 0x30 0x803d638 -.ARM.exidx 0x8 0x803d668 -.copy.table 0xc 0x803d670 -.zero.table 0x0 0x803d67c +.text 0x37388 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803d388 +_zaf_cc_config 0x8 0x803d3b8 +_cc_handlers_v3 0x240 0x803d3c0 +_zw_protocol_cmd_handlers 0x70 0x803d600 +_zw_protocol_cmd_handlers_lr 0x30 0x803d670 +.ARM.exidx 0x8 0x803d6a0 +.copy.table 0xc 0x803d6a8 +.zero.table 0x0 0x803d6b4 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xab48 0x2000159c text_application_ram 0x0 0x2000c0e4 .heap 0x800 0x2000c0e8 -.internal_storage 0x30000 0x803d67c -.zwave_nvm 0x0 0x806d67c -.nvm 0x8000 0x806d67c +.internal_storage 0x30000 0x803d6b4 +.zwave_nvm 0x0 0x806d6b4 +.nvm 0x8000 0x806d6b4 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12818 0x0 -.debug_info 0xd46251 0x0 -.debug_abbrev 0x284d1 0x0 -.debug_loclists 0x2cede 0x0 +.debug_frame 0x1280c 0x0 +.debug_info 0xd47969 0x0 +.debug_abbrev 0x2845c 0x0 +.debug_loclists 0x2cf51 0x0 .debug_aranges 0x6958 0x0 -.debug_rnglists 0x4ef7 0x0 -.debug_line 0x777cf 0x0 -.debug_str 0x90793 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf6eb36 +.debug_rnglists 0x4efd 0x0 +.debug_line 0x778a4 0x0 +.debug_str 0x9077c 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf7033c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228376 + 228432 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_US_size.txt index 5b00425811..fde0571d5c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37350 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803d350 -_zaf_cc_config 0x8 0x803d380 -_cc_handlers_v3 0x240 0x803d388 -_zw_protocol_cmd_handlers 0x70 0x803d5c8 -_zw_protocol_cmd_handlers_lr 0x30 0x803d638 -.ARM.exidx 0x8 0x803d668 -.copy.table 0xc 0x803d670 -.zero.table 0x0 0x803d67c +.text 0x37388 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803d388 +_zaf_cc_config 0x8 0x803d3b8 +_cc_handlers_v3 0x240 0x803d3c0 +_zw_protocol_cmd_handlers 0x70 0x803d600 +_zw_protocol_cmd_handlers_lr 0x30 0x803d670 +.ARM.exidx 0x8 0x803d6a0 +.copy.table 0xc 0x803d6a8 +.zero.table 0x0 0x803d6b4 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xab48 0x2000159c text_application_ram 0x0 0x2000c0e4 .heap 0x800 0x2000c0e8 -.internal_storage 0x30000 0x803d67c -.zwave_nvm 0x0 0x806d67c -.nvm 0x8000 0x806d67c +.internal_storage 0x30000 0x803d6b4 +.zwave_nvm 0x0 0x806d6b4 +.nvm 0x8000 0x806d6b4 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12818 0x0 -.debug_info 0xd46251 0x0 -.debug_abbrev 0x284d1 0x0 -.debug_loclists 0x2cede 0x0 +.debug_frame 0x1280c 0x0 +.debug_info 0xd47969 0x0 +.debug_abbrev 0x2845c 0x0 +.debug_loclists 0x2cf51 0x0 .debug_aranges 0x6958 0x0 -.debug_rnglists 0x4ef7 0x0 -.debug_line 0x777cf 0x0 -.debug_str 0x9079d 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf6eb40 +.debug_rnglists 0x4efd 0x0 +.debug_line 0x778a4 0x0 +.debug_str 0x90786 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf70346 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228376 + 228432 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_EU_size.txt index 7023581114..266472eba0 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37424 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803d424 -_zaf_cc_config 0x8 0x803d454 -_cc_handlers_v3 0x240 0x803d45c -_zw_protocol_cmd_handlers 0x70 0x803d69c -_zw_protocol_cmd_handlers_lr 0x30 0x803d70c -.ARM.exidx 0x8 0x803d73c -.copy.table 0xc 0x803d744 -.zero.table 0x0 0x803d750 +.text 0x3743c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803d43c +_zaf_cc_config 0x8 0x803d46c +_cc_handlers_v3 0x240 0x803d474 +_zw_protocol_cmd_handlers 0x70 0x803d6b4 +_zw_protocol_cmd_handlers_lr 0x30 0x803d724 +.ARM.exidx 0x8 0x803d754 +.copy.table 0xc 0x803d75c +.zero.table 0x0 0x803d768 .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xab44 0x200015a0 text_application_ram 0x0 0x2000c0e4 .heap 0x800 0x2000c0e8 -.internal_storage 0x30000 0x803d750 -.zwave_nvm 0x0 0x806d750 -.nvm 0x8000 0x806d750 +.internal_storage 0x30000 0x803d768 +.zwave_nvm 0x0 0x806d768 +.nvm 0x8000 0x806d768 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12848 0x0 -.debug_info 0xd464c9 0x0 -.debug_abbrev 0x285d3 0x0 -.debug_loclists 0x2cede 0x0 +.debug_frame 0x1283c 0x0 +.debug_info 0xd47be1 0x0 +.debug_abbrev 0x2855e 0x0 +.debug_loclists 0x2cf51 0x0 .debug_aranges 0x6978 0x0 -.debug_rnglists 0x4f0a 0x0 -.debug_line 0x779a8 0x0 -.debug_str 0x90970 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf6f39d +.debug_rnglists 0x4f10 0x0 +.debug_line 0x77a7d 0x0 +.debug_str 0x90959 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf70b83 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228592 + 228616 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_US_LR_size.txt index c805318d37..a6f561fe3a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37424 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803d424 -_zaf_cc_config 0x8 0x803d454 -_cc_handlers_v3 0x240 0x803d45c -_zw_protocol_cmd_handlers 0x70 0x803d69c -_zw_protocol_cmd_handlers_lr 0x30 0x803d70c -.ARM.exidx 0x8 0x803d73c -.copy.table 0xc 0x803d744 -.zero.table 0x0 0x803d750 +.text 0x3743c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803d43c +_zaf_cc_config 0x8 0x803d46c +_cc_handlers_v3 0x240 0x803d474 +_zw_protocol_cmd_handlers 0x70 0x803d6b4 +_zw_protocol_cmd_handlers_lr 0x30 0x803d724 +.ARM.exidx 0x8 0x803d754 +.copy.table 0xc 0x803d75c +.zero.table 0x0 0x803d768 .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xab44 0x200015a0 text_application_ram 0x0 0x2000c0e4 .heap 0x800 0x2000c0e8 -.internal_storage 0x30000 0x803d750 -.zwave_nvm 0x0 0x806d750 -.nvm 0x8000 0x806d750 +.internal_storage 0x30000 0x803d768 +.zwave_nvm 0x0 0x806d768 +.nvm 0x8000 0x806d768 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12848 0x0 -.debug_info 0xd464c9 0x0 -.debug_abbrev 0x285d3 0x0 -.debug_loclists 0x2cede 0x0 +.debug_frame 0x1283c 0x0 +.debug_info 0xd47be1 0x0 +.debug_abbrev 0x2855e 0x0 +.debug_loclists 0x2cf51 0x0 .debug_aranges 0x6978 0x0 -.debug_rnglists 0x4f0a 0x0 -.debug_line 0x779a8 0x0 -.debug_str 0x90966 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf6f393 +.debug_rnglists 0x4f10 0x0 +.debug_line 0x77a7d 0x0 +.debug_str 0x9094f 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf70b79 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228592 + 228616 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_US_size.txt index 7023581114..266472eba0 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37424 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803d424 -_zaf_cc_config 0x8 0x803d454 -_cc_handlers_v3 0x240 0x803d45c -_zw_protocol_cmd_handlers 0x70 0x803d69c -_zw_protocol_cmd_handlers_lr 0x30 0x803d70c -.ARM.exidx 0x8 0x803d73c -.copy.table 0xc 0x803d744 -.zero.table 0x0 0x803d750 +.text 0x3743c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803d43c +_zaf_cc_config 0x8 0x803d46c +_cc_handlers_v3 0x240 0x803d474 +_zw_protocol_cmd_handlers 0x70 0x803d6b4 +_zw_protocol_cmd_handlers_lr 0x30 0x803d724 +.ARM.exidx 0x8 0x803d754 +.copy.table 0xc 0x803d75c +.zero.table 0x0 0x803d768 .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xab44 0x200015a0 text_application_ram 0x0 0x2000c0e4 .heap 0x800 0x2000c0e8 -.internal_storage 0x30000 0x803d750 -.zwave_nvm 0x0 0x806d750 -.nvm 0x8000 0x806d750 +.internal_storage 0x30000 0x803d768 +.zwave_nvm 0x0 0x806d768 +.nvm 0x8000 0x806d768 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12848 0x0 -.debug_info 0xd464c9 0x0 -.debug_abbrev 0x285d3 0x0 -.debug_loclists 0x2cede 0x0 +.debug_frame 0x1283c 0x0 +.debug_info 0xd47be1 0x0 +.debug_abbrev 0x2855e 0x0 +.debug_loclists 0x2cf51 0x0 .debug_aranges 0x6978 0x0 -.debug_rnglists 0x4f0a 0x0 -.debug_line 0x779a8 0x0 -.debug_str 0x90970 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf6f39d +.debug_rnglists 0x4f10 0x0 +.debug_line 0x77a7d 0x0 +.debug_str 0x90959 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf70b83 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228592 + 228616 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_EU_size.txt index ecd02d146b..b57ac24204 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x36f08 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803cf08 -_zaf_cc_config 0x8 0x803cf38 -_cc_handlers_v3 0x240 0x803cf40 -_zw_protocol_cmd_handlers 0x70 0x803d180 -_zw_protocol_cmd_handlers_lr 0x30 0x803d1f0 -.ARM.exidx 0x8 0x803d220 -.copy.table 0xc 0x803d228 -.zero.table 0x0 0x803d234 +.text 0x36f20 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803cf20 +_zaf_cc_config 0x8 0x803cf50 +_cc_handlers_v3 0x240 0x803cf58 +_zw_protocol_cmd_handlers 0x70 0x803d198 +_zw_protocol_cmd_handlers_lr 0x30 0x803d208 +.ARM.exidx 0x8 0x803d238 +.copy.table 0xc 0x803d240 +.zero.table 0x0 0x803d24c .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xa9a4 0x200015a0 text_application_ram 0x0 0x2000bf44 .heap 0x800 0x2000bf48 -.internal_storage 0x30000 0x803d234 -.zwave_nvm 0x0 0x806d234 -.nvm 0x8000 0x806d234 +.internal_storage 0x30000 0x803d24c +.zwave_nvm 0x0 0x806d24c +.nvm 0x8000 0x806d24c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x121b8 0x0 -.debug_info 0xd40870 0x0 -.debug_abbrev 0x27bec 0x0 -.debug_loclists 0x29395 0x0 +.debug_frame 0x121ac 0x0 +.debug_info 0xd41f88 0x0 +.debug_abbrev 0x27b77 0x0 +.debug_loclists 0x29408 0x0 .debug_aranges 0x67d8 0x0 -.debug_rnglists 0x4c60 0x0 -.debug_line 0x748e6 0x0 -.debug_str 0x904d8 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf60b15 +.debug_rnglists 0x4c66 0x0 +.debug_line 0x749b1 0x0 +.debug_str 0x904c1 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf622f1 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 227284 + 227308 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_US_LR_size.txt index 1b56e07686..d9c819174c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x36f08 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803cf08 -_zaf_cc_config 0x8 0x803cf38 -_cc_handlers_v3 0x240 0x803cf40 -_zw_protocol_cmd_handlers 0x70 0x803d180 -_zw_protocol_cmd_handlers_lr 0x30 0x803d1f0 -.ARM.exidx 0x8 0x803d220 -.copy.table 0xc 0x803d228 -.zero.table 0x0 0x803d234 +.text 0x36f20 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803cf20 +_zaf_cc_config 0x8 0x803cf50 +_cc_handlers_v3 0x240 0x803cf58 +_zw_protocol_cmd_handlers 0x70 0x803d198 +_zw_protocol_cmd_handlers_lr 0x30 0x803d208 +.ARM.exidx 0x8 0x803d238 +.copy.table 0xc 0x803d240 +.zero.table 0x0 0x803d24c .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xa9a4 0x200015a0 text_application_ram 0x0 0x2000bf44 .heap 0x800 0x2000bf48 -.internal_storage 0x30000 0x803d234 -.zwave_nvm 0x0 0x806d234 -.nvm 0x8000 0x806d234 +.internal_storage 0x30000 0x803d24c +.zwave_nvm 0x0 0x806d24c +.nvm 0x8000 0x806d24c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x121b8 0x0 -.debug_info 0xd40870 0x0 -.debug_abbrev 0x27bec 0x0 -.debug_loclists 0x29395 0x0 +.debug_frame 0x121ac 0x0 +.debug_info 0xd41f88 0x0 +.debug_abbrev 0x27b77 0x0 +.debug_loclists 0x29408 0x0 .debug_aranges 0x67d8 0x0 -.debug_rnglists 0x4c60 0x0 -.debug_line 0x748e6 0x0 -.debug_str 0x904ce 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf60b0b +.debug_rnglists 0x4c66 0x0 +.debug_line 0x749b1 0x0 +.debug_str 0x904b7 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf622e7 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 227284 + 227308 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_US_size.txt index ecd02d146b..b57ac24204 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x36f08 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803cf08 -_zaf_cc_config 0x8 0x803cf38 -_cc_handlers_v3 0x240 0x803cf40 -_zw_protocol_cmd_handlers 0x70 0x803d180 -_zw_protocol_cmd_handlers_lr 0x30 0x803d1f0 -.ARM.exidx 0x8 0x803d220 -.copy.table 0xc 0x803d228 -.zero.table 0x0 0x803d234 +.text 0x36f20 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803cf20 +_zaf_cc_config 0x8 0x803cf50 +_cc_handlers_v3 0x240 0x803cf58 +_zw_protocol_cmd_handlers 0x70 0x803d198 +_zw_protocol_cmd_handlers_lr 0x30 0x803d208 +.ARM.exidx 0x8 0x803d238 +.copy.table 0xc 0x803d240 +.zero.table 0x0 0x803d24c .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xa9a4 0x200015a0 text_application_ram 0x0 0x2000bf44 .heap 0x800 0x2000bf48 -.internal_storage 0x30000 0x803d234 -.zwave_nvm 0x0 0x806d234 -.nvm 0x8000 0x806d234 +.internal_storage 0x30000 0x803d24c +.zwave_nvm 0x0 0x806d24c +.nvm 0x8000 0x806d24c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x121b8 0x0 -.debug_info 0xd40870 0x0 -.debug_abbrev 0x27bec 0x0 -.debug_loclists 0x29395 0x0 +.debug_frame 0x121ac 0x0 +.debug_info 0xd41f88 0x0 +.debug_abbrev 0x27b77 0x0 +.debug_loclists 0x29408 0x0 .debug_aranges 0x67d8 0x0 -.debug_rnglists 0x4c60 0x0 -.debug_line 0x748e6 0x0 -.debug_str 0x904d8 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf60b15 +.debug_rnglists 0x4c66 0x0 +.debug_line 0x749b1 0x0 +.debug_str 0x904c1 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf622f1 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 227284 + 227308 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_EU_size.txt index ddb0985c1d..b2f9370cad 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37734 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803d734 -_zaf_cc_config 0x8 0x803d764 -_cc_handlers_v3 0x240 0x803d76c -_zw_protocol_cmd_handlers 0x70 0x803d9ac -_zw_protocol_cmd_handlers_lr 0x30 0x803da1c -.ARM.exidx 0x8 0x803da4c -.copy.table 0xc 0x803da54 -.zero.table 0x0 0x803da60 +.text 0x3774c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803d74c +_zaf_cc_config 0x8 0x803d77c +_cc_handlers_v3 0x240 0x803d784 +_zw_protocol_cmd_handlers 0x70 0x803d9c4 +_zw_protocol_cmd_handlers_lr 0x30 0x803da34 +.ARM.exidx 0x8 0x803da64 +.copy.table 0xc 0x803da6c +.zero.table 0x0 0x803da78 .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xab44 0x200015a0 text_application_ram 0x0 0x2000c0e4 .heap 0x800 0x2000c0e8 -.internal_storage 0x30000 0x803da60 -.zwave_nvm 0x0 0x806da60 -.nvm 0x8000 0x806da60 +.internal_storage 0x30000 0x803da78 +.zwave_nvm 0x0 0x806da78 +.nvm 0x8000 0x806da78 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12878 0x0 -.debug_info 0xd46e98 0x0 -.debug_abbrev 0x286af 0x0 -.debug_loclists 0x2cee7 0x0 +.debug_frame 0x1286c 0x0 +.debug_info 0xd485b0 0x0 +.debug_abbrev 0x2863a 0x0 +.debug_loclists 0x2cf5a 0x0 .debug_aranges 0x69c8 0x0 -.debug_rnglists 0x4f22 0x0 -.debug_line 0x7788d 0x0 -.debug_str 0x90f38 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf70697 +.debug_rnglists 0x4f28 0x0 +.debug_line 0x7795a 0x0 +.debug_str 0x90f21 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf71e75 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 229376 + 229400 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_US_LR_size.txt index fd0c0dceae..236c26d0a7 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37734 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803d734 -_zaf_cc_config 0x8 0x803d764 -_cc_handlers_v3 0x240 0x803d76c -_zw_protocol_cmd_handlers 0x70 0x803d9ac -_zw_protocol_cmd_handlers_lr 0x30 0x803da1c -.ARM.exidx 0x8 0x803da4c -.copy.table 0xc 0x803da54 -.zero.table 0x0 0x803da60 +.text 0x3774c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803d74c +_zaf_cc_config 0x8 0x803d77c +_cc_handlers_v3 0x240 0x803d784 +_zw_protocol_cmd_handlers 0x70 0x803d9c4 +_zw_protocol_cmd_handlers_lr 0x30 0x803da34 +.ARM.exidx 0x8 0x803da64 +.copy.table 0xc 0x803da6c +.zero.table 0x0 0x803da78 .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xab44 0x200015a0 text_application_ram 0x0 0x2000c0e4 .heap 0x800 0x2000c0e8 -.internal_storage 0x30000 0x803da60 -.zwave_nvm 0x0 0x806da60 -.nvm 0x8000 0x806da60 +.internal_storage 0x30000 0x803da78 +.zwave_nvm 0x0 0x806da78 +.nvm 0x8000 0x806da78 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12878 0x0 -.debug_info 0xd46e98 0x0 -.debug_abbrev 0x286af 0x0 -.debug_loclists 0x2cee7 0x0 +.debug_frame 0x1286c 0x0 +.debug_info 0xd485b0 0x0 +.debug_abbrev 0x2863a 0x0 +.debug_loclists 0x2cf5a 0x0 .debug_aranges 0x69c8 0x0 -.debug_rnglists 0x4f22 0x0 -.debug_line 0x7788d 0x0 -.debug_str 0x90f2e 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf7068d +.debug_rnglists 0x4f28 0x0 +.debug_line 0x7795a 0x0 +.debug_str 0x90f17 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf71e6b The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 229376 + 229400 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_US_size.txt index ddb0985c1d..b2f9370cad 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37734 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803d734 -_zaf_cc_config 0x8 0x803d764 -_cc_handlers_v3 0x240 0x803d76c -_zw_protocol_cmd_handlers 0x70 0x803d9ac -_zw_protocol_cmd_handlers_lr 0x30 0x803da1c -.ARM.exidx 0x8 0x803da4c -.copy.table 0xc 0x803da54 -.zero.table 0x0 0x803da60 +.text 0x3774c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803d74c +_zaf_cc_config 0x8 0x803d77c +_cc_handlers_v3 0x240 0x803d784 +_zw_protocol_cmd_handlers 0x70 0x803d9c4 +_zw_protocol_cmd_handlers_lr 0x30 0x803da34 +.ARM.exidx 0x8 0x803da64 +.copy.table 0xc 0x803da6c +.zero.table 0x0 0x803da78 .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xab44 0x200015a0 text_application_ram 0x0 0x2000c0e4 .heap 0x800 0x2000c0e8 -.internal_storage 0x30000 0x803da60 -.zwave_nvm 0x0 0x806da60 -.nvm 0x8000 0x806da60 +.internal_storage 0x30000 0x803da78 +.zwave_nvm 0x0 0x806da78 +.nvm 0x8000 0x806da78 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12878 0x0 -.debug_info 0xd46e98 0x0 -.debug_abbrev 0x286af 0x0 -.debug_loclists 0x2cee7 0x0 +.debug_frame 0x1286c 0x0 +.debug_info 0xd485b0 0x0 +.debug_abbrev 0x2863a 0x0 +.debug_loclists 0x2cf5a 0x0 .debug_aranges 0x69c8 0x0 -.debug_rnglists 0x4f22 0x0 -.debug_line 0x7788d 0x0 -.debug_str 0x90f38 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf70697 +.debug_rnglists 0x4f28 0x0 +.debug_line 0x7795a 0x0 +.debug_str 0x90f21 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf71e75 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 229376 + 229400 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_EU_size.txt index af7d0c90dd..1036e72096 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x304d4 0x0 -_zaf_event_distributor_cc_event_handler 0x30 0x304d4 -_zaf_cc_config 0x8 0x30504 -_cc_handlers_v3 0x240 0x3050c -_zw_protocol_cmd_handlers 0x70 0x3074c -_zw_protocol_cmd_handlers_lr 0x30 0x307bc -.ARM.exidx 0x8 0x307ec -.copy.table 0xc 0x307f4 -.zero.table 0x0 0x30800 +.text 0x304c8 0x0 +_zaf_event_distributor_cc_event_handler 0x30 0x304c8 +_zaf_cc_config 0x8 0x304f8 +_cc_handlers_v3 0x240 0x30500 +_zw_protocol_cmd_handlers 0x70 0x30740 +_zw_protocol_cmd_handlers_lr 0x30 0x307b0 +.ARM.exidx 0x8 0x307e0 +.copy.table 0xc 0x307e8 +.zero.table 0x0 0x307f4 .stack 0x1000 0x20000000 .data 0x41c 0x20001000 .bss 0x9fd4 0x2000141c text_application_ram 0x0 0x2000b3f0 .heap 0x800 0x2000b3f0 -.internal_storage 0x3a000 0x30800 -.zwave_nvm 0x3000 0x6a800 -.nvm 0x9000 0x6d800 +.internal_storage 0x3a000 0x307f4 +.zwave_nvm 0x3000 0x6a7f4 +.nvm 0x9000 0x6d7f4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf730 0x0 -.debug_info 0xcfbadf 0x0 -.debug_abbrev 0x22bf3 0x0 -.debug_loclists 0x18b68 0x0 -.debug_aranges 0x5a98 0x0 -.debug_rnglists 0x37b5 0x0 -.debug_line 0x60d3d 0x0 -.debug_str 0x86fb8 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xeec678 +.debug_frame 0xf704 0x0 +.debug_info 0xcfbcb9 0x0 +.debug_abbrev 0x22bae 0x0 +.debug_loclists 0x18b54 0x0 +.debug_aranges 0x5a90 0x0 +.debug_rnglists 0x37c4 0x0 +.debug_line 0x60d4d 0x0 +.debug_str 0x86f80 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xeec780 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 199708 + 199696 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_US_LR_size.txt index ec2d943b27..08420a49a3 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x304d4 0x0 -_zaf_event_distributor_cc_event_handler 0x30 0x304d4 -_zaf_cc_config 0x8 0x30504 -_cc_handlers_v3 0x240 0x3050c -_zw_protocol_cmd_handlers 0x70 0x3074c -_zw_protocol_cmd_handlers_lr 0x30 0x307bc -.ARM.exidx 0x8 0x307ec -.copy.table 0xc 0x307f4 -.zero.table 0x0 0x30800 +.text 0x304c8 0x0 +_zaf_event_distributor_cc_event_handler 0x30 0x304c8 +_zaf_cc_config 0x8 0x304f8 +_cc_handlers_v3 0x240 0x30500 +_zw_protocol_cmd_handlers 0x70 0x30740 +_zw_protocol_cmd_handlers_lr 0x30 0x307b0 +.ARM.exidx 0x8 0x307e0 +.copy.table 0xc 0x307e8 +.zero.table 0x0 0x307f4 .stack 0x1000 0x20000000 .data 0x41c 0x20001000 .bss 0x9fd4 0x2000141c text_application_ram 0x0 0x2000b3f0 .heap 0x800 0x2000b3f0 -.internal_storage 0x3a000 0x30800 -.zwave_nvm 0x3000 0x6a800 -.nvm 0x9000 0x6d800 +.internal_storage 0x3a000 0x307f4 +.zwave_nvm 0x3000 0x6a7f4 +.nvm 0x9000 0x6d7f4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf730 0x0 -.debug_info 0xcfbadf 0x0 -.debug_abbrev 0x22bf3 0x0 -.debug_loclists 0x18b68 0x0 -.debug_aranges 0x5a98 0x0 -.debug_rnglists 0x37b5 0x0 -.debug_line 0x60d3d 0x0 -.debug_str 0x86fae 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xeec66e +.debug_frame 0xf704 0x0 +.debug_info 0xcfbcb9 0x0 +.debug_abbrev 0x22bae 0x0 +.debug_loclists 0x18b54 0x0 +.debug_aranges 0x5a90 0x0 +.debug_rnglists 0x37c4 0x0 +.debug_line 0x60d4d 0x0 +.debug_str 0x86f76 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xeec776 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 199708 + 199696 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_US_size.txt index af7d0c90dd..1036e72096 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x304d4 0x0 -_zaf_event_distributor_cc_event_handler 0x30 0x304d4 -_zaf_cc_config 0x8 0x30504 -_cc_handlers_v3 0x240 0x3050c -_zw_protocol_cmd_handlers 0x70 0x3074c -_zw_protocol_cmd_handlers_lr 0x30 0x307bc -.ARM.exidx 0x8 0x307ec -.copy.table 0xc 0x307f4 -.zero.table 0x0 0x30800 +.text 0x304c8 0x0 +_zaf_event_distributor_cc_event_handler 0x30 0x304c8 +_zaf_cc_config 0x8 0x304f8 +_cc_handlers_v3 0x240 0x30500 +_zw_protocol_cmd_handlers 0x70 0x30740 +_zw_protocol_cmd_handlers_lr 0x30 0x307b0 +.ARM.exidx 0x8 0x307e0 +.copy.table 0xc 0x307e8 +.zero.table 0x0 0x307f4 .stack 0x1000 0x20000000 .data 0x41c 0x20001000 .bss 0x9fd4 0x2000141c text_application_ram 0x0 0x2000b3f0 .heap 0x800 0x2000b3f0 -.internal_storage 0x3a000 0x30800 -.zwave_nvm 0x3000 0x6a800 -.nvm 0x9000 0x6d800 +.internal_storage 0x3a000 0x307f4 +.zwave_nvm 0x3000 0x6a7f4 +.nvm 0x9000 0x6d7f4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf730 0x0 -.debug_info 0xcfbadf 0x0 -.debug_abbrev 0x22bf3 0x0 -.debug_loclists 0x18b68 0x0 -.debug_aranges 0x5a98 0x0 -.debug_rnglists 0x37b5 0x0 -.debug_line 0x60d3d 0x0 -.debug_str 0x86fb8 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xeec678 +.debug_frame 0xf704 0x0 +.debug_info 0xcfbcb9 0x0 +.debug_abbrev 0x22bae 0x0 +.debug_loclists 0x18b54 0x0 +.debug_aranges 0x5a90 0x0 +.debug_rnglists 0x37c4 0x0 +.debug_line 0x60d4d 0x0 +.debug_str 0x86f80 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xeec780 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 199708 + 199696 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4209A_REGION_US_LR_size.txt index 8ed24e164c..1322623b2f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4209A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x3040c 0x0 -_zaf_event_distributor_cc_event_handler 0x30 0x3040c -_zaf_cc_config 0x8 0x3043c -_cc_handlers_v3 0x240 0x30444 -_zw_protocol_cmd_handlers 0x70 0x30684 -_zw_protocol_cmd_handlers_lr 0x30 0x306f4 -.ARM.exidx 0x8 0x30724 -.copy.table 0xc 0x3072c -.zero.table 0x0 0x30738 +.text 0x30420 0x0 +_zaf_event_distributor_cc_event_handler 0x30 0x30420 +_zaf_cc_config 0x8 0x30450 +_cc_handlers_v3 0x240 0x30458 +_zw_protocol_cmd_handlers 0x70 0x30698 +_zw_protocol_cmd_handlers_lr 0x30 0x30708 +.ARM.exidx 0x8 0x30738 +.copy.table 0xc 0x30740 +.zero.table 0x0 0x3074c .stack 0x1000 0x20000000 .data 0x418 0x20001000 .bss 0x9fb4 0x20001418 text_application_ram 0x0 0x2000b3cc .heap 0x800 0x2000b3d0 -.internal_storage 0x3a000 0x30738 -.zwave_nvm 0x3000 0x6a738 -.nvm 0x9000 0x6d738 +.internal_storage 0x3a000 0x3074c +.zwave_nvm 0x3000 0x6a74c +.nvm 0x9000 0x6d74c .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf900 0x0 -.debug_info 0xcfd0c0 0x0 -.debug_abbrev 0x23136 0x0 -.debug_loclists 0x19205 0x0 -.debug_aranges 0x5b38 0x0 -.debug_rnglists 0x3860 0x0 -.debug_line 0x61d3e 0x0 -.debug_str 0x872da 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xeefd8b +.debug_frame 0xf8d4 0x0 +.debug_info 0xcfd29a 0x0 +.debug_abbrev 0x230f1 0x0 +.debug_loclists 0x191f1 0x0 +.debug_aranges 0x5b30 0x0 +.debug_rnglists 0x386f 0x0 +.debug_line 0x61d58 0x0 +.debug_str 0x872a2 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xeefebd The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 199504 + 199524 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4210A_REGION_US_LR_size.txt index f7822a4ff1..7bc34048a6 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4210A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37444 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803d444 -_zaf_cc_config 0x8 0x803d474 -_cc_handlers_v3 0x240 0x803d47c -_zw_protocol_cmd_handlers 0x70 0x803d6bc -_zw_protocol_cmd_handlers_lr 0x30 0x803d72c -.ARM.exidx 0x8 0x803d75c -.copy.table 0xc 0x803d764 -.zero.table 0x0 0x803d770 +.text 0x3747c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803d47c +_zaf_cc_config 0x8 0x803d4ac +_cc_handlers_v3 0x240 0x803d4b4 +_zw_protocol_cmd_handlers 0x70 0x803d6f4 +_zw_protocol_cmd_handlers_lr 0x30 0x803d764 +.ARM.exidx 0x8 0x803d794 +.copy.table 0xc 0x803d79c +.zero.table 0x0 0x803d7a8 .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xab44 0x200015a0 text_application_ram 0x0 0x2000c0e4 .heap 0x800 0x2000c0e8 -.internal_storage 0x30000 0x803d770 -.zwave_nvm 0x0 0x806d770 -.nvm 0x8000 0x806d770 +.internal_storage 0x30000 0x803d7a8 +.zwave_nvm 0x0 0x806d7a8 +.nvm 0x8000 0x806d7a8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12850 0x0 -.debug_info 0xd46493 0x0 -.debug_abbrev 0x285d3 0x0 -.debug_loclists 0x2cede 0x0 +.debug_frame 0x12844 0x0 +.debug_info 0xd47bab 0x0 +.debug_abbrev 0x2855e 0x0 +.debug_loclists 0x2cf51 0x0 .debug_aranges 0x6978 0x0 -.debug_rnglists 0x4f0a 0x0 -.debug_line 0x7797f 0x0 -.debug_str 0x90966 0x0 -.debug_loc 0x2c495 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xf6f329 +.debug_rnglists 0x4f10 0x0 +.debug_line 0x77a54 0x0 +.debug_str 0x9094f 0x0 +.debug_loc 0x2c45d 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xf70b2f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228624 + 228680 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400B_REGION_EU_size.txt index df175c49bf..78035ce4f0 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400B_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37fc4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803dfc4 -_zaf_cc_config 0x8 0x803dff4 -_cc_handlers_v3 0x240 0x803dffc -_zw_protocol_cmd_handlers 0x70 0x803e23c -_zw_protocol_cmd_handlers_lr 0x30 0x803e2ac -.ARM.exidx 0x8 0x803e2dc -.copy.table 0xc 0x803e2e4 -.zero.table 0x0 0x803e2f0 +.text 0x37ffc 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803dffc +_zaf_cc_config 0x8 0x803e02c +_cc_handlers_v3 0x240 0x803e034 +_zw_protocol_cmd_handlers 0x70 0x803e274 +_zw_protocol_cmd_handlers_lr 0x30 0x803e2e4 +.ARM.exidx 0x8 0x803e314 +.copy.table 0xc 0x803e31c +.zero.table 0x0 0x803e328 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaab4 0x2000159c text_application_ram 0x0 0x2000c050 .heap 0x800 0x2000c050 -.internal_storage 0x30000 0x803e2f0 -.zwave_nvm 0x0 0x806e2f0 -.nvm 0x8000 0x806e2f0 +.internal_storage 0x30000 0x803e328 +.zwave_nvm 0x0 0x806e328 +.nvm 0x8000 0x806e328 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12914 0x0 -.debug_info 0xd4ae4c 0x0 -.debug_abbrev 0x2891a 0x0 -.debug_loclists 0x2d40d 0x0 +.debug_frame 0x12908 0x0 +.debug_info 0xd4c568 0x0 +.debug_abbrev 0x288a5 0x0 +.debug_loclists 0x2d480 0x0 .debug_aranges 0x69f8 0x0 -.debug_rnglists 0x4f5f 0x0 -.debug_line 0x77d4c 0x0 -.debug_str 0x92255 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf76db9 +.debug_rnglists 0x4f65 0x0 +.debug_line 0x77e21 0x0 +.debug_str 0x9223e 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf785c3 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231564 + 231620 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400B_REGION_US_LR_size.txt index e4a4ebbf2f..01aab76891 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37fc4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803dfc4 -_zaf_cc_config 0x8 0x803dff4 -_cc_handlers_v3 0x240 0x803dffc -_zw_protocol_cmd_handlers 0x70 0x803e23c -_zw_protocol_cmd_handlers_lr 0x30 0x803e2ac -.ARM.exidx 0x8 0x803e2dc -.copy.table 0xc 0x803e2e4 -.zero.table 0x0 0x803e2f0 +.text 0x37ffc 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803dffc +_zaf_cc_config 0x8 0x803e02c +_cc_handlers_v3 0x240 0x803e034 +_zw_protocol_cmd_handlers 0x70 0x803e274 +_zw_protocol_cmd_handlers_lr 0x30 0x803e2e4 +.ARM.exidx 0x8 0x803e314 +.copy.table 0xc 0x803e31c +.zero.table 0x0 0x803e328 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaab4 0x2000159c text_application_ram 0x0 0x2000c050 .heap 0x800 0x2000c050 -.internal_storage 0x30000 0x803e2f0 -.zwave_nvm 0x0 0x806e2f0 -.nvm 0x8000 0x806e2f0 +.internal_storage 0x30000 0x803e328 +.zwave_nvm 0x0 0x806e328 +.nvm 0x8000 0x806e328 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12914 0x0 -.debug_info 0xd4ae4c 0x0 -.debug_abbrev 0x2891a 0x0 -.debug_loclists 0x2d40d 0x0 +.debug_frame 0x12908 0x0 +.debug_info 0xd4c568 0x0 +.debug_abbrev 0x288a5 0x0 +.debug_loclists 0x2d480 0x0 .debug_aranges 0x69f8 0x0 -.debug_rnglists 0x4f5f 0x0 -.debug_line 0x77d4c 0x0 -.debug_str 0x9224b 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf76daf +.debug_rnglists 0x4f65 0x0 +.debug_line 0x77e21 0x0 +.debug_str 0x92234 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf785b9 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231564 + 231620 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400B_REGION_US_size.txt index df175c49bf..78035ce4f0 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400B_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37fc4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803dfc4 -_zaf_cc_config 0x8 0x803dff4 -_cc_handlers_v3 0x240 0x803dffc -_zw_protocol_cmd_handlers 0x70 0x803e23c -_zw_protocol_cmd_handlers_lr 0x30 0x803e2ac -.ARM.exidx 0x8 0x803e2dc -.copy.table 0xc 0x803e2e4 -.zero.table 0x0 0x803e2f0 +.text 0x37ffc 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803dffc +_zaf_cc_config 0x8 0x803e02c +_cc_handlers_v3 0x240 0x803e034 +_zw_protocol_cmd_handlers 0x70 0x803e274 +_zw_protocol_cmd_handlers_lr 0x30 0x803e2e4 +.ARM.exidx 0x8 0x803e314 +.copy.table 0xc 0x803e31c +.zero.table 0x0 0x803e328 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaab4 0x2000159c text_application_ram 0x0 0x2000c050 .heap 0x800 0x2000c050 -.internal_storage 0x30000 0x803e2f0 -.zwave_nvm 0x0 0x806e2f0 -.nvm 0x8000 0x806e2f0 +.internal_storage 0x30000 0x803e328 +.zwave_nvm 0x0 0x806e328 +.nvm 0x8000 0x806e328 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12914 0x0 -.debug_info 0xd4ae4c 0x0 -.debug_abbrev 0x2891a 0x0 -.debug_loclists 0x2d40d 0x0 +.debug_frame 0x12908 0x0 +.debug_info 0xd4c568 0x0 +.debug_abbrev 0x288a5 0x0 +.debug_loclists 0x2d480 0x0 .debug_aranges 0x69f8 0x0 -.debug_rnglists 0x4f5f 0x0 -.debug_line 0x77d4c 0x0 -.debug_str 0x92255 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf76db9 +.debug_rnglists 0x4f65 0x0 +.debug_line 0x77e21 0x0 +.debug_str 0x9223e 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf785c3 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231564 + 231620 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400C_REGION_EU_size.txt index 92f6ce7a18..51e95c975f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37fc4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803dfc4 -_zaf_cc_config 0x8 0x803dff4 -_cc_handlers_v3 0x240 0x803dffc -_zw_protocol_cmd_handlers 0x70 0x803e23c -_zw_protocol_cmd_handlers_lr 0x30 0x803e2ac -.ARM.exidx 0x8 0x803e2dc -.copy.table 0xc 0x803e2e4 -.zero.table 0x0 0x803e2f0 +.text 0x37ffc 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803dffc +_zaf_cc_config 0x8 0x803e02c +_cc_handlers_v3 0x240 0x803e034 +_zw_protocol_cmd_handlers 0x70 0x803e274 +_zw_protocol_cmd_handlers_lr 0x30 0x803e2e4 +.ARM.exidx 0x8 0x803e314 +.copy.table 0xc 0x803e31c +.zero.table 0x0 0x803e328 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaab4 0x2000159c text_application_ram 0x0 0x2000c050 .heap 0x800 0x2000c050 -.internal_storage 0x30000 0x803e2f0 -.zwave_nvm 0x0 0x806e2f0 -.nvm 0x8000 0x806e2f0 +.internal_storage 0x30000 0x803e328 +.zwave_nvm 0x0 0x806e328 +.nvm 0x8000 0x806e328 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12928 0x0 -.debug_info 0xd4addb 0x0 -.debug_abbrev 0x28924 0x0 -.debug_loclists 0x2d3d9 0x0 +.debug_frame 0x1291c 0x0 +.debug_info 0xd4c4f7 0x0 +.debug_abbrev 0x288af 0x0 +.debug_loclists 0x2d44c 0x0 .debug_aranges 0x6a00 0x0 -.debug_rnglists 0x4f88 0x0 -.debug_line 0x77d41 0x0 -.debug_str 0x92255 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf76d58 +.debug_rnglists 0x4f8e 0x0 +.debug_line 0x77e16 0x0 +.debug_str 0x9223e 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf78562 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231564 + 231620 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400C_REGION_US_LR_size.txt index d34065d5ae..8f151da282 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37fc4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803dfc4 -_zaf_cc_config 0x8 0x803dff4 -_cc_handlers_v3 0x240 0x803dffc -_zw_protocol_cmd_handlers 0x70 0x803e23c -_zw_protocol_cmd_handlers_lr 0x30 0x803e2ac -.ARM.exidx 0x8 0x803e2dc -.copy.table 0xc 0x803e2e4 -.zero.table 0x0 0x803e2f0 +.text 0x37ffc 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803dffc +_zaf_cc_config 0x8 0x803e02c +_cc_handlers_v3 0x240 0x803e034 +_zw_protocol_cmd_handlers 0x70 0x803e274 +_zw_protocol_cmd_handlers_lr 0x30 0x803e2e4 +.ARM.exidx 0x8 0x803e314 +.copy.table 0xc 0x803e31c +.zero.table 0x0 0x803e328 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaab4 0x2000159c text_application_ram 0x0 0x2000c050 .heap 0x800 0x2000c050 -.internal_storage 0x30000 0x803e2f0 -.zwave_nvm 0x0 0x806e2f0 -.nvm 0x8000 0x806e2f0 +.internal_storage 0x30000 0x803e328 +.zwave_nvm 0x0 0x806e328 +.nvm 0x8000 0x806e328 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12928 0x0 -.debug_info 0xd4addb 0x0 -.debug_abbrev 0x28924 0x0 -.debug_loclists 0x2d3d9 0x0 +.debug_frame 0x1291c 0x0 +.debug_info 0xd4c4f7 0x0 +.debug_abbrev 0x288af 0x0 +.debug_loclists 0x2d44c 0x0 .debug_aranges 0x6a00 0x0 -.debug_rnglists 0x4f88 0x0 -.debug_line 0x77d41 0x0 -.debug_str 0x9224b 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf76d4e +.debug_rnglists 0x4f8e 0x0 +.debug_line 0x77e16 0x0 +.debug_str 0x92234 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf78558 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231564 + 231620 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400C_REGION_US_size.txt index 92f6ce7a18..51e95c975f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4400C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37fc4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803dfc4 -_zaf_cc_config 0x8 0x803dff4 -_cc_handlers_v3 0x240 0x803dffc -_zw_protocol_cmd_handlers 0x70 0x803e23c -_zw_protocol_cmd_handlers_lr 0x30 0x803e2ac -.ARM.exidx 0x8 0x803e2dc -.copy.table 0xc 0x803e2e4 -.zero.table 0x0 0x803e2f0 +.text 0x37ffc 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803dffc +_zaf_cc_config 0x8 0x803e02c +_cc_handlers_v3 0x240 0x803e034 +_zw_protocol_cmd_handlers 0x70 0x803e274 +_zw_protocol_cmd_handlers_lr 0x30 0x803e2e4 +.ARM.exidx 0x8 0x803e314 +.copy.table 0xc 0x803e31c +.zero.table 0x0 0x803e328 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaab4 0x2000159c text_application_ram 0x0 0x2000c050 .heap 0x800 0x2000c050 -.internal_storage 0x30000 0x803e2f0 -.zwave_nvm 0x0 0x806e2f0 -.nvm 0x8000 0x806e2f0 +.internal_storage 0x30000 0x803e328 +.zwave_nvm 0x0 0x806e328 +.nvm 0x8000 0x806e328 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12928 0x0 -.debug_info 0xd4addb 0x0 -.debug_abbrev 0x28924 0x0 -.debug_loclists 0x2d3d9 0x0 +.debug_frame 0x1291c 0x0 +.debug_info 0xd4c4f7 0x0 +.debug_abbrev 0x288af 0x0 +.debug_loclists 0x2d44c 0x0 .debug_aranges 0x6a00 0x0 -.debug_rnglists 0x4f88 0x0 -.debug_line 0x77d41 0x0 -.debug_str 0x92255 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf76d58 +.debug_rnglists 0x4f8e 0x0 +.debug_line 0x77e16 0x0 +.debug_str 0x9223e 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf78562 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231564 + 231620 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4401B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4401B_REGION_US_LR_size.txt index 23a6deee53..93aa4c2881 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4401B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4401B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37fe4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803dfe4 -_zaf_cc_config 0x8 0x803e014 -_cc_handlers_v3 0x240 0x803e01c -_zw_protocol_cmd_handlers 0x70 0x803e25c -_zw_protocol_cmd_handlers_lr 0x30 0x803e2cc -.ARM.exidx 0x8 0x803e2fc -.copy.table 0xc 0x803e304 -.zero.table 0x0 0x803e310 +.text 0x3801c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803e01c +_zaf_cc_config 0x8 0x803e04c +_cc_handlers_v3 0x240 0x803e054 +_zw_protocol_cmd_handlers 0x70 0x803e294 +_zw_protocol_cmd_handlers_lr 0x30 0x803e304 +.ARM.exidx 0x8 0x803e334 +.copy.table 0xc 0x803e33c +.zero.table 0x0 0x803e348 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaab4 0x2000159c text_application_ram 0x0 0x2000c050 .heap 0x800 0x2000c050 -.internal_storage 0x30000 0x803e310 -.zwave_nvm 0x0 0x806e310 -.nvm 0x8000 0x806e310 +.internal_storage 0x30000 0x803e348 +.zwave_nvm 0x0 0x806e348 +.nvm 0x8000 0x806e348 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1291c 0x0 -.debug_info 0xd4ae16 0x0 -.debug_abbrev 0x2891a 0x0 -.debug_loclists 0x2d40d 0x0 +.debug_frame 0x12910 0x0 +.debug_info 0xd4c532 0x0 +.debug_abbrev 0x288a5 0x0 +.debug_loclists 0x2d480 0x0 .debug_aranges 0x69f8 0x0 -.debug_rnglists 0x4f5f 0x0 -.debug_line 0x77d23 0x0 -.debug_str 0x9224b 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xf76d45 +.debug_rnglists 0x4f65 0x0 +.debug_line 0x77df8 0x0 +.debug_str 0x92234 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xf7854f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231596 + 231652 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4401C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4401C_REGION_EU_size.txt index 424305b1f5..78abdf9141 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4401C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4401C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37fe4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803dfe4 -_zaf_cc_config 0x8 0x803e014 -_cc_handlers_v3 0x240 0x803e01c -_zw_protocol_cmd_handlers 0x70 0x803e25c -_zw_protocol_cmd_handlers_lr 0x30 0x803e2cc -.ARM.exidx 0x8 0x803e2fc -.copy.table 0xc 0x803e304 -.zero.table 0x0 0x803e310 +.text 0x3801c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803e01c +_zaf_cc_config 0x8 0x803e04c +_cc_handlers_v3 0x240 0x803e054 +_zw_protocol_cmd_handlers 0x70 0x803e294 +_zw_protocol_cmd_handlers_lr 0x30 0x803e304 +.ARM.exidx 0x8 0x803e334 +.copy.table 0xc 0x803e33c +.zero.table 0x0 0x803e348 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaab4 0x2000159c text_application_ram 0x0 0x2000c050 .heap 0x800 0x2000c050 -.internal_storage 0x30000 0x803e310 -.zwave_nvm 0x0 0x806e310 -.nvm 0x8000 0x806e310 +.internal_storage 0x30000 0x803e348 +.zwave_nvm 0x0 0x806e348 +.nvm 0x8000 0x806e348 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12930 0x0 -.debug_info 0xd4ada5 0x0 -.debug_abbrev 0x28924 0x0 -.debug_loclists 0x2d3d9 0x0 +.debug_frame 0x12924 0x0 +.debug_info 0xd4c4c1 0x0 +.debug_abbrev 0x288af 0x0 +.debug_loclists 0x2d44c 0x0 .debug_aranges 0x6a00 0x0 -.debug_rnglists 0x4f88 0x0 -.debug_line 0x77d18 0x0 -.debug_str 0x92255 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xf76cee +.debug_rnglists 0x4f8e 0x0 +.debug_line 0x77ded 0x0 +.debug_str 0x9223e 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xf784f8 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231596 + 231652 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4401C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4401C_REGION_US_LR_size.txt index 793ba2fb5c..510b1410de 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4401C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4401C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37fe4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803dfe4 -_zaf_cc_config 0x8 0x803e014 -_cc_handlers_v3 0x240 0x803e01c -_zw_protocol_cmd_handlers 0x70 0x803e25c -_zw_protocol_cmd_handlers_lr 0x30 0x803e2cc -.ARM.exidx 0x8 0x803e2fc -.copy.table 0xc 0x803e304 -.zero.table 0x0 0x803e310 +.text 0x3801c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803e01c +_zaf_cc_config 0x8 0x803e04c +_cc_handlers_v3 0x240 0x803e054 +_zw_protocol_cmd_handlers 0x70 0x803e294 +_zw_protocol_cmd_handlers_lr 0x30 0x803e304 +.ARM.exidx 0x8 0x803e334 +.copy.table 0xc 0x803e33c +.zero.table 0x0 0x803e348 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaab4 0x2000159c text_application_ram 0x0 0x2000c050 .heap 0x800 0x2000c050 -.internal_storage 0x30000 0x803e310 -.zwave_nvm 0x0 0x806e310 -.nvm 0x8000 0x806e310 +.internal_storage 0x30000 0x803e348 +.zwave_nvm 0x0 0x806e348 +.nvm 0x8000 0x806e348 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12930 0x0 -.debug_info 0xd4ada5 0x0 -.debug_abbrev 0x28924 0x0 -.debug_loclists 0x2d3d9 0x0 +.debug_frame 0x12924 0x0 +.debug_info 0xd4c4c1 0x0 +.debug_abbrev 0x288af 0x0 +.debug_loclists 0x2d44c 0x0 .debug_aranges 0x6a00 0x0 -.debug_rnglists 0x4f88 0x0 -.debug_line 0x77d18 0x0 -.debug_str 0x9224b 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xf76ce4 +.debug_rnglists 0x4f8e 0x0 +.debug_line 0x77ded 0x0 +.debug_str 0x92234 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xf784ee The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231596 + 231652 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4401C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4401C_REGION_US_size.txt index 424305b1f5..78abdf9141 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4401C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4401C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x37fe4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x30 0x803dfe4 -_zaf_cc_config 0x8 0x803e014 -_cc_handlers_v3 0x240 0x803e01c -_zw_protocol_cmd_handlers 0x70 0x803e25c -_zw_protocol_cmd_handlers_lr 0x30 0x803e2cc -.ARM.exidx 0x8 0x803e2fc -.copy.table 0xc 0x803e304 -.zero.table 0x0 0x803e310 +.text 0x3801c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x30 0x803e01c +_zaf_cc_config 0x8 0x803e04c +_cc_handlers_v3 0x240 0x803e054 +_zw_protocol_cmd_handlers 0x70 0x803e294 +_zw_protocol_cmd_handlers_lr 0x30 0x803e304 +.ARM.exidx 0x8 0x803e334 +.copy.table 0xc 0x803e33c +.zero.table 0x0 0x803e348 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaab4 0x2000159c text_application_ram 0x0 0x2000c050 .heap 0x800 0x2000c050 -.internal_storage 0x30000 0x803e310 -.zwave_nvm 0x0 0x806e310 -.nvm 0x8000 0x806e310 +.internal_storage 0x30000 0x803e348 +.zwave_nvm 0x0 0x806e348 +.nvm 0x8000 0x806e348 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12930 0x0 -.debug_info 0xd4ada5 0x0 -.debug_abbrev 0x28924 0x0 -.debug_loclists 0x2d3d9 0x0 +.debug_frame 0x12924 0x0 +.debug_info 0xd4c4c1 0x0 +.debug_abbrev 0x288af 0x0 +.debug_loclists 0x2d44c 0x0 .debug_aranges 0x6a00 0x0 -.debug_rnglists 0x4f88 0x0 -.debug_line 0x77d18 0x0 -.debug_str 0x92255 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xf76cee +.debug_rnglists 0x4f8e 0x0 +.debug_line 0x77ded 0x0 +.debug_str 0x9223e 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xf784f8 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231596 + 231652 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD2705A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD2705A_REGION_EU_size.txt index b0d51ec83f..4afa2770d4 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD2705A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD2705A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x379a8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d9a8 -_zaf_cc_config 0x28 0x803d9b8 -_cc_handlers_v3 0x21c 0x803d9e0 -_zw_protocol_cmd_handlers 0x70 0x803dbfc -_zw_protocol_cmd_handlers_lr 0x30 0x803dc6c -.ARM.exidx 0x8 0x803dc9c -.copy.table 0xc 0x803dca4 -.zero.table 0x0 0x803dcb0 +.text 0x379c0 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d9c0 +_zaf_cc_config 0x28 0x803d9d0 +_cc_handlers_v3 0x21c 0x803d9f8 +_zw_protocol_cmd_handlers 0x70 0x803dc14 +_zw_protocol_cmd_handlers_lr 0x30 0x803dc84 +.ARM.exidx 0x8 0x803dcb4 +.copy.table 0xc 0x803dcbc +.zero.table 0x0 0x803dcc8 .stack 0x1000 0x20000000 .data 0x6f0 0x20001000 .bss 0xaa78 0x200016f0 text_application_ram 0x0 0x2000c168 .heap 0x800 0x2000c168 -.internal_storage 0x30000 0x803dcb0 -.zwave_nvm 0x0 0x806dcb0 -.nvm 0x8000 0x806dcb0 +.internal_storage 0x30000 0x803dcc8 +.zwave_nvm 0x0 0x806dcc8 +.nvm 0x8000 0x806dcc8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x122b8 0x0 -.debug_info 0xce039f 0x0 -.debug_abbrev 0x27ca7 0x0 -.debug_loclists 0x2cc07 0x0 +.debug_frame 0x122ac 0x0 +.debug_info 0xce1abb 0x0 +.debug_abbrev 0x27c32 0x0 +.debug_loclists 0x2cc7a 0x0 .debug_aranges 0x6790 0x0 -.debug_rnglists 0x4e2d 0x0 -.debug_line 0x760bd 0x0 -.debug_str 0x8fd74 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf05e05 +.debug_rnglists 0x4e33 0x0 +.debug_line 0x76192 0x0 +.debug_str 0x8fd5d 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf075ef The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230304 + 230328 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD2705A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD2705A_REGION_US_LR_size.txt index 2f16e46507..90fac435f9 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD2705A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD2705A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x379a8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d9a8 -_zaf_cc_config 0x28 0x803d9b8 -_cc_handlers_v3 0x21c 0x803d9e0 -_zw_protocol_cmd_handlers 0x70 0x803dbfc -_zw_protocol_cmd_handlers_lr 0x30 0x803dc6c -.ARM.exidx 0x8 0x803dc9c -.copy.table 0xc 0x803dca4 -.zero.table 0x0 0x803dcb0 +.text 0x379c0 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d9c0 +_zaf_cc_config 0x28 0x803d9d0 +_cc_handlers_v3 0x21c 0x803d9f8 +_zw_protocol_cmd_handlers 0x70 0x803dc14 +_zw_protocol_cmd_handlers_lr 0x30 0x803dc84 +.ARM.exidx 0x8 0x803dcb4 +.copy.table 0xc 0x803dcbc +.zero.table 0x0 0x803dcc8 .stack 0x1000 0x20000000 .data 0x6f0 0x20001000 .bss 0xaa78 0x200016f0 text_application_ram 0x0 0x2000c168 .heap 0x800 0x2000c168 -.internal_storage 0x30000 0x803dcb0 -.zwave_nvm 0x0 0x806dcb0 -.nvm 0x8000 0x806dcb0 +.internal_storage 0x30000 0x803dcc8 +.zwave_nvm 0x0 0x806dcc8 +.nvm 0x8000 0x806dcc8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x122b8 0x0 -.debug_info 0xce039f 0x0 -.debug_abbrev 0x27ca7 0x0 -.debug_loclists 0x2cc07 0x0 +.debug_frame 0x122ac 0x0 +.debug_info 0xce1abb 0x0 +.debug_abbrev 0x27c32 0x0 +.debug_loclists 0x2cc7a 0x0 .debug_aranges 0x6790 0x0 -.debug_rnglists 0x4e2d 0x0 -.debug_line 0x760bd 0x0 -.debug_str 0x8fd6a 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf05dfb +.debug_rnglists 0x4e33 0x0 +.debug_line 0x76192 0x0 +.debug_str 0x8fd53 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf075e5 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230304 + 230328 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD2705A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD2705A_REGION_US_size.txt index b0d51ec83f..4afa2770d4 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD2705A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD2705A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x379a8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d9a8 -_zaf_cc_config 0x28 0x803d9b8 -_cc_handlers_v3 0x21c 0x803d9e0 -_zw_protocol_cmd_handlers 0x70 0x803dbfc -_zw_protocol_cmd_handlers_lr 0x30 0x803dc6c -.ARM.exidx 0x8 0x803dc9c -.copy.table 0xc 0x803dca4 -.zero.table 0x0 0x803dcb0 +.text 0x379c0 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d9c0 +_zaf_cc_config 0x28 0x803d9d0 +_cc_handlers_v3 0x21c 0x803d9f8 +_zw_protocol_cmd_handlers 0x70 0x803dc14 +_zw_protocol_cmd_handlers_lr 0x30 0x803dc84 +.ARM.exidx 0x8 0x803dcb4 +.copy.table 0xc 0x803dcbc +.zero.table 0x0 0x803dcc8 .stack 0x1000 0x20000000 .data 0x6f0 0x20001000 .bss 0xaa78 0x200016f0 text_application_ram 0x0 0x2000c168 .heap 0x800 0x2000c168 -.internal_storage 0x30000 0x803dcb0 -.zwave_nvm 0x0 0x806dcb0 -.nvm 0x8000 0x806dcb0 +.internal_storage 0x30000 0x803dcc8 +.zwave_nvm 0x0 0x806dcc8 +.nvm 0x8000 0x806dcc8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x122b8 0x0 -.debug_info 0xce039f 0x0 -.debug_abbrev 0x27ca7 0x0 -.debug_loclists 0x2cc07 0x0 +.debug_frame 0x122ac 0x0 +.debug_info 0xce1abb 0x0 +.debug_abbrev 0x27c32 0x0 +.debug_loclists 0x2cc7a 0x0 .debug_aranges 0x6790 0x0 -.debug_rnglists 0x4e2d 0x0 -.debug_line 0x760bd 0x0 -.debug_str 0x8fd74 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf05e05 +.debug_rnglists 0x4e33 0x0 +.debug_line 0x76192 0x0 +.debug_str 0x8fd5d 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf075ef The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230304 + 230328 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_EU_size.txt index 7f2683c635..ce99284171 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x30698 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x30698 -_zaf_cc_config 0x28 0x306a8 -_cc_handlers_v3 0x21c 0x306d0 -_zw_protocol_cmd_handlers 0x70 0x308ec -_zw_protocol_cmd_handlers_lr 0x30 0x3095c -.ARM.exidx 0x8 0x3098c -.copy.table 0xc 0x30994 -.zero.table 0x0 0x309a0 +.text 0x3068c 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x3068c +_zaf_cc_config 0x28 0x3069c +_cc_handlers_v3 0x21c 0x306c4 +_zw_protocol_cmd_handlers 0x70 0x308e0 +_zw_protocol_cmd_handlers_lr 0x30 0x30950 +.ARM.exidx 0x8 0x30980 +.copy.table 0xc 0x30988 +.zero.table 0x0 0x30994 .stack 0x1000 0x20000000 .data 0x5e0 0x20001000 .bss 0x9f98 0x200015e0 text_application_ram 0x0 0x2000b578 .heap 0x800 0x2000b578 -.internal_storage 0x3a000 0x309a0 -.zwave_nvm 0x3000 0x6a9a0 -.nvm 0x9000 0x6d9a0 +.internal_storage 0x3a000 0x30994 +.zwave_nvm 0x3000 0x6a994 +.nvm 0x9000 0x6d994 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf6cc 0x0 -.debug_info 0xc99d21 0x0 -.debug_abbrev 0x233ad 0x0 -.debug_loclists 0x191fe 0x0 -.debug_aranges 0x5ab8 0x0 -.debug_rnglists 0x3992 0x0 -.debug_line 0x61b81 0x0 -.debug_str 0x85127 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe8ab7e +.debug_frame 0xf6a0 0x0 +.debug_info 0xc99efb 0x0 +.debug_abbrev 0x23368 0x0 +.debug_loclists 0x191ea 0x0 +.debug_aranges 0x5ab0 0x0 +.debug_rnglists 0x39a1 0x0 +.debug_line 0x61b91 0x0 +.debug_str 0x850ef 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe8ac86 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 200576 + 200564 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_US_LR_size.txt index c98f285f8e..8d01ae0d29 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x30698 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x30698 -_zaf_cc_config 0x28 0x306a8 -_cc_handlers_v3 0x21c 0x306d0 -_zw_protocol_cmd_handlers 0x70 0x308ec -_zw_protocol_cmd_handlers_lr 0x30 0x3095c -.ARM.exidx 0x8 0x3098c -.copy.table 0xc 0x30994 -.zero.table 0x0 0x309a0 +.text 0x3068c 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x3068c +_zaf_cc_config 0x28 0x3069c +_cc_handlers_v3 0x21c 0x306c4 +_zw_protocol_cmd_handlers 0x70 0x308e0 +_zw_protocol_cmd_handlers_lr 0x30 0x30950 +.ARM.exidx 0x8 0x30980 +.copy.table 0xc 0x30988 +.zero.table 0x0 0x30994 .stack 0x1000 0x20000000 .data 0x5e0 0x20001000 .bss 0x9f98 0x200015e0 text_application_ram 0x0 0x2000b578 .heap 0x800 0x2000b578 -.internal_storage 0x3a000 0x309a0 -.zwave_nvm 0x3000 0x6a9a0 -.nvm 0x9000 0x6d9a0 +.internal_storage 0x3a000 0x30994 +.zwave_nvm 0x3000 0x6a994 +.nvm 0x9000 0x6d994 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf6cc 0x0 -.debug_info 0xc99d21 0x0 -.debug_abbrev 0x233ad 0x0 -.debug_loclists 0x191fe 0x0 -.debug_aranges 0x5ab8 0x0 -.debug_rnglists 0x3992 0x0 -.debug_line 0x61b81 0x0 -.debug_str 0x8511d 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe8ab74 +.debug_frame 0xf6a0 0x0 +.debug_info 0xc99efb 0x0 +.debug_abbrev 0x23368 0x0 +.debug_loclists 0x191ea 0x0 +.debug_aranges 0x5ab0 0x0 +.debug_rnglists 0x39a1 0x0 +.debug_line 0x61b91 0x0 +.debug_str 0x850e5 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe8ac7c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 200576 + 200564 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_US_size.txt index 7f2683c635..ce99284171 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x30698 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x30698 -_zaf_cc_config 0x28 0x306a8 -_cc_handlers_v3 0x21c 0x306d0 -_zw_protocol_cmd_handlers 0x70 0x308ec -_zw_protocol_cmd_handlers_lr 0x30 0x3095c -.ARM.exidx 0x8 0x3098c -.copy.table 0xc 0x30994 -.zero.table 0x0 0x309a0 +.text 0x3068c 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x3068c +_zaf_cc_config 0x28 0x3069c +_cc_handlers_v3 0x21c 0x306c4 +_zw_protocol_cmd_handlers 0x70 0x308e0 +_zw_protocol_cmd_handlers_lr 0x30 0x30950 +.ARM.exidx 0x8 0x30980 +.copy.table 0xc 0x30988 +.zero.table 0x0 0x30994 .stack 0x1000 0x20000000 .data 0x5e0 0x20001000 .bss 0x9f98 0x200015e0 text_application_ram 0x0 0x2000b578 .heap 0x800 0x2000b578 -.internal_storage 0x3a000 0x309a0 -.zwave_nvm 0x3000 0x6a9a0 -.nvm 0x9000 0x6d9a0 +.internal_storage 0x3a000 0x30994 +.zwave_nvm 0x3000 0x6a994 +.nvm 0x9000 0x6d994 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf6cc 0x0 -.debug_info 0xc99d21 0x0 -.debug_abbrev 0x233ad 0x0 -.debug_loclists 0x191fe 0x0 -.debug_aranges 0x5ab8 0x0 -.debug_rnglists 0x3992 0x0 -.debug_line 0x61b81 0x0 -.debug_str 0x85127 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe8ab7e +.debug_frame 0xf6a0 0x0 +.debug_info 0xc99efb 0x0 +.debug_abbrev 0x23368 0x0 +.debug_loclists 0x191ea 0x0 +.debug_aranges 0x5ab0 0x0 +.debug_rnglists 0x39a1 0x0 +.debug_line 0x61b91 0x0 +.debug_str 0x850ef 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe8ac86 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 200576 + 200564 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_EU_size.txt index ccbb2a424b..f39131bfb4 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x37044 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d044 -_zaf_cc_config 0x28 0x803d054 -_cc_handlers_v3 0x21c 0x803d07c -_zw_protocol_cmd_handlers 0x70 0x803d298 -_zw_protocol_cmd_handlers_lr 0x30 0x803d308 -.ARM.exidx 0x8 0x803d338 -.copy.table 0xc 0x803d340 -.zero.table 0x0 0x803d34c +.text 0x3705c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d05c +_zaf_cc_config 0x28 0x803d06c +_cc_handlers_v3 0x21c 0x803d094 +_zw_protocol_cmd_handlers 0x70 0x803d2b0 +_zw_protocol_cmd_handlers_lr 0x30 0x803d320 +.ARM.exidx 0x8 0x803d350 +.copy.table 0xc 0x803d358 +.zero.table 0x0 0x803d364 .stack 0x1000 0x20000000 .data 0x764 0x20001000 .bss 0xa974 0x20001764 text_application_ram 0x0 0x2000c0d8 .heap 0x800 0x2000c0d8 -.internal_storage 0x30000 0x803d34c -.zwave_nvm 0x0 0x806d34c -.nvm 0x8000 0x806d34c +.internal_storage 0x30000 0x803d364 +.zwave_nvm 0x0 0x806d364 +.nvm 0x8000 0x806d364 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x120dc 0x0 -.debug_info 0xce35c4 0x0 -.debug_abbrev 0x283cb 0x0 -.debug_loclists 0x29861 0x0 +.debug_frame 0x120d0 0x0 +.debug_info 0xce4cdc 0x0 +.debug_abbrev 0x28356 0x0 +.debug_loclists 0x298d4 0x0 .debug_aranges 0x67e0 0x0 -.debug_rnglists 0x4d7d 0x0 -.debug_line 0x755d7 0x0 -.debug_str 0x8f407 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf04429 +.debug_rnglists 0x4d83 0x0 +.debug_line 0x756a2 0x0 +.debug_str 0x8f3f0 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf05c05 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228016 + 228040 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_US_LR_size.txt index 9f9189d5e5..f6d098982b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x37044 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d044 -_zaf_cc_config 0x28 0x803d054 -_cc_handlers_v3 0x21c 0x803d07c -_zw_protocol_cmd_handlers 0x70 0x803d298 -_zw_protocol_cmd_handlers_lr 0x30 0x803d308 -.ARM.exidx 0x8 0x803d338 -.copy.table 0xc 0x803d340 -.zero.table 0x0 0x803d34c +.text 0x3705c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d05c +_zaf_cc_config 0x28 0x803d06c +_cc_handlers_v3 0x21c 0x803d094 +_zw_protocol_cmd_handlers 0x70 0x803d2b0 +_zw_protocol_cmd_handlers_lr 0x30 0x803d320 +.ARM.exidx 0x8 0x803d350 +.copy.table 0xc 0x803d358 +.zero.table 0x0 0x803d364 .stack 0x1000 0x20000000 .data 0x764 0x20001000 .bss 0xa974 0x20001764 text_application_ram 0x0 0x2000c0d8 .heap 0x800 0x2000c0d8 -.internal_storage 0x30000 0x803d34c -.zwave_nvm 0x0 0x806d34c -.nvm 0x8000 0x806d34c +.internal_storage 0x30000 0x803d364 +.zwave_nvm 0x0 0x806d364 +.nvm 0x8000 0x806d364 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x120dc 0x0 -.debug_info 0xce35c4 0x0 -.debug_abbrev 0x283cb 0x0 -.debug_loclists 0x29861 0x0 +.debug_frame 0x120d0 0x0 +.debug_info 0xce4cdc 0x0 +.debug_abbrev 0x28356 0x0 +.debug_loclists 0x298d4 0x0 .debug_aranges 0x67e0 0x0 -.debug_rnglists 0x4d7d 0x0 -.debug_line 0x755d7 0x0 -.debug_str 0x8f3fd 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf0441f +.debug_rnglists 0x4d83 0x0 +.debug_line 0x756a2 0x0 +.debug_str 0x8f3e6 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf05bfb The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228016 + 228040 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_US_size.txt index ccbb2a424b..f39131bfb4 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x37044 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d044 -_zaf_cc_config 0x28 0x803d054 -_cc_handlers_v3 0x21c 0x803d07c -_zw_protocol_cmd_handlers 0x70 0x803d298 -_zw_protocol_cmd_handlers_lr 0x30 0x803d308 -.ARM.exidx 0x8 0x803d338 -.copy.table 0xc 0x803d340 -.zero.table 0x0 0x803d34c +.text 0x3705c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d05c +_zaf_cc_config 0x28 0x803d06c +_cc_handlers_v3 0x21c 0x803d094 +_zw_protocol_cmd_handlers 0x70 0x803d2b0 +_zw_protocol_cmd_handlers_lr 0x30 0x803d320 +.ARM.exidx 0x8 0x803d350 +.copy.table 0xc 0x803d358 +.zero.table 0x0 0x803d364 .stack 0x1000 0x20000000 .data 0x764 0x20001000 .bss 0xa974 0x20001764 text_application_ram 0x0 0x2000c0d8 .heap 0x800 0x2000c0d8 -.internal_storage 0x30000 0x803d34c -.zwave_nvm 0x0 0x806d34c -.nvm 0x8000 0x806d34c +.internal_storage 0x30000 0x803d364 +.zwave_nvm 0x0 0x806d364 +.nvm 0x8000 0x806d364 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x120dc 0x0 -.debug_info 0xce35c4 0x0 -.debug_abbrev 0x283cb 0x0 -.debug_loclists 0x29861 0x0 +.debug_frame 0x120d0 0x0 +.debug_info 0xce4cdc 0x0 +.debug_abbrev 0x28356 0x0 +.debug_loclists 0x298d4 0x0 .debug_aranges 0x67e0 0x0 -.debug_rnglists 0x4d7d 0x0 -.debug_line 0x755d7 0x0 -.debug_str 0x8f407 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf04429 +.debug_rnglists 0x4d83 0x0 +.debug_line 0x756a2 0x0 +.debug_str 0x8f3f0 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf05c05 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228016 + 228040 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_EU_size.txt index ef96bc05b4..8ac73b756a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x37870 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d870 -_zaf_cc_config 0x28 0x803d880 -_cc_handlers_v3 0x21c 0x803d8a8 -_zw_protocol_cmd_handlers 0x70 0x803dac4 -_zw_protocol_cmd_handlers_lr 0x30 0x803db34 -.ARM.exidx 0x8 0x803db64 -.copy.table 0xc 0x803db6c -.zero.table 0x0 0x803db78 +.text 0x37888 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d888 +_zaf_cc_config 0x28 0x803d898 +_cc_handlers_v3 0x21c 0x803d8c0 +_zw_protocol_cmd_handlers 0x70 0x803dadc +_zw_protocol_cmd_handlers_lr 0x30 0x803db4c +.ARM.exidx 0x8 0x803db7c +.copy.table 0xc 0x803db84 +.zero.table 0x0 0x803db90 .stack 0x1000 0x20000000 .data 0x764 0x20001000 .bss 0xab14 0x20001764 text_application_ram 0x0 0x2000c278 .heap 0x800 0x2000c278 -.internal_storage 0x30000 0x803db78 -.zwave_nvm 0x0 0x806db78 -.nvm 0x8000 0x806db78 +.internal_storage 0x30000 0x803db90 +.zwave_nvm 0x0 0x806db90 +.nvm 0x8000 0x806db90 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1279c 0x0 -.debug_info 0xce9bec 0x0 -.debug_abbrev 0x28e8e 0x0 -.debug_loclists 0x2d3b3 0x0 +.debug_frame 0x12790 0x0 +.debug_info 0xceb304 0x0 +.debug_abbrev 0x28e19 0x0 +.debug_loclists 0x2d426 0x0 .debug_aranges 0x69d0 0x0 -.debug_rnglists 0x503f 0x0 -.debug_line 0x7857e 0x0 -.debug_str 0x8fe67 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf13fab +.debug_rnglists 0x5045 0x0 +.debug_line 0x7864b 0x0 +.debug_str 0x8fe50 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf15789 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230108 + 230132 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_US_LR_size.txt index dc720409cc..3ae39060d4 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x37870 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d870 -_zaf_cc_config 0x28 0x803d880 -_cc_handlers_v3 0x21c 0x803d8a8 -_zw_protocol_cmd_handlers 0x70 0x803dac4 -_zw_protocol_cmd_handlers_lr 0x30 0x803db34 -.ARM.exidx 0x8 0x803db64 -.copy.table 0xc 0x803db6c -.zero.table 0x0 0x803db78 +.text 0x37888 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d888 +_zaf_cc_config 0x28 0x803d898 +_cc_handlers_v3 0x21c 0x803d8c0 +_zw_protocol_cmd_handlers 0x70 0x803dadc +_zw_protocol_cmd_handlers_lr 0x30 0x803db4c +.ARM.exidx 0x8 0x803db7c +.copy.table 0xc 0x803db84 +.zero.table 0x0 0x803db90 .stack 0x1000 0x20000000 .data 0x764 0x20001000 .bss 0xab14 0x20001764 text_application_ram 0x0 0x2000c278 .heap 0x800 0x2000c278 -.internal_storage 0x30000 0x803db78 -.zwave_nvm 0x0 0x806db78 -.nvm 0x8000 0x806db78 +.internal_storage 0x30000 0x803db90 +.zwave_nvm 0x0 0x806db90 +.nvm 0x8000 0x806db90 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1279c 0x0 -.debug_info 0xce9bec 0x0 -.debug_abbrev 0x28e8e 0x0 -.debug_loclists 0x2d3b3 0x0 +.debug_frame 0x12790 0x0 +.debug_info 0xceb304 0x0 +.debug_abbrev 0x28e19 0x0 +.debug_loclists 0x2d426 0x0 .debug_aranges 0x69d0 0x0 -.debug_rnglists 0x503f 0x0 -.debug_line 0x7857e 0x0 -.debug_str 0x8fe5d 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf13fa1 +.debug_rnglists 0x5045 0x0 +.debug_line 0x7864b 0x0 +.debug_str 0x8fe46 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf1577f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230108 + 230132 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_US_size.txt index ef96bc05b4..8ac73b756a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x37870 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d870 -_zaf_cc_config 0x28 0x803d880 -_cc_handlers_v3 0x21c 0x803d8a8 -_zw_protocol_cmd_handlers 0x70 0x803dac4 -_zw_protocol_cmd_handlers_lr 0x30 0x803db34 -.ARM.exidx 0x8 0x803db64 -.copy.table 0xc 0x803db6c -.zero.table 0x0 0x803db78 +.text 0x37888 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d888 +_zaf_cc_config 0x28 0x803d898 +_cc_handlers_v3 0x21c 0x803d8c0 +_zw_protocol_cmd_handlers 0x70 0x803dadc +_zw_protocol_cmd_handlers_lr 0x30 0x803db4c +.ARM.exidx 0x8 0x803db7c +.copy.table 0xc 0x803db84 +.zero.table 0x0 0x803db90 .stack 0x1000 0x20000000 .data 0x764 0x20001000 .bss 0xab14 0x20001764 text_application_ram 0x0 0x2000c278 .heap 0x800 0x2000c278 -.internal_storage 0x30000 0x803db78 -.zwave_nvm 0x0 0x806db78 -.nvm 0x8000 0x806db78 +.internal_storage 0x30000 0x803db90 +.zwave_nvm 0x0 0x806db90 +.nvm 0x8000 0x806db90 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1279c 0x0 -.debug_info 0xce9bec 0x0 -.debug_abbrev 0x28e8e 0x0 -.debug_loclists 0x2d3b3 0x0 +.debug_frame 0x12790 0x0 +.debug_info 0xceb304 0x0 +.debug_abbrev 0x28e19 0x0 +.debug_loclists 0x2d426 0x0 .debug_aranges 0x69d0 0x0 -.debug_rnglists 0x503f 0x0 -.debug_line 0x7857e 0x0 -.debug_str 0x8fe67 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf13fab +.debug_rnglists 0x5045 0x0 +.debug_line 0x7864b 0x0 +.debug_str 0x8fe50 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf15789 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230108 + 230132 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_EU_size.txt index 7f2683c635..ce99284171 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x30698 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x30698 -_zaf_cc_config 0x28 0x306a8 -_cc_handlers_v3 0x21c 0x306d0 -_zw_protocol_cmd_handlers 0x70 0x308ec -_zw_protocol_cmd_handlers_lr 0x30 0x3095c -.ARM.exidx 0x8 0x3098c -.copy.table 0xc 0x30994 -.zero.table 0x0 0x309a0 +.text 0x3068c 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x3068c +_zaf_cc_config 0x28 0x3069c +_cc_handlers_v3 0x21c 0x306c4 +_zw_protocol_cmd_handlers 0x70 0x308e0 +_zw_protocol_cmd_handlers_lr 0x30 0x30950 +.ARM.exidx 0x8 0x30980 +.copy.table 0xc 0x30988 +.zero.table 0x0 0x30994 .stack 0x1000 0x20000000 .data 0x5e0 0x20001000 .bss 0x9f98 0x200015e0 text_application_ram 0x0 0x2000b578 .heap 0x800 0x2000b578 -.internal_storage 0x3a000 0x309a0 -.zwave_nvm 0x3000 0x6a9a0 -.nvm 0x9000 0x6d9a0 +.internal_storage 0x3a000 0x30994 +.zwave_nvm 0x3000 0x6a994 +.nvm 0x9000 0x6d994 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf6cc 0x0 -.debug_info 0xc99d21 0x0 -.debug_abbrev 0x233ad 0x0 -.debug_loclists 0x191fe 0x0 -.debug_aranges 0x5ab8 0x0 -.debug_rnglists 0x3992 0x0 -.debug_line 0x61b81 0x0 -.debug_str 0x85127 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe8ab7e +.debug_frame 0xf6a0 0x0 +.debug_info 0xc99efb 0x0 +.debug_abbrev 0x23368 0x0 +.debug_loclists 0x191ea 0x0 +.debug_aranges 0x5ab0 0x0 +.debug_rnglists 0x39a1 0x0 +.debug_line 0x61b91 0x0 +.debug_str 0x850ef 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe8ac86 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 200576 + 200564 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_US_LR_size.txt index c98f285f8e..8d01ae0d29 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x30698 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x30698 -_zaf_cc_config 0x28 0x306a8 -_cc_handlers_v3 0x21c 0x306d0 -_zw_protocol_cmd_handlers 0x70 0x308ec -_zw_protocol_cmd_handlers_lr 0x30 0x3095c -.ARM.exidx 0x8 0x3098c -.copy.table 0xc 0x30994 -.zero.table 0x0 0x309a0 +.text 0x3068c 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x3068c +_zaf_cc_config 0x28 0x3069c +_cc_handlers_v3 0x21c 0x306c4 +_zw_protocol_cmd_handlers 0x70 0x308e0 +_zw_protocol_cmd_handlers_lr 0x30 0x30950 +.ARM.exidx 0x8 0x30980 +.copy.table 0xc 0x30988 +.zero.table 0x0 0x30994 .stack 0x1000 0x20000000 .data 0x5e0 0x20001000 .bss 0x9f98 0x200015e0 text_application_ram 0x0 0x2000b578 .heap 0x800 0x2000b578 -.internal_storage 0x3a000 0x309a0 -.zwave_nvm 0x3000 0x6a9a0 -.nvm 0x9000 0x6d9a0 +.internal_storage 0x3a000 0x30994 +.zwave_nvm 0x3000 0x6a994 +.nvm 0x9000 0x6d994 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf6cc 0x0 -.debug_info 0xc99d21 0x0 -.debug_abbrev 0x233ad 0x0 -.debug_loclists 0x191fe 0x0 -.debug_aranges 0x5ab8 0x0 -.debug_rnglists 0x3992 0x0 -.debug_line 0x61b81 0x0 -.debug_str 0x8511d 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe8ab74 +.debug_frame 0xf6a0 0x0 +.debug_info 0xc99efb 0x0 +.debug_abbrev 0x23368 0x0 +.debug_loclists 0x191ea 0x0 +.debug_aranges 0x5ab0 0x0 +.debug_rnglists 0x39a1 0x0 +.debug_line 0x61b91 0x0 +.debug_str 0x850e5 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe8ac7c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 200576 + 200564 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_US_size.txt index 7f2683c635..ce99284171 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x30698 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x30698 -_zaf_cc_config 0x28 0x306a8 -_cc_handlers_v3 0x21c 0x306d0 -_zw_protocol_cmd_handlers 0x70 0x308ec -_zw_protocol_cmd_handlers_lr 0x30 0x3095c -.ARM.exidx 0x8 0x3098c -.copy.table 0xc 0x30994 -.zero.table 0x0 0x309a0 +.text 0x3068c 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x3068c +_zaf_cc_config 0x28 0x3069c +_cc_handlers_v3 0x21c 0x306c4 +_zw_protocol_cmd_handlers 0x70 0x308e0 +_zw_protocol_cmd_handlers_lr 0x30 0x30950 +.ARM.exidx 0x8 0x30980 +.copy.table 0xc 0x30988 +.zero.table 0x0 0x30994 .stack 0x1000 0x20000000 .data 0x5e0 0x20001000 .bss 0x9f98 0x200015e0 text_application_ram 0x0 0x2000b578 .heap 0x800 0x2000b578 -.internal_storage 0x3a000 0x309a0 -.zwave_nvm 0x3000 0x6a9a0 -.nvm 0x9000 0x6d9a0 +.internal_storage 0x3a000 0x30994 +.zwave_nvm 0x3000 0x6a994 +.nvm 0x9000 0x6d994 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf6cc 0x0 -.debug_info 0xc99d21 0x0 -.debug_abbrev 0x233ad 0x0 -.debug_loclists 0x191fe 0x0 -.debug_aranges 0x5ab8 0x0 -.debug_rnglists 0x3992 0x0 -.debug_line 0x61b81 0x0 -.debug_str 0x85127 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe8ab7e +.debug_frame 0xf6a0 0x0 +.debug_info 0xc99efb 0x0 +.debug_abbrev 0x23368 0x0 +.debug_loclists 0x191ea 0x0 +.debug_aranges 0x5ab0 0x0 +.debug_rnglists 0x39a1 0x0 +.debug_line 0x61b91 0x0 +.debug_str 0x850ef 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe8ac86 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 200576 + 200564 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4209A_REGION_US_LR_size.txt index 3e5a65c73a..533701952b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4209A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x305d0 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x305d0 -_zaf_cc_config 0x28 0x305e0 -_cc_handlers_v3 0x21c 0x30608 -_zw_protocol_cmd_handlers 0x70 0x30824 -_zw_protocol_cmd_handlers_lr 0x30 0x30894 -.ARM.exidx 0x8 0x308c4 -.copy.table 0xc 0x308cc -.zero.table 0x0 0x308d8 +.text 0x305e4 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x305e4 +_zaf_cc_config 0x28 0x305f4 +_cc_handlers_v3 0x21c 0x3061c +_zw_protocol_cmd_handlers 0x70 0x30838 +_zw_protocol_cmd_handlers_lr 0x30 0x308a8 +.ARM.exidx 0x8 0x308d8 +.copy.table 0xc 0x308e0 +.zero.table 0x0 0x308ec .stack 0x1000 0x20000000 .data 0x5dc 0x20001000 .bss 0x9f80 0x200015dc text_application_ram 0x0 0x2000b55c .heap 0x800 0x2000b560 -.internal_storage 0x3a000 0x308d8 -.zwave_nvm 0x3000 0x6a8d8 -.nvm 0x9000 0x6d8d8 +.internal_storage 0x3a000 0x308ec +.zwave_nvm 0x3000 0x6a8ec +.nvm 0x9000 0x6d8ec .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf89c 0x0 -.debug_info 0xc9b302 0x0 -.debug_abbrev 0x238f0 0x0 -.debug_loclists 0x1989b 0x0 -.debug_aranges 0x5b58 0x0 -.debug_rnglists 0x3a3d 0x0 -.debug_line 0x62bc3 0x0 -.debug_str 0x8544f 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe8e2e0 +.debug_frame 0xf870 0x0 +.debug_info 0xc9b4dc 0x0 +.debug_abbrev 0x238ab 0x0 +.debug_loclists 0x19887 0x0 +.debug_aranges 0x5b50 0x0 +.debug_rnglists 0x3a4c 0x0 +.debug_line 0x62bdd 0x0 +.debug_str 0x85417 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe8e412 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 200372 + 200392 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_EU_size.txt index 85b9ac83ea..f13a5ad248 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x3abac 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x8040bac -_zaf_cc_config 0x8 0x8040bbc -_cc_handlers_v3 0x240 0x8040bc4 -_zw_protocol_cmd_handlers 0x70 0x8040e04 -_zw_protocol_cmd_handlers_lr 0x30 0x8040e74 -.ARM.exidx 0x8 0x8040ea4 -.copy.table 0xc 0x8040eac -.zero.table 0x0 0x8040eb8 +.text 0x3abc4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x8040bc4 +_zaf_cc_config 0x8 0x8040bd4 +_cc_handlers_v3 0x240 0x8040bdc +_zw_protocol_cmd_handlers 0x70 0x8040e1c +_zw_protocol_cmd_handlers_lr 0x30 0x8040e8c +.ARM.exidx 0x8 0x8040ebc +.copy.table 0xc 0x8040ec4 +.zero.table 0x0 0x8040ed0 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xad34 0x200015b4 text_application_ram 0x0 0x2000c2e8 .heap 0x800 0x2000c2e8 -.internal_storage 0x30000 0x8040eb8 -.zwave_nvm 0x0 0x8070eb8 -.nvm 0x8000 0x8070eb8 +.internal_storage 0x30000 0x8040ed0 +.zwave_nvm 0x0 0x8070ed0 +.nvm 0x8000 0x8070ed0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x2a7 0x0 -.debug_frame 0x13bec 0x0 -.debug_info 0xd5cee0 0x0 -.debug_abbrev 0x2b11f 0x0 +.debug_frame 0x13be0 0x0 +.debug_info 0xd5e5f8 0x0 +.debug_abbrev 0x2b0aa 0x0 .debug_aranges 0x7038 0x0 -.debug_rnglists 0x582b 0x0 -.debug_line 0x7eb5e 0x0 -.debug_str 0x94945 0x0 -.debug_loclists 0x31f35 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf9e7d1 +.debug_rnglists 0x5831 0x0 +.debug_line 0x7ec2b 0x0 +.debug_str 0x9492e 0x0 +.debug_loclists 0x31fa8 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf9ffaf The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 242796 + 242820 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_US_LR_size.txt index b3985c46a4..5360d966ea 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x3abac 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x8040bac -_zaf_cc_config 0x8 0x8040bbc -_cc_handlers_v3 0x240 0x8040bc4 -_zw_protocol_cmd_handlers 0x70 0x8040e04 -_zw_protocol_cmd_handlers_lr 0x30 0x8040e74 -.ARM.exidx 0x8 0x8040ea4 -.copy.table 0xc 0x8040eac -.zero.table 0x0 0x8040eb8 +.text 0x3abc4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x8040bc4 +_zaf_cc_config 0x8 0x8040bd4 +_cc_handlers_v3 0x240 0x8040bdc +_zw_protocol_cmd_handlers 0x70 0x8040e1c +_zw_protocol_cmd_handlers_lr 0x30 0x8040e8c +.ARM.exidx 0x8 0x8040ebc +.copy.table 0xc 0x8040ec4 +.zero.table 0x0 0x8040ed0 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xad34 0x200015b4 text_application_ram 0x0 0x2000c2e8 .heap 0x800 0x2000c2e8 -.internal_storage 0x30000 0x8040eb8 -.zwave_nvm 0x0 0x8070eb8 -.nvm 0x8000 0x8070eb8 +.internal_storage 0x30000 0x8040ed0 +.zwave_nvm 0x0 0x8070ed0 +.nvm 0x8000 0x8070ed0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x2a7 0x0 -.debug_frame 0x13bec 0x0 -.debug_info 0xd5cee0 0x0 -.debug_abbrev 0x2b11f 0x0 +.debug_frame 0x13be0 0x0 +.debug_info 0xd5e5f8 0x0 +.debug_abbrev 0x2b0aa 0x0 .debug_aranges 0x7038 0x0 -.debug_rnglists 0x582b 0x0 -.debug_line 0x7eb5e 0x0 -.debug_str 0x9493b 0x0 -.debug_loclists 0x31f35 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf9e7c7 +.debug_rnglists 0x5831 0x0 +.debug_line 0x7ec2b 0x0 +.debug_str 0x94924 0x0 +.debug_loclists 0x31fa8 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf9ffa5 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 242796 + 242820 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_US_size.txt index 85b9ac83ea..f13a5ad248 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x3abac 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x8040bac -_zaf_cc_config 0x8 0x8040bbc -_cc_handlers_v3 0x240 0x8040bc4 -_zw_protocol_cmd_handlers 0x70 0x8040e04 -_zw_protocol_cmd_handlers_lr 0x30 0x8040e74 -.ARM.exidx 0x8 0x8040ea4 -.copy.table 0xc 0x8040eac -.zero.table 0x0 0x8040eb8 +.text 0x3abc4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x8040bc4 +_zaf_cc_config 0x8 0x8040bd4 +_cc_handlers_v3 0x240 0x8040bdc +_zw_protocol_cmd_handlers 0x70 0x8040e1c +_zw_protocol_cmd_handlers_lr 0x30 0x8040e8c +.ARM.exidx 0x8 0x8040ebc +.copy.table 0xc 0x8040ec4 +.zero.table 0x0 0x8040ed0 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xad34 0x200015b4 text_application_ram 0x0 0x2000c2e8 .heap 0x800 0x2000c2e8 -.internal_storage 0x30000 0x8040eb8 -.zwave_nvm 0x0 0x8070eb8 -.nvm 0x8000 0x8070eb8 +.internal_storage 0x30000 0x8040ed0 +.zwave_nvm 0x0 0x8070ed0 +.nvm 0x8000 0x8070ed0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x2a7 0x0 -.debug_frame 0x13bec 0x0 -.debug_info 0xd5cee0 0x0 -.debug_abbrev 0x2b11f 0x0 +.debug_frame 0x13be0 0x0 +.debug_info 0xd5e5f8 0x0 +.debug_abbrev 0x2b0aa 0x0 .debug_aranges 0x7038 0x0 -.debug_rnglists 0x582b 0x0 -.debug_line 0x7eb5e 0x0 -.debug_str 0x94945 0x0 -.debug_loclists 0x31f35 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf9e7d1 +.debug_rnglists 0x5831 0x0 +.debug_line 0x7ec2b 0x0 +.debug_str 0x9492e 0x0 +.debug_loclists 0x31fa8 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf9ffaf The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 242796 + 242820 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2705A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2705A_REGION_EU_size.txt index 55d5996210..14847887f8 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2705A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2705A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x388c4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e8c4 -_zaf_cc_config 0x8 0x803e8d4 -_cc_handlers_v3 0x240 0x803e8dc -_zw_protocol_cmd_handlers 0x70 0x803eb1c -_zw_protocol_cmd_handlers_lr 0x30 0x803eb8c -.ARM.exidx 0x8 0x803ebbc -.copy.table 0xc 0x803ebc4 -.zero.table 0x0 0x803ebd0 +.text 0x388dc 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e8dc +_zaf_cc_config 0x8 0x803e8ec +_cc_handlers_v3 0x240 0x803e8f4 +_zw_protocol_cmd_handlers 0x70 0x803eb34 +_zw_protocol_cmd_handlers_lr 0x30 0x803eba4 +.ARM.exidx 0x8 0x803ebd4 +.copy.table 0xc 0x803ebdc +.zero.table 0x0 0x803ebe8 .stack 0x1000 0x20000000 .data 0x598 0x20001000 .bss 0xab94 0x20001598 text_application_ram 0x0 0x2000c12c .heap 0x800 0x2000c130 -.internal_storage 0x30000 0x803ebd0 -.zwave_nvm 0x0 0x806ebd0 -.nvm 0x8000 0x806ebd0 +.internal_storage 0x30000 0x803ebe8 +.zwave_nvm 0x0 0x806ebe8 +.nvm 0x8000 0x806ebe8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x128ac 0x0 -.debug_info 0xd496aa 0x0 -.debug_abbrev 0x287be 0x0 +.debug_frame 0x128a0 0x0 +.debug_info 0xd4adc6 0x0 +.debug_abbrev 0x28749 0x0 .debug_aranges 0x6a18 0x0 -.debug_rnglists 0x520d 0x0 -.debug_line 0x78415 0x0 -.debug_str 0x9261b 0x0 -.debug_loclists 0x2ea12 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf78171 +.debug_rnglists 0x5213 0x0 +.debug_line 0x784ea 0x0 +.debug_str 0x92604 0x0 +.debug_loclists 0x2ea85 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf7995b The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 233832 + 233856 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2705A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2705A_REGION_US_LR_size.txt index 57ac12258c..369bdbe324 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2705A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2705A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x388c4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e8c4 -_zaf_cc_config 0x8 0x803e8d4 -_cc_handlers_v3 0x240 0x803e8dc -_zw_protocol_cmd_handlers 0x70 0x803eb1c -_zw_protocol_cmd_handlers_lr 0x30 0x803eb8c -.ARM.exidx 0x8 0x803ebbc -.copy.table 0xc 0x803ebc4 -.zero.table 0x0 0x803ebd0 +.text 0x388dc 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e8dc +_zaf_cc_config 0x8 0x803e8ec +_cc_handlers_v3 0x240 0x803e8f4 +_zw_protocol_cmd_handlers 0x70 0x803eb34 +_zw_protocol_cmd_handlers_lr 0x30 0x803eba4 +.ARM.exidx 0x8 0x803ebd4 +.copy.table 0xc 0x803ebdc +.zero.table 0x0 0x803ebe8 .stack 0x1000 0x20000000 .data 0x598 0x20001000 .bss 0xab94 0x20001598 text_application_ram 0x0 0x2000c12c .heap 0x800 0x2000c130 -.internal_storage 0x30000 0x803ebd0 -.zwave_nvm 0x0 0x806ebd0 -.nvm 0x8000 0x806ebd0 +.internal_storage 0x30000 0x803ebe8 +.zwave_nvm 0x0 0x806ebe8 +.nvm 0x8000 0x806ebe8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x128ac 0x0 -.debug_info 0xd496aa 0x0 -.debug_abbrev 0x287be 0x0 +.debug_frame 0x128a0 0x0 +.debug_info 0xd4adc6 0x0 +.debug_abbrev 0x28749 0x0 .debug_aranges 0x6a18 0x0 -.debug_rnglists 0x520d 0x0 -.debug_line 0x78415 0x0 -.debug_str 0x92611 0x0 -.debug_loclists 0x2ea12 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf78167 +.debug_rnglists 0x5213 0x0 +.debug_line 0x784ea 0x0 +.debug_str 0x925fa 0x0 +.debug_loclists 0x2ea85 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf79951 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 233832 + 233856 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2705A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2705A_REGION_US_size.txt index 55d5996210..14847887f8 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2705A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2705A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x388c4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e8c4 -_zaf_cc_config 0x8 0x803e8d4 -_cc_handlers_v3 0x240 0x803e8dc -_zw_protocol_cmd_handlers 0x70 0x803eb1c -_zw_protocol_cmd_handlers_lr 0x30 0x803eb8c -.ARM.exidx 0x8 0x803ebbc -.copy.table 0xc 0x803ebc4 -.zero.table 0x0 0x803ebd0 +.text 0x388dc 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e8dc +_zaf_cc_config 0x8 0x803e8ec +_cc_handlers_v3 0x240 0x803e8f4 +_zw_protocol_cmd_handlers 0x70 0x803eb34 +_zw_protocol_cmd_handlers_lr 0x30 0x803eba4 +.ARM.exidx 0x8 0x803ebd4 +.copy.table 0xc 0x803ebdc +.zero.table 0x0 0x803ebe8 .stack 0x1000 0x20000000 .data 0x598 0x20001000 .bss 0xab94 0x20001598 text_application_ram 0x0 0x2000c12c .heap 0x800 0x2000c130 -.internal_storage 0x30000 0x803ebd0 -.zwave_nvm 0x0 0x806ebd0 -.nvm 0x8000 0x806ebd0 +.internal_storage 0x30000 0x803ebe8 +.zwave_nvm 0x0 0x806ebe8 +.nvm 0x8000 0x806ebe8 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x128ac 0x0 -.debug_info 0xd496aa 0x0 -.debug_abbrev 0x287be 0x0 +.debug_frame 0x128a0 0x0 +.debug_info 0xd4adc6 0x0 +.debug_abbrev 0x28749 0x0 .debug_aranges 0x6a18 0x0 -.debug_rnglists 0x520d 0x0 -.debug_line 0x78415 0x0 -.debug_str 0x9261b 0x0 -.debug_loclists 0x2ea12 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf78171 +.debug_rnglists 0x5213 0x0 +.debug_line 0x784ea 0x0 +.debug_str 0x92604 0x0 +.debug_loclists 0x2ea85 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf7995b The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 233832 + 233856 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_EU_size.txt index 0a4f19eb84..1ea2a087ae 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x31bac 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x31bac -_zaf_cc_config 0x8 0x31bbc -_cc_handlers_v3 0x240 0x31bc4 -_zw_protocol_cmd_handlers 0x70 0x31e04 -_zw_protocol_cmd_handlers_lr 0x30 0x31e74 -.ARM.exidx 0x8 0x31ea4 -.copy.table 0xc 0x31eac -.zero.table 0x0 0x31eb8 +.text 0x31bc0 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x31bc0 +_zaf_cc_config 0x8 0x31bd0 +_cc_handlers_v3 0x240 0x31bd8 +_zw_protocol_cmd_handlers 0x70 0x31e18 +_zw_protocol_cmd_handlers_lr 0x30 0x31e88 +.ARM.exidx 0x8 0x31eb8 +.copy.table 0xc 0x31ec0 +.zero.table 0x0 0x31ecc .stack 0x1000 0x20000000 .data 0x434 0x20001000 .bss 0xa0d0 0x20001434 text_application_ram 0x0 0x2000b504 .heap 0x800 0x2000b508 -.internal_storage 0x3a000 0x31eb8 -.zwave_nvm 0x3000 0x6beb8 -.nvm 0x9000 0x6eeb8 +.internal_storage 0x3a000 0x31ecc +.zwave_nvm 0x3000 0x6becc +.nvm 0x9000 0x6eecc .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xff18 0x0 -.debug_info 0xd0798d 0x0 -.debug_abbrev 0x24791 0x0 -.debug_aranges 0x5dd8 0x0 -.debug_rnglists 0x3d9c 0x0 -.debug_line 0x652eb 0x0 -.debug_str 0x88f23 0x0 -.debug_loclists 0x1c181 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xf064d1 +.debug_frame 0xfeec 0x0 +.debug_info 0xd07b67 0x0 +.debug_abbrev 0x2474c 0x0 +.debug_aranges 0x5dd0 0x0 +.debug_rnglists 0x3dab 0x0 +.debug_line 0x652fb 0x0 +.debug_str 0x88eeb 0x0 +.debug_loclists 0x1c16d 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xf065f9 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 205548 + 205568 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_US_LR_size.txt index ebf53299c3..ef52a16359 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x31bac 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x31bac -_zaf_cc_config 0x8 0x31bbc -_cc_handlers_v3 0x240 0x31bc4 -_zw_protocol_cmd_handlers 0x70 0x31e04 -_zw_protocol_cmd_handlers_lr 0x30 0x31e74 -.ARM.exidx 0x8 0x31ea4 -.copy.table 0xc 0x31eac -.zero.table 0x0 0x31eb8 +.text 0x31bc0 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x31bc0 +_zaf_cc_config 0x8 0x31bd0 +_cc_handlers_v3 0x240 0x31bd8 +_zw_protocol_cmd_handlers 0x70 0x31e18 +_zw_protocol_cmd_handlers_lr 0x30 0x31e88 +.ARM.exidx 0x8 0x31eb8 +.copy.table 0xc 0x31ec0 +.zero.table 0x0 0x31ecc .stack 0x1000 0x20000000 .data 0x434 0x20001000 .bss 0xa0d0 0x20001434 text_application_ram 0x0 0x2000b504 .heap 0x800 0x2000b508 -.internal_storage 0x3a000 0x31eb8 -.zwave_nvm 0x3000 0x6beb8 -.nvm 0x9000 0x6eeb8 +.internal_storage 0x3a000 0x31ecc +.zwave_nvm 0x3000 0x6becc +.nvm 0x9000 0x6eecc .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xff18 0x0 -.debug_info 0xd0798d 0x0 -.debug_abbrev 0x24791 0x0 -.debug_aranges 0x5dd8 0x0 -.debug_rnglists 0x3d9c 0x0 -.debug_line 0x652eb 0x0 -.debug_str 0x88f19 0x0 -.debug_loclists 0x1c181 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xf064c7 +.debug_frame 0xfeec 0x0 +.debug_info 0xd07b67 0x0 +.debug_abbrev 0x2474c 0x0 +.debug_aranges 0x5dd0 0x0 +.debug_rnglists 0x3dab 0x0 +.debug_line 0x652fb 0x0 +.debug_str 0x88ee1 0x0 +.debug_loclists 0x1c16d 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xf065ef The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 205548 + 205568 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_US_size.txt index 0a4f19eb84..1ea2a087ae 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x31bac 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x31bac -_zaf_cc_config 0x8 0x31bbc -_cc_handlers_v3 0x240 0x31bc4 -_zw_protocol_cmd_handlers 0x70 0x31e04 -_zw_protocol_cmd_handlers_lr 0x30 0x31e74 -.ARM.exidx 0x8 0x31ea4 -.copy.table 0xc 0x31eac -.zero.table 0x0 0x31eb8 +.text 0x31bc0 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x31bc0 +_zaf_cc_config 0x8 0x31bd0 +_cc_handlers_v3 0x240 0x31bd8 +_zw_protocol_cmd_handlers 0x70 0x31e18 +_zw_protocol_cmd_handlers_lr 0x30 0x31e88 +.ARM.exidx 0x8 0x31eb8 +.copy.table 0xc 0x31ec0 +.zero.table 0x0 0x31ecc .stack 0x1000 0x20000000 .data 0x434 0x20001000 .bss 0xa0d0 0x20001434 text_application_ram 0x0 0x2000b504 .heap 0x800 0x2000b508 -.internal_storage 0x3a000 0x31eb8 -.zwave_nvm 0x3000 0x6beb8 -.nvm 0x9000 0x6eeb8 +.internal_storage 0x3a000 0x31ecc +.zwave_nvm 0x3000 0x6becc +.nvm 0x9000 0x6eecc .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xff18 0x0 -.debug_info 0xd0798d 0x0 -.debug_abbrev 0x24791 0x0 -.debug_aranges 0x5dd8 0x0 -.debug_rnglists 0x3d9c 0x0 -.debug_line 0x652eb 0x0 -.debug_str 0x88f23 0x0 -.debug_loclists 0x1c181 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xf064d1 +.debug_frame 0xfeec 0x0 +.debug_info 0xd07b67 0x0 +.debug_abbrev 0x2474c 0x0 +.debug_aranges 0x5dd0 0x0 +.debug_rnglists 0x3dab 0x0 +.debug_line 0x652fb 0x0 +.debug_str 0x88eeb 0x0 +.debug_loclists 0x1c16d 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xf065f9 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 205548 + 205568 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_EU_size.txt index 2e91651677..871985344e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x38a68 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803ea68 -_zaf_cc_config 0x8 0x803ea78 -_cc_handlers_v3 0x240 0x803ea80 -_zw_protocol_cmd_handlers 0x70 0x803ecc0 -_zw_protocol_cmd_handlers_lr 0x30 0x803ed30 -.ARM.exidx 0x8 0x803ed60 -.copy.table 0xc 0x803ed68 -.zero.table 0x0 0x803ed74 +.text 0x38aa0 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803eaa0 +_zaf_cc_config 0x8 0x803eab0 +_cc_handlers_v3 0x240 0x803eab8 +_zw_protocol_cmd_handlers 0x70 0x803ecf8 +_zw_protocol_cmd_handlers_lr 0x30 0x803ed68 +.ARM.exidx 0x8 0x803ed98 +.copy.table 0xc 0x803eda0 +.zero.table 0x0 0x803edac .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xac40 0x200015b0 text_application_ram 0x0 0x2000c1f0 .heap 0x800 0x2000c1f0 -.internal_storage 0x30000 0x803ed74 -.zwave_nvm 0x0 0x806ed74 -.nvm 0x8000 0x806ed74 +.internal_storage 0x30000 0x803edac +.zwave_nvm 0x0 0x806edac +.nvm 0x8000 0x806edac .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12fd4 0x0 -.debug_info 0xd5463b 0x0 -.debug_abbrev 0x2a038 0x0 +.debug_frame 0x12fc8 0x0 +.debug_info 0xd55d53 0x0 +.debug_abbrev 0x29fc3 0x0 .debug_aranges 0x6c78 0x0 -.debug_rnglists 0x54fe 0x0 -.debug_line 0x7bd99 0x0 -.debug_str 0x926b9 0x0 -.debug_loclists 0x304a6 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf8ae26 +.debug_rnglists 0x5504 0x0 +.debug_line 0x7be6e 0x0 +.debug_str 0x926a2 0x0 +.debug_loclists 0x30519 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf8c62c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 234276 + 234332 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_US_LR_size.txt index 67d6c6397b..4f063d0da9 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x38a68 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803ea68 -_zaf_cc_config 0x8 0x803ea78 -_cc_handlers_v3 0x240 0x803ea80 -_zw_protocol_cmd_handlers 0x70 0x803ecc0 -_zw_protocol_cmd_handlers_lr 0x30 0x803ed30 -.ARM.exidx 0x8 0x803ed60 -.copy.table 0xc 0x803ed68 -.zero.table 0x0 0x803ed74 +.text 0x38aa0 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803eaa0 +_zaf_cc_config 0x8 0x803eab0 +_cc_handlers_v3 0x240 0x803eab8 +_zw_protocol_cmd_handlers 0x70 0x803ecf8 +_zw_protocol_cmd_handlers_lr 0x30 0x803ed68 +.ARM.exidx 0x8 0x803ed98 +.copy.table 0xc 0x803eda0 +.zero.table 0x0 0x803edac .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xac40 0x200015b0 text_application_ram 0x0 0x2000c1f0 .heap 0x800 0x2000c1f0 -.internal_storage 0x30000 0x803ed74 -.zwave_nvm 0x0 0x806ed74 -.nvm 0x8000 0x806ed74 +.internal_storage 0x30000 0x803edac +.zwave_nvm 0x0 0x806edac +.nvm 0x8000 0x806edac .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12fd4 0x0 -.debug_info 0xd5463b 0x0 -.debug_abbrev 0x2a038 0x0 +.debug_frame 0x12fc8 0x0 +.debug_info 0xd55d53 0x0 +.debug_abbrev 0x29fc3 0x0 .debug_aranges 0x6c78 0x0 -.debug_rnglists 0x54fe 0x0 -.debug_line 0x7bd99 0x0 -.debug_str 0x926af 0x0 -.debug_loclists 0x304a6 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf8ae1c +.debug_rnglists 0x5504 0x0 +.debug_line 0x7be6e 0x0 +.debug_str 0x92698 0x0 +.debug_loclists 0x30519 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf8c622 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 234276 + 234332 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_US_size.txt index 2e91651677..871985344e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x38a68 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803ea68 -_zaf_cc_config 0x8 0x803ea78 -_cc_handlers_v3 0x240 0x803ea80 -_zw_protocol_cmd_handlers 0x70 0x803ecc0 -_zw_protocol_cmd_handlers_lr 0x30 0x803ed30 -.ARM.exidx 0x8 0x803ed60 -.copy.table 0xc 0x803ed68 -.zero.table 0x0 0x803ed74 +.text 0x38aa0 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803eaa0 +_zaf_cc_config 0x8 0x803eab0 +_cc_handlers_v3 0x240 0x803eab8 +_zw_protocol_cmd_handlers 0x70 0x803ecf8 +_zw_protocol_cmd_handlers_lr 0x30 0x803ed68 +.ARM.exidx 0x8 0x803ed98 +.copy.table 0xc 0x803eda0 +.zero.table 0x0 0x803edac .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xac40 0x200015b0 text_application_ram 0x0 0x2000c1f0 .heap 0x800 0x2000c1f0 -.internal_storage 0x30000 0x803ed74 -.zwave_nvm 0x0 0x806ed74 -.nvm 0x8000 0x806ed74 +.internal_storage 0x30000 0x803edac +.zwave_nvm 0x0 0x806edac +.nvm 0x8000 0x806edac .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12fd4 0x0 -.debug_info 0xd5463b 0x0 -.debug_abbrev 0x2a038 0x0 +.debug_frame 0x12fc8 0x0 +.debug_info 0xd55d53 0x0 +.debug_abbrev 0x29fc3 0x0 .debug_aranges 0x6c78 0x0 -.debug_rnglists 0x54fe 0x0 -.debug_line 0x7bd99 0x0 -.debug_str 0x926b9 0x0 -.debug_loclists 0x304a6 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf8ae26 +.debug_rnglists 0x5504 0x0 +.debug_line 0x7be6e 0x0 +.debug_str 0x926a2 0x0 +.debug_loclists 0x30519 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf8c62c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 234276 + 234332 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_EU_size.txt index cb28dd20c5..e9a4939854 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x38b3c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803eb3c -_zaf_cc_config 0x8 0x803eb4c -_cc_handlers_v3 0x240 0x803eb54 -_zw_protocol_cmd_handlers 0x70 0x803ed94 -_zw_protocol_cmd_handlers_lr 0x30 0x803ee04 -.ARM.exidx 0x8 0x803ee34 -.copy.table 0xc 0x803ee3c -.zero.table 0x0 0x803ee48 +.text 0x38b54 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803eb54 +_zaf_cc_config 0x8 0x803eb64 +_cc_handlers_v3 0x240 0x803eb6c +_zw_protocol_cmd_handlers 0x70 0x803edac +_zw_protocol_cmd_handlers_lr 0x30 0x803ee1c +.ARM.exidx 0x8 0x803ee4c +.copy.table 0xc 0x803ee54 +.zero.table 0x0 0x803ee60 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xac44 0x200015b4 text_application_ram 0x0 0x2000c1f8 .heap 0x800 0x2000c1f8 -.internal_storage 0x30000 0x803ee48 -.zwave_nvm 0x0 0x806ee48 -.nvm 0x8000 0x806ee48 +.internal_storage 0x30000 0x803ee60 +.zwave_nvm 0x0 0x806ee60 +.nvm 0x8000 0x806ee60 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x13004 0x0 -.debug_info 0xd548b3 0x0 -.debug_abbrev 0x2a13a 0x0 +.debug_frame 0x12ff8 0x0 +.debug_info 0xd55fcb 0x0 +.debug_abbrev 0x2a0c5 0x0 .debug_aranges 0x6c98 0x0 -.debug_rnglists 0x5511 0x0 -.debug_line 0x7bf72 0x0 -.debug_str 0x9288c 0x0 -.debug_loclists 0x304a6 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf8b68b +.debug_rnglists 0x5517 0x0 +.debug_line 0x7c047 0x0 +.debug_str 0x92875 0x0 +.debug_loclists 0x30519 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf8ce71 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 234492 + 234516 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_US_LR_size.txt index 1dd814c7a7..dc304c2a46 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x38b3c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803eb3c -_zaf_cc_config 0x8 0x803eb4c -_cc_handlers_v3 0x240 0x803eb54 -_zw_protocol_cmd_handlers 0x70 0x803ed94 -_zw_protocol_cmd_handlers_lr 0x30 0x803ee04 -.ARM.exidx 0x8 0x803ee34 -.copy.table 0xc 0x803ee3c -.zero.table 0x0 0x803ee48 +.text 0x38b54 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803eb54 +_zaf_cc_config 0x8 0x803eb64 +_cc_handlers_v3 0x240 0x803eb6c +_zw_protocol_cmd_handlers 0x70 0x803edac +_zw_protocol_cmd_handlers_lr 0x30 0x803ee1c +.ARM.exidx 0x8 0x803ee4c +.copy.table 0xc 0x803ee54 +.zero.table 0x0 0x803ee60 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xac44 0x200015b4 text_application_ram 0x0 0x2000c1f8 .heap 0x800 0x2000c1f8 -.internal_storage 0x30000 0x803ee48 -.zwave_nvm 0x0 0x806ee48 -.nvm 0x8000 0x806ee48 +.internal_storage 0x30000 0x803ee60 +.zwave_nvm 0x0 0x806ee60 +.nvm 0x8000 0x806ee60 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x13004 0x0 -.debug_info 0xd548b3 0x0 -.debug_abbrev 0x2a13a 0x0 +.debug_frame 0x12ff8 0x0 +.debug_info 0xd55fcb 0x0 +.debug_abbrev 0x2a0c5 0x0 .debug_aranges 0x6c98 0x0 -.debug_rnglists 0x5511 0x0 -.debug_line 0x7bf72 0x0 -.debug_str 0x92882 0x0 -.debug_loclists 0x304a6 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf8b681 +.debug_rnglists 0x5517 0x0 +.debug_line 0x7c047 0x0 +.debug_str 0x9286b 0x0 +.debug_loclists 0x30519 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf8ce67 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 234492 + 234516 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_US_size.txt index cb28dd20c5..e9a4939854 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x38b3c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803eb3c -_zaf_cc_config 0x8 0x803eb4c -_cc_handlers_v3 0x240 0x803eb54 -_zw_protocol_cmd_handlers 0x70 0x803ed94 -_zw_protocol_cmd_handlers_lr 0x30 0x803ee04 -.ARM.exidx 0x8 0x803ee34 -.copy.table 0xc 0x803ee3c -.zero.table 0x0 0x803ee48 +.text 0x38b54 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803eb54 +_zaf_cc_config 0x8 0x803eb64 +_cc_handlers_v3 0x240 0x803eb6c +_zw_protocol_cmd_handlers 0x70 0x803edac +_zw_protocol_cmd_handlers_lr 0x30 0x803ee1c +.ARM.exidx 0x8 0x803ee4c +.copy.table 0xc 0x803ee54 +.zero.table 0x0 0x803ee60 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xac44 0x200015b4 text_application_ram 0x0 0x2000c1f8 .heap 0x800 0x2000c1f8 -.internal_storage 0x30000 0x803ee48 -.zwave_nvm 0x0 0x806ee48 -.nvm 0x8000 0x806ee48 +.internal_storage 0x30000 0x803ee60 +.zwave_nvm 0x0 0x806ee60 +.nvm 0x8000 0x806ee60 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x13004 0x0 -.debug_info 0xd548b3 0x0 -.debug_abbrev 0x2a13a 0x0 +.debug_frame 0x12ff8 0x0 +.debug_info 0xd55fcb 0x0 +.debug_abbrev 0x2a0c5 0x0 .debug_aranges 0x6c98 0x0 -.debug_rnglists 0x5511 0x0 -.debug_line 0x7bf72 0x0 -.debug_str 0x9288c 0x0 -.debug_loclists 0x304a6 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf8b68b +.debug_rnglists 0x5517 0x0 +.debug_line 0x7c047 0x0 +.debug_str 0x92875 0x0 +.debug_loclists 0x30519 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf8ce71 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 234492 + 234516 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_EU_size.txt index be0940143e..b475756a52 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x38620 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e620 -_zaf_cc_config 0x8 0x803e630 -_cc_handlers_v3 0x240 0x803e638 -_zw_protocol_cmd_handlers 0x70 0x803e878 -_zw_protocol_cmd_handlers_lr 0x30 0x803e8e8 -.ARM.exidx 0x8 0x803e918 -.copy.table 0xc 0x803e920 -.zero.table 0x0 0x803e92c +.text 0x38638 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e638 +_zaf_cc_config 0x8 0x803e648 +_cc_handlers_v3 0x240 0x803e650 +_zw_protocol_cmd_handlers 0x70 0x803e890 +_zw_protocol_cmd_handlers_lr 0x30 0x803e900 +.ARM.exidx 0x8 0x803e930 +.copy.table 0xc 0x803e938 +.zero.table 0x0 0x803e944 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xaaa8 0x200015b4 text_application_ram 0x0 0x2000c05c .heap 0x800 0x2000c060 -.internal_storage 0x30000 0x803e92c -.zwave_nvm 0x0 0x806e92c -.nvm 0x8000 0x806e92c +.internal_storage 0x30000 0x803e944 +.zwave_nvm 0x0 0x806e944 +.nvm 0x8000 0x806e944 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12974 0x0 -.debug_info 0xd4ec5a 0x0 -.debug_abbrev 0x29753 0x0 +.debug_frame 0x12968 0x0 +.debug_info 0xd50372 0x0 +.debug_abbrev 0x296de 0x0 .debug_aranges 0x6af8 0x0 -.debug_rnglists 0x5267 0x0 -.debug_line 0x78e70 0x0 -.debug_str 0x923fc 0x0 -.debug_loclists 0x2c95d 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf7cdcf +.debug_rnglists 0x526d 0x0 +.debug_line 0x78f3b 0x0 +.debug_str 0x923e5 0x0 +.debug_loclists 0x2c9d0 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf7e5ab The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 233184 + 233208 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_US_LR_size.txt index 89da95704a..b174e5e2b4 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x38620 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e620 -_zaf_cc_config 0x8 0x803e630 -_cc_handlers_v3 0x240 0x803e638 -_zw_protocol_cmd_handlers 0x70 0x803e878 -_zw_protocol_cmd_handlers_lr 0x30 0x803e8e8 -.ARM.exidx 0x8 0x803e918 -.copy.table 0xc 0x803e920 -.zero.table 0x0 0x803e92c +.text 0x38638 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e638 +_zaf_cc_config 0x8 0x803e648 +_cc_handlers_v3 0x240 0x803e650 +_zw_protocol_cmd_handlers 0x70 0x803e890 +_zw_protocol_cmd_handlers_lr 0x30 0x803e900 +.ARM.exidx 0x8 0x803e930 +.copy.table 0xc 0x803e938 +.zero.table 0x0 0x803e944 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xaaa8 0x200015b4 text_application_ram 0x0 0x2000c05c .heap 0x800 0x2000c060 -.internal_storage 0x30000 0x803e92c -.zwave_nvm 0x0 0x806e92c -.nvm 0x8000 0x806e92c +.internal_storage 0x30000 0x803e944 +.zwave_nvm 0x0 0x806e944 +.nvm 0x8000 0x806e944 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12974 0x0 -.debug_info 0xd4ec5a 0x0 -.debug_abbrev 0x29753 0x0 +.debug_frame 0x12968 0x0 +.debug_info 0xd50372 0x0 +.debug_abbrev 0x296de 0x0 .debug_aranges 0x6af8 0x0 -.debug_rnglists 0x5267 0x0 -.debug_line 0x78e70 0x0 -.debug_str 0x923f2 0x0 -.debug_loclists 0x2c95d 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf7cdc5 +.debug_rnglists 0x526d 0x0 +.debug_line 0x78f3b 0x0 +.debug_str 0x923db 0x0 +.debug_loclists 0x2c9d0 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf7e5a1 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 233184 + 233208 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_US_size.txt index be0940143e..b475756a52 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x38620 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e620 -_zaf_cc_config 0x8 0x803e630 -_cc_handlers_v3 0x240 0x803e638 -_zw_protocol_cmd_handlers 0x70 0x803e878 -_zw_protocol_cmd_handlers_lr 0x30 0x803e8e8 -.ARM.exidx 0x8 0x803e918 -.copy.table 0xc 0x803e920 -.zero.table 0x0 0x803e92c +.text 0x38638 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e638 +_zaf_cc_config 0x8 0x803e648 +_cc_handlers_v3 0x240 0x803e650 +_zw_protocol_cmd_handlers 0x70 0x803e890 +_zw_protocol_cmd_handlers_lr 0x30 0x803e900 +.ARM.exidx 0x8 0x803e930 +.copy.table 0xc 0x803e938 +.zero.table 0x0 0x803e944 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xaaa8 0x200015b4 text_application_ram 0x0 0x2000c05c .heap 0x800 0x2000c060 -.internal_storage 0x30000 0x803e92c -.zwave_nvm 0x0 0x806e92c -.nvm 0x8000 0x806e92c +.internal_storage 0x30000 0x803e944 +.zwave_nvm 0x0 0x806e944 +.nvm 0x8000 0x806e944 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12974 0x0 -.debug_info 0xd4ec5a 0x0 -.debug_abbrev 0x29753 0x0 +.debug_frame 0x12968 0x0 +.debug_info 0xd50372 0x0 +.debug_abbrev 0x296de 0x0 .debug_aranges 0x6af8 0x0 -.debug_rnglists 0x5267 0x0 -.debug_line 0x78e70 0x0 -.debug_str 0x923fc 0x0 -.debug_loclists 0x2c95d 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf7cdcf +.debug_rnglists 0x526d 0x0 +.debug_line 0x78f3b 0x0 +.debug_str 0x923e5 0x0 +.debug_loclists 0x2c9d0 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf7e5ab The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 233184 + 233208 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_EU_size.txt index 092943ced1..49dab19992 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x38e4c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803ee4c -_zaf_cc_config 0x8 0x803ee5c -_cc_handlers_v3 0x240 0x803ee64 -_zw_protocol_cmd_handlers 0x70 0x803f0a4 -_zw_protocol_cmd_handlers_lr 0x30 0x803f114 -.ARM.exidx 0x8 0x803f144 -.copy.table 0xc 0x803f14c -.zero.table 0x0 0x803f158 +.text 0x38e64 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803ee64 +_zaf_cc_config 0x8 0x803ee74 +_cc_handlers_v3 0x240 0x803ee7c +_zw_protocol_cmd_handlers 0x70 0x803f0bc +_zw_protocol_cmd_handlers_lr 0x30 0x803f12c +.ARM.exidx 0x8 0x803f15c +.copy.table 0xc 0x803f164 +.zero.table 0x0 0x803f170 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xac48 0x200015b4 text_application_ram 0x0 0x2000c1fc .heap 0x800 0x2000c200 -.internal_storage 0x30000 0x803f158 -.zwave_nvm 0x0 0x806f158 -.nvm 0x8000 0x806f158 +.internal_storage 0x30000 0x803f170 +.zwave_nvm 0x0 0x806f170 +.nvm 0x8000 0x806f170 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x13034 0x0 -.debug_info 0xd55282 0x0 -.debug_abbrev 0x2a216 0x0 +.debug_frame 0x13028 0x0 +.debug_info 0xd5699a 0x0 +.debug_abbrev 0x2a1a1 0x0 .debug_aranges 0x6ce8 0x0 -.debug_rnglists 0x5529 0x0 -.debug_line 0x7be17 0x0 -.debug_str 0x92e5c 0x0 -.debug_loclists 0x304af 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf8c951 +.debug_rnglists 0x552f 0x0 +.debug_line 0x7bee4 0x0 +.debug_str 0x92e45 0x0 +.debug_loclists 0x30522 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf8e12f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 235276 + 235300 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_US_LR_size.txt index 154c3b1ef9..27532a9ddd 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x38e4c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803ee4c -_zaf_cc_config 0x8 0x803ee5c -_cc_handlers_v3 0x240 0x803ee64 -_zw_protocol_cmd_handlers 0x70 0x803f0a4 -_zw_protocol_cmd_handlers_lr 0x30 0x803f114 -.ARM.exidx 0x8 0x803f144 -.copy.table 0xc 0x803f14c -.zero.table 0x0 0x803f158 +.text 0x38e64 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803ee64 +_zaf_cc_config 0x8 0x803ee74 +_cc_handlers_v3 0x240 0x803ee7c +_zw_protocol_cmd_handlers 0x70 0x803f0bc +_zw_protocol_cmd_handlers_lr 0x30 0x803f12c +.ARM.exidx 0x8 0x803f15c +.copy.table 0xc 0x803f164 +.zero.table 0x0 0x803f170 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xac48 0x200015b4 text_application_ram 0x0 0x2000c1fc .heap 0x800 0x2000c200 -.internal_storage 0x30000 0x803f158 -.zwave_nvm 0x0 0x806f158 -.nvm 0x8000 0x806f158 +.internal_storage 0x30000 0x803f170 +.zwave_nvm 0x0 0x806f170 +.nvm 0x8000 0x806f170 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x13034 0x0 -.debug_info 0xd55282 0x0 -.debug_abbrev 0x2a216 0x0 +.debug_frame 0x13028 0x0 +.debug_info 0xd5699a 0x0 +.debug_abbrev 0x2a1a1 0x0 .debug_aranges 0x6ce8 0x0 -.debug_rnglists 0x5529 0x0 -.debug_line 0x7be17 0x0 -.debug_str 0x92e52 0x0 -.debug_loclists 0x304af 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf8c947 +.debug_rnglists 0x552f 0x0 +.debug_line 0x7bee4 0x0 +.debug_str 0x92e3b 0x0 +.debug_loclists 0x30522 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf8e125 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 235276 + 235300 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_US_size.txt index 092943ced1..49dab19992 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x38e4c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803ee4c -_zaf_cc_config 0x8 0x803ee5c -_cc_handlers_v3 0x240 0x803ee64 -_zw_protocol_cmd_handlers 0x70 0x803f0a4 -_zw_protocol_cmd_handlers_lr 0x30 0x803f114 -.ARM.exidx 0x8 0x803f144 -.copy.table 0xc 0x803f14c -.zero.table 0x0 0x803f158 +.text 0x38e64 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803ee64 +_zaf_cc_config 0x8 0x803ee74 +_cc_handlers_v3 0x240 0x803ee7c +_zw_protocol_cmd_handlers 0x70 0x803f0bc +_zw_protocol_cmd_handlers_lr 0x30 0x803f12c +.ARM.exidx 0x8 0x803f15c +.copy.table 0xc 0x803f164 +.zero.table 0x0 0x803f170 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xac48 0x200015b4 text_application_ram 0x0 0x2000c1fc .heap 0x800 0x2000c200 -.internal_storage 0x30000 0x803f158 -.zwave_nvm 0x0 0x806f158 -.nvm 0x8000 0x806f158 +.internal_storage 0x30000 0x803f170 +.zwave_nvm 0x0 0x806f170 +.nvm 0x8000 0x806f170 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x13034 0x0 -.debug_info 0xd55282 0x0 -.debug_abbrev 0x2a216 0x0 +.debug_frame 0x13028 0x0 +.debug_info 0xd5699a 0x0 +.debug_abbrev 0x2a1a1 0x0 .debug_aranges 0x6ce8 0x0 -.debug_rnglists 0x5529 0x0 -.debug_line 0x7be17 0x0 -.debug_str 0x92e5c 0x0 -.debug_loclists 0x304af 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf8c951 +.debug_rnglists 0x552f 0x0 +.debug_line 0x7bee4 0x0 +.debug_str 0x92e45 0x0 +.debug_loclists 0x30522 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf8e12f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 235276 + 235300 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_EU_size.txt index 0a4f19eb84..1ea2a087ae 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x31bac 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x31bac -_zaf_cc_config 0x8 0x31bbc -_cc_handlers_v3 0x240 0x31bc4 -_zw_protocol_cmd_handlers 0x70 0x31e04 -_zw_protocol_cmd_handlers_lr 0x30 0x31e74 -.ARM.exidx 0x8 0x31ea4 -.copy.table 0xc 0x31eac -.zero.table 0x0 0x31eb8 +.text 0x31bc0 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x31bc0 +_zaf_cc_config 0x8 0x31bd0 +_cc_handlers_v3 0x240 0x31bd8 +_zw_protocol_cmd_handlers 0x70 0x31e18 +_zw_protocol_cmd_handlers_lr 0x30 0x31e88 +.ARM.exidx 0x8 0x31eb8 +.copy.table 0xc 0x31ec0 +.zero.table 0x0 0x31ecc .stack 0x1000 0x20000000 .data 0x434 0x20001000 .bss 0xa0d0 0x20001434 text_application_ram 0x0 0x2000b504 .heap 0x800 0x2000b508 -.internal_storage 0x3a000 0x31eb8 -.zwave_nvm 0x3000 0x6beb8 -.nvm 0x9000 0x6eeb8 +.internal_storage 0x3a000 0x31ecc +.zwave_nvm 0x3000 0x6becc +.nvm 0x9000 0x6eecc .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xff18 0x0 -.debug_info 0xd0798d 0x0 -.debug_abbrev 0x24791 0x0 -.debug_aranges 0x5dd8 0x0 -.debug_rnglists 0x3d9c 0x0 -.debug_line 0x652eb 0x0 -.debug_str 0x88f23 0x0 -.debug_loclists 0x1c181 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xf064d1 +.debug_frame 0xfeec 0x0 +.debug_info 0xd07b67 0x0 +.debug_abbrev 0x2474c 0x0 +.debug_aranges 0x5dd0 0x0 +.debug_rnglists 0x3dab 0x0 +.debug_line 0x652fb 0x0 +.debug_str 0x88eeb 0x0 +.debug_loclists 0x1c16d 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xf065f9 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 205548 + 205568 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_US_LR_size.txt index ebf53299c3..ef52a16359 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x31bac 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x31bac -_zaf_cc_config 0x8 0x31bbc -_cc_handlers_v3 0x240 0x31bc4 -_zw_protocol_cmd_handlers 0x70 0x31e04 -_zw_protocol_cmd_handlers_lr 0x30 0x31e74 -.ARM.exidx 0x8 0x31ea4 -.copy.table 0xc 0x31eac -.zero.table 0x0 0x31eb8 +.text 0x31bc0 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x31bc0 +_zaf_cc_config 0x8 0x31bd0 +_cc_handlers_v3 0x240 0x31bd8 +_zw_protocol_cmd_handlers 0x70 0x31e18 +_zw_protocol_cmd_handlers_lr 0x30 0x31e88 +.ARM.exidx 0x8 0x31eb8 +.copy.table 0xc 0x31ec0 +.zero.table 0x0 0x31ecc .stack 0x1000 0x20000000 .data 0x434 0x20001000 .bss 0xa0d0 0x20001434 text_application_ram 0x0 0x2000b504 .heap 0x800 0x2000b508 -.internal_storage 0x3a000 0x31eb8 -.zwave_nvm 0x3000 0x6beb8 -.nvm 0x9000 0x6eeb8 +.internal_storage 0x3a000 0x31ecc +.zwave_nvm 0x3000 0x6becc +.nvm 0x9000 0x6eecc .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xff18 0x0 -.debug_info 0xd0798d 0x0 -.debug_abbrev 0x24791 0x0 -.debug_aranges 0x5dd8 0x0 -.debug_rnglists 0x3d9c 0x0 -.debug_line 0x652eb 0x0 -.debug_str 0x88f19 0x0 -.debug_loclists 0x1c181 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xf064c7 +.debug_frame 0xfeec 0x0 +.debug_info 0xd07b67 0x0 +.debug_abbrev 0x2474c 0x0 +.debug_aranges 0x5dd0 0x0 +.debug_rnglists 0x3dab 0x0 +.debug_line 0x652fb 0x0 +.debug_str 0x88ee1 0x0 +.debug_loclists 0x1c16d 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xf065ef The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 205548 + 205568 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_US_size.txt index 0a4f19eb84..1ea2a087ae 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x31bac 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x31bac -_zaf_cc_config 0x8 0x31bbc -_cc_handlers_v3 0x240 0x31bc4 -_zw_protocol_cmd_handlers 0x70 0x31e04 -_zw_protocol_cmd_handlers_lr 0x30 0x31e74 -.ARM.exidx 0x8 0x31ea4 -.copy.table 0xc 0x31eac -.zero.table 0x0 0x31eb8 +.text 0x31bc0 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x31bc0 +_zaf_cc_config 0x8 0x31bd0 +_cc_handlers_v3 0x240 0x31bd8 +_zw_protocol_cmd_handlers 0x70 0x31e18 +_zw_protocol_cmd_handlers_lr 0x30 0x31e88 +.ARM.exidx 0x8 0x31eb8 +.copy.table 0xc 0x31ec0 +.zero.table 0x0 0x31ecc .stack 0x1000 0x20000000 .data 0x434 0x20001000 .bss 0xa0d0 0x20001434 text_application_ram 0x0 0x2000b504 .heap 0x800 0x2000b508 -.internal_storage 0x3a000 0x31eb8 -.zwave_nvm 0x3000 0x6beb8 -.nvm 0x9000 0x6eeb8 +.internal_storage 0x3a000 0x31ecc +.zwave_nvm 0x3000 0x6becc +.nvm 0x9000 0x6eecc .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xff18 0x0 -.debug_info 0xd0798d 0x0 -.debug_abbrev 0x24791 0x0 -.debug_aranges 0x5dd8 0x0 -.debug_rnglists 0x3d9c 0x0 -.debug_line 0x652eb 0x0 -.debug_str 0x88f23 0x0 -.debug_loclists 0x1c181 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xf064d1 +.debug_frame 0xfeec 0x0 +.debug_info 0xd07b67 0x0 +.debug_abbrev 0x2474c 0x0 +.debug_aranges 0x5dd0 0x0 +.debug_rnglists 0x3dab 0x0 +.debug_line 0x652fb 0x0 +.debug_str 0x88eeb 0x0 +.debug_loclists 0x1c16d 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xf065f9 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 205548 + 205568 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4209A_REGION_US_LR_size.txt index 7fe66174da..5b90f2bf14 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4209A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x31aa4 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x31aa4 -_zaf_cc_config 0x8 0x31ab4 -_cc_handlers_v3 0x240 0x31abc -_zw_protocol_cmd_handlers 0x70 0x31cfc -_zw_protocol_cmd_handlers_lr 0x30 0x31d6c -.ARM.exidx 0x8 0x31d9c -.copy.table 0xc 0x31da4 -.zero.table 0x0 0x31db0 +.text 0x31ab8 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x31ab8 +_zaf_cc_config 0x8 0x31ac8 +_cc_handlers_v3 0x240 0x31ad0 +_zw_protocol_cmd_handlers 0x70 0x31d10 +_zw_protocol_cmd_handlers_lr 0x30 0x31d80 +.ARM.exidx 0x8 0x31db0 +.copy.table 0xc 0x31db8 +.zero.table 0x0 0x31dc4 .stack 0x1000 0x20000000 .data 0x430 0x20001000 .bss 0xa0b0 0x20001430 text_application_ram 0x0 0x2000b4e0 .heap 0x800 0x2000b4e0 -.internal_storage 0x3a000 0x31db0 -.zwave_nvm 0x3000 0x6bdb0 -.nvm 0x9000 0x6edb0 +.internal_storage 0x3a000 0x31dc4 +.zwave_nvm 0x3000 0x6bdc4 +.nvm 0x9000 0x6edc4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0x100b8 0x0 -.debug_info 0xd08e4f 0x0 -.debug_abbrev 0x24c15 0x0 -.debug_aranges 0x5e58 0x0 -.debug_rnglists 0x3e34 0x0 -.debug_line 0x66184 0x0 -.debug_str 0x891a0 0x0 -.debug_loclists 0x1c716 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xf0964e +.debug_frame 0x1008c 0x0 +.debug_info 0xd09029 0x0 +.debug_abbrev 0x24bd0 0x0 +.debug_aranges 0x5e50 0x0 +.debug_rnglists 0x3e43 0x0 +.debug_line 0x6619e 0x0 +.debug_str 0x89168 0x0 +.debug_loclists 0x1c702 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xf09780 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 205280 + 205300 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4210A_REGION_US_LR_size.txt index 44bd1e7649..a57fe29e26 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4210A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x38b5c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803eb5c -_zaf_cc_config 0x8 0x803eb6c -_cc_handlers_v3 0x240 0x803eb74 -_zw_protocol_cmd_handlers 0x70 0x803edb4 -_zw_protocol_cmd_handlers_lr 0x30 0x803ee24 -.ARM.exidx 0x8 0x803ee54 -.copy.table 0xc 0x803ee5c -.zero.table 0x0 0x803ee68 +.text 0x38b74 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803eb74 +_zaf_cc_config 0x8 0x803eb84 +_cc_handlers_v3 0x240 0x803eb8c +_zw_protocol_cmd_handlers 0x70 0x803edcc +_zw_protocol_cmd_handlers_lr 0x30 0x803ee3c +.ARM.exidx 0x8 0x803ee6c +.copy.table 0xc 0x803ee74 +.zero.table 0x0 0x803ee80 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xac44 0x200015b4 text_application_ram 0x0 0x2000c1f8 .heap 0x800 0x2000c1f8 -.internal_storage 0x30000 0x803ee68 -.zwave_nvm 0x0 0x806ee68 -.nvm 0x8000 0x806ee68 +.internal_storage 0x30000 0x803ee80 +.zwave_nvm 0x0 0x806ee80 +.nvm 0x8000 0x806ee80 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1300c 0x0 -.debug_info 0xd5487d 0x0 -.debug_abbrev 0x2a13a 0x0 +.debug_frame 0x13000 0x0 +.debug_info 0xd55f95 0x0 +.debug_abbrev 0x2a0c5 0x0 .debug_aranges 0x6c98 0x0 -.debug_rnglists 0x5511 0x0 -.debug_line 0x7bf49 0x0 -.debug_str 0x92882 0x0 -.debug_loclists 0x304a6 0x0 -.debug_loc 0x2c495 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xf8b617 +.debug_rnglists 0x5517 0x0 +.debug_line 0x7c01e 0x0 +.debug_str 0x9286b 0x0 +.debug_loclists 0x30519 0x0 +.debug_loc 0x2c45d 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xf8cdfd The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 234524 + 234548 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400B_REGION_EU_size.txt index d9d9f4deac..3378c2f6c1 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400B_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x396bc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803f6bc -_zaf_cc_config 0x8 0x803f6cc -_cc_handlers_v3 0x240 0x803f6d4 -_zw_protocol_cmd_handlers 0x70 0x803f914 -_zw_protocol_cmd_handlers_lr 0x30 0x803f984 -.ARM.exidx 0x8 0x803f9b4 -.copy.table 0xc 0x803f9bc -.zero.table 0x0 0x803f9c8 +.text 0x396f4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803f6f4 +_zaf_cc_config 0x8 0x803f704 +_cc_handlers_v3 0x240 0x803f70c +_zw_protocol_cmd_handlers 0x70 0x803f94c +_zw_protocol_cmd_handlers_lr 0x30 0x803f9bc +.ARM.exidx 0x8 0x803f9ec +.copy.table 0xc 0x803f9f4 +.zero.table 0x0 0x803fa00 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xabac 0x200015b0 text_application_ram 0x0 0x2000c15c .heap 0x800 0x2000c160 -.internal_storage 0x30000 0x803f9c8 -.zwave_nvm 0x0 0x806f9c8 -.nvm 0x8000 0x806f9c8 +.internal_storage 0x30000 0x803fa00 +.zwave_nvm 0x0 0x806fa00 +.nvm 0x8000 0x806fa00 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x130d0 0x0 -.debug_info 0xd591ff 0x0 -.debug_abbrev 0x2a471 0x0 +.debug_frame 0x130c4 0x0 +.debug_info 0xd5a91b 0x0 +.debug_abbrev 0x2a3fc 0x0 .debug_aranges 0x6d18 0x0 -.debug_rnglists 0x5566 0x0 -.debug_line 0x7c2f1 0x0 -.debug_str 0x94171 0x0 -.debug_loclists 0x309bc 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf92ffa +.debug_rnglists 0x556c 0x0 +.debug_line 0x7c3c6 0x0 +.debug_str 0x9415a 0x0 +.debug_loclists 0x30a2f 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf94804 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 237432 + 237488 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400B_REGION_US_LR_size.txt index b914558fb6..a78f73d3bc 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x396bc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803f6bc -_zaf_cc_config 0x8 0x803f6cc -_cc_handlers_v3 0x240 0x803f6d4 -_zw_protocol_cmd_handlers 0x70 0x803f914 -_zw_protocol_cmd_handlers_lr 0x30 0x803f984 -.ARM.exidx 0x8 0x803f9b4 -.copy.table 0xc 0x803f9bc -.zero.table 0x0 0x803f9c8 +.text 0x396f4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803f6f4 +_zaf_cc_config 0x8 0x803f704 +_cc_handlers_v3 0x240 0x803f70c +_zw_protocol_cmd_handlers 0x70 0x803f94c +_zw_protocol_cmd_handlers_lr 0x30 0x803f9bc +.ARM.exidx 0x8 0x803f9ec +.copy.table 0xc 0x803f9f4 +.zero.table 0x0 0x803fa00 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xabac 0x200015b0 text_application_ram 0x0 0x2000c15c .heap 0x800 0x2000c160 -.internal_storage 0x30000 0x803f9c8 -.zwave_nvm 0x0 0x806f9c8 -.nvm 0x8000 0x806f9c8 +.internal_storage 0x30000 0x803fa00 +.zwave_nvm 0x0 0x806fa00 +.nvm 0x8000 0x806fa00 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x130d0 0x0 -.debug_info 0xd591ff 0x0 -.debug_abbrev 0x2a471 0x0 +.debug_frame 0x130c4 0x0 +.debug_info 0xd5a91b 0x0 +.debug_abbrev 0x2a3fc 0x0 .debug_aranges 0x6d18 0x0 -.debug_rnglists 0x5566 0x0 -.debug_line 0x7c2f1 0x0 -.debug_str 0x94167 0x0 -.debug_loclists 0x309bc 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf92ff0 +.debug_rnglists 0x556c 0x0 +.debug_line 0x7c3c6 0x0 +.debug_str 0x94150 0x0 +.debug_loclists 0x30a2f 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf947fa The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 237432 + 237488 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400B_REGION_US_size.txt index d9d9f4deac..3378c2f6c1 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400B_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x396bc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803f6bc -_zaf_cc_config 0x8 0x803f6cc -_cc_handlers_v3 0x240 0x803f6d4 -_zw_protocol_cmd_handlers 0x70 0x803f914 -_zw_protocol_cmd_handlers_lr 0x30 0x803f984 -.ARM.exidx 0x8 0x803f9b4 -.copy.table 0xc 0x803f9bc -.zero.table 0x0 0x803f9c8 +.text 0x396f4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803f6f4 +_zaf_cc_config 0x8 0x803f704 +_cc_handlers_v3 0x240 0x803f70c +_zw_protocol_cmd_handlers 0x70 0x803f94c +_zw_protocol_cmd_handlers_lr 0x30 0x803f9bc +.ARM.exidx 0x8 0x803f9ec +.copy.table 0xc 0x803f9f4 +.zero.table 0x0 0x803fa00 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xabac 0x200015b0 text_application_ram 0x0 0x2000c15c .heap 0x800 0x2000c160 -.internal_storage 0x30000 0x803f9c8 -.zwave_nvm 0x0 0x806f9c8 -.nvm 0x8000 0x806f9c8 +.internal_storage 0x30000 0x803fa00 +.zwave_nvm 0x0 0x806fa00 +.nvm 0x8000 0x806fa00 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x130d0 0x0 -.debug_info 0xd591ff 0x0 -.debug_abbrev 0x2a471 0x0 +.debug_frame 0x130c4 0x0 +.debug_info 0xd5a91b 0x0 +.debug_abbrev 0x2a3fc 0x0 .debug_aranges 0x6d18 0x0 -.debug_rnglists 0x5566 0x0 -.debug_line 0x7c2f1 0x0 -.debug_str 0x94171 0x0 -.debug_loclists 0x309bc 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf92ffa +.debug_rnglists 0x556c 0x0 +.debug_line 0x7c3c6 0x0 +.debug_str 0x9415a 0x0 +.debug_loclists 0x30a2f 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf94804 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 237432 + 237488 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400C_REGION_EU_size.txt index 1fe069fe77..4dddc721e4 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x396bc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803f6bc -_zaf_cc_config 0x8 0x803f6cc -_cc_handlers_v3 0x240 0x803f6d4 -_zw_protocol_cmd_handlers 0x70 0x803f914 -_zw_protocol_cmd_handlers_lr 0x30 0x803f984 -.ARM.exidx 0x8 0x803f9b4 -.copy.table 0xc 0x803f9bc -.zero.table 0x0 0x803f9c8 +.text 0x396f4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803f6f4 +_zaf_cc_config 0x8 0x803f704 +_cc_handlers_v3 0x240 0x803f70c +_zw_protocol_cmd_handlers 0x70 0x803f94c +_zw_protocol_cmd_handlers_lr 0x30 0x803f9bc +.ARM.exidx 0x8 0x803f9ec +.copy.table 0xc 0x803f9f4 +.zero.table 0x0 0x803fa00 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xabac 0x200015b0 text_application_ram 0x0 0x2000c15c .heap 0x800 0x2000c160 -.internal_storage 0x30000 0x803f9c8 -.zwave_nvm 0x0 0x806f9c8 -.nvm 0x8000 0x806f9c8 +.internal_storage 0x30000 0x803fa00 +.zwave_nvm 0x0 0x806fa00 +.nvm 0x8000 0x806fa00 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x130e4 0x0 -.debug_info 0xd5918e 0x0 -.debug_abbrev 0x2a47b 0x0 +.debug_frame 0x130d8 0x0 +.debug_info 0xd5a8aa 0x0 +.debug_abbrev 0x2a406 0x0 .debug_aranges 0x6d20 0x0 -.debug_rnglists 0x558f 0x0 -.debug_line 0x7c2e6 0x0 -.debug_str 0x94171 0x0 -.debug_loclists 0x30988 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf92f99 +.debug_rnglists 0x5595 0x0 +.debug_line 0x7c3bb 0x0 +.debug_str 0x9415a 0x0 +.debug_loclists 0x309fb 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf947a3 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 237432 + 237488 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400C_REGION_US_LR_size.txt index 1b49541b7c..812e9dd198 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x396bc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803f6bc -_zaf_cc_config 0x8 0x803f6cc -_cc_handlers_v3 0x240 0x803f6d4 -_zw_protocol_cmd_handlers 0x70 0x803f914 -_zw_protocol_cmd_handlers_lr 0x30 0x803f984 -.ARM.exidx 0x8 0x803f9b4 -.copy.table 0xc 0x803f9bc -.zero.table 0x0 0x803f9c8 +.text 0x396f4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803f6f4 +_zaf_cc_config 0x8 0x803f704 +_cc_handlers_v3 0x240 0x803f70c +_zw_protocol_cmd_handlers 0x70 0x803f94c +_zw_protocol_cmd_handlers_lr 0x30 0x803f9bc +.ARM.exidx 0x8 0x803f9ec +.copy.table 0xc 0x803f9f4 +.zero.table 0x0 0x803fa00 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xabac 0x200015b0 text_application_ram 0x0 0x2000c15c .heap 0x800 0x2000c160 -.internal_storage 0x30000 0x803f9c8 -.zwave_nvm 0x0 0x806f9c8 -.nvm 0x8000 0x806f9c8 +.internal_storage 0x30000 0x803fa00 +.zwave_nvm 0x0 0x806fa00 +.nvm 0x8000 0x806fa00 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x130e4 0x0 -.debug_info 0xd5918e 0x0 -.debug_abbrev 0x2a47b 0x0 +.debug_frame 0x130d8 0x0 +.debug_info 0xd5a8aa 0x0 +.debug_abbrev 0x2a406 0x0 .debug_aranges 0x6d20 0x0 -.debug_rnglists 0x558f 0x0 -.debug_line 0x7c2e6 0x0 -.debug_str 0x94167 0x0 -.debug_loclists 0x30988 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf92f8f +.debug_rnglists 0x5595 0x0 +.debug_line 0x7c3bb 0x0 +.debug_str 0x94150 0x0 +.debug_loclists 0x309fb 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf94799 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 237432 + 237488 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400C_REGION_US_size.txt index 1fe069fe77..4dddc721e4 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4400C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x396bc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803f6bc -_zaf_cc_config 0x8 0x803f6cc -_cc_handlers_v3 0x240 0x803f6d4 -_zw_protocol_cmd_handlers 0x70 0x803f914 -_zw_protocol_cmd_handlers_lr 0x30 0x803f984 -.ARM.exidx 0x8 0x803f9b4 -.copy.table 0xc 0x803f9bc -.zero.table 0x0 0x803f9c8 +.text 0x396f4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803f6f4 +_zaf_cc_config 0x8 0x803f704 +_cc_handlers_v3 0x240 0x803f70c +_zw_protocol_cmd_handlers 0x70 0x803f94c +_zw_protocol_cmd_handlers_lr 0x30 0x803f9bc +.ARM.exidx 0x8 0x803f9ec +.copy.table 0xc 0x803f9f4 +.zero.table 0x0 0x803fa00 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xabac 0x200015b0 text_application_ram 0x0 0x2000c15c .heap 0x800 0x2000c160 -.internal_storage 0x30000 0x803f9c8 -.zwave_nvm 0x0 0x806f9c8 -.nvm 0x8000 0x806f9c8 +.internal_storage 0x30000 0x803fa00 +.zwave_nvm 0x0 0x806fa00 +.nvm 0x8000 0x806fa00 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x130e4 0x0 -.debug_info 0xd5918e 0x0 -.debug_abbrev 0x2a47b 0x0 +.debug_frame 0x130d8 0x0 +.debug_info 0xd5a8aa 0x0 +.debug_abbrev 0x2a406 0x0 .debug_aranges 0x6d20 0x0 -.debug_rnglists 0x558f 0x0 -.debug_line 0x7c2e6 0x0 -.debug_str 0x94171 0x0 -.debug_loclists 0x30988 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf92f99 +.debug_rnglists 0x5595 0x0 +.debug_line 0x7c3bb 0x0 +.debug_str 0x9415a 0x0 +.debug_loclists 0x309fb 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf947a3 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 237432 + 237488 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4401B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4401B_REGION_US_LR_size.txt index 5b437ee6ff..4c54ca8db7 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4401B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4401B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x396fc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803f6fc -_zaf_cc_config 0x8 0x803f70c -_cc_handlers_v3 0x240 0x803f714 -_zw_protocol_cmd_handlers 0x70 0x803f954 -_zw_protocol_cmd_handlers_lr 0x30 0x803f9c4 -.ARM.exidx 0x8 0x803f9f4 -.copy.table 0xc 0x803f9fc -.zero.table 0x0 0x803fa08 +.text 0x39714 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803f714 +_zaf_cc_config 0x8 0x803f724 +_cc_handlers_v3 0x240 0x803f72c +_zw_protocol_cmd_handlers 0x70 0x803f96c +_zw_protocol_cmd_handlers_lr 0x30 0x803f9dc +.ARM.exidx 0x8 0x803fa0c +.copy.table 0xc 0x803fa14 +.zero.table 0x0 0x803fa20 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xabac 0x200015b0 text_application_ram 0x0 0x2000c15c .heap 0x800 0x2000c160 -.internal_storage 0x30000 0x803fa08 -.zwave_nvm 0x0 0x806fa08 -.nvm 0x8000 0x806fa08 +.internal_storage 0x30000 0x803fa20 +.zwave_nvm 0x0 0x806fa20 +.nvm 0x8000 0x806fa20 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x130d8 0x0 -.debug_info 0xd591c9 0x0 -.debug_abbrev 0x2a471 0x0 +.debug_frame 0x130cc 0x0 +.debug_info 0xd5a8e5 0x0 +.debug_abbrev 0x2a3fc 0x0 .debug_aranges 0x6d18 0x0 -.debug_rnglists 0x5566 0x0 -.debug_line 0x7c2c8 0x0 -.debug_str 0x94167 0x0 -.debug_loclists 0x309bc 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xf92fa6 +.debug_rnglists 0x556c 0x0 +.debug_line 0x7c39d 0x0 +.debug_str 0x94150 0x0 +.debug_loclists 0x30a2f 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xf94790 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 237496 + 237520 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4401C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4401C_REGION_EU_size.txt index bf76fc602a..76a0c84f68 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4401C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4401C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x396fc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803f6fc -_zaf_cc_config 0x8 0x803f70c -_cc_handlers_v3 0x240 0x803f714 -_zw_protocol_cmd_handlers 0x70 0x803f954 -_zw_protocol_cmd_handlers_lr 0x30 0x803f9c4 -.ARM.exidx 0x8 0x803f9f4 -.copy.table 0xc 0x803f9fc -.zero.table 0x0 0x803fa08 +.text 0x39714 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803f714 +_zaf_cc_config 0x8 0x803f724 +_cc_handlers_v3 0x240 0x803f72c +_zw_protocol_cmd_handlers 0x70 0x803f96c +_zw_protocol_cmd_handlers_lr 0x30 0x803f9dc +.ARM.exidx 0x8 0x803fa0c +.copy.table 0xc 0x803fa14 +.zero.table 0x0 0x803fa20 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xabac 0x200015b0 text_application_ram 0x0 0x2000c15c .heap 0x800 0x2000c160 -.internal_storage 0x30000 0x803fa08 -.zwave_nvm 0x0 0x806fa08 -.nvm 0x8000 0x806fa08 +.internal_storage 0x30000 0x803fa20 +.zwave_nvm 0x0 0x806fa20 +.nvm 0x8000 0x806fa20 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x130ec 0x0 -.debug_info 0xd59158 0x0 -.debug_abbrev 0x2a47b 0x0 +.debug_frame 0x130e0 0x0 +.debug_info 0xd5a874 0x0 +.debug_abbrev 0x2a406 0x0 .debug_aranges 0x6d20 0x0 -.debug_rnglists 0x558f 0x0 -.debug_line 0x7c2bd 0x0 -.debug_str 0x94171 0x0 -.debug_loclists 0x30988 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xf92f4f +.debug_rnglists 0x5595 0x0 +.debug_line 0x7c392 0x0 +.debug_str 0x9415a 0x0 +.debug_loclists 0x309fb 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xf94739 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 237496 + 237520 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4401C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4401C_REGION_US_LR_size.txt index 49f2998823..c708791bb1 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4401C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4401C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x396fc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803f6fc -_zaf_cc_config 0x8 0x803f70c -_cc_handlers_v3 0x240 0x803f714 -_zw_protocol_cmd_handlers 0x70 0x803f954 -_zw_protocol_cmd_handlers_lr 0x30 0x803f9c4 -.ARM.exidx 0x8 0x803f9f4 -.copy.table 0xc 0x803f9fc -.zero.table 0x0 0x803fa08 +.text 0x39714 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803f714 +_zaf_cc_config 0x8 0x803f724 +_cc_handlers_v3 0x240 0x803f72c +_zw_protocol_cmd_handlers 0x70 0x803f96c +_zw_protocol_cmd_handlers_lr 0x30 0x803f9dc +.ARM.exidx 0x8 0x803fa0c +.copy.table 0xc 0x803fa14 +.zero.table 0x0 0x803fa20 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xabac 0x200015b0 text_application_ram 0x0 0x2000c15c .heap 0x800 0x2000c160 -.internal_storage 0x30000 0x803fa08 -.zwave_nvm 0x0 0x806fa08 -.nvm 0x8000 0x806fa08 +.internal_storage 0x30000 0x803fa20 +.zwave_nvm 0x0 0x806fa20 +.nvm 0x8000 0x806fa20 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x130ec 0x0 -.debug_info 0xd59158 0x0 -.debug_abbrev 0x2a47b 0x0 +.debug_frame 0x130e0 0x0 +.debug_info 0xd5a874 0x0 +.debug_abbrev 0x2a406 0x0 .debug_aranges 0x6d20 0x0 -.debug_rnglists 0x558f 0x0 -.debug_line 0x7c2bd 0x0 -.debug_str 0x94167 0x0 -.debug_loclists 0x30988 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xf92f45 +.debug_rnglists 0x5595 0x0 +.debug_line 0x7c392 0x0 +.debug_str 0x94150 0x0 +.debug_loclists 0x309fb 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xf9472f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 237496 + 237520 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4401C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4401C_REGION_US_size.txt index bf76fc602a..76a0c84f68 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4401C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4401C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x396fc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803f6fc -_zaf_cc_config 0x8 0x803f70c -_cc_handlers_v3 0x240 0x803f714 -_zw_protocol_cmd_handlers 0x70 0x803f954 -_zw_protocol_cmd_handlers_lr 0x30 0x803f9c4 -.ARM.exidx 0x8 0x803f9f4 -.copy.table 0xc 0x803f9fc -.zero.table 0x0 0x803fa08 +.text 0x39714 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803f714 +_zaf_cc_config 0x8 0x803f724 +_cc_handlers_v3 0x240 0x803f72c +_zw_protocol_cmd_handlers 0x70 0x803f96c +_zw_protocol_cmd_handlers_lr 0x30 0x803f9dc +.ARM.exidx 0x8 0x803fa0c +.copy.table 0xc 0x803fa14 +.zero.table 0x0 0x803fa20 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xabac 0x200015b0 text_application_ram 0x0 0x2000c15c .heap 0x800 0x2000c160 -.internal_storage 0x30000 0x803fa08 -.zwave_nvm 0x0 0x806fa08 -.nvm 0x8000 0x806fa08 +.internal_storage 0x30000 0x803fa20 +.zwave_nvm 0x0 0x806fa20 +.nvm 0x8000 0x806fa20 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x130ec 0x0 -.debug_info 0xd59158 0x0 -.debug_abbrev 0x2a47b 0x0 +.debug_frame 0x130e0 0x0 +.debug_info 0xd5a874 0x0 +.debug_abbrev 0x2a406 0x0 .debug_aranges 0x6d20 0x0 -.debug_rnglists 0x558f 0x0 -.debug_line 0x7c2bd 0x0 -.debug_str 0x94171 0x0 -.debug_loclists 0x30988 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xf92f4f +.debug_rnglists 0x5595 0x0 +.debug_line 0x7c392 0x0 +.debug_str 0x9415a 0x0 +.debug_loclists 0x309fb 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xf94739 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 237496 + 237520 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2603A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2603A_REGION_EU_size.txt index d46ec692df..4d300fad57 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2603A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2603A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x38500 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e500 -_zaf_cc_config 0x28 0x803e510 -_cc_handlers_v3 0x2ac 0x803e538 -_zw_protocol_cmd_handlers 0x70 0x803e7e4 -_zw_protocol_cmd_handlers_lr 0x30 0x803e854 -.ARM.exidx 0x8 0x803e884 -.copy.table 0xc 0x803e88c -.zero.table 0x0 0x803e898 +.text 0x38538 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e538 +_zaf_cc_config 0x28 0x803e548 +_cc_handlers_v3 0x2ac 0x803e570 +_zw_protocol_cmd_handlers 0x70 0x803e81c +_zw_protocol_cmd_handlers_lr 0x30 0x803e88c +.ARM.exidx 0x8 0x803e8bc +.copy.table 0xc 0x803e8c4 +.zero.table 0x0 0x803e8d0 .stack 0x1000 0x20000000 .data 0x738 0x20001000 .bss 0xac4c 0x20001738 text_application_ram 0x0 0x2000c384 .heap 0x800 0x2000c388 -.internal_storage 0x30000 0x803e898 -.zwave_nvm 0x0 0x806e898 -.nvm 0x8000 0x806e898 +.internal_storage 0x30000 0x803e8d0 +.zwave_nvm 0x0 0x806e8d0 +.nvm 0x8000 0x806e8d0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12c78 0x0 -.debug_info 0xe1420a 0x0 -.debug_abbrev 0x29f06 0x0 -.debug_loclists 0x2e307 0x0 +.debug_frame 0x12c6c 0x0 +.debug_info 0xe15922 0x0 +.debug_abbrev 0x29e91 0x0 +.debug_loclists 0x2e37a 0x0 .debug_aranges 0x6bd8 0x0 -.debug_rnglists 0x5304 0x0 -.debug_line 0x7ade9 0x0 -.debug_str 0x90da9 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0x1045517 +.debug_rnglists 0x530a 0x0 +.debug_line 0x7aeb6 0x0 +.debug_str 0x90d92 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0x1046d15 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 233424 + 233480 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2603A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2603A_REGION_US_LR_size.txt index a3a40f1626..090fa5d308 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2603A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2603A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x38500 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e500 -_zaf_cc_config 0x28 0x803e510 -_cc_handlers_v3 0x2ac 0x803e538 -_zw_protocol_cmd_handlers 0x70 0x803e7e4 -_zw_protocol_cmd_handlers_lr 0x30 0x803e854 -.ARM.exidx 0x8 0x803e884 -.copy.table 0xc 0x803e88c -.zero.table 0x0 0x803e898 +.text 0x38538 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e538 +_zaf_cc_config 0x28 0x803e548 +_cc_handlers_v3 0x2ac 0x803e570 +_zw_protocol_cmd_handlers 0x70 0x803e81c +_zw_protocol_cmd_handlers_lr 0x30 0x803e88c +.ARM.exidx 0x8 0x803e8bc +.copy.table 0xc 0x803e8c4 +.zero.table 0x0 0x803e8d0 .stack 0x1000 0x20000000 .data 0x738 0x20001000 .bss 0xac4c 0x20001738 text_application_ram 0x0 0x2000c384 .heap 0x800 0x2000c388 -.internal_storage 0x30000 0x803e898 -.zwave_nvm 0x0 0x806e898 -.nvm 0x8000 0x806e898 +.internal_storage 0x30000 0x803e8d0 +.zwave_nvm 0x0 0x806e8d0 +.nvm 0x8000 0x806e8d0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12c78 0x0 -.debug_info 0xe1420a 0x0 -.debug_abbrev 0x29f06 0x0 -.debug_loclists 0x2e307 0x0 +.debug_frame 0x12c6c 0x0 +.debug_info 0xe15922 0x0 +.debug_abbrev 0x29e91 0x0 +.debug_loclists 0x2e37a 0x0 .debug_aranges 0x6bd8 0x0 -.debug_rnglists 0x5304 0x0 -.debug_line 0x7ade9 0x0 -.debug_str 0x90d9f 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0x104550d +.debug_rnglists 0x530a 0x0 +.debug_line 0x7aeb6 0x0 +.debug_str 0x90d88 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0x1046d0b The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 233424 + 233480 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2603A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2603A_REGION_US_size.txt index d46ec692df..4d300fad57 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2603A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2603A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x38500 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e500 -_zaf_cc_config 0x28 0x803e510 -_cc_handlers_v3 0x2ac 0x803e538 -_zw_protocol_cmd_handlers 0x70 0x803e7e4 -_zw_protocol_cmd_handlers_lr 0x30 0x803e854 -.ARM.exidx 0x8 0x803e884 -.copy.table 0xc 0x803e88c -.zero.table 0x0 0x803e898 +.text 0x38538 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e538 +_zaf_cc_config 0x28 0x803e548 +_cc_handlers_v3 0x2ac 0x803e570 +_zw_protocol_cmd_handlers 0x70 0x803e81c +_zw_protocol_cmd_handlers_lr 0x30 0x803e88c +.ARM.exidx 0x8 0x803e8bc +.copy.table 0xc 0x803e8c4 +.zero.table 0x0 0x803e8d0 .stack 0x1000 0x20000000 .data 0x738 0x20001000 .bss 0xac4c 0x20001738 text_application_ram 0x0 0x2000c384 .heap 0x800 0x2000c388 -.internal_storage 0x30000 0x803e898 -.zwave_nvm 0x0 0x806e898 -.nvm 0x8000 0x806e898 +.internal_storage 0x30000 0x803e8d0 +.zwave_nvm 0x0 0x806e8d0 +.nvm 0x8000 0x806e8d0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12c78 0x0 -.debug_info 0xe1420a 0x0 -.debug_abbrev 0x29f06 0x0 -.debug_loclists 0x2e307 0x0 +.debug_frame 0x12c6c 0x0 +.debug_info 0xe15922 0x0 +.debug_abbrev 0x29e91 0x0 +.debug_loclists 0x2e37a 0x0 .debug_aranges 0x6bd8 0x0 -.debug_rnglists 0x5304 0x0 -.debug_line 0x7ade9 0x0 -.debug_str 0x90da9 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0x1045517 +.debug_rnglists 0x530a 0x0 +.debug_line 0x7aeb6 0x0 +.debug_str 0x90d92 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0x1046d15 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 233424 + 233480 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2705A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2705A_REGION_EU_size.txt index f98c76bb3f..b014c03573 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2705A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2705A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x385d0 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e5d0 -_zaf_cc_config 0x28 0x803e5e0 -_cc_handlers_v3 0x2ac 0x803e608 -_zw_protocol_cmd_handlers 0x70 0x803e8b4 -_zw_protocol_cmd_handlers_lr 0x30 0x803e924 -.ARM.exidx 0x8 0x803e954 -.copy.table 0xc 0x803e95c -.zero.table 0x0 0x803e968 +.text 0x385e8 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e5e8 +_zaf_cc_config 0x28 0x803e5f8 +_cc_handlers_v3 0x2ac 0x803e620 +_zw_protocol_cmd_handlers 0x70 0x803e8cc +_zw_protocol_cmd_handlers_lr 0x30 0x803e93c +.ARM.exidx 0x8 0x803e96c +.copy.table 0xc 0x803e974 +.zero.table 0x0 0x803e980 .stack 0x1000 0x20000000 .data 0x6c0 0x20001000 .bss 0xabb4 0x200016c0 text_application_ram 0x0 0x2000c274 .heap 0x800 0x2000c278 -.internal_storage 0x30000 0x803e968 -.zwave_nvm 0x0 0x806e968 -.nvm 0x8000 0x806e968 +.internal_storage 0x30000 0x803e980 +.zwave_nvm 0x0 0x806e980 +.nvm 0x8000 0x806e980 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1287c 0x0 -.debug_info 0xe0c8fc 0x0 -.debug_abbrev 0x29100 0x0 -.debug_loclists 0x2dace 0x0 +.debug_frame 0x12870 0x0 +.debug_info 0xe0e018 0x0 +.debug_abbrev 0x2908b 0x0 +.debug_loclists 0x2db41 0x0 .debug_aranges 0x69f8 0x0 -.debug_rnglists 0x514e 0x0 -.debug_line 0x790a8 0x0 -.debug_str 0x90eeb 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0x103a0f5 +.debug_rnglists 0x5154 0x0 +.debug_line 0x7917d 0x0 +.debug_str 0x90ed4 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0x103b8df The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 233512 + 233536 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2705A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2705A_REGION_US_LR_size.txt index 009fcbffa6..5e2828b1f2 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2705A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2705A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x385d0 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e5d0 -_zaf_cc_config 0x28 0x803e5e0 -_cc_handlers_v3 0x2ac 0x803e608 -_zw_protocol_cmd_handlers 0x70 0x803e8b4 -_zw_protocol_cmd_handlers_lr 0x30 0x803e924 -.ARM.exidx 0x8 0x803e954 -.copy.table 0xc 0x803e95c -.zero.table 0x0 0x803e968 +.text 0x385e8 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e5e8 +_zaf_cc_config 0x28 0x803e5f8 +_cc_handlers_v3 0x2ac 0x803e620 +_zw_protocol_cmd_handlers 0x70 0x803e8cc +_zw_protocol_cmd_handlers_lr 0x30 0x803e93c +.ARM.exidx 0x8 0x803e96c +.copy.table 0xc 0x803e974 +.zero.table 0x0 0x803e980 .stack 0x1000 0x20000000 .data 0x6c0 0x20001000 .bss 0xabb4 0x200016c0 text_application_ram 0x0 0x2000c274 .heap 0x800 0x2000c278 -.internal_storage 0x30000 0x803e968 -.zwave_nvm 0x0 0x806e968 -.nvm 0x8000 0x806e968 +.internal_storage 0x30000 0x803e980 +.zwave_nvm 0x0 0x806e980 +.nvm 0x8000 0x806e980 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1287c 0x0 -.debug_info 0xe0c8fc 0x0 -.debug_abbrev 0x29100 0x0 -.debug_loclists 0x2dace 0x0 +.debug_frame 0x12870 0x0 +.debug_info 0xe0e018 0x0 +.debug_abbrev 0x2908b 0x0 +.debug_loclists 0x2db41 0x0 .debug_aranges 0x69f8 0x0 -.debug_rnglists 0x514e 0x0 -.debug_line 0x790a8 0x0 -.debug_str 0x90ee1 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0x103a0eb +.debug_rnglists 0x5154 0x0 +.debug_line 0x7917d 0x0 +.debug_str 0x90eca 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0x103b8d5 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 233512 + 233536 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2705A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2705A_REGION_US_size.txt index f98c76bb3f..b014c03573 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2705A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD2705A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x385d0 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e5d0 -_zaf_cc_config 0x28 0x803e5e0 -_cc_handlers_v3 0x2ac 0x803e608 -_zw_protocol_cmd_handlers 0x70 0x803e8b4 -_zw_protocol_cmd_handlers_lr 0x30 0x803e924 -.ARM.exidx 0x8 0x803e954 -.copy.table 0xc 0x803e95c -.zero.table 0x0 0x803e968 +.text 0x385e8 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e5e8 +_zaf_cc_config 0x28 0x803e5f8 +_cc_handlers_v3 0x2ac 0x803e620 +_zw_protocol_cmd_handlers 0x70 0x803e8cc +_zw_protocol_cmd_handlers_lr 0x30 0x803e93c +.ARM.exidx 0x8 0x803e96c +.copy.table 0xc 0x803e974 +.zero.table 0x0 0x803e980 .stack 0x1000 0x20000000 .data 0x6c0 0x20001000 .bss 0xabb4 0x200016c0 text_application_ram 0x0 0x2000c274 .heap 0x800 0x2000c278 -.internal_storage 0x30000 0x803e968 -.zwave_nvm 0x0 0x806e968 -.nvm 0x8000 0x806e968 +.internal_storage 0x30000 0x803e980 +.zwave_nvm 0x0 0x806e980 +.nvm 0x8000 0x806e980 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1287c 0x0 -.debug_info 0xe0c8fc 0x0 -.debug_abbrev 0x29100 0x0 -.debug_loclists 0x2dace 0x0 +.debug_frame 0x12870 0x0 +.debug_info 0xe0e018 0x0 +.debug_abbrev 0x2908b 0x0 +.debug_loclists 0x2db41 0x0 .debug_aranges 0x69f8 0x0 -.debug_rnglists 0x514e 0x0 -.debug_line 0x790a8 0x0 -.debug_str 0x90eeb 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0x103a0f5 +.debug_rnglists 0x5154 0x0 +.debug_line 0x7917d 0x0 +.debug_str 0x90ed4 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0x103b8df The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 233512 + 233536 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_EU_size.txt index 6bc12321a6..e089bd04e9 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x312a4 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x312a4 -_zaf_cc_config 0x28 0x312b4 -_cc_handlers_v3 0x2ac 0x312dc -_zw_protocol_cmd_handlers 0x70 0x31588 -_zw_protocol_cmd_handlers_lr 0x30 0x315f8 -.ARM.exidx 0x8 0x31628 -.copy.table 0xc 0x31630 -.zero.table 0x0 0x3163c +.text 0x312b8 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x312b8 +_zaf_cc_config 0x28 0x312c8 +_cc_handlers_v3 0x2ac 0x312f0 +_zw_protocol_cmd_handlers 0x70 0x3159c +_zw_protocol_cmd_handlers_lr 0x30 0x3160c +.ARM.exidx 0x8 0x3163c +.copy.table 0xc 0x31644 +.zero.table 0x0 0x31650 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xa0d4 0x200015b0 text_application_ram 0x0 0x2000b684 .heap 0x800 0x2000b688 -.internal_storage 0x3a000 0x3163c -.zwave_nvm 0x3000 0x6b63c -.nvm 0x9000 0x6e63c +.internal_storage 0x3a000 0x31650 +.zwave_nvm 0x3000 0x6b650 +.nvm 0x9000 0x6e650 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xfc84 0x0 -.debug_info 0xdc6278 0x0 -.debug_abbrev 0x247df 0x0 -.debug_loclists 0x1a3ef 0x0 -.debug_aranges 0x5d20 0x0 -.debug_rnglists 0x3cba 0x0 -.debug_line 0x64b28 0x0 -.debug_str 0x862b2 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xfbf11a +.debug_frame 0xfc58 0x0 +.debug_info 0xdc6452 0x0 +.debug_abbrev 0x2479a 0x0 +.debug_loclists 0x1a3db 0x0 +.debug_aranges 0x5d18 0x0 +.debug_rnglists 0x3cc9 0x0 +.debug_line 0x64b38 0x0 +.debug_str 0x8627a 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xfbf242 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 203756 + 203776 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_US_LR_size.txt index 84eb906de4..56ffadf4cc 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x312a4 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x312a4 -_zaf_cc_config 0x28 0x312b4 -_cc_handlers_v3 0x2ac 0x312dc -_zw_protocol_cmd_handlers 0x70 0x31588 -_zw_protocol_cmd_handlers_lr 0x30 0x315f8 -.ARM.exidx 0x8 0x31628 -.copy.table 0xc 0x31630 -.zero.table 0x0 0x3163c +.text 0x312b8 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x312b8 +_zaf_cc_config 0x28 0x312c8 +_cc_handlers_v3 0x2ac 0x312f0 +_zw_protocol_cmd_handlers 0x70 0x3159c +_zw_protocol_cmd_handlers_lr 0x30 0x3160c +.ARM.exidx 0x8 0x3163c +.copy.table 0xc 0x31644 +.zero.table 0x0 0x31650 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xa0d4 0x200015b0 text_application_ram 0x0 0x2000b684 .heap 0x800 0x2000b688 -.internal_storage 0x3a000 0x3163c -.zwave_nvm 0x3000 0x6b63c -.nvm 0x9000 0x6e63c +.internal_storage 0x3a000 0x31650 +.zwave_nvm 0x3000 0x6b650 +.nvm 0x9000 0x6e650 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xfc84 0x0 -.debug_info 0xdc6278 0x0 -.debug_abbrev 0x247df 0x0 -.debug_loclists 0x1a3ef 0x0 -.debug_aranges 0x5d20 0x0 -.debug_rnglists 0x3cba 0x0 -.debug_line 0x64b28 0x0 -.debug_str 0x862a8 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xfbf110 +.debug_frame 0xfc58 0x0 +.debug_info 0xdc6452 0x0 +.debug_abbrev 0x2479a 0x0 +.debug_loclists 0x1a3db 0x0 +.debug_aranges 0x5d18 0x0 +.debug_rnglists 0x3cc9 0x0 +.debug_line 0x64b38 0x0 +.debug_str 0x86270 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xfbf238 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 203756 + 203776 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_US_size.txt index 6bc12321a6..e089bd04e9 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x312a4 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x312a4 -_zaf_cc_config 0x28 0x312b4 -_cc_handlers_v3 0x2ac 0x312dc -_zw_protocol_cmd_handlers 0x70 0x31588 -_zw_protocol_cmd_handlers_lr 0x30 0x315f8 -.ARM.exidx 0x8 0x31628 -.copy.table 0xc 0x31630 -.zero.table 0x0 0x3163c +.text 0x312b8 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x312b8 +_zaf_cc_config 0x28 0x312c8 +_cc_handlers_v3 0x2ac 0x312f0 +_zw_protocol_cmd_handlers 0x70 0x3159c +_zw_protocol_cmd_handlers_lr 0x30 0x3160c +.ARM.exidx 0x8 0x3163c +.copy.table 0xc 0x31644 +.zero.table 0x0 0x31650 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xa0d4 0x200015b0 text_application_ram 0x0 0x2000b684 .heap 0x800 0x2000b688 -.internal_storage 0x3a000 0x3163c -.zwave_nvm 0x3000 0x6b63c -.nvm 0x9000 0x6e63c +.internal_storage 0x3a000 0x31650 +.zwave_nvm 0x3000 0x6b650 +.nvm 0x9000 0x6e650 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xfc84 0x0 -.debug_info 0xdc6278 0x0 -.debug_abbrev 0x247df 0x0 -.debug_loclists 0x1a3ef 0x0 -.debug_aranges 0x5d20 0x0 -.debug_rnglists 0x3cba 0x0 -.debug_line 0x64b28 0x0 -.debug_str 0x862b2 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xfbf11a +.debug_frame 0xfc58 0x0 +.debug_info 0xdc6452 0x0 +.debug_abbrev 0x2479a 0x0 +.debug_loclists 0x1a3db 0x0 +.debug_aranges 0x5d18 0x0 +.debug_rnglists 0x3cc9 0x0 +.debug_line 0x64b38 0x0 +.debug_str 0x8627a 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xfbf242 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 203756 + 203776 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_EU_size.txt index 8f12af66f5..86ccdce724 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x37c70 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803dc70 -_zaf_cc_config 0x28 0x803dc80 -_cc_handlers_v3 0x2ac 0x803dca8 -_zw_protocol_cmd_handlers 0x70 0x803df54 -_zw_protocol_cmd_handlers_lr 0x30 0x803dfc4 -.ARM.exidx 0x8 0x803dff4 -.copy.table 0xc 0x803dffc -.zero.table 0x0 0x803e008 +.text 0x37c88 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803dc88 +_zaf_cc_config 0x28 0x803dc98 +_cc_handlers_v3 0x2ac 0x803dcc0 +_zw_protocol_cmd_handlers 0x70 0x803df6c +_zw_protocol_cmd_handlers_lr 0x30 0x803dfdc +.ARM.exidx 0x8 0x803e00c +.copy.table 0xc 0x803e014 +.zero.table 0x0 0x803e020 .stack 0x1000 0x20000000 .data 0x734 0x20001000 .bss 0xaab0 0x20001734 text_application_ram 0x0 0x2000c1e4 .heap 0x800 0x2000c1e8 -.internal_storage 0x30000 0x803e008 -.zwave_nvm 0x0 0x806e008 -.nvm 0x8000 0x806e008 +.internal_storage 0x30000 0x803e020 +.zwave_nvm 0x0 0x806e020 +.nvm 0x8000 0x806e020 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12694 0x0 -.debug_info 0xe0fb21 0x0 -.debug_abbrev 0x297f9 0x0 -.debug_loclists 0x2aa32 0x0 +.debug_frame 0x12688 0x0 +.debug_info 0xe11239 0x0 +.debug_abbrev 0x29784 0x0 +.debug_loclists 0x2aaa5 0x0 .debug_aranges 0x6a48 0x0 -.debug_rnglists 0x509e 0x0 -.debug_line 0x785b1 0x0 -.debug_str 0x90593 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0x10389f4 +.debug_rnglists 0x50a4 0x0 +.debug_line 0x7867c 0x0 +.debug_str 0x9057c 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0x103a1d0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231228 + 231252 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_US_LR_size.txt index 7d9c334184..1a7ac25917 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x37c70 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803dc70 -_zaf_cc_config 0x28 0x803dc80 -_cc_handlers_v3 0x2ac 0x803dca8 -_zw_protocol_cmd_handlers 0x70 0x803df54 -_zw_protocol_cmd_handlers_lr 0x30 0x803dfc4 -.ARM.exidx 0x8 0x803dff4 -.copy.table 0xc 0x803dffc -.zero.table 0x0 0x803e008 +.text 0x37c88 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803dc88 +_zaf_cc_config 0x28 0x803dc98 +_cc_handlers_v3 0x2ac 0x803dcc0 +_zw_protocol_cmd_handlers 0x70 0x803df6c +_zw_protocol_cmd_handlers_lr 0x30 0x803dfdc +.ARM.exidx 0x8 0x803e00c +.copy.table 0xc 0x803e014 +.zero.table 0x0 0x803e020 .stack 0x1000 0x20000000 .data 0x734 0x20001000 .bss 0xaab0 0x20001734 text_application_ram 0x0 0x2000c1e4 .heap 0x800 0x2000c1e8 -.internal_storage 0x30000 0x803e008 -.zwave_nvm 0x0 0x806e008 -.nvm 0x8000 0x806e008 +.internal_storage 0x30000 0x803e020 +.zwave_nvm 0x0 0x806e020 +.nvm 0x8000 0x806e020 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12694 0x0 -.debug_info 0xe0fb21 0x0 -.debug_abbrev 0x297f9 0x0 -.debug_loclists 0x2aa32 0x0 +.debug_frame 0x12688 0x0 +.debug_info 0xe11239 0x0 +.debug_abbrev 0x29784 0x0 +.debug_loclists 0x2aaa5 0x0 .debug_aranges 0x6a48 0x0 -.debug_rnglists 0x509e 0x0 -.debug_line 0x785b1 0x0 -.debug_str 0x90589 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0x10389ea +.debug_rnglists 0x50a4 0x0 +.debug_line 0x7867c 0x0 +.debug_str 0x90572 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0x103a1c6 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231228 + 231252 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_US_size.txt index 8f12af66f5..86ccdce724 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x37c70 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803dc70 -_zaf_cc_config 0x28 0x803dc80 -_cc_handlers_v3 0x2ac 0x803dca8 -_zw_protocol_cmd_handlers 0x70 0x803df54 -_zw_protocol_cmd_handlers_lr 0x30 0x803dfc4 -.ARM.exidx 0x8 0x803dff4 -.copy.table 0xc 0x803dffc -.zero.table 0x0 0x803e008 +.text 0x37c88 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803dc88 +_zaf_cc_config 0x28 0x803dc98 +_cc_handlers_v3 0x2ac 0x803dcc0 +_zw_protocol_cmd_handlers 0x70 0x803df6c +_zw_protocol_cmd_handlers_lr 0x30 0x803dfdc +.ARM.exidx 0x8 0x803e00c +.copy.table 0xc 0x803e014 +.zero.table 0x0 0x803e020 .stack 0x1000 0x20000000 .data 0x734 0x20001000 .bss 0xaab0 0x20001734 text_application_ram 0x0 0x2000c1e4 .heap 0x800 0x2000c1e8 -.internal_storage 0x30000 0x803e008 -.zwave_nvm 0x0 0x806e008 -.nvm 0x8000 0x806e008 +.internal_storage 0x30000 0x803e020 +.zwave_nvm 0x0 0x806e020 +.nvm 0x8000 0x806e020 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12694 0x0 -.debug_info 0xe0fb21 0x0 -.debug_abbrev 0x297f9 0x0 -.debug_loclists 0x2aa32 0x0 +.debug_frame 0x12688 0x0 +.debug_info 0xe11239 0x0 +.debug_abbrev 0x29784 0x0 +.debug_loclists 0x2aaa5 0x0 .debug_aranges 0x6a48 0x0 -.debug_rnglists 0x509e 0x0 -.debug_line 0x785b1 0x0 -.debug_str 0x90593 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0x10389f4 +.debug_rnglists 0x50a4 0x0 +.debug_line 0x7867c 0x0 +.debug_str 0x9057c 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0x103a1d0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231228 + 231252 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_EU_size.txt index 239950f119..68087d2e7d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x3847c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e47c -_zaf_cc_config 0x28 0x803e48c -_cc_handlers_v3 0x2ac 0x803e4b4 -_zw_protocol_cmd_handlers 0x70 0x803e760 -_zw_protocol_cmd_handlers_lr 0x30 0x803e7d0 -.ARM.exidx 0x8 0x803e800 -.copy.table 0xc 0x803e808 -.zero.table 0x0 0x803e814 +.text 0x38494 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e494 +_zaf_cc_config 0x28 0x803e4a4 +_cc_handlers_v3 0x2ac 0x803e4cc +_zw_protocol_cmd_handlers 0x70 0x803e778 +_zw_protocol_cmd_handlers_lr 0x30 0x803e7e8 +.ARM.exidx 0x8 0x803e818 +.copy.table 0xc 0x803e820 +.zero.table 0x0 0x803e82c .stack 0x1000 0x20000000 .data 0x734 0x20001000 .bss 0xac50 0x20001734 text_application_ram 0x0 0x2000c384 .heap 0x800 0x2000c388 -.internal_storage 0x30000 0x803e814 -.zwave_nvm 0x0 0x806e814 -.nvm 0x8000 0x806e814 +.internal_storage 0x30000 0x803e82c +.zwave_nvm 0x0 0x806e82c +.nvm 0x8000 0x806e82c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12d54 0x0 -.debug_info 0xe16149 0x0 -.debug_abbrev 0x2a2bc 0x0 -.debug_loclists 0x2e584 0x0 +.debug_frame 0x12d48 0x0 +.debug_info 0xe17861 0x0 +.debug_abbrev 0x2a247 0x0 +.debug_loclists 0x2e5f7 0x0 .debug_aranges 0x6c38 0x0 -.debug_rnglists 0x5360 0x0 -.debug_line 0x7b558 0x0 -.debug_str 0x90ff3 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0x1048556 +.debug_rnglists 0x5366 0x0 +.debug_line 0x7b625 0x0 +.debug_str 0x90fdc 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0x1049d34 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 233288 + 233312 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_US_LR_size.txt index bbaacfec0d..7f35e9d479 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x3847c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e47c -_zaf_cc_config 0x28 0x803e48c -_cc_handlers_v3 0x2ac 0x803e4b4 -_zw_protocol_cmd_handlers 0x70 0x803e760 -_zw_protocol_cmd_handlers_lr 0x30 0x803e7d0 -.ARM.exidx 0x8 0x803e800 -.copy.table 0xc 0x803e808 -.zero.table 0x0 0x803e814 +.text 0x38494 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e494 +_zaf_cc_config 0x28 0x803e4a4 +_cc_handlers_v3 0x2ac 0x803e4cc +_zw_protocol_cmd_handlers 0x70 0x803e778 +_zw_protocol_cmd_handlers_lr 0x30 0x803e7e8 +.ARM.exidx 0x8 0x803e818 +.copy.table 0xc 0x803e820 +.zero.table 0x0 0x803e82c .stack 0x1000 0x20000000 .data 0x734 0x20001000 .bss 0xac50 0x20001734 text_application_ram 0x0 0x2000c384 .heap 0x800 0x2000c388 -.internal_storage 0x30000 0x803e814 -.zwave_nvm 0x0 0x806e814 -.nvm 0x8000 0x806e814 +.internal_storage 0x30000 0x803e82c +.zwave_nvm 0x0 0x806e82c +.nvm 0x8000 0x806e82c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12d54 0x0 -.debug_info 0xe16149 0x0 -.debug_abbrev 0x2a2bc 0x0 -.debug_loclists 0x2e584 0x0 +.debug_frame 0x12d48 0x0 +.debug_info 0xe17861 0x0 +.debug_abbrev 0x2a247 0x0 +.debug_loclists 0x2e5f7 0x0 .debug_aranges 0x6c38 0x0 -.debug_rnglists 0x5360 0x0 -.debug_line 0x7b558 0x0 -.debug_str 0x90fe9 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0x104854c +.debug_rnglists 0x5366 0x0 +.debug_line 0x7b625 0x0 +.debug_str 0x90fd2 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0x1049d2a The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 233288 + 233312 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_US_size.txt index 239950f119..68087d2e7d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x3847c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e47c -_zaf_cc_config 0x28 0x803e48c -_cc_handlers_v3 0x2ac 0x803e4b4 -_zw_protocol_cmd_handlers 0x70 0x803e760 -_zw_protocol_cmd_handlers_lr 0x30 0x803e7d0 -.ARM.exidx 0x8 0x803e800 -.copy.table 0xc 0x803e808 -.zero.table 0x0 0x803e814 +.text 0x38494 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e494 +_zaf_cc_config 0x28 0x803e4a4 +_cc_handlers_v3 0x2ac 0x803e4cc +_zw_protocol_cmd_handlers 0x70 0x803e778 +_zw_protocol_cmd_handlers_lr 0x30 0x803e7e8 +.ARM.exidx 0x8 0x803e818 +.copy.table 0xc 0x803e820 +.zero.table 0x0 0x803e82c .stack 0x1000 0x20000000 .data 0x734 0x20001000 .bss 0xac50 0x20001734 text_application_ram 0x0 0x2000c384 .heap 0x800 0x2000c388 -.internal_storage 0x30000 0x803e814 -.zwave_nvm 0x0 0x806e814 -.nvm 0x8000 0x806e814 +.internal_storage 0x30000 0x803e82c +.zwave_nvm 0x0 0x806e82c +.nvm 0x8000 0x806e82c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12d54 0x0 -.debug_info 0xe16149 0x0 -.debug_abbrev 0x2a2bc 0x0 -.debug_loclists 0x2e584 0x0 +.debug_frame 0x12d48 0x0 +.debug_info 0xe17861 0x0 +.debug_abbrev 0x2a247 0x0 +.debug_loclists 0x2e5f7 0x0 .debug_aranges 0x6c38 0x0 -.debug_rnglists 0x5360 0x0 -.debug_line 0x7b558 0x0 -.debug_str 0x90ff3 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0x1048556 +.debug_rnglists 0x5366 0x0 +.debug_line 0x7b625 0x0 +.debug_str 0x90fdc 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0x1049d34 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 233288 + 233312 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_EU_size.txt index 6bc12321a6..e089bd04e9 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x312a4 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x312a4 -_zaf_cc_config 0x28 0x312b4 -_cc_handlers_v3 0x2ac 0x312dc -_zw_protocol_cmd_handlers 0x70 0x31588 -_zw_protocol_cmd_handlers_lr 0x30 0x315f8 -.ARM.exidx 0x8 0x31628 -.copy.table 0xc 0x31630 -.zero.table 0x0 0x3163c +.text 0x312b8 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x312b8 +_zaf_cc_config 0x28 0x312c8 +_cc_handlers_v3 0x2ac 0x312f0 +_zw_protocol_cmd_handlers 0x70 0x3159c +_zw_protocol_cmd_handlers_lr 0x30 0x3160c +.ARM.exidx 0x8 0x3163c +.copy.table 0xc 0x31644 +.zero.table 0x0 0x31650 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xa0d4 0x200015b0 text_application_ram 0x0 0x2000b684 .heap 0x800 0x2000b688 -.internal_storage 0x3a000 0x3163c -.zwave_nvm 0x3000 0x6b63c -.nvm 0x9000 0x6e63c +.internal_storage 0x3a000 0x31650 +.zwave_nvm 0x3000 0x6b650 +.nvm 0x9000 0x6e650 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xfc84 0x0 -.debug_info 0xdc6278 0x0 -.debug_abbrev 0x247df 0x0 -.debug_loclists 0x1a3ef 0x0 -.debug_aranges 0x5d20 0x0 -.debug_rnglists 0x3cba 0x0 -.debug_line 0x64b28 0x0 -.debug_str 0x862b2 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xfbf11a +.debug_frame 0xfc58 0x0 +.debug_info 0xdc6452 0x0 +.debug_abbrev 0x2479a 0x0 +.debug_loclists 0x1a3db 0x0 +.debug_aranges 0x5d18 0x0 +.debug_rnglists 0x3cc9 0x0 +.debug_line 0x64b38 0x0 +.debug_str 0x8627a 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xfbf242 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 203756 + 203776 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_US_LR_size.txt index 84eb906de4..56ffadf4cc 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x312a4 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x312a4 -_zaf_cc_config 0x28 0x312b4 -_cc_handlers_v3 0x2ac 0x312dc -_zw_protocol_cmd_handlers 0x70 0x31588 -_zw_protocol_cmd_handlers_lr 0x30 0x315f8 -.ARM.exidx 0x8 0x31628 -.copy.table 0xc 0x31630 -.zero.table 0x0 0x3163c +.text 0x312b8 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x312b8 +_zaf_cc_config 0x28 0x312c8 +_cc_handlers_v3 0x2ac 0x312f0 +_zw_protocol_cmd_handlers 0x70 0x3159c +_zw_protocol_cmd_handlers_lr 0x30 0x3160c +.ARM.exidx 0x8 0x3163c +.copy.table 0xc 0x31644 +.zero.table 0x0 0x31650 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xa0d4 0x200015b0 text_application_ram 0x0 0x2000b684 .heap 0x800 0x2000b688 -.internal_storage 0x3a000 0x3163c -.zwave_nvm 0x3000 0x6b63c -.nvm 0x9000 0x6e63c +.internal_storage 0x3a000 0x31650 +.zwave_nvm 0x3000 0x6b650 +.nvm 0x9000 0x6e650 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xfc84 0x0 -.debug_info 0xdc6278 0x0 -.debug_abbrev 0x247df 0x0 -.debug_loclists 0x1a3ef 0x0 -.debug_aranges 0x5d20 0x0 -.debug_rnglists 0x3cba 0x0 -.debug_line 0x64b28 0x0 -.debug_str 0x862a8 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xfbf110 +.debug_frame 0xfc58 0x0 +.debug_info 0xdc6452 0x0 +.debug_abbrev 0x2479a 0x0 +.debug_loclists 0x1a3db 0x0 +.debug_aranges 0x5d18 0x0 +.debug_rnglists 0x3cc9 0x0 +.debug_line 0x64b38 0x0 +.debug_str 0x86270 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xfbf238 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 203756 + 203776 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_US_size.txt index 6bc12321a6..e089bd04e9 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x312a4 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x312a4 -_zaf_cc_config 0x28 0x312b4 -_cc_handlers_v3 0x2ac 0x312dc -_zw_protocol_cmd_handlers 0x70 0x31588 -_zw_protocol_cmd_handlers_lr 0x30 0x315f8 -.ARM.exidx 0x8 0x31628 -.copy.table 0xc 0x31630 -.zero.table 0x0 0x3163c +.text 0x312b8 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x312b8 +_zaf_cc_config 0x28 0x312c8 +_cc_handlers_v3 0x2ac 0x312f0 +_zw_protocol_cmd_handlers 0x70 0x3159c +_zw_protocol_cmd_handlers_lr 0x30 0x3160c +.ARM.exidx 0x8 0x3163c +.copy.table 0xc 0x31644 +.zero.table 0x0 0x31650 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xa0d4 0x200015b0 text_application_ram 0x0 0x2000b684 .heap 0x800 0x2000b688 -.internal_storage 0x3a000 0x3163c -.zwave_nvm 0x3000 0x6b63c -.nvm 0x9000 0x6e63c +.internal_storage 0x3a000 0x31650 +.zwave_nvm 0x3000 0x6b650 +.nvm 0x9000 0x6e650 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xfc84 0x0 -.debug_info 0xdc6278 0x0 -.debug_abbrev 0x247df 0x0 -.debug_loclists 0x1a3ef 0x0 -.debug_aranges 0x5d20 0x0 -.debug_rnglists 0x3cba 0x0 -.debug_line 0x64b28 0x0 -.debug_str 0x862b2 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xfbf11a +.debug_frame 0xfc58 0x0 +.debug_info 0xdc6452 0x0 +.debug_abbrev 0x2479a 0x0 +.debug_loclists 0x1a3db 0x0 +.debug_aranges 0x5d18 0x0 +.debug_rnglists 0x3cc9 0x0 +.debug_line 0x64b38 0x0 +.debug_str 0x8627a 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xfbf242 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 203756 + 203776 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4209A_REGION_US_LR_size.txt index 01c3a48468..57c9f67a65 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4209A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x311fc 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x311fc -_zaf_cc_config 0x28 0x3120c -_cc_handlers_v3 0x2ac 0x31234 -_zw_protocol_cmd_handlers 0x70 0x314e0 -_zw_protocol_cmd_handlers_lr 0x30 0x31550 -.ARM.exidx 0x8 0x31580 -.copy.table 0xc 0x31588 -.zero.table 0x0 0x31594 +.text 0x31210 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x31210 +_zaf_cc_config 0x28 0x31220 +_cc_handlers_v3 0x2ac 0x31248 +_zw_protocol_cmd_handlers 0x70 0x314f4 +_zw_protocol_cmd_handlers_lr 0x30 0x31564 +.ARM.exidx 0x8 0x31594 +.copy.table 0xc 0x3159c +.zero.table 0x0 0x315a8 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xa0b8 0x200015b0 text_application_ram 0x0 0x2000b668 .heap 0x800 0x2000b668 -.internal_storage 0x3a000 0x31594 -.zwave_nvm 0x3000 0x6b594 -.nvm 0x9000 0x6e594 +.internal_storage 0x3a000 0x315a8 +.zwave_nvm 0x3000 0x6b5a8 +.nvm 0x9000 0x6e5a8 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xfe54 0x0 -.debug_info 0xdc7859 0x0 -.debug_abbrev 0x24d22 0x0 -.debug_loclists 0x1aa8c 0x0 -.debug_aranges 0x5dc0 0x0 -.debug_rnglists 0x3d65 0x0 -.debug_line 0x65b6a 0x0 -.debug_str 0x865e2 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xfc28a4 +.debug_frame 0xfe28 0x0 +.debug_info 0xdc7a33 0x0 +.debug_abbrev 0x24cdd 0x0 +.debug_loclists 0x1aa78 0x0 +.debug_aranges 0x5db8 0x0 +.debug_rnglists 0x3d74 0x0 +.debug_line 0x65b84 0x0 +.debug_str 0x865aa 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xfc29d6 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 203588 + 203608 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2603A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2603A_REGION_EU_size.txt index 539ebf5906..bad0ce6cfa 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2603A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2603A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37b3c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803db3c -_zaf_cc_config 0x10 0x803db4c -_cc_handlers_v3 0x21c 0x803db5c -_zw_protocol_cmd_handlers 0x70 0x803dd78 -_zw_protocol_cmd_handlers_lr 0x30 0x803dde8 -.ARM.exidx 0x8 0x803de18 -.copy.table 0xc 0x803de20 -.zero.table 0x0 0x803de2c +.text 0x37b54 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803db54 +_zaf_cc_config 0x10 0x803db64 +_cc_handlers_v3 0x21c 0x803db74 +_zw_protocol_cmd_handlers 0x70 0x803dd90 +_zw_protocol_cmd_handlers_lr 0x30 0x803de00 +.ARM.exidx 0x8 0x803de30 +.copy.table 0xc 0x803de38 +.zero.table 0x0 0x803de44 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xacf8 0x200015b4 text_application_ram 0x0 0x2000c2ac .heap 0x800 0x2000c2b0 -.internal_storage 0x30000 0x803de2c -.zwave_nvm 0x0 0x806de2c -.nvm 0x8000 0x806de2c +.internal_storage 0x30000 0x803de44 +.zwave_nvm 0x0 0x806de44 +.nvm 0x8000 0x806de44 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1279c 0x0 -.debug_info 0xce684d 0x0 -.debug_abbrev 0x2854d 0x0 +.debug_frame 0x12790 0x0 +.debug_info 0xce7f65 0x0 +.debug_abbrev 0x284d8 0x0 .debug_aranges 0x69a0 0x0 -.debug_rnglists 0x4f1d 0x0 -.debug_line 0x77cfe 0x0 -.debug_str 0x90dc4 0x0 -.debug_loclists 0x2ccd8 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf10463 +.debug_rnglists 0x4f23 0x0 +.debug_line 0x77dcb 0x0 +.debug_str 0x90dad 0x0 +.debug_loclists 0x2cd4b 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf11c41 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230368 + 230392 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2603A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2603A_REGION_US_LR_size.txt index 58efac888a..58721cd442 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2603A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2603A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37b3c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803db3c -_zaf_cc_config 0x10 0x803db4c -_cc_handlers_v3 0x21c 0x803db5c -_zw_protocol_cmd_handlers 0x70 0x803dd78 -_zw_protocol_cmd_handlers_lr 0x30 0x803dde8 -.ARM.exidx 0x8 0x803de18 -.copy.table 0xc 0x803de20 -.zero.table 0x0 0x803de2c +.text 0x37b54 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803db54 +_zaf_cc_config 0x10 0x803db64 +_cc_handlers_v3 0x21c 0x803db74 +_zw_protocol_cmd_handlers 0x70 0x803dd90 +_zw_protocol_cmd_handlers_lr 0x30 0x803de00 +.ARM.exidx 0x8 0x803de30 +.copy.table 0xc 0x803de38 +.zero.table 0x0 0x803de44 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xacf8 0x200015b4 text_application_ram 0x0 0x2000c2ac .heap 0x800 0x2000c2b0 -.internal_storage 0x30000 0x803de2c -.zwave_nvm 0x0 0x806de2c -.nvm 0x8000 0x806de2c +.internal_storage 0x30000 0x803de44 +.zwave_nvm 0x0 0x806de44 +.nvm 0x8000 0x806de44 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1279c 0x0 -.debug_info 0xce684d 0x0 -.debug_abbrev 0x2854d 0x0 +.debug_frame 0x12790 0x0 +.debug_info 0xce7f65 0x0 +.debug_abbrev 0x284d8 0x0 .debug_aranges 0x69a0 0x0 -.debug_rnglists 0x4f1d 0x0 -.debug_line 0x77cfe 0x0 -.debug_str 0x90dba 0x0 -.debug_loclists 0x2ccd8 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf10459 +.debug_rnglists 0x4f23 0x0 +.debug_line 0x77dcb 0x0 +.debug_str 0x90da3 0x0 +.debug_loclists 0x2cd4b 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf11c37 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230368 + 230392 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2603A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2603A_REGION_US_size.txt index 539ebf5906..bad0ce6cfa 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2603A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2603A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37b3c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803db3c -_zaf_cc_config 0x10 0x803db4c -_cc_handlers_v3 0x21c 0x803db5c -_zw_protocol_cmd_handlers 0x70 0x803dd78 -_zw_protocol_cmd_handlers_lr 0x30 0x803dde8 -.ARM.exidx 0x8 0x803de18 -.copy.table 0xc 0x803de20 -.zero.table 0x0 0x803de2c +.text 0x37b54 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803db54 +_zaf_cc_config 0x10 0x803db64 +_cc_handlers_v3 0x21c 0x803db74 +_zw_protocol_cmd_handlers 0x70 0x803dd90 +_zw_protocol_cmd_handlers_lr 0x30 0x803de00 +.ARM.exidx 0x8 0x803de30 +.copy.table 0xc 0x803de38 +.zero.table 0x0 0x803de44 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xacf8 0x200015b4 text_application_ram 0x0 0x2000c2ac .heap 0x800 0x2000c2b0 -.internal_storage 0x30000 0x803de2c -.zwave_nvm 0x0 0x806de2c -.nvm 0x8000 0x806de2c +.internal_storage 0x30000 0x803de44 +.zwave_nvm 0x0 0x806de44 +.nvm 0x8000 0x806de44 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1279c 0x0 -.debug_info 0xce684d 0x0 -.debug_abbrev 0x2854d 0x0 +.debug_frame 0x12790 0x0 +.debug_info 0xce7f65 0x0 +.debug_abbrev 0x284d8 0x0 .debug_aranges 0x69a0 0x0 -.debug_rnglists 0x4f1d 0x0 -.debug_line 0x77cfe 0x0 -.debug_str 0x90dc4 0x0 -.debug_loclists 0x2ccd8 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf10463 +.debug_rnglists 0x4f23 0x0 +.debug_line 0x77dcb 0x0 +.debug_str 0x90dad 0x0 +.debug_loclists 0x2cd4b 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf11c41 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230368 + 230392 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2705A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2705A_REGION_EU_size.txt index 48c8a5cd16..2c5220dc80 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2705A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2705A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37f90 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803df90 -_zaf_cc_config 0x10 0x803dfa0 -_cc_handlers_v3 0x21c 0x803dfb0 -_zw_protocol_cmd_handlers 0x70 0x803e1cc -_zw_protocol_cmd_handlers_lr 0x30 0x803e23c -.ARM.exidx 0x8 0x803e26c -.copy.table 0xc 0x803e274 -.zero.table 0x0 0x803e280 +.text 0x37fa8 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803dfa8 +_zaf_cc_config 0x10 0x803dfb8 +_cc_handlers_v3 0x21c 0x803dfc8 +_zw_protocol_cmd_handlers 0x70 0x803e1e4 +_zw_protocol_cmd_handlers_lr 0x30 0x803e254 +.ARM.exidx 0x8 0x803e284 +.copy.table 0xc 0x803e28c +.zero.table 0x0 0x803e298 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xac60 0x200015b0 text_application_ram 0x0 0x2000c210 .heap 0x800 0x2000c210 -.internal_storage 0x30000 0x803e280 -.zwave_nvm 0x0 0x806e280 -.nvm 0x8000 0x806e280 +.internal_storage 0x30000 0x803e298 +.zwave_nvm 0x0 0x806e298 +.nvm 0x8000 0x806e298 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x125a0 0x0 -.debug_info 0xce2fcd 0x0 -.debug_abbrev 0x27fa2 0x0 +.debug_frame 0x12594 0x0 +.debug_info 0xce46e9 0x0 +.debug_abbrev 0x27f2d 0x0 .debug_aranges 0x68c0 0x0 -.debug_rnglists 0x4e5a 0x0 -.debug_line 0x76d6d 0x0 -.debug_str 0x912d6 0x0 -.debug_loclists 0x2ca9f 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf0b895 +.debug_rnglists 0x4e60 0x0 +.debug_line 0x76e42 0x0 +.debug_str 0x912bf 0x0 +.debug_loclists 0x2cb12 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf0d07f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231472 + 231496 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2705A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2705A_REGION_US_LR_size.txt index 88610a7fdc..80b9ab9412 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2705A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2705A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37f90 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803df90 -_zaf_cc_config 0x10 0x803dfa0 -_cc_handlers_v3 0x21c 0x803dfb0 -_zw_protocol_cmd_handlers 0x70 0x803e1cc -_zw_protocol_cmd_handlers_lr 0x30 0x803e23c -.ARM.exidx 0x8 0x803e26c -.copy.table 0xc 0x803e274 -.zero.table 0x0 0x803e280 +.text 0x37fa8 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803dfa8 +_zaf_cc_config 0x10 0x803dfb8 +_cc_handlers_v3 0x21c 0x803dfc8 +_zw_protocol_cmd_handlers 0x70 0x803e1e4 +_zw_protocol_cmd_handlers_lr 0x30 0x803e254 +.ARM.exidx 0x8 0x803e284 +.copy.table 0xc 0x803e28c +.zero.table 0x0 0x803e298 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xac60 0x200015b0 text_application_ram 0x0 0x2000c210 .heap 0x800 0x2000c210 -.internal_storage 0x30000 0x803e280 -.zwave_nvm 0x0 0x806e280 -.nvm 0x8000 0x806e280 +.internal_storage 0x30000 0x803e298 +.zwave_nvm 0x0 0x806e298 +.nvm 0x8000 0x806e298 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x125a0 0x0 -.debug_info 0xce2fcd 0x0 -.debug_abbrev 0x27fa2 0x0 +.debug_frame 0x12594 0x0 +.debug_info 0xce46e9 0x0 +.debug_abbrev 0x27f2d 0x0 .debug_aranges 0x68c0 0x0 -.debug_rnglists 0x4e5a 0x0 -.debug_line 0x76d6d 0x0 -.debug_str 0x912cc 0x0 -.debug_loclists 0x2ca9f 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf0b88b +.debug_rnglists 0x4e60 0x0 +.debug_line 0x76e42 0x0 +.debug_str 0x912b5 0x0 +.debug_loclists 0x2cb12 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf0d075 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231472 + 231496 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2705A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2705A_REGION_US_size.txt index 48c8a5cd16..2c5220dc80 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2705A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD2705A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37f90 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803df90 -_zaf_cc_config 0x10 0x803dfa0 -_cc_handlers_v3 0x21c 0x803dfb0 -_zw_protocol_cmd_handlers 0x70 0x803e1cc -_zw_protocol_cmd_handlers_lr 0x30 0x803e23c -.ARM.exidx 0x8 0x803e26c -.copy.table 0xc 0x803e274 -.zero.table 0x0 0x803e280 +.text 0x37fa8 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803dfa8 +_zaf_cc_config 0x10 0x803dfb8 +_cc_handlers_v3 0x21c 0x803dfc8 +_zw_protocol_cmd_handlers 0x70 0x803e1e4 +_zw_protocol_cmd_handlers_lr 0x30 0x803e254 +.ARM.exidx 0x8 0x803e284 +.copy.table 0xc 0x803e28c +.zero.table 0x0 0x803e298 .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xac60 0x200015b0 text_application_ram 0x0 0x2000c210 .heap 0x800 0x2000c210 -.internal_storage 0x30000 0x803e280 -.zwave_nvm 0x0 0x806e280 -.nvm 0x8000 0x806e280 +.internal_storage 0x30000 0x803e298 +.zwave_nvm 0x0 0x806e298 +.nvm 0x8000 0x806e298 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x125a0 0x0 -.debug_info 0xce2fcd 0x0 -.debug_abbrev 0x27fa2 0x0 +.debug_frame 0x12594 0x0 +.debug_info 0xce46e9 0x0 +.debug_abbrev 0x27f2d 0x0 .debug_aranges 0x68c0 0x0 -.debug_rnglists 0x4e5a 0x0 -.debug_line 0x76d6d 0x0 -.debug_str 0x912d6 0x0 -.debug_loclists 0x2ca9f 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf0b895 +.debug_rnglists 0x4e60 0x0 +.debug_line 0x76e42 0x0 +.debug_str 0x912bf 0x0 +.debug_loclists 0x2cb12 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf0d07f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231472 + 231496 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_EU_size.txt index 50f08b5e71..e574a0bba0 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x308d4 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x308d4 -_zaf_cc_config 0x10 0x308e4 -_cc_handlers_v3 0x21c 0x308f4 -_zw_protocol_cmd_handlers 0x70 0x30b10 -_zw_protocol_cmd_handlers_lr 0x30 0x30b80 -.ARM.exidx 0x8 0x30bb0 -.copy.table 0xc 0x30bb8 -.zero.table 0x0 0x30bc4 +.text 0x308c8 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x308c8 +_zaf_cc_config 0x10 0x308d8 +_cc_handlers_v3 0x21c 0x308e8 +_zw_protocol_cmd_handlers 0x70 0x30b04 +_zw_protocol_cmd_handlers_lr 0x30 0x30b74 +.ARM.exidx 0x8 0x30ba4 +.copy.table 0xc 0x30bac +.zero.table 0x0 0x30bb8 .stack 0x1000 0x20000000 .data 0x430 0x20001000 .bss 0xa180 0x20001430 text_application_ram 0x0 0x2000b5b0 .heap 0x800 0x2000b5b0 -.internal_storage 0x3a000 0x30bc4 -.zwave_nvm 0x3000 0x6abc4 -.nvm 0x9000 0x6dbc4 +.internal_storage 0x3a000 0x30bb8 +.zwave_nvm 0x3000 0x6abb8 +.nvm 0x9000 0x6dbb8 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf738 0x0 -.debug_info 0xc9d3ee 0x0 -.debug_abbrev 0x22e46 0x0 -.debug_aranges 0x5ad0 0x0 -.debug_rnglists 0x3830 0x0 -.debug_line 0x61925 0x0 -.debug_str 0x8708b 0x0 -.debug_loclists 0x18bea 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe8f556 +.debug_frame 0xf70c 0x0 +.debug_info 0xc9d5c8 0x0 +.debug_abbrev 0x22e01 0x0 +.debug_aranges 0x5ac8 0x0 +.debug_rnglists 0x383f 0x0 +.debug_line 0x61935 0x0 +.debug_str 0x87053 0x0 +.debug_loclists 0x18bd6 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe8f65e The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 200692 + 200680 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_US_LR_size.txt index 4c18ffebfc..3eda7ea1c5 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x308d4 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x308d4 -_zaf_cc_config 0x10 0x308e4 -_cc_handlers_v3 0x21c 0x308f4 -_zw_protocol_cmd_handlers 0x70 0x30b10 -_zw_protocol_cmd_handlers_lr 0x30 0x30b80 -.ARM.exidx 0x8 0x30bb0 -.copy.table 0xc 0x30bb8 -.zero.table 0x0 0x30bc4 +.text 0x308c8 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x308c8 +_zaf_cc_config 0x10 0x308d8 +_cc_handlers_v3 0x21c 0x308e8 +_zw_protocol_cmd_handlers 0x70 0x30b04 +_zw_protocol_cmd_handlers_lr 0x30 0x30b74 +.ARM.exidx 0x8 0x30ba4 +.copy.table 0xc 0x30bac +.zero.table 0x0 0x30bb8 .stack 0x1000 0x20000000 .data 0x430 0x20001000 .bss 0xa180 0x20001430 text_application_ram 0x0 0x2000b5b0 .heap 0x800 0x2000b5b0 -.internal_storage 0x3a000 0x30bc4 -.zwave_nvm 0x3000 0x6abc4 -.nvm 0x9000 0x6dbc4 +.internal_storage 0x3a000 0x30bb8 +.zwave_nvm 0x3000 0x6abb8 +.nvm 0x9000 0x6dbb8 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf738 0x0 -.debug_info 0xc9d3ee 0x0 -.debug_abbrev 0x22e46 0x0 -.debug_aranges 0x5ad0 0x0 -.debug_rnglists 0x3830 0x0 -.debug_line 0x61925 0x0 -.debug_str 0x87081 0x0 -.debug_loclists 0x18bea 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe8f54c +.debug_frame 0xf70c 0x0 +.debug_info 0xc9d5c8 0x0 +.debug_abbrev 0x22e01 0x0 +.debug_aranges 0x5ac8 0x0 +.debug_rnglists 0x383f 0x0 +.debug_line 0x61935 0x0 +.debug_str 0x87049 0x0 +.debug_loclists 0x18bd6 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe8f654 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 200692 + 200680 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_US_size.txt index 50f08b5e71..e574a0bba0 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x308d4 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x308d4 -_zaf_cc_config 0x10 0x308e4 -_cc_handlers_v3 0x21c 0x308f4 -_zw_protocol_cmd_handlers 0x70 0x30b10 -_zw_protocol_cmd_handlers_lr 0x30 0x30b80 -.ARM.exidx 0x8 0x30bb0 -.copy.table 0xc 0x30bb8 -.zero.table 0x0 0x30bc4 +.text 0x308c8 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x308c8 +_zaf_cc_config 0x10 0x308d8 +_cc_handlers_v3 0x21c 0x308e8 +_zw_protocol_cmd_handlers 0x70 0x30b04 +_zw_protocol_cmd_handlers_lr 0x30 0x30b74 +.ARM.exidx 0x8 0x30ba4 +.copy.table 0xc 0x30bac +.zero.table 0x0 0x30bb8 .stack 0x1000 0x20000000 .data 0x430 0x20001000 .bss 0xa180 0x20001430 text_application_ram 0x0 0x2000b5b0 .heap 0x800 0x2000b5b0 -.internal_storage 0x3a000 0x30bc4 -.zwave_nvm 0x3000 0x6abc4 -.nvm 0x9000 0x6dbc4 +.internal_storage 0x3a000 0x30bb8 +.zwave_nvm 0x3000 0x6abb8 +.nvm 0x9000 0x6dbb8 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf738 0x0 -.debug_info 0xc9d3ee 0x0 -.debug_abbrev 0x22e46 0x0 -.debug_aranges 0x5ad0 0x0 -.debug_rnglists 0x3830 0x0 -.debug_line 0x61925 0x0 -.debug_str 0x8708b 0x0 -.debug_loclists 0x18bea 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe8f556 +.debug_frame 0xf70c 0x0 +.debug_info 0xc9d5c8 0x0 +.debug_abbrev 0x22e01 0x0 +.debug_aranges 0x5ac8 0x0 +.debug_rnglists 0x383f 0x0 +.debug_line 0x61935 0x0 +.debug_str 0x87053 0x0 +.debug_loclists 0x18bd6 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe8f65e The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 200692 + 200680 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_EU_size.txt index 72280d1a93..435626a289 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37770 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d770 -_zaf_cc_config 0x10 0x803d780 -_cc_handlers_v3 0x21c 0x803d790 -_zw_protocol_cmd_handlers 0x70 0x803d9ac -_zw_protocol_cmd_handlers_lr 0x30 0x803da1c -.ARM.exidx 0x8 0x803da4c -.copy.table 0xc 0x803da54 -.zero.table 0x0 0x803da60 +.text 0x37788 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d788 +_zaf_cc_config 0x10 0x803d798 +_cc_handlers_v3 0x21c 0x803d7a8 +_zw_protocol_cmd_handlers 0x70 0x803d9c4 +_zw_protocol_cmd_handlers_lr 0x30 0x803da34 +.ARM.exidx 0x8 0x803da64 +.copy.table 0xc 0x803da6c +.zero.table 0x0 0x803da78 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xacf8 0x200015b4 text_application_ram 0x0 0x2000c2ac .heap 0x800 0x2000c2b0 -.internal_storage 0x30000 0x803da60 -.zwave_nvm 0x0 0x806da60 -.nvm 0x8000 0x806da60 +.internal_storage 0x30000 0x803da78 +.zwave_nvm 0x0 0x806da78 +.nvm 0x8000 0x806da78 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12820 0x0 -.debug_info 0xce8063 0x0 -.debug_abbrev 0x28722 0x0 +.debug_frame 0x12814 0x0 +.debug_info 0xce977b 0x0 +.debug_abbrev 0x286ad 0x0 .debug_aranges 0x6990 0x0 -.debug_rnglists 0x4f4f 0x0 -.debug_line 0x783ce 0x0 -.debug_str 0x90873 0x0 -.debug_loclists 0x2cf46 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf11f24 +.debug_rnglists 0x4f55 0x0 +.debug_line 0x784a3 0x0 +.debug_str 0x9085c 0x0 +.debug_loclists 0x2cfb9 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf1370a The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 229396 + 229420 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_US_LR_size.txt index a24a635856..cfd1dff30c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37770 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d770 -_zaf_cc_config 0x10 0x803d780 -_cc_handlers_v3 0x21c 0x803d790 -_zw_protocol_cmd_handlers 0x70 0x803d9ac -_zw_protocol_cmd_handlers_lr 0x30 0x803da1c -.ARM.exidx 0x8 0x803da4c -.copy.table 0xc 0x803da54 -.zero.table 0x0 0x803da60 +.text 0x37788 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d788 +_zaf_cc_config 0x10 0x803d798 +_cc_handlers_v3 0x21c 0x803d7a8 +_zw_protocol_cmd_handlers 0x70 0x803d9c4 +_zw_protocol_cmd_handlers_lr 0x30 0x803da34 +.ARM.exidx 0x8 0x803da64 +.copy.table 0xc 0x803da6c +.zero.table 0x0 0x803da78 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xacf8 0x200015b4 text_application_ram 0x0 0x2000c2ac .heap 0x800 0x2000c2b0 -.internal_storage 0x30000 0x803da60 -.zwave_nvm 0x0 0x806da60 -.nvm 0x8000 0x806da60 +.internal_storage 0x30000 0x803da78 +.zwave_nvm 0x0 0x806da78 +.nvm 0x8000 0x806da78 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12820 0x0 -.debug_info 0xce8063 0x0 -.debug_abbrev 0x28722 0x0 +.debug_frame 0x12814 0x0 +.debug_info 0xce977b 0x0 +.debug_abbrev 0x286ad 0x0 .debug_aranges 0x6990 0x0 -.debug_rnglists 0x4f4f 0x0 -.debug_line 0x783ce 0x0 -.debug_str 0x90869 0x0 -.debug_loclists 0x2cf46 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf11f1a +.debug_rnglists 0x4f55 0x0 +.debug_line 0x784a3 0x0 +.debug_str 0x90852 0x0 +.debug_loclists 0x2cfb9 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf13700 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 229396 + 229420 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_US_size.txt index 72280d1a93..435626a289 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37770 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d770 -_zaf_cc_config 0x10 0x803d780 -_cc_handlers_v3 0x21c 0x803d790 -_zw_protocol_cmd_handlers 0x70 0x803d9ac -_zw_protocol_cmd_handlers_lr 0x30 0x803da1c -.ARM.exidx 0x8 0x803da4c -.copy.table 0xc 0x803da54 -.zero.table 0x0 0x803da60 +.text 0x37788 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d788 +_zaf_cc_config 0x10 0x803d798 +_cc_handlers_v3 0x21c 0x803d7a8 +_zw_protocol_cmd_handlers 0x70 0x803d9c4 +_zw_protocol_cmd_handlers_lr 0x30 0x803da34 +.ARM.exidx 0x8 0x803da64 +.copy.table 0xc 0x803da6c +.zero.table 0x0 0x803da78 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xacf8 0x200015b4 text_application_ram 0x0 0x2000c2ac .heap 0x800 0x2000c2b0 -.internal_storage 0x30000 0x803da60 -.zwave_nvm 0x0 0x806da60 -.nvm 0x8000 0x806da60 +.internal_storage 0x30000 0x803da78 +.zwave_nvm 0x0 0x806da78 +.nvm 0x8000 0x806da78 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12820 0x0 -.debug_info 0xce8063 0x0 -.debug_abbrev 0x28722 0x0 +.debug_frame 0x12814 0x0 +.debug_info 0xce977b 0x0 +.debug_abbrev 0x286ad 0x0 .debug_aranges 0x6990 0x0 -.debug_rnglists 0x4f4f 0x0 -.debug_line 0x783ce 0x0 -.debug_str 0x90873 0x0 -.debug_loclists 0x2cf46 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf11f24 +.debug_rnglists 0x4f55 0x0 +.debug_line 0x784a3 0x0 +.debug_str 0x9085c 0x0 +.debug_loclists 0x2cfb9 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf1370a The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 229396 + 229420 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_EU_size.txt index b167e61ba2..9ba9ddb855 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37844 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d844 -_zaf_cc_config 0x10 0x803d854 -_cc_handlers_v3 0x21c 0x803d864 -_zw_protocol_cmd_handlers 0x70 0x803da80 -_zw_protocol_cmd_handlers_lr 0x30 0x803daf0 -.ARM.exidx 0x8 0x803db20 -.copy.table 0xc 0x803db28 -.zero.table 0x0 0x803db34 +.text 0x3785c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d85c +_zaf_cc_config 0x10 0x803d86c +_cc_handlers_v3 0x21c 0x803d87c +_zw_protocol_cmd_handlers 0x70 0x803da98 +_zw_protocol_cmd_handlers_lr 0x30 0x803db08 +.ARM.exidx 0x8 0x803db38 +.copy.table 0xc 0x803db40 +.zero.table 0x0 0x803db4c .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xacf8 0x200015b4 text_application_ram 0x0 0x2000c2ac .heap 0x800 0x2000c2b0 -.internal_storage 0x30000 0x803db34 -.zwave_nvm 0x0 0x806db34 -.nvm 0x8000 0x806db34 +.internal_storage 0x30000 0x803db4c +.zwave_nvm 0x0 0x806db4c +.nvm 0x8000 0x806db4c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12850 0x0 -.debug_info 0xce82db 0x0 -.debug_abbrev 0x28824 0x0 +.debug_frame 0x12844 0x0 +.debug_info 0xce99f3 0x0 +.debug_abbrev 0x287af 0x0 .debug_aranges 0x69b0 0x0 -.debug_rnglists 0x4f62 0x0 -.debug_line 0x785ae 0x0 -.debug_str 0x90a46 0x0 -.debug_loclists 0x2cf46 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf12788 +.debug_rnglists 0x4f68 0x0 +.debug_line 0x78683 0x0 +.debug_str 0x90a2f 0x0 +.debug_loclists 0x2cfb9 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf13f6e The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 229608 + 229632 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_US_LR_size.txt index d70a2239e6..5f96b7e450 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37844 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d844 -_zaf_cc_config 0x10 0x803d854 -_cc_handlers_v3 0x21c 0x803d864 -_zw_protocol_cmd_handlers 0x70 0x803da80 -_zw_protocol_cmd_handlers_lr 0x30 0x803daf0 -.ARM.exidx 0x8 0x803db20 -.copy.table 0xc 0x803db28 -.zero.table 0x0 0x803db34 +.text 0x3785c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d85c +_zaf_cc_config 0x10 0x803d86c +_cc_handlers_v3 0x21c 0x803d87c +_zw_protocol_cmd_handlers 0x70 0x803da98 +_zw_protocol_cmd_handlers_lr 0x30 0x803db08 +.ARM.exidx 0x8 0x803db38 +.copy.table 0xc 0x803db40 +.zero.table 0x0 0x803db4c .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xacf8 0x200015b4 text_application_ram 0x0 0x2000c2ac .heap 0x800 0x2000c2b0 -.internal_storage 0x30000 0x803db34 -.zwave_nvm 0x0 0x806db34 -.nvm 0x8000 0x806db34 +.internal_storage 0x30000 0x803db4c +.zwave_nvm 0x0 0x806db4c +.nvm 0x8000 0x806db4c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12850 0x0 -.debug_info 0xce82db 0x0 -.debug_abbrev 0x28824 0x0 +.debug_frame 0x12844 0x0 +.debug_info 0xce99f3 0x0 +.debug_abbrev 0x287af 0x0 .debug_aranges 0x69b0 0x0 -.debug_rnglists 0x4f62 0x0 -.debug_line 0x785ae 0x0 -.debug_str 0x90a3c 0x0 -.debug_loclists 0x2cf46 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf1277e +.debug_rnglists 0x4f68 0x0 +.debug_line 0x78683 0x0 +.debug_str 0x90a25 0x0 +.debug_loclists 0x2cfb9 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf13f64 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 229608 + 229632 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_US_size.txt index b167e61ba2..9ba9ddb855 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37844 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d844 -_zaf_cc_config 0x10 0x803d854 -_cc_handlers_v3 0x21c 0x803d864 -_zw_protocol_cmd_handlers 0x70 0x803da80 -_zw_protocol_cmd_handlers_lr 0x30 0x803daf0 -.ARM.exidx 0x8 0x803db20 -.copy.table 0xc 0x803db28 -.zero.table 0x0 0x803db34 +.text 0x3785c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d85c +_zaf_cc_config 0x10 0x803d86c +_cc_handlers_v3 0x21c 0x803d87c +_zw_protocol_cmd_handlers 0x70 0x803da98 +_zw_protocol_cmd_handlers_lr 0x30 0x803db08 +.ARM.exidx 0x8 0x803db38 +.copy.table 0xc 0x803db40 +.zero.table 0x0 0x803db4c .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xacf8 0x200015b4 text_application_ram 0x0 0x2000c2ac .heap 0x800 0x2000c2b0 -.internal_storage 0x30000 0x803db34 -.zwave_nvm 0x0 0x806db34 -.nvm 0x8000 0x806db34 +.internal_storage 0x30000 0x803db4c +.zwave_nvm 0x0 0x806db4c +.nvm 0x8000 0x806db4c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12850 0x0 -.debug_info 0xce82db 0x0 -.debug_abbrev 0x28824 0x0 +.debug_frame 0x12844 0x0 +.debug_info 0xce99f3 0x0 +.debug_abbrev 0x287af 0x0 .debug_aranges 0x69b0 0x0 -.debug_rnglists 0x4f62 0x0 -.debug_line 0x785ae 0x0 -.debug_str 0x90a46 0x0 -.debug_loclists 0x2cf46 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf12788 +.debug_rnglists 0x4f68 0x0 +.debug_line 0x78683 0x0 +.debug_str 0x90a2f 0x0 +.debug_loclists 0x2cfb9 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf13f6e The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 229608 + 229632 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_EU_size.txt index 220428df28..ef94cfe1d8 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37328 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d328 -_zaf_cc_config 0x10 0x803d338 -_cc_handlers_v3 0x21c 0x803d348 -_zw_protocol_cmd_handlers 0x70 0x803d564 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5d4 -.ARM.exidx 0x8 0x803d604 -.copy.table 0xc 0x803d60c -.zero.table 0x0 0x803d618 +.text 0x37340 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d340 +_zaf_cc_config 0x10 0x803d350 +_cc_handlers_v3 0x21c 0x803d360 +_zw_protocol_cmd_handlers 0x70 0x803d57c +_zw_protocol_cmd_handlers_lr 0x30 0x803d5ec +.ARM.exidx 0x8 0x803d61c +.copy.table 0xc 0x803d624 +.zero.table 0x0 0x803d630 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xab58 0x200015b4 text_application_ram 0x0 0x2000c10c .heap 0x800 0x2000c110 -.internal_storage 0x30000 0x803d618 -.zwave_nvm 0x0 0x806d618 -.nvm 0x8000 0x806d618 +.internal_storage 0x30000 0x803d630 +.zwave_nvm 0x0 0x806d630 +.nvm 0x8000 0x806d630 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x121c0 0x0 -.debug_info 0xce2682 0x0 -.debug_abbrev 0x27e3d 0x0 +.debug_frame 0x121b4 0x0 +.debug_info 0xce3d9a 0x0 +.debug_abbrev 0x27dc8 0x0 .debug_aranges 0x6810 0x0 -.debug_rnglists 0x4cb8 0x0 -.debug_line 0x754dd 0x0 -.debug_str 0x905ae 0x0 -.debug_loclists 0x293fd 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf03ef1 +.debug_rnglists 0x4cbe 0x0 +.debug_line 0x755a8 0x0 +.debug_str 0x90597 0x0 +.debug_loclists 0x29470 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf056cd The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228300 + 228324 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_US_LR_size.txt index b8e579f42e..63952a9b08 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37328 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d328 -_zaf_cc_config 0x10 0x803d338 -_cc_handlers_v3 0x21c 0x803d348 -_zw_protocol_cmd_handlers 0x70 0x803d564 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5d4 -.ARM.exidx 0x8 0x803d604 -.copy.table 0xc 0x803d60c -.zero.table 0x0 0x803d618 +.text 0x37340 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d340 +_zaf_cc_config 0x10 0x803d350 +_cc_handlers_v3 0x21c 0x803d360 +_zw_protocol_cmd_handlers 0x70 0x803d57c +_zw_protocol_cmd_handlers_lr 0x30 0x803d5ec +.ARM.exidx 0x8 0x803d61c +.copy.table 0xc 0x803d624 +.zero.table 0x0 0x803d630 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xab58 0x200015b4 text_application_ram 0x0 0x2000c10c .heap 0x800 0x2000c110 -.internal_storage 0x30000 0x803d618 -.zwave_nvm 0x0 0x806d618 -.nvm 0x8000 0x806d618 +.internal_storage 0x30000 0x803d630 +.zwave_nvm 0x0 0x806d630 +.nvm 0x8000 0x806d630 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x121c0 0x0 -.debug_info 0xce2682 0x0 -.debug_abbrev 0x27e3d 0x0 +.debug_frame 0x121b4 0x0 +.debug_info 0xce3d9a 0x0 +.debug_abbrev 0x27dc8 0x0 .debug_aranges 0x6810 0x0 -.debug_rnglists 0x4cb8 0x0 -.debug_line 0x754dd 0x0 -.debug_str 0x905a4 0x0 -.debug_loclists 0x293fd 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf03ee7 +.debug_rnglists 0x4cbe 0x0 +.debug_line 0x755a8 0x0 +.debug_str 0x9058d 0x0 +.debug_loclists 0x29470 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf056c3 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228300 + 228324 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_US_size.txt index 220428df28..ef94cfe1d8 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37328 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d328 -_zaf_cc_config 0x10 0x803d338 -_cc_handlers_v3 0x21c 0x803d348 -_zw_protocol_cmd_handlers 0x70 0x803d564 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5d4 -.ARM.exidx 0x8 0x803d604 -.copy.table 0xc 0x803d60c -.zero.table 0x0 0x803d618 +.text 0x37340 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d340 +_zaf_cc_config 0x10 0x803d350 +_cc_handlers_v3 0x21c 0x803d360 +_zw_protocol_cmd_handlers 0x70 0x803d57c +_zw_protocol_cmd_handlers_lr 0x30 0x803d5ec +.ARM.exidx 0x8 0x803d61c +.copy.table 0xc 0x803d624 +.zero.table 0x0 0x803d630 .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xab58 0x200015b4 text_application_ram 0x0 0x2000c10c .heap 0x800 0x2000c110 -.internal_storage 0x30000 0x803d618 -.zwave_nvm 0x0 0x806d618 -.nvm 0x8000 0x806d618 +.internal_storage 0x30000 0x803d630 +.zwave_nvm 0x0 0x806d630 +.nvm 0x8000 0x806d630 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x121c0 0x0 -.debug_info 0xce2682 0x0 -.debug_abbrev 0x27e3d 0x0 +.debug_frame 0x121b4 0x0 +.debug_info 0xce3d9a 0x0 +.debug_abbrev 0x27dc8 0x0 .debug_aranges 0x6810 0x0 -.debug_rnglists 0x4cb8 0x0 -.debug_line 0x754dd 0x0 -.debug_str 0x905ae 0x0 -.debug_loclists 0x293fd 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf03ef1 +.debug_rnglists 0x4cbe 0x0 +.debug_line 0x755a8 0x0 +.debug_str 0x90597 0x0 +.debug_loclists 0x29470 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf056cd The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228300 + 228324 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_EU_size.txt index c1be886383..6a43b34e83 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37b54 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803db54 -_zaf_cc_config 0x10 0x803db64 -_cc_handlers_v3 0x21c 0x803db74 -_zw_protocol_cmd_handlers 0x70 0x803dd90 -_zw_protocol_cmd_handlers_lr 0x30 0x803de00 -.ARM.exidx 0x8 0x803de30 -.copy.table 0xc 0x803de38 -.zero.table 0x0 0x803de44 +.text 0x37b6c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803db6c +_zaf_cc_config 0x10 0x803db7c +_cc_handlers_v3 0x21c 0x803db8c +_zw_protocol_cmd_handlers 0x70 0x803dda8 +_zw_protocol_cmd_handlers_lr 0x30 0x803de18 +.ARM.exidx 0x8 0x803de48 +.copy.table 0xc 0x803de50 +.zero.table 0x0 0x803de5c .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xacf8 0x200015b4 text_application_ram 0x0 0x2000c2ac .heap 0x800 0x2000c2b0 -.internal_storage 0x30000 0x803de44 -.zwave_nvm 0x0 0x806de44 -.nvm 0x8000 0x806de44 +.internal_storage 0x30000 0x803de5c +.zwave_nvm 0x0 0x806de5c +.nvm 0x8000 0x806de5c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12880 0x0 -.debug_info 0xce8caa 0x0 -.debug_abbrev 0x28900 0x0 +.debug_frame 0x12874 0x0 +.debug_info 0xcea3c2 0x0 +.debug_abbrev 0x2888b 0x0 .debug_aranges 0x6a00 0x0 -.debug_rnglists 0x4f7a 0x0 -.debug_line 0x78484 0x0 -.debug_str 0x9100e 0x0 -.debug_loclists 0x2cf4f 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf13a73 +.debug_rnglists 0x4f80 0x0 +.debug_line 0x78551 0x0 +.debug_str 0x90ff7 0x0 +.debug_loclists 0x2cfc2 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf15251 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230392 + 230416 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_US_LR_size.txt index 4377c9d2b3..bded9e4f95 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37b54 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803db54 -_zaf_cc_config 0x10 0x803db64 -_cc_handlers_v3 0x21c 0x803db74 -_zw_protocol_cmd_handlers 0x70 0x803dd90 -_zw_protocol_cmd_handlers_lr 0x30 0x803de00 -.ARM.exidx 0x8 0x803de30 -.copy.table 0xc 0x803de38 -.zero.table 0x0 0x803de44 +.text 0x37b6c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803db6c +_zaf_cc_config 0x10 0x803db7c +_cc_handlers_v3 0x21c 0x803db8c +_zw_protocol_cmd_handlers 0x70 0x803dda8 +_zw_protocol_cmd_handlers_lr 0x30 0x803de18 +.ARM.exidx 0x8 0x803de48 +.copy.table 0xc 0x803de50 +.zero.table 0x0 0x803de5c .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xacf8 0x200015b4 text_application_ram 0x0 0x2000c2ac .heap 0x800 0x2000c2b0 -.internal_storage 0x30000 0x803de44 -.zwave_nvm 0x0 0x806de44 -.nvm 0x8000 0x806de44 +.internal_storage 0x30000 0x803de5c +.zwave_nvm 0x0 0x806de5c +.nvm 0x8000 0x806de5c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12880 0x0 -.debug_info 0xce8caa 0x0 -.debug_abbrev 0x28900 0x0 +.debug_frame 0x12874 0x0 +.debug_info 0xcea3c2 0x0 +.debug_abbrev 0x2888b 0x0 .debug_aranges 0x6a00 0x0 -.debug_rnglists 0x4f7a 0x0 -.debug_line 0x78484 0x0 -.debug_str 0x91004 0x0 -.debug_loclists 0x2cf4f 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf13a69 +.debug_rnglists 0x4f80 0x0 +.debug_line 0x78551 0x0 +.debug_str 0x90fed 0x0 +.debug_loclists 0x2cfc2 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf15247 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230392 + 230416 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_US_size.txt index c1be886383..6a43b34e83 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37b54 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803db54 -_zaf_cc_config 0x10 0x803db64 -_cc_handlers_v3 0x21c 0x803db74 -_zw_protocol_cmd_handlers 0x70 0x803dd90 -_zw_protocol_cmd_handlers_lr 0x30 0x803de00 -.ARM.exidx 0x8 0x803de30 -.copy.table 0xc 0x803de38 -.zero.table 0x0 0x803de44 +.text 0x37b6c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803db6c +_zaf_cc_config 0x10 0x803db7c +_cc_handlers_v3 0x21c 0x803db8c +_zw_protocol_cmd_handlers 0x70 0x803dda8 +_zw_protocol_cmd_handlers_lr 0x30 0x803de18 +.ARM.exidx 0x8 0x803de48 +.copy.table 0xc 0x803de50 +.zero.table 0x0 0x803de5c .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xacf8 0x200015b4 text_application_ram 0x0 0x2000c2ac .heap 0x800 0x2000c2b0 -.internal_storage 0x30000 0x803de44 -.zwave_nvm 0x0 0x806de44 -.nvm 0x8000 0x806de44 +.internal_storage 0x30000 0x803de5c +.zwave_nvm 0x0 0x806de5c +.nvm 0x8000 0x806de5c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12880 0x0 -.debug_info 0xce8caa 0x0 -.debug_abbrev 0x28900 0x0 +.debug_frame 0x12874 0x0 +.debug_info 0xcea3c2 0x0 +.debug_abbrev 0x2888b 0x0 .debug_aranges 0x6a00 0x0 -.debug_rnglists 0x4f7a 0x0 -.debug_line 0x78484 0x0 -.debug_str 0x9100e 0x0 -.debug_loclists 0x2cf4f 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf13a73 +.debug_rnglists 0x4f80 0x0 +.debug_line 0x78551 0x0 +.debug_str 0x90ff7 0x0 +.debug_loclists 0x2cfc2 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf15251 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230392 + 230416 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_EU_size.txt index 50f08b5e71..e574a0bba0 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x308d4 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x308d4 -_zaf_cc_config 0x10 0x308e4 -_cc_handlers_v3 0x21c 0x308f4 -_zw_protocol_cmd_handlers 0x70 0x30b10 -_zw_protocol_cmd_handlers_lr 0x30 0x30b80 -.ARM.exidx 0x8 0x30bb0 -.copy.table 0xc 0x30bb8 -.zero.table 0x0 0x30bc4 +.text 0x308c8 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x308c8 +_zaf_cc_config 0x10 0x308d8 +_cc_handlers_v3 0x21c 0x308e8 +_zw_protocol_cmd_handlers 0x70 0x30b04 +_zw_protocol_cmd_handlers_lr 0x30 0x30b74 +.ARM.exidx 0x8 0x30ba4 +.copy.table 0xc 0x30bac +.zero.table 0x0 0x30bb8 .stack 0x1000 0x20000000 .data 0x430 0x20001000 .bss 0xa180 0x20001430 text_application_ram 0x0 0x2000b5b0 .heap 0x800 0x2000b5b0 -.internal_storage 0x3a000 0x30bc4 -.zwave_nvm 0x3000 0x6abc4 -.nvm 0x9000 0x6dbc4 +.internal_storage 0x3a000 0x30bb8 +.zwave_nvm 0x3000 0x6abb8 +.nvm 0x9000 0x6dbb8 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf738 0x0 -.debug_info 0xc9d3ee 0x0 -.debug_abbrev 0x22e46 0x0 -.debug_aranges 0x5ad0 0x0 -.debug_rnglists 0x3830 0x0 -.debug_line 0x61925 0x0 -.debug_str 0x8708b 0x0 -.debug_loclists 0x18bea 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe8f556 +.debug_frame 0xf70c 0x0 +.debug_info 0xc9d5c8 0x0 +.debug_abbrev 0x22e01 0x0 +.debug_aranges 0x5ac8 0x0 +.debug_rnglists 0x383f 0x0 +.debug_line 0x61935 0x0 +.debug_str 0x87053 0x0 +.debug_loclists 0x18bd6 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe8f65e The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 200692 + 200680 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_US_LR_size.txt index 4c18ffebfc..3eda7ea1c5 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x308d4 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x308d4 -_zaf_cc_config 0x10 0x308e4 -_cc_handlers_v3 0x21c 0x308f4 -_zw_protocol_cmd_handlers 0x70 0x30b10 -_zw_protocol_cmd_handlers_lr 0x30 0x30b80 -.ARM.exidx 0x8 0x30bb0 -.copy.table 0xc 0x30bb8 -.zero.table 0x0 0x30bc4 +.text 0x308c8 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x308c8 +_zaf_cc_config 0x10 0x308d8 +_cc_handlers_v3 0x21c 0x308e8 +_zw_protocol_cmd_handlers 0x70 0x30b04 +_zw_protocol_cmd_handlers_lr 0x30 0x30b74 +.ARM.exidx 0x8 0x30ba4 +.copy.table 0xc 0x30bac +.zero.table 0x0 0x30bb8 .stack 0x1000 0x20000000 .data 0x430 0x20001000 .bss 0xa180 0x20001430 text_application_ram 0x0 0x2000b5b0 .heap 0x800 0x2000b5b0 -.internal_storage 0x3a000 0x30bc4 -.zwave_nvm 0x3000 0x6abc4 -.nvm 0x9000 0x6dbc4 +.internal_storage 0x3a000 0x30bb8 +.zwave_nvm 0x3000 0x6abb8 +.nvm 0x9000 0x6dbb8 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf738 0x0 -.debug_info 0xc9d3ee 0x0 -.debug_abbrev 0x22e46 0x0 -.debug_aranges 0x5ad0 0x0 -.debug_rnglists 0x3830 0x0 -.debug_line 0x61925 0x0 -.debug_str 0x87081 0x0 -.debug_loclists 0x18bea 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe8f54c +.debug_frame 0xf70c 0x0 +.debug_info 0xc9d5c8 0x0 +.debug_abbrev 0x22e01 0x0 +.debug_aranges 0x5ac8 0x0 +.debug_rnglists 0x383f 0x0 +.debug_line 0x61935 0x0 +.debug_str 0x87049 0x0 +.debug_loclists 0x18bd6 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe8f654 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 200692 + 200680 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_US_size.txt index 50f08b5e71..e574a0bba0 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x308d4 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x308d4 -_zaf_cc_config 0x10 0x308e4 -_cc_handlers_v3 0x21c 0x308f4 -_zw_protocol_cmd_handlers 0x70 0x30b10 -_zw_protocol_cmd_handlers_lr 0x30 0x30b80 -.ARM.exidx 0x8 0x30bb0 -.copy.table 0xc 0x30bb8 -.zero.table 0x0 0x30bc4 +.text 0x308c8 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x308c8 +_zaf_cc_config 0x10 0x308d8 +_cc_handlers_v3 0x21c 0x308e8 +_zw_protocol_cmd_handlers 0x70 0x30b04 +_zw_protocol_cmd_handlers_lr 0x30 0x30b74 +.ARM.exidx 0x8 0x30ba4 +.copy.table 0xc 0x30bac +.zero.table 0x0 0x30bb8 .stack 0x1000 0x20000000 .data 0x430 0x20001000 .bss 0xa180 0x20001430 text_application_ram 0x0 0x2000b5b0 .heap 0x800 0x2000b5b0 -.internal_storage 0x3a000 0x30bc4 -.zwave_nvm 0x3000 0x6abc4 -.nvm 0x9000 0x6dbc4 +.internal_storage 0x3a000 0x30bb8 +.zwave_nvm 0x3000 0x6abb8 +.nvm 0x9000 0x6dbb8 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf738 0x0 -.debug_info 0xc9d3ee 0x0 -.debug_abbrev 0x22e46 0x0 -.debug_aranges 0x5ad0 0x0 -.debug_rnglists 0x3830 0x0 -.debug_line 0x61925 0x0 -.debug_str 0x8708b 0x0 -.debug_loclists 0x18bea 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe8f556 +.debug_frame 0xf70c 0x0 +.debug_info 0xc9d5c8 0x0 +.debug_abbrev 0x22e01 0x0 +.debug_aranges 0x5ac8 0x0 +.debug_rnglists 0x383f 0x0 +.debug_line 0x61935 0x0 +.debug_str 0x87053 0x0 +.debug_loclists 0x18bd6 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe8f65e The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 200692 + 200680 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4209A_REGION_US_LR_size.txt index 89fa62489f..2edc169308 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4209A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x3080c 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x3080c -_zaf_cc_config 0x10 0x3081c -_cc_handlers_v3 0x21c 0x3082c -_zw_protocol_cmd_handlers 0x70 0x30a48 -_zw_protocol_cmd_handlers_lr 0x30 0x30ab8 -.ARM.exidx 0x8 0x30ae8 -.copy.table 0xc 0x30af0 -.zero.table 0x0 0x30afc +.text 0x30820 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x30820 +_zaf_cc_config 0x10 0x30830 +_cc_handlers_v3 0x21c 0x30840 +_zw_protocol_cmd_handlers 0x70 0x30a5c +_zw_protocol_cmd_handlers_lr 0x30 0x30acc +.ARM.exidx 0x8 0x30afc +.copy.table 0xc 0x30b04 +.zero.table 0x0 0x30b10 .stack 0x1000 0x20000000 .data 0x430 0x20001000 .bss 0xa164 0x20001430 text_application_ram 0x0 0x2000b594 .heap 0x800 0x2000b598 -.internal_storage 0x3a000 0x30afc -.zwave_nvm 0x3000 0x6aafc -.nvm 0x9000 0x6dafc +.internal_storage 0x3a000 0x30b10 +.zwave_nvm 0x3000 0x6ab10 +.nvm 0x9000 0x6db10 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf908 0x0 -.debug_info 0xc9e9cf 0x0 -.debug_abbrev 0x23389 0x0 -.debug_aranges 0x5b70 0x0 -.debug_rnglists 0x38db 0x0 -.debug_line 0x62930 0x0 -.debug_str 0x873ad 0x0 -.debug_loclists 0x19287 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe92c7b +.debug_frame 0xf8dc 0x0 +.debug_info 0xc9eba9 0x0 +.debug_abbrev 0x23344 0x0 +.debug_aranges 0x5b68 0x0 +.debug_rnglists 0x38ea 0x0 +.debug_line 0x6294a 0x0 +.debug_str 0x87375 0x0 +.debug_loclists 0x19273 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe92dad The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 200492 + 200512 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4210A_REGION_US_LR_size.txt index d283c30f70..f91f7137d0 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4210A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x37864 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d864 -_zaf_cc_config 0x10 0x803d874 -_cc_handlers_v3 0x21c 0x803d884 -_zw_protocol_cmd_handlers 0x70 0x803daa0 -_zw_protocol_cmd_handlers_lr 0x30 0x803db10 -.ARM.exidx 0x8 0x803db40 -.copy.table 0xc 0x803db48 -.zero.table 0x0 0x803db54 +.text 0x3787c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d87c +_zaf_cc_config 0x10 0x803d88c +_cc_handlers_v3 0x21c 0x803d89c +_zw_protocol_cmd_handlers 0x70 0x803dab8 +_zw_protocol_cmd_handlers_lr 0x30 0x803db28 +.ARM.exidx 0x8 0x803db58 +.copy.table 0xc 0x803db60 +.zero.table 0x0 0x803db6c .stack 0x1000 0x20000000 .data 0x5b4 0x20001000 .bss 0xacf8 0x200015b4 text_application_ram 0x0 0x2000c2ac .heap 0x800 0x2000c2b0 -.internal_storage 0x30000 0x803db54 -.zwave_nvm 0x0 0x806db54 -.nvm 0x8000 0x806db54 +.internal_storage 0x30000 0x803db6c +.zwave_nvm 0x0 0x806db6c +.nvm 0x8000 0x806db6c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12858 0x0 -.debug_info 0xce82a5 0x0 -.debug_abbrev 0x28824 0x0 +.debug_frame 0x1284c 0x0 +.debug_info 0xce99bd 0x0 +.debug_abbrev 0x287af 0x0 .debug_aranges 0x69b0 0x0 -.debug_rnglists 0x4f62 0x0 -.debug_line 0x78585 0x0 -.debug_str 0x90a3c 0x0 -.debug_loclists 0x2cf46 0x0 -.debug_loc 0x2c495 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xf12714 +.debug_rnglists 0x4f68 0x0 +.debug_line 0x7865a 0x0 +.debug_str 0x90a25 0x0 +.debug_loclists 0x2cfb9 0x0 +.debug_loc 0x2c45d 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xf13efa The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 229640 + 229664 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400B_REGION_EU_size.txt index fad77f3596..e8b26214d2 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400B_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x383e4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e3e4 -_zaf_cc_config 0x10 0x803e3f4 -_cc_handlers_v3 0x21c 0x803e404 -_zw_protocol_cmd_handlers 0x70 0x803e620 -_zw_protocol_cmd_handlers_lr 0x30 0x803e690 -.ARM.exidx 0x8 0x803e6c0 -.copy.table 0xc 0x803e6c8 -.zero.table 0x0 0x803e6d4 +.text 0x383fc 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e3fc +_zaf_cc_config 0x10 0x803e40c +_cc_handlers_v3 0x21c 0x803e41c +_zw_protocol_cmd_handlers 0x70 0x803e638 +_zw_protocol_cmd_handlers_lr 0x30 0x803e6a8 +.ARM.exidx 0x8 0x803e6d8 +.copy.table 0xc 0x803e6e0 +.zero.table 0x0 0x803e6ec .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xac60 0x200015b0 text_application_ram 0x0 0x2000c210 .heap 0x800 0x2000c210 -.internal_storage 0x30000 0x803e6d4 -.zwave_nvm 0x0 0x806e6d4 -.nvm 0x8000 0x806e6d4 +.internal_storage 0x30000 0x803e6ec +.zwave_nvm 0x0 0x806e6ec +.nvm 0x8000 0x806e6ec .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1291c 0x0 -.debug_info 0xcecc5e 0x0 -.debug_abbrev 0x28b6b 0x0 +.debug_frame 0x12910 0x0 +.debug_info 0xcee37a 0x0 +.debug_abbrev 0x28af6 0x0 .debug_aranges 0x6a30 0x0 -.debug_rnglists 0x4fb7 0x0 -.debug_line 0x78954 0x0 -.debug_str 0x9232b 0x0 -.debug_loclists 0x2d475 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf1a19e +.debug_rnglists 0x4fbd 0x0 +.debug_line 0x78a29 0x0 +.debug_str 0x92314 0x0 +.debug_loclists 0x2d4e8 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf1b988 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 232580 + 232604 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400B_REGION_US_LR_size.txt index 919e99c6bd..5ea4ba56f7 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x383e4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e3e4 -_zaf_cc_config 0x10 0x803e3f4 -_cc_handlers_v3 0x21c 0x803e404 -_zw_protocol_cmd_handlers 0x70 0x803e620 -_zw_protocol_cmd_handlers_lr 0x30 0x803e690 -.ARM.exidx 0x8 0x803e6c0 -.copy.table 0xc 0x803e6c8 -.zero.table 0x0 0x803e6d4 +.text 0x383fc 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e3fc +_zaf_cc_config 0x10 0x803e40c +_cc_handlers_v3 0x21c 0x803e41c +_zw_protocol_cmd_handlers 0x70 0x803e638 +_zw_protocol_cmd_handlers_lr 0x30 0x803e6a8 +.ARM.exidx 0x8 0x803e6d8 +.copy.table 0xc 0x803e6e0 +.zero.table 0x0 0x803e6ec .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xac60 0x200015b0 text_application_ram 0x0 0x2000c210 .heap 0x800 0x2000c210 -.internal_storage 0x30000 0x803e6d4 -.zwave_nvm 0x0 0x806e6d4 -.nvm 0x8000 0x806e6d4 +.internal_storage 0x30000 0x803e6ec +.zwave_nvm 0x0 0x806e6ec +.nvm 0x8000 0x806e6ec .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1291c 0x0 -.debug_info 0xcecc5e 0x0 -.debug_abbrev 0x28b6b 0x0 +.debug_frame 0x12910 0x0 +.debug_info 0xcee37a 0x0 +.debug_abbrev 0x28af6 0x0 .debug_aranges 0x6a30 0x0 -.debug_rnglists 0x4fb7 0x0 -.debug_line 0x78954 0x0 -.debug_str 0x92321 0x0 -.debug_loclists 0x2d475 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf1a194 +.debug_rnglists 0x4fbd 0x0 +.debug_line 0x78a29 0x0 +.debug_str 0x9230a 0x0 +.debug_loclists 0x2d4e8 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf1b97e The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 232580 + 232604 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400B_REGION_US_size.txt index fad77f3596..e8b26214d2 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400B_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x383e4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e3e4 -_zaf_cc_config 0x10 0x803e3f4 -_cc_handlers_v3 0x21c 0x803e404 -_zw_protocol_cmd_handlers 0x70 0x803e620 -_zw_protocol_cmd_handlers_lr 0x30 0x803e690 -.ARM.exidx 0x8 0x803e6c0 -.copy.table 0xc 0x803e6c8 -.zero.table 0x0 0x803e6d4 +.text 0x383fc 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e3fc +_zaf_cc_config 0x10 0x803e40c +_cc_handlers_v3 0x21c 0x803e41c +_zw_protocol_cmd_handlers 0x70 0x803e638 +_zw_protocol_cmd_handlers_lr 0x30 0x803e6a8 +.ARM.exidx 0x8 0x803e6d8 +.copy.table 0xc 0x803e6e0 +.zero.table 0x0 0x803e6ec .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xac60 0x200015b0 text_application_ram 0x0 0x2000c210 .heap 0x800 0x2000c210 -.internal_storage 0x30000 0x803e6d4 -.zwave_nvm 0x0 0x806e6d4 -.nvm 0x8000 0x806e6d4 +.internal_storage 0x30000 0x803e6ec +.zwave_nvm 0x0 0x806e6ec +.nvm 0x8000 0x806e6ec .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1291c 0x0 -.debug_info 0xcecc5e 0x0 -.debug_abbrev 0x28b6b 0x0 +.debug_frame 0x12910 0x0 +.debug_info 0xcee37a 0x0 +.debug_abbrev 0x28af6 0x0 .debug_aranges 0x6a30 0x0 -.debug_rnglists 0x4fb7 0x0 -.debug_line 0x78954 0x0 -.debug_str 0x9232b 0x0 -.debug_loclists 0x2d475 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf1a19e +.debug_rnglists 0x4fbd 0x0 +.debug_line 0x78a29 0x0 +.debug_str 0x92314 0x0 +.debug_loclists 0x2d4e8 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf1b988 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 232580 + 232604 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400C_REGION_EU_size.txt index da2091f018..d99884c0b7 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x383e4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e3e4 -_zaf_cc_config 0x10 0x803e3f4 -_cc_handlers_v3 0x21c 0x803e404 -_zw_protocol_cmd_handlers 0x70 0x803e620 -_zw_protocol_cmd_handlers_lr 0x30 0x803e690 -.ARM.exidx 0x8 0x803e6c0 -.copy.table 0xc 0x803e6c8 -.zero.table 0x0 0x803e6d4 +.text 0x383fc 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e3fc +_zaf_cc_config 0x10 0x803e40c +_cc_handlers_v3 0x21c 0x803e41c +_zw_protocol_cmd_handlers 0x70 0x803e638 +_zw_protocol_cmd_handlers_lr 0x30 0x803e6a8 +.ARM.exidx 0x8 0x803e6d8 +.copy.table 0xc 0x803e6e0 +.zero.table 0x0 0x803e6ec .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xac60 0x200015b0 text_application_ram 0x0 0x2000c210 .heap 0x800 0x2000c210 -.internal_storage 0x30000 0x803e6d4 -.zwave_nvm 0x0 0x806e6d4 -.nvm 0x8000 0x806e6d4 +.internal_storage 0x30000 0x803e6ec +.zwave_nvm 0x0 0x806e6ec +.nvm 0x8000 0x806e6ec .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12930 0x0 -.debug_info 0xcecbed 0x0 -.debug_abbrev 0x28b75 0x0 +.debug_frame 0x12924 0x0 +.debug_info 0xcee309 0x0 +.debug_abbrev 0x28b00 0x0 .debug_aranges 0x6a38 0x0 -.debug_rnglists 0x4fe0 0x0 -.debug_line 0x78949 0x0 -.debug_str 0x9232b 0x0 -.debug_loclists 0x2d441 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf1a13d +.debug_rnglists 0x4fe6 0x0 +.debug_line 0x78a1e 0x0 +.debug_str 0x92314 0x0 +.debug_loclists 0x2d4b4 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf1b927 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 232580 + 232604 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400C_REGION_US_LR_size.txt index d66a53d19e..64d1c2d348 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x383e4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e3e4 -_zaf_cc_config 0x10 0x803e3f4 -_cc_handlers_v3 0x21c 0x803e404 -_zw_protocol_cmd_handlers 0x70 0x803e620 -_zw_protocol_cmd_handlers_lr 0x30 0x803e690 -.ARM.exidx 0x8 0x803e6c0 -.copy.table 0xc 0x803e6c8 -.zero.table 0x0 0x803e6d4 +.text 0x383fc 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e3fc +_zaf_cc_config 0x10 0x803e40c +_cc_handlers_v3 0x21c 0x803e41c +_zw_protocol_cmd_handlers 0x70 0x803e638 +_zw_protocol_cmd_handlers_lr 0x30 0x803e6a8 +.ARM.exidx 0x8 0x803e6d8 +.copy.table 0xc 0x803e6e0 +.zero.table 0x0 0x803e6ec .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xac60 0x200015b0 text_application_ram 0x0 0x2000c210 .heap 0x800 0x2000c210 -.internal_storage 0x30000 0x803e6d4 -.zwave_nvm 0x0 0x806e6d4 -.nvm 0x8000 0x806e6d4 +.internal_storage 0x30000 0x803e6ec +.zwave_nvm 0x0 0x806e6ec +.nvm 0x8000 0x806e6ec .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12930 0x0 -.debug_info 0xcecbed 0x0 -.debug_abbrev 0x28b75 0x0 +.debug_frame 0x12924 0x0 +.debug_info 0xcee309 0x0 +.debug_abbrev 0x28b00 0x0 .debug_aranges 0x6a38 0x0 -.debug_rnglists 0x4fe0 0x0 -.debug_line 0x78949 0x0 -.debug_str 0x92321 0x0 -.debug_loclists 0x2d441 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf1a133 +.debug_rnglists 0x4fe6 0x0 +.debug_line 0x78a1e 0x0 +.debug_str 0x9230a 0x0 +.debug_loclists 0x2d4b4 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf1b91d The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 232580 + 232604 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400C_REGION_US_size.txt index da2091f018..d99884c0b7 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4400C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x383e4 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e3e4 -_zaf_cc_config 0x10 0x803e3f4 -_cc_handlers_v3 0x21c 0x803e404 -_zw_protocol_cmd_handlers 0x70 0x803e620 -_zw_protocol_cmd_handlers_lr 0x30 0x803e690 -.ARM.exidx 0x8 0x803e6c0 -.copy.table 0xc 0x803e6c8 -.zero.table 0x0 0x803e6d4 +.text 0x383fc 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e3fc +_zaf_cc_config 0x10 0x803e40c +_cc_handlers_v3 0x21c 0x803e41c +_zw_protocol_cmd_handlers 0x70 0x803e638 +_zw_protocol_cmd_handlers_lr 0x30 0x803e6a8 +.ARM.exidx 0x8 0x803e6d8 +.copy.table 0xc 0x803e6e0 +.zero.table 0x0 0x803e6ec .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xac60 0x200015b0 text_application_ram 0x0 0x2000c210 .heap 0x800 0x2000c210 -.internal_storage 0x30000 0x803e6d4 -.zwave_nvm 0x0 0x806e6d4 -.nvm 0x8000 0x806e6d4 +.internal_storage 0x30000 0x803e6ec +.zwave_nvm 0x0 0x806e6ec +.nvm 0x8000 0x806e6ec .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12930 0x0 -.debug_info 0xcecbed 0x0 -.debug_abbrev 0x28b75 0x0 +.debug_frame 0x12924 0x0 +.debug_info 0xcee309 0x0 +.debug_abbrev 0x28b00 0x0 .debug_aranges 0x6a38 0x0 -.debug_rnglists 0x4fe0 0x0 -.debug_line 0x78949 0x0 -.debug_str 0x9232b 0x0 -.debug_loclists 0x2d441 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xf1a13d +.debug_rnglists 0x4fe6 0x0 +.debug_line 0x78a1e 0x0 +.debug_str 0x92314 0x0 +.debug_loclists 0x2d4b4 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xf1b927 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 232580 + 232604 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4401B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4401B_REGION_US_LR_size.txt index ba897b51bb..336ee2e977 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4401B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4401B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x38404 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e404 -_zaf_cc_config 0x10 0x803e414 -_cc_handlers_v3 0x21c 0x803e424 -_zw_protocol_cmd_handlers 0x70 0x803e640 -_zw_protocol_cmd_handlers_lr 0x30 0x803e6b0 -.ARM.exidx 0x8 0x803e6e0 -.copy.table 0xc 0x803e6e8 -.zero.table 0x0 0x803e6f4 +.text 0x3843c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e43c +_zaf_cc_config 0x10 0x803e44c +_cc_handlers_v3 0x21c 0x803e45c +_zw_protocol_cmd_handlers 0x70 0x803e678 +_zw_protocol_cmd_handlers_lr 0x30 0x803e6e8 +.ARM.exidx 0x8 0x803e718 +.copy.table 0xc 0x803e720 +.zero.table 0x0 0x803e72c .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xac60 0x200015b0 text_application_ram 0x0 0x2000c210 .heap 0x800 0x2000c210 -.internal_storage 0x30000 0x803e6f4 -.zwave_nvm 0x0 0x806e6f4 -.nvm 0x8000 0x806e6f4 +.internal_storage 0x30000 0x803e72c +.zwave_nvm 0x0 0x806e72c +.nvm 0x8000 0x806e72c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12924 0x0 -.debug_info 0xcecc28 0x0 -.debug_abbrev 0x28b6b 0x0 +.debug_frame 0x12918 0x0 +.debug_info 0xcee344 0x0 +.debug_abbrev 0x28af6 0x0 .debug_aranges 0x6a30 0x0 -.debug_rnglists 0x4fb7 0x0 -.debug_line 0x7892b 0x0 -.debug_str 0x92321 0x0 -.debug_loclists 0x2d475 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xf1a12a +.debug_rnglists 0x4fbd 0x0 +.debug_line 0x78a00 0x0 +.debug_str 0x9230a 0x0 +.debug_loclists 0x2d4e8 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xf1b934 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 232612 + 232668 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4401C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4401C_REGION_EU_size.txt index 7111535091..ee67202e1e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4401C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4401C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x38404 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e404 -_zaf_cc_config 0x10 0x803e414 -_cc_handlers_v3 0x21c 0x803e424 -_zw_protocol_cmd_handlers 0x70 0x803e640 -_zw_protocol_cmd_handlers_lr 0x30 0x803e6b0 -.ARM.exidx 0x8 0x803e6e0 -.copy.table 0xc 0x803e6e8 -.zero.table 0x0 0x803e6f4 +.text 0x3843c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e43c +_zaf_cc_config 0x10 0x803e44c +_cc_handlers_v3 0x21c 0x803e45c +_zw_protocol_cmd_handlers 0x70 0x803e678 +_zw_protocol_cmd_handlers_lr 0x30 0x803e6e8 +.ARM.exidx 0x8 0x803e718 +.copy.table 0xc 0x803e720 +.zero.table 0x0 0x803e72c .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xac60 0x200015b0 text_application_ram 0x0 0x2000c210 .heap 0x800 0x2000c210 -.internal_storage 0x30000 0x803e6f4 -.zwave_nvm 0x0 0x806e6f4 -.nvm 0x8000 0x806e6f4 +.internal_storage 0x30000 0x803e72c +.zwave_nvm 0x0 0x806e72c +.nvm 0x8000 0x806e72c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12938 0x0 -.debug_info 0xcecbb7 0x0 -.debug_abbrev 0x28b75 0x0 +.debug_frame 0x1292c 0x0 +.debug_info 0xcee2d3 0x0 +.debug_abbrev 0x28b00 0x0 .debug_aranges 0x6a38 0x0 -.debug_rnglists 0x4fe0 0x0 -.debug_line 0x78920 0x0 -.debug_str 0x9232b 0x0 -.debug_loclists 0x2d441 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xf1a0d3 +.debug_rnglists 0x4fe6 0x0 +.debug_line 0x789f5 0x0 +.debug_str 0x92314 0x0 +.debug_loclists 0x2d4b4 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xf1b8dd The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 232612 + 232668 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4401C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4401C_REGION_US_LR_size.txt index dc89fd39be..d638425c31 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4401C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4401C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x38404 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e404 -_zaf_cc_config 0x10 0x803e414 -_cc_handlers_v3 0x21c 0x803e424 -_zw_protocol_cmd_handlers 0x70 0x803e640 -_zw_protocol_cmd_handlers_lr 0x30 0x803e6b0 -.ARM.exidx 0x8 0x803e6e0 -.copy.table 0xc 0x803e6e8 -.zero.table 0x0 0x803e6f4 +.text 0x3843c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e43c +_zaf_cc_config 0x10 0x803e44c +_cc_handlers_v3 0x21c 0x803e45c +_zw_protocol_cmd_handlers 0x70 0x803e678 +_zw_protocol_cmd_handlers_lr 0x30 0x803e6e8 +.ARM.exidx 0x8 0x803e718 +.copy.table 0xc 0x803e720 +.zero.table 0x0 0x803e72c .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xac60 0x200015b0 text_application_ram 0x0 0x2000c210 .heap 0x800 0x2000c210 -.internal_storage 0x30000 0x803e6f4 -.zwave_nvm 0x0 0x806e6f4 -.nvm 0x8000 0x806e6f4 +.internal_storage 0x30000 0x803e72c +.zwave_nvm 0x0 0x806e72c +.nvm 0x8000 0x806e72c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12938 0x0 -.debug_info 0xcecbb7 0x0 -.debug_abbrev 0x28b75 0x0 +.debug_frame 0x1292c 0x0 +.debug_info 0xcee2d3 0x0 +.debug_abbrev 0x28b00 0x0 .debug_aranges 0x6a38 0x0 -.debug_rnglists 0x4fe0 0x0 -.debug_line 0x78920 0x0 -.debug_str 0x92321 0x0 -.debug_loclists 0x2d441 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xf1a0c9 +.debug_rnglists 0x4fe6 0x0 +.debug_line 0x789f5 0x0 +.debug_str 0x9230a 0x0 +.debug_loclists 0x2d4b4 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xf1b8d3 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 232612 + 232668 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4401C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4401C_REGION_US_size.txt index 7111535091..ee67202e1e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4401C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4401C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x38404 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803e404 -_zaf_cc_config 0x10 0x803e414 -_cc_handlers_v3 0x21c 0x803e424 -_zw_protocol_cmd_handlers 0x70 0x803e640 -_zw_protocol_cmd_handlers_lr 0x30 0x803e6b0 -.ARM.exidx 0x8 0x803e6e0 -.copy.table 0xc 0x803e6e8 -.zero.table 0x0 0x803e6f4 +.text 0x3843c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803e43c +_zaf_cc_config 0x10 0x803e44c +_cc_handlers_v3 0x21c 0x803e45c +_zw_protocol_cmd_handlers 0x70 0x803e678 +_zw_protocol_cmd_handlers_lr 0x30 0x803e6e8 +.ARM.exidx 0x8 0x803e718 +.copy.table 0xc 0x803e720 +.zero.table 0x0 0x803e72c .stack 0x1000 0x20000000 .data 0x5b0 0x20001000 .bss 0xac60 0x200015b0 text_application_ram 0x0 0x2000c210 .heap 0x800 0x2000c210 -.internal_storage 0x30000 0x803e6f4 -.zwave_nvm 0x0 0x806e6f4 -.nvm 0x8000 0x806e6f4 +.internal_storage 0x30000 0x803e72c +.zwave_nvm 0x0 0x806e72c +.nvm 0x8000 0x806e72c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12938 0x0 -.debug_info 0xcecbb7 0x0 -.debug_abbrev 0x28b75 0x0 +.debug_frame 0x1292c 0x0 +.debug_info 0xcee2d3 0x0 +.debug_abbrev 0x28b00 0x0 .debug_aranges 0x6a38 0x0 -.debug_rnglists 0x4fe0 0x0 -.debug_line 0x78920 0x0 -.debug_str 0x9232b 0x0 -.debug_loclists 0x2d441 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xf1a0d3 +.debug_rnglists 0x4fe6 0x0 +.debug_line 0x789f5 0x0 +.debug_str 0x92314 0x0 +.debug_loclists 0x2d4b4 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xf1b8dd The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 232612 + 232668 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_EU_size.txt index 93172c521f..e1c03314b8 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x36af8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803caf8 -_zaf_cc_config 0x10 0x803cb08 -_cc_handlers_v3 0x1f8 0x803cb18 -_zw_protocol_cmd_handlers 0x70 0x803cd10 -_zw_protocol_cmd_handlers_lr 0x30 0x803cd80 -.ARM.exidx 0x8 0x803cdb0 -.copy.table 0xc 0x803cdb8 -.zero.table 0x0 0x803cdc4 +.text 0x36b10 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cb10 +_zaf_cc_config 0x10 0x803cb20 +_cc_handlers_v3 0x1f8 0x803cb30 +_zw_protocol_cmd_handlers 0x70 0x803cd28 +_zw_protocol_cmd_handlers_lr 0x30 0x803cd98 +.ARM.exidx 0x8 0x803cdc8 +.copy.table 0xc 0x803cdd0 +.zero.table 0x0 0x803cddc .stack 0x1000 0x20000000 .data 0x610 0x20001000 .bss 0xaa98 0x20001610 text_application_ram 0x0 0x2000c0a8 .heap 0x800 0x2000c0a8 -.internal_storage 0x30000 0x803cdc4 -.zwave_nvm 0x0 0x806cdc4 -.nvm 0x8000 0x806cdc4 +.internal_storage 0x30000 0x803cddc +.zwave_nvm 0x0 0x806cddc +.nvm 0x8000 0x806cddc .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x120dc 0x0 -.debug_info 0xc7aa96 0x0 -.debug_abbrev 0x27181 0x0 -.debug_loclists 0x2bcc9 0x0 +.debug_frame 0x120d0 0x0 +.debug_info 0xc7c1ae 0x0 +.debug_abbrev 0x2710c 0x0 +.debug_loclists 0x2bd3c 0x0 .debug_aranges 0x66c0 0x0 -.debug_rnglists 0x4c57 0x0 -.debug_line 0x74b8a 0x0 -.debug_str 0x8e5bf 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe9aa86 +.debug_rnglists 0x4c5d 0x0 +.debug_line 0x74c57 0x0 +.debug_str 0x8e5a8 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe9c264 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 226260 + 226284 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_US_LR_size.txt index 098cbf2f55..044df6a06e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x36af8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803caf8 -_zaf_cc_config 0x10 0x803cb08 -_cc_handlers_v3 0x1f8 0x803cb18 -_zw_protocol_cmd_handlers 0x70 0x803cd10 -_zw_protocol_cmd_handlers_lr 0x30 0x803cd80 -.ARM.exidx 0x8 0x803cdb0 -.copy.table 0xc 0x803cdb8 -.zero.table 0x0 0x803cdc4 +.text 0x36b10 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cb10 +_zaf_cc_config 0x10 0x803cb20 +_cc_handlers_v3 0x1f8 0x803cb30 +_zw_protocol_cmd_handlers 0x70 0x803cd28 +_zw_protocol_cmd_handlers_lr 0x30 0x803cd98 +.ARM.exidx 0x8 0x803cdc8 +.copy.table 0xc 0x803cdd0 +.zero.table 0x0 0x803cddc .stack 0x1000 0x20000000 .data 0x610 0x20001000 .bss 0xaa98 0x20001610 text_application_ram 0x0 0x2000c0a8 .heap 0x800 0x2000c0a8 -.internal_storage 0x30000 0x803cdc4 -.zwave_nvm 0x0 0x806cdc4 -.nvm 0x8000 0x806cdc4 +.internal_storage 0x30000 0x803cddc +.zwave_nvm 0x0 0x806cddc +.nvm 0x8000 0x806cddc .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x120dc 0x0 -.debug_info 0xc7aa96 0x0 -.debug_abbrev 0x27181 0x0 -.debug_loclists 0x2bcc9 0x0 +.debug_frame 0x120d0 0x0 +.debug_info 0xc7c1ae 0x0 +.debug_abbrev 0x2710c 0x0 +.debug_loclists 0x2bd3c 0x0 .debug_aranges 0x66c0 0x0 -.debug_rnglists 0x4c57 0x0 -.debug_line 0x74b8a 0x0 -.debug_str 0x8e5b5 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe9aa7c +.debug_rnglists 0x4c5d 0x0 +.debug_line 0x74c57 0x0 +.debug_str 0x8e59e 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe9c25a The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 226260 + 226284 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_US_size.txt index 93172c521f..e1c03314b8 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x36af8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803caf8 -_zaf_cc_config 0x10 0x803cb08 -_cc_handlers_v3 0x1f8 0x803cb18 -_zw_protocol_cmd_handlers 0x70 0x803cd10 -_zw_protocol_cmd_handlers_lr 0x30 0x803cd80 -.ARM.exidx 0x8 0x803cdb0 -.copy.table 0xc 0x803cdb8 -.zero.table 0x0 0x803cdc4 +.text 0x36b10 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cb10 +_zaf_cc_config 0x10 0x803cb20 +_cc_handlers_v3 0x1f8 0x803cb30 +_zw_protocol_cmd_handlers 0x70 0x803cd28 +_zw_protocol_cmd_handlers_lr 0x30 0x803cd98 +.ARM.exidx 0x8 0x803cdc8 +.copy.table 0xc 0x803cdd0 +.zero.table 0x0 0x803cddc .stack 0x1000 0x20000000 .data 0x610 0x20001000 .bss 0xaa98 0x20001610 text_application_ram 0x0 0x2000c0a8 .heap 0x800 0x2000c0a8 -.internal_storage 0x30000 0x803cdc4 -.zwave_nvm 0x0 0x806cdc4 -.nvm 0x8000 0x806cdc4 +.internal_storage 0x30000 0x803cddc +.zwave_nvm 0x0 0x806cddc +.nvm 0x8000 0x806cddc .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x120dc 0x0 -.debug_info 0xc7aa96 0x0 -.debug_abbrev 0x27181 0x0 -.debug_loclists 0x2bcc9 0x0 +.debug_frame 0x120d0 0x0 +.debug_info 0xc7c1ae 0x0 +.debug_abbrev 0x2710c 0x0 +.debug_loclists 0x2bd3c 0x0 .debug_aranges 0x66c0 0x0 -.debug_rnglists 0x4c57 0x0 -.debug_line 0x74b8a 0x0 -.debug_str 0x8e5bf 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe9aa86 +.debug_rnglists 0x4c5d 0x0 +.debug_line 0x74c57 0x0 +.debug_str 0x8e5a8 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe9c264 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 226260 + 226284 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2705A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2705A_REGION_EU_size.txt index d4e3dea354..f5bf70e06a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2705A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2705A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x36f28 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803cf28 -_zaf_cc_config 0x10 0x803cf38 -_cc_handlers_v3 0x1f8 0x803cf48 -_zw_protocol_cmd_handlers 0x70 0x803d140 -_zw_protocol_cmd_handlers_lr 0x30 0x803d1b0 -.ARM.exidx 0x8 0x803d1e0 -.copy.table 0xc 0x803d1e8 -.zero.table 0x0 0x803d1f4 +.text 0x36f40 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cf40 +_zaf_cc_config 0x10 0x803cf50 +_cc_handlers_v3 0x1f8 0x803cf60 +_zw_protocol_cmd_handlers 0x70 0x803d158 +_zw_protocol_cmd_handlers_lr 0x30 0x803d1c8 +.ARM.exidx 0x8 0x803d1f8 +.copy.table 0xc 0x803d200 +.zero.table 0x0 0x803d20c .stack 0x1000 0x20000000 .data 0x60c 0x20001000 .bss 0xaa04 0x2000160c text_application_ram 0x0 0x2000c010 .heap 0x800 0x2000c010 -.internal_storage 0x30000 0x803d1f4 -.zwave_nvm 0x0 0x806d1f4 -.nvm 0x8000 0x806d1f4 +.internal_storage 0x30000 0x803d20c +.zwave_nvm 0x0 0x806d20c +.nvm 0x8000 0x806d20c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11edc 0x0 -.debug_info 0xc771cd 0x0 -.debug_abbrev 0x26bd6 0x0 -.debug_loclists 0x2ba8d 0x0 +.debug_frame 0x11ed0 0x0 +.debug_info 0xc788e9 0x0 +.debug_abbrev 0x26b61 0x0 +.debug_loclists 0x2bb00 0x0 .debug_aranges 0x65e0 0x0 -.debug_rnglists 0x4b94 0x0 -.debug_line 0x73bd1 0x0 -.debug_str 0x8ea73 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe95dc2 +.debug_rnglists 0x4b9a 0x0 +.debug_line 0x73ca6 0x0 +.debug_str 0x8ea5c 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe975ac The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 227328 + 227352 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2705A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2705A_REGION_US_LR_size.txt index 7094380e03..cf3231c2bc 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2705A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2705A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x36f28 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803cf28 -_zaf_cc_config 0x10 0x803cf38 -_cc_handlers_v3 0x1f8 0x803cf48 -_zw_protocol_cmd_handlers 0x70 0x803d140 -_zw_protocol_cmd_handlers_lr 0x30 0x803d1b0 -.ARM.exidx 0x8 0x803d1e0 -.copy.table 0xc 0x803d1e8 -.zero.table 0x0 0x803d1f4 +.text 0x36f40 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cf40 +_zaf_cc_config 0x10 0x803cf50 +_cc_handlers_v3 0x1f8 0x803cf60 +_zw_protocol_cmd_handlers 0x70 0x803d158 +_zw_protocol_cmd_handlers_lr 0x30 0x803d1c8 +.ARM.exidx 0x8 0x803d1f8 +.copy.table 0xc 0x803d200 +.zero.table 0x0 0x803d20c .stack 0x1000 0x20000000 .data 0x60c 0x20001000 .bss 0xaa04 0x2000160c text_application_ram 0x0 0x2000c010 .heap 0x800 0x2000c010 -.internal_storage 0x30000 0x803d1f4 -.zwave_nvm 0x0 0x806d1f4 -.nvm 0x8000 0x806d1f4 +.internal_storage 0x30000 0x803d20c +.zwave_nvm 0x0 0x806d20c +.nvm 0x8000 0x806d20c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11edc 0x0 -.debug_info 0xc771cd 0x0 -.debug_abbrev 0x26bd6 0x0 -.debug_loclists 0x2ba8d 0x0 +.debug_frame 0x11ed0 0x0 +.debug_info 0xc788e9 0x0 +.debug_abbrev 0x26b61 0x0 +.debug_loclists 0x2bb00 0x0 .debug_aranges 0x65e0 0x0 -.debug_rnglists 0x4b94 0x0 -.debug_line 0x73bd1 0x0 -.debug_str 0x8ea69 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe95db8 +.debug_rnglists 0x4b9a 0x0 +.debug_line 0x73ca6 0x0 +.debug_str 0x8ea52 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe975a2 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 227328 + 227352 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2705A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2705A_REGION_US_size.txt index d4e3dea354..f5bf70e06a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2705A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2705A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x36f28 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803cf28 -_zaf_cc_config 0x10 0x803cf38 -_cc_handlers_v3 0x1f8 0x803cf48 -_zw_protocol_cmd_handlers 0x70 0x803d140 -_zw_protocol_cmd_handlers_lr 0x30 0x803d1b0 -.ARM.exidx 0x8 0x803d1e0 -.copy.table 0xc 0x803d1e8 -.zero.table 0x0 0x803d1f4 +.text 0x36f40 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cf40 +_zaf_cc_config 0x10 0x803cf50 +_cc_handlers_v3 0x1f8 0x803cf60 +_zw_protocol_cmd_handlers 0x70 0x803d158 +_zw_protocol_cmd_handlers_lr 0x30 0x803d1c8 +.ARM.exidx 0x8 0x803d1f8 +.copy.table 0xc 0x803d200 +.zero.table 0x0 0x803d20c .stack 0x1000 0x20000000 .data 0x60c 0x20001000 .bss 0xaa04 0x2000160c text_application_ram 0x0 0x2000c010 .heap 0x800 0x2000c010 -.internal_storage 0x30000 0x803d1f4 -.zwave_nvm 0x0 0x806d1f4 -.nvm 0x8000 0x806d1f4 +.internal_storage 0x30000 0x803d20c +.zwave_nvm 0x0 0x806d20c +.nvm 0x8000 0x806d20c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11edc 0x0 -.debug_info 0xc771cd 0x0 -.debug_abbrev 0x26bd6 0x0 -.debug_loclists 0x2ba8d 0x0 +.debug_frame 0x11ed0 0x0 +.debug_info 0xc788e9 0x0 +.debug_abbrev 0x26b61 0x0 +.debug_loclists 0x2bb00 0x0 .debug_aranges 0x65e0 0x0 -.debug_rnglists 0x4b94 0x0 -.debug_line 0x73bd1 0x0 -.debug_str 0x8ea73 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe95dc2 +.debug_rnglists 0x4b9a 0x0 +.debug_line 0x73ca6 0x0 +.debug_str 0x8ea5c 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe975ac The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 227328 + 227352 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_EU_size.txt index f76f7078d2..41395e581b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x2fb14 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2fb14 -_zaf_cc_config 0x10 0x2fb24 -_cc_handlers_v3 0x1f8 0x2fb34 -_zw_protocol_cmd_handlers 0x70 0x2fd2c -_zw_protocol_cmd_handlers_lr 0x30 0x2fd9c -.ARM.exidx 0x8 0x2fdcc -.copy.table 0xc 0x2fdd4 -.zero.table 0x0 0x2fde0 +.text 0x2fb08 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2fb08 +_zaf_cc_config 0x10 0x2fb18 +_cc_handlers_v3 0x1f8 0x2fb28 +_zw_protocol_cmd_handlers 0x70 0x2fd20 +_zw_protocol_cmd_handlers_lr 0x30 0x2fd90 +.ARM.exidx 0x8 0x2fdc0 +.copy.table 0xc 0x2fdc8 +.zero.table 0x0 0x2fdd4 .stack 0x1000 0x20000000 .data 0x48c 0x20001000 .bss 0x9f24 0x2000148c text_application_ram 0x0 0x2000b3b0 .heap 0x800 0x2000b3b0 -.internal_storage 0x3a000 0x2fde0 -.zwave_nvm 0x3000 0x69de0 -.nvm 0x9000 0x6cde0 +.internal_storage 0x3a000 0x2fdd4 +.zwave_nvm 0x3000 0x69dd4 +.nvm 0x9000 0x6cdd4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf14c 0x0 -.debug_info 0xc324d9 0x0 -.debug_abbrev 0x21b3a 0x0 -.debug_loclists 0x17eb8 0x0 -.debug_aranges 0x5820 0x0 -.debug_rnglists 0x35df 0x0 -.debug_line 0x5ec99 0x0 -.debug_str 0x83cfd 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe1ab18 +.debug_frame 0xf120 0x0 +.debug_info 0xc326b3 0x0 +.debug_abbrev 0x21af5 0x0 +.debug_loclists 0x17ea4 0x0 +.debug_aranges 0x5818 0x0 +.debug_rnglists 0x35ee 0x0 +.debug_line 0x5eca9 0x0 +.debug_str 0x83cc5 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe1ac20 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197228 + 197216 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_US_LR_size.txt index 08071b27c9..2c2d5d2664 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x2fb14 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2fb14 -_zaf_cc_config 0x10 0x2fb24 -_cc_handlers_v3 0x1f8 0x2fb34 -_zw_protocol_cmd_handlers 0x70 0x2fd2c -_zw_protocol_cmd_handlers_lr 0x30 0x2fd9c -.ARM.exidx 0x8 0x2fdcc -.copy.table 0xc 0x2fdd4 -.zero.table 0x0 0x2fde0 +.text 0x2fb08 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2fb08 +_zaf_cc_config 0x10 0x2fb18 +_cc_handlers_v3 0x1f8 0x2fb28 +_zw_protocol_cmd_handlers 0x70 0x2fd20 +_zw_protocol_cmd_handlers_lr 0x30 0x2fd90 +.ARM.exidx 0x8 0x2fdc0 +.copy.table 0xc 0x2fdc8 +.zero.table 0x0 0x2fdd4 .stack 0x1000 0x20000000 .data 0x48c 0x20001000 .bss 0x9f24 0x2000148c text_application_ram 0x0 0x2000b3b0 .heap 0x800 0x2000b3b0 -.internal_storage 0x3a000 0x2fde0 -.zwave_nvm 0x3000 0x69de0 -.nvm 0x9000 0x6cde0 +.internal_storage 0x3a000 0x2fdd4 +.zwave_nvm 0x3000 0x69dd4 +.nvm 0x9000 0x6cdd4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf14c 0x0 -.debug_info 0xc324d9 0x0 -.debug_abbrev 0x21b3a 0x0 -.debug_loclists 0x17eb8 0x0 -.debug_aranges 0x5820 0x0 -.debug_rnglists 0x35df 0x0 -.debug_line 0x5ec99 0x0 -.debug_str 0x83cf3 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe1ab0e +.debug_frame 0xf120 0x0 +.debug_info 0xc326b3 0x0 +.debug_abbrev 0x21af5 0x0 +.debug_loclists 0x17ea4 0x0 +.debug_aranges 0x5818 0x0 +.debug_rnglists 0x35ee 0x0 +.debug_line 0x5eca9 0x0 +.debug_str 0x83cbb 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe1ac16 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197228 + 197216 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_US_size.txt index f76f7078d2..41395e581b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x2fb14 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2fb14 -_zaf_cc_config 0x10 0x2fb24 -_cc_handlers_v3 0x1f8 0x2fb34 -_zw_protocol_cmd_handlers 0x70 0x2fd2c -_zw_protocol_cmd_handlers_lr 0x30 0x2fd9c -.ARM.exidx 0x8 0x2fdcc -.copy.table 0xc 0x2fdd4 -.zero.table 0x0 0x2fde0 +.text 0x2fb08 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2fb08 +_zaf_cc_config 0x10 0x2fb18 +_cc_handlers_v3 0x1f8 0x2fb28 +_zw_protocol_cmd_handlers 0x70 0x2fd20 +_zw_protocol_cmd_handlers_lr 0x30 0x2fd90 +.ARM.exidx 0x8 0x2fdc0 +.copy.table 0xc 0x2fdc8 +.zero.table 0x0 0x2fdd4 .stack 0x1000 0x20000000 .data 0x48c 0x20001000 .bss 0x9f24 0x2000148c text_application_ram 0x0 0x2000b3b0 .heap 0x800 0x2000b3b0 -.internal_storage 0x3a000 0x2fde0 -.zwave_nvm 0x3000 0x69de0 -.nvm 0x9000 0x6cde0 +.internal_storage 0x3a000 0x2fdd4 +.zwave_nvm 0x3000 0x69dd4 +.nvm 0x9000 0x6cdd4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf14c 0x0 -.debug_info 0xc324d9 0x0 -.debug_abbrev 0x21b3a 0x0 -.debug_loclists 0x17eb8 0x0 -.debug_aranges 0x5820 0x0 -.debug_rnglists 0x35df 0x0 -.debug_line 0x5ec99 0x0 -.debug_str 0x83cfd 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe1ab18 +.debug_frame 0xf120 0x0 +.debug_info 0xc326b3 0x0 +.debug_abbrev 0x21af5 0x0 +.debug_loclists 0x17ea4 0x0 +.debug_aranges 0x5818 0x0 +.debug_rnglists 0x35ee 0x0 +.debug_line 0x5eca9 0x0 +.debug_str 0x83cc5 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe1ac20 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197228 + 197216 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_EU_size.txt index a83b331064..b8de93642c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x366e8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c6e8 -_zaf_cc_config 0x10 0x803c6f8 -_cc_handlers_v3 0x1f8 0x803c708 -_zw_protocol_cmd_handlers 0x70 0x803c900 -_zw_protocol_cmd_handlers_lr 0x30 0x803c970 -.ARM.exidx 0x8 0x803c9a0 -.copy.table 0xc 0x803c9a8 -.zero.table 0x0 0x803c9b4 +.text 0x36720 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c720 +_zaf_cc_config 0x10 0x803c730 +_cc_handlers_v3 0x1f8 0x803c740 +_zw_protocol_cmd_handlers 0x70 0x803c938 +_zw_protocol_cmd_handlers_lr 0x30 0x803c9a8 +.ARM.exidx 0x8 0x803c9d8 +.copy.table 0xc 0x803c9e0 +.zero.table 0x0 0x803c9ec .stack 0x1000 0x20000000 .data 0x60c 0x20001000 .bss 0xaa98 0x2000160c text_application_ram 0x0 0x2000c0a4 .heap 0x800 0x2000c0a8 -.internal_storage 0x30000 0x803c9b4 -.zwave_nvm 0x0 0x806c9b4 -.nvm 0x8000 0x806c9b4 +.internal_storage 0x30000 0x803c9ec +.zwave_nvm 0x0 0x806c9ec +.nvm 0x8000 0x806c9ec .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12160 0x0 -.debug_info 0xc7c272 0x0 -.debug_abbrev 0x27356 0x0 -.debug_loclists 0x2bf3a 0x0 +.debug_frame 0x12154 0x0 +.debug_info 0xc7d98a 0x0 +.debug_abbrev 0x272e1 0x0 +.debug_loclists 0x2bfad 0x0 .debug_aranges 0x66b0 0x0 -.debug_rnglists 0x4c88 0x0 -.debug_line 0x7522a 0x0 -.debug_str 0x8e066 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe9c48f +.debug_rnglists 0x4c8e 0x0 +.debug_line 0x752ff 0x0 +.debug_str 0x8e04f 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe9dc95 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225216 + 225272 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_US_LR_size.txt index ca41efe31e..ed83701d1a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x366e8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c6e8 -_zaf_cc_config 0x10 0x803c6f8 -_cc_handlers_v3 0x1f8 0x803c708 -_zw_protocol_cmd_handlers 0x70 0x803c900 -_zw_protocol_cmd_handlers_lr 0x30 0x803c970 -.ARM.exidx 0x8 0x803c9a0 -.copy.table 0xc 0x803c9a8 -.zero.table 0x0 0x803c9b4 +.text 0x36720 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c720 +_zaf_cc_config 0x10 0x803c730 +_cc_handlers_v3 0x1f8 0x803c740 +_zw_protocol_cmd_handlers 0x70 0x803c938 +_zw_protocol_cmd_handlers_lr 0x30 0x803c9a8 +.ARM.exidx 0x8 0x803c9d8 +.copy.table 0xc 0x803c9e0 +.zero.table 0x0 0x803c9ec .stack 0x1000 0x20000000 .data 0x60c 0x20001000 .bss 0xaa98 0x2000160c text_application_ram 0x0 0x2000c0a4 .heap 0x800 0x2000c0a8 -.internal_storage 0x30000 0x803c9b4 -.zwave_nvm 0x0 0x806c9b4 -.nvm 0x8000 0x806c9b4 +.internal_storage 0x30000 0x803c9ec +.zwave_nvm 0x0 0x806c9ec +.nvm 0x8000 0x806c9ec .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12160 0x0 -.debug_info 0xc7c272 0x0 -.debug_abbrev 0x27356 0x0 -.debug_loclists 0x2bf3a 0x0 +.debug_frame 0x12154 0x0 +.debug_info 0xc7d98a 0x0 +.debug_abbrev 0x272e1 0x0 +.debug_loclists 0x2bfad 0x0 .debug_aranges 0x66b0 0x0 -.debug_rnglists 0x4c88 0x0 -.debug_line 0x7522a 0x0 -.debug_str 0x8e05c 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe9c485 +.debug_rnglists 0x4c8e 0x0 +.debug_line 0x752ff 0x0 +.debug_str 0x8e045 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe9dc8b The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225216 + 225272 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_US_size.txt index a83b331064..b8de93642c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x366e8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c6e8 -_zaf_cc_config 0x10 0x803c6f8 -_cc_handlers_v3 0x1f8 0x803c708 -_zw_protocol_cmd_handlers 0x70 0x803c900 -_zw_protocol_cmd_handlers_lr 0x30 0x803c970 -.ARM.exidx 0x8 0x803c9a0 -.copy.table 0xc 0x803c9a8 -.zero.table 0x0 0x803c9b4 +.text 0x36720 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c720 +_zaf_cc_config 0x10 0x803c730 +_cc_handlers_v3 0x1f8 0x803c740 +_zw_protocol_cmd_handlers 0x70 0x803c938 +_zw_protocol_cmd_handlers_lr 0x30 0x803c9a8 +.ARM.exidx 0x8 0x803c9d8 +.copy.table 0xc 0x803c9e0 +.zero.table 0x0 0x803c9ec .stack 0x1000 0x20000000 .data 0x60c 0x20001000 .bss 0xaa98 0x2000160c text_application_ram 0x0 0x2000c0a4 .heap 0x800 0x2000c0a8 -.internal_storage 0x30000 0x803c9b4 -.zwave_nvm 0x0 0x806c9b4 -.nvm 0x8000 0x806c9b4 +.internal_storage 0x30000 0x803c9ec +.zwave_nvm 0x0 0x806c9ec +.nvm 0x8000 0x806c9ec .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12160 0x0 -.debug_info 0xc7c272 0x0 -.debug_abbrev 0x27356 0x0 -.debug_loclists 0x2bf3a 0x0 +.debug_frame 0x12154 0x0 +.debug_info 0xc7d98a 0x0 +.debug_abbrev 0x272e1 0x0 +.debug_loclists 0x2bfad 0x0 .debug_aranges 0x66b0 0x0 -.debug_rnglists 0x4c88 0x0 -.debug_line 0x7522a 0x0 -.debug_str 0x8e066 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe9c48f +.debug_rnglists 0x4c8e 0x0 +.debug_line 0x752ff 0x0 +.debug_str 0x8e04f 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe9dc95 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225216 + 225272 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_EU_size.txt index 85f22cf171..5e9038675d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x367bc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c7bc -_zaf_cc_config 0x10 0x803c7cc -_cc_handlers_v3 0x1f8 0x803c7dc -_zw_protocol_cmd_handlers 0x70 0x803c9d4 -_zw_protocol_cmd_handlers_lr 0x30 0x803ca44 -.ARM.exidx 0x8 0x803ca74 -.copy.table 0xc 0x803ca7c -.zero.table 0x0 0x803ca88 +.text 0x367d4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c7d4 +_zaf_cc_config 0x10 0x803c7e4 +_cc_handlers_v3 0x1f8 0x803c7f4 +_zw_protocol_cmd_handlers 0x70 0x803c9ec +_zw_protocol_cmd_handlers_lr 0x30 0x803ca5c +.ARM.exidx 0x8 0x803ca8c +.copy.table 0xc 0x803ca94 +.zero.table 0x0 0x803caa0 .stack 0x1000 0x20000000 .data 0x610 0x20001000 .bss 0xaa94 0x20001610 text_application_ram 0x0 0x2000c0a4 .heap 0x800 0x2000c0a8 -.internal_storage 0x30000 0x803ca88 -.zwave_nvm 0x0 0x806ca88 -.nvm 0x8000 0x806ca88 +.internal_storage 0x30000 0x803caa0 +.zwave_nvm 0x0 0x806caa0 +.nvm 0x8000 0x806caa0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12190 0x0 -.debug_info 0xc7c4ea 0x0 -.debug_abbrev 0x27458 0x0 -.debug_loclists 0x2bf3a 0x0 +.debug_frame 0x12184 0x0 +.debug_info 0xc7dc02 0x0 +.debug_abbrev 0x273e3 0x0 +.debug_loclists 0x2bfad 0x0 .debug_aranges 0x66d0 0x0 -.debug_rnglists 0x4c9b 0x0 -.debug_line 0x75403 0x0 -.debug_str 0x8e239 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe9ccec +.debug_rnglists 0x4ca1 0x0 +.debug_line 0x754d8 0x0 +.debug_str 0x8e222 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe9e4d2 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225432 + 225456 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_US_LR_size.txt index 500185cdea..6103cf9462 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x367bc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c7bc -_zaf_cc_config 0x10 0x803c7cc -_cc_handlers_v3 0x1f8 0x803c7dc -_zw_protocol_cmd_handlers 0x70 0x803c9d4 -_zw_protocol_cmd_handlers_lr 0x30 0x803ca44 -.ARM.exidx 0x8 0x803ca74 -.copy.table 0xc 0x803ca7c -.zero.table 0x0 0x803ca88 +.text 0x367d4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c7d4 +_zaf_cc_config 0x10 0x803c7e4 +_cc_handlers_v3 0x1f8 0x803c7f4 +_zw_protocol_cmd_handlers 0x70 0x803c9ec +_zw_protocol_cmd_handlers_lr 0x30 0x803ca5c +.ARM.exidx 0x8 0x803ca8c +.copy.table 0xc 0x803ca94 +.zero.table 0x0 0x803caa0 .stack 0x1000 0x20000000 .data 0x610 0x20001000 .bss 0xaa94 0x20001610 text_application_ram 0x0 0x2000c0a4 .heap 0x800 0x2000c0a8 -.internal_storage 0x30000 0x803ca88 -.zwave_nvm 0x0 0x806ca88 -.nvm 0x8000 0x806ca88 +.internal_storage 0x30000 0x803caa0 +.zwave_nvm 0x0 0x806caa0 +.nvm 0x8000 0x806caa0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12190 0x0 -.debug_info 0xc7c4ea 0x0 -.debug_abbrev 0x27458 0x0 -.debug_loclists 0x2bf3a 0x0 +.debug_frame 0x12184 0x0 +.debug_info 0xc7dc02 0x0 +.debug_abbrev 0x273e3 0x0 +.debug_loclists 0x2bfad 0x0 .debug_aranges 0x66d0 0x0 -.debug_rnglists 0x4c9b 0x0 -.debug_line 0x75403 0x0 -.debug_str 0x8e22f 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe9cce2 +.debug_rnglists 0x4ca1 0x0 +.debug_line 0x754d8 0x0 +.debug_str 0x8e218 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe9e4c8 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225432 + 225456 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_US_size.txt index 85f22cf171..5e9038675d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x367bc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c7bc -_zaf_cc_config 0x10 0x803c7cc -_cc_handlers_v3 0x1f8 0x803c7dc -_zw_protocol_cmd_handlers 0x70 0x803c9d4 -_zw_protocol_cmd_handlers_lr 0x30 0x803ca44 -.ARM.exidx 0x8 0x803ca74 -.copy.table 0xc 0x803ca7c -.zero.table 0x0 0x803ca88 +.text 0x367d4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c7d4 +_zaf_cc_config 0x10 0x803c7e4 +_cc_handlers_v3 0x1f8 0x803c7f4 +_zw_protocol_cmd_handlers 0x70 0x803c9ec +_zw_protocol_cmd_handlers_lr 0x30 0x803ca5c +.ARM.exidx 0x8 0x803ca8c +.copy.table 0xc 0x803ca94 +.zero.table 0x0 0x803caa0 .stack 0x1000 0x20000000 .data 0x610 0x20001000 .bss 0xaa94 0x20001610 text_application_ram 0x0 0x2000c0a4 .heap 0x800 0x2000c0a8 -.internal_storage 0x30000 0x803ca88 -.zwave_nvm 0x0 0x806ca88 -.nvm 0x8000 0x806ca88 +.internal_storage 0x30000 0x803caa0 +.zwave_nvm 0x0 0x806caa0 +.nvm 0x8000 0x806caa0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12190 0x0 -.debug_info 0xc7c4ea 0x0 -.debug_abbrev 0x27458 0x0 -.debug_loclists 0x2bf3a 0x0 +.debug_frame 0x12184 0x0 +.debug_info 0xc7dc02 0x0 +.debug_abbrev 0x273e3 0x0 +.debug_loclists 0x2bfad 0x0 .debug_aranges 0x66d0 0x0 -.debug_rnglists 0x4c9b 0x0 -.debug_line 0x75403 0x0 -.debug_str 0x8e239 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe9ccec +.debug_rnglists 0x4ca1 0x0 +.debug_line 0x754d8 0x0 +.debug_str 0x8e222 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe9e4d2 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225432 + 225456 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_EU_size.txt index 53c21535f0..31a322ab70 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x362a0 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c2a0 -_zaf_cc_config 0x10 0x803c2b0 -_cc_handlers_v3 0x1f8 0x803c2c0 -_zw_protocol_cmd_handlers 0x70 0x803c4b8 -_zw_protocol_cmd_handlers_lr 0x30 0x803c528 -.ARM.exidx 0x8 0x803c558 -.copy.table 0xc 0x803c560 -.zero.table 0x0 0x803c56c +.text 0x362b8 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c2b8 +_zaf_cc_config 0x10 0x803c2c8 +_cc_handlers_v3 0x1f8 0x803c2d8 +_zw_protocol_cmd_handlers 0x70 0x803c4d0 +_zw_protocol_cmd_handlers_lr 0x30 0x803c540 +.ARM.exidx 0x8 0x803c570 +.copy.table 0xc 0x803c578 +.zero.table 0x0 0x803c584 .stack 0x1000 0x20000000 .data 0x610 0x20001000 .bss 0xa8f8 0x20001610 text_application_ram 0x0 0x2000bf08 .heap 0x800 0x2000bf08 -.internal_storage 0x30000 0x803c56c -.zwave_nvm 0x0 0x806c56c -.nvm 0x8000 0x806c56c +.internal_storage 0x30000 0x803c584 +.zwave_nvm 0x0 0x806c584 +.nvm 0x8000 0x806c584 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b00 0x0 -.debug_info 0xc76891 0x0 -.debug_abbrev 0x26a71 0x0 -.debug_loclists 0x283f1 0x0 +.debug_frame 0x11af4 0x0 +.debug_info 0xc77fa9 0x0 +.debug_abbrev 0x269fc 0x0 +.debug_loclists 0x28464 0x0 .debug_aranges 0x6530 0x0 -.debug_rnglists 0x49f1 0x0 -.debug_line 0x72355 0x0 -.debug_str 0x8dda9 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe8e484 +.debug_rnglists 0x49f7 0x0 +.debug_line 0x72420 0x0 +.debug_str 0x8dd92 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe8fc60 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 224124 + 224148 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_US_LR_size.txt index cf66241c0a..d17ab3ace0 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x362a0 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c2a0 -_zaf_cc_config 0x10 0x803c2b0 -_cc_handlers_v3 0x1f8 0x803c2c0 -_zw_protocol_cmd_handlers 0x70 0x803c4b8 -_zw_protocol_cmd_handlers_lr 0x30 0x803c528 -.ARM.exidx 0x8 0x803c558 -.copy.table 0xc 0x803c560 -.zero.table 0x0 0x803c56c +.text 0x362b8 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c2b8 +_zaf_cc_config 0x10 0x803c2c8 +_cc_handlers_v3 0x1f8 0x803c2d8 +_zw_protocol_cmd_handlers 0x70 0x803c4d0 +_zw_protocol_cmd_handlers_lr 0x30 0x803c540 +.ARM.exidx 0x8 0x803c570 +.copy.table 0xc 0x803c578 +.zero.table 0x0 0x803c584 .stack 0x1000 0x20000000 .data 0x610 0x20001000 .bss 0xa8f8 0x20001610 text_application_ram 0x0 0x2000bf08 .heap 0x800 0x2000bf08 -.internal_storage 0x30000 0x803c56c -.zwave_nvm 0x0 0x806c56c -.nvm 0x8000 0x806c56c +.internal_storage 0x30000 0x803c584 +.zwave_nvm 0x0 0x806c584 +.nvm 0x8000 0x806c584 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b00 0x0 -.debug_info 0xc76891 0x0 -.debug_abbrev 0x26a71 0x0 -.debug_loclists 0x283f1 0x0 +.debug_frame 0x11af4 0x0 +.debug_info 0xc77fa9 0x0 +.debug_abbrev 0x269fc 0x0 +.debug_loclists 0x28464 0x0 .debug_aranges 0x6530 0x0 -.debug_rnglists 0x49f1 0x0 -.debug_line 0x72355 0x0 -.debug_str 0x8dd9f 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe8e47a +.debug_rnglists 0x49f7 0x0 +.debug_line 0x72420 0x0 +.debug_str 0x8dd88 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe8fc56 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 224124 + 224148 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_US_size.txt index 53c21535f0..31a322ab70 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x362a0 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c2a0 -_zaf_cc_config 0x10 0x803c2b0 -_cc_handlers_v3 0x1f8 0x803c2c0 -_zw_protocol_cmd_handlers 0x70 0x803c4b8 -_zw_protocol_cmd_handlers_lr 0x30 0x803c528 -.ARM.exidx 0x8 0x803c558 -.copy.table 0xc 0x803c560 -.zero.table 0x0 0x803c56c +.text 0x362b8 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c2b8 +_zaf_cc_config 0x10 0x803c2c8 +_cc_handlers_v3 0x1f8 0x803c2d8 +_zw_protocol_cmd_handlers 0x70 0x803c4d0 +_zw_protocol_cmd_handlers_lr 0x30 0x803c540 +.ARM.exidx 0x8 0x803c570 +.copy.table 0xc 0x803c578 +.zero.table 0x0 0x803c584 .stack 0x1000 0x20000000 .data 0x610 0x20001000 .bss 0xa8f8 0x20001610 text_application_ram 0x0 0x2000bf08 .heap 0x800 0x2000bf08 -.internal_storage 0x30000 0x803c56c -.zwave_nvm 0x0 0x806c56c -.nvm 0x8000 0x806c56c +.internal_storage 0x30000 0x803c584 +.zwave_nvm 0x0 0x806c584 +.nvm 0x8000 0x806c584 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11b00 0x0 -.debug_info 0xc76891 0x0 -.debug_abbrev 0x26a71 0x0 -.debug_loclists 0x283f1 0x0 +.debug_frame 0x11af4 0x0 +.debug_info 0xc77fa9 0x0 +.debug_abbrev 0x269fc 0x0 +.debug_loclists 0x28464 0x0 .debug_aranges 0x6530 0x0 -.debug_rnglists 0x49f1 0x0 -.debug_line 0x72355 0x0 -.debug_str 0x8dda9 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe8e484 +.debug_rnglists 0x49f7 0x0 +.debug_line 0x72420 0x0 +.debug_str 0x8dd92 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe8fc60 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 224124 + 224148 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_EU_size.txt index 68883722be..40985c5f72 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x36acc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803cacc -_zaf_cc_config 0x10 0x803cadc -_cc_handlers_v3 0x1f8 0x803caec -_zw_protocol_cmd_handlers 0x70 0x803cce4 -_zw_protocol_cmd_handlers_lr 0x30 0x803cd54 -.ARM.exidx 0x8 0x803cd84 -.copy.table 0xc 0x803cd8c -.zero.table 0x0 0x803cd98 +.text 0x36ae4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cae4 +_zaf_cc_config 0x10 0x803caf4 +_cc_handlers_v3 0x1f8 0x803cb04 +_zw_protocol_cmd_handlers 0x70 0x803ccfc +_zw_protocol_cmd_handlers_lr 0x30 0x803cd6c +.ARM.exidx 0x8 0x803cd9c +.copy.table 0xc 0x803cda4 +.zero.table 0x0 0x803cdb0 .stack 0x1000 0x20000000 .data 0x610 0x20001000 .bss 0xaa98 0x20001610 text_application_ram 0x0 0x2000c0a8 .heap 0x800 0x2000c0a8 -.internal_storage 0x30000 0x803cd98 -.zwave_nvm 0x0 0x806cd98 -.nvm 0x8000 0x806cd98 +.internal_storage 0x30000 0x803cdb0 +.zwave_nvm 0x0 0x806cdb0 +.nvm 0x8000 0x806cdb0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x121c0 0x0 -.debug_info 0xc7ceb9 0x0 -.debug_abbrev 0x27534 0x0 -.debug_loclists 0x2bf43 0x0 +.debug_frame 0x121b4 0x0 +.debug_info 0xc7e5d1 0x0 +.debug_abbrev 0x274bf 0x0 +.debug_loclists 0x2bfb6 0x0 .debug_aranges 0x6720 0x0 -.debug_rnglists 0x4cb3 0x0 -.debug_line 0x752fc 0x0 -.debug_str 0x8e809 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe9e006 +.debug_rnglists 0x4cb9 0x0 +.debug_line 0x753c9 0x0 +.debug_str 0x8e7f2 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe9f7e4 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 226216 + 226240 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_US_LR_size.txt index 97c7658b00..1ded8d1a79 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x36acc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803cacc -_zaf_cc_config 0x10 0x803cadc -_cc_handlers_v3 0x1f8 0x803caec -_zw_protocol_cmd_handlers 0x70 0x803cce4 -_zw_protocol_cmd_handlers_lr 0x30 0x803cd54 -.ARM.exidx 0x8 0x803cd84 -.copy.table 0xc 0x803cd8c -.zero.table 0x0 0x803cd98 +.text 0x36ae4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cae4 +_zaf_cc_config 0x10 0x803caf4 +_cc_handlers_v3 0x1f8 0x803cb04 +_zw_protocol_cmd_handlers 0x70 0x803ccfc +_zw_protocol_cmd_handlers_lr 0x30 0x803cd6c +.ARM.exidx 0x8 0x803cd9c +.copy.table 0xc 0x803cda4 +.zero.table 0x0 0x803cdb0 .stack 0x1000 0x20000000 .data 0x610 0x20001000 .bss 0xaa98 0x20001610 text_application_ram 0x0 0x2000c0a8 .heap 0x800 0x2000c0a8 -.internal_storage 0x30000 0x803cd98 -.zwave_nvm 0x0 0x806cd98 -.nvm 0x8000 0x806cd98 +.internal_storage 0x30000 0x803cdb0 +.zwave_nvm 0x0 0x806cdb0 +.nvm 0x8000 0x806cdb0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x121c0 0x0 -.debug_info 0xc7ceb9 0x0 -.debug_abbrev 0x27534 0x0 -.debug_loclists 0x2bf43 0x0 +.debug_frame 0x121b4 0x0 +.debug_info 0xc7e5d1 0x0 +.debug_abbrev 0x274bf 0x0 +.debug_loclists 0x2bfb6 0x0 .debug_aranges 0x6720 0x0 -.debug_rnglists 0x4cb3 0x0 -.debug_line 0x752fc 0x0 -.debug_str 0x8e7ff 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe9dffc +.debug_rnglists 0x4cb9 0x0 +.debug_line 0x753c9 0x0 +.debug_str 0x8e7e8 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe9f7da The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 226216 + 226240 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_US_size.txt index 68883722be..40985c5f72 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x36acc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803cacc -_zaf_cc_config 0x10 0x803cadc -_cc_handlers_v3 0x1f8 0x803caec -_zw_protocol_cmd_handlers 0x70 0x803cce4 -_zw_protocol_cmd_handlers_lr 0x30 0x803cd54 -.ARM.exidx 0x8 0x803cd84 -.copy.table 0xc 0x803cd8c -.zero.table 0x0 0x803cd98 +.text 0x36ae4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cae4 +_zaf_cc_config 0x10 0x803caf4 +_cc_handlers_v3 0x1f8 0x803cb04 +_zw_protocol_cmd_handlers 0x70 0x803ccfc +_zw_protocol_cmd_handlers_lr 0x30 0x803cd6c +.ARM.exidx 0x8 0x803cd9c +.copy.table 0xc 0x803cda4 +.zero.table 0x0 0x803cdb0 .stack 0x1000 0x20000000 .data 0x610 0x20001000 .bss 0xaa98 0x20001610 text_application_ram 0x0 0x2000c0a8 .heap 0x800 0x2000c0a8 -.internal_storage 0x30000 0x803cd98 -.zwave_nvm 0x0 0x806cd98 -.nvm 0x8000 0x806cd98 +.internal_storage 0x30000 0x803cdb0 +.zwave_nvm 0x0 0x806cdb0 +.nvm 0x8000 0x806cdb0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x121c0 0x0 -.debug_info 0xc7ceb9 0x0 -.debug_abbrev 0x27534 0x0 -.debug_loclists 0x2bf43 0x0 +.debug_frame 0x121b4 0x0 +.debug_info 0xc7e5d1 0x0 +.debug_abbrev 0x274bf 0x0 +.debug_loclists 0x2bfb6 0x0 .debug_aranges 0x6720 0x0 -.debug_rnglists 0x4cb3 0x0 -.debug_line 0x752fc 0x0 -.debug_str 0x8e809 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe9e006 +.debug_rnglists 0x4cb9 0x0 +.debug_line 0x753c9 0x0 +.debug_str 0x8e7f2 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe9f7e4 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 226216 + 226240 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_EU_size.txt index f76f7078d2..41395e581b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x2fb14 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2fb14 -_zaf_cc_config 0x10 0x2fb24 -_cc_handlers_v3 0x1f8 0x2fb34 -_zw_protocol_cmd_handlers 0x70 0x2fd2c -_zw_protocol_cmd_handlers_lr 0x30 0x2fd9c -.ARM.exidx 0x8 0x2fdcc -.copy.table 0xc 0x2fdd4 -.zero.table 0x0 0x2fde0 +.text 0x2fb08 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2fb08 +_zaf_cc_config 0x10 0x2fb18 +_cc_handlers_v3 0x1f8 0x2fb28 +_zw_protocol_cmd_handlers 0x70 0x2fd20 +_zw_protocol_cmd_handlers_lr 0x30 0x2fd90 +.ARM.exidx 0x8 0x2fdc0 +.copy.table 0xc 0x2fdc8 +.zero.table 0x0 0x2fdd4 .stack 0x1000 0x20000000 .data 0x48c 0x20001000 .bss 0x9f24 0x2000148c text_application_ram 0x0 0x2000b3b0 .heap 0x800 0x2000b3b0 -.internal_storage 0x3a000 0x2fde0 -.zwave_nvm 0x3000 0x69de0 -.nvm 0x9000 0x6cde0 +.internal_storage 0x3a000 0x2fdd4 +.zwave_nvm 0x3000 0x69dd4 +.nvm 0x9000 0x6cdd4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf14c 0x0 -.debug_info 0xc324d9 0x0 -.debug_abbrev 0x21b3a 0x0 -.debug_loclists 0x17eb8 0x0 -.debug_aranges 0x5820 0x0 -.debug_rnglists 0x35df 0x0 -.debug_line 0x5ec99 0x0 -.debug_str 0x83cfd 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe1ab18 +.debug_frame 0xf120 0x0 +.debug_info 0xc326b3 0x0 +.debug_abbrev 0x21af5 0x0 +.debug_loclists 0x17ea4 0x0 +.debug_aranges 0x5818 0x0 +.debug_rnglists 0x35ee 0x0 +.debug_line 0x5eca9 0x0 +.debug_str 0x83cc5 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe1ac20 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197228 + 197216 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_US_LR_size.txt index 08071b27c9..2c2d5d2664 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x2fb14 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2fb14 -_zaf_cc_config 0x10 0x2fb24 -_cc_handlers_v3 0x1f8 0x2fb34 -_zw_protocol_cmd_handlers 0x70 0x2fd2c -_zw_protocol_cmd_handlers_lr 0x30 0x2fd9c -.ARM.exidx 0x8 0x2fdcc -.copy.table 0xc 0x2fdd4 -.zero.table 0x0 0x2fde0 +.text 0x2fb08 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2fb08 +_zaf_cc_config 0x10 0x2fb18 +_cc_handlers_v3 0x1f8 0x2fb28 +_zw_protocol_cmd_handlers 0x70 0x2fd20 +_zw_protocol_cmd_handlers_lr 0x30 0x2fd90 +.ARM.exidx 0x8 0x2fdc0 +.copy.table 0xc 0x2fdc8 +.zero.table 0x0 0x2fdd4 .stack 0x1000 0x20000000 .data 0x48c 0x20001000 .bss 0x9f24 0x2000148c text_application_ram 0x0 0x2000b3b0 .heap 0x800 0x2000b3b0 -.internal_storage 0x3a000 0x2fde0 -.zwave_nvm 0x3000 0x69de0 -.nvm 0x9000 0x6cde0 +.internal_storage 0x3a000 0x2fdd4 +.zwave_nvm 0x3000 0x69dd4 +.nvm 0x9000 0x6cdd4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf14c 0x0 -.debug_info 0xc324d9 0x0 -.debug_abbrev 0x21b3a 0x0 -.debug_loclists 0x17eb8 0x0 -.debug_aranges 0x5820 0x0 -.debug_rnglists 0x35df 0x0 -.debug_line 0x5ec99 0x0 -.debug_str 0x83cf3 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe1ab0e +.debug_frame 0xf120 0x0 +.debug_info 0xc326b3 0x0 +.debug_abbrev 0x21af5 0x0 +.debug_loclists 0x17ea4 0x0 +.debug_aranges 0x5818 0x0 +.debug_rnglists 0x35ee 0x0 +.debug_line 0x5eca9 0x0 +.debug_str 0x83cbb 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe1ac16 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197228 + 197216 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_US_size.txt index f76f7078d2..41395e581b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x2fb14 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2fb14 -_zaf_cc_config 0x10 0x2fb24 -_cc_handlers_v3 0x1f8 0x2fb34 -_zw_protocol_cmd_handlers 0x70 0x2fd2c -_zw_protocol_cmd_handlers_lr 0x30 0x2fd9c -.ARM.exidx 0x8 0x2fdcc -.copy.table 0xc 0x2fdd4 -.zero.table 0x0 0x2fde0 +.text 0x2fb08 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2fb08 +_zaf_cc_config 0x10 0x2fb18 +_cc_handlers_v3 0x1f8 0x2fb28 +_zw_protocol_cmd_handlers 0x70 0x2fd20 +_zw_protocol_cmd_handlers_lr 0x30 0x2fd90 +.ARM.exidx 0x8 0x2fdc0 +.copy.table 0xc 0x2fdc8 +.zero.table 0x0 0x2fdd4 .stack 0x1000 0x20000000 .data 0x48c 0x20001000 .bss 0x9f24 0x2000148c text_application_ram 0x0 0x2000b3b0 .heap 0x800 0x2000b3b0 -.internal_storage 0x3a000 0x2fde0 -.zwave_nvm 0x3000 0x69de0 -.nvm 0x9000 0x6cde0 +.internal_storage 0x3a000 0x2fdd4 +.zwave_nvm 0x3000 0x69dd4 +.nvm 0x9000 0x6cdd4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf14c 0x0 -.debug_info 0xc324d9 0x0 -.debug_abbrev 0x21b3a 0x0 -.debug_loclists 0x17eb8 0x0 -.debug_aranges 0x5820 0x0 -.debug_rnglists 0x35df 0x0 -.debug_line 0x5ec99 0x0 -.debug_str 0x83cfd 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe1ab18 +.debug_frame 0xf120 0x0 +.debug_info 0xc326b3 0x0 +.debug_abbrev 0x21af5 0x0 +.debug_loclists 0x17ea4 0x0 +.debug_aranges 0x5818 0x0 +.debug_rnglists 0x35ee 0x0 +.debug_line 0x5eca9 0x0 +.debug_str 0x83cc5 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe1ac20 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197228 + 197216 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4209A_REGION_US_LR_size.txt index 98812ec6a6..e9d2efbe94 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4209A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x2fa4c 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2fa4c -_zaf_cc_config 0x10 0x2fa5c -_cc_handlers_v3 0x1f8 0x2fa6c -_zw_protocol_cmd_handlers 0x70 0x2fc64 -_zw_protocol_cmd_handlers_lr 0x30 0x2fcd4 -.ARM.exidx 0x8 0x2fd04 -.copy.table 0xc 0x2fd0c -.zero.table 0x0 0x2fd18 +.text 0x2fa60 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2fa60 +_zaf_cc_config 0x10 0x2fa70 +_cc_handlers_v3 0x1f8 0x2fa80 +_zw_protocol_cmd_handlers 0x70 0x2fc78 +_zw_protocol_cmd_handlers_lr 0x30 0x2fce8 +.ARM.exidx 0x8 0x2fd18 +.copy.table 0xc 0x2fd20 +.zero.table 0x0 0x2fd2c .stack 0x1000 0x20000000 .data 0x488 0x20001000 .bss 0x9f08 0x20001488 text_application_ram 0x0 0x2000b390 .heap 0x800 0x2000b390 -.internal_storage 0x3a000 0x2fd18 -.zwave_nvm 0x3000 0x69d18 -.nvm 0x9000 0x6cd18 +.internal_storage 0x3a000 0x2fd2c +.zwave_nvm 0x3000 0x69d2c +.nvm 0x9000 0x6cd2c .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf31c 0x0 -.debug_info 0xc33aba 0x0 -.debug_abbrev 0x2207d 0x0 -.debug_loclists 0x18555 0x0 -.debug_aranges 0x58c0 0x0 -.debug_rnglists 0x368a 0x0 -.debug_line 0x5fc81 0x0 -.debug_str 0x84025 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xe1e21c +.debug_frame 0xf2f0 0x0 +.debug_info 0xc33c94 0x0 +.debug_abbrev 0x22038 0x0 +.debug_loclists 0x18541 0x0 +.debug_aranges 0x58b8 0x0 +.debug_rnglists 0x3699 0x0 +.debug_line 0x5fc9b 0x0 +.debug_str 0x83fed 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xe1e34e The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197024 + 197044 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4210A_REGION_US_LR_size.txt index 40e7c37650..7c13199ea3 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4210A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x367dc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c7dc -_zaf_cc_config 0x10 0x803c7ec -_cc_handlers_v3 0x1f8 0x803c7fc -_zw_protocol_cmd_handlers 0x70 0x803c9f4 -_zw_protocol_cmd_handlers_lr 0x30 0x803ca64 -.ARM.exidx 0x8 0x803ca94 -.copy.table 0xc 0x803ca9c -.zero.table 0x0 0x803caa8 +.text 0x367f4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c7f4 +_zaf_cc_config 0x10 0x803c804 +_cc_handlers_v3 0x1f8 0x803c814 +_zw_protocol_cmd_handlers 0x70 0x803ca0c +_zw_protocol_cmd_handlers_lr 0x30 0x803ca7c +.ARM.exidx 0x8 0x803caac +.copy.table 0xc 0x803cab4 +.zero.table 0x0 0x803cac0 .stack 0x1000 0x20000000 .data 0x610 0x20001000 .bss 0xaa94 0x20001610 text_application_ram 0x0 0x2000c0a4 .heap 0x800 0x2000c0a8 -.internal_storage 0x30000 0x803caa8 -.zwave_nvm 0x0 0x806caa8 -.nvm 0x8000 0x806caa8 +.internal_storage 0x30000 0x803cac0 +.zwave_nvm 0x0 0x806cac0 +.nvm 0x8000 0x806cac0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12198 0x0 -.debug_info 0xc7c4b4 0x0 -.debug_abbrev 0x27458 0x0 -.debug_loclists 0x2bf3a 0x0 +.debug_frame 0x1218c 0x0 +.debug_info 0xc7dbcc 0x0 +.debug_abbrev 0x273e3 0x0 +.debug_loclists 0x2bfad 0x0 .debug_aranges 0x66d0 0x0 -.debug_rnglists 0x4c9b 0x0 -.debug_line 0x753da 0x0 -.debug_str 0x8e22f 0x0 -.debug_loc 0x2c495 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xe9cc78 +.debug_rnglists 0x4ca1 0x0 +.debug_line 0x754af 0x0 +.debug_str 0x8e218 0x0 +.debug_loc 0x2c45d 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xe9e45e The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225464 + 225488 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400B_REGION_EU_size.txt index ccaf428fb3..2981ecf9a8 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400B_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x3735c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d35c -_zaf_cc_config 0x10 0x803d36c -_cc_handlers_v3 0x1f8 0x803d37c -_zw_protocol_cmd_handlers 0x70 0x803d574 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5e4 -.ARM.exidx 0x8 0x803d614 -.copy.table 0xc 0x803d61c -.zero.table 0x0 0x803d628 +.text 0x37374 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d374 +_zaf_cc_config 0x10 0x803d384 +_cc_handlers_v3 0x1f8 0x803d394 +_zw_protocol_cmd_handlers 0x70 0x803d58c +_zw_protocol_cmd_handlers_lr 0x30 0x803d5fc +.ARM.exidx 0x8 0x803d62c +.copy.table 0xc 0x803d634 +.zero.table 0x0 0x803d640 .stack 0x1000 0x20000000 .data 0x60c 0x20001000 .bss 0xaa04 0x2000160c text_application_ram 0x0 0x2000c010 .heap 0x800 0x2000c010 -.internal_storage 0x30000 0x803d628 -.zwave_nvm 0x0 0x806d628 -.nvm 0x8000 0x806d628 +.internal_storage 0x30000 0x803d640 +.zwave_nvm 0x0 0x806d640 +.nvm 0x8000 0x806d640 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1225c 0x0 -.debug_info 0xc80e25 0x0 -.debug_abbrev 0x2779f 0x0 -.debug_loclists 0x2c469 0x0 +.debug_frame 0x12250 0x0 +.debug_info 0xc82541 0x0 +.debug_abbrev 0x2772a 0x0 +.debug_loclists 0x2c4dc 0x0 .debug_aranges 0x6750 0x0 -.debug_rnglists 0x4cf0 0x0 -.debug_line 0x7579d 0x0 -.debug_str 0x8fac8 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xea4660 +.debug_rnglists 0x4cf6 0x0 +.debug_line 0x75872 0x0 +.debug_str 0x8fab1 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xea5e4a The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228404 + 228428 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400B_REGION_US_LR_size.txt index 008b14f93a..ac8380cfb5 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x3735c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d35c -_zaf_cc_config 0x10 0x803d36c -_cc_handlers_v3 0x1f8 0x803d37c -_zw_protocol_cmd_handlers 0x70 0x803d574 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5e4 -.ARM.exidx 0x8 0x803d614 -.copy.table 0xc 0x803d61c -.zero.table 0x0 0x803d628 +.text 0x37374 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d374 +_zaf_cc_config 0x10 0x803d384 +_cc_handlers_v3 0x1f8 0x803d394 +_zw_protocol_cmd_handlers 0x70 0x803d58c +_zw_protocol_cmd_handlers_lr 0x30 0x803d5fc +.ARM.exidx 0x8 0x803d62c +.copy.table 0xc 0x803d634 +.zero.table 0x0 0x803d640 .stack 0x1000 0x20000000 .data 0x60c 0x20001000 .bss 0xaa04 0x2000160c text_application_ram 0x0 0x2000c010 .heap 0x800 0x2000c010 -.internal_storage 0x30000 0x803d628 -.zwave_nvm 0x0 0x806d628 -.nvm 0x8000 0x806d628 +.internal_storage 0x30000 0x803d640 +.zwave_nvm 0x0 0x806d640 +.nvm 0x8000 0x806d640 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1225c 0x0 -.debug_info 0xc80e25 0x0 -.debug_abbrev 0x2779f 0x0 -.debug_loclists 0x2c469 0x0 +.debug_frame 0x12250 0x0 +.debug_info 0xc82541 0x0 +.debug_abbrev 0x2772a 0x0 +.debug_loclists 0x2c4dc 0x0 .debug_aranges 0x6750 0x0 -.debug_rnglists 0x4cf0 0x0 -.debug_line 0x7579d 0x0 -.debug_str 0x8fabe 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xea4656 +.debug_rnglists 0x4cf6 0x0 +.debug_line 0x75872 0x0 +.debug_str 0x8faa7 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xea5e40 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228404 + 228428 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400B_REGION_US_size.txt index ccaf428fb3..2981ecf9a8 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400B_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x3735c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d35c -_zaf_cc_config 0x10 0x803d36c -_cc_handlers_v3 0x1f8 0x803d37c -_zw_protocol_cmd_handlers 0x70 0x803d574 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5e4 -.ARM.exidx 0x8 0x803d614 -.copy.table 0xc 0x803d61c -.zero.table 0x0 0x803d628 +.text 0x37374 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d374 +_zaf_cc_config 0x10 0x803d384 +_cc_handlers_v3 0x1f8 0x803d394 +_zw_protocol_cmd_handlers 0x70 0x803d58c +_zw_protocol_cmd_handlers_lr 0x30 0x803d5fc +.ARM.exidx 0x8 0x803d62c +.copy.table 0xc 0x803d634 +.zero.table 0x0 0x803d640 .stack 0x1000 0x20000000 .data 0x60c 0x20001000 .bss 0xaa04 0x2000160c text_application_ram 0x0 0x2000c010 .heap 0x800 0x2000c010 -.internal_storage 0x30000 0x803d628 -.zwave_nvm 0x0 0x806d628 -.nvm 0x8000 0x806d628 +.internal_storage 0x30000 0x803d640 +.zwave_nvm 0x0 0x806d640 +.nvm 0x8000 0x806d640 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1225c 0x0 -.debug_info 0xc80e25 0x0 -.debug_abbrev 0x2779f 0x0 -.debug_loclists 0x2c469 0x0 +.debug_frame 0x12250 0x0 +.debug_info 0xc82541 0x0 +.debug_abbrev 0x2772a 0x0 +.debug_loclists 0x2c4dc 0x0 .debug_aranges 0x6750 0x0 -.debug_rnglists 0x4cf0 0x0 -.debug_line 0x7579d 0x0 -.debug_str 0x8fac8 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xea4660 +.debug_rnglists 0x4cf6 0x0 +.debug_line 0x75872 0x0 +.debug_str 0x8fab1 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xea5e4a The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228404 + 228428 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400C_REGION_EU_size.txt index f3924bc78f..cf81d2a86a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x3735c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d35c -_zaf_cc_config 0x10 0x803d36c -_cc_handlers_v3 0x1f8 0x803d37c -_zw_protocol_cmd_handlers 0x70 0x803d574 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5e4 -.ARM.exidx 0x8 0x803d614 -.copy.table 0xc 0x803d61c -.zero.table 0x0 0x803d628 +.text 0x37374 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d374 +_zaf_cc_config 0x10 0x803d384 +_cc_handlers_v3 0x1f8 0x803d394 +_zw_protocol_cmd_handlers 0x70 0x803d58c +_zw_protocol_cmd_handlers_lr 0x30 0x803d5fc +.ARM.exidx 0x8 0x803d62c +.copy.table 0xc 0x803d634 +.zero.table 0x0 0x803d640 .stack 0x1000 0x20000000 .data 0x60c 0x20001000 .bss 0xaa04 0x2000160c text_application_ram 0x0 0x2000c010 .heap 0x800 0x2000c010 -.internal_storage 0x30000 0x803d628 -.zwave_nvm 0x0 0x806d628 -.nvm 0x8000 0x806d628 +.internal_storage 0x30000 0x803d640 +.zwave_nvm 0x0 0x806d640 +.nvm 0x8000 0x806d640 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12270 0x0 -.debug_info 0xc80db4 0x0 -.debug_abbrev 0x277a9 0x0 -.debug_loclists 0x2c435 0x0 +.debug_frame 0x12264 0x0 +.debug_info 0xc824d0 0x0 +.debug_abbrev 0x27734 0x0 +.debug_loclists 0x2c4a8 0x0 .debug_aranges 0x6758 0x0 -.debug_rnglists 0x4d19 0x0 -.debug_line 0x75792 0x0 -.debug_str 0x8fac8 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xea45ff +.debug_rnglists 0x4d1f 0x0 +.debug_line 0x75867 0x0 +.debug_str 0x8fab1 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xea5de9 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228404 + 228428 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400C_REGION_US_LR_size.txt index 3fed105daf..eb1d8a90af 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x3735c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d35c -_zaf_cc_config 0x10 0x803d36c -_cc_handlers_v3 0x1f8 0x803d37c -_zw_protocol_cmd_handlers 0x70 0x803d574 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5e4 -.ARM.exidx 0x8 0x803d614 -.copy.table 0xc 0x803d61c -.zero.table 0x0 0x803d628 +.text 0x37374 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d374 +_zaf_cc_config 0x10 0x803d384 +_cc_handlers_v3 0x1f8 0x803d394 +_zw_protocol_cmd_handlers 0x70 0x803d58c +_zw_protocol_cmd_handlers_lr 0x30 0x803d5fc +.ARM.exidx 0x8 0x803d62c +.copy.table 0xc 0x803d634 +.zero.table 0x0 0x803d640 .stack 0x1000 0x20000000 .data 0x60c 0x20001000 .bss 0xaa04 0x2000160c text_application_ram 0x0 0x2000c010 .heap 0x800 0x2000c010 -.internal_storage 0x30000 0x803d628 -.zwave_nvm 0x0 0x806d628 -.nvm 0x8000 0x806d628 +.internal_storage 0x30000 0x803d640 +.zwave_nvm 0x0 0x806d640 +.nvm 0x8000 0x806d640 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12270 0x0 -.debug_info 0xc80db4 0x0 -.debug_abbrev 0x277a9 0x0 -.debug_loclists 0x2c435 0x0 +.debug_frame 0x12264 0x0 +.debug_info 0xc824d0 0x0 +.debug_abbrev 0x27734 0x0 +.debug_loclists 0x2c4a8 0x0 .debug_aranges 0x6758 0x0 -.debug_rnglists 0x4d19 0x0 -.debug_line 0x75792 0x0 -.debug_str 0x8fabe 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xea45f5 +.debug_rnglists 0x4d1f 0x0 +.debug_line 0x75867 0x0 +.debug_str 0x8faa7 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xea5ddf The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228404 + 228428 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400C_REGION_US_size.txt index f3924bc78f..cf81d2a86a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4400C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x3735c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d35c -_zaf_cc_config 0x10 0x803d36c -_cc_handlers_v3 0x1f8 0x803d37c -_zw_protocol_cmd_handlers 0x70 0x803d574 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5e4 -.ARM.exidx 0x8 0x803d614 -.copy.table 0xc 0x803d61c -.zero.table 0x0 0x803d628 +.text 0x37374 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d374 +_zaf_cc_config 0x10 0x803d384 +_cc_handlers_v3 0x1f8 0x803d394 +_zw_protocol_cmd_handlers 0x70 0x803d58c +_zw_protocol_cmd_handlers_lr 0x30 0x803d5fc +.ARM.exidx 0x8 0x803d62c +.copy.table 0xc 0x803d634 +.zero.table 0x0 0x803d640 .stack 0x1000 0x20000000 .data 0x60c 0x20001000 .bss 0xaa04 0x2000160c text_application_ram 0x0 0x2000c010 .heap 0x800 0x2000c010 -.internal_storage 0x30000 0x803d628 -.zwave_nvm 0x0 0x806d628 -.nvm 0x8000 0x806d628 +.internal_storage 0x30000 0x803d640 +.zwave_nvm 0x0 0x806d640 +.nvm 0x8000 0x806d640 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12270 0x0 -.debug_info 0xc80db4 0x0 -.debug_abbrev 0x277a9 0x0 -.debug_loclists 0x2c435 0x0 +.debug_frame 0x12264 0x0 +.debug_info 0xc824d0 0x0 +.debug_abbrev 0x27734 0x0 +.debug_loclists 0x2c4a8 0x0 .debug_aranges 0x6758 0x0 -.debug_rnglists 0x4d19 0x0 -.debug_line 0x75792 0x0 -.debug_str 0x8fac8 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xea45ff +.debug_rnglists 0x4d1f 0x0 +.debug_line 0x75867 0x0 +.debug_str 0x8fab1 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xea5de9 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228404 + 228428 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4401B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4401B_REGION_US_LR_size.txt index 77939d3a21..6b514a4058 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4401B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4401B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x3737c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d37c -_zaf_cc_config 0x10 0x803d38c -_cc_handlers_v3 0x1f8 0x803d39c -_zw_protocol_cmd_handlers 0x70 0x803d594 -_zw_protocol_cmd_handlers_lr 0x30 0x803d604 -.ARM.exidx 0x8 0x803d634 -.copy.table 0xc 0x803d63c -.zero.table 0x0 0x803d648 +.text 0x373b4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d3b4 +_zaf_cc_config 0x10 0x803d3c4 +_cc_handlers_v3 0x1f8 0x803d3d4 +_zw_protocol_cmd_handlers 0x70 0x803d5cc +_zw_protocol_cmd_handlers_lr 0x30 0x803d63c +.ARM.exidx 0x8 0x803d66c +.copy.table 0xc 0x803d674 +.zero.table 0x0 0x803d680 .stack 0x1000 0x20000000 .data 0x60c 0x20001000 .bss 0xaa04 0x2000160c text_application_ram 0x0 0x2000c010 .heap 0x800 0x2000c010 -.internal_storage 0x30000 0x803d648 -.zwave_nvm 0x0 0x806d648 -.nvm 0x8000 0x806d648 +.internal_storage 0x30000 0x803d680 +.zwave_nvm 0x0 0x806d680 +.nvm 0x8000 0x806d680 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12264 0x0 -.debug_info 0xc80def 0x0 -.debug_abbrev 0x2779f 0x0 -.debug_loclists 0x2c469 0x0 +.debug_frame 0x12258 0x0 +.debug_info 0xc8250b 0x0 +.debug_abbrev 0x2772a 0x0 +.debug_loclists 0x2c4dc 0x0 .debug_aranges 0x6750 0x0 -.debug_rnglists 0x4cf0 0x0 -.debug_line 0x75774 0x0 -.debug_str 0x8fabe 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xea45ec +.debug_rnglists 0x4cf6 0x0 +.debug_line 0x75849 0x0 +.debug_str 0x8faa7 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xea5df6 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228436 + 228492 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4401C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4401C_REGION_EU_size.txt index 7a52bcdb50..dedd6004f1 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4401C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4401C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x3737c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d37c -_zaf_cc_config 0x10 0x803d38c -_cc_handlers_v3 0x1f8 0x803d39c -_zw_protocol_cmd_handlers 0x70 0x803d594 -_zw_protocol_cmd_handlers_lr 0x30 0x803d604 -.ARM.exidx 0x8 0x803d634 -.copy.table 0xc 0x803d63c -.zero.table 0x0 0x803d648 +.text 0x373b4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d3b4 +_zaf_cc_config 0x10 0x803d3c4 +_cc_handlers_v3 0x1f8 0x803d3d4 +_zw_protocol_cmd_handlers 0x70 0x803d5cc +_zw_protocol_cmd_handlers_lr 0x30 0x803d63c +.ARM.exidx 0x8 0x803d66c +.copy.table 0xc 0x803d674 +.zero.table 0x0 0x803d680 .stack 0x1000 0x20000000 .data 0x60c 0x20001000 .bss 0xaa04 0x2000160c text_application_ram 0x0 0x2000c010 .heap 0x800 0x2000c010 -.internal_storage 0x30000 0x803d648 -.zwave_nvm 0x0 0x806d648 -.nvm 0x8000 0x806d648 +.internal_storage 0x30000 0x803d680 +.zwave_nvm 0x0 0x806d680 +.nvm 0x8000 0x806d680 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12278 0x0 -.debug_info 0xc80d7e 0x0 -.debug_abbrev 0x277a9 0x0 -.debug_loclists 0x2c435 0x0 +.debug_frame 0x1226c 0x0 +.debug_info 0xc8249a 0x0 +.debug_abbrev 0x27734 0x0 +.debug_loclists 0x2c4a8 0x0 .debug_aranges 0x6758 0x0 -.debug_rnglists 0x4d19 0x0 -.debug_line 0x75769 0x0 -.debug_str 0x8fac8 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xea4595 +.debug_rnglists 0x4d1f 0x0 +.debug_line 0x7583e 0x0 +.debug_str 0x8fab1 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xea5d9f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228436 + 228492 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4401C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4401C_REGION_US_LR_size.txt index 24afe093ec..4bca10eb4b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4401C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4401C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x3737c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d37c -_zaf_cc_config 0x10 0x803d38c -_cc_handlers_v3 0x1f8 0x803d39c -_zw_protocol_cmd_handlers 0x70 0x803d594 -_zw_protocol_cmd_handlers_lr 0x30 0x803d604 -.ARM.exidx 0x8 0x803d634 -.copy.table 0xc 0x803d63c -.zero.table 0x0 0x803d648 +.text 0x373b4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d3b4 +_zaf_cc_config 0x10 0x803d3c4 +_cc_handlers_v3 0x1f8 0x803d3d4 +_zw_protocol_cmd_handlers 0x70 0x803d5cc +_zw_protocol_cmd_handlers_lr 0x30 0x803d63c +.ARM.exidx 0x8 0x803d66c +.copy.table 0xc 0x803d674 +.zero.table 0x0 0x803d680 .stack 0x1000 0x20000000 .data 0x60c 0x20001000 .bss 0xaa04 0x2000160c text_application_ram 0x0 0x2000c010 .heap 0x800 0x2000c010 -.internal_storage 0x30000 0x803d648 -.zwave_nvm 0x0 0x806d648 -.nvm 0x8000 0x806d648 +.internal_storage 0x30000 0x803d680 +.zwave_nvm 0x0 0x806d680 +.nvm 0x8000 0x806d680 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12278 0x0 -.debug_info 0xc80d7e 0x0 -.debug_abbrev 0x277a9 0x0 -.debug_loclists 0x2c435 0x0 +.debug_frame 0x1226c 0x0 +.debug_info 0xc8249a 0x0 +.debug_abbrev 0x27734 0x0 +.debug_loclists 0x2c4a8 0x0 .debug_aranges 0x6758 0x0 -.debug_rnglists 0x4d19 0x0 -.debug_line 0x75769 0x0 -.debug_str 0x8fabe 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xea458b +.debug_rnglists 0x4d1f 0x0 +.debug_line 0x7583e 0x0 +.debug_str 0x8faa7 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xea5d95 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228436 + 228492 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4401C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4401C_REGION_US_size.txt index 7a52bcdb50..dedd6004f1 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4401C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4401C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x3737c 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d37c -_zaf_cc_config 0x10 0x803d38c -_cc_handlers_v3 0x1f8 0x803d39c -_zw_protocol_cmd_handlers 0x70 0x803d594 -_zw_protocol_cmd_handlers_lr 0x30 0x803d604 -.ARM.exidx 0x8 0x803d634 -.copy.table 0xc 0x803d63c -.zero.table 0x0 0x803d648 +.text 0x373b4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d3b4 +_zaf_cc_config 0x10 0x803d3c4 +_cc_handlers_v3 0x1f8 0x803d3d4 +_zw_protocol_cmd_handlers 0x70 0x803d5cc +_zw_protocol_cmd_handlers_lr 0x30 0x803d63c +.ARM.exidx 0x8 0x803d66c +.copy.table 0xc 0x803d674 +.zero.table 0x0 0x803d680 .stack 0x1000 0x20000000 .data 0x60c 0x20001000 .bss 0xaa04 0x2000160c text_application_ram 0x0 0x2000c010 .heap 0x800 0x2000c010 -.internal_storage 0x30000 0x803d648 -.zwave_nvm 0x0 0x806d648 -.nvm 0x8000 0x806d648 +.internal_storage 0x30000 0x803d680 +.zwave_nvm 0x0 0x806d680 +.nvm 0x8000 0x806d680 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12278 0x0 -.debug_info 0xc80d7e 0x0 -.debug_abbrev 0x277a9 0x0 -.debug_loclists 0x2c435 0x0 +.debug_frame 0x1226c 0x0 +.debug_info 0xc8249a 0x0 +.debug_abbrev 0x27734 0x0 +.debug_loclists 0x2c4a8 0x0 .debug_aranges 0x6758 0x0 -.debug_rnglists 0x4d19 0x0 -.debug_line 0x75769 0x0 -.debug_str 0x8fac8 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xea4595 +.debug_rnglists 0x4d1f 0x0 +.debug_line 0x7583e 0x0 +.debug_str 0x8fab1 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xea5d9f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228436 + 228492 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2603A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2603A_REGION_EU_size.txt index 82a9ed776b..d69b9f9ea1 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2603A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2603A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x36b04 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803cb04 -_zaf_cc_config 0x8 0x803cb14 -_cc_handlers_v3 0x1d4 0x803cb1c -_zw_protocol_cmd_handlers 0x70 0x803ccf0 -_zw_protocol_cmd_handlers_lr 0x30 0x803cd60 -.ARM.exidx 0x8 0x803cd90 -.copy.table 0xc 0x803cd98 -.zero.table 0x0 0x803cda4 +.text 0x36b1c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cb1c +_zaf_cc_config 0x8 0x803cb2c +_cc_handlers_v3 0x1d4 0x803cb34 +_zw_protocol_cmd_handlers 0x70 0x803cd08 +_zw_protocol_cmd_handlers_lr 0x30 0x803cd78 +.ARM.exidx 0x8 0x803cda8 +.copy.table 0xc 0x803cdb0 +.zero.table 0x0 0x803cdbc .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xaf70 0x200015a0 text_application_ram 0x0 0x2000c510 .heap 0x800 0x2000c510 -.internal_storage 0x30000 0x803cda4 -.zwave_nvm 0x0 0x806cda4 -.nvm 0x8000 0x806cda4 +.internal_storage 0x30000 0x803cdbc +.zwave_nvm 0x0 0x806cdbc +.nvm 0x8000 0x806cdbc .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11fa0 0x0 -.debug_info 0xc163a5 0x0 -.debug_abbrev 0x26c4c 0x0 -.debug_loclists 0x2b6f8 0x0 +.debug_frame 0x11f94 0x0 +.debug_info 0xc17abd 0x0 +.debug_abbrev 0x26bd7 0x0 +.debug_loclists 0x2b76b 0x0 .debug_aranges 0x6678 0x0 -.debug_rnglists 0x4b97 0x0 -.debug_line 0x74342 0x0 -.debug_str 0x8e8e1 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe3556d +.debug_rnglists 0x4b9d 0x0 +.debug_line 0x7440f 0x0 +.debug_str 0x8e8ca 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe36d4b The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 226116 + 226140 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2603A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2603A_REGION_US_LR_size.txt index 5558da5788..e5c317b736 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2603A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2603A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x36b04 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803cb04 -_zaf_cc_config 0x8 0x803cb14 -_cc_handlers_v3 0x1d4 0x803cb1c -_zw_protocol_cmd_handlers 0x70 0x803ccf0 -_zw_protocol_cmd_handlers_lr 0x30 0x803cd60 -.ARM.exidx 0x8 0x803cd90 -.copy.table 0xc 0x803cd98 -.zero.table 0x0 0x803cda4 +.text 0x36b1c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cb1c +_zaf_cc_config 0x8 0x803cb2c +_cc_handlers_v3 0x1d4 0x803cb34 +_zw_protocol_cmd_handlers 0x70 0x803cd08 +_zw_protocol_cmd_handlers_lr 0x30 0x803cd78 +.ARM.exidx 0x8 0x803cda8 +.copy.table 0xc 0x803cdb0 +.zero.table 0x0 0x803cdbc .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xaf70 0x200015a0 text_application_ram 0x0 0x2000c510 .heap 0x800 0x2000c510 -.internal_storage 0x30000 0x803cda4 -.zwave_nvm 0x0 0x806cda4 -.nvm 0x8000 0x806cda4 +.internal_storage 0x30000 0x803cdbc +.zwave_nvm 0x0 0x806cdbc +.nvm 0x8000 0x806cdbc .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11fa0 0x0 -.debug_info 0xc163a5 0x0 -.debug_abbrev 0x26c4c 0x0 -.debug_loclists 0x2b6f8 0x0 +.debug_frame 0x11f94 0x0 +.debug_info 0xc17abd 0x0 +.debug_abbrev 0x26bd7 0x0 +.debug_loclists 0x2b76b 0x0 .debug_aranges 0x6678 0x0 -.debug_rnglists 0x4b97 0x0 -.debug_line 0x74342 0x0 -.debug_str 0x8e8d7 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe35563 +.debug_rnglists 0x4b9d 0x0 +.debug_line 0x7440f 0x0 +.debug_str 0x8e8c0 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe36d41 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 226116 + 226140 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2603A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2603A_REGION_US_size.txt index 82a9ed776b..d69b9f9ea1 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2603A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2603A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x36b04 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803cb04 -_zaf_cc_config 0x8 0x803cb14 -_cc_handlers_v3 0x1d4 0x803cb1c -_zw_protocol_cmd_handlers 0x70 0x803ccf0 -_zw_protocol_cmd_handlers_lr 0x30 0x803cd60 -.ARM.exidx 0x8 0x803cd90 -.copy.table 0xc 0x803cd98 -.zero.table 0x0 0x803cda4 +.text 0x36b1c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cb1c +_zaf_cc_config 0x8 0x803cb2c +_cc_handlers_v3 0x1d4 0x803cb34 +_zw_protocol_cmd_handlers 0x70 0x803cd08 +_zw_protocol_cmd_handlers_lr 0x30 0x803cd78 +.ARM.exidx 0x8 0x803cda8 +.copy.table 0xc 0x803cdb0 +.zero.table 0x0 0x803cdbc .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xaf70 0x200015a0 text_application_ram 0x0 0x2000c510 .heap 0x800 0x2000c510 -.internal_storage 0x30000 0x803cda4 -.zwave_nvm 0x0 0x806cda4 -.nvm 0x8000 0x806cda4 +.internal_storage 0x30000 0x803cdbc +.zwave_nvm 0x0 0x806cdbc +.nvm 0x8000 0x806cdbc .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11fa0 0x0 -.debug_info 0xc163a5 0x0 -.debug_abbrev 0x26c4c 0x0 -.debug_loclists 0x2b6f8 0x0 +.debug_frame 0x11f94 0x0 +.debug_info 0xc17abd 0x0 +.debug_abbrev 0x26bd7 0x0 +.debug_loclists 0x2b76b 0x0 .debug_aranges 0x6678 0x0 -.debug_rnglists 0x4b97 0x0 -.debug_line 0x74342 0x0 -.debug_str 0x8e8e1 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe3556d +.debug_rnglists 0x4b9d 0x0 +.debug_line 0x7440f 0x0 +.debug_str 0x8e8ca 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe36d4b The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 226116 + 226140 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2705A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2705A_REGION_EU_size.txt index 77ebdacf36..1157604d5a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2705A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2705A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x36f54 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803cf54 -_zaf_cc_config 0x8 0x803cf64 -_cc_handlers_v3 0x1d4 0x803cf6c -_zw_protocol_cmd_handlers 0x70 0x803d140 -_zw_protocol_cmd_handlers_lr 0x30 0x803d1b0 -.ARM.exidx 0x8 0x803d1e0 -.copy.table 0xc 0x803d1e8 -.zero.table 0x0 0x803d1f4 +.text 0x36f6c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cf6c +_zaf_cc_config 0x8 0x803cf7c +_cc_handlers_v3 0x1d4 0x803cf84 +_zw_protocol_cmd_handlers 0x70 0x803d158 +_zw_protocol_cmd_handlers_lr 0x30 0x803d1c8 +.ARM.exidx 0x8 0x803d1f8 +.copy.table 0xc 0x803d200 +.zero.table 0x0 0x803d20c .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaedc 0x2000159c text_application_ram 0x0 0x2000c478 .heap 0x800 0x2000c478 -.internal_storage 0x30000 0x803d1f4 -.zwave_nvm 0x0 0x806d1f4 -.nvm 0x8000 0x806d1f4 +.internal_storage 0x30000 0x803d20c +.zwave_nvm 0x0 0x806d20c +.nvm 0x8000 0x806d20c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11da0 0x0 -.debug_info 0xc12add 0x0 -.debug_abbrev 0x266a1 0x0 -.debug_loclists 0x2b4bf 0x0 +.debug_frame 0x11d94 0x0 +.debug_info 0xc141f9 0x0 +.debug_abbrev 0x2662c 0x0 +.debug_loclists 0x2b532 0x0 .debug_aranges 0x6598 0x0 -.debug_rnglists 0x4ad4 0x0 -.debug_line 0x7338b 0x0 -.debug_str 0x8ed95 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe308cf +.debug_rnglists 0x4ada 0x0 +.debug_line 0x73460 0x0 +.debug_str 0x8ed7e 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe320b9 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 227216 + 227240 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2705A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2705A_REGION_US_LR_size.txt index 64318be985..33f7b7c5d4 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2705A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2705A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x36f54 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803cf54 -_zaf_cc_config 0x8 0x803cf64 -_cc_handlers_v3 0x1d4 0x803cf6c -_zw_protocol_cmd_handlers 0x70 0x803d140 -_zw_protocol_cmd_handlers_lr 0x30 0x803d1b0 -.ARM.exidx 0x8 0x803d1e0 -.copy.table 0xc 0x803d1e8 -.zero.table 0x0 0x803d1f4 +.text 0x36f6c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cf6c +_zaf_cc_config 0x8 0x803cf7c +_cc_handlers_v3 0x1d4 0x803cf84 +_zw_protocol_cmd_handlers 0x70 0x803d158 +_zw_protocol_cmd_handlers_lr 0x30 0x803d1c8 +.ARM.exidx 0x8 0x803d1f8 +.copy.table 0xc 0x803d200 +.zero.table 0x0 0x803d20c .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaedc 0x2000159c text_application_ram 0x0 0x2000c478 .heap 0x800 0x2000c478 -.internal_storage 0x30000 0x803d1f4 -.zwave_nvm 0x0 0x806d1f4 -.nvm 0x8000 0x806d1f4 +.internal_storage 0x30000 0x803d20c +.zwave_nvm 0x0 0x806d20c +.nvm 0x8000 0x806d20c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11da0 0x0 -.debug_info 0xc12add 0x0 -.debug_abbrev 0x266a1 0x0 -.debug_loclists 0x2b4bf 0x0 +.debug_frame 0x11d94 0x0 +.debug_info 0xc141f9 0x0 +.debug_abbrev 0x2662c 0x0 +.debug_loclists 0x2b532 0x0 .debug_aranges 0x6598 0x0 -.debug_rnglists 0x4ad4 0x0 -.debug_line 0x7338b 0x0 -.debug_str 0x8ed8b 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe308c5 +.debug_rnglists 0x4ada 0x0 +.debug_line 0x73460 0x0 +.debug_str 0x8ed74 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe320af The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 227216 + 227240 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2705A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2705A_REGION_US_size.txt index 77ebdacf36..1157604d5a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2705A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD2705A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x36f54 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803cf54 -_zaf_cc_config 0x8 0x803cf64 -_cc_handlers_v3 0x1d4 0x803cf6c -_zw_protocol_cmd_handlers 0x70 0x803d140 -_zw_protocol_cmd_handlers_lr 0x30 0x803d1b0 -.ARM.exidx 0x8 0x803d1e0 -.copy.table 0xc 0x803d1e8 -.zero.table 0x0 0x803d1f4 +.text 0x36f6c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cf6c +_zaf_cc_config 0x8 0x803cf7c +_cc_handlers_v3 0x1d4 0x803cf84 +_zw_protocol_cmd_handlers 0x70 0x803d158 +_zw_protocol_cmd_handlers_lr 0x30 0x803d1c8 +.ARM.exidx 0x8 0x803d1f8 +.copy.table 0xc 0x803d200 +.zero.table 0x0 0x803d20c .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaedc 0x2000159c text_application_ram 0x0 0x2000c478 .heap 0x800 0x2000c478 -.internal_storage 0x30000 0x803d1f4 -.zwave_nvm 0x0 0x806d1f4 -.nvm 0x8000 0x806d1f4 +.internal_storage 0x30000 0x803d20c +.zwave_nvm 0x0 0x806d20c +.nvm 0x8000 0x806d20c .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x11da0 0x0 -.debug_info 0xc12add 0x0 -.debug_abbrev 0x266a1 0x0 -.debug_loclists 0x2b4bf 0x0 +.debug_frame 0x11d94 0x0 +.debug_info 0xc141f9 0x0 +.debug_abbrev 0x2662c 0x0 +.debug_loclists 0x2b532 0x0 .debug_aranges 0x6598 0x0 -.debug_rnglists 0x4ad4 0x0 -.debug_line 0x7338b 0x0 -.debug_str 0x8ed95 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe308cf +.debug_rnglists 0x4ada 0x0 +.debug_line 0x73460 0x0 +.debug_str 0x8ed7e 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe320b9 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 227216 + 227240 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_EU_size.txt index 1f605bc7af..9bb1722de6 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x2fb40 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2fb40 -_zaf_cc_config 0x8 0x2fb50 -_cc_handlers_v3 0x1d4 0x2fb58 -_zw_protocol_cmd_handlers 0x70 0x2fd2c -_zw_protocol_cmd_handlers_lr 0x30 0x2fd9c -.ARM.exidx 0x8 0x2fdcc -.copy.table 0xc 0x2fdd4 -.zero.table 0x0 0x2fde0 +.text 0x2fb34 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2fb34 +_zaf_cc_config 0x8 0x2fb44 +_cc_handlers_v3 0x1d4 0x2fb4c +_zw_protocol_cmd_handlers 0x70 0x2fd20 +_zw_protocol_cmd_handlers_lr 0x30 0x2fd90 +.ARM.exidx 0x8 0x2fdc0 +.copy.table 0xc 0x2fdc8 +.zero.table 0x0 0x2fdd4 .stack 0x1000 0x20000000 .data 0x41c 0x20001000 .bss 0xa3fc 0x2000141c text_application_ram 0x0 0x2000b818 .heap 0x800 0x2000b818 -.internal_storage 0x3a000 0x2fde0 -.zwave_nvm 0x3000 0x69de0 -.nvm 0x9000 0x6cde0 +.internal_storage 0x3a000 0x2fdd4 +.zwave_nvm 0x3000 0x69dd4 +.nvm 0x9000 0x6cdd4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf010 0x0 -.debug_info 0xbcdde4 0x0 -.debug_abbrev 0x21603 0x0 -.debug_loclists 0x17908 0x0 -.debug_aranges 0x57d8 0x0 -.debug_rnglists 0x3521 0x0 -.debug_line 0x5e463 0x0 -.debug_str 0x84028 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xdb5657 +.debug_frame 0xefe4 0x0 +.debug_info 0xbcdfbe 0x0 +.debug_abbrev 0x215be 0x0 +.debug_loclists 0x178f4 0x0 +.debug_aranges 0x57d0 0x0 +.debug_rnglists 0x3530 0x0 +.debug_line 0x5e473 0x0 +.debug_str 0x83ff0 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xdb575f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197116 + 197104 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_US_LR_size.txt index d23b20590e..af73815bb1 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x2fb40 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2fb40 -_zaf_cc_config 0x8 0x2fb50 -_cc_handlers_v3 0x1d4 0x2fb58 -_zw_protocol_cmd_handlers 0x70 0x2fd2c -_zw_protocol_cmd_handlers_lr 0x30 0x2fd9c -.ARM.exidx 0x8 0x2fdcc -.copy.table 0xc 0x2fdd4 -.zero.table 0x0 0x2fde0 +.text 0x2fb34 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2fb34 +_zaf_cc_config 0x8 0x2fb44 +_cc_handlers_v3 0x1d4 0x2fb4c +_zw_protocol_cmd_handlers 0x70 0x2fd20 +_zw_protocol_cmd_handlers_lr 0x30 0x2fd90 +.ARM.exidx 0x8 0x2fdc0 +.copy.table 0xc 0x2fdc8 +.zero.table 0x0 0x2fdd4 .stack 0x1000 0x20000000 .data 0x41c 0x20001000 .bss 0xa3fc 0x2000141c text_application_ram 0x0 0x2000b818 .heap 0x800 0x2000b818 -.internal_storage 0x3a000 0x2fde0 -.zwave_nvm 0x3000 0x69de0 -.nvm 0x9000 0x6cde0 +.internal_storage 0x3a000 0x2fdd4 +.zwave_nvm 0x3000 0x69dd4 +.nvm 0x9000 0x6cdd4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf010 0x0 -.debug_info 0xbcdde4 0x0 -.debug_abbrev 0x21603 0x0 -.debug_loclists 0x17908 0x0 -.debug_aranges 0x57d8 0x0 -.debug_rnglists 0x3521 0x0 -.debug_line 0x5e463 0x0 -.debug_str 0x8401e 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xdb564d +.debug_frame 0xefe4 0x0 +.debug_info 0xbcdfbe 0x0 +.debug_abbrev 0x215be 0x0 +.debug_loclists 0x178f4 0x0 +.debug_aranges 0x57d0 0x0 +.debug_rnglists 0x3530 0x0 +.debug_line 0x5e473 0x0 +.debug_str 0x83fe6 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xdb5755 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197116 + 197104 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_US_size.txt index 1f605bc7af..9bb1722de6 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x2fb40 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2fb40 -_zaf_cc_config 0x8 0x2fb50 -_cc_handlers_v3 0x1d4 0x2fb58 -_zw_protocol_cmd_handlers 0x70 0x2fd2c -_zw_protocol_cmd_handlers_lr 0x30 0x2fd9c -.ARM.exidx 0x8 0x2fdcc -.copy.table 0xc 0x2fdd4 -.zero.table 0x0 0x2fde0 +.text 0x2fb34 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2fb34 +_zaf_cc_config 0x8 0x2fb44 +_cc_handlers_v3 0x1d4 0x2fb4c +_zw_protocol_cmd_handlers 0x70 0x2fd20 +_zw_protocol_cmd_handlers_lr 0x30 0x2fd90 +.ARM.exidx 0x8 0x2fdc0 +.copy.table 0xc 0x2fdc8 +.zero.table 0x0 0x2fdd4 .stack 0x1000 0x20000000 .data 0x41c 0x20001000 .bss 0xa3fc 0x2000141c text_application_ram 0x0 0x2000b818 .heap 0x800 0x2000b818 -.internal_storage 0x3a000 0x2fde0 -.zwave_nvm 0x3000 0x69de0 -.nvm 0x9000 0x6cde0 +.internal_storage 0x3a000 0x2fdd4 +.zwave_nvm 0x3000 0x69dd4 +.nvm 0x9000 0x6cdd4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf010 0x0 -.debug_info 0xbcdde4 0x0 -.debug_abbrev 0x21603 0x0 -.debug_loclists 0x17908 0x0 -.debug_aranges 0x57d8 0x0 -.debug_rnglists 0x3521 0x0 -.debug_line 0x5e463 0x0 -.debug_str 0x84028 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xdb5657 +.debug_frame 0xefe4 0x0 +.debug_info 0xbcdfbe 0x0 +.debug_abbrev 0x215be 0x0 +.debug_loclists 0x178f4 0x0 +.debug_aranges 0x57d0 0x0 +.debug_rnglists 0x3530 0x0 +.debug_line 0x5e473 0x0 +.debug_str 0x83ff0 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xdb575f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197116 + 197104 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_EU_size.txt index 6f7ea2352c..128d2d0fe9 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x36714 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c714 -_zaf_cc_config 0x8 0x803c724 -_cc_handlers_v3 0x1d4 0x803c72c -_zw_protocol_cmd_handlers 0x70 0x803c900 -_zw_protocol_cmd_handlers_lr 0x30 0x803c970 -.ARM.exidx 0x8 0x803c9a0 -.copy.table 0xc 0x803c9a8 -.zero.table 0x0 0x803c9b4 +.text 0x3674c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c74c +_zaf_cc_config 0x8 0x803c75c +_cc_handlers_v3 0x1d4 0x803c764 +_zw_protocol_cmd_handlers 0x70 0x803c938 +_zw_protocol_cmd_handlers_lr 0x30 0x803c9a8 +.ARM.exidx 0x8 0x803c9d8 +.copy.table 0xc 0x803c9e0 +.zero.table 0x0 0x803c9ec .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xaf6c 0x200015a0 text_application_ram 0x0 0x2000c50c .heap 0x800 0x2000c510 -.internal_storage 0x30000 0x803c9b4 -.zwave_nvm 0x0 0x806c9b4 -.nvm 0x8000 0x806c9b4 +.internal_storage 0x30000 0x803c9ec +.zwave_nvm 0x0 0x806c9ec +.nvm 0x8000 0x806c9ec .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12024 0x0 -.debug_info 0xc17b82 0x0 -.debug_abbrev 0x26e21 0x0 -.debug_loclists 0x2b96c 0x0 +.debug_frame 0x12018 0x0 +.debug_info 0xc1929a 0x0 +.debug_abbrev 0x26dac 0x0 +.debug_loclists 0x2b9df 0x0 .debug_aranges 0x6668 0x0 -.debug_rnglists 0x4bc8 0x0 -.debug_line 0x749e4 0x0 -.debug_str 0x8e388 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe36f9c +.debug_rnglists 0x4bce 0x0 +.debug_line 0x74ab9 0x0 +.debug_str 0x8e371 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe387a2 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225108 + 225164 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_US_LR_size.txt index 2d4fd6b600..a37d6bc1b7 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x36714 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c714 -_zaf_cc_config 0x8 0x803c724 -_cc_handlers_v3 0x1d4 0x803c72c -_zw_protocol_cmd_handlers 0x70 0x803c900 -_zw_protocol_cmd_handlers_lr 0x30 0x803c970 -.ARM.exidx 0x8 0x803c9a0 -.copy.table 0xc 0x803c9a8 -.zero.table 0x0 0x803c9b4 +.text 0x3674c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c74c +_zaf_cc_config 0x8 0x803c75c +_cc_handlers_v3 0x1d4 0x803c764 +_zw_protocol_cmd_handlers 0x70 0x803c938 +_zw_protocol_cmd_handlers_lr 0x30 0x803c9a8 +.ARM.exidx 0x8 0x803c9d8 +.copy.table 0xc 0x803c9e0 +.zero.table 0x0 0x803c9ec .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xaf6c 0x200015a0 text_application_ram 0x0 0x2000c50c .heap 0x800 0x2000c510 -.internal_storage 0x30000 0x803c9b4 -.zwave_nvm 0x0 0x806c9b4 -.nvm 0x8000 0x806c9b4 +.internal_storage 0x30000 0x803c9ec +.zwave_nvm 0x0 0x806c9ec +.nvm 0x8000 0x806c9ec .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12024 0x0 -.debug_info 0xc17b82 0x0 -.debug_abbrev 0x26e21 0x0 -.debug_loclists 0x2b96c 0x0 +.debug_frame 0x12018 0x0 +.debug_info 0xc1929a 0x0 +.debug_abbrev 0x26dac 0x0 +.debug_loclists 0x2b9df 0x0 .debug_aranges 0x6668 0x0 -.debug_rnglists 0x4bc8 0x0 -.debug_line 0x749e4 0x0 -.debug_str 0x8e37e 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe36f92 +.debug_rnglists 0x4bce 0x0 +.debug_line 0x74ab9 0x0 +.debug_str 0x8e367 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe38798 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225108 + 225164 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_US_size.txt index 6f7ea2352c..128d2d0fe9 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x36714 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c714 -_zaf_cc_config 0x8 0x803c724 -_cc_handlers_v3 0x1d4 0x803c72c -_zw_protocol_cmd_handlers 0x70 0x803c900 -_zw_protocol_cmd_handlers_lr 0x30 0x803c970 -.ARM.exidx 0x8 0x803c9a0 -.copy.table 0xc 0x803c9a8 -.zero.table 0x0 0x803c9b4 +.text 0x3674c 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c74c +_zaf_cc_config 0x8 0x803c75c +_cc_handlers_v3 0x1d4 0x803c764 +_zw_protocol_cmd_handlers 0x70 0x803c938 +_zw_protocol_cmd_handlers_lr 0x30 0x803c9a8 +.ARM.exidx 0x8 0x803c9d8 +.copy.table 0xc 0x803c9e0 +.zero.table 0x0 0x803c9ec .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xaf6c 0x200015a0 text_application_ram 0x0 0x2000c50c .heap 0x800 0x2000c510 -.internal_storage 0x30000 0x803c9b4 -.zwave_nvm 0x0 0x806c9b4 -.nvm 0x8000 0x806c9b4 +.internal_storage 0x30000 0x803c9ec +.zwave_nvm 0x0 0x806c9ec +.nvm 0x8000 0x806c9ec .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12024 0x0 -.debug_info 0xc17b82 0x0 -.debug_abbrev 0x26e21 0x0 -.debug_loclists 0x2b96c 0x0 +.debug_frame 0x12018 0x0 +.debug_info 0xc1929a 0x0 +.debug_abbrev 0x26dac 0x0 +.debug_loclists 0x2b9df 0x0 .debug_aranges 0x6668 0x0 -.debug_rnglists 0x4bc8 0x0 -.debug_line 0x749e4 0x0 -.debug_str 0x8e388 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe36f9c +.debug_rnglists 0x4bce 0x0 +.debug_line 0x74ab9 0x0 +.debug_str 0x8e371 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe387a2 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225108 + 225164 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_EU_size.txt index 7df4a14b96..30943b4e97 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x367e8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c7e8 -_zaf_cc_config 0x8 0x803c7f8 -_cc_handlers_v3 0x1d4 0x803c800 -_zw_protocol_cmd_handlers 0x70 0x803c9d4 -_zw_protocol_cmd_handlers_lr 0x30 0x803ca44 -.ARM.exidx 0x8 0x803ca74 -.copy.table 0xc 0x803ca7c -.zero.table 0x0 0x803ca88 +.text 0x36800 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c800 +_zaf_cc_config 0x8 0x803c810 +_cc_handlers_v3 0x1d4 0x803c818 +_zw_protocol_cmd_handlers 0x70 0x803c9ec +_zw_protocol_cmd_handlers_lr 0x30 0x803ca5c +.ARM.exidx 0x8 0x803ca8c +.copy.table 0xc 0x803ca94 +.zero.table 0x0 0x803caa0 .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xaf6c 0x200015a0 text_application_ram 0x0 0x2000c50c .heap 0x800 0x2000c510 -.internal_storage 0x30000 0x803ca88 -.zwave_nvm 0x0 0x806ca88 -.nvm 0x8000 0x806ca88 +.internal_storage 0x30000 0x803caa0 +.zwave_nvm 0x0 0x806caa0 +.nvm 0x8000 0x806caa0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12054 0x0 -.debug_info 0xc17dfa 0x0 -.debug_abbrev 0x26f23 0x0 -.debug_loclists 0x2b96c 0x0 +.debug_frame 0x12048 0x0 +.debug_info 0xc19512 0x0 +.debug_abbrev 0x26eae 0x0 +.debug_loclists 0x2b9df 0x0 .debug_aranges 0x6688 0x0 -.debug_rnglists 0x4bdb 0x0 -.debug_line 0x74bbd 0x0 -.debug_str 0x8e55b 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe377f9 +.debug_rnglists 0x4be1 0x0 +.debug_line 0x74c92 0x0 +.debug_str 0x8e544 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe38fdf The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225320 + 225344 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_US_LR_size.txt index b43b6d2a1d..152a33b42f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x367e8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c7e8 -_zaf_cc_config 0x8 0x803c7f8 -_cc_handlers_v3 0x1d4 0x803c800 -_zw_protocol_cmd_handlers 0x70 0x803c9d4 -_zw_protocol_cmd_handlers_lr 0x30 0x803ca44 -.ARM.exidx 0x8 0x803ca74 -.copy.table 0xc 0x803ca7c -.zero.table 0x0 0x803ca88 +.text 0x36800 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c800 +_zaf_cc_config 0x8 0x803c810 +_cc_handlers_v3 0x1d4 0x803c818 +_zw_protocol_cmd_handlers 0x70 0x803c9ec +_zw_protocol_cmd_handlers_lr 0x30 0x803ca5c +.ARM.exidx 0x8 0x803ca8c +.copy.table 0xc 0x803ca94 +.zero.table 0x0 0x803caa0 .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xaf6c 0x200015a0 text_application_ram 0x0 0x2000c50c .heap 0x800 0x2000c510 -.internal_storage 0x30000 0x803ca88 -.zwave_nvm 0x0 0x806ca88 -.nvm 0x8000 0x806ca88 +.internal_storage 0x30000 0x803caa0 +.zwave_nvm 0x0 0x806caa0 +.nvm 0x8000 0x806caa0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12054 0x0 -.debug_info 0xc17dfa 0x0 -.debug_abbrev 0x26f23 0x0 -.debug_loclists 0x2b96c 0x0 +.debug_frame 0x12048 0x0 +.debug_info 0xc19512 0x0 +.debug_abbrev 0x26eae 0x0 +.debug_loclists 0x2b9df 0x0 .debug_aranges 0x6688 0x0 -.debug_rnglists 0x4bdb 0x0 -.debug_line 0x74bbd 0x0 -.debug_str 0x8e551 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe377ef +.debug_rnglists 0x4be1 0x0 +.debug_line 0x74c92 0x0 +.debug_str 0x8e53a 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe38fd5 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225320 + 225344 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_US_size.txt index 7df4a14b96..30943b4e97 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x367e8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c7e8 -_zaf_cc_config 0x8 0x803c7f8 -_cc_handlers_v3 0x1d4 0x803c800 -_zw_protocol_cmd_handlers 0x70 0x803c9d4 -_zw_protocol_cmd_handlers_lr 0x30 0x803ca44 -.ARM.exidx 0x8 0x803ca74 -.copy.table 0xc 0x803ca7c -.zero.table 0x0 0x803ca88 +.text 0x36800 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c800 +_zaf_cc_config 0x8 0x803c810 +_cc_handlers_v3 0x1d4 0x803c818 +_zw_protocol_cmd_handlers 0x70 0x803c9ec +_zw_protocol_cmd_handlers_lr 0x30 0x803ca5c +.ARM.exidx 0x8 0x803ca8c +.copy.table 0xc 0x803ca94 +.zero.table 0x0 0x803caa0 .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xaf6c 0x200015a0 text_application_ram 0x0 0x2000c50c .heap 0x800 0x2000c510 -.internal_storage 0x30000 0x803ca88 -.zwave_nvm 0x0 0x806ca88 -.nvm 0x8000 0x806ca88 +.internal_storage 0x30000 0x803caa0 +.zwave_nvm 0x0 0x806caa0 +.nvm 0x8000 0x806caa0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12054 0x0 -.debug_info 0xc17dfa 0x0 -.debug_abbrev 0x26f23 0x0 -.debug_loclists 0x2b96c 0x0 +.debug_frame 0x12048 0x0 +.debug_info 0xc19512 0x0 +.debug_abbrev 0x26eae 0x0 +.debug_loclists 0x2b9df 0x0 .debug_aranges 0x6688 0x0 -.debug_rnglists 0x4bdb 0x0 -.debug_line 0x74bbd 0x0 -.debug_str 0x8e55b 0x0 -.debug_loc 0x2c4b0 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe377f9 +.debug_rnglists 0x4be1 0x0 +.debug_line 0x74c92 0x0 +.debug_str 0x8e544 0x0 +.debug_loc 0x2c478 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe38fdf The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225320 + 225344 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_EU_size.txt index 18ed91eb9b..8681bfd30b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x362cc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c2cc -_zaf_cc_config 0x8 0x803c2dc -_cc_handlers_v3 0x1d4 0x803c2e4 -_zw_protocol_cmd_handlers 0x70 0x803c4b8 -_zw_protocol_cmd_handlers_lr 0x30 0x803c528 -.ARM.exidx 0x8 0x803c558 -.copy.table 0xc 0x803c560 -.zero.table 0x0 0x803c56c +.text 0x362e4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c2e4 +_zaf_cc_config 0x8 0x803c2f4 +_cc_handlers_v3 0x1d4 0x803c2fc +_zw_protocol_cmd_handlers 0x70 0x803c4d0 +_zw_protocol_cmd_handlers_lr 0x30 0x803c540 +.ARM.exidx 0x8 0x803c570 +.copy.table 0xc 0x803c578 +.zero.table 0x0 0x803c584 .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xadd0 0x200015a0 text_application_ram 0x0 0x2000c370 .heap 0x800 0x2000c370 -.internal_storage 0x30000 0x803c56c -.zwave_nvm 0x0 0x806c56c -.nvm 0x8000 0x806c56c +.internal_storage 0x30000 0x803c584 +.zwave_nvm 0x0 0x806c584 +.nvm 0x8000 0x806c584 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x119c4 0x0 -.debug_info 0xc121a1 0x0 -.debug_abbrev 0x2653c 0x0 -.debug_loclists 0x27e23 0x0 +.debug_frame 0x119b8 0x0 +.debug_info 0xc138b9 0x0 +.debug_abbrev 0x264c7 0x0 +.debug_loclists 0x27e96 0x0 .debug_aranges 0x64e8 0x0 -.debug_rnglists 0x4931 0x0 -.debug_line 0x71b0f 0x0 -.debug_str 0x8e0cb 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe28f91 +.debug_rnglists 0x4937 0x0 +.debug_line 0x71bda 0x0 +.debug_str 0x8e0b4 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe2a76d The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 224012 + 224036 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_US_LR_size.txt index 4b71f12e0a..d04e2eeb87 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x362cc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c2cc -_zaf_cc_config 0x8 0x803c2dc -_cc_handlers_v3 0x1d4 0x803c2e4 -_zw_protocol_cmd_handlers 0x70 0x803c4b8 -_zw_protocol_cmd_handlers_lr 0x30 0x803c528 -.ARM.exidx 0x8 0x803c558 -.copy.table 0xc 0x803c560 -.zero.table 0x0 0x803c56c +.text 0x362e4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c2e4 +_zaf_cc_config 0x8 0x803c2f4 +_cc_handlers_v3 0x1d4 0x803c2fc +_zw_protocol_cmd_handlers 0x70 0x803c4d0 +_zw_protocol_cmd_handlers_lr 0x30 0x803c540 +.ARM.exidx 0x8 0x803c570 +.copy.table 0xc 0x803c578 +.zero.table 0x0 0x803c584 .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xadd0 0x200015a0 text_application_ram 0x0 0x2000c370 .heap 0x800 0x2000c370 -.internal_storage 0x30000 0x803c56c -.zwave_nvm 0x0 0x806c56c -.nvm 0x8000 0x806c56c +.internal_storage 0x30000 0x803c584 +.zwave_nvm 0x0 0x806c584 +.nvm 0x8000 0x806c584 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x119c4 0x0 -.debug_info 0xc121a1 0x0 -.debug_abbrev 0x2653c 0x0 -.debug_loclists 0x27e23 0x0 +.debug_frame 0x119b8 0x0 +.debug_info 0xc138b9 0x0 +.debug_abbrev 0x264c7 0x0 +.debug_loclists 0x27e96 0x0 .debug_aranges 0x64e8 0x0 -.debug_rnglists 0x4931 0x0 -.debug_line 0x71b0f 0x0 -.debug_str 0x8e0c1 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe28f87 +.debug_rnglists 0x4937 0x0 +.debug_line 0x71bda 0x0 +.debug_str 0x8e0aa 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe2a763 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 224012 + 224036 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_US_size.txt index 18ed91eb9b..8681bfd30b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x362cc 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c2cc -_zaf_cc_config 0x8 0x803c2dc -_cc_handlers_v3 0x1d4 0x803c2e4 -_zw_protocol_cmd_handlers 0x70 0x803c4b8 -_zw_protocol_cmd_handlers_lr 0x30 0x803c528 -.ARM.exidx 0x8 0x803c558 -.copy.table 0xc 0x803c560 -.zero.table 0x0 0x803c56c +.text 0x362e4 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c2e4 +_zaf_cc_config 0x8 0x803c2f4 +_cc_handlers_v3 0x1d4 0x803c2fc +_zw_protocol_cmd_handlers 0x70 0x803c4d0 +_zw_protocol_cmd_handlers_lr 0x30 0x803c540 +.ARM.exidx 0x8 0x803c570 +.copy.table 0xc 0x803c578 +.zero.table 0x0 0x803c584 .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xadd0 0x200015a0 text_application_ram 0x0 0x2000c370 .heap 0x800 0x2000c370 -.internal_storage 0x30000 0x803c56c -.zwave_nvm 0x0 0x806c56c -.nvm 0x8000 0x806c56c +.internal_storage 0x30000 0x803c584 +.zwave_nvm 0x0 0x806c584 +.nvm 0x8000 0x806c584 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x119c4 0x0 -.debug_info 0xc121a1 0x0 -.debug_abbrev 0x2653c 0x0 -.debug_loclists 0x27e23 0x0 +.debug_frame 0x119b8 0x0 +.debug_info 0xc138b9 0x0 +.debug_abbrev 0x264c7 0x0 +.debug_loclists 0x27e96 0x0 .debug_aranges 0x64e8 0x0 -.debug_rnglists 0x4931 0x0 -.debug_line 0x71b0f 0x0 -.debug_str 0x8e0cb 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe28f91 +.debug_rnglists 0x4937 0x0 +.debug_line 0x71bda 0x0 +.debug_str 0x8e0b4 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe2a76d The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 224012 + 224036 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_EU_size.txt index a1470684ff..a4a85360df 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x36af8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803caf8 -_zaf_cc_config 0x8 0x803cb08 -_cc_handlers_v3 0x1d4 0x803cb10 -_zw_protocol_cmd_handlers 0x70 0x803cce4 -_zw_protocol_cmd_handlers_lr 0x30 0x803cd54 -.ARM.exidx 0x8 0x803cd84 -.copy.table 0xc 0x803cd8c -.zero.table 0x0 0x803cd98 +.text 0x36b10 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cb10 +_zaf_cc_config 0x8 0x803cb20 +_cc_handlers_v3 0x1d4 0x803cb28 +_zw_protocol_cmd_handlers 0x70 0x803ccfc +_zw_protocol_cmd_handlers_lr 0x30 0x803cd6c +.ARM.exidx 0x8 0x803cd9c +.copy.table 0xc 0x803cda4 +.zero.table 0x0 0x803cdb0 .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xaf70 0x200015a0 text_application_ram 0x0 0x2000c510 .heap 0x800 0x2000c510 -.internal_storage 0x30000 0x803cd98 -.zwave_nvm 0x0 0x806cd98 -.nvm 0x8000 0x806cd98 +.internal_storage 0x30000 0x803cdb0 +.zwave_nvm 0x0 0x806cdb0 +.nvm 0x8000 0x806cdb0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12084 0x0 -.debug_info 0xc187c9 0x0 -.debug_abbrev 0x26fff 0x0 -.debug_loclists 0x2b975 0x0 +.debug_frame 0x12078 0x0 +.debug_info 0xc19ee1 0x0 +.debug_abbrev 0x26f8a 0x0 +.debug_loclists 0x2b9e8 0x0 .debug_aranges 0x66d8 0x0 -.debug_rnglists 0x4bf3 0x0 -.debug_line 0x74ab6 0x0 -.debug_str 0x8eb2b 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe38b13 +.debug_rnglists 0x4bf9 0x0 +.debug_line 0x74b83 0x0 +.debug_str 0x8eb14 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe3a2f1 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 226104 + 226128 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_US_LR_size.txt index 39f50487a7..f6724e2d34 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x36af8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803caf8 -_zaf_cc_config 0x8 0x803cb08 -_cc_handlers_v3 0x1d4 0x803cb10 -_zw_protocol_cmd_handlers 0x70 0x803cce4 -_zw_protocol_cmd_handlers_lr 0x30 0x803cd54 -.ARM.exidx 0x8 0x803cd84 -.copy.table 0xc 0x803cd8c -.zero.table 0x0 0x803cd98 +.text 0x36b10 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cb10 +_zaf_cc_config 0x8 0x803cb20 +_cc_handlers_v3 0x1d4 0x803cb28 +_zw_protocol_cmd_handlers 0x70 0x803ccfc +_zw_protocol_cmd_handlers_lr 0x30 0x803cd6c +.ARM.exidx 0x8 0x803cd9c +.copy.table 0xc 0x803cda4 +.zero.table 0x0 0x803cdb0 .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xaf70 0x200015a0 text_application_ram 0x0 0x2000c510 .heap 0x800 0x2000c510 -.internal_storage 0x30000 0x803cd98 -.zwave_nvm 0x0 0x806cd98 -.nvm 0x8000 0x806cd98 +.internal_storage 0x30000 0x803cdb0 +.zwave_nvm 0x0 0x806cdb0 +.nvm 0x8000 0x806cdb0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12084 0x0 -.debug_info 0xc187c9 0x0 -.debug_abbrev 0x26fff 0x0 -.debug_loclists 0x2b975 0x0 +.debug_frame 0x12078 0x0 +.debug_info 0xc19ee1 0x0 +.debug_abbrev 0x26f8a 0x0 +.debug_loclists 0x2b9e8 0x0 .debug_aranges 0x66d8 0x0 -.debug_rnglists 0x4bf3 0x0 -.debug_line 0x74ab6 0x0 -.debug_str 0x8eb21 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe38b09 +.debug_rnglists 0x4bf9 0x0 +.debug_line 0x74b83 0x0 +.debug_str 0x8eb0a 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe3a2e7 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 226104 + 226128 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_US_size.txt index a1470684ff..a4a85360df 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x36af8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803caf8 -_zaf_cc_config 0x8 0x803cb08 -_cc_handlers_v3 0x1d4 0x803cb10 -_zw_protocol_cmd_handlers 0x70 0x803cce4 -_zw_protocol_cmd_handlers_lr 0x30 0x803cd54 -.ARM.exidx 0x8 0x803cd84 -.copy.table 0xc 0x803cd8c -.zero.table 0x0 0x803cd98 +.text 0x36b10 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803cb10 +_zaf_cc_config 0x8 0x803cb20 +_cc_handlers_v3 0x1d4 0x803cb28 +_zw_protocol_cmd_handlers 0x70 0x803ccfc +_zw_protocol_cmd_handlers_lr 0x30 0x803cd6c +.ARM.exidx 0x8 0x803cd9c +.copy.table 0xc 0x803cda4 +.zero.table 0x0 0x803cdb0 .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xaf70 0x200015a0 text_application_ram 0x0 0x2000c510 .heap 0x800 0x2000c510 -.internal_storage 0x30000 0x803cd98 -.zwave_nvm 0x0 0x806cd98 -.nvm 0x8000 0x806cd98 +.internal_storage 0x30000 0x803cdb0 +.zwave_nvm 0x0 0x806cdb0 +.nvm 0x8000 0x806cdb0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12084 0x0 -.debug_info 0xc187c9 0x0 -.debug_abbrev 0x26fff 0x0 -.debug_loclists 0x2b975 0x0 +.debug_frame 0x12078 0x0 +.debug_info 0xc19ee1 0x0 +.debug_abbrev 0x26f8a 0x0 +.debug_loclists 0x2b9e8 0x0 .debug_aranges 0x66d8 0x0 -.debug_rnglists 0x4bf3 0x0 -.debug_line 0x74ab6 0x0 -.debug_str 0x8eb2b 0x0 -.debug_loc 0x2c4a1 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe38b13 +.debug_rnglists 0x4bf9 0x0 +.debug_line 0x74b83 0x0 +.debug_str 0x8eb14 0x0 +.debug_loc 0x2c469 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe3a2f1 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 226104 + 226128 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_EU_size.txt index 1f605bc7af..9bb1722de6 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x2fb40 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2fb40 -_zaf_cc_config 0x8 0x2fb50 -_cc_handlers_v3 0x1d4 0x2fb58 -_zw_protocol_cmd_handlers 0x70 0x2fd2c -_zw_protocol_cmd_handlers_lr 0x30 0x2fd9c -.ARM.exidx 0x8 0x2fdcc -.copy.table 0xc 0x2fdd4 -.zero.table 0x0 0x2fde0 +.text 0x2fb34 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2fb34 +_zaf_cc_config 0x8 0x2fb44 +_cc_handlers_v3 0x1d4 0x2fb4c +_zw_protocol_cmd_handlers 0x70 0x2fd20 +_zw_protocol_cmd_handlers_lr 0x30 0x2fd90 +.ARM.exidx 0x8 0x2fdc0 +.copy.table 0xc 0x2fdc8 +.zero.table 0x0 0x2fdd4 .stack 0x1000 0x20000000 .data 0x41c 0x20001000 .bss 0xa3fc 0x2000141c text_application_ram 0x0 0x2000b818 .heap 0x800 0x2000b818 -.internal_storage 0x3a000 0x2fde0 -.zwave_nvm 0x3000 0x69de0 -.nvm 0x9000 0x6cde0 +.internal_storage 0x3a000 0x2fdd4 +.zwave_nvm 0x3000 0x69dd4 +.nvm 0x9000 0x6cdd4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf010 0x0 -.debug_info 0xbcdde4 0x0 -.debug_abbrev 0x21603 0x0 -.debug_loclists 0x17908 0x0 -.debug_aranges 0x57d8 0x0 -.debug_rnglists 0x3521 0x0 -.debug_line 0x5e463 0x0 -.debug_str 0x84028 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xdb5657 +.debug_frame 0xefe4 0x0 +.debug_info 0xbcdfbe 0x0 +.debug_abbrev 0x215be 0x0 +.debug_loclists 0x178f4 0x0 +.debug_aranges 0x57d0 0x0 +.debug_rnglists 0x3530 0x0 +.debug_line 0x5e473 0x0 +.debug_str 0x83ff0 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xdb575f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197116 + 197104 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_US_LR_size.txt index d23b20590e..af73815bb1 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x2fb40 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2fb40 -_zaf_cc_config 0x8 0x2fb50 -_cc_handlers_v3 0x1d4 0x2fb58 -_zw_protocol_cmd_handlers 0x70 0x2fd2c -_zw_protocol_cmd_handlers_lr 0x30 0x2fd9c -.ARM.exidx 0x8 0x2fdcc -.copy.table 0xc 0x2fdd4 -.zero.table 0x0 0x2fde0 +.text 0x2fb34 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2fb34 +_zaf_cc_config 0x8 0x2fb44 +_cc_handlers_v3 0x1d4 0x2fb4c +_zw_protocol_cmd_handlers 0x70 0x2fd20 +_zw_protocol_cmd_handlers_lr 0x30 0x2fd90 +.ARM.exidx 0x8 0x2fdc0 +.copy.table 0xc 0x2fdc8 +.zero.table 0x0 0x2fdd4 .stack 0x1000 0x20000000 .data 0x41c 0x20001000 .bss 0xa3fc 0x2000141c text_application_ram 0x0 0x2000b818 .heap 0x800 0x2000b818 -.internal_storage 0x3a000 0x2fde0 -.zwave_nvm 0x3000 0x69de0 -.nvm 0x9000 0x6cde0 +.internal_storage 0x3a000 0x2fdd4 +.zwave_nvm 0x3000 0x69dd4 +.nvm 0x9000 0x6cdd4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf010 0x0 -.debug_info 0xbcdde4 0x0 -.debug_abbrev 0x21603 0x0 -.debug_loclists 0x17908 0x0 -.debug_aranges 0x57d8 0x0 -.debug_rnglists 0x3521 0x0 -.debug_line 0x5e463 0x0 -.debug_str 0x8401e 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xdb564d +.debug_frame 0xefe4 0x0 +.debug_info 0xbcdfbe 0x0 +.debug_abbrev 0x215be 0x0 +.debug_loclists 0x178f4 0x0 +.debug_aranges 0x57d0 0x0 +.debug_rnglists 0x3530 0x0 +.debug_line 0x5e473 0x0 +.debug_str 0x83fe6 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xdb5755 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197116 + 197104 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_US_size.txt index 1f605bc7af..9bb1722de6 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x2fb40 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2fb40 -_zaf_cc_config 0x8 0x2fb50 -_cc_handlers_v3 0x1d4 0x2fb58 -_zw_protocol_cmd_handlers 0x70 0x2fd2c -_zw_protocol_cmd_handlers_lr 0x30 0x2fd9c -.ARM.exidx 0x8 0x2fdcc -.copy.table 0xc 0x2fdd4 -.zero.table 0x0 0x2fde0 +.text 0x2fb34 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2fb34 +_zaf_cc_config 0x8 0x2fb44 +_cc_handlers_v3 0x1d4 0x2fb4c +_zw_protocol_cmd_handlers 0x70 0x2fd20 +_zw_protocol_cmd_handlers_lr 0x30 0x2fd90 +.ARM.exidx 0x8 0x2fdc0 +.copy.table 0xc 0x2fdc8 +.zero.table 0x0 0x2fdd4 .stack 0x1000 0x20000000 .data 0x41c 0x20001000 .bss 0xa3fc 0x2000141c text_application_ram 0x0 0x2000b818 .heap 0x800 0x2000b818 -.internal_storage 0x3a000 0x2fde0 -.zwave_nvm 0x3000 0x69de0 -.nvm 0x9000 0x6cde0 +.internal_storage 0x3a000 0x2fdd4 +.zwave_nvm 0x3000 0x69dd4 +.nvm 0x9000 0x6cdd4 .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf010 0x0 -.debug_info 0xbcdde4 0x0 -.debug_abbrev 0x21603 0x0 -.debug_loclists 0x17908 0x0 -.debug_aranges 0x57d8 0x0 -.debug_rnglists 0x3521 0x0 -.debug_line 0x5e463 0x0 -.debug_str 0x84028 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xdb5657 +.debug_frame 0xefe4 0x0 +.debug_info 0xbcdfbe 0x0 +.debug_abbrev 0x215be 0x0 +.debug_loclists 0x178f4 0x0 +.debug_aranges 0x57d0 0x0 +.debug_rnglists 0x3530 0x0 +.debug_line 0x5e473 0x0 +.debug_str 0x83ff0 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xdb575f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 197116 + 197104 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4209A_REGION_US_LR_size.txt index 1f8e556462..2490758b20 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4209A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x2fa78 0x0 -_zaf_event_distributor_cc_event_handler 0x10 0x2fa78 -_zaf_cc_config 0x8 0x2fa88 -_cc_handlers_v3 0x1d4 0x2fa90 -_zw_protocol_cmd_handlers 0x70 0x2fc64 -_zw_protocol_cmd_handlers_lr 0x30 0x2fcd4 -.ARM.exidx 0x8 0x2fd04 -.copy.table 0xc 0x2fd0c -.zero.table 0x0 0x2fd18 +.text 0x2fa8c 0x0 +_zaf_event_distributor_cc_event_handler 0x10 0x2fa8c +_zaf_cc_config 0x8 0x2fa9c +_cc_handlers_v3 0x1d4 0x2faa4 +_zw_protocol_cmd_handlers 0x70 0x2fc78 +_zw_protocol_cmd_handlers_lr 0x30 0x2fce8 +.ARM.exidx 0x8 0x2fd18 +.copy.table 0xc 0x2fd20 +.zero.table 0x0 0x2fd2c .stack 0x1000 0x20000000 .data 0x41c 0x20001000 .bss 0xa3e4 0x2000141c text_application_ram 0x0 0x2000b800 .heap 0x800 0x2000b800 -.internal_storage 0x3a000 0x2fd18 -.zwave_nvm 0x3000 0x69d18 -.nvm 0x9000 0x6cd18 +.internal_storage 0x3a000 0x2fd2c +.zwave_nvm 0x3000 0x69d2c +.nvm 0x9000 0x6cd2c .ARM.attributes 0x2e 0x0 .comment 0x45 0x0 .debug_line_str 0x29d 0x0 -.debug_frame 0xf1e0 0x0 -.debug_info 0xbcf3c5 0x0 -.debug_abbrev 0x21b46 0x0 -.debug_loclists 0x17fa5 0x0 -.debug_aranges 0x5878 0x0 -.debug_rnglists 0x35cc 0x0 -.debug_line 0x5f44b 0x0 -.debug_str 0x84350 0x0 -.debug_loc 0x2d79c 0x0 -.debug_ranges 0x4f30 0x0 -Total 0xdb8d63 +.debug_frame 0xf1b4 0x0 +.debug_info 0xbcf59f 0x0 +.debug_abbrev 0x21b01 0x0 +.debug_loclists 0x17f91 0x0 +.debug_aranges 0x5870 0x0 +.debug_rnglists 0x35db 0x0 +.debug_line 0x5f465 0x0 +.debug_str 0x84318 0x0 +.debug_loc 0x2d764 0x0 +.debug_ranges 0x4f48 0x0 +Total 0xdb8e95 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 196916 + 196936 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4210A_REGION_US_LR_size.txt index 125603d2b1..801b30689b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4210A_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x36808 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803c808 -_zaf_cc_config 0x8 0x803c818 -_cc_handlers_v3 0x1d4 0x803c820 -_zw_protocol_cmd_handlers 0x70 0x803c9f4 -_zw_protocol_cmd_handlers_lr 0x30 0x803ca64 -.ARM.exidx 0x8 0x803ca94 -.copy.table 0xc 0x803ca9c -.zero.table 0x0 0x803caa8 +.text 0x36820 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803c820 +_zaf_cc_config 0x8 0x803c830 +_cc_handlers_v3 0x1d4 0x803c838 +_zw_protocol_cmd_handlers 0x70 0x803ca0c +_zw_protocol_cmd_handlers_lr 0x30 0x803ca7c +.ARM.exidx 0x8 0x803caac +.copy.table 0xc 0x803cab4 +.zero.table 0x0 0x803cac0 .stack 0x1000 0x20000000 .data 0x5a0 0x20001000 .bss 0xaf6c 0x200015a0 text_application_ram 0x0 0x2000c50c .heap 0x800 0x2000c510 -.internal_storage 0x30000 0x803caa8 -.zwave_nvm 0x0 0x806caa8 -.nvm 0x8000 0x806caa8 +.internal_storage 0x30000 0x803cac0 +.zwave_nvm 0x0 0x806cac0 +.nvm 0x8000 0x806cac0 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1205c 0x0 -.debug_info 0xc17dc4 0x0 -.debug_abbrev 0x26f23 0x0 -.debug_loclists 0x2b96c 0x0 +.debug_frame 0x12050 0x0 +.debug_info 0xc194dc 0x0 +.debug_abbrev 0x26eae 0x0 +.debug_loclists 0x2b9df 0x0 .debug_aranges 0x6688 0x0 -.debug_rnglists 0x4bdb 0x0 -.debug_line 0x74b94 0x0 -.debug_str 0x8e551 0x0 -.debug_loc 0x2c495 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xe37785 +.debug_rnglists 0x4be1 0x0 +.debug_line 0x74c69 0x0 +.debug_str 0x8e53a 0x0 +.debug_loc 0x2c45d 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xe38f6b The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225352 + 225376 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400B_REGION_EU_size.txt index 4c09669987..c8c4947589 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400B_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x37388 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d388 -_zaf_cc_config 0x8 0x803d398 -_cc_handlers_v3 0x1d4 0x803d3a0 -_zw_protocol_cmd_handlers 0x70 0x803d574 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5e4 -.ARM.exidx 0x8 0x803d614 -.copy.table 0xc 0x803d61c -.zero.table 0x0 0x803d628 +.text 0x373a0 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d3a0 +_zaf_cc_config 0x8 0x803d3b0 +_cc_handlers_v3 0x1d4 0x803d3b8 +_zw_protocol_cmd_handlers 0x70 0x803d58c +_zw_protocol_cmd_handlers_lr 0x30 0x803d5fc +.ARM.exidx 0x8 0x803d62c +.copy.table 0xc 0x803d634 +.zero.table 0x0 0x803d640 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaedc 0x2000159c text_application_ram 0x0 0x2000c478 .heap 0x800 0x2000c478 -.internal_storage 0x30000 0x803d628 -.zwave_nvm 0x0 0x806d628 -.nvm 0x8000 0x806d628 +.internal_storage 0x30000 0x803d640 +.zwave_nvm 0x0 0x806d640 +.nvm 0x8000 0x806d640 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12120 0x0 -.debug_info 0xc1c735 0x0 -.debug_abbrev 0x2726a 0x0 -.debug_loclists 0x2be9b 0x0 +.debug_frame 0x12114 0x0 +.debug_info 0xc1de51 0x0 +.debug_abbrev 0x271f5 0x0 +.debug_loclists 0x2bf0e 0x0 .debug_aranges 0x6708 0x0 -.debug_rnglists 0x4c30 0x0 -.debug_line 0x74f57 0x0 -.debug_str 0x8fdea 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe3f16d +.debug_rnglists 0x4c36 0x0 +.debug_line 0x7502c 0x0 +.debug_str 0x8fdd3 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe40957 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228292 + 228316 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400B_REGION_US_LR_size.txt index 72806f670b..02ef3fbbe8 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x37388 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d388 -_zaf_cc_config 0x8 0x803d398 -_cc_handlers_v3 0x1d4 0x803d3a0 -_zw_protocol_cmd_handlers 0x70 0x803d574 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5e4 -.ARM.exidx 0x8 0x803d614 -.copy.table 0xc 0x803d61c -.zero.table 0x0 0x803d628 +.text 0x373a0 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d3a0 +_zaf_cc_config 0x8 0x803d3b0 +_cc_handlers_v3 0x1d4 0x803d3b8 +_zw_protocol_cmd_handlers 0x70 0x803d58c +_zw_protocol_cmd_handlers_lr 0x30 0x803d5fc +.ARM.exidx 0x8 0x803d62c +.copy.table 0xc 0x803d634 +.zero.table 0x0 0x803d640 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaedc 0x2000159c text_application_ram 0x0 0x2000c478 .heap 0x800 0x2000c478 -.internal_storage 0x30000 0x803d628 -.zwave_nvm 0x0 0x806d628 -.nvm 0x8000 0x806d628 +.internal_storage 0x30000 0x803d640 +.zwave_nvm 0x0 0x806d640 +.nvm 0x8000 0x806d640 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12120 0x0 -.debug_info 0xc1c735 0x0 -.debug_abbrev 0x2726a 0x0 -.debug_loclists 0x2be9b 0x0 +.debug_frame 0x12114 0x0 +.debug_info 0xc1de51 0x0 +.debug_abbrev 0x271f5 0x0 +.debug_loclists 0x2bf0e 0x0 .debug_aranges 0x6708 0x0 -.debug_rnglists 0x4c30 0x0 -.debug_line 0x74f57 0x0 -.debug_str 0x8fde0 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe3f163 +.debug_rnglists 0x4c36 0x0 +.debug_line 0x7502c 0x0 +.debug_str 0x8fdc9 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe4094d The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228292 + 228316 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400B_REGION_US_size.txt index 4c09669987..c8c4947589 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400B_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x37388 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d388 -_zaf_cc_config 0x8 0x803d398 -_cc_handlers_v3 0x1d4 0x803d3a0 -_zw_protocol_cmd_handlers 0x70 0x803d574 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5e4 -.ARM.exidx 0x8 0x803d614 -.copy.table 0xc 0x803d61c -.zero.table 0x0 0x803d628 +.text 0x373a0 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d3a0 +_zaf_cc_config 0x8 0x803d3b0 +_cc_handlers_v3 0x1d4 0x803d3b8 +_zw_protocol_cmd_handlers 0x70 0x803d58c +_zw_protocol_cmd_handlers_lr 0x30 0x803d5fc +.ARM.exidx 0x8 0x803d62c +.copy.table 0xc 0x803d634 +.zero.table 0x0 0x803d640 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaedc 0x2000159c text_application_ram 0x0 0x2000c478 .heap 0x800 0x2000c478 -.internal_storage 0x30000 0x803d628 -.zwave_nvm 0x0 0x806d628 -.nvm 0x8000 0x806d628 +.internal_storage 0x30000 0x803d640 +.zwave_nvm 0x0 0x806d640 +.nvm 0x8000 0x806d640 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12120 0x0 -.debug_info 0xc1c735 0x0 -.debug_abbrev 0x2726a 0x0 -.debug_loclists 0x2be9b 0x0 +.debug_frame 0x12114 0x0 +.debug_info 0xc1de51 0x0 +.debug_abbrev 0x271f5 0x0 +.debug_loclists 0x2bf0e 0x0 .debug_aranges 0x6708 0x0 -.debug_rnglists 0x4c30 0x0 -.debug_line 0x74f57 0x0 -.debug_str 0x8fdea 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe3f16d +.debug_rnglists 0x4c36 0x0 +.debug_line 0x7502c 0x0 +.debug_str 0x8fdd3 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe40957 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228292 + 228316 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400C_REGION_EU_size.txt index 3ffff0aced..0182e77561 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x37388 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d388 -_zaf_cc_config 0x8 0x803d398 -_cc_handlers_v3 0x1d4 0x803d3a0 -_zw_protocol_cmd_handlers 0x70 0x803d574 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5e4 -.ARM.exidx 0x8 0x803d614 -.copy.table 0xc 0x803d61c -.zero.table 0x0 0x803d628 +.text 0x373a0 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d3a0 +_zaf_cc_config 0x8 0x803d3b0 +_cc_handlers_v3 0x1d4 0x803d3b8 +_zw_protocol_cmd_handlers 0x70 0x803d58c +_zw_protocol_cmd_handlers_lr 0x30 0x803d5fc +.ARM.exidx 0x8 0x803d62c +.copy.table 0xc 0x803d634 +.zero.table 0x0 0x803d640 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaedc 0x2000159c text_application_ram 0x0 0x2000c478 .heap 0x800 0x2000c478 -.internal_storage 0x30000 0x803d628 -.zwave_nvm 0x0 0x806d628 -.nvm 0x8000 0x806d628 +.internal_storage 0x30000 0x803d640 +.zwave_nvm 0x0 0x806d640 +.nvm 0x8000 0x806d640 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12134 0x0 -.debug_info 0xc1c6c4 0x0 -.debug_abbrev 0x27274 0x0 -.debug_loclists 0x2be67 0x0 +.debug_frame 0x12128 0x0 +.debug_info 0xc1dde0 0x0 +.debug_abbrev 0x271ff 0x0 +.debug_loclists 0x2beda 0x0 .debug_aranges 0x6710 0x0 -.debug_rnglists 0x4c59 0x0 -.debug_line 0x74f4c 0x0 -.debug_str 0x8fdea 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe3f10c +.debug_rnglists 0x4c5f 0x0 +.debug_line 0x75021 0x0 +.debug_str 0x8fdd3 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe408f6 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228292 + 228316 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400C_REGION_US_LR_size.txt index 9b4a85821b..de46c0212a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x37388 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d388 -_zaf_cc_config 0x8 0x803d398 -_cc_handlers_v3 0x1d4 0x803d3a0 -_zw_protocol_cmd_handlers 0x70 0x803d574 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5e4 -.ARM.exidx 0x8 0x803d614 -.copy.table 0xc 0x803d61c -.zero.table 0x0 0x803d628 +.text 0x373a0 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d3a0 +_zaf_cc_config 0x8 0x803d3b0 +_cc_handlers_v3 0x1d4 0x803d3b8 +_zw_protocol_cmd_handlers 0x70 0x803d58c +_zw_protocol_cmd_handlers_lr 0x30 0x803d5fc +.ARM.exidx 0x8 0x803d62c +.copy.table 0xc 0x803d634 +.zero.table 0x0 0x803d640 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaedc 0x2000159c text_application_ram 0x0 0x2000c478 .heap 0x800 0x2000c478 -.internal_storage 0x30000 0x803d628 -.zwave_nvm 0x0 0x806d628 -.nvm 0x8000 0x806d628 +.internal_storage 0x30000 0x803d640 +.zwave_nvm 0x0 0x806d640 +.nvm 0x8000 0x806d640 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12134 0x0 -.debug_info 0xc1c6c4 0x0 -.debug_abbrev 0x27274 0x0 -.debug_loclists 0x2be67 0x0 +.debug_frame 0x12128 0x0 +.debug_info 0xc1dde0 0x0 +.debug_abbrev 0x271ff 0x0 +.debug_loclists 0x2beda 0x0 .debug_aranges 0x6710 0x0 -.debug_rnglists 0x4c59 0x0 -.debug_line 0x74f4c 0x0 -.debug_str 0x8fde0 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe3f102 +.debug_rnglists 0x4c5f 0x0 +.debug_line 0x75021 0x0 +.debug_str 0x8fdc9 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe408ec The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228292 + 228316 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400C_REGION_US_size.txt index 3ffff0aced..0182e77561 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4400C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x37388 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d388 -_zaf_cc_config 0x8 0x803d398 -_cc_handlers_v3 0x1d4 0x803d3a0 -_zw_protocol_cmd_handlers 0x70 0x803d574 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5e4 -.ARM.exidx 0x8 0x803d614 -.copy.table 0xc 0x803d61c -.zero.table 0x0 0x803d628 +.text 0x373a0 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d3a0 +_zaf_cc_config 0x8 0x803d3b0 +_cc_handlers_v3 0x1d4 0x803d3b8 +_zw_protocol_cmd_handlers 0x70 0x803d58c +_zw_protocol_cmd_handlers_lr 0x30 0x803d5fc +.ARM.exidx 0x8 0x803d62c +.copy.table 0xc 0x803d634 +.zero.table 0x0 0x803d640 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaedc 0x2000159c text_application_ram 0x0 0x2000c478 .heap 0x800 0x2000c478 -.internal_storage 0x30000 0x803d628 -.zwave_nvm 0x0 0x806d628 -.nvm 0x8000 0x806d628 +.internal_storage 0x30000 0x803d640 +.zwave_nvm 0x0 0x806d640 +.nvm 0x8000 0x806d640 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12134 0x0 -.debug_info 0xc1c6c4 0x0 -.debug_abbrev 0x27274 0x0 -.debug_loclists 0x2be67 0x0 +.debug_frame 0x12128 0x0 +.debug_info 0xc1dde0 0x0 +.debug_abbrev 0x271ff 0x0 +.debug_loclists 0x2beda 0x0 .debug_aranges 0x6710 0x0 -.debug_rnglists 0x4c59 0x0 -.debug_line 0x74f4c 0x0 -.debug_str 0x8fdea 0x0 -.debug_loc 0x2c39d 0x0 -.debug_ranges 0x4e48 0x0 -Total 0xe3f10c +.debug_rnglists 0x4c5f 0x0 +.debug_line 0x75021 0x0 +.debug_str 0x8fdd3 0x0 +.debug_loc 0x2c365 0x0 +.debug_ranges 0x4e80 0x0 +Total 0xe408f6 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228292 + 228316 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4401B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4401B_REGION_US_LR_size.txt index cf5601739b..4f0a3e018f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4401B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4401B_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x373a8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d3a8 -_zaf_cc_config 0x8 0x803d3b8 -_cc_handlers_v3 0x1d4 0x803d3c0 -_zw_protocol_cmd_handlers 0x70 0x803d594 -_zw_protocol_cmd_handlers_lr 0x30 0x803d604 -.ARM.exidx 0x8 0x803d634 -.copy.table 0xc 0x803d63c -.zero.table 0x0 0x803d648 +.text 0x373e0 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d3e0 +_zaf_cc_config 0x8 0x803d3f0 +_cc_handlers_v3 0x1d4 0x803d3f8 +_zw_protocol_cmd_handlers 0x70 0x803d5cc +_zw_protocol_cmd_handlers_lr 0x30 0x803d63c +.ARM.exidx 0x8 0x803d66c +.copy.table 0xc 0x803d674 +.zero.table 0x0 0x803d680 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaedc 0x2000159c text_application_ram 0x0 0x2000c478 .heap 0x800 0x2000c478 -.internal_storage 0x30000 0x803d648 -.zwave_nvm 0x0 0x806d648 -.nvm 0x8000 0x806d648 +.internal_storage 0x30000 0x803d680 +.zwave_nvm 0x0 0x806d680 +.nvm 0x8000 0x806d680 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x12128 0x0 -.debug_info 0xc1c6ff 0x0 -.debug_abbrev 0x2726a 0x0 -.debug_loclists 0x2be9b 0x0 +.debug_frame 0x1211c 0x0 +.debug_info 0xc1de1b 0x0 +.debug_abbrev 0x271f5 0x0 +.debug_loclists 0x2bf0e 0x0 .debug_aranges 0x6708 0x0 -.debug_rnglists 0x4c30 0x0 -.debug_line 0x74f2e 0x0 -.debug_str 0x8fde0 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xe3f0f9 +.debug_rnglists 0x4c36 0x0 +.debug_line 0x75003 0x0 +.debug_str 0x8fdc9 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xe40903 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228324 + 228380 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4401C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4401C_REGION_EU_size.txt index 4d4950cd61..151ccc3ee9 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4401C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4401C_REGION_EU_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x373a8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d3a8 -_zaf_cc_config 0x8 0x803d3b8 -_cc_handlers_v3 0x1d4 0x803d3c0 -_zw_protocol_cmd_handlers 0x70 0x803d594 -_zw_protocol_cmd_handlers_lr 0x30 0x803d604 -.ARM.exidx 0x8 0x803d634 -.copy.table 0xc 0x803d63c -.zero.table 0x0 0x803d648 +.text 0x373e0 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d3e0 +_zaf_cc_config 0x8 0x803d3f0 +_cc_handlers_v3 0x1d4 0x803d3f8 +_zw_protocol_cmd_handlers 0x70 0x803d5cc +_zw_protocol_cmd_handlers_lr 0x30 0x803d63c +.ARM.exidx 0x8 0x803d66c +.copy.table 0xc 0x803d674 +.zero.table 0x0 0x803d680 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaedc 0x2000159c text_application_ram 0x0 0x2000c478 .heap 0x800 0x2000c478 -.internal_storage 0x30000 0x803d648 -.zwave_nvm 0x0 0x806d648 -.nvm 0x8000 0x806d648 +.internal_storage 0x30000 0x803d680 +.zwave_nvm 0x0 0x806d680 +.nvm 0x8000 0x806d680 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1213c 0x0 -.debug_info 0xc1c68e 0x0 -.debug_abbrev 0x27274 0x0 -.debug_loclists 0x2be67 0x0 +.debug_frame 0x12130 0x0 +.debug_info 0xc1ddaa 0x0 +.debug_abbrev 0x271ff 0x0 +.debug_loclists 0x2beda 0x0 .debug_aranges 0x6710 0x0 -.debug_rnglists 0x4c59 0x0 -.debug_line 0x74f23 0x0 -.debug_str 0x8fdea 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xe3f0a2 +.debug_rnglists 0x4c5f 0x0 +.debug_line 0x74ff8 0x0 +.debug_str 0x8fdd3 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xe408ac The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228324 + 228380 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4401C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4401C_REGION_US_LR_size.txt index e7a4f2ecf4..dabbc5bf99 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4401C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4401C_REGION_US_LR_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x373a8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d3a8 -_zaf_cc_config 0x8 0x803d3b8 -_cc_handlers_v3 0x1d4 0x803d3c0 -_zw_protocol_cmd_handlers 0x70 0x803d594 -_zw_protocol_cmd_handlers_lr 0x30 0x803d604 -.ARM.exidx 0x8 0x803d634 -.copy.table 0xc 0x803d63c -.zero.table 0x0 0x803d648 +.text 0x373e0 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d3e0 +_zaf_cc_config 0x8 0x803d3f0 +_cc_handlers_v3 0x1d4 0x803d3f8 +_zw_protocol_cmd_handlers 0x70 0x803d5cc +_zw_protocol_cmd_handlers_lr 0x30 0x803d63c +.ARM.exidx 0x8 0x803d66c +.copy.table 0xc 0x803d674 +.zero.table 0x0 0x803d680 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaedc 0x2000159c text_application_ram 0x0 0x2000c478 .heap 0x800 0x2000c478 -.internal_storage 0x30000 0x803d648 -.zwave_nvm 0x0 0x806d648 -.nvm 0x8000 0x806d648 +.internal_storage 0x30000 0x803d680 +.zwave_nvm 0x0 0x806d680 +.nvm 0x8000 0x806d680 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1213c 0x0 -.debug_info 0xc1c68e 0x0 -.debug_abbrev 0x27274 0x0 -.debug_loclists 0x2be67 0x0 +.debug_frame 0x12130 0x0 +.debug_info 0xc1ddaa 0x0 +.debug_abbrev 0x271ff 0x0 +.debug_loclists 0x2beda 0x0 .debug_aranges 0x6710 0x0 -.debug_rnglists 0x4c59 0x0 -.debug_line 0x74f23 0x0 -.debug_str 0x8fde0 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xe3f098 +.debug_rnglists 0x4c5f 0x0 +.debug_line 0x74ff8 0x0 +.debug_str 0x8fdc9 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xe408a2 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228324 + 228380 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4401C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4401C_REGION_US_size.txt index 4d4950cd61..151ccc3ee9 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4401C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4401C_REGION_US_size.txt @@ -5,42 +5,42 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x373a8 0x8006000 -_zaf_event_distributor_cc_event_handler 0x10 0x803d3a8 -_zaf_cc_config 0x8 0x803d3b8 -_cc_handlers_v3 0x1d4 0x803d3c0 -_zw_protocol_cmd_handlers 0x70 0x803d594 -_zw_protocol_cmd_handlers_lr 0x30 0x803d604 -.ARM.exidx 0x8 0x803d634 -.copy.table 0xc 0x803d63c -.zero.table 0x0 0x803d648 +.text 0x373e0 0x8006000 +_zaf_event_distributor_cc_event_handler 0x10 0x803d3e0 +_zaf_cc_config 0x8 0x803d3f0 +_cc_handlers_v3 0x1d4 0x803d3f8 +_zw_protocol_cmd_handlers 0x70 0x803d5cc +_zw_protocol_cmd_handlers_lr 0x30 0x803d63c +.ARM.exidx 0x8 0x803d66c +.copy.table 0xc 0x803d674 +.zero.table 0x0 0x803d680 .stack 0x1000 0x20000000 .data 0x59c 0x20001000 .bss 0xaedc 0x2000159c text_application_ram 0x0 0x2000c478 .heap 0x800 0x2000c478 -.internal_storage 0x30000 0x803d648 -.zwave_nvm 0x0 0x806d648 -.nvm 0x8000 0x806d648 +.internal_storage 0x30000 0x803d680 +.zwave_nvm 0x0 0x806d680 +.nvm 0x8000 0x806d680 .ARM.attributes 0x36 0x0 .comment 0x45 0x0 .debug_line_str 0x29a 0x0 -.debug_frame 0x1213c 0x0 -.debug_info 0xc1c68e 0x0 -.debug_abbrev 0x27274 0x0 -.debug_loclists 0x2be67 0x0 +.debug_frame 0x12130 0x0 +.debug_info 0xc1ddaa 0x0 +.debug_abbrev 0x271ff 0x0 +.debug_loclists 0x2beda 0x0 .debug_aranges 0x6710 0x0 -.debug_rnglists 0x4c59 0x0 -.debug_line 0x74f23 0x0 -.debug_str 0x8fdea 0x0 -.debug_loc 0x2c382 0x0 -.debug_ranges 0x4e30 0x0 -Total 0xe3f0a2 +.debug_rnglists 0x4c5f 0x0 +.debug_line 0x74ff8 0x0 +.debug_str 0x8fdd3 0x0 +.debug_loc 0x2c34a 0x0 +.debug_ranges 0x4e68 0x0 +Total 0xe408ac The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228324 + 228380 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 32768 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) diff --git a/protocol/z-wave/Apps/bin/demos.xml b/protocol/z-wave/Apps/bin/demos.xml index a98f3c8f92..fb18159ea0 100644 --- a/protocol/z-wave/Apps/bin/demos.xml +++ b/protocol/z-wave/Apps/bin/demos.xml @@ -7,7 +7,7 @@ - + ota Bootloader for BRD2705A board @@ -16,7 +16,7 @@ - + ota Bootloader for BRD4200A board @@ -25,7 +25,7 @@ - + ota Bootloader for BRD4201C board @@ -34,7 +34,7 @@ - + ota Bootloader for BRD4201D board @@ -43,7 +43,7 @@ - + ota Bootloader for BRD4202A board @@ -52,7 +52,7 @@ - + ota Bootloader for BRD4204A board @@ -61,7 +61,7 @@ - + ota Bootloader for BRD4204B board @@ -70,7 +70,7 @@ - + ota Bootloader for BRD4204C board @@ -79,7 +79,7 @@ - + ota Bootloader for BRD4204D board @@ -88,7 +88,7 @@ - + ota Bootloader for BRD4205A board @@ -97,7 +97,7 @@ - + ota Bootloader for BRD4205B board @@ -106,7 +106,7 @@ - + ota Bootloader for BRD4207A board @@ -115,7 +115,7 @@ - + ota Bootloader for BRD4209A board @@ -124,7 +124,7 @@ - + ota Bootloader for BRD4210A board @@ -133,7 +133,7 @@ - + ota Bootloader for BRD4400C board @@ -142,7 +142,7 @@ - + ota Bootloader for BRD4401C board @@ -151,7 +151,7 @@ - + otw Bootloader for BRD2603A board @@ -160,7 +160,7 @@ - + otw Bootloader for BRD2705A board @@ -169,7 +169,7 @@ - + otw Bootloader for BRD4200A board @@ -178,7 +178,7 @@ - + otw Bootloader for BRD4201A board @@ -187,7 +187,7 @@ - + otw Bootloader for BRD4202A board @@ -196,7 +196,7 @@ - + otw Bootloader for BRD4204A board @@ -205,7 +205,7 @@ - + otw Bootloader for BRD4204B board @@ -214,7 +214,7 @@ - + otw Bootloader for BRD4204C board @@ -223,7 +223,7 @@ - + otw Bootloader for BRD4204D board @@ -232,7 +232,7 @@ - + otw Bootloader for BRD4205A board @@ -241,7 +241,7 @@ - + otw Bootloader for BRD4205B board @@ -250,7 +250,7 @@ - + otw Bootloader for BRD4206A board @@ -259,7 +259,7 @@ - + otw Bootloader for BRD4207A board @@ -268,7 +268,7 @@ - + otw Bootloader for BRD4208A board @@ -277,7 +277,7 @@ - + otw Bootloader for BRD4209A board @@ -286,7 +286,7 @@ - + otw Bootloader for BRD4210A board @@ -295,7 +295,7 @@ - + otw Bootloader for BRD4400C board @@ -304,7 +304,7 @@ - + otw Bootloader for BRD4401C board @@ -313,6 +313,6 @@ - + diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2603A.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2603A.gbl index f3ced5f3e5..e24a797003 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2603A.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2603A.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:88be6f80a536be1841f6789206b3569a9a0d0badbde7986c85d38b3f00a0041e -size 137668 +oid sha256:0d9fa97f64f45ae1f5011f151c6e4d52d3621dfd734d9c454586b8da23cc9758 +size 137792 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2603A_v255.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2603A_v255.gbl index ba015e6d00..12df425e29 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2603A_v255.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2603A_v255.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b291a49b5c2c408ef40aa9cc760d6e639536e8af854d03657c5fbf763e0f4d86 -size 137668 +oid sha256:4becd307cad506fcc47524f774fb733ba035e8680a1773eb349a02f18e0790e9 +size 137788 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2705A.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2705A.gbl index 28db1c6199..cb63e5aad9 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2705A.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2705A.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:05814bfcac7597a6961b265049784152c5dcf6aa50d39bcc3c79f3e96b91d443 -size 138564 +oid sha256:f7538307c7c92a95f23e4f2d61fc78661cb3beeb0c967ee49a42c569578701c9 +size 138620 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2705A_v255.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2705A_v255.gbl index 2a6262bde5..9c9769e315 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2705A_v255.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2705A_v255.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:acb36cacf5c97a3571da05370e5484b4323ef5999af9f30749bf5130298acdd0 -size 138560 +oid sha256:06c13729264c2b719e45366d01e15cae4d4ea0fecd9a8231faefbe1337c64616 +size 138620 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4201A.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4201A.gbl index fda2821fea..6cd606b292 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4201A.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4201A.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:151f4a92ea8f4abfc822089f67ce3ca149655452d8d849e0484691821cb5e8ac -size 174616 +oid sha256:0959625f35b814b984aaefe2b9c3d5f25672b311815b524b7cfcd38a46243946 +size 174640 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4201A_v255.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4201A_v255.gbl index 23f7d79d60..d8554d46e9 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4201A_v255.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4201A_v255.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9ccf2b2151d1be4d14ab00483cafdc7458b798749236af659407640559bb864d -size 174612 +oid sha256:07d786e27062042c7207317a1252c670d4c8c442dc8e9e661c4becb547c4382a +size 174632 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4202A.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4202A.gbl index 19f28be18c..ed38e41fc1 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4202A.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4202A.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:aba2c6503f6a783b3c711c68b4dc7cbc9bab4e8df12367079802c5bebdb6f043 -size 176720 +oid sha256:c59e29d031118f2f901f024d9436e006d5907d92535ed9160ca0392d8cab4094 +size 176764 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4202A_v255.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4202A_v255.gbl index b31c6dc6b7..9aadc9ff4c 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4202A_v255.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4202A_v255.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:408fa78ad1939f062b62ffb46f6a5136ecc6d2e6eb8cb0028418b61441903cb4 -size 176720 +oid sha256:cfbd71ec3129ec81c322d6af00f2f7832c956645edbd1b338c5c10ff5ad05601 +size 176760 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204C.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204C.gbl index 86c0a95875..26f0c10e51 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204C.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204C.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c1b1b67fefc84077de15eed2f9aa0a51b3f1348b887e02495794714df588a2b0 -size 137076 +oid sha256:9f29175258835c16b84b7266ad5403b43f53fef86784ff7a39e58a2ecaac71ef +size 137140 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204C_v255.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204C_v255.gbl index a58ea2c66b..883aa0a9b7 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204C_v255.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204C_v255.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:80be004d76d676e48648d81e1fbc3f1cd067d0eac5758cff3941cae20d7504fd -size 137068 +oid sha256:99866b29367b99c304e1fe6e56ab939e4d3d8f88b0c8df7937f12685f2d6b9a0 +size 137140 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204D.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204D.gbl index 9def794ddc..79feda075f 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204D.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204D.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2cf0790e731f2d83392923d94c35767a14ef5f00ea9abe431b2837bc8bd51ca6 -size 137232 +oid sha256:85bb40601803a4e355f0a479be13ffa9c9fdd3ffacc2c5c7891f5a703ee1e94a +size 137312 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204D_v255.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204D_v255.gbl index 3c51a0104b..5772fcbad7 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204D_v255.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204D_v255.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c6f9398af9bc7376547424f0ead896d8011ed725d829811110afa192e9cebdf5 -size 137228 +oid sha256:69b72c42a7f88d4cc9004b22272a8ebf65cf87c8796bb0760aa5bdff46e2c544 +size 137304 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4205A.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4205A.gbl index 611ebffd0f..374dee89ac 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4205A.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4205A.gbl @@ -1,3 +1,3 @@ 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a/protocol/z-wave/Apps/bin/gbl/zwave_soc_wall_controller_BRD4401C.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_soc_wall_controller_BRD4401C.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:84b3520f6bd2c82b75175fcf86fece9809114c3bcbccdaeb1f073f1d35060c2b -size 148276 +oid sha256:e0bd7ea7f0cc39f5be1ed9a4b1216ca5901701445736fad840b4e2190c346a26 +size 148304 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_soc_wall_controller_BRD4401C_v255.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_soc_wall_controller_BRD4401C_v255.gbl index 28b2d66792..87b6fbb2cf 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_soc_wall_controller_BRD4401C_v255.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_soc_wall_controller_BRD4401C_v255.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3ed97ae1730ffb5db76a14f739d64a2e1df9194a83af136a91ea6b62f118e310 -size 148272 +oid sha256:370863973a7d23934f22bdf8c25afad531ea16b00ff936d717427a0b1597e8d8 +size 148300 diff --git a/protocol/z-wave/Apps/zwave_ncp_serial_api/serialapi_file.c b/protocol/z-wave/Apps/zwave_ncp_serial_api/serialapi_file.c index e0c4dab83e..99a13724a0 100644 --- a/protocol/z-wave/Apps/zwave_ncp_serial_api/serialapi_file.c +++ b/protocol/z-wave/Apps/zwave_ncp_serial_api/serialapi_file.c @@ -106,10 +106,6 @@ typedef struct __attribute__((packed)) SApplicationConfiguration // Must be pac static void WriteDefault(void); -// Application file system -static zpal_nvm_handle_t pFileSystemApplication; - - static void WriteDefaultApplicationConfiguration(void); static bool ObjectExist(zpal_nvm_object_key_t key); @@ -127,8 +123,8 @@ static void SerialAPI_FileSystemMigrationManagement(void) { //Read present file system version file - uint32_t presentFilesysVersion; - uint32_t expectedFilesysVersion; // This will hold the file system version that current SW will support. + uint32_t presentFilesysVersion = 0; + uint32_t expectedFilesysVersion = 0; // This will hold the file system version that current SW will support. SerialAPI_GetZWVersion(&presentFilesysVersion); @@ -153,17 +149,17 @@ SerialAPI_FileSystemMigrationManagement(void) //Get length of legacy file size_t dataLen; - zpal_nvm_get_object_size(pFileSystemApplication, FILE_ID_APPLICATIONCONFIGURATION, &dataLen); + ZAF_nvm_app_get_object_size(FILE_ID_APPLICATIONCONFIGURATION, &dataLen); //Read legacy file to first members of tApplicationConfiguration SApplicationConfiguration_v7_15_3 tApplicationConfiguration = { 0 }; // Initialize, since zpal_nvm_read() might fail. - zpal_nvm_read(pFileSystemApplication, FILE_ID_APPLICATIONCONFIGURATION, &tApplicationConfiguration, dataLen); + ZAF_nvm_app_read(FILE_ID_APPLICATIONCONFIGURATION, &tApplicationConfiguration, dataLen); //Write default values to new members of tApplicationConfiguration and update the file. tApplicationConfiguration.radio_debug_enable = 0; tApplicationConfiguration.maxTxPower = 140; - zpal_status_t status = zpal_nvm_write(pFileSystemApplication, FILE_ID_APPLICATIONCONFIGURATION, &tApplicationConfiguration, + zpal_status_t status = ZAF_nvm_app_write(FILE_ID_APPLICATIONCONFIGURATION, &tApplicationConfiguration, sizeof(tApplicationConfiguration)); if (ZPAL_STATUS_OK == status) { @@ -178,7 +174,7 @@ SerialAPI_FileSystemMigrationManagement(void) SApplicationConfiguration_V7_18_1 tApplicationConfiguration = { 0 }; zpal_status_t status; - status = zpal_nvm_read(pFileSystemApplication, FILE_ID_APPLICATIONCONFIGURATION, &tApplicationConfiguration_v7_15_3, + status = ZAF_nvm_app_read(FILE_ID_APPLICATIONCONFIGURATION, &tApplicationConfiguration_v7_15_3, sizeof(tApplicationConfiguration_v7_15_3)); if (ZPAL_STATUS_OK != status) { @@ -192,7 +188,7 @@ SerialAPI_FileSystemMigrationManagement(void) tApplicationConfiguration.radio_debug_enable = tApplicationConfiguration_v7_15_3.radio_debug_enable; tApplicationConfiguration.maxTxPower = tApplicationConfiguration_v7_15_3.maxTxPower; - status = zpal_nvm_write(pFileSystemApplication, FILE_ID_APPLICATIONCONFIGURATION, &tApplicationConfiguration, + status = ZAF_nvm_app_write(FILE_ID_APPLICATIONCONFIGURATION, &tApplicationConfiguration, sizeof(tApplicationConfiguration)); /* Do not use FILE_SIZE_APPLICATIONCONFIGURATION in * migration functions, instead hard-code the size as * sizes do change with FW upgrades. */ diff --git a/protocol/z-wave/Apps/zwave_soc_door_lock_keypad/README.md b/protocol/z-wave/Apps/zwave_soc_door_lock_keypad/README.md index 61f4f58016..70b0fe3fc8 100644 --- a/protocol/z-wave/Apps/zwave_soc_door_lock_keypad/README.md +++ b/protocol/z-wave/Apps/zwave_soc_door_lock_keypad/README.md @@ -93,7 +93,9 @@ X: For Z-Wave node count is equal to 5 and for Z-Wave Long Range it is 1. ## Usage of Buttons and LED Status -The following buttons and LEDs are used. +To use the sample app, the BRD8029A Button and LEDs Expansion Board must be used. BTN0-BTN3 and LED0-LED3 refer to the buttons and LEDs on the Expansion Board. + +The following LEDs and buttons shown in the next table below are used. diff --git a/protocol/z-wave/Apps/zwave_soc_power_strip/README.md b/protocol/z-wave/Apps/zwave_soc_power_strip/README.md index 1623cd31cb..7c11387b9b 100644 --- a/protocol/z-wave/Apps/zwave_soc_power_strip/README.md +++ b/protocol/z-wave/Apps/zwave_soc_power_strip/README.md @@ -206,6 +206,8 @@ Y: For Z-Wave node count is equal to 5 and for Z-Wave Long Range it is 0. ## Usage of Buttons and LED Status +To use the sample app, the BRD8029A Button and LEDs Expansion Board must be used. BTN0-BTN3 and LED0-LED3 refer to the buttons and LEDs on the Expansion Board. + The following LEDs and buttons shown in the next table below are used.
diff --git a/protocol/z-wave/Apps/zwave_soc_sensor_pir/README.md b/protocol/z-wave/Apps/zwave_soc_sensor_pir/README.md index 0801f53a42..df1391d3d1 100644 --- a/protocol/z-wave/Apps/zwave_soc_sensor_pir/README.md +++ b/protocol/z-wave/Apps/zwave_soc_sensor_pir/README.md @@ -88,6 +88,10 @@ Y: For Z-Wave node count is equal to 5 and for Z-Wave Long Range it is 0. ## Usage of Buttons and LED Status +To use the sample app, the BRD8029A Button and LEDs Expansion Board must be used. BTN0-BTN3 and LED0-LED3 refer to the buttons and LEDs on the Expansion Board. + +The following LEDs and buttons shown in the next table below are used. +
diff --git a/protocol/z-wave/Apps/zwave_soc_switch_on_off/README.md b/protocol/z-wave/Apps/zwave_soc_switch_on_off/README.md index d335efaf0a..02eeb82694 100644 --- a/protocol/z-wave/Apps/zwave_soc_switch_on_off/README.md +++ b/protocol/z-wave/Apps/zwave_soc_switch_on_off/README.md @@ -70,6 +70,10 @@ X: For Z-Wave node count is equal to 5 and for Z-Wave Long Range it is 1. ## Usage of Buttons and LED Status +To use the sample app, the BRD8029A Button and LEDs Expansion Board must be used. BTN0-BTN3 and LED0-LED3 refer to the buttons and LEDs on the Expansion Board. + +The following LEDs and buttons shown in the next table below are used. +
Button
diff --git a/protocol/z-wave/Apps/zwave_soc_wall_controller/README.md b/protocol/z-wave/Apps/zwave_soc_wall_controller/README.md index 463cf6df25..a531e3c253 100644 --- a/protocol/z-wave/Apps/zwave_soc_wall_controller/README.md +++ b/protocol/z-wave/Apps/zwave_soc_wall_controller/README.md @@ -101,7 +101,9 @@ Y: For Z-Wave node count is equal to 5 and for Z-Wave Long Range it is 0. ## Usage of Buttons and LED Status -The following buttons and LEDs are used. +To use the sample app, the BRD8029A Button and LEDs Expansion Board must be used. BTN0-BTN3 and LED0-LED3 refer to the buttons and LEDs on the Expansion Board. + +The following LEDs and buttons shown in the next table below are used.
Button
diff --git a/protocol/z-wave/NonCertifiableApps/zwave_soc_led_bulb/README.md b/protocol/z-wave/NonCertifiableApps/zwave_soc_led_bulb/README.md index a89ecb9425..16d24e3007 100644 --- a/protocol/z-wave/NonCertifiableApps/zwave_soc_led_bulb/README.md +++ b/protocol/z-wave/NonCertifiableApps/zwave_soc_led_bulb/README.md @@ -80,7 +80,9 @@ X: For Z-Wave node count is equal to 5 and for Z-Wave Long Range it is 1. ## Usage of Buttons and LED Status -The following LEDs and buttons shown in the table below are used. +To use the sample app, the BRD8029A Button and LEDs Expansion Board must be used. BTN0-BTN3 and LED0-LED3 refer to the buttons and LEDs on the Expansion Board. + +The following LEDs and buttons shown in the next table below are used.
diff --git a/protocol/z-wave/NonCertifiableApps/zwave_soc_multilevel_sensor/README.md b/protocol/z-wave/NonCertifiableApps/zwave_soc_multilevel_sensor/README.md index 10b800ffb7..96e679563c 100644 --- a/protocol/z-wave/NonCertifiableApps/zwave_soc_multilevel_sensor/README.md +++ b/protocol/z-wave/NonCertifiableApps/zwave_soc_multilevel_sensor/README.md @@ -74,6 +74,8 @@ can be read, triggered from other Z-Wave devices ## Usage of Buttons and LED Status +To use the sample app, the BRD8029A Button and LEDs Expansion Board must be used. BTN0-BTN3 and LED0-LED3 refer to the buttons and LEDs on the Expansion Board. + The following LEDs and buttons shown in the next table below are used.
diff --git a/protocol/z-wave/ZAF/ApplicationUtilities/TrueStatusEngine/ZAF_TSE.c b/protocol/z-wave/ZAF/ApplicationUtilities/TrueStatusEngine/ZAF_TSE.c index ef852da5d1..582ccf8399 100644 --- a/protocol/z-wave/ZAF/ApplicationUtilities/TrueStatusEngine/ZAF_TSE.c +++ b/protocol/z-wave/ZAF/ApplicationUtilities/TrueStatusEngine/ZAF_TSE.c @@ -190,42 +190,6 @@ bool ZAF_TSE_Trigger(zaf_tse_callback_t pCallback, return true; } -/** - * Checks whether Multi Channel encapsulation should be applied to an outgoing - * status report. - * - * @param[in] source_endpoint The Endpoint whence the state change originates - * @param[in] destination_node_id The ID of the Node that needs to be notified - */ -static inline bool -ShouldUseMultiChannelEncapsulation(uint8_t source_endpoint, - uint16_t destination_node_id) -{ - // The Root Endpoint does not need Multi Channel encapsulation - if (source_endpoint == 0) { - return false; - } - - /** - * CC:008E.02.00.21.008, CC:008E.03.00.11.001, CC:008E.03.00.21.002: - * A Root Device must not use Multi Channel encapsulation when - * communicating to another Root Device. - * - * Find the relevant association based on the destination Node ID and include - * the source Endpoint in the outgoing frame only if this is a Multi Channel - * Association. - */ - MULTICHAN_NODE_ID* pList = NULL; - uint8_t ListLen = 0; - handleAssociationGetnodeList(ZAF_TSE_GROUP_ID, 0, &pList, &ListLen); - for (uint8_t i = 0; i < ListLen; ++i) { - if (pList[i].node.nodeId == destination_node_id) { - return pList[i].nodeInfo.BitMultiChannelEncap; - } - } - return false; -} - static void InvokeRegisteredCallback(void) { DPRINTF("\r\n%s():", __func__); @@ -236,6 +200,18 @@ static void InvokeRegisteredCallback(void) DPRINTF("\tTSE transmit call back for dest node %d endpoint %d\r\n", pCurrentTrigger->pCurrentNode->node.nodeId, pCurrentTrigger->pCurrentNode->node.endpoint); + /** + * CC:008E.02.00.21.008, CC:008E.03.00.11.001, CC:008E.03.00.21.002: + * A Root Device must not use Multi Channel encapsulation when + * communicating to another Root Device. + * + * Set the Source Endpoint only if the Association is Multi Channel, to avoid + * incorrectly applying encapsulation for "plain" Associations later. + */ + const uint8_t source_endpoint = + pCurrentTrigger->pCurrentNode->nodeInfo.BitMultiChannelEncap == 1 + ? RxOptions.destNode.endpoint : 0; + /* Build a txOptionEx */ zaf_tx_options_t tx_options; @@ -243,9 +219,7 @@ static void InvokeRegisteredCallback(void) tx_options.dest_endpoint = pCurrentTrigger->pCurrentNode->node.endpoint; tx_options.bit_addressing = pCurrentTrigger->pCurrentNode->node.BitAddress; tx_options.security_key = pCurrentTrigger->pCurrentNode->nodeInfo.security; - tx_options.source_endpoint = ShouldUseMultiChannelEncapsulation( - RxOptions.destNode.endpoint, pCurrentTrigger->pCurrentNode->node.nodeId) - ? RxOptions.destNode.endpoint : 0; + tx_options.source_endpoint = source_endpoint; tx_options.tx_options = TRANSMIT_OPTION_ACK | TRANSMIT_OPTION_EXPLORE | ZWAVE_PLUS_TX_OPTIONS; if (RxOptions.rxStatus & RECEIVE_STATUS_LOW_POWER) { diff --git a/protocol/z-wave/ZWave/lib/libZWaveController_700s.a b/protocol/z-wave/ZWave/lib/libZWaveController_700s.a index 5ad9105d4a..9b69bab7b0 100644 --- a/protocol/z-wave/ZWave/lib/libZWaveController_700s.a +++ b/protocol/z-wave/ZWave/lib/libZWaveController_700s.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e710ed369f4c360fb14da364a46308d44e5cae408a60b61cd525638d57d64141 -size 4147922 +oid sha256:c74e7f4961addc7a051edf739e8274206792119266fcd9ff1a0a746ad884e070 +size 4148730 diff --git a/protocol/z-wave/ZWave/lib/libZWaveController_800s.a b/protocol/z-wave/ZWave/lib/libZWaveController_800s.a index 366d2dca7c..b8a8a781df 100644 --- a/protocol/z-wave/ZWave/lib/libZWaveController_800s.a +++ b/protocol/z-wave/ZWave/lib/libZWaveController_800s.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:75f1f3a703882cfa28cae28afe4f8438e58bb214c6edef94b6399a9f9626a8cc -size 4141204 +oid sha256:dbda1b3ef722b874965c7b3ade13a5dfc32cd7f15f78f6671e476c7fe60b2126 +size 4142060 diff --git a/protocol/z-wave/ZWave/lib/libZWaveSlave_700s.a b/protocol/z-wave/ZWave/lib/libZWaveSlave_700s.a index 760b13c90f..1403ca1f69 100644 --- a/protocol/z-wave/ZWave/lib/libZWaveSlave_700s.a +++ b/protocol/z-wave/ZWave/lib/libZWaveSlave_700s.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cdec8466c0bdbe5e70f2c557938c5680a49136c89b9484d94efa2155c83c45c8 -size 7165578 +oid sha256:b52fcc7cdf0e606c857d0a1900e2eff273950b2ee9cbbdf55023f3a3253387dc +size 7165126 diff --git a/protocol/z-wave/ZWave/lib/libZWaveSlave_800s.a b/protocol/z-wave/ZWave/lib/libZWaveSlave_800s.a index d938e8f937..8685427997 100644 --- a/protocol/z-wave/ZWave/lib/libZWaveSlave_800s.a +++ b/protocol/z-wave/ZWave/lib/libZWaveSlave_800s.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3cca49bcbf09aad773e78edb3fecf9ebc6fbd8662f64f016edd410b2939a26c1 -size 7109310 +oid sha256:fd56a4b34cad0dab1e8cc7b2dac8cfc91c3cf73bdf13c2a9ec58292ec144a93c +size 7108914 diff --git a/protocol/z-wave/component/zw_versions.slcc b/protocol/z-wave/component/zw_versions.slcc index e6de549da8..7acdead990 100644 --- a/protocol/z-wave/component/zw_versions.slcc +++ b/protocol/z-wave/component/zw_versions.slcc @@ -18,21 +18,21 @@ define: - name: ZW_VERSION_MINOR value: 21 - name: ZW_VERSION_PATCH - value: 1 + value: 2 # Z-Wave Plus Framework and Apps - name: ZAF_VERSION_MAJOR value: 10 - name: ZAF_VERSION_MINOR value: 21 - name: ZAF_VERSION_PATCH - value: 1 + value: 2 # SDK - name: SDK_VERSION_MAJOR value: 7 - name: SDK_VERSION_MINOR value: 21 - name: SDK_VERSION_PATCH - value: 1 + value: 2 config_file: - path: protocol/z-wave/platform/SiliconLabs/PAL/config/version/zw_version_config.h file_id: version_config diff --git a/protocol/z-wave/studio-docs/docs.xml b/protocol/z-wave/docs_public/docs.xml similarity index 93% rename from protocol/z-wave/studio-docs/docs.xml rename to protocol/z-wave/docs_public/docs.xml index 169a536cfb..283cb4466a 100644 --- a/protocol/z-wave/studio-docs/docs.xml +++ b/protocol/z-wave/docs_public/docs.xml @@ -1,12 +1,12 @@ - + This MS Excel file describes how to measure the Tx power of a Z-Wave frame and use this to calibrate the Tx Power of your final Z-Wave product. - + Describes how to use the Tiny App for upgrading Secure Element firmware. @@ -48,37 +48,37 @@ - + ZGM130S SIP Module Datasheet - + EFR32ZG14 Z-Wave 700 Modem SoC Data Sheet - + EFR32ZG14 Zen Gecko Z-Wave 700 USB Stick Bridge Module UZB-7 Data Sheet - + Describes the Test Observations (TO) that exists on the development and test tool Z-Wave Zniffer. - + Schematic for the BRD4206A Z-Wave 700 Long Range radio board with EFR32ZG14. - + ZGM130S Long Range Wireless Starter Kit User's Guide @@ -96,37 +96,37 @@ - + Discusses the latest changes to the PC-based Zniffer tool and lists new features. - + Discusses the latest changes to the PC-based Controller code and lists new features. - + Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the Silicon Labs Z-Wave SDK and associated utilities, including added/deleted/deprecated features/API, and lists fixed and known issues. - + Development Material for UZB-7. - + Schematic for the BRD4207A Z-Wave 700 Long Range radio board with ZGM130S. - + PCB documentation for UZB-7 PCB. @@ -138,19 +138,19 @@ - + Z-Wave gbl files - + Important Changes in Z-Wave SDK in latest release - + Describes the Z-Wave Certification process for the Z-Wave 700 products and serves as a guide on where to find additional information. @@ -234,7 +234,7 @@ - + Z-Wave HTML documentation diff --git a/protocol/z-wave/esf.properties b/protocol/z-wave/esf.properties index 2de6a5f2fd..94ba32b8a2 100644 --- a/protocol/z-wave/esf.properties +++ b/protocol/z-wave/esf.properties @@ -3,7 +3,7 @@ id=com.silabs.sdk.stack.zwave label=Z-Wave SDK description=Silicon Labs Z-Wave SDK for the EFR32 family -version=7.21.1.0 +version=7.21.2.0 #Build Information @@ -12,7 +12,7 @@ buildNumber=0 # Note: this particular string must be escaped -prop.subLabel=Z-Wave\\ SDK\\ 7.21.1.0 +prop.subLabel=Z-Wave\\ SDK\\ 7.21.2.0 # Path to side-package properties file extendedProperties=efr32zg13l.properties efr32zg13p.properties efr32zg13s.properties @@ -21,7 +21,7 @@ extendedProperties=efr32zg13l.properties efr32zg13p.properties efr32zg13s.proper prop.file.templatesFile=z-wave_production_templates.xml z-wave_alpha_templates.xml z-wave_beta_templates.xml z-wave_test_templates.xml z-wave_internal_templates.xml z-wave_development_templates.xml # ---- Documents ---- -prop.file.docsFile=studio-docs/docs.xml +prop.file.docsFile=docs_public/docs.xml # ---- Demos --- prop.file.demosFile=Apps/bin/demos.xml z-wave_production_demos.xml z-wave_alpha_demos.xml z-wave_beta_demos.xml z-wave_test_demos.xml z-wave_internal_demos.xml z-wave_development_demos.xml diff --git a/protocol/z-wave/important_changes.md b/protocol/z-wave/important_changes.md index 9a258d788a..0aee7164f2 100644 --- a/protocol/z-wave/important_changes.md +++ b/protocol/z-wave/important_changes.md @@ -3,6 +3,12 @@ The changes described in this file will possibly break the build and/or functionality of an existing application. The description serves the purpose of helping to fix the failing build. +# 7.21.2 {#section-7-21-2} + +## Fix migration process from 7.17 to 7.18+ +The migration process of the controller is broken since 7.18.1. Restore this migration process. +This process is used when a controller is updated from a version older than 7.18 to 7.18 or newer. + # 7.21.1 {#section-7-21-1} ## Support diff --git a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13l231f512gm32_zniffer.a b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13l231f512gm32_zniffer.a index 80806a7241..110c17c9a0 100644 --- a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13l231f512gm32_zniffer.a +++ b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13l231f512gm32_zniffer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c6bc856d42c8c97b16b4246403d0cb69c721eae58821fefa5b8b197c19cb0189 +oid sha256:275826bc00f6612814858b364324f9aae11dd7b411bfe072e509122779df94ff size 478162 diff --git a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13l231f512gm32_zniffer_app.a b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13l231f512gm32_zniffer_app.a index 6aca475704..6ea5ded2b9 100644 --- a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13l231f512gm32_zniffer_app.a +++ b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13l231f512gm32_zniffer_app.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6314484b5bf99067991b24cf31cdd8131214f9821b580189a92a5fcd033df536 +oid sha256:85a70314981ac20766c875048ee2377d098a86a32550fa7c524ac4494c499cdd size 501094 diff --git a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13l231f512im32_zniffer.a b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13l231f512im32_zniffer.a index 4cde8e28c9..3a32ed071a 100644 --- a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13l231f512im32_zniffer.a +++ b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13l231f512im32_zniffer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:09e1115da730aacf52425b0932abf54e8a79e96f9772a2689de5e91ddddeddcd +oid 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a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13p231f512gm64_zniffer.a +++ b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13p231f512gm64_zniffer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8e1c729cefc337ad18e32581181220fb81ca38f0d1dd9999d70b61fef9a5423b +oid sha256:4364d4902a3dc13a786b8b3327db93981b82bac2573b78c4e1003f46a32e652b size 478162 diff --git a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13p231f512gm64_zniffer_app.a b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13p231f512gm64_zniffer_app.a index 8af8411b51..c08160f6d2 100644 --- a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13p231f512gm64_zniffer_app.a +++ b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg13p231f512gm64_zniffer_app.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4204b7cede65102bca09a215a7064b37ff95eb52d61dbcb0c96761a9465f9963 +oid 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a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_zgm230sb27hnn.a +++ b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_zgm230sb27hnn.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:91f4d9bb0c684dd2bb3852eef8c87db12a43a186afe216178e9a13e7e3e10f31 +oid sha256:174b5735ca3563e718ad20e00bc730c0ea55d8af7a1d61f3b378ebc6ddfb32b7 size 540584 diff --git a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_zgm230sb27hnn_zniffer.a b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_zgm230sb27hnn_zniffer.a index c626f0ab63..ecdc10de57 100644 --- a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_zgm230sb27hnn_zniffer.a +++ b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_zgm230sb27hnn_zniffer.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fa0ce8b9165f618577eb4d8108ec9a987cb67e973a30335f834798a5fd634602 +oid sha256:20707c3764cacaa873368fca2e6a3b361765502011289bbc9abe3acce8073f1a size 518004 diff --git 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+97,7 @@ - + @@ -110,7 +110,7 @@ - + @@ -123,7 +123,7 @@ - + @@ -136,7 +136,7 @@ - + @@ -149,7 +149,7 @@ - + @@ -162,7 +162,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -188,7 +188,7 @@ - + @@ -201,7 +201,7 @@ - + @@ -214,7 +214,7 @@ - + @@ -227,7 +227,7 @@ - + @@ -240,7 +240,7 @@ - + @@ -253,7 +253,7 @@ - + @@ -266,7 +266,7 @@ - + @@ -279,7 +279,7 @@ - + @@ -292,7 +292,7 @@ - + @@ -305,7 +305,7 @@ - + @@ -318,7 +318,7 @@ - + @@ -331,7 +331,7 @@ - + @@ -344,7 +344,7 @@ - + @@ -357,7 +357,7 @@ - + @@ -370,7 +370,7 @@ - + @@ -383,7 +383,7 @@ - + @@ -396,7 +396,7 @@ - + @@ -409,7 +409,7 @@ - + @@ -422,7 +422,7 @@ - + @@ -435,7 +435,7 @@ - + @@ -448,7 +448,7 @@ - + @@ -461,7 +461,7 @@ - + @@ -474,7 +474,7 @@ - + @@ -487,7 +487,7 @@ - + @@ -500,7 +500,7 @@ - + @@ -513,7 +513,7 @@ - + @@ -526,7 +526,7 @@ - + @@ -539,7 +539,7 @@ - + @@ -552,7 +552,7 @@ - + @@ -565,7 +565,7 @@ - + @@ -579,7 +579,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -593,7 +593,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -607,7 +607,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -621,7 +621,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -635,7 +635,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -649,7 +649,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -663,7 +663,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -677,7 +677,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -691,7 +691,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -705,7 +705,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -719,7 +719,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -733,7 +733,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -747,7 +747,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -761,7 +761,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -775,7 +775,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -789,7 +789,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -803,7 +803,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -817,7 +817,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -831,7 +831,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -845,7 +845,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -859,7 +859,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -873,7 +873,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -887,7 +887,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -901,7 +901,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -915,7 +915,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -929,7 +929,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -943,7 +943,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -957,7 +957,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -971,7 +971,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -985,7 +985,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -997,7 +997,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1009,7 +1009,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1021,7 +1021,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1033,7 +1033,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1045,7 +1045,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1057,7 +1057,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1070,7 +1070,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1083,7 +1083,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1096,7 +1096,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1109,7 +1109,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1122,7 +1122,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1135,7 +1135,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1148,7 +1148,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1161,7 +1161,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1174,7 +1174,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1187,7 +1187,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1200,7 +1200,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1213,7 +1213,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1226,7 +1226,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1239,7 +1239,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1252,7 +1252,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1265,7 +1265,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1278,7 +1278,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1291,7 +1291,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1304,7 +1304,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1317,7 +1317,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1330,7 +1330,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1343,7 +1343,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1356,7 +1356,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1369,7 +1369,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1382,7 +1382,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1395,7 +1395,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1408,7 +1408,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1421,7 +1421,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1434,7 +1434,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1447,7 +1447,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1460,7 +1460,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1473,7 +1473,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1486,7 +1486,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1499,7 +1499,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1512,7 +1512,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1525,7 +1525,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1538,7 +1538,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1551,7 +1551,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1564,7 +1564,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1577,7 +1577,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1590,7 +1590,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1603,7 +1603,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1616,7 +1616,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1629,7 +1629,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1642,7 +1642,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1655,7 +1655,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1668,7 +1668,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1681,7 +1681,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1694,7 +1694,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1707,7 +1707,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1720,7 +1720,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1733,7 +1733,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1746,7 +1746,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1759,7 +1759,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1772,7 +1772,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1785,7 +1785,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1798,7 +1798,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1811,7 +1811,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1824,7 +1824,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1837,7 +1837,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1850,7 +1850,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1863,7 +1863,7 @@ The Serial API End Device allows the user to create a product with a host applic - + @@ -1877,7 +1877,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -1890,7 +1890,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -1903,7 +1903,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -1916,7 +1916,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -1929,7 +1929,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -1943,7 +1943,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -1956,7 +1956,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -1969,7 +1969,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -1982,7 +1982,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -1995,7 +1995,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2009,7 +2009,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2022,7 +2022,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2035,7 +2035,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2048,7 +2048,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2061,7 +2061,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2074,7 +2074,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2087,7 +2087,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2100,7 +2100,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2113,7 +2113,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2126,7 +2126,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2139,7 +2139,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2152,7 +2152,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2165,7 +2165,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2178,7 +2178,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2191,7 +2191,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2204,7 +2204,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2217,7 +2217,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2230,7 +2230,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2243,7 +2243,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2256,7 +2256,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2269,7 +2269,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2282,7 +2282,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2295,7 +2295,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2308,7 +2308,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2321,7 +2321,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2334,7 +2334,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2347,7 +2347,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2360,7 +2360,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2373,7 +2373,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2386,7 +2386,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2399,7 +2399,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2412,7 +2412,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2425,7 +2425,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2438,7 +2438,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2451,7 +2451,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2464,7 +2464,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2477,7 +2477,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2490,7 +2490,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2503,7 +2503,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2516,7 +2516,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2529,7 +2529,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2542,7 +2542,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2557,7 +2557,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2573,7 +2573,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2588,7 +2588,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2603,7 +2603,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2618,7 +2618,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2633,7 +2633,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2648,7 +2648,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2664,7 +2664,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2679,7 +2679,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2694,7 +2694,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2709,7 +2709,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2724,7 +2724,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2739,7 +2739,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2755,7 +2755,7 @@ This is the EFR32xG28 Explorer Kit specific version of the application. - + @@ -2770,7 +2770,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2785,7 +2785,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2800,7 +2800,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2815,7 +2815,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2830,7 +2830,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2843,7 +2843,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2856,7 +2856,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2869,7 +2869,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2882,7 +2882,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2895,7 +2895,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2908,7 +2908,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2921,7 +2921,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2934,7 +2934,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2947,7 +2947,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2960,7 +2960,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2973,7 +2973,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2986,7 +2986,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -2999,7 +2999,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3012,7 +3012,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3025,7 +3025,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3038,7 +3038,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3051,7 +3051,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3064,7 +3064,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3077,7 +3077,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3090,7 +3090,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3103,7 +3103,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3116,7 +3116,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3129,7 +3129,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3142,7 +3142,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3155,7 +3155,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3168,7 +3168,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3181,7 +3181,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3194,7 +3194,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3207,7 +3207,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3220,7 +3220,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3233,7 +3233,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3246,7 +3246,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3259,7 +3259,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3272,7 +3272,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3285,7 +3285,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3298,7 +3298,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3311,7 +3311,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3324,7 +3324,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3337,7 +3337,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3350,7 +3350,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3363,7 +3363,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3376,7 +3376,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3389,7 +3389,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3402,7 +3402,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3415,7 +3415,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3428,7 +3428,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3441,7 +3441,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3454,7 +3454,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3467,7 +3467,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3480,7 +3480,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3493,7 +3493,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3506,7 +3506,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3519,7 +3519,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3532,7 +3532,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3545,7 +3545,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3558,7 +3558,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3571,7 +3571,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3584,7 +3584,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3597,7 +3597,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3610,7 +3610,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3623,7 +3623,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3636,7 +3636,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3649,7 +3649,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3662,7 +3662,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3675,7 +3675,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3688,7 +3688,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3701,7 +3701,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3714,7 +3714,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3727,7 +3727,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3740,7 +3740,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3753,7 +3753,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3766,7 +3766,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3779,7 +3779,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3792,7 +3792,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3805,7 +3805,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3818,7 +3818,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3831,7 +3831,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3844,7 +3844,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3857,7 +3857,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3870,7 +3870,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3883,7 +3883,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3896,7 +3896,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3909,7 +3909,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3922,7 +3922,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3935,7 +3935,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3948,7 +3948,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3961,7 +3961,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3974,7 +3974,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -3987,7 +3987,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4000,7 +4000,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4013,7 +4013,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4026,7 +4026,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4039,7 +4039,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4052,7 +4052,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4065,7 +4065,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4078,7 +4078,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4091,7 +4091,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4104,7 +4104,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4117,7 +4117,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4130,7 +4130,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4143,7 +4143,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4156,7 +4156,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4169,7 +4169,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4182,7 +4182,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4195,7 +4195,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4208,7 +4208,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4221,7 +4221,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + @@ -4234,7 +4234,7 @@ Endpoint 2 device type - generic type light dimmer switch and specific type ligh - + diff --git a/protocol/zigbee/app/framework/cli/network-cli.c b/protocol/zigbee/app/framework/cli/network-cli.c index 88504da712..c936a45aac 100644 --- a/protocol/zigbee/app/framework/cli/network-cli.c +++ b/protocol/zigbee/app/framework/cli/network-cli.c @@ -17,7 +17,9 @@ #include "app/framework/include/af.h" #include "app/util/serial/sl_zigbee_command_interpreter.h" - +#ifdef SL_COMPONENT_CATALOG_PRESENT +#include "sl_component_catalog.h" +#endif // SL_COMPONENT_CATALOG_PRESENT // TODO: this is to bring in sli_zigbee_af_permit_join() and emberAfGetBindingTableSize() // prototypes. #include "app/framework/util/af-main.h" @@ -29,6 +31,10 @@ #include "app/framework/plugin/zll-commissioning-common/zll-commissioning-common.h" #endif +#ifdef SL_CATALOG_ZIGBEE_PHY_2_4_SUBGHZ_JOINING_END_DEVICE_PRESENT + #include "stack/include/stack-info.h" +#endif // SL_CATALOG_ZIGBEE_PHY_2_4_SUBGHZ_JOINING_END_DEVICE_PRESENT + uint8_t sli_zigbee_af_cli_network_index = EMBER_AF_DEFAULT_NETWORK_INDEX; extern uint8_t sli_zigbee_af_extended_pan_id[]; static void initNetworkParams(EmberNetworkParameters *networkParams, @@ -103,6 +109,15 @@ void networkRejoinCommand(sl_cli_command_arg_t *arguments) uint32_t channelMask = sl_cli_get_argument_uint32(arguments, 1); if (channelMask == 0) { channelMask = EMBER_ALL_802_15_4_CHANNELS_MASK; + // Allow the upper layer to update the rejoin mask incase needed in this callback. + // Why do we need this callback - in SE 1.4 CCB 2637 introduced a device type that is slightly + // different Multi-MAC Selection device called as the Multi-MAC Joining device. + // The Joining Device shall not change the interface during rejoin but the selection device can. + // Since this code is in library of the leaf node with the folloiwng callback it would be able + // update mask for rejoining based on the above device types. + #ifdef SL_CATALOG_ZIGBEE_PHY_2_4_SUBGHZ_JOINING_END_DEVICE_PRESENT + emberUpdateMultiMacRejoinChannelMaskForSelectionOrJoiningDevice(&channelMask); + #endif // SL_CATALOG_ZIGBEE_PHY_2_4_SUBGHZ_JOINING_END_DEVICE_PRESENT } EmberStatus status = emberFindAndRejoinNetworkWithReason(haveCurrentNetworkKey, channelMask, @@ -206,7 +221,7 @@ void networkMultiPhyStartCommand(sl_cli_command_arg_t *arguments) int8_t power = sl_cli_get_argument_int8(arguments, 2); uint8_t optionsMask = 0; - if (sl_cli_get_command_count(arguments) > 3) { + if (sl_cli_get_argument_count(arguments) > 3) { optionsMask = sl_cli_get_argument_uint8(arguments, 3); } diff --git a/protocol/zigbee/app/framework/common/zigbee_app_framework_common.c b/protocol/zigbee/app/framework/common/zigbee_app_framework_common.c index f2e26dda53..11df0c2fdd 100644 --- a/protocol/zigbee/app/framework/common/zigbee_app_framework_common.c +++ b/protocol/zigbee/app/framework/common/zigbee_app_framework_common.c @@ -230,6 +230,13 @@ sl_zigbee_event_t* sli_zigbee_get_event_ptr(sl_zigbee_event_t *event, return event; } +// Event initialisation routine for the event that gets activated from ISRs. +void sl_zigbee_af_isr_event_init(sl_zigbee_event_t *event, + void (*handler)(sl_zigbee_event_t *)) +{ + sl_zigbee_event_init(event, handler); + event->actions.marker = sli_zigbee_isr_event_marker; +} //------------------------------------------------------------------------------ // Callbacks stubs diff --git a/protocol/zigbee/app/framework/common/zigbee_app_framework_event.h b/protocol/zigbee/app/framework/common/zigbee_app_framework_event.h index b9bb45a62d..9eff4a8c75 100644 --- a/protocol/zigbee/app/framework/common/zigbee_app_framework_event.h +++ b/protocol/zigbee/app/framework/common/zigbee_app_framework_event.h @@ -49,6 +49,18 @@ * @code * // Declare event as global * sl_zigbee_event_t my_event; + * sl_zigbee_event_t my_isr_event; + * + * void SOME_IRQHandler(void) + * { + * // Activates the ISR type event from IRQ Handler. + * sl_zigbee_event_set_active(&my_isr_event); + * } + * + * void my_isr_event_handler(sl_zigbee_event_t *event) + * { + * // Event expired, do something + * } * * void my_event_hendler(sl_zigbee_event_t *event) * { @@ -63,6 +75,9 @@ * // Initialize event * sl_zigbee_event_init(&my_event, my_event_handler); * + * // Initialise an event type that can be activated from the ISR. + * sl_zigbee_af_isr_event_init(&my_isr_event, my_isr_event_handler); + * * // Set the event to expire immediately (that is, in the next iteration of the main loop) * sl_zigbee_event_set_active(&my_event); * } @@ -79,6 +94,22 @@ typedef EmberEvent sl_zigbee_event_t; /** @name API */ // @{ +/** @brief Application event initialization routine for events intended to be activated in ISR. + * An event that is activated in ISR context must be initialized using this API. + * Such event can only be scheduled to expire immediately using \ref sl_zigbee_event_set_active. + * The event handler will be executed from DSR context either from the application main loop in + * a bare metal setup or in the Application Framework Task main loop in an OS setup. + * Any attempt to schedule a non zero delay or deactivation for an event initialized as ISR event + * will result in an assert. + * + * @param[in] event A pointer to the \ref sl_zigbee_event_t object to be + * initialized. Event objects must be global. + * + * @param[in] handler Handler function that shall be called when the event runs. + */ +void sl_zigbee_af_isr_event_init(sl_zigbee_event_t *event, + void (*handler)(sl_zigbee_event_t *)); + #if defined(DOXYGEN_SHOULD_SKIP_THIS) /** @brief Application event initialization routine. Every application event * must be initialized. diff --git a/protocol/zigbee/app/framework/plugin-soc/high_datarate_phy/high_datarate_phy.c b/protocol/zigbee/app/framework/plugin-soc/high_datarate_phy/high_datarate_phy.c index 11a47ea252..71261bf45d 100644 --- a/protocol/zigbee/app/framework/plugin-soc/high_datarate_phy/high_datarate_phy.c +++ b/protocol/zigbee/app/framework/plugin-soc/high_datarate_phy/high_datarate_phy.c @@ -21,11 +21,13 @@ #include "ember-multi-network.h" static sl_zigbee_event_t app_cli_event; -#define MIN_PAYLOAD_LEN 3 -#define MAX_PAYLOAD_LEN 252 +#define MIN_PAYLOAD_LEN 2 +#define MAX_PAYLOAD_LEN 251 #define FUTURE_MAX_PAYLOAD_LEN 2049 + +#define LEN_BYTES (2u) // In future parts, there is expected to be support for 2047 byte packets -static uint8_t local_byte_array[FUTURE_MAX_PAYLOAD_LEN]; +static uint8_t local_byte_array[MAX_PAYLOAD_LEN + LEN_BYTES]; static uint32_t high_datarate_phy_rx_packet_count = 0; static uint32_t high_datarate_phy_tx_packet_count = 0; static void app_cli_event_handler(sl_zigbee_event_t *event); @@ -46,7 +48,7 @@ extern void sli_mac_lower_mac_set_high_datarate_phy_radio_priorities (EmberMulti * Default receive callback function for High-BW-phy packets * Note that packet does not include 4 byte CRC * packet[0] packet[1] : 2 byte Length (packet[1] << 8 + packet[0]) - * packet[1] .. packet[Length] payload + * packet[2] .. packet[Length+1] payload * linkQuality of received packet * rssi of received packet * @@ -56,7 +58,7 @@ void sl_high_datarate_phy_rx_cb(uint8_t *packet, uint8_t linkQuality, int8_t rss { high_datarate_phy_rx_packet_count++; sl_zigbee_app_debug_print(" Received Packet : "); - for (uint16_t i = 2; i <= (uint16_t)packet[0] + ((uint16_t)packet[1] << 8); i++ ) { + for (uint16_t i = 2; i < (uint16_t)packet[0] + ((uint16_t)packet[1] << 8) + LEN_BYTES; i++ ) { sl_zigbee_app_debug_print("%02X ", packet[i]); } sl_zigbee_app_debug_println("\nLQI : %d\nRSSI : %d\n", linkQuality, rssi); @@ -80,7 +82,7 @@ void sl_high_datarate_phy_tx_cb(uint8_t mac_index, sl_status_t status, PacketHea sl_zigbee_app_debug_println("\npacket len : %d\n", packet_length); - for (uint16_t i = 2; i <= packet_length; i++) { + for (uint16_t i = 2; i < packet_length + LEN_BYTES; i++) { sl_zigbee_app_debug_print("%02X ", packet_pointer[i]); } @@ -110,7 +112,7 @@ void sli_high_datarate_phy_init(uint8_t init_level) * * @param[in] Function pointer to receive callback * packet[0] packet[1] : 2 byte Length (packet[1] << 8 + packet[0]) - * packet[1] .. packet[Length] payload + * packet[2] .. packet[Length+1] payload * linkQuality of received packet * rssi of received packet * @@ -158,12 +160,12 @@ void sl_high_datarate_phy_config_radio_priorities(EmberMultiprotocolPriorities * } /** - * Transmits a High-BW-Phy packet consisting of bytes of payload + * Transmits a High-BW-Phy packet consisting of bytes of payload * Note that there is a 4 byte CRC which is tacked on later and is not part * of the packet parameter * @param[in] payload Pointer to bytes of transmitted data * packet[0] packet[1] : 2 byte Length (packet[1] << 8 + packet[0]) - * packet[1] .. packet[Length] payload + * packet[2] .. packet[Length+1] payload * * CAUTION: Do not call this function from any other RTOS task context except Zigbee * This fuction manipulates buffers and will cause unpredictable errors if this rule is not @@ -182,9 +184,9 @@ sl_status_t sl_high_datarate_phy_transmit(uint8_t *payload) } /** * CLI Command handler to transmit High-BW-Phy packet - * @param[in] length Transmits a packet that contains bytes using the high-BW-phy + * @param[in] length Transmits a packet that contains bytes using the high-BW-phy * packet[0] packet[1] : 2 byte Length (packet[1] << 8 + packet[0]) - * packet[1] .. packet[Length] payload + * packet[2] .. packet[Length+1] payload */ static uint16_t length; void sl_high_datarate_phy_tx_command(sl_cli_command_arg_t *arguments) @@ -198,15 +200,16 @@ void sl_high_datarate_phy_tx_command(sl_cli_command_arg_t *arguments) * and this cannot be done from anywhere except the zigbee task context in an RTOS * application */ +#include "em_gpio.h" static void app_cli_event_handler(sl_zigbee_event_t *event) { - if ( length > FUTURE_MAX_PAYLOAD_LEN ) { + if ( length > MAX_PAYLOAD_LEN ) { sl_zigbee_app_debug_println("Status = 0x%02x", SL_STATUS_INVALID_PARAMETER); return; } local_byte_array[0] = (uint8_t)(length & 0xFF); local_byte_array[1] = (uint8_t)(length >> 8); - for (uint16_t i = 2; i <= length; i++) { + for (uint16_t i = 2; i < length + LEN_BYTES; i++) { local_byte_array[i] = i - 1; } diff --git a/protocol/zigbee/app/framework/plugin-soc/high_datarate_phy/high_datarate_phy.h b/protocol/zigbee/app/framework/plugin-soc/high_datarate_phy/high_datarate_phy.h index 165c88c50d..97de9fe38b 100644 --- a/protocol/zigbee/app/framework/plugin-soc/high_datarate_phy/high_datarate_phy.h +++ b/protocol/zigbee/app/framework/plugin-soc/high_datarate_phy/high_datarate_phy.h @@ -25,12 +25,12 @@ #include "sl_cli.h" /** - * Transmits a High-BW-Phy packet consisting of bytes of payload + * Transmits a High-BW-Phy packet consisting of bytes of payload * Note that there is a 4 byte CRC which is tacked on later and is not part * of the packet parameter * @param[in] payload Pointer to bytes of transmitted data * packet[0] packet[1] : 2 byte Length (packet[1] << 8 + packet[0]) - * packet[2] .. packet[Length] payload + * packet[2] .. packet[Length+1] payload * * CAUTION: Do not call this function from any other RTOS task context except Zigbee * This calls into a function that manipulates buffers and will cause unpredictable errors if this rule is not @@ -58,7 +58,7 @@ RAIL_Status_t sl_high_datarate_phy_set_reception_enable (bool enable_f); * Note that packet does not include 4 byte CRC. * @param[in] Function pointer to receive callback * packet[0] packet[1] : 2 byte Length (packet[1] << 8 + packet[0]) - * packet[1] .. packet[Length] payload + * packet[2] .. packet[Length+1] payload * linkQuality of received packet * rssi of received packet * @@ -85,7 +85,7 @@ void sl_high_datarate_phy_config_radio_priorities(EmberMultiprotocolPriorities * /** * Default receive callback function for High-BW-phy packets * packet[0] packet[1] : 2 byte Length (packet[1] << 8 + packet[0]) - * packet[1] .. packet[Length] payload + * packet[2] .. packet[Length+1] payload * linkQuality of received packet * rssi of received packet * diff --git a/protocol/zigbee/app/framework/plugin/gas-proxy-function/gas-proxy-function-cli.c b/protocol/zigbee/app/framework/plugin/gas-proxy-function/gas-proxy-function-cli.c index 879b2cec63..14761a150a 100644 --- a/protocol/zigbee/app/framework/plugin/gas-proxy-function/gas-proxy-function-cli.c +++ b/protocol/zigbee/app/framework/plugin/gas-proxy-function/gas-proxy-function-cli.c @@ -1705,7 +1705,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t 0x00, // extended header control field 0x07, 0x09, // extended header cluster id 0x00, 0x11, // extended gbz command length - 0x01, // frame control + 0x11, // frame control 0x00, // trans. seq number 0x00, // ZCL command id - GetEventLog 0x13, // Event Control / Log ID - GPF General Log @@ -1719,7 +1719,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t 0x01, // extended header control field 0x07, 0x09, // extended header cluster id 0x00, 0x11, // extended gbz command length - 0x01, // frame control + 0x11, // frame control 0x01, // trans. seq number 0x00, // ZCL command id - GetEventLog 0x16, // Event Control / Log ID - GSME General Log @@ -1750,7 +1750,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t 0x00, // extended header control field 0x07, 0x09, // extended header cluster id 0x00, 0x11, // extended gbz command length - 0x01, // frame control + 0x11, // frame control 0x00, // trans. seq number 0x00, // ZCL command id - GetEventLog 0x04, // Event Control / Log ID - GPF Security Log @@ -1764,7 +1764,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t 0x01, // extended header control field 0x07, 0x09, // extended header cluster id 0x00, 0x11, // extended gbz command length - 0x01, // frame control + 0x11, // frame control 0x01, // trans. seq number 0x00, // ZCL command id - GetEventLog 0x07, // Event Control / Log ID - GSME Security Log @@ -1957,7 +1957,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t gbzCommand[gbzCommandIndex++] = 0x00; // extended gbz command length gbzCommand[gbzCommandIndex++] = 0x10; - emberAfCopyInt8u(gbzCommand, gbzCommandIndex, 0x01); // frame control + emberAfCopyInt8u(gbzCommand, gbzCommandIndex, 0x11); // frame control gbzCommandIndex += 1; emberAfCopyInt8u(gbzCommand, gbzCommandIndex, i); // trans. seq number gbzCommandIndex += 1; @@ -1985,7 +1985,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t gbzCommand[gbzCommandIndex++] = 0x00; // extended gbz command length gbzCommand[gbzCommandIndex++] = 0x10; - emberAfCopyInt8u(gbzCommand, gbzCommandIndex, 0x01); // frame control + emberAfCopyInt8u(gbzCommand, gbzCommandIndex, 0x11); // frame control gbzCommandIndex += 1; emberAfCopyInt8u(gbzCommand, gbzCommandIndex, i + 12); // trans. seq number gbzCommandIndex += 1; @@ -2032,7 +2032,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t gbzCommand[gbzCommandIndex++] = 0x00; // extended gbz command length gbzCommand[gbzCommandIndex++] = 0x10; - emberAfCopyInt8u(gbzCommand, gbzCommandIndex, 0x01); // frame control + emberAfCopyInt8u(gbzCommand, gbzCommandIndex, 0x11); // frame control gbzCommandIndex += 1; emberAfCopyInt8u(gbzCommand, gbzCommandIndex, i); // trans. seq number gbzCommandIndex += 1; @@ -2060,7 +2060,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t gbzCommand[gbzCommandIndex++] = 0x00; // extended gbz command length gbzCommand[gbzCommandIndex++] = 0x10; - emberAfCopyInt8u(gbzCommand, gbzCommandIndex, 0x01); // frame control + emberAfCopyInt8u(gbzCommand, gbzCommandIndex, 0x11); // frame control gbzCommandIndex += 1; emberAfCopyInt8u(gbzCommand, gbzCommandIndex, i + 12); // trans. seq number gbzCommandIndex += 1; @@ -2118,7 +2118,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t 0x07, 0x05, // extended header cluster id 0x00, 0x08, // extended gbz command length 0x00, 0x00, 0x00, 0x00, // extended header from date (TODO) - 0x01, // frame control + 0x11, // frame control 0x00, // trans. seq number 0x08, // ZCL command id - GetTopUpLog 0xFE, 0xFF, 0xFF, 0xFF, // Latest End Time @@ -2141,7 +2141,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t 0x00, // extended header control field 0x07, 0x00, // extended header cluster id 0x00, 0x27, // extended gbz command length - 0x00, // frame control + 0x10, // frame control 0x00, // trans. seq number 0x00, // ZCL command id - ReadAttributes 0x03, 0x02, // Attribute ID - Block Period: ThresholdDivisor @@ -2167,7 +2167,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t 0x00, // extended header control field 0x07, 0x07, // extended header cluster id 0x00, 0x0D, // extended gbz command length - 0x01, // frame control + 0x11, // frame control 0x01, // trans. seq number 0x01, // ZCL command id - GetDayProfiles 0x00, 0x00, 0x00, 0x00, // Provider ID - unused @@ -2179,7 +2179,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t 0x00, // extended header control field 0x07, 0x07, // extended header cluster id 0x00, 0x0D, // extended gbz command length - 0x01, // frame control + 0x11, // frame control 0x02, // trans. seq number 0x02, // ZCL command id - GetWeekProfiles 0x00, 0x00, 0x00, 0x00, // Provider ID - unused @@ -2191,7 +2191,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t 0x00, // extended header control field 0x07, 0x07, // extended header cluster id 0x00, 0x0B, // extended gbz command length - 0x01, // frame control + 0x11, // frame control 0x03, // trans. seq number 0x03, // ZCL command id - GetSeasons 0x00, 0x00, 0x00, 0x00, // Provider ID - unused @@ -2201,7 +2201,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t 0x00, // extended header control field 0x07, 0x07, // extended header cluster id 0x00, 0x11, // extended gbz command length - 0x01, // frame control + 0x11, // frame control 0x04, // trans. seq number 0x04, // ZCL command id - GetSpecialDays 0x00, 0x00, 0x00, 0x00, // Start Time @@ -2214,7 +2214,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t 0x01, // extended header control field 0x07, 0x00, // extended header cluster id 0x00, 0x04, // extended gbz command length - 0x01, // frame control + 0x11, // frame control 0x05, // trans. seq number 0x00, // ZCL command id - GetCurrentPrice 0x00, // Active Price @@ -2236,7 +2236,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t 0x00, // extended header control field 0x07, 0x05, // extended header cluster id 0x00, 0x1B, // extended gbz command length - 0x00, // frame control + 0x10, // frame control 0x00, // trans. seq number 0x00, // ZCL command id - ReadAttributes 0x39, 0x02, // Attribute ID - Debt Attribute: DebtRecoveryTopUpPercentage#3 @@ -2256,7 +2256,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t 0x00, // extended header control field 0x07, 0x00, // extended header cluster id 0x00, 0x05, // extended gbz command length - 0x00, // frame control + 0x10, // frame control 0x01, // trans. seq number 0x00, // ZCL command id - ReadAttributes 0x17, 0x06, //Attribute ID - Price Trailing Digits @@ -2265,7 +2265,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t 0x00, // extended header control field 0x07, 0x07, // extended header cluster id 0x00, 0x0D, // extended gbz command length - 0x01, // frame control + 0x11, // frame control 0x02, // trans. seq number 0x01, // ZCL command id - GetDayProfiles 0x00, 0x00, 0x00, 0x00, // Provider ID - unused @@ -2277,7 +2277,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t 0x00, // extended header control field 0x07, 0x07, // extended header cluster id 0x00, 0x0D, // extended gbz command length - 0x01, // frame control + 0x11, // frame control 0x03, // trans. seq number 0x02, // ZCL command id - GetWeekProfiles 0x00, 0x00, 0x00, 0x00, // Provider ID - unused @@ -2289,7 +2289,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t 0x00, // extended header control field 0x07, 0x07, // extended header cluster id 0x00, 0x0B, // extended gbz command length - 0x01, // frame control + 0x11, // frame control 0x04, // trans. seq number 0x03, // ZCL command id - GetSeasons 0x00, 0x00, 0x00, 0x00, // Provider ID - unused @@ -2299,7 +2299,7 @@ void sli_zigbee_af_gas_proxy_function_cli_simulate_gbz_msg(sl_cli_command_arg_t 0x01, // extended header control field 0x07, 0x07, // extended header cluster id 0x00, 0x11, // extended gbz command length - 0x01, // frame control + 0x11, // frame control 0x05, // trans. seq number 0x04, // ZCL command id - GetSpecialDays 0x00, 0x00, 0x00, 0x00, // Start Time diff --git a/protocol/zigbee/app/framework/plugin/green-power-server/green-power-server.c b/protocol/zigbee/app/framework/plugin/green-power-server/green-power-server.c index 46b10a4139..4983645af2 100644 --- a/protocol/zigbee/app/framework/plugin/green-power-server/green-power-server.c +++ b/protocol/zigbee/app/framework/plugin/green-power-server/green-power-server.c @@ -2659,7 +2659,7 @@ bool emberAfGreenPowerClusterGpNotificationCallback(EmberAfClusterCommand *cmd) if (sinkSecLevel > 0) { if (sinkSecLevel > receivedSecLevel || sinkKeyType != receivedKeyType - || entry.gpdSecurityFrameCounter > cmd_data.gpdSecurityFrameCounter) { + || entry.gpdSecurityFrameCounter >= cmd_data.gpdSecurityFrameCounter) { // DROP emberAfGreenPowerClusterPrintln("Gp Notif : DROP - SecLevel, Key type or framecounter mismatch"); return true; diff --git a/protocol/zigbee/app/framework/plugin/on-off/on-off.c b/protocol/zigbee/app/framework/plugin/on-off/on-off.c index bf7da1737e..1a3e19c866 100644 --- a/protocol/zigbee/app/framework/plugin/on-off/on-off.c +++ b/protocol/zigbee/app/framework/plugin/on-off/on-off.c @@ -149,7 +149,7 @@ bool emberAfOnOffClusterOffCallback(void) emberAfPluginZllOnOffServerOffZllExtensions(emberAfCurrentCommand()); } #endif - emberAfSendImmediateDefaultResponse(status); + UNUSED_VAR(status); return true; } @@ -163,7 +163,7 @@ bool emberAfOnOffClusterOnCallback(void) emberAfPluginZllOnOffServerOnZllExtensions(emberAfCurrentCommand()); } #endif - emberAfSendImmediateDefaultResponse(status); + UNUSED_VAR(status); return true; } @@ -177,7 +177,7 @@ bool emberAfOnOffClusterToggleCallback(void) emberAfPluginZllOnOffServerToggleZllExtensions(emberAfCurrentCommand()); } #endif - emberAfSendImmediateDefaultResponse(status); + UNUSED_VAR(status); return true; } diff --git a/protocol/zigbee/app/framework/plugin/reporting/reporting-tokens.h b/protocol/zigbee/app/framework/plugin/reporting/reporting-tokens.h index bd3ae5be95..b1b5203641 100644 --- a/protocol/zigbee/app/framework/plugin/reporting/reporting-tokens.h +++ b/protocol/zigbee/app/framework/plugin/reporting/reporting-tokens.h @@ -16,12 +16,7 @@ ******************************************************************************/ #include "reporting-config.h" -#if (EMBER_AF_PLUGIN_REPORTING_ENABLE_EXPANDED_TABLE == 1) -#define EXPANDED_TABLE -#endif - -#ifdef EXPANDED_TABLE -#else +#if (EMBER_AF_PLUGIN_REPORTING_ENABLE_EXPANDED_TABLE == 0) #define CREATOR_REPORT_TABLE (0x8725) // This key is used for an indexed token and the subsequent 0x7F keys are also reserved #define NVM3KEY_REPORT_TABLE (NVM3KEY_DOMAIN_ZIGBEE | 0x4000) @@ -49,4 +44,4 @@ DEFINE_INDEXED_TOKEN(REPORT_TABLE, EMBER_AF_PLUGIN_REPORTING_UNUSED_ENDPOINT_ID }) #endif //DEFINETOKENS -#endif //EXPANDED_TABLE +#endif //(EMBER_AF_PLUGIN_REPORTING_ENABLE_EXPANDED_TABLE == 0) diff --git a/protocol/zigbee/app/framework/plugin/reporting/reporting.c b/protocol/zigbee/app/framework/plugin/reporting/reporting.c index c015d90a8f..b2a00c4352 100644 --- a/protocol/zigbee/app/framework/plugin/reporting/reporting.c +++ b/protocol/zigbee/app/framework/plugin/reporting/reporting.c @@ -114,7 +114,7 @@ void sli_zigbee_af_reporting_set_entry(uint16_t index, EmberAfPluginReportingEnt { ifValidIndex(MEMMOVE(&table[index], value, sizeof(EmberAfPluginReportingEntry))); } -#elif defined(ENABLE_EXPANDED_TABLE) +#elif defined(ENABLE_EXPANDED_TABLE) // SOC and expanded table is enabled #define reportingTableKey(index) (NVM3KEY_REPORTING_TABLE_EXPANDED + (index)) void sli_zigbee_af_reporting_get_entry(uint16_t index, EmberAfPluginReportingEntry *result) { diff --git a/protocol/zigbee/app/framework/plugin/reporting/reporting.h b/protocol/zigbee/app/framework/plugin/reporting/reporting.h index 3328fce43a..60805fd965 100644 --- a/protocol/zigbee/app/framework/plugin/reporting/reporting.h +++ b/protocol/zigbee/app/framework/plugin/reporting/reporting.h @@ -62,13 +62,12 @@ #define NULL_INDEX 0xFFFF #if defined(ENABLE_EXPANDED_TABLE) +#ifndef EZSP_HOST #include "nvm3.h" - + #define NVM3KEY_REPORTING_TABLE_EXPANDED (NVM3KEY_DOMAIN_ZIGBEE | 0x6000) +#endif //!EZSP_HOST #define REPORTING_TABLE_MAX_RANGE 0x400 #define REPORTING_TABLE_PLUGIN_SIZE (EMBER_AF_PLUGIN_REPORTING_EXPANDED_TABLE_SIZE) - - #define NVM3KEY_REPORTING_TABLE_EXPANDED (NVM3KEY_DOMAIN_ZIGBEE | 0x6000) - #define REPORTING_TABLE_EXPANDED_MAX_KEY (NVM3KEY_REPORTING_TABLE_EXPANDED + REPORTING_TABLE_MAX_RANGE - 1) #else // not expanded #define REPORTING_TABLE_MAX_RANGE 127 #define REPORTING_TABLE_PLUGIN_SIZE (EMBER_AF_PLUGIN_REPORTING_TABLE_SIZE) diff --git a/protocol/zigbee/app/framework/plugin/trust-center-keepalive/trust-center-keepalive.c b/protocol/zigbee/app/framework/plugin/trust-center-keepalive/trust-center-keepalive.c index 81d4277fe7..5f28cd245d 100644 --- a/protocol/zigbee/app/framework/plugin/trust-center-keepalive/trust-center-keepalive.c +++ b/protocol/zigbee/app/framework/plugin/trust-center-keepalive/trust-center-keepalive.c @@ -578,8 +578,19 @@ static void initiateSearchForNewNetworkWithTrustCenter(void) // Activate TC-connectivity based beacon prioritization, we won't deactivate it later param.beaconClassificationMask |= PRIORITIZE_BEACONS_BASED_ON_TC_CONNECTVITY; emberSetBeaconClassificationParams(¶m); + + // Allow the upper layer to update the rejoin mask incase needed in this callback. + // Why do we need this callback - in SE 1.4 CCB 2637 introduced a device type that is slightly + // different Multi-MAC Selection device called as the Multi-MAC Joining device. + // The Joining Device shall not change the interface during rejoin but the selection device can. + // Since this code is in library of the leaf node with the folloiwng callback it would be able + // update mask for rejoining based on the above device types. + uint32_t rejoinChannelMask = EMBER_ALL_802_15_4_CHANNELS_MASK; +#ifdef SL_CATALOG_ZIGBEE_PHY_2_4_SUBGHZ_JOINING_END_DEVICE_PRESENT + emberUpdateMultiMacRejoinChannelMaskForSelectionOrJoiningDevice(&rejoinChannelMask); +#endif //SL_CATALOG_ZIGBEE_PHY_2_4_SUBGHZ_JOINING_END_DEVICE_PRESENT status = emberFindAndRejoinNetworkWithReason(false, // TC (unsecured) rejoin - EMBER_ALL_802_15_4_CHANNELS_MASK, + rejoinChannelMask, EMBER_AF_REJOIN_DUE_TO_TC_KEEPALIVE_FAILURE); } else { emberAfSecurityPrintln("Failed to suspend token writing"); diff --git a/protocol/zigbee/app/framework/scenarios/z3/Z3Gateway/Z3Gateway.slcp b/protocol/zigbee/app/framework/scenarios/z3/Z3Gateway/Z3Gateway.slcp index b9315ff7cf..8fcfb03ee7 100644 --- a/protocol/zigbee/app/framework/scenarios/z3/Z3Gateway/Z3Gateway.slcp +++ b/protocol/zigbee/app/framework/scenarios/z3/Z3Gateway/Z3Gateway.slcp @@ -101,6 +101,22 @@ template_contribution: group: custom name: changeNwkKey handler: changeNwkKeyCommand + condition: + - zigbee_trust_center_nwk_key_update_broadcast + - name: cli_command + value: + group: custom + name: changeNwkKey + handler: changeNwkKeyCommand + condition: + - zigbee_trust_center_nwk_key_update_unicast + - name: cli_command + value: + group: custom + name: changeNwkKey + handler: changeNwkKeyCommand + condition: + - zigbee_test_harness - name: cli_command value: group: custom diff --git a/protocol/zigbee/app/framework/scenarios/z3/Z3Gateway/app.c b/protocol/zigbee/app/framework/scenarios/z3/Z3Gateway/app.c index 01bb83d7dd..e66a1c41cb 100644 --- a/protocol/zigbee/app/framework/scenarios/z3/Z3Gateway/app.c +++ b/protocol/zigbee/app/framework/scenarios/z3/Z3Gateway/app.c @@ -36,7 +36,13 @@ // app/util/ezsp/ezsp-enum.h. #define MFGSAMP_EZSP_TOKEN_MFG_MAXSIZE 92 +#if defined(SL_CATALOG_ZIGBEE_TRUST_CENTER_NWK_KEY_UPDATE_UNICAST_PRESENT) \ + || defined(SL_CATALOG_ZIGBEE_TRUST_CENTER_NWK_KEY_UPDATE_BROADCAST_PRESENT) \ + || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT) extern EmberStatus emberAfTrustCenterStartNetworkKeyUpdate(void); +#endif // defined(SL_CATALOG_ZIGBEE_TRUST_CENTER_NWK_KEY_UPDATE_UNICAST_PRESENT) || +// defined(SL_CATALOG_ZIGBEE_TRUST_CENTER_NWK_KEY_UPDATE_BROADCAST_PRESENT) || +// defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT) //---------------------- // ZCL commands handling @@ -216,6 +222,9 @@ void mfgappTokenDump(sl_cli_command_arg_t *arguments) sl_zigbee_app_debug_println(""); } +#if defined(SL_CATALOG_ZIGBEE_TRUST_CENTER_NWK_KEY_UPDATE_UNICAST_PRESENT) \ + || defined(SL_CATALOG_ZIGBEE_TRUST_CENTER_NWK_KEY_UPDATE_BROADCAST_PRESENT) \ + || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT) void changeNwkKeyCommand(sl_cli_command_arg_t *arguments) { (void)arguments; @@ -228,6 +237,9 @@ void changeNwkKeyCommand(sl_cli_command_arg_t *arguments) sl_zigbee_app_debug_println("Change Key Success"); } } +#endif // defined(SL_CATALOG_ZIGBEE_TRUST_CENTER_NWK_KEY_UPDATE_UNICAST_PRESENT) || +// defined(SL_CATALOG_ZIGBEE_TRUST_CENTER_NWK_KEY_UPDATE_BROADCAST_PRESENT) || +// defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT) static void dcPrintKey(uint8_t label, uint8_t *key) { diff --git a/protocol/zigbee/app/framework/util/process-cluster-message.c b/protocol/zigbee/app/framework/util/process-cluster-message.c index 07b18ee31e..49ff599ecb 100644 --- a/protocol/zigbee/app/framework/util/process-cluster-message.c +++ b/protocol/zigbee/app/framework/util/process-cluster-message.c @@ -75,25 +75,23 @@ bool sli_zigbee_af_process_cluster_specific_command(EmberAfClusterCommand *cmd) cmd->apsFrame->destinationEndpoint, cmd->apsFrame->clusterId, cmd->commandId); - emberAfSendDefaultResponse(cmd, EMBER_ZCL_STATUS_FAILURE); - return true; - } - - if ((cmd->direction == (uint8_t)ZCL_DIRECTION_SERVER_TO_CLIENT - && emberAfContainsClientWithMfgCode(cmd->apsFrame->destinationEndpoint, - cmd->apsFrame->clusterId, - cmd->mfgCode)) - || (cmd->direction == (uint8_t)ZCL_DIRECTION_CLIENT_TO_SERVER - && emberAfContainsServerWithMfgCode(cmd->apsFrame->destinationEndpoint, - cmd->apsFrame->clusterId, - cmd->mfgCode))) { + zcl_status = EMBER_ZCL_STATUS_FAILURE; + } else if ((cmd->direction == (uint8_t)ZCL_DIRECTION_SERVER_TO_CLIENT + && emberAfContainsClientWithMfgCode(cmd->apsFrame->destinationEndpoint, + cmd->apsFrame->clusterId, + cmd->mfgCode)) + || (cmd->direction == (uint8_t)ZCL_DIRECTION_CLIENT_TO_SERVER + && emberAfContainsServerWithMfgCode(cmd->apsFrame->destinationEndpoint, + cmd->apsFrame->clusterId, + cmd->mfgCode))) { zcl_status = emberAfClusterSpecificCommandParse(cmd); + } else { + // Do nothing. } - - if (zcl_status != EMBER_ZCL_STATUS_SUCCESS) { - emberAfSendDefaultResponse(cmd, zcl_status); - } - + // Call emberAfSendDefaultResponse, in which, it would check for other + // conditions including Disable Default Response bit of ZCL FC of the + // incoming command. + emberAfSendDefaultResponse(cmd, zcl_status); return true; } diff --git a/protocol/zigbee/app/ncp/sample-app/ncp-spi/app.c b/protocol/zigbee/app/ncp/sample-app/ncp-spi/app.c index 37dbad6386..0c68c662a9 100644 --- a/protocol/zigbee/app/ncp/sample-app/ncp-spi/app.c +++ b/protocol/zigbee/app/ncp/sample-app/ncp-spi/app.c @@ -18,11 +18,6 @@ #include PLATFORM_HEADER #include "ember.h" -#ifdef SL_CATALOG_LEGACY_NCP_SPI_PRESENT -#include "em_gpio.h" -#include "spi-protocol-device.h" -#endif // SL_CATALOG_LEGACY_NCP_SPI_PRESENT - /** @brief * * Application framework equivalent of ::emberRadioNeedsCalibratingHandler @@ -31,19 +26,3 @@ void emberAfRadioNeedsCalibratingCallback(void) { sl_mac_calibrate_current_channel(); } - -void emberAfMainInitCallback(void) -{ -#if (((SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION == 0) \ - || (SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION == 0)) \ - && !defined(EMBER_TEST)) - if ((strcmp(SL_BOARD_NAME, "BRD4186C") == 0) \ - || (strcmp(SL_BOARD_NAME, "BRD4187C") == 0) \ - || (strcmp(SL_BOARD_NAME, "BRD4188B") == 0)) { - GPIO_IntDisable(1 << BSP_SPINCP_NWAKE_PIN); - GPIO_EM4WUExtIntConfig(BSP_SPINCP_NWAKE_PORT, BSP_SPINCP_NWAKE_PIN, 9, false, true); - } -#endif // (((SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION == 0) || - // (SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION == 0)) && - // !defined(EMBER_TEST)) -} diff --git a/protocol/zigbee/build/gcc/arm32v7/zigbee-dynamic-commissioning/release/libzigbee-dynamic-commissioning.a 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a/protocol/zigbee/build/iar/cortex-m4/zigbee-zll/release_singlenetwork/libzigbee-zll.a b/protocol/zigbee/build/iar/cortex-m4/zigbee-zll/release_singlenetwork/libzigbee-zll.a index 547a22fb51..7c707fac0b 100644 --- a/protocol/zigbee/build/iar/cortex-m4/zigbee-zll/release_singlenetwork/libzigbee-zll.a +++ b/protocol/zigbee/build/iar/cortex-m4/zigbee-zll/release_singlenetwork/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7b668d5d8ad907c6a7653e37a190f9d63299204d95df30a34af7983ab5428eb0 +oid sha256:f85ca3ff3b7e36f9af2e8abd81c592e3b0887af287310640ce609e571cf0c936 size 104004 diff --git a/protocol/zigbee/build/iar/cortex-m4/zigbee-zll/release_stackprotection/libzigbee-zll.a b/protocol/zigbee/build/iar/cortex-m4/zigbee-zll/release_stackprotection/libzigbee-zll.a index 65160bb180..6ca9492267 100644 --- a/protocol/zigbee/build/iar/cortex-m4/zigbee-zll/release_stackprotection/libzigbee-zll.a +++ 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a/protocol/zigbee/build/iar/cortex-m4/zigbee-zll/release_stackprotection_railgb_singlenetwork/libzigbee-zll.a b/protocol/zigbee/build/iar/cortex-m4/zigbee-zll/release_stackprotection_railgb_singlenetwork/libzigbee-zll.a index 4890871005..d03b3340d0 100644 --- a/protocol/zigbee/build/iar/cortex-m4/zigbee-zll/release_stackprotection_railgb_singlenetwork/libzigbee-zll.a +++ b/protocol/zigbee/build/iar/cortex-m4/zigbee-zll/release_stackprotection_railgb_singlenetwork/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f03f7862253d5cb93f59f74ae7b2733b5029b14e53b48a460743fcd644092cdf +oid sha256:4c374a702f7dc327ba541cc4d345405ca58d8d501178c6a555029c9d998dadb1 size 115714 diff --git a/protocol/zigbee/build/iar/cortex-m4/zigbee-zll/release_stackprotection_singlenetwork/libzigbee-zll.a b/protocol/zigbee/build/iar/cortex-m4/zigbee-zll/release_stackprotection_singlenetwork/libzigbee-zll.a index 6f2314486f..d70e83142e 100644 --- a/protocol/zigbee/build/iar/cortex-m4/zigbee-zll/release_stackprotection_singlenetwork/libzigbee-zll.a +++ b/protocol/zigbee/build/iar/cortex-m4/zigbee-zll/release_stackprotection_singlenetwork/libzigbee-zll.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:89284ed2420ed49e5e55c98bc3f2a4a8d939835f2f9b823791ad576400332f37 +oid sha256:3780692dc35c80bb7759113525f862b56fd468cbb14e9a07915713a6c7620de8 size 110642 diff --git a/protocol/zigbee/component/zigbee_ncp_cpc.slcc b/protocol/zigbee/component/zigbee_ncp_cpc.slcc index 59b5e65239..9bbc73f094 100644 --- a/protocol/zigbee/component/zigbee_ncp_cpc.slcc +++ b/protocol/zigbee/component/zigbee_ncp_cpc.slcc @@ -7,8 +7,6 @@ description: This component provides Co-Processor Communication (CPC) support fo provides: - name: zigbee_ncp_cpc - name: zigbee_ncp - # OPENTHREAD-2545: Temporary workaround to disable coex - - name: ot_coex requires: - name: cpc_secondary diff --git a/protocol/zigbee/component/zigbee_pro_leaf_stack_mac_test_cmds.slcc b/protocol/zigbee/component/zigbee_pro_leaf_stack_mac_test_cmds.slcc index 1ee41dc99a..c4973f11d9 100644 --- a/protocol/zigbee/component/zigbee_pro_leaf_stack_mac_test_cmds.slcc +++ b/protocol/zigbee/component/zigbee_pro_leaf_stack_mac_test_cmds.slcc @@ -1,5 +1,5 @@ id: zigbee_pro_leaf_stack_mac_test_cmds -label: Pro Leaf Stack +label: Pro Leaf Stack with Mac test commands package: Zigbee category: Zigbee|Stack|Pro Core quality: production diff --git a/protocol/zigbee/docs/release-highlights.txt b/protocol/zigbee/docs/release-highlights.txt index 39952ecf33..45fb9bda26 100755 --- a/protocol/zigbee/docs/release-highlights.txt +++ b/protocol/zigbee/docs/release-highlights.txt @@ -1,5 +1,5 @@ -Zigbee EmberZNet SDK 7.4.1.0 +Zigbee EmberZNet SDK 7.4.2.0 Zigbee: - Targeted quality improvements and bug fixes. -Multi-Protocol -- Targeted quality improvements and bug fixes \ No newline at end of file +Multiprotocol +- Targeted quality improvements and bug fixes. \ No newline at end of file diff --git a/protocol/zigbee/documentation/slEmberZNet_docContent.xml b/protocol/zigbee/documentation/slEmberZNet_docContent.xml index 2d46a5cc6e..777d979db4 100644 --- a/protocol/zigbee/documentation/slEmberZNet_docContent.xml +++ b/protocol/zigbee/documentation/slEmberZNet_docContent.xml @@ -1,6 +1,6 @@ - + Describes the impact of Wi-Fi on Zigbee and Thread, and methods to improve coexistence. First, methods to improve coexistence without direct interaction between Zigbee/Thread and Wi-Fi radios are described. Second, Silicon Labs's Packet Traffic Arbitration (PTA) support to coordinate 2.5 GHz RF traffic for co-located Zigbee/Thread and Wi-Fi radios is described (for the EFR32MG only). @@ -8,35 +8,35 @@ - + Includes detailed information on using the Silicon Labs Gecko Bootloader with EmberZNet. It supplements the general Gecko Bootloader implementation information provided in UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher. - + Explains how to use Simplicity Commander to check, write, verify, and erase installation codes on Silicon Labs Wireless Gecko (EFR32) devices. - + Includes guidelines for certifying Zigbee 3.0 devices, instructions on setting up and using the Zigbee test harness and Zigbee test tool, and troubleshooting tips. - + Contains three complete PICS documents for Z3ColorControlLight, Z3Gateway and Z3SmartOutlet reference designs, along with XML files for Z3ColorControlLight clusters. - + Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. @@ -44,14 +44,14 @@ - + Details methods for testing Zigbee mesh network performance; results are intended to provide guidance on design practices and principles as well as expected field performance results. - + Reviews the Zigbee, Thread, and Bluetooth mesh networks to evaluate their differences in performance and behavior. @@ -59,7 +59,7 @@ - + Describes tokens and shows how to use them for non-volatile data storage in EmberZNet PRO and Silicon Labs Flex applications. @@ -67,14 +67,14 @@ - + Describes how to use the manufacturing library and its associated plugins in Simplicity Studio to perform RF tests during the manufacturing phase. - + Describes how to lock and unlock the debug access of EFR32 Gecko Series 2 devices. Many aspects of the debug access, including the secure debug unlock are described. The Debug Challenge Interface (DCI) and Secure Engine (SE) Mailbox Interface for locking and unlocking debug access are also included. @@ -82,7 +82,7 @@ - + Contains detailed information on configuring and using the Secure Boot with hardware Root of Trust and Secure Loader on Series 2 devices, including how to provision the signing key. This is a companion document to UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher. @@ -90,7 +90,7 @@ - + Details on programming, provisioning, and configuring Series 2 devices in production environments. Covers Secure Engine Subsystem of Series 2 devices, which runs easily upgradeable Secure Engine (SE) or Virtual Secure Engine (VSE) firmware. @@ -98,14 +98,14 @@ - + Introduces some basic security concepts, including network layer security, trust centers, and application support layer security features. It then discusses the types of standard security protocols available in EmberZNet PRO. Coding requirements for implementing security are reviewed in summary. Finally, information on implementing Zigbee Smart Energy security is provided. - + How to program, provision, and configure the anti-tamper module on EFR32 Series 2 devices with Secure Vault. @@ -113,7 +113,7 @@ - + How to authenticate an EFR32 Series 2 device with Secure Vault, using secure device certificates and signatures. @@ -121,7 +121,7 @@ - + How to securely "wrap" keys in EFR32 Series 2 devices with Secure Vault, so they can be stored in non-volatile storage. @@ -129,7 +129,7 @@ - + Summarizes the differences between Zigbee EmberZNet 7.x in GSDK 4.x and earlier AppBuilder-based versions. @@ -137,7 +137,7 @@ - + Describes how to provision and configure Series 2 devices through the DCI and SWD. @@ -145,7 +145,7 @@ - + Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. @@ -153,35 +153,35 @@ - + Provides instructions for configuring various aspects of a component-based NCP application using Zigbee EmberZNet SDK 7.0 and higher with the tools included in Simplicity Studio 5. - + Describes how to configure peripherals running firmware produced with Zigbee 7.0 and higher using Simplicity Studio's Pin Tool and Project Configurator. - + Provides details on developing Dynamic Multiprotocol applications using Bluetooth and Zigbee EmberZNet SDK 7.0 and higher. - + Describes how to use Project Configurator to configure both receive and transmit Antenna Diversity in Zigbee EmberZNet applications. - + Describes how to use ZAP, an advanced configuration tool within Simplicity Studio that allows the developer to manage Zigbee endpoints, clusters and commands implemented by their device. ZAP, which is also used in Matter configuration, is known as the Zigbee Cluster Configurator (ZCL) in the Zigbee context. @@ -189,7 +189,7 @@ - + Describes how to run any combination of Zigbee EmberZNet, OpenThread, and Bluetooth networking stacks on a Linux host processor, interfacing with a single EFR32 radio co-processor (RCP) with multiprotocol and multi-PAN support, as well as how to run the Zigbee stack on the EFR32 as a network co-processor (NCP) alongside the OpenThread RCP. @@ -197,7 +197,7 @@ - + Documents the steps needed to properly configure and run the CPC daemon (CPCd) on Linux or Android. @@ -205,7 +205,7 @@ - + Covers the basics of ARMv8-M TrustZone, describes how TrustZone is implemented on Series 2 devices, and provides application examples. @@ -213,14 +213,14 @@ - + Describes how to perform a Zigbee over-the-air (OTA) bootloading session between a ZCL OTA Upgrade cluster client device and server device. The instructions are for EFR32MG12 development kits. Users can also refer to this procedure when setting up or testing Zigbee OTA bootload cluster download in their own development environments with their own hardware. - + Summarizes the results of simultaneous Thread and Zigbee throughput performance testing for the concurrent multiprotocol / multi-PAN RCP, running both OpenThread and Zigbee on the host processor. @@ -228,21 +228,21 @@ - + Describes how to use the backup and restore feature in a Z3GatewayGPCombo scenario application. - + Zigbee EmberZNet 7.0 and higher no longer supports compiling host applications in MinGW for Windows. This document offers an alternative solution by using a Docker container to run the NCP Host Application. - + Describes how to run a combination of Zigbee, Bluetooth, and OpenThread networking stacks and the Zigbee application layer on a System-on-Chip (SoC). @@ -250,7 +250,7 @@ - + Details the different options for integrating RF testing and characterization into standard test flows for the EFR32. @@ -258,35 +258,35 @@ - + Describes procedures for initial tests of a host connected to a Zigbee processor using EZSP-UART. It assumes that you have already read UG101, the UART Gateway Protocol Reference Guide. You should have a basic understanding of the UART Gateway protocol, as well as the signals needed by the UART interface. - + Details the EZSP-SPI Protocol used by a host microcontroller to communicate with an Ember network co-processor (NCP) running the EmberZNet PRO stack. It includes recommended procedures for developing and testing a driver for the EZSP-SPI Protocol on a new host microcontroller. - + Describes how to set up a device with the security resources required to support Smart Energy (SE) security, which is based on certificate-based key establishment (CBKE) using Elliptic-Curve Cryptography (ECC). You should be familiar the Zigbee Smart Energy Profile specification. - + Provides instructions for creating Zigbee Over-the-air (OTA) bootloader files with Image Builder, which takes an existing file (or multiple files) and wraps them in the file format as declared in the Zigbee specification. - + Provides a high-level description of the different options for integrating RF testing and characterization into your standard test flows. It is intended for customers who are moving from the early prototype development stage to the manufacturing production environment and need assistance with manufacturing test. @@ -294,14 +294,14 @@ - + Describes the multi-network stack feature that allows a single-radio chip to be concurrently part of more than one distinct network. Some limitations and restrictions are enforced by the multi-network stack and should be taken into account during the design of a multi-network application. These limitations are mostly related to the role the node assumes on the networks and are discussed here in detail. - + Describes how to initialize a piece of custom hardware (a 'device') based on the EFR32MG and EFR32FG families so that it interfaces correctly with a network stack. The same procedures can be used to restore devices whose settings have been corrupted or erased. @@ -309,49 +309,49 @@ - + Provides an overview and hyperlinks to all packaged documentation. - + Provides basic information on configuring, building, and installing applications for the EFR32MG family of SoCs using the Zigbee EmberZNet Software Development Kit (SDK) v7.0 and higher with Simplicity Studio 5. - + Lists SoC Platform APIs used to interface to the EmberZNet PRO stack, HAL, and status of the application-controlled network. These APIs concern network management, device and stack management, messaging, fragmentation, serial communication, token access, peripheral access, bootload utilities, and others. They are independent of the Application Framework and therefore can be used to develop applications that do not rely on the Zigbee Cluster Library. - + Describes Zigbee Application Framework APIs, the CLI interface, and callbacks. - + A companion to the EmberZNet API references, for developers whose applications require functionality not available through Project Configurator and the application framework, or who prefer working with an API. Includes an introduction to the stack API, a discussion of advanced design issues to consider when developing an application using the API, and provides an example application. - + The Zigbee Application Framework is a body of embedded C code that can be configured by project configuration tools to implement any Zigbee Cluster Library (ZCL) application. This guide covers the structure and usage of the Zigbee Application Framework in SDK 7.0 and higher. - + Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. @@ -359,7 +359,7 @@ - + A detailed overview of all the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform consists of: EMLIB, EMDRV, RAIL Library, NVM3, and the mbedTLS Plugin. @@ -367,28 +367,28 @@ - + Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the Zigbee 7.x stack (and associated utilities) including added/deleted/deprecated features/API, and lists bugs that have been fixed since the last release and any pending ones. - + Describes the EmberZNet Serial Protocol (EZSP), used by a host application processor to interact with the EmberZNet PRO stack running on an NCP over either a SPI or a UART interface. Describes the frame formats for different EZSP-bound stack activities such as network management, messaging, bootloading, and token access. - + Describes the protocol used by EZSP-UART to reliably carry commands and responses between a host processor and a network co-processor. The topics discussed include a brief overview of Ember-designed ASH (Asynchronus Serial Host) protocol, general ASH frame format, different ASH frames, and their operation. - + Introduces some fundamental concepts of wireless networking. These concepts are referred to in other Fundamentals documents. If you are new to wireless networking, read this document first. @@ -396,21 +396,21 @@ - + Describes the key features and characteristics of a Zigbee solution. It also includes a section on Zigbee 3.0. - + Discusses the major decisions that must be made about which wireless protocol you should use, as well as additional decisions to be made if you are designing a Zigbee solution. - + Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. @@ -418,7 +418,7 @@ - + Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader and describes the file formats used by each. @@ -426,7 +426,7 @@ - + Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: Simulated EEPROM, PS Store, and NVM3. @@ -434,21 +434,21 @@ - + Compares the ZLL stack and network with the EmberZNet PRO stack and network, with notes about considerations when implementing a ZLL solution. Includes a basic description of ZLL configuration and commissioning, and notes about the interoperability of ZLL and non-ZLL devices. - + Describes the main features and functions of Zigbee Green Power (ZGP) and a basic ZGP network, including its device types and commissioning process, and how EmberZNet supports the ZGP device types. - + Describes the four multiprotocol modes, discusses considerations when selecting protocols for multiprotocol implementations, and reviews the Radio Scheduler, a required component of a dynamic multiprotocol solution. @@ -456,7 +456,7 @@ - + Describes methods to improve the coexistence of 2.4 GHz IEEE 802.11b/g/n Wi-Fi and other 2.4 GHz radios such as Bluetooth, Bluetooth Mesh, Bluetooth Low Energy, and IEEE 802.15.4-based radios such as Zigbee and OpenThread @@ -464,14 +464,14 @@ - + Describes strategies for testing and debugging applications, including: hardware and application considerations, initial development testing, and lab testing. For additional information about later stages of programming and testing see application notes AN700.1: Manufacturing Test Guidelines and AN718: Manufacturing Test Overview. - + Describes how and when to use Simplicity Commander's Command-Line Interface with EFR32 parts. @@ -479,7 +479,7 @@ - + Describes how to implement a dynamic multiprotocol solution. @@ -487,14 +487,14 @@ - + Introduces Silicon Labs Green Power components within the EmberZNet PRO stack and explains how to enable your network for Green Power. - + Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. diff --git a/protocol/zigbee/esf.properties b/protocol/zigbee/esf.properties index 51ffb79aa2..4c6a578fb5 100644 --- a/protocol/zigbee/esf.properties +++ b/protocol/zigbee/esf.properties @@ -3,16 +3,16 @@ # # This files lists Studio SDK properties pertaining to the ZigBee stack. # -# The version=7.4.1.0 +# The version=7.4.2.0 # release branch, or it should be set to 0.0.0 otherwise. This is the # version that Studio displays for the loaded stack. # id=com.silabs.sdk.stack.znet -version=7.4.1.0 +version=7.4.2.0 label=EmberZNet SDK description=Silicon Labs EmberZNet SDK -prop.subLabel=EmberZNet\\ 7.4.1.0 +prop.subLabel=EmberZNet\\ 7.4.2.0 prop.partCompatibility=.*host.* .*efr32mg(12|13)p.* .*efr32mg2[1247].* .*mgm(12|13|21|22|24).* .*rm21.* diff --git a/protocol/zigbee/stack/config/config.h b/protocol/zigbee/stack/config/config.h index 78eb08f370..597d9c5161 100644 --- a/protocol/zigbee/stack/config/config.h +++ b/protocol/zigbee/stack/config/config.h @@ -33,7 +33,7 @@ // The 4 digit version: A.B.C.D #define EMBER_MAJOR_VERSION 7 #define EMBER_MINOR_VERSION 4 -#define EMBER_PATCH_VERSION 1 +#define EMBER_PATCH_VERSION 2 #define EMBER_SPECIAL_VERSION 0 // 2 bytes diff --git a/protocol/zigbee/stack/gp/gp-token-config.h b/protocol/zigbee/stack/gp/gp-token-config.h index ca310ab69f..2ecbdc12b3 100644 --- a/protocol/zigbee/stack/gp/gp-token-config.h +++ b/protocol/zigbee/stack/gp/gp-token-config.h @@ -108,7 +108,7 @@ DEFINE_INDEXED_TOKEN(STACK_GP_PROXY_TABLE, DEFINE_INDEXED_TOKEN(STACK_GP_INCOMING_FC, tokTypeGPDIncomingFC, EMBER_GP_INCOMING_FC_TOKEN_TABLE_SIZE, - { 0xFFFFFFFFU }) + { 0x00000000U }) // Sink Table and Sink table incoming FC tokens @@ -140,5 +140,5 @@ DEFINE_INDEXED_TOKEN(STACK_GP_SINK_TABLE, DEFINE_INDEXED_TOKEN(STACK_GP_INCOMING_FC_IN_SINK, tokTypeGPDIncomingFCInSink, EMBER_GP_SINK_TABLE_SIZE, - { 0xFFFFFFFFU }) + { 0x00000000U }) #endif diff --git a/protocol/zigbee/tool/image-builder/image-builder-linux b/protocol/zigbee/tool/image-builder/image-builder-linux index f5b00d1f40..5019ccc2d4 100755 Binary files a/protocol/zigbee/tool/image-builder/image-builder-linux and b/protocol/zigbee/tool/image-builder/image-builder-linux differ diff --git a/protocol/zigbee/tool/image-builder/image-builder-windows.exe b/protocol/zigbee/tool/image-builder/image-builder-windows.exe index ba069ea500..6419dc78e0 100755 --- a/protocol/zigbee/tool/image-builder/image-builder-windows.exe +++ b/protocol/zigbee/tool/image-builder/image-builder-windows.exe @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f8555e88b41ad67c2de8adf7605914fec6fdd5cd2612cde8b4730c56bae8d5ee +oid sha256:d8cbc2ae0fd2a5205cf516493faed6b6bf602af8b969a66a228ab954bd31da57 size 3014347 diff --git a/protocol/zigbee/zigbee_production_demos.xml b/protocol/zigbee/zigbee_production_demos.xml index 8d36186a1c..613a59cfb9 100644 --- a/protocol/zigbee/zigbee_production_demos.xml +++ b/protocol/zigbee/zigbee_production_demos.xml @@ -5,7 +5,7 @@ - + @@ -15,7 +15,7 @@ - + @@ -25,7 +25,7 @@ - + @@ -35,7 +35,7 @@ - + @@ -45,7 +45,7 @@ - + @@ -55,7 +55,7 @@ - + @@ -65,7 +65,7 @@ - + @@ -75,7 +75,7 @@ - + @@ -85,7 +85,7 @@ - + @@ -95,7 +95,7 @@ - + @@ -105,7 +105,7 @@ - + @@ -115,7 +115,7 @@ - + @@ -125,7 +125,7 @@ - + @@ -135,7 +135,7 @@ - + @@ -145,7 +145,7 @@ - + @@ -155,7 +155,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -175,7 +175,7 @@ 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a/util/third_party/cmsis/lib/gcc/cortex-m3/libCMSISDSP.a +++ b/util/third_party/cmsis/lib/gcc/cortex-m3/libCMSISDSP.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c0e6f9c2479b0de84978ef6d5c70b7f5244aabbacf4fd0e560d027557b2fbf45 +oid sha256:d34470f7c335403ba4395b66483017f9b2ac4481dc172ab75cd641c96ea2d608 size 2069520 diff --git a/util/third_party/cmsis/lib/gcc/cortex-m3/libcmsis-nn.a b/util/third_party/cmsis/lib/gcc/cortex-m3/libcmsis-nn.a index 5eaa195135..80a2cbc57b 100644 --- a/util/third_party/cmsis/lib/gcc/cortex-m3/libcmsis-nn.a +++ b/util/third_party/cmsis/lib/gcc/cortex-m3/libcmsis-nn.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:aa506b2502150642f3424c1ada27f110ddea40056f988087374a048e0a405b25 +oid sha256:414e9071ef4501cdebd65232e12504ca24b132f311e4002ee34f3f62dcf5c8a8 size 108636 diff --git a/util/third_party/cmsis/lib/gcc/cortex-m33/libCMSISDSP.a b/util/third_party/cmsis/lib/gcc/cortex-m33/libCMSISDSP.a index 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a/util/third_party/cmsis/lib/iar/cortex-m33/libCMSISDSP.a b/util/third_party/cmsis/lib/iar/cortex-m33/libCMSISDSP.a index aa13fed649..83c8eeb4a7 100644 --- a/util/third_party/cmsis/lib/iar/cortex-m33/libCMSISDSP.a +++ b/util/third_party/cmsis/lib/iar/cortex-m33/libCMSISDSP.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e3d8e3a188319437625c30baffebb42f8657dd348bcd051f0de397d0921a6b21 +oid sha256:29b61ba989f86d57271241654bb65e0e3f40fb6a8202ddca76fb3c814c5f7ac2 size 2705194 diff --git a/util/third_party/cmsis/lib/iar/cortex-m33/libcmsis-nn.a b/util/third_party/cmsis/lib/iar/cortex-m33/libcmsis-nn.a index 32001598a4..3770e7673f 100644 --- a/util/third_party/cmsis/lib/iar/cortex-m33/libcmsis-nn.a +++ b/util/third_party/cmsis/lib/iar/cortex-m33/libcmsis-nn.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3937777e49e25d76f50f114277861b1131dc8149ce13b411eaf50966afed751c +oid sha256:a88ca89e2e1bdc199a240ec811983900af3cba173062a905d1dc6feefeb0ad50 size 259764 diff --git a/util/third_party/mbedtls/library/psa_crypto_driver_wrappers.h b/util/third_party/mbedtls/library/psa_crypto_driver_wrappers.h index 18715fd666..27b538c8c7 100644 --- a/util/third_party/mbedtls/library/psa_crypto_driver_wrappers.h +++ b/util/third_party/mbedtls/library/psa_crypto_driver_wrappers.h @@ -273,6 +273,20 @@ static inline psa_status_t psa_driver_wrapper_sign_message( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif +#if defined(SLI_ECDSA_DEVICE_SI91X) + status = sli_si91x_crypto_sign_message( attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_size, + signature_length); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ break; @@ -308,6 +322,21 @@ static inline psa_status_t psa_driver_wrapper_sign_message( /* No fallback for opaque */ return( status ); #endif +#if defined(SLI_ECDSA_DEVICE_SI91X) +#if defined(SLI_SECURE_KEY_STORAGE_DEVICE_SI91X) + case PSA_KEY_VOLATILE_PERSISTENT_WRAPPED: + status = sli_si91x_crypto_sign_message( attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_size, + signature_length); + return status; +#endif +#endif /* SLI_ECDSA_DEVICE_SI91X */ #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ default: /* Key is declared with a lifetime not known to us */ @@ -373,6 +402,19 @@ static inline psa_status_t psa_driver_wrapper_verify_message( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif +#if defined(SLI_ECDSA_DEVICE_SI91X) + status = sli_si91x_crypto_verify_message( attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_length); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ break; @@ -403,7 +445,22 @@ static inline psa_status_t psa_driver_wrapper_verify_message( /* No fallback for opaque */ return( status ); #endif +#if defined(SLI_ECDSA_DEVICE_SI91X) +#if defined(SLI_SECURE_KEY_STORAGE_DEVICE_SI91X) + case PSA_KEY_VOLATILE_PERSISTENT_WRAPPED: + status = sli_si91x_crypto_verify_message( attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_length); + return status; +#endif +#endif /* SLI_ECDSA_DEVICE_SI91X */ #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: /* Key is declared with a lifetime not known to us */ (void)status; diff --git a/util/third_party/openthread/src/lib/spinel/radio_spinel.cpp b/util/third_party/openthread/src/lib/spinel/radio_spinel.cpp index 4307a65459..d89958c200 100644 --- a/util/third_party/openthread/src/lib/spinel/radio_spinel.cpp +++ b/util/third_party/openthread/src/lib/spinel/radio_spinel.cpp @@ -1731,9 +1731,12 @@ void RadioSpinel::HandleTransmitDone(uint32_t aCommand, } exit: - // A parse error indicates an RCP misbehavior, so recover the RCP immediately. + // Recover the RCP immediately if the error is not one of the expected transmit done errors. mState = kStateTransmitDone; - if (error != OT_ERROR_PARSE) + if (error == OT_ERROR_NONE || + error == OT_ERROR_ABORT || + error == OT_ERROR_NO_ACK || + error == OT_ERROR_CHANNEL_ACCESS_FAILURE) { mTxError = error; } diff --git a/util/third_party/openthread/src/ncp/ncp_base.cpp b/util/third_party/openthread/src/ncp/ncp_base.cpp index 71b70702e1..aa5dcce304 100644 --- a/util/third_party/openthread/src/ncp/ncp_base.cpp +++ b/util/third_party/openthread/src/ncp/ncp_base.cpp @@ -898,7 +898,7 @@ otError NcpBase::HandlePendingTransmit(PendingCommandEntry *aEntry) *frame = aEntry->mTransmitFrame; VerifyOrExit(frame->mLength <= OT_RADIO_FRAME_MAX_SIZE, error = OT_ERROR_PARSE); frame->mPsdu = savePsdu; - memcpy(frame->mPsdu, &aEntry->mTransmitFrame.mPsdu, frame->mLength); + memcpy(frame->mPsdu, aEntry->mTransmitFrame.mPsdu, frame->mLength); frame->mIid = aEntry->mIid; SuccessOrExit(error = otLinkRawTransmit(mInstance, &NcpBase::LinkRawTransmitDone)); diff --git a/util/third_party/tensorflow_extra/component/tensorflow_lite_micro.slcc b/util/third_party/tensorflow_extra/component/tensorflow_lite_micro.slcc index a43d64596f..11ad60f6ac 100644 --- a/util/third_party/tensorflow_extra/component/tensorflow_lite_micro.slcc +++ b/util/third_party/tensorflow_extra/component/tensorflow_lite_micro.slcc @@ -237,8 +237,8 @@ template_contribution: - name: component_catalog value: tflite_micro documentation: - docset: gecko-platform - document: machine-learning/tensorflow/overview + docset: machine-learning + document: machine-learning-tensorflow-lite-for-microcontrollers define: - name: TF_LITE_STATIC_MEMORY library: diff --git a/util/third_party/tensorflow_extra/lib/gcc/cortex-m0plus/libtflm.a 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